stats.txt revision 11353:31c5786945b4
19242SN/A 29242SN/A---------- Begin Simulation Statistics ---------- 39242SN/Asim_seconds 47.256536 # Number of seconds simulated 49242SN/Asim_ticks 47256535705500 # Number of ticks simulated 59242SN/Afinal_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 69242SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711530Sandreas.sandberg@arm.comhost_inst_rate 1671940 # Simulator instruction rate (inst/s) 811530Sandreas.sandberg@arm.comhost_op_rate 1966949 # Simulator op (including micro ops) rate (op/s) 911530Sandreas.sandberg@arm.comhost_tick_rate 80984002716 # Simulator tick rate (ticks/s) 1010036SAli.Saidi@ARM.comhost_mem_usage 693668 # Number of bytes of host memory used 1110036SAli.Saidi@ARM.comhost_seconds 583.53 # Real time elapsed on the host 1211530Sandreas.sandberg@arm.comsim_insts 975625723 # Number of instructions simulated 139242SN/Asim_ops 1147772483 # Number of ops (including micro ops) simulated 149242SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510616Sandreas.hansson@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610616Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory 179242SN/Asystem.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory 189242SN/Asystem.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory 1910616Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory 2010616Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 217792 # Number of bytes read from this memory 219242SN/Asystem.physmem.bytes_read::cpu1.itb.walker 214080 # Number of bytes read from this memory 229242SN/Asystem.physmem.bytes_read::cpu1.inst 2613000 # Number of bytes read from this memory 2310616Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 38038064 # Number of bytes read from this memory 2410616Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 430464 # Number of bytes read from this memory 2510616Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 81291956 # Number of bytes read from this memory 2610616Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3883124 # Number of instructions bytes read from this memory 2711530Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2613000 # Number of instructions bytes read from this memory 2811530Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 6496124 # Number of instructions bytes read from this memory 2910616Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 101151552 # Number of bytes written to this memory 3010616Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3110616Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3211530Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 101172136 # Number of bytes written to this memory 339729SN/Asystem.physmem.num_reads::cpu0.dtb.walker 2451 # Number of read requests responded to by this memory 349729SN/Asystem.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory 3510616Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 101081 # Number of read requests responded to by this memory 3610616Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 556375 # Number of read requests responded to by this memory 3710616Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3403 # Number of read requests responded to by this memory 3810616Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3345 # Number of read requests responded to by this memory 3910616Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 40935 # Number of read requests responded to by this memory 4010616Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 594361 # Number of read requests responded to by this memory 4110616Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6726 # Number of read requests responded to by this memory 4210616Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1310730 # Number of read requests responded to by this memory 4310616Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1580493 # Number of write requests responded to by this memory 4410616Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4511530Sandreas.sandberg@arm.comsystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 469242SN/Asystem.physmem.num_writes::total 1583067 # Number of write requests responded to by this memory 479242SN/Asystem.physmem.bw_read::cpu0.dtb.walker 3319 # Total read bandwidth from this memory (bytes/s) 489242SN/Asystem.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s) 499242SN/Asystem.physmem.bw_read::cpu0.inst 82171 # Total read bandwidth from this memory (bytes/s) 509242SN/Asystem.physmem.bw_read::cpu0.data 753487 # Total read bandwidth from this memory (bytes/s) 519242SN/Asystem.physmem.bw_read::cpu1.dtb.walker 4609 # Total read bandwidth from this memory (bytes/s) 529242SN/Asystem.physmem.bw_read::cpu1.itb.walker 4530 # Total read bandwidth from this memory (bytes/s) 539242SN/Asystem.physmem.bw_read::cpu1.inst 55294 # Total read bandwidth from this memory (bytes/s) 549242SN/Asystem.physmem.bw_read::cpu1.data 804927 # Total read bandwidth from this memory (bytes/s) 559242SN/Asystem.physmem.bw_read::realview.ide 9109 # Total read bandwidth from this memory (bytes/s) 569242SN/Asystem.physmem.bw_read::total 1720227 # Total read bandwidth from this memory (bytes/s) 579242SN/Asystem.physmem.bw_inst_read::cpu0.inst 82171 # Instruction read bandwidth from this memory (bytes/s) 589242SN/Asystem.physmem.bw_inst_read::cpu1.inst 55294 # Instruction read bandwidth from this memory (bytes/s) 599242SN/Asystem.physmem.bw_inst_read::total 137465 # Instruction read bandwidth from this memory (bytes/s) 609242SN/Asystem.physmem.bw_write::writebacks 2140478 # Write bandwidth from this memory (bytes/s) 619242SN/Asystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 629242SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 639242SN/Asystem.physmem.bw_write::total 2140913 # Write bandwidth from this memory (bytes/s) 649242SN/Asystem.physmem.bw_total::writebacks 2140478 # Total bandwidth to/from this memory (bytes/s) 659242SN/Asystem.physmem.bw_total::cpu0.dtb.walker 3319 # Total bandwidth to/from this memory (bytes/s) 669242SN/Asystem.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s) 679242SN/Asystem.physmem.bw_total::cpu0.inst 82171 # Total bandwidth to/from this memory (bytes/s) 689242SN/Asystem.physmem.bw_total::cpu0.data 753922 # Total bandwidth to/from this memory (bytes/s) 699242SN/Asystem.physmem.bw_total::cpu1.dtb.walker 4609 # Total bandwidth to/from this memory (bytes/s) 709242SN/Asystem.physmem.bw_total::cpu1.itb.walker 4530 # Total bandwidth to/from this memory (bytes/s) 7110616Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 55294 # Total bandwidth to/from this memory (bytes/s) 729242SN/Asystem.physmem.bw_total::cpu1.data 804927 # Total bandwidth to/from this memory (bytes/s) 739242SN/Asystem.physmem.bw_total::realview.ide 9109 # Total bandwidth to/from this memory (bytes/s) 749242SN/Asystem.physmem.bw_total::total 3861140 # Total bandwidth to/from this memory (bytes/s) 759242SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 769242SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 779242SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 789242SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 799242SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 809242SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 819242SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 829242SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 839242SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 849242SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 859242SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 869242SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 879242SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 889242SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 899242SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 909242SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110616Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 929242SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 939242SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 949242SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510616Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 969242SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 979242SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 989242SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 999242SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 1009242SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 1019242SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 1029242SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 1039242SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 1049242SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 1059242SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 1069242SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 1079242SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 1089242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1099242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1109242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1119242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1129242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1139242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1149242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1159242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1169242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1179242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1189242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1199242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1209242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1219242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1229242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1239242SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12410616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12510616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12610616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12710616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12810616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12910616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13010616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13110616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13210616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13310616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13410616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 13510616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13610616Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13710616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 124170 # Table walker walks requested 13810616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors 13910616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency 14010616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14110616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency 14210616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 14310616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 14410616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 14510616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated 14610616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated 1479242SN/Asystem.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated 14810616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst 14910616Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1509242SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst 15111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst 15211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1539242SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst 1549242SN/Asystem.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst 1559242SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 1569242SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 1579242SN/Asystem.cpu0.dtb.read_hits 91996645 # DTB read hits 1589242SN/Asystem.cpu0.dtb.read_misses 87944 # DTB read misses 1599242SN/Asystem.cpu0.dtb.write_hits 85085804 # DTB write hits 1609242SN/Asystem.cpu0.dtb.write_misses 36226 # DTB write misses 1619242SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 1629242SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1639242SN/Asystem.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 1649242SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 1659242SN/Asystem.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB 1669242SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1679242SN/Asystem.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch 16810892Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16911201Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions 17011201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 92084589 # DTB read accesses 17111201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 85122030 # DTB write accesses 1729242SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1739242SN/Asystem.cpu0.dtb.hits 177082449 # DTB hits 1749242SN/Asystem.cpu0.dtb.misses 124170 # DTB misses 17510616Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 177206619 # DTB accesses 17611201Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17711201Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17810616Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1799242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1809242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1819242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1829242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1839242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1849242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1859242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1869242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1879242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1889242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1899242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1909242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1919242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1929242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19310892Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19411201Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19511201Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19611201Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19711201Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19811201Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19910616Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2009242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2019242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2029242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2039242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2049242SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2059242SN/Asystem.cpu0.itb.walker.walks 60706 # Table walker walks requested 2069242SN/Asystem.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors 2079242SN/Asystem.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency 2089242SN/Asystem.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency 2099242SN/Asystem.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency 2109242SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 2119242SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 2129242SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 2139242SN/Asystem.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated 2149242SN/Asystem.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated 2159242SN/Asystem.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated 2169242SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 2179242SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst 2189242SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst 2199242SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 2209242SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst 2219242SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst 2229242SN/Asystem.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst 2239242SN/Asystem.cpu0.itb.inst_hits 494456191 # ITB inst hits 2249242SN/Asystem.cpu0.itb.inst_misses 60706 # ITB inst misses 2259242SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 2269242SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 2279242SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 22810616Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 22910616Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23010616Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2319242SN/Asystem.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 2329242SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 2339729SN/Asystem.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB 2349242SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2359242SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2369242SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710616Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23810616Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 23910616Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 24010616Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 494516897 # ITB inst accesses 24110616Sandreas.hansson@arm.comsystem.cpu0.itb.hits 494456191 # DTB hits 24210616Sandreas.hansson@arm.comsystem.cpu0.itb.misses 60706 # DTB misses 24310616Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 494516897 # DTB accesses 24410616Sandreas.hansson@arm.comsystem.cpu0.numCycles 94513084765 # number of cpu cycles simulated 24510616Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24610616Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 24710616Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 24810616Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed 24910616Sandreas.hansson@arm.comsystem.cpu0.committedInsts 494222683 # Number of instructions committed 25010616Sandreas.hansson@arm.comsystem.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed 25110616Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses 25210616Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses 2539729SN/Asystem.cpu0.num_func_calls 28754621 # number of times a function call or return occured 25410616Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls 25510616Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 532690974 # number of integer instructions 25610616Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 523276 # number of float instructions 25710616Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read 25810616Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written 2599242SN/Asystem.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read 26010616Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written 26110616Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read 26210616Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written 26310616Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 177183712 # number of memory refs 26410616Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 92070454 # Number of load instructions 26510616Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 85113258 # Number of store instructions 26610616Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles 26710616Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles 26810616Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles 26910616Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.993847 # Percentage of idle cycles 27010616Sandreas.hansson@arm.comsystem.cpu0.Branches 110567658 # Number of branches fetched 27110616Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27210616Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction 27310616Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction 27410616Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction 27510616Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 27610616Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 27710616Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 27810616Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 27910616Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 28010616Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 2819613SN/Asystem.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 28210616Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 28310616Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 2849242SN/Asystem.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 2859242SN/Asystem.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 2869242SN/Asystem.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 2879242SN/Asystem.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 2889242SN/Asystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 2899242SN/Asystem.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 2909242SN/Asystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 2919242SN/Asystem.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 2929242SN/Asystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 2939242SN/Asystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 2949242SN/Asystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 2959242SN/Asystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 2969242SN/Asystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 2979242SN/Asystem.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction 2989242SN/Asystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 2999242SN/Asystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 3009242SN/Asystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction 3019242SN/Asystem.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction 3029242SN/Asystem.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction 3039242SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 3049242SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 3059242SN/Asystem.cpu0.op_class::total 581576758 # Class of executed instruction 3069242SN/Asystem.cpu0.dcache.tags.replacements 6248192 # number of replacements 3079242SN/Asystem.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use 3089242SN/Asystem.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks. 3099242SN/Asystem.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks. 31010616Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks. 31110616Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 3129242SN/Asystem.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor 31310616Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy 31410616Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy 3159242SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 3169242SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 3179242SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 3189242SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 3199242SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 3209242SN/Asystem.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses 3219242SN/Asystem.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses 3229242SN/Asystem.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits 3239242SN/Asystem.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits 3249242SN/Asystem.cpu0.dcache.WriteReq_hits::cpu0.data 80310144 # number of WriteReq hits 3259242SN/Asystem.cpu0.dcache.WriteReq_hits::total 80310144 # number of WriteReq hits 3269242SN/Asystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits 3279242SN/Asystem.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits 3289242SN/Asystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits 3299242SN/Asystem.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits 3309242SN/Asystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits 3319242SN/Asystem.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits 3329242SN/Asystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits 3339242SN/Asystem.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits 3349242SN/Asystem.cpu0.dcache.demand_hits::cpu0.data 165871488 # number of demand (read+write) hits 3359242SN/Asystem.cpu0.dcache.demand_hits::total 165871488 # number of demand (read+write) hits 3369242SN/Asystem.cpu0.dcache.overall_hits::cpu0.data 166085900 # number of overall hits 3379242SN/Asystem.cpu0.dcache.overall_hits::total 166085900 # number of overall hits 3389242SN/Asystem.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses 3399242SN/Asystem.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses 3409242SN/Asystem.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses 3419242SN/Asystem.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses 3429242SN/Asystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses 3439242SN/Asystem.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses 3449242SN/Asystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses 3459242SN/Asystem.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses 3469242SN/Asystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses 3479242SN/Asystem.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses 3489242SN/Asystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses 3499242SN/Asystem.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses 3509242SN/Asystem.cpu0.dcache.demand_misses::cpu0.data 4777518 # number of demand (read+write) misses 3519242SN/Asystem.cpu0.dcache.demand_misses::total 4777518 # number of demand (read+write) misses 3529242SN/Asystem.cpu0.dcache.overall_misses::cpu0.data 5552076 # number of overall misses 3539242SN/Asystem.cpu0.dcache.overall_misses::total 5552076 # number of overall misses 3549242SN/Asystem.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) 3559242SN/Asystem.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) 3569242SN/Asystem.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) 3579242SN/Asystem.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) 3589242SN/Asystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) 3599242SN/Asystem.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) 36010616Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) 36110616Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) 36210616Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) 36310616Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) 36410616Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) 36510616Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) 36610616Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 170649006 # number of demand (read+write) accesses 36710616Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 170649006 # number of demand (read+write) accesses 36810616Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 171637976 # number of overall (read+write) accesses 36910616Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 171637976 # number of overall (read+write) accesses 37010616Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses 37110616Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses 37210616Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses 37310616Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses 37410616Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses 37510616Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses 37610616Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses 37710616Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses 37810616Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses 37910616Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses 38010616Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses 38110616Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses 38210616Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses 3839242SN/Asystem.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses 38410997Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032348 # miss rate for overall accesses 38510997Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032348 # miss rate for overall accesses 38610997Sandreas.sandberg@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710997Sandreas.sandberg@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810997Sandreas.sandberg@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 38910997Sandreas.sandberg@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39010997Sandreas.sandberg@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110997Sandreas.sandberg@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39210997Sandreas.sandberg@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 39310997Sandreas.sandberg@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 39410997Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks 39510997Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::total 6248192 # number of writebacks 39610997Sandreas.sandberg@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 39710997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.replacements 5479450 # number of replacements 39810997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use 39910997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. 40010997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. 40110997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. 40210997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 40310997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor 40410997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 40510997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 40610997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40710997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 40810997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 40910997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 41010997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41110997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses 41210997Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses 41310997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits 41410997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits 41510997Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits 41610997Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits 41710997Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits 41810997Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::total 489031557 # number of overall hits 41910997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses 42010997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses 42110997Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses 42210997Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses 42310997Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses 42410997Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::total 5479967 # number of overall misses 42510997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses) 42610997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses) 42710997Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses 42810997Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses 42910997Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses 43010997Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses 43110997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses 43210997Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses 4339242SN/Asystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses 4349242SN/Asystem.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses 435system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses 436system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses 437system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu0.icache.fast_writes 0 # number of fast writes performed 444system.cpu0.icache.cache_copies 0 # number of cache copies performed 445system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks 446system.cpu0.icache.writebacks::total 5479450 # number of writebacks 447system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 448system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 449system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 450system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 451system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 452system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 453system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 454system.cpu0.l2cache.tags.replacements 2651590 # number of replacements 455system.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use 456system.cpu0.l2cache.tags.total_refs 15457113 # Total number of references to valid blocks. 457system.cpu0.l2cache.tags.sampled_refs 2667587 # Sample count of references to valid blocks. 458system.cpu0.l2cache.tags.avg_refs 5.794418 # Average number of references to valid blocks. 459system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 460system.cpu0.l2cache.tags.occ_blocks::writebacks 15991.608429 # Average occupied blocks per requestor 461system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.291374 # Average occupied blocks per requestor 462system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.584847 # Average occupied blocks per requestor 463system.cpu0.l2cache.tags.occ_percent::writebacks 0.976050 # Average percentage of cache occupancy 464system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003009 # Average percentage of cache occupancy 465system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003148 # Average percentage of cache occupancy 466system.cpu0.l2cache.tags.occ_percent::total 0.982207 # Average percentage of cache occupancy 467system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 468system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15920 # Occupied blocks per task id 469system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id 470system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 471system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1478 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4821 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4797 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4598 # Occupied blocks per task id 477system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 478system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971680 # Percentage of cache occupancy per task id 479system.cpu0.l2cache.tags.tag_accesses 394865177 # Number of tag accesses 480system.cpu0.l2cache.tags.data_accesses 394865177 # Number of data accesses 481system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294372 # number of ReadReq hits 482system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156640 # number of ReadReq hits 483system.cpu0.l2cache.ReadReq_hits::total 451012 # number of ReadReq hits 484system.cpu0.l2cache.WritebackDirty_hits::writebacks 4430802 # number of WritebackDirty hits 485system.cpu0.l2cache.WritebackDirty_hits::total 4430802 # number of WritebackDirty hits 486system.cpu0.l2cache.WritebackClean_hits::writebacks 7295441 # number of WritebackClean hits 487system.cpu0.l2cache.WritebackClean_hits::total 7295441 # number of WritebackClean hits 488system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 774 # number of UpgradeReq hits 489system.cpu0.l2cache.UpgradeReq_hits::total 774 # number of UpgradeReq hits 490system.cpu0.l2cache.ReadExReq_hits::cpu0.data 631554 # number of ReadExReq hits 491system.cpu0.l2cache.ReadExReq_hits::total 631554 # number of ReadExReq hits 492system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4983798 # number of ReadCleanReq hits 493system.cpu0.l2cache.ReadCleanReq_hits::total 4983798 # number of ReadCleanReq hits 494system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2949332 # number of ReadSharedReq hits 495system.cpu0.l2cache.ReadSharedReq_hits::total 2949332 # number of ReadSharedReq hits 496system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218231 # number of InvalidateReq hits 497system.cpu0.l2cache.InvalidateReq_hits::total 218231 # number of InvalidateReq hits 498system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294372 # number of demand (read+write) hits 499system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156640 # number of demand (read+write) hits 500system.cpu0.l2cache.demand_hits::cpu0.inst 4983798 # number of demand (read+write) hits 501system.cpu0.l2cache.demand_hits::cpu0.data 3580886 # number of demand (read+write) hits 502system.cpu0.l2cache.demand_hits::total 9015696 # number of demand (read+write) hits 503system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294372 # number of overall hits 504system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156640 # number of overall hits 505system.cpu0.l2cache.overall_hits::cpu0.inst 4983798 # number of overall hits 506system.cpu0.l2cache.overall_hits::cpu0.data 3580886 # number of overall hits 507system.cpu0.l2cache.overall_hits::total 9015696 # number of overall hits 508system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11531 # number of ReadReq misses 509system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8761 # number of ReadReq misses 510system.cpu0.l2cache.ReadReq_misses::total 20292 # number of ReadReq misses 511system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140614 # number of UpgradeReq misses 512system.cpu0.l2cache.UpgradeReq_misses::total 140614 # number of UpgradeReq misses 513system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156654 # number of SCUpgradeReq misses 514system.cpu0.l2cache.SCUpgradeReq_misses::total 156654 # number of SCUpgradeReq misses 515system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712280 # number of ReadExReq misses 516system.cpu0.l2cache.ReadExReq_misses::total 712280 # number of ReadExReq misses 517system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 496169 # number of ReadCleanReq misses 518system.cpu0.l2cache.ReadCleanReq_misses::total 496169 # number of ReadCleanReq misses 519system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236248 # number of ReadSharedReq misses 520system.cpu0.l2cache.ReadSharedReq_misses::total 1236248 # number of ReadSharedReq misses 521system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604597 # number of InvalidateReq misses 522system.cpu0.l2cache.InvalidateReq_misses::total 604597 # number of InvalidateReq misses 523system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11531 # number of demand (read+write) misses 524system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8761 # number of demand (read+write) misses 525system.cpu0.l2cache.demand_misses::cpu0.inst 496169 # number of demand (read+write) misses 526system.cpu0.l2cache.demand_misses::cpu0.data 1948528 # number of demand (read+write) misses 527system.cpu0.l2cache.demand_misses::total 2464989 # number of demand (read+write) misses 528system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11531 # number of overall misses 529system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8761 # number of overall misses 530system.cpu0.l2cache.overall_misses::cpu0.inst 496169 # number of overall misses 531system.cpu0.l2cache.overall_misses::cpu0.data 1948528 # number of overall misses 532system.cpu0.l2cache.overall_misses::total 2464989 # number of overall misses 533system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305903 # number of ReadReq accesses(hits+misses) 534system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165401 # number of ReadReq accesses(hits+misses) 535system.cpu0.l2cache.ReadReq_accesses::total 471304 # number of ReadReq accesses(hits+misses) 536system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4430802 # number of WritebackDirty accesses(hits+misses) 537system.cpu0.l2cache.WritebackDirty_accesses::total 4430802 # number of WritebackDirty accesses(hits+misses) 538system.cpu0.l2cache.WritebackClean_accesses::writebacks 7295441 # number of WritebackClean accesses(hits+misses) 539system.cpu0.l2cache.WritebackClean_accesses::total 7295441 # number of WritebackClean accesses(hits+misses) 540system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141388 # number of UpgradeReq accesses(hits+misses) 541system.cpu0.l2cache.UpgradeReq_accesses::total 141388 # number of UpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156654 # number of SCUpgradeReq accesses(hits+misses) 543system.cpu0.l2cache.SCUpgradeReq_accesses::total 156654 # number of SCUpgradeReq accesses(hits+misses) 544system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses) 545system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses) 546system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses) 547system.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses) 548system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses) 549system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses) 550system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses) 551system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses) 552system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305903 # number of demand (read+write) accesses 553system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165401 # number of demand (read+write) accesses 554system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses 555system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses 556system.cpu0.l2cache.demand_accesses::total 11480685 # number of demand (read+write) accesses 557system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305903 # number of overall (read+write) accesses 558system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165401 # number of overall (read+write) accesses 559system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses 560system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses 561system.cpu0.l2cache.overall_accesses::total 11480685 # number of overall (read+write) accesses 562system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for ReadReq accesses 563system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052968 # miss rate for ReadReq accesses 564system.cpu0.l2cache.ReadReq_miss_rate::total 0.043055 # miss rate for ReadReq accesses 565system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994526 # miss rate for UpgradeReq accesses 566system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994526 # miss rate for UpgradeReq accesses 567system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 568system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 569system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530036 # miss rate for ReadExReq accesses 570system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530036 # miss rate for ReadExReq accesses 571system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090542 # miss rate for ReadCleanReq accesses 572system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090542 # miss rate for ReadCleanReq accesses 573system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295359 # miss rate for ReadSharedReq accesses 574system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295359 # miss rate for ReadSharedReq accesses 575system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734779 # miss rate for InvalidateReq accesses 576system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734779 # miss rate for InvalidateReq accesses 577system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for demand accesses 578system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052968 # miss rate for demand accesses 579system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090542 # miss rate for demand accesses 580system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352393 # miss rate for demand accesses 581system.cpu0.l2cache.demand_miss_rate::total 0.214707 # miss rate for demand accesses 582system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for overall accesses 583system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052968 # miss rate for overall accesses 584system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090542 # miss rate for overall accesses 585system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses 586system.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses 587system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 588system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 589system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 590system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 591system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 592system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 593system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 594system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 595system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks 596system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks 597system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 598system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter. 599system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data. 600system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter. 602system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 603system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::WritebackDirty 4430802 # Transaction distribution 609system.cpu0.toL2Bus.trans_dist::WritebackClean 7296840 # Transaction distribution 610system.cpu0.toL2Bus.trans_dist::UpgradeReq 141388 # Transaction distribution 611system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156654 # Transaction distribution 612system.cpu0.toL2Bus.trans_dist::UpgradeResp 298042 # Transaction distribution 613system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution 614system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution 615system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution 616system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution 617system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution 618system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution 619system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes) 620system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681390 # Packet count per connected master and slave (bytes) 621system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes) 622system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes) 623system.cpu0.toL2Bus.pkt_count::total 37292106 # Packet count per connected master and slave (bytes) 624system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes) 625system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes) 626system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes) 627system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes) 628system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes) 629system.cpu0.toL2Bus.snoops 6124419 # Total snoops (count) 630system.cpu0.toL2Bus.snoop_fanout::samples 30450834 # Request fanout histogram 631system.cpu0.toL2Bus.snoop_fanout::mean 0.067260 # Request fanout histogram 632system.cpu0.toL2Bus.snoop_fanout::stdev 0.250516 # Request fanout histogram 633system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 634system.cpu0.toL2Bus.snoop_fanout::0 28403043 93.28% 93.28% # Request fanout histogram 635system.cpu0.toL2Bus.snoop_fanout::1 2047457 6.72% 100.00% # Request fanout histogram 636system.cpu0.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram 637system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 638system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 639system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 640system.cpu0.toL2Bus.snoop_fanout::total 30450834 # Request fanout histogram 641system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 642system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 643system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 644system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 645system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 646system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 647system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 648system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 649system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 650system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 651system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 652system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 653system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 654system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 655system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 656system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 657system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 658system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 659system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 660system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 661system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 662system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 663system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 664system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 665system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 666system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 667system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 668system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 669system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 670system.cpu1.dtb.walker.walks 145097 # Table walker walks requested 671system.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors 672system.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency 673system.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency 674system.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency 675system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 676system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 677system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 678system.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated 679system.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated 680system.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated 681system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst 682system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 683system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst 684system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst 685system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 686system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst 687system.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst 688system.cpu1.dtb.inst_hits 0 # ITB inst hits 689system.cpu1.dtb.inst_misses 0 # ITB inst misses 690system.cpu1.dtb.read_hits 90839106 # DTB read hits 691system.cpu1.dtb.read_misses 112437 # DTB read misses 692system.cpu1.dtb.write_hits 81787747 # DTB write hits 693system.cpu1.dtb.write_misses 32660 # DTB write misses 694system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 695system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 696system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 697system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 698system.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB 699system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 700system.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch 701system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 702system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions 703system.cpu1.dtb.read_accesses 90951543 # DTB read accesses 704system.cpu1.dtb.write_accesses 81820407 # DTB write accesses 705system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 706system.cpu1.dtb.hits 172626853 # DTB hits 707system.cpu1.dtb.misses 145097 # DTB misses 708system.cpu1.dtb.accesses 172771950 # DTB accesses 709system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 710system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 711system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 712system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 713system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 714system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 715system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 716system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 717system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 718system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 719system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 720system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 721system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 722system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 723system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 724system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 725system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 726system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 727system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 728system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 729system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 730system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 731system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 732system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 733system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 734system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 735system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 736system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 737system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 738system.cpu1.itb.walker.walks 61573 # Table walker walks requested 739system.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors 740system.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency 741system.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency 742system.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency 743system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 744system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 745system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 746system.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated 747system.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated 748system.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated 749system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 750system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst 751system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst 752system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 753system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst 754system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst 755system.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst 756system.cpu1.itb.inst_hits 481656543 # ITB inst hits 757system.cpu1.itb.inst_misses 61573 # ITB inst misses 758system.cpu1.itb.read_hits 0 # DTB read hits 759system.cpu1.itb.read_misses 0 # DTB read misses 760system.cpu1.itb.write_hits 0 # DTB write hits 761system.cpu1.itb.write_misses 0 # DTB write misses 762system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 763system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 764system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID 765system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 766system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB 767system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 768system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 769system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 770system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 771system.cpu1.itb.read_accesses 0 # DTB read accesses 772system.cpu1.itb.write_accesses 0 # DTB write accesses 773system.cpu1.itb.inst_accesses 481718116 # ITB inst accesses 774system.cpu1.itb.hits 481656543 # DTB hits 775system.cpu1.itb.misses 61573 # DTB misses 776system.cpu1.itb.accesses 481718116 # DTB accesses 777system.cpu1.numCycles 94513077683 # number of cpu cycles simulated 778system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 779system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 780system.cpu1.kern.inst.arm 0 # number of arm instructions executed 781system.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed 782system.cpu1.committedInsts 481403040 # Number of instructions committed 783system.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed 784system.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses 785system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses 786system.cpu1.num_func_calls 28379648 # number of times a function call or return occured 787system.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls 788system.cpu1.num_int_insts 519926686 # number of integer instructions 789system.cpu1.num_fp_insts 376275 # number of float instructions 790system.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read 791system.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written 792system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read 793system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written 794system.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read 795system.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written 796system.cpu1.num_mem_refs 172748485 # number of memory refs 797system.cpu1.num_load_insts 90938541 # Number of load instructions 798system.cpu1.num_store_insts 81809944 # Number of store instructions 799system.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles 800system.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles 801system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles 802system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles 803system.cpu1.Branches 107246711 # Number of branches fetched 804system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 805system.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction 806system.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction 807system.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction 808system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 809system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 810system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 811system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 812system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 813system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 814system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 815system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 816system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 817system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 818system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 819system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 820system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 821system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 822system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 823system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 824system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 825system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 826system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 827system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 828system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 829system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 830system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction 831system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 832system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 833system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 834system.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction 835system.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction 836system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 837system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 838system.cpu1.op_class::total 566836400 # Class of executed instruction 839system.cpu1.dcache.tags.replacements 5963482 # number of replacements 840system.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use 841system.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks. 842system.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks. 843system.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks. 844system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 845system.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor 846system.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy 847system.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy 848system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 849system.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id 850system.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id 851system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 852system.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses 853system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses 854system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits 855system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits 856system.cpu1.dcache.WriteReq_hits::cpu1.data 77626026 # number of WriteReq hits 857system.cpu1.dcache.WriteReq_hits::total 77626026 # number of WriteReq hits 858system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits 859system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits 860system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits 861system.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits 862system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits 863system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits 864system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits 865system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits 866system.cpu1.dcache.demand_hits::cpu1.data 162001697 # number of demand (read+write) hits 867system.cpu1.dcache.demand_hits::total 162001697 # number of demand (read+write) hits 868system.cpu1.dcache.overall_hits::cpu1.data 162189982 # number of overall hits 869system.cpu1.dcache.overall_hits::total 162189982 # number of overall hits 870system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses 871system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses 872system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses 873system.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses 874system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses 875system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses 876system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses 877system.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses 878system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses 879system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses 880system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses 881system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses 882system.cpu1.dcache.demand_misses::cpu1.data 4833784 # number of demand (read+write) misses 883system.cpu1.dcache.demand_misses::total 4833784 # number of demand (read+write) misses 884system.cpu1.dcache.overall_misses::cpu1.data 5624082 # number of overall misses 885system.cpu1.dcache.overall_misses::total 5624082 # number of overall misses 886system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) 887system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) 888system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) 889system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) 890system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) 891system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) 892system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) 893system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) 894system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) 895system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) 896system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) 897system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) 898system.cpu1.dcache.demand_accesses::cpu1.data 166835481 # number of demand (read+write) accesses 899system.cpu1.dcache.demand_accesses::total 166835481 # number of demand (read+write) accesses 900system.cpu1.dcache.overall_accesses::cpu1.data 167814064 # number of overall (read+write) accesses 901system.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses 902system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses 903system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses 904system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses 905system.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses 906system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses 907system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses 908system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses 909system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses 910system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses 911system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses 912system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses 913system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses 914system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses 915system.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses 916system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033514 # miss rate for overall accesses 917system.cpu1.dcache.overall_miss_rate::total 0.033514 # miss rate for overall accesses 918system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu1.dcache.fast_writes 0 # number of fast writes performed 925system.cpu1.dcache.cache_copies 0 # number of cache copies performed 926system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks 927system.cpu1.dcache.writebacks::total 5963482 # number of writebacks 928system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 929system.cpu1.icache.tags.replacements 4804881 # number of replacements 930system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use 931system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. 932system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. 933system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. 934system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 935system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor 936system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy 937system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy 938system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 939system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 940system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id 941system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 942system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 943system.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses 944system.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses 945system.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits 946system.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits 947system.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits 948system.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits 949system.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits 950system.cpu1.icache.overall_hits::total 476906226 # number of overall hits 951system.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses 952system.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses 953system.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses 954system.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses 955system.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses 956system.cpu1.icache.overall_misses::total 4805393 # number of overall misses 957system.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses) 958system.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses) 959system.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses 960system.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses 961system.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses 962system.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses 963system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses 964system.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses 965system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses 966system.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses 967system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses 968system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses 969system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 970system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 971system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 972system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 973system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 974system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 975system.cpu1.icache.fast_writes 0 # number of fast writes performed 976system.cpu1.icache.cache_copies 0 # number of cache copies performed 977system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks 978system.cpu1.icache.writebacks::total 4804881 # number of writebacks 979system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 980system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 981system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 982system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 983system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 984system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 985system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 986system.cpu1.l2cache.tags.replacements 2274505 # number of replacements 987system.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use 988system.cpu1.l2cache.tags.total_refs 14355408 # Total number of references to valid blocks. 989system.cpu1.l2cache.tags.sampled_refs 2290637 # Sample count of references to valid blocks. 990system.cpu1.l2cache.tags.avg_refs 6.266994 # Average number of references to valid blocks. 991system.cpu1.l2cache.tags.warmup_cycle 9713557342500 # Cycle when the warmup percentage was hit. 992system.cpu1.l2cache.tags.occ_blocks::writebacks 13266.664229 # Average occupied blocks per requestor 993system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.449121 # Average occupied blocks per requestor 994system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.160502 # Average occupied blocks per requestor 995system.cpu1.l2cache.tags.occ_percent::writebacks 0.809733 # Average percentage of cache occupancy 996system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002713 # Average percentage of cache occupancy 997system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003611 # Average percentage of cache occupancy 998system.cpu1.l2cache.tags.occ_percent::total 0.816057 # Average percentage of cache occupancy 999system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id 1000system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id 1001system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1002system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id 1003system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1004system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 1005system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id 1006system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id 1007system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5867 # Occupied blocks per task id 1008system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4427 # Occupied blocks per task id 1009system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3923 # Occupied blocks per task id 1010system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id 1011system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id 1012system.cpu1.l2cache.tags.tag_accesses 364664430 # Number of tag accesses 1013system.cpu1.l2cache.tags.data_accesses 364664430 # Number of data accesses 1014system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349739 # number of ReadReq hits 1015system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155441 # number of ReadReq hits 1016system.cpu1.l2cache.ReadReq_hits::total 505180 # number of ReadReq hits 1017system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030758 # number of WritebackDirty hits 1018system.cpu1.l2cache.WritebackDirty_hits::total 4030758 # number of WritebackDirty hits 1019system.cpu1.l2cache.WritebackClean_hits::writebacks 6737219 # number of WritebackClean hits 1020system.cpu1.l2cache.WritebackClean_hits::total 6737219 # number of WritebackClean hits 1021system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1036 # number of UpgradeReq hits 1022system.cpu1.l2cache.UpgradeReq_hits::total 1036 # number of UpgradeReq hits 1023system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606945 # number of ReadExReq hits 1024system.cpu1.l2cache.ReadExReq_hits::total 606945 # number of ReadExReq hits 1025system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338204 # number of ReadCleanReq hits 1026system.cpu1.l2cache.ReadCleanReq_hits::total 4338204 # number of ReadCleanReq hits 1027system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3075973 # number of ReadSharedReq hits 1028system.cpu1.l2cache.ReadSharedReq_hits::total 3075973 # number of ReadSharedReq hits 1029system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 162958 # number of InvalidateReq hits 1030system.cpu1.l2cache.InvalidateReq_hits::total 162958 # number of InvalidateReq hits 1031system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349739 # number of demand (read+write) hits 1032system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155441 # number of demand (read+write) hits 1033system.cpu1.l2cache.demand_hits::cpu1.inst 4338204 # number of demand (read+write) hits 1034system.cpu1.l2cache.demand_hits::cpu1.data 3682918 # number of demand (read+write) hits 1035system.cpu1.l2cache.demand_hits::total 8526302 # number of demand (read+write) hits 1036system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349739 # number of overall hits 1037system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155441 # number of overall hits 1038system.cpu1.l2cache.overall_hits::cpu1.inst 4338204 # number of overall hits 1039system.cpu1.l2cache.overall_hits::cpu1.data 3682918 # number of overall hits 1040system.cpu1.l2cache.overall_hits::total 8526302 # number of overall hits 1041system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12351 # number of ReadReq misses 1042system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9805 # number of ReadReq misses 1043system.cpu1.l2cache.ReadReq_misses::total 22156 # number of ReadReq misses 1044system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147585 # number of UpgradeReq misses 1045system.cpu1.l2cache.UpgradeReq_misses::total 147585 # number of UpgradeReq misses 1046system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158992 # number of SCUpgradeReq misses 1047system.cpu1.l2cache.SCUpgradeReq_misses::total 158992 # number of SCUpgradeReq misses 1048system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708546 # number of ReadExReq misses 1049system.cpu1.l2cache.ReadExReq_misses::total 708546 # number of ReadExReq misses 1050system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467189 # number of ReadCleanReq misses 1051system.cpu1.l2cache.ReadCleanReq_misses::total 467189 # number of ReadCleanReq misses 1052system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230120 # number of ReadSharedReq misses 1053system.cpu1.l2cache.ReadSharedReq_misses::total 1230120 # number of ReadSharedReq misses 1054system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272650 # number of InvalidateReq misses 1055system.cpu1.l2cache.InvalidateReq_misses::total 272650 # number of InvalidateReq misses 1056system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12351 # number of demand (read+write) misses 1057system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9805 # number of demand (read+write) misses 1058system.cpu1.l2cache.demand_misses::cpu1.inst 467189 # number of demand (read+write) misses 1059system.cpu1.l2cache.demand_misses::cpu1.data 1938666 # number of demand (read+write) misses 1060system.cpu1.l2cache.demand_misses::total 2428011 # number of demand (read+write) misses 1061system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12351 # number of overall misses 1062system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9805 # number of overall misses 1063system.cpu1.l2cache.overall_misses::cpu1.inst 467189 # number of overall misses 1064system.cpu1.l2cache.overall_misses::cpu1.data 1938666 # number of overall misses 1065system.cpu1.l2cache.overall_misses::total 2428011 # number of overall misses 1066system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362090 # number of ReadReq accesses(hits+misses) 1067system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165246 # number of ReadReq accesses(hits+misses) 1068system.cpu1.l2cache.ReadReq_accesses::total 527336 # number of ReadReq accesses(hits+misses) 1069system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030758 # number of WritebackDirty accesses(hits+misses) 1070system.cpu1.l2cache.WritebackDirty_accesses::total 4030758 # number of WritebackDirty accesses(hits+misses) 1071system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737219 # number of WritebackClean accesses(hits+misses) 1072system.cpu1.l2cache.WritebackClean_accesses::total 6737219 # number of WritebackClean accesses(hits+misses) 1073system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148621 # number of UpgradeReq accesses(hits+misses) 1074system.cpu1.l2cache.UpgradeReq_accesses::total 148621 # number of UpgradeReq accesses(hits+misses) 1075system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158992 # number of SCUpgradeReq accesses(hits+misses) 1076system.cpu1.l2cache.SCUpgradeReq_accesses::total 158992 # number of SCUpgradeReq accesses(hits+misses) 1077system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses) 1078system.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses) 1079system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses) 1080system.cpu1.l2cache.ReadCleanReq_accesses::total 4805393 # number of ReadCleanReq accesses(hits+misses) 1081system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 # number of ReadSharedReq accesses(hits+misses) 1082system.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses) 1083system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses) 1084system.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses) 1085system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362090 # number of demand (read+write) accesses 1086system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165246 # number of demand (read+write) accesses 1087system.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses 1088system.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses 1089system.cpu1.l2cache.demand_accesses::total 10954313 # number of demand (read+write) accesses 1090system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362090 # number of overall (read+write) accesses 1091system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165246 # number of overall (read+write) accesses 1092system.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses 1093system.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses 1094system.cpu1.l2cache.overall_accesses::total 10954313 # number of overall (read+write) accesses 1095system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for ReadReq accesses 1096system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059336 # miss rate for ReadReq accesses 1097system.cpu1.l2cache.ReadReq_miss_rate::total 0.042015 # miss rate for ReadReq accesses 1098system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993029 # miss rate for UpgradeReq accesses 1099system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993029 # miss rate for UpgradeReq accesses 1100system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1101system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1102system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538617 # miss rate for ReadExReq accesses 1103system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538617 # miss rate for ReadExReq accesses 1104system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097222 # miss rate for ReadCleanReq accesses 1105system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097222 # miss rate for ReadCleanReq accesses 1106system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285670 # miss rate for ReadSharedReq accesses 1107system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285670 # miss rate for ReadSharedReq accesses 1108system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625907 # miss rate for InvalidateReq accesses 1109system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625907 # miss rate for InvalidateReq accesses 1110system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for demand accesses 1111system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059336 # miss rate for demand accesses 1112system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097222 # miss rate for demand accesses 1113system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344861 # miss rate for demand accesses 1114system.cpu1.l2cache.demand_miss_rate::total 0.221649 # miss rate for demand accesses 1115system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for overall accesses 1116system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059336 # miss rate for overall accesses 1117system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097222 # miss rate for overall accesses 1118system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses 1119system.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses 1120system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1121system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1122system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1123system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1124system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1125system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1126system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1127system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1128system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks 1129system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks 1130system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1131system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter. 1132system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1133system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1134system.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter. 1135system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1136system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1137system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution 1138system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution 1139system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution 1140system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution 1141system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030758 # Transaction distribution 1142system.cpu1.toL2Bus.trans_dist::WritebackClean 6737605 # Transaction distribution 1143system.cpu1.toL2Bus.trans_dist::UpgradeReq 148621 # Transaction distribution 1144system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158992 # Transaction distribution 1145system.cpu1.toL2Bus.trans_dist::UpgradeResp 307613 # Transaction distribution 1146system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution 1147system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution 1148system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution 1149system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution 1150system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution 1151system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution 1152system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes) 1153system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18716020 # Packet count per connected master and slave (bytes) 1154system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) 1155system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes) 1156system.cpu1.toL2Bus.pkt_count::total 34341155 # Packet count per connected master and slave (bytes) 1157system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes) 1158system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes) 1159system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) 1160system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu1.toL2Bus.snoops 5725702 # Total snoops (count) 1163system.cpu1.toL2Bus.snoop_fanout::samples 28118123 # Request fanout histogram 1164system.cpu1.toL2Bus.snoop_fanout::mean 0.072932 # Request fanout histogram 1165system.cpu1.toL2Bus.snoop_fanout::stdev 0.260049 # Request fanout histogram 1166system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1167system.cpu1.toL2Bus.snoop_fanout::0 26067606 92.71% 92.71% # Request fanout histogram 1168system.cpu1.toL2Bus.snoop_fanout::1 2050333 7.29% 100.00% # Request fanout histogram 1169system.cpu1.toL2Bus.snoop_fanout::2 184 0.00% 100.00% # Request fanout histogram 1170system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1171system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1172system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1173system.cpu1.toL2Bus.snoop_fanout::total 28118123 # Request fanout histogram 1174system.iobus.trans_dist::ReadReq 40311 # Transaction distribution 1175system.iobus.trans_dist::ReadResp 40311 # Transaction distribution 1176system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1177system.iobus.trans_dist::WriteResp 136636 # Transaction distribution 1178system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1195system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes) 1197system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) 1211system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes) 1216system.iocache.tags.replacements 115596 # number of replacements 1217system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use 1218system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1219system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. 1220system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1221system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 1222system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor 1223system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor 1224system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy 1225system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy 1226system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy 1227system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1228system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1229system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1230system.iocache.tags.tag_accesses 1040892 # Number of tag accesses 1231system.iocache.tags.data_accesses 1040892 # Number of data accesses 1232system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1233system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses 1234system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses 1235system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1236system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1237system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1238system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1239system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1240system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses 1241system.iocache.demand_misses::total 8927 # number of demand (read+write) misses 1242system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1243system.iocache.overall_misses::realview.ide 8887 # number of overall misses 1244system.iocache.overall_misses::total 8927 # number of overall misses 1245system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1246system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) 1247system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) 1248system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1249system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1250system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1251system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1252system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1253system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses 1254system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses 1255system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1256system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses 1257system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses 1258system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1259system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1260system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1261system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1262system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1263system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1264system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1265system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1266system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1267system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1268system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1269system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1270system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1271system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1272system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1273system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1274system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1275system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1276system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1277system.iocache.fast_writes 0 # number of fast writes performed 1278system.iocache.cache_copies 0 # number of cache copies performed 1279system.iocache.writebacks::writebacks 106694 # number of writebacks 1280system.iocache.writebacks::total 106694 # number of writebacks 1281system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1282system.l2c.tags.replacements 1766126 # number of replacements 1283system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use 1284system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks. 1285system.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks. 1286system.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks. 1287system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 1288system.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor 1289system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor 1290system.l2c.tags.occ_blocks::cpu0.itb.walker 102.298868 # Average occupied blocks per requestor 1291system.l2c.tags.occ_blocks::cpu0.inst 3405.442592 # Average occupied blocks per requestor 1292system.l2c.tags.occ_blocks::cpu0.data 8003.318713 # Average occupied blocks per requestor 1293system.l2c.tags.occ_blocks::cpu1.dtb.walker 244.723732 # Average occupied blocks per requestor 1294system.l2c.tags.occ_blocks::cpu1.itb.walker 389.512702 # Average occupied blocks per requestor 1295system.l2c.tags.occ_blocks::cpu1.inst 2881.151775 # Average occupied blocks per requestor 1296system.l2c.tags.occ_blocks::cpu1.data 13153.170652 # Average occupied blocks per requestor 1297system.l2c.tags.occ_percent::writebacks 0.531906 # Average percentage of cache occupancy 1298system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001038 # Average percentage of cache occupancy 1299system.l2c.tags.occ_percent::cpu0.itb.walker 0.001561 # Average percentage of cache occupancy 1300system.l2c.tags.occ_percent::cpu0.inst 0.051963 # Average percentage of cache occupancy 1301system.l2c.tags.occ_percent::cpu0.data 0.122121 # Average percentage of cache occupancy 1302system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003734 # Average percentage of cache occupancy 1303system.l2c.tags.occ_percent::cpu1.itb.walker 0.005943 # Average percentage of cache occupancy 1304system.l2c.tags.occ_percent::cpu1.inst 0.043963 # Average percentage of cache occupancy 1305system.l2c.tags.occ_percent::cpu1.data 0.200701 # Average percentage of cache occupancy 1306system.l2c.tags.occ_percent::total 0.962930 # Average percentage of cache occupancy 1307system.l2c.tags.occ_task_id_blocks::1023 203 # Occupied blocks per task id 1308system.l2c.tags.occ_task_id_blocks::1024 59170 # Occupied blocks per task id 1309system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1310system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id 1311system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1312system.l2c.tags.age_task_id_blocks_1024::1 472 # Occupied blocks per task id 1313system.l2c.tags.age_task_id_blocks_1024::2 3156 # Occupied blocks per task id 1314system.l2c.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id 1315system.l2c.tags.age_task_id_blocks_1024::4 50220 # Occupied blocks per task id 1316system.l2c.tags.occ_task_id_percent::1023 0.003098 # Percentage of cache occupancy per task id 1317system.l2c.tags.occ_task_id_percent::1024 0.902863 # Percentage of cache occupancy per task id 1318system.l2c.tags.tag_accesses 73355182 # Number of tag accesses 1319system.l2c.tags.data_accesses 73355182 # Number of data accesses 1320system.l2c.WritebackDirty_hits::writebacks 2757627 # number of WritebackDirty hits 1321system.l2c.WritebackDirty_hits::total 2757627 # number of WritebackDirty hits 1322system.l2c.UpgradeReq_hits::cpu0.data 19019 # number of UpgradeReq hits 1323system.l2c.UpgradeReq_hits::cpu1.data 16164 # number of UpgradeReq hits 1324system.l2c.UpgradeReq_hits::total 35183 # number of UpgradeReq hits 1325system.l2c.SCUpgradeReq_hits::cpu0.data 2641 # number of SCUpgradeReq hits 1326system.l2c.SCUpgradeReq_hits::cpu1.data 2463 # number of SCUpgradeReq hits 1327system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits 1328system.l2c.ReadExReq_hits::cpu0.data 198159 # number of ReadExReq hits 1329system.l2c.ReadExReq_hits::cpu1.data 177179 # number of ReadExReq hits 1330system.l2c.ReadExReq_hits::total 375338 # number of ReadExReq hits 1331system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6315 # number of ReadSharedReq hits 1332system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4649 # number of ReadSharedReq hits 1333system.l2c.ReadSharedReq_hits::cpu0.inst 438189 # number of ReadSharedReq hits 1334system.l2c.ReadSharedReq_hits::cpu0.data 723007 # number of ReadSharedReq hits 1335system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5487 # number of ReadSharedReq hits 1336system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3779 # number of ReadSharedReq hits 1337system.l2c.ReadSharedReq_hits::cpu1.inst 426355 # number of ReadSharedReq hits 1338system.l2c.ReadSharedReq_hits::cpu1.data 685222 # number of ReadSharedReq hits 1339system.l2c.ReadSharedReq_hits::total 2293003 # number of ReadSharedReq hits 1340system.l2c.InvalidateReq_hits::cpu0.data 118931 # number of InvalidateReq hits 1341system.l2c.InvalidateReq_hits::cpu1.data 103897 # number of InvalidateReq hits 1342system.l2c.InvalidateReq_hits::total 222828 # number of InvalidateReq hits 1343system.l2c.demand_hits::cpu0.dtb.walker 6315 # number of demand (read+write) hits 1344system.l2c.demand_hits::cpu0.itb.walker 4649 # number of demand (read+write) hits 1345system.l2c.demand_hits::cpu0.inst 438189 # number of demand (read+write) hits 1346system.l2c.demand_hits::cpu0.data 921166 # number of demand (read+write) hits 1347system.l2c.demand_hits::cpu1.dtb.walker 5487 # number of demand (read+write) hits 1348system.l2c.demand_hits::cpu1.itb.walker 3779 # number of demand (read+write) hits 1349system.l2c.demand_hits::cpu1.inst 426355 # number of demand (read+write) hits 1350system.l2c.demand_hits::cpu1.data 862401 # number of demand (read+write) hits 1351system.l2c.demand_hits::total 2668341 # number of demand (read+write) hits 1352system.l2c.overall_hits::cpu0.dtb.walker 6315 # number of overall hits 1353system.l2c.overall_hits::cpu0.itb.walker 4649 # number of overall hits 1354system.l2c.overall_hits::cpu0.inst 438189 # number of overall hits 1355system.l2c.overall_hits::cpu0.data 921166 # number of overall hits 1356system.l2c.overall_hits::cpu1.dtb.walker 5487 # number of overall hits 1357system.l2c.overall_hits::cpu1.itb.walker 3779 # number of overall hits 1358system.l2c.overall_hits::cpu1.inst 426355 # number of overall hits 1359system.l2c.overall_hits::cpu1.data 862401 # number of overall hits 1360system.l2c.overall_hits::total 2668341 # number of overall hits 1361system.l2c.UpgradeReq_misses::cpu0.data 65379 # number of UpgradeReq misses 1362system.l2c.UpgradeReq_misses::cpu1.data 61938 # number of UpgradeReq misses 1363system.l2c.UpgradeReq_misses::total 127317 # number of UpgradeReq misses 1364system.l2c.SCUpgradeReq_misses::cpu0.data 6666 # number of SCUpgradeReq misses 1365system.l2c.SCUpgradeReq_misses::cpu1.data 6353 # number of SCUpgradeReq misses 1366system.l2c.SCUpgradeReq_misses::total 13019 # number of SCUpgradeReq misses 1367system.l2c.ReadExReq_misses::cpu0.data 385718 # number of ReadExReq misses 1368system.l2c.ReadExReq_misses::cpu1.data 415753 # number of ReadExReq misses 1369system.l2c.ReadExReq_misses::total 801471 # number of ReadExReq misses 1370system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2451 # number of ReadSharedReq misses 1371system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2053 # number of ReadSharedReq misses 1372system.l2c.ReadSharedReq_misses::cpu0.inst 57980 # number of ReadSharedReq misses 1373system.l2c.ReadSharedReq_misses::cpu0.data 180523 # number of ReadSharedReq misses 1374system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3403 # number of ReadSharedReq misses 1375system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3345 # number of ReadSharedReq misses 1376system.l2c.ReadSharedReq_misses::cpu1.inst 40834 # number of ReadSharedReq misses 1377system.l2c.ReadSharedReq_misses::cpu1.data 186956 # number of ReadSharedReq misses 1378system.l2c.ReadSharedReq_misses::total 477545 # number of ReadSharedReq misses 1379system.l2c.InvalidateReq_misses::cpu0.data 477269 # number of InvalidateReq misses 1380system.l2c.InvalidateReq_misses::cpu1.data 162394 # number of InvalidateReq misses 1381system.l2c.InvalidateReq_misses::total 639663 # number of InvalidateReq misses 1382system.l2c.demand_misses::cpu0.dtb.walker 2451 # number of demand (read+write) misses 1383system.l2c.demand_misses::cpu0.itb.walker 2053 # number of demand (read+write) misses 1384system.l2c.demand_misses::cpu0.inst 57980 # number of demand (read+write) misses 1385system.l2c.demand_misses::cpu0.data 566241 # number of demand (read+write) misses 1386system.l2c.demand_misses::cpu1.dtb.walker 3403 # number of demand (read+write) misses 1387system.l2c.demand_misses::cpu1.itb.walker 3345 # number of demand (read+write) misses 1388system.l2c.demand_misses::cpu1.inst 40834 # number of demand (read+write) misses 1389system.l2c.demand_misses::cpu1.data 602709 # number of demand (read+write) misses 1390system.l2c.demand_misses::total 1279016 # number of demand (read+write) misses 1391system.l2c.overall_misses::cpu0.dtb.walker 2451 # number of overall misses 1392system.l2c.overall_misses::cpu0.itb.walker 2053 # number of overall misses 1393system.l2c.overall_misses::cpu0.inst 57980 # number of overall misses 1394system.l2c.overall_misses::cpu0.data 566241 # number of overall misses 1395system.l2c.overall_misses::cpu1.dtb.walker 3403 # number of overall misses 1396system.l2c.overall_misses::cpu1.itb.walker 3345 # number of overall misses 1397system.l2c.overall_misses::cpu1.inst 40834 # number of overall misses 1398system.l2c.overall_misses::cpu1.data 602709 # number of overall misses 1399system.l2c.overall_misses::total 1279016 # number of overall misses 1400system.l2c.WritebackDirty_accesses::writebacks 2757627 # number of WritebackDirty accesses(hits+misses) 1401system.l2c.WritebackDirty_accesses::total 2757627 # number of WritebackDirty accesses(hits+misses) 1402system.l2c.UpgradeReq_accesses::cpu0.data 84398 # number of UpgradeReq accesses(hits+misses) 1403system.l2c.UpgradeReq_accesses::cpu1.data 78102 # number of UpgradeReq accesses(hits+misses) 1404system.l2c.UpgradeReq_accesses::total 162500 # number of UpgradeReq accesses(hits+misses) 1405system.l2c.SCUpgradeReq_accesses::cpu0.data 9307 # number of SCUpgradeReq accesses(hits+misses) 1406system.l2c.SCUpgradeReq_accesses::cpu1.data 8816 # number of SCUpgradeReq accesses(hits+misses) 1407system.l2c.SCUpgradeReq_accesses::total 18123 # number of SCUpgradeReq accesses(hits+misses) 1408system.l2c.ReadExReq_accesses::cpu0.data 583877 # number of ReadExReq accesses(hits+misses) 1409system.l2c.ReadExReq_accesses::cpu1.data 592932 # number of ReadExReq accesses(hits+misses) 1410system.l2c.ReadExReq_accesses::total 1176809 # number of ReadExReq accesses(hits+misses) 1411system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8766 # number of ReadSharedReq accesses(hits+misses) 1412system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6702 # number of ReadSharedReq accesses(hits+misses) 1413system.l2c.ReadSharedReq_accesses::cpu0.inst 496169 # number of ReadSharedReq accesses(hits+misses) 1414system.l2c.ReadSharedReq_accesses::cpu0.data 903530 # number of ReadSharedReq accesses(hits+misses) 1415system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8890 # number of ReadSharedReq accesses(hits+misses) 1416system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7124 # number of ReadSharedReq accesses(hits+misses) 1417system.l2c.ReadSharedReq_accesses::cpu1.inst 467189 # number of ReadSharedReq accesses(hits+misses) 1418system.l2c.ReadSharedReq_accesses::cpu1.data 872178 # number of ReadSharedReq accesses(hits+misses) 1419system.l2c.ReadSharedReq_accesses::total 2770548 # number of ReadSharedReq accesses(hits+misses) 1420system.l2c.InvalidateReq_accesses::cpu0.data 596200 # number of InvalidateReq accesses(hits+misses) 1421system.l2c.InvalidateReq_accesses::cpu1.data 266291 # number of InvalidateReq accesses(hits+misses) 1422system.l2c.InvalidateReq_accesses::total 862491 # number of InvalidateReq accesses(hits+misses) 1423system.l2c.demand_accesses::cpu0.dtb.walker 8766 # number of demand (read+write) accesses 1424system.l2c.demand_accesses::cpu0.itb.walker 6702 # number of demand (read+write) accesses 1425system.l2c.demand_accesses::cpu0.inst 496169 # number of demand (read+write) accesses 1426system.l2c.demand_accesses::cpu0.data 1487407 # number of demand (read+write) accesses 1427system.l2c.demand_accesses::cpu1.dtb.walker 8890 # number of demand (read+write) accesses 1428system.l2c.demand_accesses::cpu1.itb.walker 7124 # number of demand (read+write) accesses 1429system.l2c.demand_accesses::cpu1.inst 467189 # number of demand (read+write) accesses 1430system.l2c.demand_accesses::cpu1.data 1465110 # number of demand (read+write) accesses 1431system.l2c.demand_accesses::total 3947357 # number of demand (read+write) accesses 1432system.l2c.overall_accesses::cpu0.dtb.walker 8766 # number of overall (read+write) accesses 1433system.l2c.overall_accesses::cpu0.itb.walker 6702 # number of overall (read+write) accesses 1434system.l2c.overall_accesses::cpu0.inst 496169 # number of overall (read+write) accesses 1435system.l2c.overall_accesses::cpu0.data 1487407 # number of overall (read+write) accesses 1436system.l2c.overall_accesses::cpu1.dtb.walker 8890 # number of overall (read+write) accesses 1437system.l2c.overall_accesses::cpu1.itb.walker 7124 # number of overall (read+write) accesses 1438system.l2c.overall_accesses::cpu1.inst 467189 # number of overall (read+write) accesses 1439system.l2c.overall_accesses::cpu1.data 1465110 # number of overall (read+write) accesses 1440system.l2c.overall_accesses::total 3947357 # number of overall (read+write) accesses 1441system.l2c.UpgradeReq_miss_rate::cpu0.data 0.774651 # miss rate for UpgradeReq accesses 1442system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793040 # miss rate for UpgradeReq accesses 1443system.l2c.UpgradeReq_miss_rate::total 0.783489 # miss rate for UpgradeReq accesses 1444system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.716235 # miss rate for SCUpgradeReq accesses 1445system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720622 # miss rate for SCUpgradeReq accesses 1446system.l2c.SCUpgradeReq_miss_rate::total 0.718369 # miss rate for SCUpgradeReq accesses 1447system.l2c.ReadExReq_miss_rate::cpu0.data 0.660615 # miss rate for ReadExReq accesses 1448system.l2c.ReadExReq_miss_rate::cpu1.data 0.701182 # miss rate for ReadExReq accesses 1449system.l2c.ReadExReq_miss_rate::total 0.681054 # miss rate for ReadExReq accesses 1450system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for ReadSharedReq accesses 1451system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.306326 # miss rate for ReadSharedReq accesses 1452system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.116855 # miss rate for ReadSharedReq accesses 1453system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.199797 # miss rate for ReadSharedReq accesses 1454system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for ReadSharedReq accesses 1455system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.469540 # miss rate for ReadSharedReq accesses 1456system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087404 # miss rate for ReadSharedReq accesses 1457system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.214355 # miss rate for ReadSharedReq accesses 1458system.l2c.ReadSharedReq_miss_rate::total 0.172365 # miss rate for ReadSharedReq accesses 1459system.l2c.InvalidateReq_miss_rate::cpu0.data 0.800518 # miss rate for InvalidateReq accesses 1460system.l2c.InvalidateReq_miss_rate::cpu1.data 0.609837 # miss rate for InvalidateReq accesses 1461system.l2c.InvalidateReq_miss_rate::total 0.741646 # miss rate for InvalidateReq accesses 1462system.l2c.demand_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for demand accesses 1463system.l2c.demand_miss_rate::cpu0.itb.walker 0.306326 # miss rate for demand accesses 1464system.l2c.demand_miss_rate::cpu0.inst 0.116855 # miss rate for demand accesses 1465system.l2c.demand_miss_rate::cpu0.data 0.380690 # miss rate for demand accesses 1466system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for demand accesses 1467system.l2c.demand_miss_rate::cpu1.itb.walker 0.469540 # miss rate for demand accesses 1468system.l2c.demand_miss_rate::cpu1.inst 0.087404 # miss rate for demand accesses 1469system.l2c.demand_miss_rate::cpu1.data 0.411375 # miss rate for demand accesses 1470system.l2c.demand_miss_rate::total 0.324018 # miss rate for demand accesses 1471system.l2c.overall_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for overall accesses 1472system.l2c.overall_miss_rate::cpu0.itb.walker 0.306326 # miss rate for overall accesses 1473system.l2c.overall_miss_rate::cpu0.inst 0.116855 # miss rate for overall accesses 1474system.l2c.overall_miss_rate::cpu0.data 0.380690 # miss rate for overall accesses 1475system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for overall accesses 1476system.l2c.overall_miss_rate::cpu1.itb.walker 0.469540 # miss rate for overall accesses 1477system.l2c.overall_miss_rate::cpu1.inst 0.087404 # miss rate for overall accesses 1478system.l2c.overall_miss_rate::cpu1.data 0.411375 # miss rate for overall accesses 1479system.l2c.overall_miss_rate::total 0.324018 # miss rate for overall accesses 1480system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1481system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1482system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1483system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1484system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1485system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1486system.l2c.fast_writes 0 # number of fast writes performed 1487system.l2c.cache_copies 0 # number of cache copies performed 1488system.l2c.writebacks::writebacks 1473799 # number of writebacks 1489system.l2c.writebacks::total 1473799 # number of writebacks 1490system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1491system.membus.trans_dist::ReadReq 82185 # Transaction distribution 1492system.membus.trans_dist::ReadResp 568654 # Transaction distribution 1493system.membus.trans_dist::WriteReq 38847 # Transaction distribution 1494system.membus.trans_dist::WriteResp 38847 # Transaction distribution 1495system.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution 1496system.membus.trans_dist::CleanEvict 246676 # Transaction distribution 1497system.membus.trans_dist::UpgradeReq 346899 # Transaction distribution 1498system.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution 1499system.membus.trans_dist::UpgradeResp 162598 # Transaction distribution 1500system.membus.trans_dist::ReadExReq 787734 # Transaction distribution 1501system.membus.trans_dist::ReadExResp 783864 # Transaction distribution 1502system.membus.trans_dist::ReadSharedReq 486469 # Transaction distribution 1503system.membus.trans_dist::InvalidateReq 741739 # Transaction distribution 1504system.membus.trans_dist::InvalidateResp 741739 # Transaction distribution 1505system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) 1506system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 1507system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes) 1508system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6419962 # Packet count per connected master and slave (bytes) 1509system.membus.pkt_count_system.l2c.mem_side::total 6570380 # Packet count per connected master and slave (bytes) 1510system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes) 1511system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes) 1512system.membus.pkt_count::total 6917286 # Packet count per connected master and slave (bytes) 1513system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) 1514system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 1515system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes) 1516system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175247068 # Cumulative packet size per connected master and slave (bytes) 1517system.membus.pkt_size_system.l2c.mem_side::total 175458447 # Cumulative packet size per connected master and slave (bytes) 1518system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes) 1519system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes) 1520system.membus.pkt_size::total 182857999 # Cumulative packet size per connected master and slave (bytes) 1521system.membus.snoops 0 # Total snoops (count) 1522system.membus.snoop_fanout::samples 4621584 # Request fanout histogram 1523system.membus.snoop_fanout::mean 1 # Request fanout histogram 1524system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1525system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1526system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1527system.membus.snoop_fanout::1 4621584 100.00% 100.00% # Request fanout histogram 1528system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1529system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1530system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1531system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1532system.membus.snoop_fanout::total 4621584 # Request fanout histogram 1533system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1534system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1535system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1536system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1537system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1538system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1539system.realview.ethernet.txBytes 966 # Bytes Transmitted 1540system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1541system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1542system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1543system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1544system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1545system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1546system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1547system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1548system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 1549system.realview.ethernet.totPackets 3 # Total Packets 1550system.realview.ethernet.totBytes 966 # Total Bytes 1551system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1552system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 1553system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1554system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1555system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1556system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1557system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1558system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1559system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1560system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1561system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1562system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1563system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1564system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1565system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1566system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1567system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1568system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1569system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1570system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1571system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1572system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1573system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1574system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1575system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1576system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1577system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1578system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1579system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1580system.realview.ethernet.droppedPackets 0 # number of packets dropped 1581system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1582system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1583system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1584system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1585system.toL2Bus.snoop_filter.tot_requests 11149977 # Total number of requests made to the snoop filter. 1586system.toL2Bus.snoop_filter.hit_single_requests 5745476 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1587system.toL2Bus.snoop_filter.hit_multi_requests 1663139 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1588system.toL2Bus.snoop_filter.tot_snoops 131712 # Total number of snoops made to the snoop filter. 1589system.toL2Bus.snoop_filter.hit_single_snoops 118684 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1590system.toL2Bus.snoop_filter.hit_multi_snoops 13028 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1591system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution 1592system.toL2Bus.trans_dist::ReadResp 3554361 # Transaction distribution 1593system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution 1594system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution 1595system.toL2Bus.trans_dist::WritebackDirty 2757627 # Transaction distribution 1596system.toL2Bus.trans_dist::CleanEvict 2018256 # Transaction distribution 1597system.toL2Bus.trans_dist::UpgradeReq 359820 # Transaction distribution 1598system.toL2Bus.trans_dist::SCUpgradeReq 315646 # Transaction distribution 1599system.toL2Bus.trans_dist::UpgradeResp 675466 # Transaction distribution 1600system.toL2Bus.trans_dist::ReadExReq 1363961 # Transaction distribution 1601system.toL2Bus.trans_dist::ReadExResp 1363961 # Transaction distribution 1602system.toL2Bus.trans_dist::ReadSharedReq 3472174 # Transaction distribution 1603system.toL2Bus.trans_dist::InvalidateReq 862491 # Transaction distribution 1604system.toL2Bus.trans_dist::InvalidateResp 862491 # Transaction distribution 1605system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9530168 # Packet count per connected master and slave (bytes) 1606system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8235967 # Packet count per connected master and slave (bytes) 1607system.toL2Bus.pkt_count::total 17766135 # Packet count per connected master and slave (bytes) 1608system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255951612 # Cumulative packet size per connected master and slave (bytes) 1609system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 230454307 # Cumulative packet size per connected master and slave (bytes) 1610system.toL2Bus.pkt_size::total 486405919 # Cumulative packet size per connected master and slave (bytes) 1611system.toL2Bus.snoops 1999071 # Total snoops (count) 1612system.toL2Bus.snoop_fanout::samples 13268387 # Request fanout histogram 1613system.toL2Bus.snoop_fanout::mean 0.283691 # Request fanout histogram 1614system.toL2Bus.snoop_fanout::stdev 0.452962 # Request fanout histogram 1615system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1616system.toL2Bus.snoop_fanout::0 9517290 71.73% 71.73% # Request fanout histogram 1617system.toL2Bus.snoop_fanout::1 3738069 28.17% 99.90% # Request fanout histogram 1618system.toL2Bus.snoop_fanout::2 13028 0.10% 100.00% # Request fanout histogram 1619system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1620system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1621system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1622system.toL2Bus.snoop_fanout::total 13268387 # Request fanout histogram 1623 1624---------- End Simulation Statistics ---------- 1625