stats.txt revision 10616
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310726SN/Asim_seconds 47.177080 # Number of seconds simulated 410726SN/Asim_ticks 47177080006500 # Number of ticks simulated 510726SN/Afinal_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710944Sandreas.hansson@arm.comhost_inst_rate 1024538 # Simulator instruction rate (inst/s) 810944Sandreas.hansson@arm.comhost_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) 910944Sandreas.hansson@arm.comhost_tick_rate 49483118923 # Simulator tick rate (ticks/s) 1010944Sandreas.hansson@arm.comhost_mem_usage 669884 # Number of bytes of host memory used 1110944Sandreas.hansson@arm.comhost_seconds 953.40 # Real time elapsed on the host 1210726SN/Asim_insts 976792036 # Number of instructions simulated 1310726SN/Asim_ops 1149086878 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 149696 # Number of bytes read from this memory 1710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 124032 # Number of bytes read from this memory 1810892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3867700 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 35125336 # Number of bytes read from this memory 2010892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 224640 # Number of bytes read from this memory 2110892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 222848 # Number of bytes read from this memory 2210892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2692808 # Number of bytes read from this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 38798848 # Number of bytes read from this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 404992 # Number of bytes read from this memory 2510892Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 81610900 # Number of bytes read from this memory 2610892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3867700 # Number of instructions bytes read from this memory 2710892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2692808 # Number of instructions bytes read from this memory 2810892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory 2910892Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 100759808 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 3110585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3210892Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 100780624 # Number of bytes written to this memory 3310892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2339 # Number of read requests responded to by this memory 3410892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1938 # Number of read requests responded to by this memory 3510892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 100840 # Number of read requests responded to by this memory 3610892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 548855 # Number of read requests responded to by this memory 3710892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3510 # Number of read requests responded to by this memory 3810892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3482 # Number of read requests responded to by this memory 3910892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 42182 # Number of read requests responded to by this memory 4010892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 606250 # Number of read requests responded to by this memory 4110892Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6328 # Number of read requests responded to by this memory 4210892Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1315724 # Number of read requests responded to by this memory 4310892Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1574372 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 4510585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4610892Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1576975 # Number of write requests responded to by this memory 4710892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) 4810892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) 4910892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 81983 # Total read bandwidth from this memory (bytes/s) 5010892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 744542 # Total read bandwidth from this memory (bytes/s) 5110892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4762 # Total read bandwidth from this memory (bytes/s) 5210892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4724 # Total read bandwidth from this memory (bytes/s) 5310892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 57079 # Total read bandwidth from this memory (bytes/s) 5410892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 822409 # Total read bandwidth from this memory (bytes/s) 5510892Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8585 # Total read bandwidth from this memory (bytes/s) 5610892Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1729885 # Total read bandwidth from this memory (bytes/s) 5710892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 81983 # Instruction read bandwidth from this memory (bytes/s) 5810892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 57079 # Instruction read bandwidth from this memory (bytes/s) 5910892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 139061 # Instruction read bandwidth from this memory (bytes/s) 6010892Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2135779 # Write bandwidth from this memory (bytes/s) 6110827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) 6210585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6310892Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2136220 # Write bandwidth from this memory (bytes/s) 6410892Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2135779 # Total bandwidth to/from this memory (bytes/s) 6510892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) 6610892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) 6710892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 81983 # Total bandwidth to/from this memory (bytes/s) 6810892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 744984 # Total bandwidth to/from this memory (bytes/s) 6910892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4762 # Total bandwidth to/from this memory (bytes/s) 7010892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4724 # Total bandwidth to/from this memory (bytes/s) 7110892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 57079 # Total bandwidth to/from this memory (bytes/s) 7210892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 822409 # Total bandwidth to/from this memory (bytes/s) 7310892Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8585 # Total bandwidth to/from this memory (bytes/s) 7410892Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3866105 # Total bandwidth to/from this memory (bytes/s) 7510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 8910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10110585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10210585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10310585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10410585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 10510585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 10610585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 10710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 10810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 11210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 11310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 11610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 11710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12910585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 13010585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 13110585SN/Asystem.cpu0.dtb.read_hits 91355479 # DTB read hits 13210585SN/Asystem.cpu0.dtb.read_misses 87819 # DTB read misses 13310585SN/Asystem.cpu0.dtb.write_hits 84601943 # DTB write hits 13410585SN/Asystem.cpu0.dtb.write_misses 36095 # DTB write misses 13510585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 13610585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 13710726SN/Asystem.cpu0.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 13810726SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 13910726SN/Asystem.cpu0.dtb.flush_entries 36260 # Number of entries that have been flushed from TLB 14010726SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 14110726SN/Asystem.cpu0.dtb.prefetch_faults 5461 # Number of TLB faults due to prefetch 14210628SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 14310628SN/Asystem.cpu0.dtb.perms_faults 10344 # Number of TLB faults due to permissions restrictions 14410628SN/Asystem.cpu0.dtb.read_accesses 91443298 # DTB read accesses 14510726SN/Asystem.cpu0.dtb.write_accesses 84638038 # DTB write accesses 14610726SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 14710726SN/Asystem.cpu0.dtb.hits 175957422 # DTB hits 14810726SN/Asystem.cpu0.dtb.misses 123914 # DTB misses 14910628SN/Asystem.cpu0.dtb.accesses 176081336 # DTB accesses 15010726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 15110726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 15210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 15310726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 15410726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 15510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 15610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 15710726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 15810726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15910726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 16010726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 16110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 16210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 16310726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 16410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 16510726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 16610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 16710726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 16810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 16910726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 17010726SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 17110726SN/Asystem.cpu0.itb.inst_hits 491372488 # ITB inst hits 17210585SN/Asystem.cpu0.itb.inst_misses 60226 # ITB inst misses 17310726SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 17410726SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 17510726SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 17610628SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 17710628SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 17810628SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17910628SN/Asystem.cpu0.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 18010628SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 18110628SN/Asystem.cpu0.itb.flush_entries 25015 # Number of entries that have been flushed from TLB 18210628SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 18310628SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 18410585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 18510585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 18610585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 18710585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 18810585SN/Asystem.cpu0.itb.inst_accesses 491432714 # ITB inst accesses 18910585SN/Asystem.cpu0.itb.hits 491372488 # DTB hits 19010585SN/Asystem.cpu0.itb.misses 60226 # DTB misses 19110585SN/Asystem.cpu0.itb.accesses 491432714 # DTB accesses 19210585SN/Asystem.cpu0.numCycles 94354173207 # number of cpu cycles simulated 19310585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 19410585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 19510585SN/Asystem.cpu0.committedInsts 491139120 # Number of instructions committed 19610585SN/Asystem.cpu0.committedOps 577575160 # Number of ops (including micro ops) committed 19710585SN/Asystem.cpu0.num_int_alu_accesses 529301791 # Number of integer alu accesses 19810585SN/Asystem.cpu0.num_fp_alu_accesses 523058 # Number of float alu accesses 19910585SN/Asystem.cpu0.num_func_calls 28573576 # number of times a function call or return occured 20010585SN/Asystem.cpu0.num_conditional_control_insts 75495865 # number of instructions that are conditional controls 20110585SN/Asystem.cpu0.num_int_insts 529301791 # number of integer instructions 20210585SN/Asystem.cpu0.num_fp_insts 523058 # number of float instructions 20310585SN/Asystem.cpu0.num_int_register_reads 775565033 # number of times the integer registers were read 20410585SN/Asystem.cpu0.num_int_register_writes 419986522 # number of times the integer registers were written 20510726SN/Asystem.cpu0.num_fp_register_reads 843711 # number of times the floating registers were read 20610726SN/Asystem.cpu0.num_fp_register_writes 444676 # number of times the floating registers were written 20710726SN/Asystem.cpu0.num_cc_register_reads 132153354 # number of times the CC registers were read 20810726SN/Asystem.cpu0.num_cc_register_writes 131825344 # number of times the CC registers were written 20910726SN/Asystem.cpu0.num_mem_refs 176058068 # number of memory refs 21010628SN/Asystem.cpu0.num_load_insts 91428761 # Number of load instructions 21110628SN/Asystem.cpu0.num_store_insts 84629307 # Number of store instructions 21210628SN/Asystem.cpu0.num_idle_cycles 93776262262.183929 # Number of idle cycles 21310726SN/Asystem.cpu0.num_busy_cycles 577910944.816068 # Number of busy cycles 21410726SN/Asystem.cpu0.not_idle_fraction 0.006125 # Percentage of non-idle cycles 21510726SN/Asystem.cpu0.idle_fraction 0.993875 # Percentage of idle cycles 21610628SN/Asystem.cpu0.Branches 109891880 # Number of branches fetched 21710726SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 21810726SN/Asystem.cpu0.op_class::IntAlu 400497126 69.30% 69.30% # Class of executed instruction 21910628SN/Asystem.cpu0.op_class::IntMult 1218559 0.21% 69.51% # Class of executed instruction 22010726SN/Asystem.cpu0.op_class::IntDiv 59561 0.01% 69.52% # Class of executed instruction 22110726SN/Asystem.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 22210726SN/Asystem.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 22310726SN/Asystem.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 22410726SN/Asystem.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 22510585SN/Asystem.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 22610585SN/Asystem.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 22710585SN/Asystem.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 22810585SN/Asystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 22910585SN/Asystem.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 23010585SN/Asystem.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 23110726SN/Asystem.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 23210585SN/Asystem.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 23310726SN/Asystem.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 23410585SN/Asystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 23510585SN/Asystem.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 23610585SN/Asystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 23710585SN/Asystem.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 23810585SN/Asystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 23910585SN/Asystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 24010726SN/Asystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 24110726SN/Asystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 24210726SN/Asystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 24310726SN/Asystem.cpu0.op_class::SimdFloatMisc 73140 0.01% 69.54% # Class of executed instruction 24410726SN/Asystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction 24510585SN/Asystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction 24610585SN/Asystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction 24710726SN/Asystem.cpu0.op_class::MemRead 91428761 15.82% 85.36% # Class of executed instruction 24810726SN/Asystem.cpu0.op_class::MemWrite 84629307 14.64% 100.00% # Class of executed instruction 24910726SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 25010726SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 25110726SN/Asystem.cpu0.op_class::total 577906497 # Class of executed instruction 25210726SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 25310726SN/Asystem.cpu0.kern.inst.quiesce 13193 # number of quiesce instructions executed 25410726SN/Asystem.cpu0.dcache.tags.replacements 6189405 # number of replacements 25510726SN/Asystem.cpu0.dcache.tags.tagsinuse 506.263112 # Cycle average of tags in use 25610726SN/Asystem.cpu0.dcache.tags.total_refs 169698310 # Total number of references to valid blocks. 25710726SN/Asystem.cpu0.dcache.tags.sampled_refs 6189917 # Sample count of references to valid blocks. 25810726SN/Asystem.cpu0.dcache.tags.avg_refs 27.415280 # Average number of references to valid blocks. 25910726SN/Asystem.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. 26010726SN/Asystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.263112 # Average occupied blocks per requestor 26110726SN/Asystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988795 # Average percentage of cache occupancy 26210726SN/Asystem.cpu0.dcache.tags.occ_percent::total 0.988795 # Average percentage of cache occupancy 26310726SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 26410726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 26510726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id 26610726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 26710726SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 26810726SN/Asystem.cpu0.dcache.tags.tag_accesses 358274198 # Number of tag accesses 26910585SN/Asystem.cpu0.dcache.tags.data_accesses 358274198 # Number of data accesses 27010726SN/Asystem.cpu0.dcache.ReadReq_hits::cpu0.data 84971856 # number of ReadReq hits 27110726SN/Asystem.cpu0.dcache.ReadReq_hits::total 84971856 # number of ReadReq hits 27210726SN/Asystem.cpu0.dcache.WriteReq_hits::cpu0.data 79868150 # number of WriteReq hits 27310726SN/Asystem.cpu0.dcache.WriteReq_hits::total 79868150 # number of WriteReq hits 27410726SN/Asystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 214674 # number of SoftPFReq hits 27510726SN/Asystem.cpu0.dcache.SoftPFReq_hits::total 214674 # number of SoftPFReq hits 27610726SN/Asystem.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 260533 # number of WriteInvalidateReq hits 27710726SN/Asystem.cpu0.dcache.WriteInvalidateReq_hits::total 260533 # number of WriteInvalidateReq hits 27810726SN/Asystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2068908 # number of LoadLockedReq hits 27910726SN/Asystem.cpu0.dcache.LoadLockedReq_hits::total 2068908 # number of LoadLockedReq hits 28010726SN/Asystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028668 # number of StoreCondReq hits 28110726SN/Asystem.cpu0.dcache.StoreCondReq_hits::total 2028668 # number of StoreCondReq hits 28210726SN/Asystem.cpu0.dcache.demand_hits::cpu0.data 164840006 # number of demand (read+write) hits 28310726SN/Asystem.cpu0.dcache.demand_hits::total 164840006 # number of demand (read+write) hits 28410726SN/Asystem.cpu0.dcache.overall_hits::cpu0.data 165054680 # number of overall hits 28510726SN/Asystem.cpu0.dcache.overall_hits::total 165054680 # number of overall hits 28610726SN/Asystem.cpu0.dcache.ReadReq_misses::cpu0.data 3260277 # number of ReadReq misses 28710726SN/Asystem.cpu0.dcache.ReadReq_misses::total 3260277 # number of ReadReq misses 28810726SN/Asystem.cpu0.dcache.WriteReq_misses::cpu0.data 1458399 # number of WriteReq misses 28910726SN/Asystem.cpu0.dcache.WriteReq_misses::total 1458399 # number of WriteReq misses 29010726SN/Asystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 767112 # number of SoftPFReq misses 29110726SN/Asystem.cpu0.dcache.SoftPFReq_misses::total 767112 # number of SoftPFReq misses 29210726SN/Asystem.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 819206 # number of WriteInvalidateReq misses 29310726SN/Asystem.cpu0.dcache.WriteInvalidateReq_misses::total 819206 # number of WriteInvalidateReq misses 29410726SN/Asystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 116959 # number of LoadLockedReq misses 29510726SN/Asystem.cpu0.dcache.LoadLockedReq_misses::total 116959 # number of LoadLockedReq misses 29610726SN/Asystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 156094 # number of StoreCondReq misses 29710726SN/Asystem.cpu0.dcache.StoreCondReq_misses::total 156094 # number of StoreCondReq misses 29810726SN/Asystem.cpu0.dcache.demand_misses::cpu0.data 4718676 # number of demand (read+write) misses 29910726SN/Asystem.cpu0.dcache.demand_misses::total 4718676 # number of demand (read+write) misses 30010726SN/Asystem.cpu0.dcache.overall_misses::cpu0.data 5485788 # number of overall misses 30110585SN/Asystem.cpu0.dcache.overall_misses::total 5485788 # number of overall misses 30210585SN/Asystem.cpu0.dcache.ReadReq_accesses::cpu0.data 88232133 # number of ReadReq accesses(hits+misses) 30310726SN/Asystem.cpu0.dcache.ReadReq_accesses::total 88232133 # number of ReadReq accesses(hits+misses) 30410585SN/Asystem.cpu0.dcache.WriteReq_accesses::cpu0.data 81326549 # number of WriteReq accesses(hits+misses) 30510726SN/Asystem.cpu0.dcache.WriteReq_accesses::total 81326549 # number of WriteReq accesses(hits+misses) 30610827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 981786 # number of SoftPFReq accesses(hits+misses) 30710726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::total 981786 # number of SoftPFReq accesses(hits+misses) 30810827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079739 # number of WriteInvalidateReq accesses(hits+misses) 30910827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::total 1079739 # number of WriteInvalidateReq accesses(hits+misses) 31010827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185867 # number of LoadLockedReq accesses(hits+misses) 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2185867 # number of LoadLockedReq accesses(hits+misses) 31210726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184762 # number of StoreCondReq accesses(hits+misses) 31310726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::total 2184762 # number of StoreCondReq accesses(hits+misses) 31410726SN/Asystem.cpu0.dcache.demand_accesses::cpu0.data 169558682 # number of demand (read+write) accesses 31510585SN/Asystem.cpu0.dcache.demand_accesses::total 169558682 # number of demand (read+write) accesses 31610726SN/Asystem.cpu0.dcache.overall_accesses::cpu0.data 170540468 # number of overall (read+write) accesses 31710726SN/Asystem.cpu0.dcache.overall_accesses::total 170540468 # number of overall (read+write) accesses 31810726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036951 # miss rate for ReadReq accesses 31910585SN/Asystem.cpu0.dcache.ReadReq_miss_rate::total 0.036951 # miss rate for ReadReq accesses 32010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017933 # miss rate for WriteReq accesses 32110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.017933 # miss rate for WriteReq accesses 32210892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781343 # miss rate for SoftPFReq accesses 32310892Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781343 # miss rate for SoftPFReq accesses 32410892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.758707 # miss rate for WriteInvalidateReq accesses 32510892Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.758707 # miss rate for WriteInvalidateReq accesses 32610827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053507 # miss rate for LoadLockedReq accesses 32710827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053507 # miss rate for LoadLockedReq accesses 32810892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071447 # miss rate for StoreCondReq accesses 32910892Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.071447 # miss rate for StoreCondReq accesses 33010892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027829 # miss rate for demand accesses 33110892Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027829 # miss rate for demand accesses 33210892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032167 # miss rate for overall accesses 33310892Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032167 # miss rate for overall accesses 33410892Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 33510892Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 33610892Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 33710892Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 33810892Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 33910892Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 34010892Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 34110892Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 34210827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 4407988 # number of writebacks 34310827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 4407988 # number of writebacks 34410892Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 34510892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5467768 # number of replacements 34610892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use 34710892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 485959047 # Total number of references to valid blocks. 34810892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5468280 # Sample count of references to valid blocks. 34910892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 88.868721 # Average number of references to valid blocks. 35010892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 35110892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor 35210892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 35310892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 35410827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 35510827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id 35610827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 35710827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 35810726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 35910726SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 36010892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 988322949 # Number of tag accesses 36110892Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 988322949 # Number of data accesses 36210726SN/Asystem.cpu0.icache.ReadReq_hits::cpu0.inst 485959047 # number of ReadReq hits 36310726SN/Asystem.cpu0.icache.ReadReq_hits::total 485959047 # number of ReadReq hits 36410726SN/Asystem.cpu0.icache.demand_hits::cpu0.inst 485959047 # number of demand (read+write) hits 36510726SN/Asystem.cpu0.icache.demand_hits::total 485959047 # number of demand (read+write) hits 36610827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 485959047 # number of overall hits 36710827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 485959047 # number of overall hits 36810827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5468285 # number of ReadReq misses 36910827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5468285 # number of ReadReq misses 37010726SN/Asystem.cpu0.icache.demand_misses::cpu0.inst 5468285 # number of demand (read+write) misses 37110726SN/Asystem.cpu0.icache.demand_misses::total 5468285 # number of demand (read+write) misses 37210827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5468285 # number of overall misses 37310827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5468285 # number of overall misses 37410827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 491427332 # number of ReadReq accesses(hits+misses) 37510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 491427332 # number of ReadReq accesses(hits+misses) 37610892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 491427332 # number of demand (read+write) accesses 37710892Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 491427332 # number of demand (read+write) accesses 37810726SN/Asystem.cpu0.icache.overall_accesses::cpu0.inst 491427332 # number of overall (read+write) accesses 37910726SN/Asystem.cpu0.icache.overall_accesses::total 491427332 # number of overall (read+write) accesses 38010892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011127 # miss rate for ReadReq accesses 38110892Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011127 # miss rate for ReadReq accesses 38210827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011127 # miss rate for demand accesses 38310827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011127 # miss rate for demand accesses 38410892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011127 # miss rate for overall accesses 38510892Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011127 # miss rate for overall accesses 38610585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 38910585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 39010585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39210585SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 39310585SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 39410892Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 39510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 39610585SN/Asystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 39710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 39810726SN/Asystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 39910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 40010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 40110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 40210585SN/Asystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 40310726SN/Asystem.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 40410585SN/Asystem.cpu0.l2cache.tags.replacements 2648971 # number of replacements 40510585SN/Asystem.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use 40610585SN/Asystem.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. 40710726SN/Asystem.cpu0.l2cache.tags.sampled_refs 2665005 # Sample count of references to valid blocks. 40810726SN/Asystem.cpu0.l2cache.tags.avg_refs 4.283598 # Average number of references to valid blocks. 40910726SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 41010585SN/Asystem.cpu0.l2cache.tags.occ_blocks::writebacks 5428.449185 # Average occupied blocks per requestor 41110585SN/Asystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.127041 # Average occupied blocks per requestor 41210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.911966 # Average occupied blocks per requestor 41310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4608.843039 # Average occupied blocks per requestor 41410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 6080.573004 # Average occupied blocks per requestor 41510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.331326 # Average percentage of cache occupancy 41610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003060 # Average percentage of cache occupancy 41710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003168 # Average percentage of cache occupancy 41810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.281301 # Average percentage of cache occupancy 41910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.371129 # Average percentage of cache occupancy 42010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.989984 # Average percentage of cache occupancy 42110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id 42210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15969 # Occupied blocks per task id 42310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 42410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 50 # Occupied blocks per task id 42510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 42610726SN/Asystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 42710726SN/Asystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 42810726SN/Asystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1130 # Occupied blocks per task id 42910726SN/Asystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4626 # Occupied blocks per task id 43010726SN/Asystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id 43110726SN/Asystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4547 # Occupied blocks per task id 43210726SN/Asystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id 43310726SN/Asystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.974670 # Percentage of cache occupancy per task id 43410726SN/Asystem.cpu0.l2cache.tags.tag_accesses 274915962 # Number of tag accesses 43510726SN/Asystem.cpu0.l2cache.tags.data_accesses 274915962 # Number of data accesses 43610726SN/Asystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 266204 # number of ReadReq hits 43710726SN/Asystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 139155 # number of ReadReq hits 43810585SN/Asystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 4917807 # number of ReadReq hits 43910585SN/Asystem.cpu0.l2cache.ReadReq_hits::cpu0.data 2910870 # number of ReadReq hits 44010585SN/Asystem.cpu0.l2cache.ReadReq_hits::total 8234036 # number of ReadReq hits 44110585SN/Asystem.cpu0.l2cache.Writeback_hits::writebacks 4407988 # number of Writeback hits 44210585SN/Asystem.cpu0.l2cache.Writeback_hits::total 4407988 # number of Writeback hits 44310585SN/Asystem.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 219663 # number of WriteInvalidateReq hits 44410585SN/Asystem.cpu0.l2cache.WriteInvalidateReq_hits::total 219663 # number of WriteInvalidateReq hits 44510585SN/Asystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3562 # number of UpgradeReq hits 44610585SN/Asystem.cpu0.l2cache.UpgradeReq_hits::total 3562 # number of UpgradeReq hits 44710628SN/Asystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 630387 # number of ReadExReq hits 44810628SN/Asystem.cpu0.l2cache.ReadExReq_hits::total 630387 # number of ReadExReq hits 44910628SN/Asystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 266204 # number of demand (read+write) hits 45010628SN/Asystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 139155 # number of demand (read+write) hits 45110628SN/Asystem.cpu0.l2cache.demand_hits::cpu0.inst 4917807 # number of demand (read+write) hits 45210628SN/Asystem.cpu0.l2cache.demand_hits::cpu0.data 3541257 # number of demand (read+write) hits 45310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8864423 # number of demand (read+write) hits 45410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 266204 # number of overall hits 45510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 139155 # number of overall hits 45610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4917807 # number of overall hits 45710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3541257 # number of overall hits 45810585SN/Asystem.cpu0.l2cache.overall_hits::total 8864423 # number of overall hits 45910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10959 # number of ReadReq misses 46010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8288 # number of ReadReq misses 46110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 550478 # number of ReadReq misses 46210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 1233478 # number of ReadReq misses 46310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 1803203 # number of ReadReq misses 46410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 599179 # number of WriteInvalidateReq misses 46510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::total 599179 # number of WriteInvalidateReq misses 46610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 125865 # number of UpgradeReq misses 46710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 125865 # number of UpgradeReq misses 46810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156094 # number of SCUpgradeReq misses 46910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 156094 # number of SCUpgradeReq misses 47010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 698949 # number of ReadExReq misses 47110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 698949 # number of ReadExReq misses 47210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10959 # number of demand (read+write) misses 47310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8288 # number of demand (read+write) misses 47410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 550478 # number of demand (read+write) misses 47510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1932427 # number of demand (read+write) misses 47610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2502152 # number of demand (read+write) misses 47710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10959 # number of overall misses 47810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8288 # number of overall misses 47910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 550478 # number of overall misses 48010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1932427 # number of overall misses 48110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2502152 # number of overall misses 48210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277163 # number of ReadReq accesses(hits+misses) 48310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 147443 # number of ReadReq accesses(hits+misses) 48410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5468285 # number of ReadReq accesses(hits+misses) 48510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 4144348 # number of ReadReq accesses(hits+misses) 48610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 10037239 # number of ReadReq accesses(hits+misses) 48710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 4407988 # number of Writeback accesses(hits+misses) 48810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 4407988 # number of Writeback accesses(hits+misses) 48910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 818842 # number of WriteInvalidateReq accesses(hits+misses) 49010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::total 818842 # number of WriteInvalidateReq accesses(hits+misses) 49110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 129427 # number of UpgradeReq accesses(hits+misses) 49210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 129427 # number of UpgradeReq accesses(hits+misses) 49310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156094 # number of SCUpgradeReq accesses(hits+misses) 49410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 156094 # number of SCUpgradeReq accesses(hits+misses) 49510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1329336 # number of ReadExReq accesses(hits+misses) 49610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1329336 # number of ReadExReq accesses(hits+misses) 49710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277163 # number of demand (read+write) accesses 49810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 147443 # number of demand (read+write) accesses 49910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5468285 # number of demand (read+write) accesses 50010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5473684 # number of demand (read+write) accesses 50110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11366575 # number of demand (read+write) accesses 50210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277163 # number of overall (read+write) accesses 50310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 147443 # number of overall (read+write) accesses 50410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5468285 # number of overall (read+write) accesses 50510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5473684 # number of overall (read+write) accesses 50610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11366575 # number of overall (read+write) accesses 50710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for ReadReq accesses 50810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056212 # miss rate for ReadReq accesses 50910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.100667 # miss rate for ReadReq accesses 51010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.297629 # miss rate for ReadReq accesses 51110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.179651 # miss rate for ReadReq accesses 51210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731739 # miss rate for WriteInvalidateReq accesses 51310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731739 # miss rate for WriteInvalidateReq accesses 51410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.972479 # miss rate for UpgradeReq accesses 51510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.972479 # miss rate for UpgradeReq accesses 51610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 51710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 51810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525788 # miss rate for ReadExReq accesses 51910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.525788 # miss rate for ReadExReq accesses 52010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for demand accesses 52110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056212 # miss rate for demand accesses 52210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100667 # miss rate for demand accesses 52310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.353040 # miss rate for demand accesses 52410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.220132 # miss rate for demand accesses 52510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for overall accesses 52610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056212 # miss rate for overall accesses 52710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100667 # miss rate for overall accesses 52810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.353040 # miss rate for overall accesses 52910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.220132 # miss rate for overall accesses 53010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 53110892Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 53210892Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 53310892Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 53410892Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 53510892Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 53610892Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 53710892Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 53810892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1542533 # number of writebacks 53910892Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1542533 # number of writebacks 54010892Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 54110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 10228504 # Transaction distribution 54210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10228504 # Transaction distribution 54310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32523 # Transaction distribution 54410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32523 # Transaction distribution 54510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 4407988 # Transaction distribution 54610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 818842 # Transaction distribution 54710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 818842 # Transaction distribution 54810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 129427 # Transaction distribution 54910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156094 # Transaction distribution 55010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 285521 # Transaction distribution 55110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1329336 # Transaction distribution 55210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1329336 # Transaction distribution 55310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11022820 # Packet count per connected master and slave (bytes) 55410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17694214 # Packet count per connected master and slave (bytes) 55510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 359792 # Packet count per connected master and slave (bytes) 55610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 720614 # Packet count per connected master and slave (bytes) 55710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 29797440 # Packet count per connected master and slave (bytes) 55810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350142740 # Cumulative packet size per connected master and slave (bytes) 55910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 685026670 # Cumulative packet size per connected master and slave (bytes) 56010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) 56110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2882456 # Cumulative packet size per connected master and slave (bytes) 56210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1039491034 # Cumulative packet size per connected master and slave (bytes) 56310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 3383860 # Total snoops (count) 56410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 20196192 # Request fanout histogram 56510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 5.158528 # Request fanout histogram 56610585SN/Asystem.cpu0.toL2Bus.snoop_fanout::stdev 0.365236 # Request fanout histogram 56710585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 56810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 56910892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 57010892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 57110892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 57210892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 57310892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::5 16994523 84.15% 84.15% # Request fanout histogram 57410892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::6 3201669 15.85% 100.00% # Request fanout histogram 57510892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 57610892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 57710892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 57810892Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram 57910892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 58010892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58110892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 58210892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 58310892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 58410892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 58510892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 58610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 58810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 59110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 59210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 59310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59410892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 59510892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 59610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59710892Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 59810827Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 59910827Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 60010827Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 60110892Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 60210892Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 91720002 # DTB read hits 60310892Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 112244 # DTB read misses 60410892Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 82499013 # DTB write hits 60510892Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 32608 # DTB write misses 60610892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 60710892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 60810892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 60910892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 61010892Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 45118 # Number of entries that have been flushed from TLB 61110892Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 61210892Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4542 # Number of TLB faults due to prefetch 61310892Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 61410726SN/Asystem.cpu1.dtb.perms_faults 11534 # Number of TLB faults due to permissions restrictions 61510726SN/Asystem.cpu1.dtb.read_accesses 91832246 # DTB read accesses 61610892Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 82531621 # DTB write accesses 61710892Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 61810892Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 174219015 # DTB hits 61910726SN/Asystem.cpu1.dtb.misses 144852 # DTB misses 62010726SN/Asystem.cpu1.dtb.accesses 174363867 # DTB accesses 62110892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 62210892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 62310892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 62410892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 62510892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 62610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 62810892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 62910892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 63010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 63110827Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 63210827Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 63310892Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 63510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 63810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 63910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 64010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 64110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 64210585SN/Asystem.cpu1.itb.inst_hits 485906850 # ITB inst hits 64310585SN/Asystem.cpu1.itb.inst_misses 61939 # ITB inst misses 64410585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 64510585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 64610585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 64710585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 64810585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 64910585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 65010585SN/Asystem.cpu1.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID 65110585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 65210585SN/Asystem.cpu1.itb.flush_entries 31863 # Number of entries that have been flushed from TLB 65310585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 65410585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 65510585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65610585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65710585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 65810585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 65910585SN/Asystem.cpu1.itb.inst_accesses 485968789 # ITB inst accesses 66010585SN/Asystem.cpu1.itb.hits 485906850 # DTB hits 66110585SN/Asystem.cpu1.itb.misses 61939 # DTB misses 66210585SN/Asystem.cpu1.itb.accesses 485968789 # DTB accesses 66310726SN/Asystem.cpu1.numCycles 94354166192 # number of cpu cycles simulated 66410726SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 66510726SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 66610726SN/Asystem.cpu1.committedInsts 485652916 # Number of instructions committed 66710726SN/Asystem.cpu1.committedOps 571511718 # Number of ops (including micro ops) committed 66810628SN/Asystem.cpu1.num_int_alu_accesses 524558211 # Number of integer alu accesses 66910628SN/Asystem.cpu1.num_fp_alu_accesses 375128 # Number of float alu accesses 67010628SN/Asystem.cpu1.num_func_calls 28666071 # number of times a function call or return occured 67110726SN/Asystem.cpu1.num_conditional_control_insts 74347572 # number of instructions that are conditional controls 67210726SN/Asystem.cpu1.num_int_insts 524558211 # number of integer instructions 67310726SN/Asystem.cpu1.num_fp_insts 375128 # number of float instructions 67410726SN/Asystem.cpu1.num_int_register_reads 774388464 # number of times the integer registers were read 67510628SN/Asystem.cpu1.num_int_register_writes 417530639 # number of times the integer registers were written 67610726SN/Asystem.cpu1.num_fp_register_reads 610571 # number of times the floating registers were read 67710726SN/Asystem.cpu1.num_fp_register_writes 303256 # number of times the floating registers were written 67810628SN/Asystem.cpu1.num_cc_register_reads 128278137 # number of times the CC registers were read 67910726SN/Asystem.cpu1.num_cc_register_writes 127991607 # number of times the CC registers were written 68010726SN/Asystem.cpu1.num_mem_refs 174340371 # number of memory refs 68110585SN/Asystem.cpu1.num_load_insts 91819242 # Number of load instructions 68210585SN/Asystem.cpu1.num_store_insts 82521129 # Number of store instructions 68310726SN/Asystem.cpu1.num_idle_cycles 93782340058.888657 # Number of idle cycles 68410726SN/Asystem.cpu1.num_busy_cycles 571826133.111340 # Number of busy cycles 68510726SN/Asystem.cpu1.not_idle_fraction 0.006060 # Percentage of non-idle cycles 68610726SN/Asystem.cpu1.idle_fraction 0.993940 # Percentage of idle cycles 68710585SN/Asystem.cpu1.Branches 108195111 # Number of branches fetched 68810585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 68910726SN/Asystem.cpu1.op_class::IntAlu 396230726 69.29% 69.29% # Class of executed instruction 69010585SN/Asystem.cpu1.op_class::IntMult 1151823 0.20% 69.49% # Class of executed instruction 69110726SN/Asystem.cpu1.op_class::IntDiv 61886 0.01% 69.51% # Class of executed instruction 69210585SN/Asystem.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 69310726SN/Asystem.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 69410585SN/Asystem.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction 69510726SN/Asystem.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction 69610726SN/Asystem.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction 69710726SN/Asystem.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 69810585SN/Asystem.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 69910726SN/Asystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 70010726SN/Asystem.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 70110726SN/Asystem.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 70210628SN/Asystem.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 70310628SN/Asystem.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 70410628SN/Asystem.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 70510628SN/Asystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 70610628SN/Asystem.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 70710628SN/Asystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 70810628SN/Asystem.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 70910628SN/Asystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction 71010585SN/Asystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 71110585SN/Asystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction 71210585SN/Asystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction 71310585SN/Asystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 71410585SN/Asystem.cpu1.op_class::SimdFloatMisc 36426 0.01% 69.51% # Class of executed instruction 71510585SN/Asystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 71610585SN/Asystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 71710585SN/Asystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 71810585SN/Asystem.cpu1.op_class::MemRead 91819242 16.06% 85.57% # Class of executed instruction 71910585SN/Asystem.cpu1.op_class::MemWrite 82521129 14.43% 100.00% # Class of executed instruction 72010585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 72110585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 72210585SN/Asystem.cpu1.op_class::total 571821232 # Class of executed instruction 72310585SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 72410585SN/Asystem.cpu1.kern.inst.quiesce 6178 # number of quiesce instructions executed 72510585SN/Asystem.cpu1.dcache.tags.replacements 6025220 # number of replacements 72610585SN/Asystem.cpu1.dcache.tags.tagsinuse 443.938244 # Cycle average of tags in use 72710585SN/Asystem.cpu1.dcache.tags.total_refs 168203685 # Total number of references to valid blocks. 72810585SN/Asystem.cpu1.dcache.tags.sampled_refs 6025731 # Sample count of references to valid blocks. 72910585SN/Asystem.cpu1.dcache.tags.avg_refs 27.914237 # Average number of references to valid blocks. 73010585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 73110726SN/Asystem.cpu1.dcache.tags.occ_blocks::cpu1.data 443.938244 # Average occupied blocks per requestor 73210726SN/Asystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.867067 # Average percentage of cache occupancy 73310726SN/Asystem.cpu1.dcache.tags.occ_percent::total 0.867067 # Average percentage of cache occupancy 73410726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 73510726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 73610628SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id 73710628SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 73810628SN/Asystem.cpu1.dcache.tags.tag_accesses 354758936 # Number of tag accesses 73910726SN/Asystem.cpu1.dcache.tags.data_accesses 354758936 # Number of data accesses 74010726SN/Asystem.cpu1.dcache.ReadReq_hits::cpu1.data 85201700 # number of ReadReq hits 74110726SN/Asystem.cpu1.dcache.ReadReq_hits::total 85201700 # number of ReadReq hits 74210628SN/Asystem.cpu1.dcache.WriteReq_hits::cpu1.data 78314445 # number of WriteReq hits 74310726SN/Asystem.cpu1.dcache.WriteReq_hits::total 78314445 # number of WriteReq hits 74410726SN/Asystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 188411 # number of SoftPFReq hits 74510628SN/Asystem.cpu1.dcache.SoftPFReq_hits::total 188411 # number of SoftPFReq hits 74610726SN/Asystem.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 65692 # number of WriteInvalidateReq hits 74710726SN/Asystem.cpu1.dcache.WriteInvalidateReq_hits::total 65692 # number of WriteInvalidateReq hits 74810726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2073864 # number of LoadLockedReq hits 74910726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::total 2073864 # number of LoadLockedReq hits 75010726SN/Asystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2064069 # number of StoreCondReq hits 75110585SN/Asystem.cpu1.dcache.StoreCondReq_hits::total 2064069 # number of StoreCondReq hits 75210585SN/Asystem.cpu1.dcache.demand_hits::cpu1.data 163516145 # number of demand (read+write) hits 75310585SN/Asystem.cpu1.dcache.demand_hits::total 163516145 # number of demand (read+write) hits 75410585SN/Asystem.cpu1.dcache.overall_hits::cpu1.data 163704556 # number of overall hits 75510585SN/Asystem.cpu1.dcache.overall_hits::total 163704556 # number of overall hits 75610585SN/Asystem.cpu1.dcache.ReadReq_misses::cpu1.data 3403274 # number of ReadReq misses 75710726SN/Asystem.cpu1.dcache.ReadReq_misses::total 3403274 # number of ReadReq misses 75810585SN/Asystem.cpu1.dcache.WriteReq_misses::cpu1.data 1467363 # number of WriteReq misses 75910726SN/Asystem.cpu1.dcache.WriteReq_misses::total 1467363 # number of WriteReq misses 76010585SN/Asystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 796168 # number of SoftPFReq misses 76110585SN/Asystem.cpu1.dcache.SoftPFReq_misses::total 796168 # number of SoftPFReq misses 76210585SN/Asystem.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 438523 # number of WriteInvalidateReq misses 76310585SN/Asystem.cpu1.dcache.WriteInvalidateReq_misses::total 438523 # number of WriteInvalidateReq misses 76410585SN/Asystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 149383 # number of LoadLockedReq misses 76510585SN/Asystem.cpu1.dcache.LoadLockedReq_misses::total 149383 # number of LoadLockedReq misses 76610726SN/Asystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 157982 # number of StoreCondReq misses 76710726SN/Asystem.cpu1.dcache.StoreCondReq_misses::total 157982 # number of StoreCondReq misses 76810726SN/Asystem.cpu1.dcache.demand_misses::cpu1.data 4870637 # number of demand (read+write) misses 76910726SN/Asystem.cpu1.dcache.demand_misses::total 4870637 # number of demand (read+write) misses 77010726SN/Asystem.cpu1.dcache.overall_misses::cpu1.data 5666805 # number of overall misses 77110585SN/Asystem.cpu1.dcache.overall_misses::total 5666805 # number of overall misses 77210585SN/Asystem.cpu1.dcache.ReadReq_accesses::cpu1.data 88604974 # number of ReadReq accesses(hits+misses) 77310726SN/Asystem.cpu1.dcache.ReadReq_accesses::total 88604974 # number of ReadReq accesses(hits+misses) 77410726SN/Asystem.cpu1.dcache.WriteReq_accesses::cpu1.data 79781808 # number of WriteReq accesses(hits+misses) 77510726SN/Asystem.cpu1.dcache.WriteReq_accesses::total 79781808 # number of WriteReq accesses(hits+misses) 77610726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 984579 # number of SoftPFReq accesses(hits+misses) 77710726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::total 984579 # number of SoftPFReq accesses(hits+misses) 77810726SN/Asystem.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 504215 # number of WriteInvalidateReq accesses(hits+misses) 77910726SN/Asystem.cpu1.dcache.WriteInvalidateReq_accesses::total 504215 # number of WriteInvalidateReq accesses(hits+misses) 78010726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2223247 # number of LoadLockedReq accesses(hits+misses) 78110726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::total 2223247 # number of LoadLockedReq accesses(hits+misses) 78210726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2222051 # number of StoreCondReq accesses(hits+misses) 78310726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::total 2222051 # number of StoreCondReq accesses(hits+misses) 78410726SN/Asystem.cpu1.dcache.demand_accesses::cpu1.data 168386782 # number of demand (read+write) accesses 78510726SN/Asystem.cpu1.dcache.demand_accesses::total 168386782 # number of demand (read+write) accesses 78610726SN/Asystem.cpu1.dcache.overall_accesses::cpu1.data 169371361 # number of overall (read+write) accesses 78710726SN/Asystem.cpu1.dcache.overall_accesses::total 169371361 # number of overall (read+write) accesses 78810726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038410 # miss rate for ReadReq accesses 78910726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::total 0.038410 # miss rate for ReadReq accesses 79010726SN/Asystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018392 # miss rate for WriteReq accesses 79110726SN/Asystem.cpu1.dcache.WriteReq_miss_rate::total 0.018392 # miss rate for WriteReq accesses 79210726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808638 # miss rate for SoftPFReq accesses 79310726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.808638 # miss rate for SoftPFReq accesses 79410726SN/Asystem.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.869714 # miss rate for WriteInvalidateReq accesses 79510585SN/Asystem.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.869714 # miss rate for WriteInvalidateReq accesses 79610726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067191 # miss rate for LoadLockedReq accesses 79710726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067191 # miss rate for LoadLockedReq accesses 79810726SN/Asystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071097 # miss rate for StoreCondReq accesses 79910726SN/Asystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.071097 # miss rate for StoreCondReq accesses 80010726SN/Asystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.028925 # miss rate for demand accesses 80110726SN/Asystem.cpu1.dcache.demand_miss_rate::total 0.028925 # miss rate for demand accesses 80210726SN/Asystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.033458 # miss rate for overall accesses 80310726SN/Asystem.cpu1.dcache.overall_miss_rate::total 0.033458 # miss rate for overall accesses 80410726SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80510726SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 80610726SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 80710726SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 80810726SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80910726SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81010726SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 81110726SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 81210726SN/Asystem.cpu1.dcache.writebacks::writebacks 4091318 # number of writebacks 81310726SN/Asystem.cpu1.dcache.writebacks::total 4091318 # number of writebacks 81410726SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 81510726SN/Asystem.cpu1.icache.tags.replacements 4818195 # number of replacements 81610726SN/Asystem.cpu1.icache.tags.tagsinuse 496.412963 # Cycle average of tags in use 81710726SN/Asystem.cpu1.icache.tags.total_refs 481143593 # Total number of references to valid blocks. 81810726SN/Asystem.cpu1.icache.tags.sampled_refs 4818707 # Sample count of references to valid blocks. 81910726SN/Asystem.cpu1.icache.tags.avg_refs 99.849107 # Average number of references to valid blocks. 82010726SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 82110726SN/Asystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412963 # Average occupied blocks per requestor 82210726SN/Asystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy 82310726SN/Asystem.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy 82410726SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 82510726SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 82610726SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 82710585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id 82810585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 82910726SN/Asystem.cpu1.icache.tags.tag_accesses 976743307 # Number of tag accesses 83010585SN/Asystem.cpu1.icache.tags.data_accesses 976743307 # Number of data accesses 83110726SN/Asystem.cpu1.icache.ReadReq_hits::cpu1.inst 481143593 # number of ReadReq hits 83210726SN/Asystem.cpu1.icache.ReadReq_hits::total 481143593 # number of ReadReq hits 83310726SN/Asystem.cpu1.icache.demand_hits::cpu1.inst 481143593 # number of demand (read+write) hits 83410726SN/Asystem.cpu1.icache.demand_hits::total 481143593 # number of demand (read+write) hits 83510726SN/Asystem.cpu1.icache.overall_hits::cpu1.inst 481143593 # number of overall hits 83610726SN/Asystem.cpu1.icache.overall_hits::total 481143593 # number of overall hits 83710585SN/Asystem.cpu1.icache.ReadReq_misses::cpu1.inst 4818707 # number of ReadReq misses 83810726SN/Asystem.cpu1.icache.ReadReq_misses::total 4818707 # number of ReadReq misses 83910726SN/Asystem.cpu1.icache.demand_misses::cpu1.inst 4818707 # number of demand (read+write) misses 84010726SN/Asystem.cpu1.icache.demand_misses::total 4818707 # number of demand (read+write) misses 84110726SN/Asystem.cpu1.icache.overall_misses::cpu1.inst 4818707 # number of overall misses 84210726SN/Asystem.cpu1.icache.overall_misses::total 4818707 # number of overall misses 84310726SN/Asystem.cpu1.icache.ReadReq_accesses::cpu1.inst 485962300 # number of ReadReq accesses(hits+misses) 84410726SN/Asystem.cpu1.icache.ReadReq_accesses::total 485962300 # number of ReadReq accesses(hits+misses) 84510726SN/Asystem.cpu1.icache.demand_accesses::cpu1.inst 485962300 # number of demand (read+write) accesses 84610726SN/Asystem.cpu1.icache.demand_accesses::total 485962300 # number of demand (read+write) accesses 84710726SN/Asystem.cpu1.icache.overall_accesses::cpu1.inst 485962300 # number of overall (read+write) accesses 84810726SN/Asystem.cpu1.icache.overall_accesses::total 485962300 # number of overall (read+write) accesses 84910726SN/Asystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses 85010892Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses 85110892Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses 85210726SN/Asystem.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses 85310726SN/Asystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses 85410892Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses 85510892Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85610726SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85710726SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 85810892Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 85910892Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 86010892Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86110892Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 86210892Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 86310892Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 86410726SN/Asystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 86510726SN/Asystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 86610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 86710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 86810726SN/Asystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 86910726SN/Asystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 87010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 87110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 87210726SN/Asystem.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 87310726SN/Asystem.cpu1.l2cache.tags.replacements 2333825 # number of replacements 87410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use 87510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. 87610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2349876 # Sample count of references to valid blocks. 87710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.683889 # Average number of references to valid blocks. 87810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9726491548000 # Cycle when the warmup percentage was hit. 87910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5253.379361 # Average occupied blocks per requestor 88010726SN/Asystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.604678 # Average occupied blocks per requestor 88110726SN/Asystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.064726 # Average occupied blocks per requestor 88210726SN/Asystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2656.476360 # Average occupied blocks per requestor 88310726SN/Asystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 5431.499219 # Average occupied blocks per requestor 88410726SN/Asystem.cpu1.l2cache.tags.occ_percent::writebacks 0.320641 # Average percentage of cache occupancy 88510726SN/Asystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy 88610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004582 # Average percentage of cache occupancy 88710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.162138 # Average percentage of cache occupancy 88810726SN/Asystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.331512 # Average percentage of cache occupancy 88910726SN/Asystem.cpu1.l2cache.tags.occ_percent::total 0.823000 # Average percentage of cache occupancy 89010726SN/Asystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id 89110726SN/Asystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15948 # Occupied blocks per task id 89210726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 89310726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id 89410726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id 89510726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 89610726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 89710726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 89810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1580 # Occupied blocks per task id 89910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5821 # Occupied blocks per task id 90010726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4453 # Occupied blocks per task id 90110726SN/Asystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4016 # Occupied blocks per task id 90210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id 90310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973389 # Percentage of cache occupancy per task id 90410726SN/Asystem.cpu1.l2cache.tags.tag_accesses 257480243 # Number of tag accesses 90510726SN/Asystem.cpu1.l2cache.tags.data_accesses 257480243 # Number of data accesses 90610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 323221 # number of ReadReq hits 90710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141798 # number of ReadReq hits 90810726SN/Asystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 4279723 # number of ReadReq hits 90910726SN/Asystem.cpu1.l2cache.ReadReq_hits::cpu1.data 3095607 # number of ReadReq hits 91010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 7840349 # number of ReadReq hits 91110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 4091318 # number of Writeback hits 91210585SN/Asystem.cpu1.l2cache.Writeback_hits::total 4091318 # number of Writeback hits 91310585SN/Asystem.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 167179 # number of WriteInvalidateReq hits 91410585SN/Asystem.cpu1.l2cache.WriteInvalidateReq_hits::total 167179 # number of WriteInvalidateReq hits 91510585SN/Asystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3859 # number of UpgradeReq hits 91610585SN/Asystem.cpu1.l2cache.UpgradeReq_hits::total 3859 # number of UpgradeReq hits 91710585SN/Asystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 621347 # number of ReadExReq hits 91810585SN/Asystem.cpu1.l2cache.ReadExReq_hits::total 621347 # number of ReadExReq hits 91910585SN/Asystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 323221 # number of demand (read+write) hits 92010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 141798 # number of demand (read+write) hits 92110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4279723 # number of demand (read+write) hits 92210585SN/Asystem.cpu1.l2cache.demand_hits::cpu1.data 3716954 # number of demand (read+write) hits 92310726SN/Asystem.cpu1.l2cache.demand_hits::total 8461696 # number of demand (read+write) hits 92410726SN/Asystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 323221 # number of overall hits 92510726SN/Asystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 141798 # number of overall hits 92610726SN/Asystem.cpu1.l2cache.overall_hits::cpu1.inst 4279723 # number of overall hits 92710726SN/Asystem.cpu1.l2cache.overall_hits::cpu1.data 3716954 # number of overall hits 92810585SN/Asystem.cpu1.l2cache.overall_hits::total 8461696 # number of overall hits 92910726SN/Asystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12537 # number of ReadReq misses 93010726SN/Asystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9802 # number of ReadReq misses 93110726SN/Asystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 538984 # number of ReadReq misses 93210585SN/Asystem.cpu1.l2cache.ReadReq_misses::cpu1.data 1253218 # number of ReadReq misses 93310585SN/Asystem.cpu1.l2cache.ReadReq_misses::total 1814541 # number of ReadReq misses 93410585SN/Asystem.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271117 # number of WriteInvalidateReq misses 93510585SN/Asystem.cpu1.l2cache.WriteInvalidateReq_misses::total 271117 # number of WriteInvalidateReq misses 93610585SN/Asystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133664 # number of UpgradeReq misses 93710726SN/Asystem.cpu1.l2cache.UpgradeReq_misses::total 133664 # number of UpgradeReq misses 93810726SN/Asystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157982 # number of SCUpgradeReq misses 93910726SN/Asystem.cpu1.l2cache.SCUpgradeReq_misses::total 157982 # number of SCUpgradeReq misses 94010726SN/Asystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 708720 # number of ReadExReq misses 94110726SN/Asystem.cpu1.l2cache.ReadExReq_misses::total 708720 # number of ReadExReq misses 94210726SN/Asystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12537 # number of demand (read+write) misses 94310726SN/Asystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9802 # number of demand (read+write) misses 94410726SN/Asystem.cpu1.l2cache.demand_misses::cpu1.inst 538984 # number of demand (read+write) misses 94510726SN/Asystem.cpu1.l2cache.demand_misses::cpu1.data 1961938 # number of demand (read+write) misses 94610726SN/Asystem.cpu1.l2cache.demand_misses::total 2523261 # number of demand (read+write) misses 94710726SN/Asystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12537 # number of overall misses 94810726SN/Asystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9802 # number of overall misses 94910726SN/Asystem.cpu1.l2cache.overall_misses::cpu1.inst 538984 # number of overall misses 95010726SN/Asystem.cpu1.l2cache.overall_misses::cpu1.data 1961938 # number of overall misses 95110726SN/Asystem.cpu1.l2cache.overall_misses::total 2523261 # number of overall misses 95210726SN/Asystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 335758 # number of ReadReq accesses(hits+misses) 95310726SN/Asystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 151600 # number of ReadReq accesses(hits+misses) 95410726SN/Asystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4818707 # number of ReadReq accesses(hits+misses) 95510726SN/Asystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 4348825 # number of ReadReq accesses(hits+misses) 95610726SN/Asystem.cpu1.l2cache.ReadReq_accesses::total 9654890 # number of ReadReq accesses(hits+misses) 95710726SN/Asystem.cpu1.l2cache.Writeback_accesses::writebacks 4091318 # number of Writeback accesses(hits+misses) 95810726SN/Asystem.cpu1.l2cache.Writeback_accesses::total 4091318 # number of Writeback accesses(hits+misses) 95910726SN/Asystem.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 438296 # number of WriteInvalidateReq accesses(hits+misses) 96010726SN/Asystem.cpu1.l2cache.WriteInvalidateReq_accesses::total 438296 # number of WriteInvalidateReq accesses(hits+misses) 96110726SN/Asystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137523 # number of UpgradeReq accesses(hits+misses) 96210726SN/Asystem.cpu1.l2cache.UpgradeReq_accesses::total 137523 # number of UpgradeReq accesses(hits+misses) 96310585SN/Asystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157982 # number of SCUpgradeReq accesses(hits+misses) 96410585SN/Asystem.cpu1.l2cache.SCUpgradeReq_accesses::total 157982 # number of SCUpgradeReq accesses(hits+misses) 96510585SN/Asystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1330067 # number of ReadExReq accesses(hits+misses) 96610585SN/Asystem.cpu1.l2cache.ReadExReq_accesses::total 1330067 # number of ReadExReq accesses(hits+misses) 96710585SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 335758 # number of demand (read+write) accesses 96810585SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 151600 # number of demand (read+write) accesses 96910585SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.inst 4818707 # number of demand (read+write) accesses 97010585SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.data 5678892 # number of demand (read+write) accesses 97110585SN/Asystem.cpu1.l2cache.demand_accesses::total 10984957 # number of demand (read+write) accesses 97210628SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 335758 # number of overall (read+write) accesses 97310628SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 151600 # number of overall (read+write) accesses 97410628SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.inst 4818707 # number of overall (read+write) accesses 97510628SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.data 5678892 # number of overall (read+write) accesses 97610628SN/Asystem.cpu1.l2cache.overall_accesses::total 10984957 # number of overall (read+write) accesses 97710628SN/Asystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for ReadReq accesses 97810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064657 # miss rate for ReadReq accesses 97910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.111852 # miss rate for ReadReq accesses 98010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288174 # miss rate for ReadReq accesses 98110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.187940 # miss rate for ReadReq accesses 98210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.618571 # miss rate for WriteInvalidateReq accesses 98310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.618571 # miss rate for WriteInvalidateReq accesses 98410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971939 # miss rate for UpgradeReq accesses 98510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971939 # miss rate for UpgradeReq accesses 98610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 98710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 98810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532845 # miss rate for ReadExReq accesses 98910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.532845 # miss rate for ReadExReq accesses 99010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for demand accesses 99110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064657 # miss rate for demand accesses 99210892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111852 # miss rate for demand accesses 99310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345479 # miss rate for demand accesses 99410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.229701 # miss rate for demand accesses 99510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for overall accesses 99610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064657 # miss rate for overall accesses 99710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111852 # miss rate for overall accesses 99810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345479 # miss rate for overall accesses 99910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.229701 # miss rate for overall accesses 100010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 100110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 100210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 100310892Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 100410892Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 100510892Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 100610892Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 100710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 100810892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1212706 # number of writebacks 100910892Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1212706 # number of writebacks 101010892Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 101110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 9779239 # Transaction distribution 101210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9779239 # Transaction distribution 101310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 6380 # Transaction distribution 101410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 6380 # Transaction distribution 101510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 4091318 # Transaction distribution 101610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 438296 # Transaction distribution 101710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 438296 # Transaction distribution 101810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 137523 # Transaction distribution 101910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157982 # Transaction distribution 102010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 295505 # Transaction distribution 102110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1330067 # Transaction distribution 102210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1330067 # Transaction distribution 102310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9637674 # Packet count per connected master and slave (bytes) 102410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16942172 # Packet count per connected master and slave (bytes) 102510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370292 # Packet count per connected master and slave (bytes) 102610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 840154 # Packet count per connected master and slave (bytes) 102710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 27790292 # Packet count per connected master and slave (bytes) 102810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 308397768 # Cumulative packet size per connected master and slave (bytes) 102910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 653382681 # Cumulative packet size per connected master and slave (bytes) 103010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1481168 # Cumulative packet size per connected master and slave (bytes) 103110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3360616 # Cumulative packet size per connected master and slave (bytes) 103210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 966622233 # Cumulative packet size per connected master and slave (bytes) 103310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 3659793 # Total snoops (count) 103410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 19426876 # Request fanout histogram 103510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 5.180108 # Request fanout histogram 103610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.384277 # Request fanout histogram 103710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 103810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 103910892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 104010892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 104110892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 104210892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 104310892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::5 15927941 81.99% 81.99% # Request fanout histogram 104410892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::6 3498935 18.01% 100.00% # Request fanout histogram 104510892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 104610892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 104710892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 104810892Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 19426876 # Request fanout histogram 104910892Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40346 # Transaction distribution 105010892Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40346 # Transaction distribution 105110892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136741 # Transaction distribution 105210892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 30013 # Transaction distribution 105310892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 105410892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47950 # Packet count per connected master and slave (bytes) 105510892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 105610892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 105710892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 105810892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 105910892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 106010892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 106110892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 106210892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 106310892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 106410892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 106510892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 106610892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 106710892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 106810892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 106910892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122884 # Packet count per connected master and slave (bytes) 107010726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) 107110726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) 107210892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 107310892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 107410892Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354174 # Packet count per connected master and slave (bytes) 107510892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47970 # Cumulative packet size per connected master and slave (bytes) 107610892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 107710892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 107810892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 107910892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 108010726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 108110726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 108210892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 108310892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 108410892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 108510726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 108610726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 108710892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 108810892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 108910892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 109010892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155991 # Cumulative packet size per connected master and slave (bytes) 109110892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) 109210892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) 109310585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 109410585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 109510892Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496933 # Cumulative packet size per connected master and slave (bytes) 109610892Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115586 # number of replacements 109710892Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.286927 # Cycle average of tags in use 109810892Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 109910892Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115602 # Sample count of references to valid blocks. 110010892Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 110110892Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 110210892Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.855232 # Average occupied blocks per requestor 110310892Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.431695 # Average occupied blocks per requestor 110410892Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240952 # Average percentage of cache occupancy 110510892Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.464481 # Average percentage of cache occupancy 110610892Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705433 # Average percentage of cache occupancy 110710892Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 110810892Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 110910892Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 111010892Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040802 # Number of tag accesses 111110892Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040802 # Number of data accesses 111210892Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 111310585SN/Asystem.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses 111410585SN/Asystem.iocache.ReadReq_misses::total 8914 # number of ReadReq misses 111510585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 111610585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 111710585SN/Asystem.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 111810585SN/Asystem.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 111910585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 112010585SN/Asystem.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses 112110892Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8917 # number of demand (read+write) misses 112210892Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 112310585SN/Asystem.iocache.overall_misses::realview.ide 8877 # number of overall misses 112410892Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8917 # number of overall misses 112510726SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 112610726SN/Asystem.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) 112710726SN/Asystem.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) 112810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 112910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 113010892Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 113110892Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 113210892Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 113310726SN/Asystem.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses 113410726SN/Asystem.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses 113510892Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 113610892Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses 113710892Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses 113810892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 113910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 114010892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 114110726SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 114210726SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 114310892Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 114410726SN/Asystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 114510892Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 114610726SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 114710726SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 114810892Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 114910892Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 115010892Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 115110892Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 115210892Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 115310585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 115410585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 115510892Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 115610892Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 115710585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 115810827Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 115910827Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106694 # number of writebacks 116010892Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106694 # number of writebacks 116110726SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 116210726SN/Asystem.l2c.tags.replacements 1764050 # number of replacements 116310726SN/Asystem.l2c.tags.tagsinuse 62893.103184 # Cycle average of tags in use 116410892Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 3693923 # Total number of references to valid blocks. 116510726SN/Asystem.l2c.tags.sampled_refs 1823047 # Sample count of references to valid blocks. 116610585SN/Asystem.l2c.tags.avg_refs 2.026236 # Average number of references to valid blocks. 116710585SN/Asystem.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. 116810585SN/Asystem.l2c.tags.occ_blocks::writebacks 35252.715261 # Average occupied blocks per requestor 116910585SN/Asystem.l2c.tags.occ_blocks::cpu0.dtb.walker 32.297168 # Average occupied blocks per requestor 117010585SN/Asystem.l2c.tags.occ_blocks::cpu0.itb.walker 36.889266 # Average occupied blocks per requestor 117110585SN/Asystem.l2c.tags.occ_blocks::cpu0.inst 3199.431904 # Average occupied blocks per requestor 117210585SN/Asystem.l2c.tags.occ_blocks::cpu0.data 6870.253722 # Average occupied blocks per requestor 117310585SN/Asystem.l2c.tags.occ_blocks::cpu1.dtb.walker 308.072507 # Average occupied blocks per requestor 117410585SN/Asystem.l2c.tags.occ_blocks::cpu1.itb.walker 447.332489 # Average occupied blocks per requestor 117510585SN/Asystem.l2c.tags.occ_blocks::cpu1.inst 2890.642136 # Average occupied blocks per requestor 117610585SN/Asystem.l2c.tags.occ_blocks::cpu1.data 13855.468731 # Average occupied blocks per requestor 117710585SN/Asystem.l2c.tags.occ_percent::writebacks 0.537914 # Average percentage of cache occupancy 117810585SN/Asystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000493 # Average percentage of cache occupancy 117910585SN/Asystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000563 # Average percentage of cache occupancy 118010726SN/Asystem.l2c.tags.occ_percent::cpu0.inst 0.048819 # Average percentage of cache occupancy 118110726SN/Asystem.l2c.tags.occ_percent::cpu0.data 0.104832 # Average percentage of cache occupancy 118210726SN/Asystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004701 # Average percentage of cache occupancy 118310585SN/Asystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006826 # Average percentage of cache occupancy 118410585SN/Asystem.l2c.tags.occ_percent::cpu1.inst 0.044108 # Average percentage of cache occupancy 118510726SN/Asystem.l2c.tags.occ_percent::cpu1.data 0.211418 # Average percentage of cache occupancy 118610726SN/Asystem.l2c.tags.occ_percent::total 0.959673 # Average percentage of cache occupancy 118710585SN/Asystem.l2c.tags.occ_task_id_blocks::1023 209 # Occupied blocks per task id 118810585SN/Asystem.l2c.tags.occ_task_id_blocks::1024 58788 # Occupied blocks per task id 118910585SN/Asystem.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 119010585SN/Asystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 119110585SN/Asystem.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id 119210585SN/Asystem.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 119310585SN/Asystem.l2c.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id 119410585SN/Asystem.l2c.tags.age_task_id_blocks_1024::2 3602 # Occupied blocks per task id 119510585SN/Asystem.l2c.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id 119610585SN/Asystem.l2c.tags.age_task_id_blocks_1024::4 49009 # Occupied blocks per task id 119710585SN/Asystem.l2c.tags.occ_task_id_percent::1023 0.003189 # Percentage of cache occupancy per task id 119810585SN/Asystem.l2c.tags.occ_task_id_percent::1024 0.897034 # Percentage of cache occupancy per task id 119910585SN/Asystem.l2c.tags.tag_accesses 66315846 # Number of tag accesses 120010585SN/Asystem.l2c.tags.data_accesses 66315846 # Number of data accesses 120110726SN/Asystem.l2c.ReadReq_hits::cpu0.dtb.walker 5920 # number of ReadReq hits 120210726SN/Asystem.l2c.ReadReq_hits::cpu0.itb.walker 4325 # number of ReadReq hits 120310726SN/Asystem.l2c.ReadReq_hits::cpu0.inst 492739 # number of ReadReq hits 120410585SN/Asystem.l2c.ReadReq_hits::cpu0.data 723130 # number of ReadReq hits 120510585SN/Asystem.l2c.ReadReq_hits::cpu1.dtb.walker 5730 # number of ReadReq hits 120610726SN/Asystem.l2c.ReadReq_hits::cpu1.itb.walker 3764 # number of ReadReq hits 120710726SN/Asystem.l2c.ReadReq_hits::cpu1.inst 496903 # number of ReadReq hits 120810726SN/Asystem.l2c.ReadReq_hits::cpu1.data 707011 # number of ReadReq hits 120910585SN/Asystem.l2c.ReadReq_hits::total 2439522 # number of ReadReq hits 121010726SN/Asystem.l2c.Writeback_hits::writebacks 2755239 # number of Writeback hits 121110585SN/Asystem.l2c.Writeback_hits::total 2755239 # number of Writeback hits 121210585SN/Asystem.l2c.WriteInvalidateReq_hits::cpu0.data 115462 # number of WriteInvalidateReq hits 121310726SN/Asystem.l2c.WriteInvalidateReq_hits::cpu1.data 102925 # number of WriteInvalidateReq hits 121410726SN/Asystem.l2c.WriteInvalidateReq_hits::total 218387 # number of WriteInvalidateReq hits 121510726SN/Asystem.l2c.UpgradeReq_hits::cpu0.data 13978 # number of UpgradeReq hits 121610726SN/Asystem.l2c.UpgradeReq_hits::cpu1.data 10743 # number of UpgradeReq hits 121710726SN/Asystem.l2c.UpgradeReq_hits::total 24721 # number of UpgradeReq hits 121810585SN/Asystem.l2c.SCUpgradeReq_hits::cpu0.data 1494 # number of SCUpgradeReq hits 121910585SN/Asystem.l2c.SCUpgradeReq_hits::cpu1.data 1282 # number of SCUpgradeReq hits 122010585SN/Asystem.l2c.SCUpgradeReq_hits::total 2776 # number of SCUpgradeReq hits 122110726SN/Asystem.l2c.ReadExReq_hits::cpu0.data 196550 # number of ReadExReq hits 122210726SN/Asystem.l2c.ReadExReq_hits::cpu1.data 177871 # number of ReadExReq hits 122310585SN/Asystem.l2c.ReadExReq_hits::total 374421 # number of ReadExReq hits 122410726SN/Asystem.l2c.demand_hits::cpu0.dtb.walker 5920 # number of demand (read+write) hits 122510726SN/Asystem.l2c.demand_hits::cpu0.itb.walker 4325 # number of demand (read+write) hits 122610585SN/Asystem.l2c.demand_hits::cpu0.inst 492739 # number of demand (read+write) hits 122710585SN/Asystem.l2c.demand_hits::cpu0.data 919680 # number of demand (read+write) hits 122810892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5730 # number of demand (read+write) hits 122910892Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3764 # number of demand (read+write) hits 123010585SN/Asystem.l2c.demand_hits::cpu1.inst 496903 # number of demand (read+write) hits 123110726SN/Asystem.l2c.demand_hits::cpu1.data 884882 # number of demand (read+write) hits 123210726SN/Asystem.l2c.demand_hits::total 2813943 # number of demand (read+write) hits 123310585SN/Asystem.l2c.overall_hits::cpu0.dtb.walker 5920 # number of overall hits 123410726SN/Asystem.l2c.overall_hits::cpu0.itb.walker 4325 # number of overall hits 123510726SN/Asystem.l2c.overall_hits::cpu0.inst 492739 # number of overall hits 123610585SN/Asystem.l2c.overall_hits::cpu0.data 919680 # number of overall hits 123710726SN/Asystem.l2c.overall_hits::cpu1.dtb.walker 5730 # number of overall hits 123810726SN/Asystem.l2c.overall_hits::cpu1.itb.walker 3764 # number of overall hits 123910585SN/Asystem.l2c.overall_hits::cpu1.inst 496903 # number of overall hits 124010585SN/Asystem.l2c.overall_hits::cpu1.data 884882 # number of overall hits 124110892Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2813943 # number of overall hits 124210892Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 2339 # number of ReadReq misses 124310585SN/Asystem.l2c.ReadReq_misses::cpu0.itb.walker 1938 # number of ReadReq misses 124410726SN/Asystem.l2c.ReadReq_misses::cpu0.inst 57739 # number of ReadReq misses 124510726SN/Asystem.l2c.ReadReq_misses::cpu0.data 182657 # number of ReadReq misses 124610585SN/Asystem.l2c.ReadReq_misses::cpu1.dtb.walker 3510 # number of ReadReq misses 124710726SN/Asystem.l2c.ReadReq_misses::cpu1.itb.walker 3482 # number of ReadReq misses 124810726SN/Asystem.l2c.ReadReq_misses::cpu1.inst 42081 # number of ReadReq misses 124910585SN/Asystem.l2c.ReadReq_misses::cpu1.data 192722 # number of ReadReq misses 125010585SN/Asystem.l2c.ReadReq_misses::total 486468 # number of ReadReq misses 125110585SN/Asystem.l2c.WriteInvalidateReq_misses::cpu0.data 475939 # number of WriteInvalidateReq misses 125210585SN/Asystem.l2c.WriteInvalidateReq_misses::cpu1.data 161383 # number of WriteInvalidateReq misses 125310585SN/Asystem.l2c.WriteInvalidateReq_misses::total 637322 # number of WriteInvalidateReq misses 125410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 57732 # number of UpgradeReq misses 125510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 55051 # number of UpgradeReq misses 125610585SN/Asystem.l2c.UpgradeReq_misses::total 112783 # number of UpgradeReq misses 125710585SN/Asystem.l2c.SCUpgradeReq_misses::cpu0.data 7557 # number of SCUpgradeReq misses 125810585SN/Asystem.l2c.SCUpgradeReq_misses::cpu1.data 7409 # number of SCUpgradeReq misses 125910585SN/Asystem.l2c.SCUpgradeReq_misses::total 14966 # number of SCUpgradeReq misses 126010585SN/Asystem.l2c.ReadExReq_misses::cpu0.data 376574 # number of ReadExReq misses 126110585SN/Asystem.l2c.ReadExReq_misses::cpu1.data 420815 # number of ReadExReq misses 126210585SN/Asystem.l2c.ReadExReq_misses::total 797389 # number of ReadExReq misses 126310585SN/Asystem.l2c.demand_misses::cpu0.dtb.walker 2339 # number of demand (read+write) misses 126410585SN/Asystem.l2c.demand_misses::cpu0.itb.walker 1938 # number of demand (read+write) misses 126510585SN/Asystem.l2c.demand_misses::cpu0.inst 57739 # number of demand (read+write) misses 126610585SN/Asystem.l2c.demand_misses::cpu0.data 559231 # number of demand (read+write) misses 126710585SN/Asystem.l2c.demand_misses::cpu1.dtb.walker 3510 # number of demand (read+write) misses 126810585SN/Asystem.l2c.demand_misses::cpu1.itb.walker 3482 # number of demand (read+write) misses 126910585SN/Asystem.l2c.demand_misses::cpu1.inst 42081 # number of demand (read+write) misses 127010585SN/Asystem.l2c.demand_misses::cpu1.data 613537 # number of demand (read+write) misses 127110585SN/Asystem.l2c.demand_misses::total 1283857 # number of demand (read+write) misses 127210585SN/Asystem.l2c.overall_misses::cpu0.dtb.walker 2339 # number of overall misses 127310892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1938 # number of overall misses 127410892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 57739 # number of overall misses 127510892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 559231 # number of overall misses 127610892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3510 # number of overall misses 127710892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3482 # number of overall misses 127810892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 42081 # number of overall misses 127910892Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 613537 # number of overall misses 128010892Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1283857 # number of overall misses 128110892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 8259 # number of ReadReq accesses(hits+misses) 128210892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 6263 # number of ReadReq accesses(hits+misses) 128310892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 550478 # number of ReadReq accesses(hits+misses) 128410892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 905787 # number of ReadReq accesses(hits+misses) 128510892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 9240 # number of ReadReq accesses(hits+misses) 128610892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 7246 # number of ReadReq accesses(hits+misses) 128710892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 538984 # number of ReadReq accesses(hits+misses) 128810892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 899733 # number of ReadReq accesses(hits+misses) 128910892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2925990 # number of ReadReq accesses(hits+misses) 129010892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2755239 # number of Writeback accesses(hits+misses) 129110892Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2755239 # number of Writeback accesses(hits+misses) 129210892Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu0.data 591401 # number of WriteInvalidateReq accesses(hits+misses) 129310892Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu1.data 264308 # number of WriteInvalidateReq accesses(hits+misses) 129410892Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::total 855709 # number of WriteInvalidateReq accesses(hits+misses) 129510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 71710 # number of UpgradeReq accesses(hits+misses) 129610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 65794 # number of UpgradeReq accesses(hits+misses) 129710892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 137504 # number of UpgradeReq accesses(hits+misses) 129810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9051 # number of SCUpgradeReq accesses(hits+misses) 129910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8691 # number of SCUpgradeReq accesses(hits+misses) 130010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 17742 # number of SCUpgradeReq accesses(hits+misses) 130110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 573124 # number of ReadExReq accesses(hits+misses) 130210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 598686 # number of ReadExReq accesses(hits+misses) 130310892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1171810 # number of ReadExReq accesses(hits+misses) 130410892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8259 # number of demand (read+write) accesses 130510892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6263 # number of demand (read+write) accesses 130610892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 550478 # number of demand (read+write) accesses 130710892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1478911 # number of demand (read+write) accesses 130810892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 9240 # number of demand (read+write) accesses 130910892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7246 # number of demand (read+write) accesses 131010892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 538984 # number of demand (read+write) accesses 131110892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1498419 # number of demand (read+write) accesses 131210892Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4097800 # number of demand (read+write) accesses 131310892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8259 # number of overall (read+write) accesses 131410892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6263 # number of overall (read+write) accesses 131510892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 550478 # number of overall (read+write) accesses 131610892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1478911 # number of overall (read+write) accesses 131710892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 9240 # number of overall (read+write) accesses 131810892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7246 # number of overall (read+write) accesses 131910892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 538984 # number of overall (read+write) accesses 132010892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1498419 # number of overall (read+write) accesses 132110892Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4097800 # number of overall (read+write) accesses 132210892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for ReadReq accesses 132310892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309436 # miss rate for ReadReq accesses 132410892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.104889 # miss rate for ReadReq accesses 132510892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.201656 # miss rate for ReadReq accesses 132610892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for ReadReq accesses 132710892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.480541 # miss rate for ReadReq accesses 132810892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.078075 # miss rate for ReadReq accesses 132910892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.214199 # miss rate for ReadReq accesses 133010892Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.166258 # miss rate for ReadReq accesses 133110892Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.804765 # miss rate for WriteInvalidateReq accesses 133210892Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.610587 # miss rate for WriteInvalidateReq accesses 133310892Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::total 0.744788 # miss rate for WriteInvalidateReq accesses 133410892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.805076 # miss rate for UpgradeReq accesses 133510892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.836718 # miss rate for UpgradeReq accesses 133610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.820216 # miss rate for UpgradeReq accesses 133710892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.834935 # miss rate for SCUpgradeReq accesses 133810892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.852491 # miss rate for SCUpgradeReq accesses 133910892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.843535 # miss rate for SCUpgradeReq accesses 134010892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.657055 # miss rate for ReadExReq accesses 134110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.702898 # miss rate for ReadExReq accesses 134210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.680476 # miss rate for ReadExReq accesses 134310892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for demand accesses 134410892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.309436 # miss rate for demand accesses 134510892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.104889 # miss rate for demand accesses 134610892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.378137 # miss rate for demand accesses 134710892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for demand accesses 134810892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.480541 # miss rate for demand accesses 134910892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.078075 # miss rate for demand accesses 135010892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.409456 # miss rate for demand accesses 135110892Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.313304 # miss rate for demand accesses 135210892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for overall accesses 135310892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.309436 # miss rate for overall accesses 135410892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.104889 # miss rate for overall accesses 135510892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.378137 # miss rate for overall accesses 135610892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for overall accesses 135710892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.480541 # miss rate for overall accesses 135810892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.078075 # miss rate for overall accesses 135910892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.409456 # miss rate for overall accesses 136010892Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.313304 # miss rate for overall accesses 136110892Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136210892Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 136310892Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 136410892Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 136510892Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 136610892Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 136710892Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 136810892Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 136910892Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1467678 # number of writebacks 137010892Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1467678 # number of writebacks 137110892Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 137210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 577534 # Transaction distribution 137310892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 577534 # Transaction distribution 137410892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38903 # Transaction distribution 137510892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38903 # Transaction distribution 137610892Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1574372 # Transaction distribution 137710892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 739425 # Transaction distribution 137810892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 739425 # Transaction distribution 137910892Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 325897 # Transaction distribution 138010892Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 311300 # Transaction distribution 138110892Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 149445 # Transaction distribution 138210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 961374 # Transaction distribution 138310892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 780321 # Transaction distribution 138410892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122884 # Packet count per connected master and slave (bytes) 138510892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 138610892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27406 # Packet count per connected master and slave (bytes) 138710892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6326067 # Packet count per connected master and slave (bytes) 138810892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6476449 # Packet count per connected master and slave (bytes) 138910892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337984 # Packet count per connected master and slave (bytes) 139010892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 337984 # Packet count per connected master and slave (bytes) 139110892Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6814433 # Packet count per connected master and slave (bytes) 139210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155991 # Cumulative packet size per connected master and slave (bytes) 139310892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 139410892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54812 # Cumulative packet size per connected master and slave (bytes) 139510892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215692580 # Cumulative packet size per connected master and slave (bytes) 139610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 215903587 # Cumulative packet size per connected master and slave (bytes) 139710892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229504 # Cumulative packet size per connected master and slave (bytes) 139810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 14229504 # Cumulative packet size per connected master and slave (bytes) 139910892Sandreas.hansson@arm.comsystem.membus.pkt_size::total 230133091 # Cumulative packet size per connected master and slave (bytes) 140010892Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 140110892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4407750 # Request fanout histogram 140210892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 140310892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 140410892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 140510892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 140610892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4407750 100.00% 100.00% # Request fanout histogram 140710892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 140810892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 140910892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 141010892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 141110892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4407750 # Request fanout histogram 141210892Sandreas.hansson@arm.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 141310892Sandreas.hansson@arm.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 141410892Sandreas.hansson@arm.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 141510892Sandreas.hansson@arm.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 141610892Sandreas.hansson@arm.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 141710892Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 141810892Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 141910892Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 142010892Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 142110892Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 142210892Sandreas.hansson@arm.comsystem.realview.ethernet.totPackets 3 # Total Packets 142310892Sandreas.hansson@arm.comsystem.realview.ethernet.totBytes 966 # Total Bytes 142410892Sandreas.hansson@arm.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 142510892Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 142610892Sandreas.hansson@arm.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 142710892Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 142810892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 142910892Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 143010892Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 143110892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 143210892Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 143310892Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 143410892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 143510892Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 143610892Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 143710892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 143810892Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 143910892Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 144010892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 144110892Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 144210892Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 144310892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 144410892Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 144510892Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 144610892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 144710892Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 144810892Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 144910892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 145010892Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 145110892Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 145210892Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 145310892Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 145410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 3699896 # Transaction distribution 145510892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3699896 # Transaction distribution 145610892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38903 # Transaction distribution 145710892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38903 # Transaction distribution 145810892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2755239 # Transaction distribution 145910515SN/Asystem.toL2Bus.trans_dist::WriteInvalidateReq 855709 # Transaction distribution 146010515SN/Asystem.toL2Bus.trans_dist::WriteInvalidateResp 855709 # Transaction distribution 146110515SN/Asystem.toL2Bus.trans_dist::UpgradeReq 328922 # Transaction distribution 146210515SN/Asystem.toL2Bus.trans_dist::SCUpgradeReq 314076 # Transaction distribution 146310515SN/Asystem.toL2Bus.trans_dist::UpgradeResp 642998 # Transaction distribution 146410515SN/Asystem.toL2Bus.trans_dist::ReadExReq 1352863 # Transaction distribution 146510515SN/Asystem.toL2Bus.trans_dist::ReadExResp 1352863 # Transaction distribution 146610515SN/Asystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8525495 # Packet count per connected master and slave (bytes) 146710892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7410482 # Packet count per connected master and slave (bytes) 146810892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 15935977 # Packet count per connected master and slave (bytes) 146910515SN/Asystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295216066 # Cumulative packet size per connected master and slave (bytes) 147010892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 254408545 # Cumulative packet size per connected master and slave (bytes) 147110892Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 549624611 # Cumulative packet size per connected master and slave (bytes) 147210827Sandreas.hansson@arm.comsystem.toL2Bus.snoops 117315 # Total snoops (count) 147310827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 9340198 # Request fanout histogram 147410892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.012381 # Request fanout histogram 147510944Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.110581 # Request fanout histogram 147610892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 147710892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 147810892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 9224553 98.76% 98.76% # Request fanout histogram 147910892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 115645 1.24% 100.00% # Request fanout histogram 148010892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 148110892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 148210892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 148310892Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 9340198 # Request fanout histogram 148410726SN/A 148510585SN/A---------- End Simulation Statistics ---------- 148610726SN/A