stats.txt revision 11353:31c5786945b4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.327140 # Number of seconds simulated 4sim_ticks 51327140089000 # Number of ticks simulated 5final_tick 51327140089000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 210997 # Simulator instruction rate (inst/s) 8host_op_rate 247928 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12768702843 # Simulator tick rate (ticks/s) 10host_mem_usage 688028 # Number of bytes of host memory used 11host_seconds 4019.76 # Real time elapsed on the host 12sim_insts 848158120 # Number of instructions simulated 13sim_ops 996609834 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 211968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 207872 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5637664 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 41611720 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory 21system.physmem.bytes_read::total 48116328 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5637664 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5637664 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 68318336 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 68338916 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 3312 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 3248 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 104041 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 650196 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 767783 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1067474 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1070047 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 4130 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 4050 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 109838 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 810716 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 8711 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 937444 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 109838 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 109838 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1331037 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1331438 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1331037 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 4130 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 4050 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 109838 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 811117 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 8711 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 2268882 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 767783 # Number of read requests accepted 55system.physmem.writeReqs 1070047 # Number of write requests accepted 56system.physmem.readBursts 767783 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1070047 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 49097152 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue 60system.physmem.bytesWritten 68336896 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 48116328 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 68338916 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 640 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 44980 # Per bank write bursts 67system.physmem.perBankRdBursts::1 51602 # Per bank write bursts 68system.physmem.perBankRdBursts::2 47368 # Per bank write bursts 69system.physmem.perBankRdBursts::3 43602 # Per bank write bursts 70system.physmem.perBankRdBursts::4 45132 # Per bank write bursts 71system.physmem.perBankRdBursts::5 50541 # Per bank write bursts 72system.physmem.perBankRdBursts::6 45264 # Per bank write bursts 73system.physmem.perBankRdBursts::7 48215 # Per bank write bursts 74system.physmem.perBankRdBursts::8 45181 # Per bank write bursts 75system.physmem.perBankRdBursts::9 71916 # Per bank write bursts 76system.physmem.perBankRdBursts::10 43746 # Per bank write bursts 77system.physmem.perBankRdBursts::11 51986 # Per bank write bursts 78system.physmem.perBankRdBursts::12 43936 # Per bank write bursts 79system.physmem.perBankRdBursts::13 46943 # Per bank write bursts 80system.physmem.perBankRdBursts::14 42923 # Per bank write bursts 81system.physmem.perBankRdBursts::15 43808 # Per bank write bursts 82system.physmem.perBankWrBursts::0 64378 # Per bank write bursts 83system.physmem.perBankWrBursts::1 68822 # Per bank write bursts 84system.physmem.perBankWrBursts::2 67360 # Per bank write bursts 85system.physmem.perBankWrBursts::3 65401 # Per bank write bursts 86system.physmem.perBankWrBursts::4 67058 # Per bank write bursts 87system.physmem.perBankWrBursts::5 69359 # Per bank write bursts 88system.physmem.perBankWrBursts::6 64813 # Per bank write bursts 89system.physmem.perBankWrBursts::7 68136 # Per bank write bursts 90system.physmem.perBankWrBursts::8 65855 # Per bank write bursts 91system.physmem.perBankWrBursts::9 70723 # Per bank write bursts 92system.physmem.perBankWrBursts::10 64194 # Per bank write bursts 93system.physmem.perBankWrBursts::11 71056 # Per bank write bursts 94system.physmem.perBankWrBursts::12 64787 # Per bank write bursts 95system.physmem.perBankWrBursts::13 67120 # Per bank write bursts 96system.physmem.perBankWrBursts::14 64460 # Per bank write bursts 97system.physmem.perBankWrBursts::15 64242 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 33 # Number of times write queue was full causing retry 100system.physmem.totGap 51327138675500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 21272 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 746498 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1067474 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 514277 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 203743 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 30358 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 13038 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 584 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 588 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 567 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1290 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 814 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 374 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 135 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 118 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 26644 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 32364 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 49179 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 54414 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 60551 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 60830 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 61808 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 61874 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 69991 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 63900 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 76806 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 62055 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 64795 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 68451 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 60364 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 58974 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 57166 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 3220 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 1478 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 1170 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 1018 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 1079 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 849 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 677 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 559 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 604 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 463 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 371 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 342 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 360 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 309 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 305 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 242 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 279 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 159 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 123 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 181 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 471185 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 249.230345 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 149.487407 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 290.645433 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 207601 44.06% 44.06% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 122052 25.90% 69.96% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 43152 9.16% 79.12% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 22522 4.78% 83.90% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 14798 3.14% 87.04% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 9568 2.03% 89.07% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 7612 1.62% 90.69% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 6084 1.29% 91.98% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 37796 8.02% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 471185 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 54136 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 14.170570 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 76.787361 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-511 54130 99.99% 99.99% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::512-1023 3 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 54136 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 54136 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 19.723733 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 18.769647 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 8.988954 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-19 40635 75.06% 75.06% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20-23 4496 8.31% 83.37% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::24-27 5195 9.60% 92.96% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28-31 1325 2.45% 95.41% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32-35 409 0.76% 96.17% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36-39 232 0.43% 96.59% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-43 326 0.60% 97.20% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::44-47 142 0.26% 97.46% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::48-51 398 0.74% 98.19% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::56-59 56 0.10% 98.53% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::60-63 67 0.12% 98.66% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::64-67 319 0.59% 99.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::68-71 37 0.07% 99.31% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::72-75 24 0.04% 99.36% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::76-79 111 0.21% 99.56% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::80-83 168 0.31% 99.87% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::84-87 2 0.00% 99.88% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 3 0.01% 99.88% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 3 0.01% 99.89% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 2 0.00% 99.89% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::104-107 5 0.01% 99.90% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::108-111 1 0.00% 99.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::116-119 3 0.01% 99.91% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::120-123 2 0.00% 99.92% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 11 0.02% 99.94% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 5 0.01% 99.95% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::208-211 2 0.00% 100.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::total 54136 # Writes before turning the bus around for reads 275system.physmem.totQLat 15242803686 # Total ticks spent queuing 276system.physmem.totMemAccLat 29626734936 # Total ticks spent from burst creation until serviced by the DRAM 277system.physmem.totBusLat 3835715000 # Total ticks spent in databus transfers 278system.physmem.avgQLat 19869.57 # Average queueing delay per DRAM burst 279system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 280system.physmem.avgMemAccLat 38619.57 # Average memory access latency per DRAM burst 281system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s 282system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s 283system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s 284system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s 285system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 286system.physmem.busUtil 0.02 # Data bus utilization in percentage 287system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 288system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 289system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing 290system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing 291system.physmem.readRowHits 579803 # Number of row buffer hits during reads 292system.physmem.writeRowHits 783916 # Number of row buffer hits during writes 293system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 294system.physmem.writeRowHitRate 73.42 # Row buffer hit rate for writes 295system.physmem.avgGap 27928121.03 # Average gap between requests 296system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined 297system.physmem_0.actEnergy 1791077400 # Energy for activate commands per rank (pJ) 298system.physmem_0.preEnergy 977274375 # Energy for precharge commands per rank (pJ) 299system.physmem_0.readEnergy 2938244400 # Energy for read commands per rank (pJ) 300system.physmem_0.writeEnergy 3468841200 # Energy for write commands per rank (pJ) 301system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) 302system.physmem_0.actBackEnergy 1235175473835 # Energy for active background per rank (pJ) 303system.physmem_0.preBackEnergy 29712796340250 # Energy for precharge background per rank (pJ) 304system.physmem_0.totalEnergy 34309586468340 # Total energy per rank (pJ) 305system.physmem_0.averagePower 668.449224 # Core power per rank (mW) 306system.physmem_0.memoryStateTime::IDLE 49429866192554 # Time in different power states 307system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states 308system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 309system.physmem_0.memoryStateTime::ACT 183347171196 # Time in different power states 310system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.physmem_1.actEnergy 1771020720 # Energy for activate commands per rank (pJ) 312system.physmem_1.preEnergy 966330750 # Energy for precharge commands per rank (pJ) 313system.physmem_1.readEnergy 3045424200 # Energy for read commands per rank (pJ) 314system.physmem_1.writeEnergy 3450165840 # Energy for write commands per rank (pJ) 315system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) 316system.physmem_1.actBackEnergy 1235608843410 # Energy for active background per rank (pJ) 317system.physmem_1.preBackEnergy 29712416191500 # Energy for precharge background per rank (pJ) 318system.physmem_1.totalEnergy 34309697193300 # Total energy per rank (pJ) 319system.physmem_1.averagePower 668.451381 # Core power per rank (mW) 320system.physmem_1.memoryStateTime::IDLE 49429214230967 # Time in different power states 321system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states 322system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 323system.physmem_1.memoryStateTime::ACT 183999255033 # Time in different power states 324system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 325system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 333system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 340system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 341system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 342system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 343system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 344system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 345system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 346system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 347system.cpu.branchPred.lookups 224297572 # Number of BP lookups 348system.cpu.branchPred.condPredicted 149902957 # Number of conditional branches predicted 349system.cpu.branchPred.condIncorrect 12193787 # Number of conditional branches incorrect 350system.cpu.branchPred.BTBLookups 158452721 # Number of BTB lookups 351system.cpu.branchPred.BTBHits 103491021 # Number of BTB hits 352system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 353system.cpu.branchPred.BTBHitPct 65.313502 # BTB Hit Percentage 354system.cpu.branchPred.usedRAS 30817326 # Number of times the RAS was used to get a target. 355system.cpu.branchPred.RASInCorrect 343319 # Number of incorrect RAS predictions. 356system.cpu_clk_domain.clock 500 # Clock period in ticks 357system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 366system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 367system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 368system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 369system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 370system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 371system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 372system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 373system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 374system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 375system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 376system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 377system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 378system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 386system.cpu.dtb.walker.walks 949838 # Table walker walks requested 387system.cpu.dtb.walker.walksLong 949838 # Table walker walks initiated with long descriptors 388system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15818 # Level at which table walker walks with long descriptors terminate 389system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155419 # Level at which table walker walks with long descriptors terminate 390system.cpu.dtb.walker.walksSquashedBefore 436827 # Table walks squashed before starting 391system.cpu.dtb.walker.walkWaitTime::samples 513011 # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::mean 2225.817770 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273 # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::0-65535 509618 99.34% 99.34% # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::65536-131071 1930 0.38% 99.71% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::131072-196607 987 0.19% 99.91% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::196608-262143 197 0.04% 99.95% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::262144-327679 149 0.03% 99.97% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::393216-458751 53 0.01% 99.99% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::total 513011 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkCompletionTime::samples 485512 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::0-65535 474265 97.68% 97.68% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::65536-131071 7843 1.62% 99.30% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::131072-196607 2427 0.50% 99.80% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::196608-262143 166 0.03% 99.83% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::262144-327679 551 0.11% 99.95% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::327680-393215 105 0.02% 99.97% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::393216-458751 109 0.02% 99.99% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::total 485512 # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walksPending::samples 779669132376 # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::mean 0.722626 # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::stdev 0.523315 # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::0-1 777439658376 99.71% 99.71% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::2-3 1176099000 0.15% 99.86% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::4-5 488850000 0.06% 99.93% # Table walker pending requests distribution 427system.cpu.dtb.walker.walksPending::6-7 205535000 0.03% 99.95% # Table walker pending requests distribution 428system.cpu.dtb.walker.walksPending::8-9 152105500 0.02% 99.97% # Table walker pending requests distribution 429system.cpu.dtb.walker.walksPending::10-11 121751500 0.02% 99.99% # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::12-13 29187500 0.00% 99.99% # Table walker pending requests distribution 431system.cpu.dtb.walker.walksPending::14-15 53249500 0.01% 100.00% # Table walker pending requests distribution 432system.cpu.dtb.walker.walksPending::16-17 2696000 0.00% 100.00% # Table walker pending requests distribution 433system.cpu.dtb.walker.walksPending::total 779669132376 # Table walker pending requests distribution 434system.cpu.dtb.walker.walkPageSizes::4K 155420 90.76% 90.76% # Table walker page sizes translated 435system.cpu.dtb.walker.walkPageSizes::2M 15818 9.24% 100.00% # Table walker page sizes translated 436system.cpu.dtb.walker.walkPageSizes::total 171238 # Table walker page sizes translated 437system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949838 # Table walker requests started/completed, data/inst 438system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949838 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171238 # Table walker requests started/completed, data/inst 441system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171238 # Table walker requests started/completed, data/inst 443system.cpu.dtb.walker.walkRequestOrigin::total 1121076 # Table walker requests started/completed, data/inst 444system.cpu.dtb.inst_hits 0 # ITB inst hits 445system.cpu.dtb.inst_misses 0 # ITB inst misses 446system.cpu.dtb.read_hits 169331819 # DTB read hits 447system.cpu.dtb.read_misses 674131 # DTB read misses 448system.cpu.dtb.write_hits 147501461 # DTB write hits 449system.cpu.dtb.write_misses 275707 # DTB write misses 450system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 451system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 452system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 453system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID 454system.cpu.dtb.flush_entries 72020 # Number of entries that have been flushed from TLB 455system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions 456system.cpu.dtb.prefetch_faults 10130 # Number of TLB faults due to prefetch 457system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 458system.cpu.dtb.perms_faults 69829 # Number of TLB faults due to permissions restrictions 459system.cpu.dtb.read_accesses 170005950 # DTB read accesses 460system.cpu.dtb.write_accesses 147777168 # DTB write accesses 461system.cpu.dtb.inst_accesses 0 # ITB inst accesses 462system.cpu.dtb.hits 316833280 # DTB hits 463system.cpu.dtb.misses 949838 # DTB misses 464system.cpu.dtb.accesses 317783118 # DTB accesses 465system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 473system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 474system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 475system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 476system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 477system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 478system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 479system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 480system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 481system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 482system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 483system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 484system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 485system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 486system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 494system.cpu.itb.walker.walks 161333 # Table walker walks requested 495system.cpu.itb.walker.walksLong 161333 # Table walker walks initiated with long descriptors 496system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate 497system.cpu.itb.walker.walksLongTerminationLevel::Level3 121604 # Level at which table walker walks with long descriptors terminate 498system.cpu.itb.walker.walksSquashedBefore 17607 # Table walks squashed before starting 499system.cpu.itb.walker.walkWaitTime::samples 143726 # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::mean 1329.870726 # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::stdev 9693.373994 # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::0-32767 142645 99.25% 99.25% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::32768-65535 592 0.41% 99.66% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::65536-98303 67 0.05% 99.71% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::98304-131071 93 0.06% 99.77% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.96% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::163840-196607 24 0.02% 99.98% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::229376-262143 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency 511system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency 512system.cpu.itb.walker.walkWaitTime::360448-393215 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 513system.cpu.itb.walker.walkWaitTime::total 143726 # Table walker wait (enqueue to first request) latency 514system.cpu.itb.walker.walkCompletionTime::samples 140644 # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::mean 29101.756918 # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283 # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201 # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::0-65535 137486 97.75% 97.75% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::65536-131071 886 0.63% 98.38% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::131072-196607 1961 1.39% 99.78% # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walkCompletionTime::196608-262143 124 0.09% 99.87% # Table walker service (enqueue to completion) latency 522system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.09% 99.96% # Table walker service (enqueue to completion) latency 523system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.02% 99.98% # Table walker service (enqueue to completion) latency 524system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.99% # Table walker service (enqueue to completion) latency 525system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 526system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 527system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 528system.cpu.itb.walker.walkCompletionTime::total 140644 # Table walker service (enqueue to completion) latency 529system.cpu.itb.walker.walksPending::samples 672291747976 # Table walker pending requests distribution 530system.cpu.itb.walker.walksPending::mean 0.944017 # Table walker pending requests distribution 531system.cpu.itb.walker.walksPending::stdev 0.230261 # Table walker pending requests distribution 532system.cpu.itb.walker.walksPending::0 37693655356 5.61% 5.61% # Table walker pending requests distribution 533system.cpu.itb.walker.walksPending::1 634541752620 94.38% 99.99% # Table walker pending requests distribution 534system.cpu.itb.walker.walksPending::2 55651000 0.01% 100.00% # Table walker pending requests distribution 535system.cpu.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution 536system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution 537system.cpu.itb.walker.walksPending::total 672291747976 # Table walker pending requests distribution 538system.cpu.itb.walker.walkPageSizes::4K 121604 98.84% 98.84% # Table walker page sizes translated 539system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated 540system.cpu.itb.walker.walkPageSizes::total 123037 # Table walker page sizes translated 541system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 542system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161333 # Table walker requests started/completed, data/inst 543system.cpu.itb.walker.walkRequestOrigin_Requested::total 161333 # Table walker requests started/completed, data/inst 544system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 545system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123037 # Table walker requests started/completed, data/inst 546system.cpu.itb.walker.walkRequestOrigin_Completed::total 123037 # Table walker requests started/completed, data/inst 547system.cpu.itb.walker.walkRequestOrigin::total 284370 # Table walker requests started/completed, data/inst 548system.cpu.itb.inst_hits 356599136 # ITB inst hits 549system.cpu.itb.inst_misses 161333 # ITB inst misses 550system.cpu.itb.read_hits 0 # DTB read hits 551system.cpu.itb.read_misses 0 # DTB read misses 552system.cpu.itb.write_hits 0 # DTB write hits 553system.cpu.itb.write_misses 0 # DTB write misses 554system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 555system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 556system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 557system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID 558system.cpu.itb.flush_entries 53042 # Number of entries that have been flushed from TLB 559system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 560system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 561system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 562system.cpu.itb.perms_faults 369633 # Number of TLB faults due to permissions restrictions 563system.cpu.itb.read_accesses 0 # DTB read accesses 564system.cpu.itb.write_accesses 0 # DTB write accesses 565system.cpu.itb.inst_accesses 356760469 # ITB inst accesses 566system.cpu.itb.hits 356599136 # DTB hits 567system.cpu.itb.misses 161333 # DTB misses 568system.cpu.itb.accesses 356760469 # DTB accesses 569system.cpu.numCycles 1628081885 # number of cpu cycles simulated 570system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 571system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 572system.cpu.fetch.icacheStallCycles 644023121 # Number of cycles fetch is stalled on an Icache miss 573system.cpu.fetch.Insts 1000825975 # Number of instructions fetch has processed 574system.cpu.fetch.Branches 224297572 # Number of branches that fetch encountered 575system.cpu.fetch.predictedBranches 134308347 # Number of branches that fetch has predicted taken 576system.cpu.fetch.Cycles 897356081 # Number of cycles fetch has run and was not squashing or blocked 577system.cpu.fetch.SquashCycles 26042356 # Number of cycles fetch has spent squashing 578system.cpu.fetch.TlbCycles 3815311 # Number of cycles fetch has spent waiting for tlb 579system.cpu.fetch.MiscStallCycles 27434 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 580system.cpu.fetch.PendingTrapStallCycles 9297529 # Number of stall cycles due to pending traps 581system.cpu.fetch.PendingQuiesceStallCycles 1037208 # Number of stall cycles due to pending quiesce instructions 582system.cpu.fetch.IcacheWaitRetryStallCycles 977 # Number of stall cycles due to full MSHR 583system.cpu.fetch.CacheLines 356212596 # Number of cache lines fetched 584system.cpu.fetch.IcacheSquashes 6096332 # Number of outstanding Icache misses that were squashed 585system.cpu.fetch.ItlbSquashes 48851 # Number of outstanding ITLB misses that were squashed 586system.cpu.fetch.rateDist::samples 1568578839 # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::mean 0.747604 # Number of instructions fetched each cycle (Total) 588system.cpu.fetch.rateDist::stdev 1.149571 # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 590system.cpu.fetch.rateDist::0 1011708684 64.50% 64.50% # Number of instructions fetched each cycle (Total) 591system.cpu.fetch.rateDist::1 213717515 13.62% 78.12% # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::2 70499052 4.49% 82.62% # Number of instructions fetched each cycle (Total) 593system.cpu.fetch.rateDist::3 272653588 17.38% 100.00% # Number of instructions fetched each cycle (Total) 594system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 595system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::total 1568578839 # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.branchRate 0.137768 # Number of branch fetches per cycle 599system.cpu.fetch.rate 0.614727 # Number of inst fetches per cycle 600system.cpu.decode.IdleCycles 523834599 # Number of cycles decode is idle 601system.cpu.decode.BlockedCycles 552751170 # Number of cycles decode is blocked 602system.cpu.decode.RunCycles 433009950 # Number of cycles decode is running 603system.cpu.decode.UnblockCycles 49764409 # Number of cycles decode is unblocking 604system.cpu.decode.SquashCycles 9218711 # Number of cycles decode is squashing 605system.cpu.decode.BranchResolved 33629126 # Number of times decode resolved a branch 606system.cpu.decode.BranchMispred 3862659 # Number of times decode detected a branch misprediction 607system.cpu.decode.DecodedInsts 1084582874 # Number of instructions handled by decode 608system.cpu.decode.SquashedInsts 28977480 # Number of squashed instructions handled by decode 609system.cpu.rename.SquashCycles 9218711 # Number of cycles rename is squashing 610system.cpu.rename.IdleCycles 568372766 # Number of cycles rename is idle 611system.cpu.rename.BlockCycles 66217937 # Number of cycles rename is blocking 612system.cpu.rename.serializeStallCycles 371830406 # count of cycles rename stalled for serializing inst 613system.cpu.rename.RunCycles 438295981 # Number of cycles rename is running 614system.cpu.rename.UnblockCycles 114643038 # Number of cycles rename is unblocking 615system.cpu.rename.RenamedInsts 1064838864 # Number of instructions processed by rename 616system.cpu.rename.SquashedInsts 6775021 # Number of squashed instructions processed by rename 617system.cpu.rename.ROBFullEvents 5115924 # Number of times rename has blocked due to ROB full 618system.cpu.rename.IQFullEvents 336846 # Number of times rename has blocked due to IQ full 619system.cpu.rename.LQFullEvents 638712 # Number of times rename has blocked due to LQ full 620system.cpu.rename.SQFullEvents 63601510 # Number of times rename has blocked due to SQ full 621system.cpu.rename.FullRegisterEvents 20546 # Number of times there has been no free registers 622system.cpu.rename.RenamedOperands 1012729668 # Number of destination operands rename has renamed 623system.cpu.rename.RenameLookups 1640391275 # Number of register rename lookups that rename has made 624system.cpu.rename.int_rename_lookups 1259385666 # Number of integer rename lookups 625system.cpu.rename.fp_rename_lookups 1476745 # Number of floating rename lookups 626system.cpu.rename.CommittedMaps 947192806 # Number of HB maps that are committed 627system.cpu.rename.UndoneMaps 65536859 # Number of HB maps that are undone due to squashing 628system.cpu.rename.serializingInsts 26910765 # count of serializing insts renamed 629system.cpu.rename.tempSerializingInsts 23247835 # count of temporary serializing insts renamed 630system.cpu.rename.skidInsts 101832167 # count of insts added to the skid buffer 631system.cpu.memDep0.insertedLoads 173436334 # Number of loads inserted to the mem dependence unit. 632system.cpu.memDep0.insertedStores 151069277 # Number of stores inserted to the mem dependence unit. 633system.cpu.memDep0.conflictingLoads 9864131 # Number of conflicting loads. 634system.cpu.memDep0.conflictingStores 8951241 # Number of conflicting stores. 635system.cpu.iq.iqInstsAdded 1029826470 # Number of instructions added to the IQ (excludes non-spec) 636system.cpu.iq.iqNonSpecInstsAdded 27204925 # Number of non-speculative instructions added to the IQ 637system.cpu.iq.iqInstsIssued 1045231227 # Number of instructions issued 638system.cpu.iq.iqSquashedInstsIssued 3279121 # Number of squashed instructions issued 639system.cpu.iq.iqSquashedInstsExamined 60421557 # Number of squashed instructions iterated over during squash; mainly for profiling 640system.cpu.iq.iqSquashedOperandsExamined 33664917 # Number of squashed operands that are examined and possibly removed from graph 641system.cpu.iq.iqSquashedNonSpecRemoved 313528 # Number of squashed non-spec instructions that were removed 642system.cpu.iq.issued_per_cycle::samples 1568578839 # Number of insts issued each cycle 643system.cpu.iq.issued_per_cycle::mean 0.666356 # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::stdev 0.920348 # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 646system.cpu.iq.issued_per_cycle::0 921654762 58.76% 58.76% # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::1 333747896 21.28% 80.03% # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::2 234544221 14.95% 94.99% # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::3 72152324 4.60% 99.59% # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::4 6460263 0.41% 100.00% # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::5 19373 0.00% 100.00% # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 653system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::total 1568578839 # Number of insts issued each cycle 659system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 660system.cpu.iq.fu_full::IntAlu 57742950 35.03% 35.03% # attempts to use FU when none available 661system.cpu.iq.fu_full::IntMult 99825 0.06% 35.09% # attempts to use FU when none available 662system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.11% # attempts to use FU when none available 663system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available 664system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available 665system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available 666system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available 667system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available 668system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdFloatMisc 625 0.00% 35.11% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available 689system.cpu.iq.fu_full::MemRead 44231739 26.83% 61.94% # attempts to use FU when none available 690system.cpu.iq.fu_full::MemWrite 62727458 38.06% 100.00% # attempts to use FU when none available 691system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 692system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 693system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued 694system.cpu.iq.FU_type_0::IntAlu 719843938 68.87% 68.87% # Type of FU issued 695system.cpu.iq.FU_type_0::IntMult 2535420 0.24% 69.11% # Type of FU issued 696system.cpu.iq.FU_type_0::IntDiv 122954 0.01% 69.12% # Type of FU issued 697system.cpu.iq.FU_type_0::FloatAdd 380 0.00% 69.12% # Type of FU issued 698system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued 699system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued 700system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued 701system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued 702system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued 715system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued 716system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdFloatMisc 121377 0.01% 69.14% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued 723system.cpu.iq.FU_type_0::MemRead 173211987 16.57% 85.71% # Type of FU issued 724system.cpu.iq.FU_type_0::MemWrite 149395124 14.29% 100.00% # Type of FU issued 725system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 726system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 727system.cpu.iq.FU_type_0::total 1045231227 # Type of FU issued 728system.cpu.iq.rate 0.642002 # Inst issue rate 729system.cpu.iq.fu_busy_cnt 164829337 # FU busy when requested 730system.cpu.iq.fu_busy_rate 0.157697 # FU busy rate (busy events/executed inst) 731system.cpu.iq.int_inst_queue_reads 3824665950 # Number of integer instruction queue reads 732system.cpu.iq.int_inst_queue_writes 1116644145 # Number of integer instruction queue writes 733system.cpu.iq.int_inst_queue_wakeup_accesses 1027372601 # Number of integer instruction queue wakeup accesses 734system.cpu.iq.fp_inst_queue_reads 2483800 # Number of floating instruction queue reads 735system.cpu.iq.fp_inst_queue_writes 950168 # Number of floating instruction queue writes 736system.cpu.iq.fp_inst_queue_wakeup_accesses 912054 # Number of floating instruction queue wakeup accesses 737system.cpu.iq.int_alu_accesses 1208499896 # Number of integer alu accesses 738system.cpu.iq.fp_alu_accesses 1560667 # Number of floating point alu accesses 739system.cpu.iew.lsq.thread0.forwLoads 4304106 # Number of loads that had data forwarded from stores 740system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 741system.cpu.iew.lsq.thread0.squashedLoads 13785862 # Number of loads squashed 742system.cpu.iew.lsq.thread0.ignoredResponses 14456 # Number of memory responses ignored because the instruction is squashed 743system.cpu.iew.lsq.thread0.memOrderViolation 142604 # Number of memory ordering violations 744system.cpu.iew.lsq.thread0.squashedStores 6312817 # Number of stores squashed 745system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 746system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 747system.cpu.iew.lsq.thread0.rescheduledLoads 2532139 # Number of loads that were rescheduled 748system.cpu.iew.lsq.thread0.cacheBlocked 1442341 # Number of times an access to memory failed due to the cache being blocked 749system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 750system.cpu.iew.iewSquashCycles 9218711 # Number of cycles IEW is squashing 751system.cpu.iew.iewBlockCycles 7060342 # Number of cycles IEW is blocking 752system.cpu.iew.iewUnblockCycles 6923682 # Number of cycles IEW is unblocking 753system.cpu.iew.iewDispatchedInsts 1057253447 # Number of instructions dispatched to IQ 754system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 755system.cpu.iew.iewDispLoadInsts 173436334 # Number of dispatched load instructions 756system.cpu.iew.iewDispStoreInsts 151069277 # Number of dispatched store instructions 757system.cpu.iew.iewDispNonSpecInsts 22822922 # Number of dispatched non-speculative instructions 758system.cpu.iew.iewIQFullEvents 57401 # Number of times the IQ has become full, causing a stall 759system.cpu.iew.iewLSQFullEvents 6792645 # Number of times the LSQ has become full, causing a stall 760system.cpu.iew.memOrderViolationEvents 142604 # Number of memory order violations 761system.cpu.iew.predictedTakenIncorrect 3655399 # Number of branches that were predicted taken incorrectly 762system.cpu.iew.predictedNotTakenIncorrect 5100784 # Number of branches that were predicted not taken incorrectly 763system.cpu.iew.branchMispredicts 8756183 # Number of branch mispredicts detected at execute 764system.cpu.iew.iewExecutedInsts 1034064574 # Number of executed instructions 765system.cpu.iew.iewExecLoadInsts 169319677 # Number of load instructions executed 766system.cpu.iew.iewExecSquashedInsts 10227871 # Number of squashed instructions skipped in execute 767system.cpu.iew.exec_swp 0 # number of swp insts executed 768system.cpu.iew.exec_nop 222052 # number of nop insts executed 769system.cpu.iew.exec_refs 316816486 # number of memory reference insts executed 770system.cpu.iew.exec_branches 196206176 # Number of branches executed 771system.cpu.iew.exec_stores 147496809 # Number of stores executed 772system.cpu.iew.exec_rate 0.635143 # Inst execution rate 773system.cpu.iew.wb_sent 1029092840 # cumulative count of insts sent to commit 774system.cpu.iew.wb_count 1028284655 # cumulative count of insts written-back 775system.cpu.iew.wb_producers 437786008 # num instructions producing a value 776system.cpu.iew.wb_consumers 708231099 # num instructions consuming a value 777system.cpu.iew.wb_rate 0.631593 # insts written-back per cycle 778system.cpu.iew.wb_fanout 0.618140 # average fanout of values written-back 779system.cpu.commit.commitSquashedInsts 51332329 # The number of squashed insts skipped by commit 780system.cpu.commit.commitNonSpecStalls 26891397 # The number of times commit has been forced to stall to communicate backwards 781system.cpu.commit.branchMispredicts 8391320 # The number of times a branch was mispredicted 782system.cpu.commit.committed_per_cycle::samples 1556613982 # Number of insts commited each cycle 783system.cpu.commit.committed_per_cycle::mean 0.640242 # Number of insts commited each cycle 784system.cpu.commit.committed_per_cycle::stdev 1.274821 # Number of insts commited each cycle 785system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::0 1044975044 67.13% 67.13% # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::1 287768132 18.49% 85.62% # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::2 120346121 7.73% 93.35% # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::3 36551788 2.35% 95.70% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::4 28453995 1.83% 97.53% # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::5 14010396 0.90% 98.43% # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::6 8635881 0.55% 98.98% # Number of insts commited each cycle 793system.cpu.commit.committed_per_cycle::7 4170150 0.27% 99.25% # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::8 11702475 0.75% 100.00% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::total 1556613982 # Number of insts commited each cycle 799system.cpu.commit.committedInsts 848158120 # Number of instructions committed 800system.cpu.commit.committedOps 996609834 # Number of ops (including micro ops) committed 801system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 802system.cpu.commit.refs 304406931 # Number of memory references committed 803system.cpu.commit.loads 159650471 # Number of loads committed 804system.cpu.commit.membars 6926449 # Number of memory barriers committed 805system.cpu.commit.branches 189300112 # Number of branches committed 806system.cpu.commit.fp_insts 898776 # Number of committed floating point instructions. 807system.cpu.commit.int_insts 915651780 # Number of committed integer instructions. 808system.cpu.commit.function_calls 25280403 # Number of function calls committed. 809system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 810system.cpu.commit.op_class_0::IntAlu 689842559 69.22% 69.22% # Class of committed instruction 811system.cpu.commit.op_class_0::IntMult 2150231 0.22% 69.43% # Class of committed instruction 812system.cpu.commit.op_class_0::IntDiv 98139 0.01% 69.44% # Class of committed instruction 813system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction 814system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction 815system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction 816system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction 817system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction 818system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction 819system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction 820system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction 821system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction 822system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction 828system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction 829system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction 832system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction 833system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction 834system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 839system.cpu.commit.op_class_0::MemRead 159650471 16.02% 85.48% # Class of committed instruction 840system.cpu.commit.op_class_0::MemWrite 144756460 14.52% 100.00% # Class of committed instruction 841system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 842system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 843system.cpu.commit.op_class_0::total 996609834 # Class of committed instruction 844system.cpu.commit.bw_lim_events 11702475 # number cycles where commit BW limit reached 845system.cpu.rob.rob_reads 2585312705 # The number of ROB reads 846system.cpu.rob.rob_writes 2107755396 # The number of ROB writes 847system.cpu.timesIdled 8146940 # Number of times that the entire CPU went into an idle state and unscheduled itself 848system.cpu.idleCycles 59503046 # Total number of cycles that the CPU has spent unscheduled due to idling 849system.cpu.quiesceCycles 101026198411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 850system.cpu.committedInsts 848158120 # Number of Instructions Simulated 851system.cpu.committedOps 996609834 # Number of Ops (including micro ops) Simulated 852system.cpu.cpi 1.919550 # CPI: Cycles Per Instruction 853system.cpu.cpi_total 1.919550 # CPI: Total CPI of All Threads 854system.cpu.ipc 0.520955 # IPC: Instructions Per Cycle 855system.cpu.ipc_total 0.520955 # IPC: Total IPC of All Threads 856system.cpu.int_regfile_reads 1224113620 # number of integer regfile reads 857system.cpu.int_regfile_writes 731133953 # number of integer regfile writes 858system.cpu.fp_regfile_reads 1465257 # number of floating regfile reads 859system.cpu.fp_regfile_writes 785096 # number of floating regfile writes 860system.cpu.cc_regfile_reads 225210240 # number of cc regfile reads 861system.cpu.cc_regfile_writes 225863400 # number of cc regfile writes 862system.cpu.misc_regfile_reads 2555640420 # number of misc regfile reads 863system.cpu.misc_regfile_writes 26930775 # number of misc regfile writes 864system.cpu.dcache.tags.replacements 9682749 # number of replacements 865system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use 866system.cpu.dcache.tags.total_refs 283083620 # Total number of references to valid blocks. 867system.cpu.dcache.tags.sampled_refs 9683261 # Sample count of references to valid blocks. 868system.cpu.dcache.tags.avg_refs 29.234327 # Average number of references to valid blocks. 869system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. 870system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor 871system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy 872system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy 873system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 874system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 875system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 876system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 877system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 878system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 879system.cpu.dcache.tags.tag_accesses 1236470793 # Number of tag accesses 880system.cpu.dcache.tags.data_accesses 1236470793 # Number of data accesses 881system.cpu.dcache.ReadReq_hits::cpu.data 147113779 # number of ReadReq hits 882system.cpu.dcache.ReadReq_hits::total 147113779 # number of ReadReq hits 883system.cpu.dcache.WriteReq_hits::cpu.data 128236098 # number of WriteReq hits 884system.cpu.dcache.WriteReq_hits::total 128236098 # number of WriteReq hits 885system.cpu.dcache.SoftPFReq_hits::cpu.data 377977 # number of SoftPFReq hits 886system.cpu.dcache.SoftPFReq_hits::total 377977 # number of SoftPFReq hits 887system.cpu.dcache.WriteLineReq_hits::cpu.data 323653 # number of WriteLineReq hits 888system.cpu.dcache.WriteLineReq_hits::total 323653 # number of WriteLineReq hits 889system.cpu.dcache.LoadLockedReq_hits::cpu.data 3296961 # number of LoadLockedReq hits 890system.cpu.dcache.LoadLockedReq_hits::total 3296961 # number of LoadLockedReq hits 891system.cpu.dcache.StoreCondReq_hits::cpu.data 3691090 # number of StoreCondReq hits 892system.cpu.dcache.StoreCondReq_hits::total 3691090 # number of StoreCondReq hits 893system.cpu.dcache.demand_hits::cpu.data 275349877 # number of demand (read+write) hits 894system.cpu.dcache.demand_hits::total 275349877 # number of demand (read+write) hits 895system.cpu.dcache.overall_hits::cpu.data 275727854 # number of overall hits 896system.cpu.dcache.overall_hits::total 275727854 # number of overall hits 897system.cpu.dcache.ReadReq_misses::cpu.data 9547222 # number of ReadReq misses 898system.cpu.dcache.ReadReq_misses::total 9547222 # number of ReadReq misses 899system.cpu.dcache.WriteReq_misses::cpu.data 11260039 # number of WriteReq misses 900system.cpu.dcache.WriteReq_misses::total 11260039 # number of WriteReq misses 901system.cpu.dcache.SoftPFReq_misses::cpu.data 1170114 # number of SoftPFReq misses 902system.cpu.dcache.SoftPFReq_misses::total 1170114 # number of SoftPFReq misses 903system.cpu.dcache.WriteLineReq_misses::cpu.data 1233803 # number of WriteLineReq misses 904system.cpu.dcache.WriteLineReq_misses::total 1233803 # number of WriteLineReq misses 905system.cpu.dcache.LoadLockedReq_misses::cpu.data 446138 # number of LoadLockedReq misses 906system.cpu.dcache.LoadLockedReq_misses::total 446138 # number of LoadLockedReq misses 907system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses 908system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses 909system.cpu.dcache.demand_misses::cpu.data 20807261 # number of demand (read+write) misses 910system.cpu.dcache.demand_misses::total 20807261 # number of demand (read+write) misses 911system.cpu.dcache.overall_misses::cpu.data 21977375 # number of overall misses 912system.cpu.dcache.overall_misses::total 21977375 # number of overall misses 913system.cpu.dcache.ReadReq_miss_latency::cpu.data 168019956500 # number of ReadReq miss cycles 914system.cpu.dcache.ReadReq_miss_latency::total 168019956500 # number of ReadReq miss cycles 915system.cpu.dcache.WriteReq_miss_latency::cpu.data 444932022751 # number of WriteReq miss cycles 916system.cpu.dcache.WriteReq_miss_latency::total 444932022751 # number of WriteReq miss cycles 917system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52262346938 # number of WriteLineReq miss cycles 918system.cpu.dcache.WriteLineReq_miss_latency::total 52262346938 # number of WriteLineReq miss cycles 919system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6889431000 # number of LoadLockedReq miss cycles 920system.cpu.dcache.LoadLockedReq_miss_latency::total 6889431000 # number of LoadLockedReq miss cycles 921system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles 922system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles 923system.cpu.dcache.demand_miss_latency::cpu.data 612951979251 # number of demand (read+write) miss cycles 924system.cpu.dcache.demand_miss_latency::total 612951979251 # number of demand (read+write) miss cycles 925system.cpu.dcache.overall_miss_latency::cpu.data 612951979251 # number of overall miss cycles 926system.cpu.dcache.overall_miss_latency::total 612951979251 # number of overall miss cycles 927system.cpu.dcache.ReadReq_accesses::cpu.data 156661001 # number of ReadReq accesses(hits+misses) 928system.cpu.dcache.ReadReq_accesses::total 156661001 # number of ReadReq accesses(hits+misses) 929system.cpu.dcache.WriteReq_accesses::cpu.data 139496137 # number of WriteReq accesses(hits+misses) 930system.cpu.dcache.WriteReq_accesses::total 139496137 # number of WriteReq accesses(hits+misses) 931system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548091 # number of SoftPFReq accesses(hits+misses) 932system.cpu.dcache.SoftPFReq_accesses::total 1548091 # number of SoftPFReq accesses(hits+misses) 933system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) 934system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) 935system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3743099 # number of LoadLockedReq accesses(hits+misses) 936system.cpu.dcache.LoadLockedReq_accesses::total 3743099 # number of LoadLockedReq accesses(hits+misses) 937system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691096 # number of StoreCondReq accesses(hits+misses) 938system.cpu.dcache.StoreCondReq_accesses::total 3691096 # number of StoreCondReq accesses(hits+misses) 939system.cpu.dcache.demand_accesses::cpu.data 296157138 # number of demand (read+write) accesses 940system.cpu.dcache.demand_accesses::total 296157138 # number of demand (read+write) accesses 941system.cpu.dcache.overall_accesses::cpu.data 297705229 # number of overall (read+write) accesses 942system.cpu.dcache.overall_accesses::total 297705229 # number of overall (read+write) accesses 943system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses 944system.cpu.dcache.ReadReq_miss_rate::total 0.060942 # miss rate for ReadReq accesses 945system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080719 # miss rate for WriteReq accesses 946system.cpu.dcache.WriteReq_miss_rate::total 0.080719 # miss rate for WriteReq accesses 947system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.755843 # miss rate for SoftPFReq accesses 948system.cpu.dcache.SoftPFReq_miss_rate::total 0.755843 # miss rate for SoftPFReq accesses 949system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792191 # miss rate for WriteLineReq accesses 950system.cpu.dcache.WriteLineReq_miss_rate::total 0.792191 # miss rate for WriteLineReq accesses 951system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119189 # miss rate for LoadLockedReq accesses 952system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119189 # miss rate for LoadLockedReq accesses 953system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses 954system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses 955system.cpu.dcache.demand_miss_rate::cpu.data 0.070258 # miss rate for demand accesses 956system.cpu.dcache.demand_miss_rate::total 0.070258 # miss rate for demand accesses 957system.cpu.dcache.overall_miss_rate::cpu.data 0.073823 # miss rate for overall accesses 958system.cpu.dcache.overall_miss_rate::total 0.073823 # miss rate for overall accesses 959system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.832048 # average ReadReq miss latency 960system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048 # average ReadReq miss latency 961system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371 # average WriteReq miss latency 962system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371 # average WriteReq miss latency 963system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228 # average WriteLineReq miss latency 964system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228 # average WriteLineReq miss latency 965system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574 # average LoadLockedReq miss latency 966system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574 # average LoadLockedReq miss latency 967system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333 # average StoreCondReq miss latency 968system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333 # average StoreCondReq miss latency 969system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569 # average overall miss latency 970system.cpu.dcache.demand_avg_miss_latency::total 29458.561569 # average overall miss latency 971system.cpu.dcache.overall_avg_miss_latency::cpu.data 27890.136072 # average overall miss latency 972system.cpu.dcache.overall_avg_miss_latency::total 27890.136072 # average overall miss latency 973system.cpu.dcache.blocked_cycles::no_mshrs 32144751 # number of cycles access was blocked 974system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 975system.cpu.dcache.blocked::no_mshrs 1600072 # number of cycles access was blocked 976system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 977system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089565 # average number of cycles each access was blocked 978system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 979system.cpu.dcache.fast_writes 0 # number of fast writes performed 980system.cpu.dcache.cache_copies 0 # number of cache copies performed 981system.cpu.dcache.writebacks::writebacks 7504258 # number of writebacks 982system.cpu.dcache.writebacks::total 7504258 # number of writebacks 983system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4442516 # number of ReadReq MSHR hits 984system.cpu.dcache.ReadReq_mshr_hits::total 4442516 # number of ReadReq MSHR hits 985system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9255736 # number of WriteReq MSHR hits 986system.cpu.dcache.WriteReq_mshr_hits::total 9255736 # number of WriteReq MSHR hits 987system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7058 # number of WriteLineReq MSHR hits 988system.cpu.dcache.WriteLineReq_mshr_hits::total 7058 # number of WriteLineReq MSHR hits 989system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218425 # number of LoadLockedReq MSHR hits 990system.cpu.dcache.LoadLockedReq_mshr_hits::total 218425 # number of LoadLockedReq MSHR hits 991system.cpu.dcache.demand_mshr_hits::cpu.data 13698252 # number of demand (read+write) MSHR hits 992system.cpu.dcache.demand_mshr_hits::total 13698252 # number of demand (read+write) MSHR hits 993system.cpu.dcache.overall_mshr_hits::cpu.data 13698252 # number of overall MSHR hits 994system.cpu.dcache.overall_mshr_hits::total 13698252 # number of overall MSHR hits 995system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5104706 # number of ReadReq MSHR misses 996system.cpu.dcache.ReadReq_mshr_misses::total 5104706 # number of ReadReq MSHR misses 997system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2004303 # number of WriteReq MSHR misses 998system.cpu.dcache.WriteReq_mshr_misses::total 2004303 # number of WriteReq MSHR misses 999system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163297 # number of SoftPFReq MSHR misses 1000system.cpu.dcache.SoftPFReq_mshr_misses::total 1163297 # number of SoftPFReq MSHR misses 1001system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226745 # number of WriteLineReq MSHR misses 1002system.cpu.dcache.WriteLineReq_mshr_misses::total 1226745 # number of WriteLineReq MSHR misses 1003system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227713 # number of LoadLockedReq MSHR misses 1004system.cpu.dcache.LoadLockedReq_mshr_misses::total 227713 # number of LoadLockedReq MSHR misses 1005system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses 1006system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses 1007system.cpu.dcache.demand_mshr_misses::cpu.data 7109009 # number of demand (read+write) MSHR misses 1008system.cpu.dcache.demand_mshr_misses::total 7109009 # number of demand (read+write) MSHR misses 1009system.cpu.dcache.overall_mshr_misses::cpu.data 8272306 # number of overall MSHR misses 1010system.cpu.dcache.overall_mshr_misses::total 8272306 # number of overall MSHR misses 1011system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 1012system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable 1013system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 1014system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 1015system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 1016system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses 1017system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84710979000 # number of ReadReq MSHR miss cycles 1018system.cpu.dcache.ReadReq_mshr_miss_latency::total 84710979000 # number of ReadReq MSHR miss cycles 1019system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77672671390 # number of WriteReq MSHR miss cycles 1020system.cpu.dcache.WriteReq_mshr_miss_latency::total 77672671390 # number of WriteReq MSHR miss cycles 1021system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23648689000 # number of SoftPFReq MSHR miss cycles 1022system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23648689000 # number of SoftPFReq MSHR miss cycles 1023system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50594844438 # number of WriteLineReq MSHR miss cycles 1024system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50594844438 # number of WriteLineReq MSHR miss cycles 1025system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3209583500 # number of LoadLockedReq MSHR miss cycles 1026system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3209583500 # number of LoadLockedReq MSHR miss cycles 1027system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 279500 # number of StoreCondReq MSHR miss cycles 1028system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 279500 # number of StoreCondReq MSHR miss cycles 1029system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162383650390 # number of demand (read+write) MSHR miss cycles 1030system.cpu.dcache.demand_mshr_miss_latency::total 162383650390 # number of demand (read+write) MSHR miss cycles 1031system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390 # number of overall MSHR miss cycles 1032system.cpu.dcache.overall_mshr_miss_latency::total 186032339390 # number of overall MSHR miss cycles 1033system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191842000 # number of ReadReq MSHR uncacheable cycles 1034system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191842000 # number of ReadReq MSHR uncacheable cycles 1035system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228406964 # number of WriteReq MSHR uncacheable cycles 1036system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228406964 # number of WriteReq MSHR uncacheable cycles 1037system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420248964 # number of overall MSHR uncacheable cycles 1038system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420248964 # number of overall MSHR uncacheable cycles 1039system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032584 # mshr miss rate for ReadReq accesses 1040system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032584 # mshr miss rate for ReadReq accesses 1041system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014368 # mshr miss rate for WriteReq accesses 1042system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014368 # mshr miss rate for WriteReq accesses 1043system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751440 # mshr miss rate for SoftPFReq accesses 1044system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751440 # mshr miss rate for SoftPFReq accesses 1045system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787659 # mshr miss rate for WriteLineReq accesses 1046system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787659 # mshr miss rate for WriteLineReq accesses 1047system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060835 # mshr miss rate for LoadLockedReq accesses 1048system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060835 # mshr miss rate for LoadLockedReq accesses 1049system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses 1050system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses 1051system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024004 # mshr miss rate for demand accesses 1052system.cpu.dcache.demand_mshr_miss_rate::total 0.024004 # mshr miss rate for demand accesses 1053system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027787 # mshr miss rate for overall accesses 1054system.cpu.dcache.overall_mshr_miss_rate::total 0.027787 # mshr miss rate for overall accesses 1055system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220 # average ReadReq mshr miss latency 1056system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220 # average ReadReq mshr miss latency 1057system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38752.958704 # average WriteReq mshr miss latency 1058system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38752.958704 # average WriteReq mshr miss latency 1059system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20329.020878 # average SoftPFReq mshr miss latency 1060system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878 # average SoftPFReq mshr miss latency 1061system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41243.163362 # average WriteLineReq mshr miss latency 1062system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41243.163362 # average WriteLineReq mshr miss latency 1063system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14094.862832 # average LoadLockedReq mshr miss latency 1064system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832 # average LoadLockedReq mshr miss latency 1065system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46583.333333 # average StoreCondReq mshr miss latency 1066system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333 # average StoreCondReq mshr miss latency 1067system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132 # average overall mshr miss latency 1068system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132 # average overall mshr miss latency 1069system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828 # average overall mshr miss latency 1070system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828 # average overall mshr miss latency 1071system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495 # average ReadReq mshr uncacheable latency 1072system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495 # average ReadReq mshr uncacheable latency 1073system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346 # average WriteReq mshr uncacheable latency 1074system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346 # average WriteReq mshr uncacheable latency 1075system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.804257 # average overall mshr uncacheable latency 1076system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.804257 # average overall mshr uncacheable latency 1077system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1078system.cpu.icache.tags.replacements 15019267 # number of replacements 1079system.cpu.icache.tags.tagsinuse 511.928693 # Cycle average of tags in use 1080system.cpu.icache.tags.total_refs 340404778 # Total number of references to valid blocks. 1081system.cpu.icache.tags.sampled_refs 15019779 # Sample count of references to valid blocks. 1082system.cpu.icache.tags.avg_refs 22.663767 # Average number of references to valid blocks. 1083system.cpu.icache.tags.warmup_cycle 20448016500 # Cycle when the warmup percentage was hit. 1084system.cpu.icache.tags.occ_blocks::cpu.inst 511.928693 # Average occupied blocks per requestor 1085system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy 1086system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy 1087system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1088system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 1089system.cpu.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id 1090system.cpu.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id 1091system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1092system.cpu.icache.tags.tag_accesses 371211305 # Number of tag accesses 1093system.cpu.icache.tags.data_accesses 371211305 # Number of data accesses 1094system.cpu.icache.ReadReq_hits::cpu.inst 340404778 # number of ReadReq hits 1095system.cpu.icache.ReadReq_hits::total 340404778 # number of ReadReq hits 1096system.cpu.icache.demand_hits::cpu.inst 340404778 # number of demand (read+write) hits 1097system.cpu.icache.demand_hits::total 340404778 # number of demand (read+write) hits 1098system.cpu.icache.overall_hits::cpu.inst 340404778 # number of overall hits 1099system.cpu.icache.overall_hits::total 340404778 # number of overall hits 1100system.cpu.icache.ReadReq_misses::cpu.inst 15786521 # number of ReadReq misses 1101system.cpu.icache.ReadReq_misses::total 15786521 # number of ReadReq misses 1102system.cpu.icache.demand_misses::cpu.inst 15786521 # number of demand (read+write) misses 1103system.cpu.icache.demand_misses::total 15786521 # number of demand (read+write) misses 1104system.cpu.icache.overall_misses::cpu.inst 15786521 # number of overall misses 1105system.cpu.icache.overall_misses::total 15786521 # number of overall misses 1106system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380 # number of ReadReq miss cycles 1107system.cpu.icache.ReadReq_miss_latency::total 213423777380 # number of ReadReq miss cycles 1108system.cpu.icache.demand_miss_latency::cpu.inst 213423777380 # number of demand (read+write) miss cycles 1109system.cpu.icache.demand_miss_latency::total 213423777380 # number of demand (read+write) miss cycles 1110system.cpu.icache.overall_miss_latency::cpu.inst 213423777380 # number of overall miss cycles 1111system.cpu.icache.overall_miss_latency::total 213423777380 # number of overall miss cycles 1112system.cpu.icache.ReadReq_accesses::cpu.inst 356191299 # number of ReadReq accesses(hits+misses) 1113system.cpu.icache.ReadReq_accesses::total 356191299 # number of ReadReq accesses(hits+misses) 1114system.cpu.icache.demand_accesses::cpu.inst 356191299 # number of demand (read+write) accesses 1115system.cpu.icache.demand_accesses::total 356191299 # number of demand (read+write) accesses 1116system.cpu.icache.overall_accesses::cpu.inst 356191299 # number of overall (read+write) accesses 1117system.cpu.icache.overall_accesses::total 356191299 # number of overall (read+write) accesses 1118system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044320 # miss rate for ReadReq accesses 1119system.cpu.icache.ReadReq_miss_rate::total 0.044320 # miss rate for ReadReq accesses 1120system.cpu.icache.demand_miss_rate::cpu.inst 0.044320 # miss rate for demand accesses 1121system.cpu.icache.demand_miss_rate::total 0.044320 # miss rate for demand accesses 1122system.cpu.icache.overall_miss_rate::cpu.inst 0.044320 # miss rate for overall accesses 1123system.cpu.icache.overall_miss_rate::total 0.044320 # miss rate for overall accesses 1124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13519.367401 # average ReadReq miss latency 1125system.cpu.icache.ReadReq_avg_miss_latency::total 13519.367401 # average ReadReq miss latency 1126system.cpu.icache.demand_avg_miss_latency::cpu.inst 13519.367401 # average overall miss latency 1127system.cpu.icache.demand_avg_miss_latency::total 13519.367401 # average overall miss latency 1128system.cpu.icache.overall_avg_miss_latency::cpu.inst 13519.367401 # average overall miss latency 1129system.cpu.icache.overall_avg_miss_latency::total 13519.367401 # average overall miss latency 1130system.cpu.icache.blocked_cycles::no_mshrs 24648 # number of cycles access was blocked 1131system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1132system.cpu.icache.blocked::no_mshrs 1434 # number of cycles access was blocked 1133system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1134system.cpu.icache.avg_blocked_cycles::no_mshrs 17.188285 # average number of cycles each access was blocked 1135system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1136system.cpu.icache.fast_writes 0 # number of fast writes performed 1137system.cpu.icache.cache_copies 0 # number of cache copies performed 1138system.cpu.icache.writebacks::writebacks 15019267 # number of writebacks 1139system.cpu.icache.writebacks::total 15019267 # number of writebacks 1140system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766515 # number of ReadReq MSHR hits 1141system.cpu.icache.ReadReq_mshr_hits::total 766515 # number of ReadReq MSHR hits 1142system.cpu.icache.demand_mshr_hits::cpu.inst 766515 # number of demand (read+write) MSHR hits 1143system.cpu.icache.demand_mshr_hits::total 766515 # number of demand (read+write) MSHR hits 1144system.cpu.icache.overall_mshr_hits::cpu.inst 766515 # number of overall MSHR hits 1145system.cpu.icache.overall_mshr_hits::total 766515 # number of overall MSHR hits 1146system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15020006 # number of ReadReq MSHR misses 1147system.cpu.icache.ReadReq_mshr_misses::total 15020006 # number of ReadReq MSHR misses 1148system.cpu.icache.demand_mshr_misses::cpu.inst 15020006 # number of demand (read+write) MSHR misses 1149system.cpu.icache.demand_mshr_misses::total 15020006 # number of demand (read+write) MSHR misses 1150system.cpu.icache.overall_mshr_misses::cpu.inst 15020006 # number of overall MSHR misses 1151system.cpu.icache.overall_mshr_misses::total 15020006 # number of overall MSHR misses 1152system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 1153system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable 1154system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 1155system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses 1156system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191135995392 # number of ReadReq MSHR miss cycles 1157system.cpu.icache.ReadReq_mshr_miss_latency::total 191135995392 # number of ReadReq MSHR miss cycles 1158system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191135995392 # number of demand (read+write) MSHR miss cycles 1159system.cpu.icache.demand_mshr_miss_latency::total 191135995392 # number of demand (read+write) MSHR miss cycles 1160system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191135995392 # number of overall MSHR miss cycles 1161system.cpu.icache.overall_mshr_miss_latency::total 191135995392 # number of overall MSHR miss cycles 1162system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938000 # number of ReadReq MSHR uncacheable cycles 1163system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938000 # number of ReadReq MSHR uncacheable cycles 1164system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938000 # number of overall MSHR uncacheable cycles 1165system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938000 # number of overall MSHR uncacheable cycles 1166system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for ReadReq accesses 1167system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042168 # mshr miss rate for ReadReq accesses 1168system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for demand accesses 1169system.cpu.icache.demand_mshr_miss_rate::total 0.042168 # mshr miss rate for demand accesses 1170system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for overall accesses 1171system.cpu.icache.overall_mshr_miss_rate::total 0.042168 # mshr miss rate for overall accesses 1172system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12725.427366 # average ReadReq mshr miss latency 1173system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.427366 # average ReadReq mshr miss latency 1174system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.427366 # average overall mshr miss latency 1175system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.427366 # average overall mshr miss latency 1176system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.427366 # average overall mshr miss latency 1177system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.427366 # average overall mshr miss latency 1178system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average ReadReq mshr uncacheable latency 1179system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243 # average ReadReq mshr uncacheable latency 1180system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average overall mshr uncacheable latency 1181system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243 # average overall mshr uncacheable latency 1182system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1183system.cpu.l2cache.tags.replacements 1144462 # number of replacements 1184system.cpu.l2cache.tags.tagsinuse 65297.598211 # Cycle average of tags in use 1185system.cpu.l2cache.tags.total_refs 46017703 # Total number of references to valid blocks. 1186system.cpu.l2cache.tags.sampled_refs 1207114 # Sample count of references to valid blocks. 1187system.cpu.l2cache.tags.avg_refs 38.122085 # Average number of references to valid blocks. 1188system.cpu.l2cache.tags.warmup_cycle 4511701500 # Cycle when the warmup percentage was hit. 1189system.cpu.l2cache.tags.occ_blocks::writebacks 37171.608657 # Average occupied blocks per requestor 1190system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 289.486238 # Average occupied blocks per requestor 1191system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.841209 # Average occupied blocks per requestor 1192system.cpu.l2cache.tags.occ_blocks::cpu.inst 7858.021749 # Average occupied blocks per requestor 1193system.cpu.l2cache.tags.occ_blocks::cpu.data 19528.640359 # Average occupied blocks per requestor 1194system.cpu.l2cache.tags.occ_percent::writebacks 0.567194 # Average percentage of cache occupancy 1195system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004417 # Average percentage of cache occupancy 1196system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006864 # Average percentage of cache occupancy 1197system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119904 # Average percentage of cache occupancy 1198system.cpu.l2cache.tags.occ_percent::cpu.data 0.297983 # Average percentage of cache occupancy 1199system.cpu.l2cache.tags.occ_percent::total 0.996362 # Average percentage of cache occupancy 1200system.cpu.l2cache.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id 1201system.cpu.l2cache.tags.occ_task_id_blocks::1024 62375 # Occupied blocks per task id 1202system.cpu.l2cache.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id 1203system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 1204system.cpu.l2cache.tags.age_task_id_blocks_1024::1 573 # Occupied blocks per task id 1205system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2650 # Occupied blocks per task id 1206system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5065 # Occupied blocks per task id 1207system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54017 # Occupied blocks per task id 1208system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004227 # Percentage of cache occupancy per task id 1209system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951767 # Percentage of cache occupancy per task id 1210system.cpu.l2cache.tags.tag_accesses 408203781 # Number of tag accesses 1211system.cpu.l2cache.tags.data_accesses 408203781 # Number of data accesses 1212system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 781080 # number of ReadReq hits 1213system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 297784 # number of ReadReq hits 1214system.cpu.l2cache.ReadReq_hits::total 1078864 # number of ReadReq hits 1215system.cpu.l2cache.WritebackDirty_hits::writebacks 7504258 # number of WritebackDirty hits 1216system.cpu.l2cache.WritebackDirty_hits::total 7504258 # number of WritebackDirty hits 1217system.cpu.l2cache.WritebackClean_hits::writebacks 15016613 # number of WritebackClean hits 1218system.cpu.l2cache.WritebackClean_hits::total 15016613 # number of WritebackClean hits 1219system.cpu.l2cache.UpgradeReq_hits::cpu.data 9434 # number of UpgradeReq hits 1220system.cpu.l2cache.UpgradeReq_hits::total 9434 # number of UpgradeReq hits 1221system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1222system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 1223system.cpu.l2cache.ReadExReq_hits::cpu.data 1568735 # number of ReadExReq hits 1224system.cpu.l2cache.ReadExReq_hits::total 1568735 # number of ReadExReq hits 1225system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14937013 # number of ReadCleanReq hits 1226system.cpu.l2cache.ReadCleanReq_hits::total 14937013 # number of ReadCleanReq hits 1227system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6236325 # number of ReadSharedReq hits 1228system.cpu.l2cache.ReadSharedReq_hits::total 6236325 # number of ReadSharedReq hits 1229system.cpu.l2cache.InvalidateReq_hits::cpu.data 728917 # number of InvalidateReq hits 1230system.cpu.l2cache.InvalidateReq_hits::total 728917 # number of InvalidateReq hits 1231system.cpu.l2cache.demand_hits::cpu.dtb.walker 781080 # number of demand (read+write) hits 1232system.cpu.l2cache.demand_hits::cpu.itb.walker 297784 # number of demand (read+write) hits 1233system.cpu.l2cache.demand_hits::cpu.inst 14937013 # number of demand (read+write) hits 1234system.cpu.l2cache.demand_hits::cpu.data 7805060 # number of demand (read+write) hits 1235system.cpu.l2cache.demand_hits::total 23820937 # number of demand (read+write) hits 1236system.cpu.l2cache.overall_hits::cpu.dtb.walker 781080 # number of overall hits 1237system.cpu.l2cache.overall_hits::cpu.itb.walker 297784 # number of overall hits 1238system.cpu.l2cache.overall_hits::cpu.inst 14937013 # number of overall hits 1239system.cpu.l2cache.overall_hits::cpu.data 7805060 # number of overall hits 1240system.cpu.l2cache.overall_hits::total 23820937 # number of overall hits 1241system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3313 # number of ReadReq misses 1242system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3248 # number of ReadReq misses 1243system.cpu.l2cache.ReadReq_misses::total 6561 # number of ReadReq misses 1244system.cpu.l2cache.UpgradeReq_misses::cpu.data 34060 # number of UpgradeReq misses 1245system.cpu.l2cache.UpgradeReq_misses::total 34060 # number of UpgradeReq misses 1246system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1247system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1248system.cpu.l2cache.ReadExReq_misses::cpu.data 395411 # number of ReadExReq misses 1249system.cpu.l2cache.ReadExReq_misses::total 395411 # number of ReadExReq misses 1250system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82785 # number of ReadCleanReq misses 1251system.cpu.l2cache.ReadCleanReq_misses::total 82785 # number of ReadCleanReq misses 1252system.cpu.l2cache.ReadSharedReq_misses::cpu.data 256057 # number of ReadSharedReq misses 1253system.cpu.l2cache.ReadSharedReq_misses::total 256057 # number of ReadSharedReq misses 1254system.cpu.l2cache.InvalidateReq_misses::cpu.data 497828 # number of InvalidateReq misses 1255system.cpu.l2cache.InvalidateReq_misses::total 497828 # number of InvalidateReq misses 1256system.cpu.l2cache.demand_misses::cpu.dtb.walker 3313 # number of demand (read+write) misses 1257system.cpu.l2cache.demand_misses::cpu.itb.walker 3248 # number of demand (read+write) misses 1258system.cpu.l2cache.demand_misses::cpu.inst 82785 # number of demand (read+write) misses 1259system.cpu.l2cache.demand_misses::cpu.data 651468 # number of demand (read+write) misses 1260system.cpu.l2cache.demand_misses::total 740814 # number of demand (read+write) misses 1261system.cpu.l2cache.overall_misses::cpu.dtb.walker 3313 # number of overall misses 1262system.cpu.l2cache.overall_misses::cpu.itb.walker 3248 # number of overall misses 1263system.cpu.l2cache.overall_misses::cpu.inst 82785 # number of overall misses 1264system.cpu.l2cache.overall_misses::cpu.data 651468 # number of overall misses 1265system.cpu.l2cache.overall_misses::total 740814 # number of overall misses 1266system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 456063500 # number of ReadReq miss cycles 1267system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 443832500 # number of ReadReq miss cycles 1268system.cpu.l2cache.ReadReq_miss_latency::total 899896000 # number of ReadReq miss cycles 1269system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1363124000 # number of UpgradeReq miss cycles 1270system.cpu.l2cache.UpgradeReq_miss_latency::total 1363124000 # number of UpgradeReq miss cycles 1271system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 1272system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 1273system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55147182500 # number of ReadExReq miss cycles 1274system.cpu.l2cache.ReadExReq_miss_latency::total 55147182500 # number of ReadExReq miss cycles 1275system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11136291500 # number of ReadCleanReq miss cycles 1276system.cpu.l2cache.ReadCleanReq_miss_latency::total 11136291500 # number of ReadCleanReq miss cycles 1277system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35748767000 # number of ReadSharedReq miss cycles 1278system.cpu.l2cache.ReadSharedReq_miss_latency::total 35748767000 # number of ReadSharedReq miss cycles 1279system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 13337500 # number of InvalidateReq miss cycles 1280system.cpu.l2cache.InvalidateReq_miss_latency::total 13337500 # number of InvalidateReq miss cycles 1281system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 456063500 # number of demand (read+write) miss cycles 1282system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 443832500 # number of demand (read+write) miss cycles 1283system.cpu.l2cache.demand_miss_latency::cpu.inst 11136291500 # number of demand (read+write) miss cycles 1284system.cpu.l2cache.demand_miss_latency::cpu.data 90895949500 # number of demand (read+write) miss cycles 1285system.cpu.l2cache.demand_miss_latency::total 102932137000 # number of demand (read+write) miss cycles 1286system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 456063500 # number of overall miss cycles 1287system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 443832500 # number of overall miss cycles 1288system.cpu.l2cache.overall_miss_latency::cpu.inst 11136291500 # number of overall miss cycles 1289system.cpu.l2cache.overall_miss_latency::cpu.data 90895949500 # number of overall miss cycles 1290system.cpu.l2cache.overall_miss_latency::total 102932137000 # number of overall miss cycles 1291system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 784393 # number of ReadReq accesses(hits+misses) 1292system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 301032 # number of ReadReq accesses(hits+misses) 1293system.cpu.l2cache.ReadReq_accesses::total 1085425 # number of ReadReq accesses(hits+misses) 1294system.cpu.l2cache.WritebackDirty_accesses::writebacks 7504258 # number of WritebackDirty accesses(hits+misses) 1295system.cpu.l2cache.WritebackDirty_accesses::total 7504258 # number of WritebackDirty accesses(hits+misses) 1296system.cpu.l2cache.WritebackClean_accesses::writebacks 15016613 # number of WritebackClean accesses(hits+misses) 1297system.cpu.l2cache.WritebackClean_accesses::total 15016613 # number of WritebackClean accesses(hits+misses) 1298system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43494 # number of UpgradeReq accesses(hits+misses) 1299system.cpu.l2cache.UpgradeReq_accesses::total 43494 # number of UpgradeReq accesses(hits+misses) 1300system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses) 1301system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) 1302system.cpu.l2cache.ReadExReq_accesses::cpu.data 1964146 # number of ReadExReq accesses(hits+misses) 1303system.cpu.l2cache.ReadExReq_accesses::total 1964146 # number of ReadExReq accesses(hits+misses) 1304system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15019798 # number of ReadCleanReq accesses(hits+misses) 1305system.cpu.l2cache.ReadCleanReq_accesses::total 15019798 # number of ReadCleanReq accesses(hits+misses) 1306system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6492382 # number of ReadSharedReq accesses(hits+misses) 1307system.cpu.l2cache.ReadSharedReq_accesses::total 6492382 # number of ReadSharedReq accesses(hits+misses) 1308system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226745 # number of InvalidateReq accesses(hits+misses) 1309system.cpu.l2cache.InvalidateReq_accesses::total 1226745 # number of InvalidateReq accesses(hits+misses) 1310system.cpu.l2cache.demand_accesses::cpu.dtb.walker 784393 # number of demand (read+write) accesses 1311system.cpu.l2cache.demand_accesses::cpu.itb.walker 301032 # number of demand (read+write) accesses 1312system.cpu.l2cache.demand_accesses::cpu.inst 15019798 # number of demand (read+write) accesses 1313system.cpu.l2cache.demand_accesses::cpu.data 8456528 # number of demand (read+write) accesses 1314system.cpu.l2cache.demand_accesses::total 24561751 # number of demand (read+write) accesses 1315system.cpu.l2cache.overall_accesses::cpu.dtb.walker 784393 # number of overall (read+write) accesses 1316system.cpu.l2cache.overall_accesses::cpu.itb.walker 301032 # number of overall (read+write) accesses 1317system.cpu.l2cache.overall_accesses::cpu.inst 15019798 # number of overall (read+write) accesses 1318system.cpu.l2cache.overall_accesses::cpu.data 8456528 # number of overall (read+write) accesses 1319system.cpu.l2cache.overall_accesses::total 24561751 # number of overall (read+write) accesses 1320system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004224 # miss rate for ReadReq accesses 1321system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010790 # miss rate for ReadReq accesses 1322system.cpu.l2cache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses 1323system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783097 # miss rate for UpgradeReq accesses 1324system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783097 # miss rate for UpgradeReq accesses 1325system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 1326system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses 1327system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.201314 # miss rate for ReadExReq accesses 1328system.cpu.l2cache.ReadExReq_miss_rate::total 0.201314 # miss rate for ReadExReq accesses 1329system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005512 # miss rate for ReadCleanReq accesses 1330system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005512 # miss rate for ReadCleanReq accesses 1331system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039440 # miss rate for ReadSharedReq accesses 1332system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039440 # miss rate for ReadSharedReq accesses 1333system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.405812 # miss rate for InvalidateReq accesses 1334system.cpu.l2cache.InvalidateReq_miss_rate::total 0.405812 # miss rate for InvalidateReq accesses 1335system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004224 # miss rate for demand accesses 1336system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010790 # miss rate for demand accesses 1337system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005512 # miss rate for demand accesses 1338system.cpu.l2cache.demand_miss_rate::cpu.data 0.077037 # miss rate for demand accesses 1339system.cpu.l2cache.demand_miss_rate::total 0.030161 # miss rate for demand accesses 1340system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004224 # miss rate for overall accesses 1341system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010790 # miss rate for overall accesses 1342system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005512 # miss rate for overall accesses 1343system.cpu.l2cache.overall_miss_rate::cpu.data 0.077037 # miss rate for overall accesses 1344system.cpu.l2cache.overall_miss_rate::total 0.030161 # miss rate for overall accesses 1345system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137658.768488 # average ReadReq miss latency 1346system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136647.937192 # average ReadReq miss latency 1347system.cpu.l2cache.ReadReq_avg_miss_latency::total 137158.360006 # average ReadReq miss latency 1348system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40021.256606 # average UpgradeReq miss latency 1349system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40021.256606 # average UpgradeReq miss latency 1350system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency 1351system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency 1352system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139468.002913 # average ReadExReq miss latency 1353system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139468.002913 # average ReadExReq miss latency 1354system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134520.643836 # average ReadCleanReq miss latency 1355system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134520.643836 # average ReadCleanReq miss latency 1356system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139612.535490 # average ReadSharedReq miss latency 1357system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139612.535490 # average ReadSharedReq miss latency 1358system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 26.791382 # average InvalidateReq miss latency 1359system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 26.791382 # average InvalidateReq miss latency 1360system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137658.768488 # average overall miss latency 1361system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136647.937192 # average overall miss latency 1362system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134520.643836 # average overall miss latency 1363system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139524.810889 # average overall miss latency 1364system.cpu.l2cache.demand_avg_miss_latency::total 138944.643325 # average overall miss latency 1365system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137658.768488 # average overall miss latency 1366system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136647.937192 # average overall miss latency 1367system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134520.643836 # average overall miss latency 1368system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139524.810889 # average overall miss latency 1369system.cpu.l2cache.overall_avg_miss_latency::total 138944.643325 # average overall miss latency 1370system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1371system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1372system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1373system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1374system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1375system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1376system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1377system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1378system.cpu.l2cache.writebacks::writebacks 960844 # number of writebacks 1379system.cpu.l2cache.writebacks::total 960844 # number of writebacks 1380system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits 1381system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1382system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1383system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1384system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits 1385system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1386system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 1387system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits 1388system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1389system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits 1390system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3312 # number of ReadReq MSHR misses 1391system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3248 # number of ReadReq MSHR misses 1392system.cpu.l2cache.ReadReq_mshr_misses::total 6560 # number of ReadReq MSHR misses 1393system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 1394system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 1395system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34060 # number of UpgradeReq MSHR misses 1396system.cpu.l2cache.UpgradeReq_mshr_misses::total 34060 # number of UpgradeReq MSHR misses 1397system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1398system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1399system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 395411 # number of ReadExReq MSHR misses 1400system.cpu.l2cache.ReadExReq_mshr_misses::total 395411 # number of ReadExReq MSHR misses 1401system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 82785 # number of ReadCleanReq MSHR misses 1402system.cpu.l2cache.ReadCleanReq_mshr_misses::total 82785 # number of ReadCleanReq MSHR misses 1403system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256036 # number of ReadSharedReq MSHR misses 1404system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256036 # number of ReadSharedReq MSHR misses 1405system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 497828 # number of InvalidateReq MSHR misses 1406system.cpu.l2cache.InvalidateReq_mshr_misses::total 497828 # number of InvalidateReq MSHR misses 1407system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3312 # number of demand (read+write) MSHR misses 1408system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3248 # number of demand (read+write) MSHR misses 1409system.cpu.l2cache.demand_mshr_misses::cpu.inst 82785 # number of demand (read+write) MSHR misses 1410system.cpu.l2cache.demand_mshr_misses::cpu.data 651447 # number of demand (read+write) MSHR misses 1411system.cpu.l2cache.demand_mshr_misses::total 740792 # number of demand (read+write) MSHR misses 1412system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3312 # number of overall MSHR misses 1413system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3248 # number of overall MSHR misses 1414system.cpu.l2cache.overall_mshr_misses::cpu.inst 82785 # number of overall MSHR misses 1415system.cpu.l2cache.overall_mshr_misses::cpu.data 651447 # number of overall MSHR misses 1416system.cpu.l2cache.overall_mshr_misses::total 740792 # number of overall MSHR misses 1417system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 1418system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 1419system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54972 # number of ReadReq MSHR uncacheable 1420system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 1421system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 1422system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 1423system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 1424system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88668 # number of overall MSHR uncacheable misses 1425system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 422876510 # number of ReadReq MSHR miss cycles 1426system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 411352500 # number of ReadReq MSHR miss cycles 1427system.cpu.l2cache.ReadReq_mshr_miss_latency::total 834229010 # number of ReadReq MSHR miss cycles 1428system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2316435500 # number of UpgradeReq MSHR miss cycles 1429system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2316435500 # number of UpgradeReq MSHR miss cycles 1430system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 209000 # number of SCUpgradeReq MSHR miss cycles 1431system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 209000 # number of SCUpgradeReq MSHR miss cycles 1432system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 51192062926 # number of ReadExReq MSHR miss cycles 1433system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 51192062926 # number of ReadExReq MSHR miss cycles 1434system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10308356184 # number of ReadCleanReq MSHR miss cycles 1435system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10308356184 # number of ReadCleanReq MSHR miss cycles 1436system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33185372324 # number of ReadSharedReq MSHR miss cycles 1437system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33185372324 # number of ReadSharedReq MSHR miss cycles 1438system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 34796895500 # number of InvalidateReq MSHR miss cycles 1439system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 34796895500 # number of InvalidateReq MSHR miss cycles 1440system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 422876510 # number of demand (read+write) MSHR miss cycles 1441system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 411352500 # number of demand (read+write) MSHR miss cycles 1442system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10308356184 # number of demand (read+write) MSHR miss cycles 1443system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84377435250 # number of demand (read+write) MSHR miss cycles 1444system.cpu.l2cache.demand_mshr_miss_latency::total 95520020444 # number of demand (read+write) MSHR miss cycles 1445system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 422876510 # number of overall MSHR miss cycles 1446system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 411352500 # number of overall MSHR miss cycles 1447system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10308356184 # number of overall MSHR miss cycles 1448system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84377435250 # number of overall MSHR miss cycles 1449system.cpu.l2cache.overall_mshr_miss_latency::total 95520020444 # number of overall MSHR miss cycles 1450system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763000 # number of ReadReq MSHR uncacheable cycles 1451system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770678500 # number of ReadReq MSHR uncacheable cycles 1452system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189441500 # number of ReadReq MSHR uncacheable cycles 1453system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836379500 # number of WriteReq MSHR uncacheable cycles 1454system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836379500 # number of WriteReq MSHR uncacheable cycles 1455system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763000 # number of overall MSHR uncacheable cycles 1456system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607058000 # number of overall MSHR uncacheable cycles 1457system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025821000 # number of overall MSHR uncacheable cycles 1458system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for ReadReq accesses 1459system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for ReadReq accesses 1460system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006044 # mshr miss rate for ReadReq accesses 1461system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1462system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1463system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783097 # mshr miss rate for UpgradeReq accesses 1464system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783097 # mshr miss rate for UpgradeReq accesses 1465system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1466system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1467system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201314 # mshr miss rate for ReadExReq accesses 1468system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201314 # mshr miss rate for ReadExReq accesses 1469system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for ReadCleanReq accesses 1470system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005512 # mshr miss rate for ReadCleanReq accesses 1471system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039436 # mshr miss rate for ReadSharedReq accesses 1472system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039436 # mshr miss rate for ReadSharedReq accesses 1473system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405812 # mshr miss rate for InvalidateReq accesses 1474system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405812 # mshr miss rate for InvalidateReq accesses 1475system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for demand accesses 1476system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for demand accesses 1477system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for demand accesses 1478system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for demand accesses 1479system.cpu.l2cache.demand_mshr_miss_rate::total 0.030160 # mshr miss rate for demand accesses 1480system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for overall accesses 1481system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for overall accesses 1482system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for overall accesses 1483system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for overall accesses 1484system.cpu.l2cache.overall_mshr_miss_rate::total 0.030160 # mshr miss rate for overall accesses 1485system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average ReadReq mshr miss latency 1486system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average ReadReq mshr miss latency 1487system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127169.056402 # average ReadReq mshr miss latency 1488system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68010.437463 # average UpgradeReq mshr miss latency 1489system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68010.437463 # average UpgradeReq mshr miss latency 1490system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency 1491system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency 1492system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129465.449687 # average ReadExReq mshr miss latency 1493system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129465.449687 # average ReadExReq mshr miss latency 1494system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124519.613263 # average ReadCleanReq mshr miss latency 1495system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124519.613263 # average ReadCleanReq mshr miss latency 1496system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129612.133934 # average ReadSharedReq mshr miss latency 1497system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129612.133934 # average ReadSharedReq mshr miss latency 1498system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69897.425416 # average InvalidateReq mshr miss latency 1499system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69897.425416 # average InvalidateReq mshr miss latency 1500system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency 1501system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency 1502system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency 1503system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency 1504system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency 1505system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency 1506system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency 1507system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency 1508system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency 1509system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency 1510system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency 1511system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369 # average ReadReq mshr uncacheable latency 1512system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069 # average ReadReq mshr uncacheable latency 1513system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993 # average WriteReq mshr uncacheable latency 1514system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993 # average WriteReq mshr uncacheable latency 1515system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency 1516system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416 # average overall mshr uncacheable latency 1517system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427 # average overall mshr uncacheable latency 1518system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1519system.cpu.toL2Bus.snoop_filter.tot_requests 50149666 # Total number of requests made to the snoop filter. 1520system.cpu.toL2Bus.snoop_filter.hit_single_requests 25446406 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1521system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1522system.cpu.toL2Bus.snoop_filter.tot_snoops 2163 # Total number of snoops made to the snoop filter. 1523system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1524system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1525system.cpu.toL2Bus.trans_dist::ReadReq 1624231 # Transaction distribution 1526system.cpu.toL2Bus.trans_dist::ReadResp 23137410 # Transaction distribution 1527system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution 1528system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution 1529system.cpu.toL2Bus.trans_dist::WritebackDirty 8571764 # Transaction distribution 1530system.cpu.toL2Bus.trans_dist::WritebackClean 15019267 # Transaction distribution 1531system.cpu.toL2Bus.trans_dist::CleanEvict 2370936 # Transaction distribution 1532system.cpu.toL2Bus.trans_dist::UpgradeReq 43497 # Transaction distribution 1533system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution 1534system.cpu.toL2Bus.trans_dist::UpgradeResp 43503 # Transaction distribution 1535system.cpu.toL2Bus.trans_dist::ReadExReq 1964146 # Transaction distribution 1536system.cpu.toL2Bus.trans_dist::ReadExResp 1964146 # Transaction distribution 1537system.cpu.toL2Bus.trans_dist::ReadCleanReq 15020006 # Transaction distribution 1538system.cpu.toL2Bus.trans_dist::ReadSharedReq 6501231 # Transaction distribution 1539system.cpu.toL2Bus.trans_dist::InvalidateReq 1333409 # Transaction distribution 1540system.cpu.toL2Bus.trans_dist::InvalidateResp 1226745 # Transaction distribution 1541system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45101659 # Packet count per connected master and slave (bytes) 1542system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29271837 # Packet count per connected master and slave (bytes) 1543system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729068 # Packet count per connected master and slave (bytes) 1544system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1925616 # Packet count per connected master and slave (bytes) 1545system.cpu.toL2Bus.pkt_count::total 77028180 # Packet count per connected master and slave (bytes) 1546system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922840864 # Cumulative packet size per connected master and slave (bytes) 1547system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1021731230 # Cumulative packet size per connected master and slave (bytes) 1548system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2408256 # Cumulative packet size per connected master and slave (bytes) 1549system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6275144 # Cumulative packet size per connected master and slave (bytes) 1550system.cpu.toL2Bus.pkt_size::total 2953255494 # Cumulative packet size per connected master and slave (bytes) 1551system.cpu.toL2Bus.snoops 1860303 # Total snoops (count) 1552system.cpu.toL2Bus.snoop_fanout::samples 27780180 # Request fanout histogram 1553system.cpu.toL2Bus.snoop_fanout::mean 0.025443 # Request fanout histogram 1554system.cpu.toL2Bus.snoop_fanout::stdev 0.157467 # Request fanout histogram 1555system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1556system.cpu.toL2Bus.snoop_fanout::0 27073367 97.46% 97.46% # Request fanout histogram 1557system.cpu.toL2Bus.snoop_fanout::1 706813 2.54% 100.00% # Request fanout histogram 1558system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1559system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1560system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1561system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1562system.cpu.toL2Bus.snoop_fanout::total 27780180 # Request fanout histogram 1563system.cpu.toL2Bus.reqLayer0.occupancy 48093772959 # Layer occupancy (ticks) 1564system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1565system.cpu.toL2Bus.snoopLayer0.occupancy 1496382 # Layer occupancy (ticks) 1566system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1567system.cpu.toL2Bus.respLayer0.occupancy 22560257433 # Layer occupancy (ticks) 1568system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1569system.cpu.toL2Bus.respLayer1.occupancy 13373462829 # Layer occupancy (ticks) 1570system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1571system.cpu.toL2Bus.respLayer2.occupancy 428394234 # Layer occupancy (ticks) 1572system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1573system.cpu.toL2Bus.respLayer3.occupancy 1141603196 # Layer occupancy (ticks) 1574system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1575system.iobus.trans_dist::ReadReq 40297 # Transaction distribution 1576system.iobus.trans_dist::ReadResp 40297 # Transaction distribution 1577system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1578system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1579system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1580system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1581system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1582system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1583system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1584system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1585system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1586system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1587system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1588system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1589system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1590system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1591system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1592system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1593system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) 1594system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) 1595system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1596system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1597system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) 1598system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1599system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1600system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1601system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1602system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1603system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1604system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1605system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1606system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1607system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1608system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1609system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1610system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1611system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1612system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) 1613system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) 1614system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1615system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1616system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) 1617system.iobus.reqLayer0.occupancy 41874500 # Layer occupancy (ticks) 1618system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1619system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 1620system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1621system.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks) 1622system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1623system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 1624system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1625system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 1626system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1627system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 1628system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1629system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1630system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1631system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1632system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1633system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1634system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1635system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 1636system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1637system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1638system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1639system.iobus.reqLayer23.occupancy 25162500 # Layer occupancy (ticks) 1640system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1641system.iobus.reqLayer24.occupancy 36499500 # Layer occupancy (ticks) 1642system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1643system.iobus.reqLayer25.occupancy 567349755 # Layer occupancy (ticks) 1644system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1645system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1646system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1647system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) 1648system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1649system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1650system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1651system.iocache.tags.replacements 115457 # number of replacements 1652system.iocache.tags.tagsinuse 10.423127 # Cycle average of tags in use 1653system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1654system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. 1655system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1656system.iocache.tags.warmup_cycle 13098803375000 # Cycle when the warmup percentage was hit. 1657system.iocache.tags.occ_blocks::realview.ethernet 3.544202 # Average occupied blocks per requestor 1658system.iocache.tags.occ_blocks::realview.ide 6.878925 # Average occupied blocks per requestor 1659system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy 1660system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy 1661system.iocache.tags.occ_percent::total 0.651445 # Average percentage of cache occupancy 1662system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1663system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1664system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1665system.iocache.tags.tag_accesses 1039641 # Number of tag accesses 1666system.iocache.tags.data_accesses 1039641 # Number of data accesses 1667system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1668system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses 1669system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses 1670system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1671system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1672system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1673system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1674system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1675system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses 1676system.iocache.demand_misses::total 8852 # number of demand (read+write) misses 1677system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1678system.iocache.overall_misses::realview.ide 8812 # number of overall misses 1679system.iocache.overall_misses::total 8852 # number of overall misses 1680system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles 1681system.iocache.ReadReq_miss_latency::realview.ide 1683110232 # number of ReadReq miss cycles 1682system.iocache.ReadReq_miss_latency::total 1688179732 # number of ReadReq miss cycles 1683system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1684system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1685system.iocache.WriteLineReq_miss_latency::realview.ide 13415109023 # number of WriteLineReq miss cycles 1686system.iocache.WriteLineReq_miss_latency::total 13415109023 # number of WriteLineReq miss cycles 1687system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles 1688system.iocache.demand_miss_latency::realview.ide 1683110232 # number of demand (read+write) miss cycles 1689system.iocache.demand_miss_latency::total 1688530732 # number of demand (read+write) miss cycles 1690system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles 1691system.iocache.overall_miss_latency::realview.ide 1683110232 # number of overall miss cycles 1692system.iocache.overall_miss_latency::total 1688530732 # number of overall miss cycles 1693system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1694system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) 1695system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) 1696system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1697system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1698system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1699system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1700system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1701system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses 1702system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses 1703system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1704system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses 1705system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses 1706system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1707system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1708system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1709system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1710system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1711system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1712system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1713system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1714system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1715system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1716system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1717system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1718system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1719system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency 1720system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997 # average ReadReq miss latency 1721system.iocache.ReadReq_avg_miss_latency::total 190776.328625 # average ReadReq miss latency 1722system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1723system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1724system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335 # average WriteLineReq miss latency 1725system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335 # average WriteLineReq miss latency 1726system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency 1727system.iocache.demand_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency 1728system.iocache.demand_avg_miss_latency::total 190751.325350 # average overall miss latency 1729system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency 1730system.iocache.overall_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency 1731system.iocache.overall_avg_miss_latency::total 190751.325350 # average overall miss latency 1732system.iocache.blocked_cycles::no_mshrs 34444 # number of cycles access was blocked 1733system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1734system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked 1735system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1736system.iocache.avg_blocked_cycles::no_mshrs 9.824301 # average number of cycles each access was blocked 1737system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1738system.iocache.fast_writes 0 # number of fast writes performed 1739system.iocache.cache_copies 0 # number of cache copies performed 1740system.iocache.writebacks::writebacks 106630 # number of writebacks 1741system.iocache.writebacks::total 106630 # number of writebacks 1742system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1743system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses 1744system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses 1745system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1746system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1747system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1748system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1749system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1750system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses 1751system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses 1752system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1753system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses 1754system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses 1755system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles 1756system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242510232 # number of ReadReq MSHR miss cycles 1757system.iocache.ReadReq_mshr_miss_latency::total 1245729732 # number of ReadReq MSHR miss cycles 1758system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1759system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1760system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076836456 # number of WriteLineReq MSHR miss cycles 1761system.iocache.WriteLineReq_mshr_miss_latency::total 8076836456 # number of WriteLineReq MSHR miss cycles 1762system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles 1763system.iocache.demand_mshr_miss_latency::realview.ide 1242510232 # number of demand (read+write) MSHR miss cycles 1764system.iocache.demand_mshr_miss_latency::total 1245930732 # number of demand (read+write) MSHR miss cycles 1765system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles 1766system.iocache.overall_mshr_miss_latency::realview.ide 1242510232 # number of overall MSHR miss cycles 1767system.iocache.overall_mshr_miss_latency::total 1245930732 # number of overall MSHR miss cycles 1768system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1769system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1770system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1771system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1772system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1773system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1774system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1775system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1776system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1777system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1778system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1779system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1780system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1781system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency 1782system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997 # average ReadReq mshr miss latency 1783system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625 # average ReadReq mshr miss latency 1784system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1785system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1786system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831 # average WriteLineReq mshr miss latency 1787system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831 # average WriteLineReq mshr miss latency 1788system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency 1789system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency 1790system.iocache.demand_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency 1791system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency 1792system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency 1793system.iocache.overall_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency 1794system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1795system.membus.trans_dist::ReadReq 54972 # Transaction distribution 1796system.membus.trans_dist::ReadResp 409202 # Transaction distribution 1797system.membus.trans_dist::WriteReq 33696 # Transaction distribution 1798system.membus.trans_dist::WriteResp 33696 # Transaction distribution 1799system.membus.trans_dist::WritebackDirty 1067474 # Transaction distribution 1800system.membus.trans_dist::CleanEvict 191385 # Transaction distribution 1801system.membus.trans_dist::UpgradeReq 34855 # Transaction distribution 1802system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1803system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 1804system.membus.trans_dist::ReadExReq 394790 # Transaction distribution 1805system.membus.trans_dist::ReadExResp 394790 # Transaction distribution 1806system.membus.trans_dist::ReadSharedReq 354230 # Transaction distribution 1807system.membus.trans_dist::InvalidateReq 604321 # Transaction distribution 1808system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1809system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1810system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) 1811system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3203313 # Packet count per connected master and slave (bytes) 1812system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3332933 # Packet count per connected master and slave (bytes) 1813system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237959 # Packet count per connected master and slave (bytes) 1814system.membus.pkt_count_system.iocache.mem_side::total 237959 # Packet count per connected master and slave (bytes) 1815system.membus.pkt_count::total 3570892 # Packet count per connected master and slave (bytes) 1816system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1817system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) 1818system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) 1819system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109183820 # Cumulative packet size per connected master and slave (bytes) 1820system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109353790 # Cumulative packet size per connected master and slave (bytes) 1821system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271424 # Cumulative packet size per connected master and slave (bytes) 1822system.membus.pkt_size_system.iocache.mem_side::total 7271424 # Cumulative packet size per connected master and slave (bytes) 1823system.membus.pkt_size::total 116625214 # Cumulative packet size per connected master and slave (bytes) 1824system.membus.snoops 2530 # Total snoops (count) 1825system.membus.snoop_fanout::samples 2735759 # Request fanout histogram 1826system.membus.snoop_fanout::mean 1 # Request fanout histogram 1827system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1828system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1829system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1830system.membus.snoop_fanout::1 2735759 100.00% 100.00% # Request fanout histogram 1831system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1832system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1833system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1834system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1835system.membus.snoop_fanout::total 2735759 # Request fanout histogram 1836system.membus.reqLayer0.occupancy 103971500 # Layer occupancy (ticks) 1837system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1838system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) 1839system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1840system.membus.reqLayer2.occupancy 5468000 # Layer occupancy (ticks) 1841system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1842system.membus.reqLayer5.occupancy 7155774176 # Layer occupancy (ticks) 1843system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1844system.membus.respLayer2.occupancy 4068025704 # Layer occupancy (ticks) 1845system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1846system.membus.respLayer3.occupancy 44802062 # Layer occupancy (ticks) 1847system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1848system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1849system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1850system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1851system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1852system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1853system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1854system.realview.ethernet.txBytes 966 # Bytes Transmitted 1855system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1856system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1857system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1858system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1859system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1860system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1861system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1862system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1863system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 1864system.realview.ethernet.totPackets 3 # Total Packets 1865system.realview.ethernet.totBytes 966 # Total Bytes 1866system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1867system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 1868system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1869system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1870system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1871system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1872system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1873system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1874system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1875system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1876system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1877system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1878system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1879system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1880system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1881system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1882system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1883system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1884system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1885system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1886system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1887system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1888system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1889system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1890system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1891system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1892system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1893system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1894system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1895system.realview.ethernet.droppedPackets 0 # number of packets dropped 1896system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1897system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1898system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1899system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1900system.cpu.kern.inst.arm 0 # number of arm instructions executed 1901system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed 1902 1903---------- End Simulation Statistics ---------- 1904