stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.320647 # Number of seconds simulated 4sim_ticks 51320647066500 # Number of ticks simulated 5final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 114690 # Simulator instruction rate (inst/s) 8host_op_rate 134762 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6864170011 # Simulator tick rate (ticks/s) 10host_mem_usage 721888 # Number of bytes of host memory used 11host_seconds 7476.60 # Real time elapsed on the host 12sim_insts 857487967 # Number of instructions simulated 13sim_ops 1007562352 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory 21system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 791544 # Number of read requests accepted 55system.physmem.writeReqs 1694292 # Number of write requests accepted 56system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue 60system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 48315 # Per bank write bursts 67system.physmem.perBankRdBursts::1 50150 # Per bank write bursts 68system.physmem.perBankRdBursts::2 46175 # Per bank write bursts 69system.physmem.perBankRdBursts::3 46946 # Per bank write bursts 70system.physmem.perBankRdBursts::4 45323 # Per bank write bursts 71system.physmem.perBankRdBursts::5 52981 # Per bank write bursts 72system.physmem.perBankRdBursts::6 47646 # Per bank write bursts 73system.physmem.perBankRdBursts::7 48748 # Per bank write bursts 74system.physmem.perBankRdBursts::8 44337 # Per bank write bursts 75system.physmem.perBankRdBursts::9 72322 # Per bank write bursts 76system.physmem.perBankRdBursts::10 50834 # Per bank write bursts 77system.physmem.perBankRdBursts::11 50772 # Per bank write bursts 78system.physmem.perBankRdBursts::12 48451 # Per bank write bursts 79system.physmem.perBankRdBursts::13 47387 # Per bank write bursts 80system.physmem.perBankRdBursts::14 44232 # Per bank write bursts 81system.physmem.perBankRdBursts::15 46363 # Per bank write bursts 82system.physmem.perBankWrBursts::0 103979 # Per bank write bursts 83system.physmem.perBankWrBursts::1 105038 # Per bank write bursts 84system.physmem.perBankWrBursts::2 105754 # Per bank write bursts 85system.physmem.perBankWrBursts::3 105161 # Per bank write bursts 86system.physmem.perBankWrBursts::4 103562 # Per bank write bursts 87system.physmem.perBankWrBursts::5 108435 # Per bank write bursts 88system.physmem.perBankWrBursts::6 103867 # Per bank write bursts 89system.physmem.perBankWrBursts::7 105467 # Per bank write bursts 90system.physmem.perBankWrBursts::8 102645 # Per bank write bursts 91system.physmem.perBankWrBursts::9 108407 # Per bank write bursts 92system.physmem.perBankWrBursts::10 108582 # Per bank write bursts 93system.physmem.perBankWrBursts::11 107982 # Per bank write bursts 94system.physmem.perBankWrBursts::12 105330 # Per bank write bursts 95system.physmem.perBankWrBursts::13 105345 # Per bank write bursts 96system.physmem.perBankWrBursts::14 103911 # Per bank write bursts 97system.physmem.perBankWrBursts::15 104029 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 30 # Number of times write queue was full causing retry 100system.physmem.totGap 51320645833500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 21272 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 770259 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1691719 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 3795 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 3522 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 3348 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 3077 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 3049 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 2918 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 2900 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 2759 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 2637 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 2554 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 2529 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 2364 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads 270system.physmem.totQLat 15484448260 # Total ticks spent queuing 271system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 275system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.02 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 284system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 285system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing 286system.physmem.readRowHits 603455 # Number of row buffer hits during reads 287system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes 290system.physmem.avgGap 20645225.93 # Average gap between requests 291system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) 300system.physmem_0.averagePower 668.473889 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states 302system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 304system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 306system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) 314system.physmem_1.averagePower 668.480369 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states 316system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 318system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 320system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory 321system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory 323system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory 324system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory 325system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory 326system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 327system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory 328system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 334system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 335system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 336system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 337system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 338system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 339system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 340system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 341system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 342system.cpu.branchPred.lookups 226505876 # Number of BP lookups 343system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted 344system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect 345system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups 346system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits 347system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 348system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage 349system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. 350system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. 351system.cpu_clk_domain.clock 500 # Clock period in ticks 352system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 361system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 362system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 363system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 364system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 365system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 366system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 370system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 371system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 372system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 376system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 377system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 378system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 379system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 380system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 381system.cpu.dtb.walker.walks 931379 # Table walker walks requested 382system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors 383system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate 384system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate 385system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting 386system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution 427system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution 428system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution 429system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution 431system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated 432system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated 433system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated 434system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst 435system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 436system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst 437system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst 438system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst 441system.cpu.dtb.inst_hits 0 # ITB inst hits 442system.cpu.dtb.inst_misses 0 # ITB inst misses 443system.cpu.dtb.read_hits 171278986 # DTB read hits 444system.cpu.dtb.read_misses 671795 # DTB read misses 445system.cpu.dtb.write_hits 149102166 # DTB write hits 446system.cpu.dtb.write_misses 259584 # DTB write misses 447system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 448system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 449system.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID 450system.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID 451system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB 452system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions 453system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch 454system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 455system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions 456system.cpu.dtb.read_accesses 171950781 # DTB read accesses 457system.cpu.dtb.write_accesses 149361750 # DTB write accesses 458system.cpu.dtb.inst_accesses 0 # ITB inst accesses 459system.cpu.dtb.hits 320381152 # DTB hits 460system.cpu.dtb.misses 931379 # DTB misses 461system.cpu.dtb.accesses 321312531 # DTB accesses 462system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 463system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 471system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 472system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 473system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 474system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 475system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 476system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 477system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 479system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 480system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 481system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 482system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 483system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 485system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 486system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 487system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 488system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 489system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 490system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 491system.cpu.itb.walker.walks 161841 # Table walker walks requested 492system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors 493system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate 494system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate 495system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting 496system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency 497system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency 498system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 511system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency 512system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency 522system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency 523system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency 524system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency 525system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 526system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 527system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 528system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 529system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 530system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency 531system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution 532system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution 533system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution 534system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution 535system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution 536system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution 537system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution 538system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution 539system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated 540system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated 541system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated 542system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 543system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst 544system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst 545system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 546system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst 547system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst 548system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst 549system.cpu.itb.inst_hits 360168043 # ITB inst hits 550system.cpu.itb.inst_misses 161841 # ITB inst misses 551system.cpu.itb.read_hits 0 # DTB read hits 552system.cpu.itb.read_misses 0 # DTB read misses 553system.cpu.itb.write_hits 0 # DTB write hits 554system.cpu.itb.write_misses 0 # DTB write misses 555system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 556system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 557system.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID 558system.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID 559system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB 560system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 561system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 562system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 563system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions 564system.cpu.itb.read_accesses 0 # DTB read accesses 565system.cpu.itb.write_accesses 0 # DTB write accesses 566system.cpu.itb.inst_accesses 360329884 # ITB inst accesses 567system.cpu.itb.hits 360168043 # DTB hits 568system.cpu.itb.misses 161841 # DTB misses 569system.cpu.itb.accesses 360329884 # DTB accesses 570system.cpu.numCycles 1576983833 # number of cpu cycles simulated 571system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 572system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 573system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss 574system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed 575system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered 576system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken 577system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked 578system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing 579system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb 580system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 581system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps 582system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions 583system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR 584system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched 585system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed 586system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed 587system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) 588system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) 590system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 591system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) 593system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) 594system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) 595system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle 600system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle 601system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle 602system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked 603system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running 604system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking 605system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing 606system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch 607system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction 608system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode 609system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode 610system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing 611system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle 612system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking 613system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst 614system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running 615system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking 616system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename 617system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename 618system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full 619system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full 620system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full 621system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full 622system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers 623system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed 624system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made 625system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups 626system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups 627system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed 628system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing 629system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed 630system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed 631system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer 632system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. 633system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. 634system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. 635system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. 636system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) 637system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ 638system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued 639system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued 640system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling 641system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph 642system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed 643system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle 646system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle 653system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle 660system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 661system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available 662system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available 663system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available 664system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available 665system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available 666system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available 667system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available 668system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available 669system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available 690system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available 691system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available 692system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 693system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 694system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued 695system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued 696system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued 697system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued 698system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued 699system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued 700system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued 701system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued 702system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued 703system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued 715system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued 716system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued 724system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued 725system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued 726system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 727system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 728system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued 729system.cpu.iq.rate 0.670005 # Inst issue rate 730system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested 731system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) 732system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads 733system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes 734system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses 735system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads 736system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes 737system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses 738system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses 739system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses 740system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores 741system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 742system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed 743system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed 744system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations 745system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed 746system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 747system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 748system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled 749system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked 750system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 751system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing 752system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking 753system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking 754system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ 755system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 756system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions 757system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions 758system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions 759system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall 760system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall 761system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations 762system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly 763system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly 764system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute 765system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions 766system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed 767system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute 768system.cpu.iew.exec_swp 0 # number of swp insts executed 769system.cpu.iew.exec_nop 224348 # number of nop insts executed 770system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed 771system.cpu.iew.exec_branches 198404489 # Number of branches executed 772system.cpu.iew.exec_stores 149099070 # Number of stores executed 773system.cpu.iew.exec_rate 0.662897 # Inst execution rate 774system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit 775system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back 776system.cpu.iew.wb_producers 442335874 # num instructions producing a value 777system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value 778system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 779system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle 780system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back 781system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 782system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit 783system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards 784system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted 785system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle 793system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle 802system.cpu.commit.committedInsts 857487967 # Number of instructions committed 803system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed 804system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 805system.cpu.commit.refs 307720812 # Number of memory references committed 806system.cpu.commit.loads 161382253 # Number of loads committed 807system.cpu.commit.membars 7017472 # Number of memory barriers committed 808system.cpu.commit.branches 191417503 # Number of branches committed 809system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. 810system.cpu.commit.int_insts 925548459 # Number of committed integer instructions. 811system.cpu.commit.function_calls 25509836 # Number of function calls committed. 812system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 813system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction 814system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction 815system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction 816system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction 817system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction 818system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction 819system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction 820system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction 821system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction 822system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction 828system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction 829system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction 832system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction 833system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction 834system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 842system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction 843system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction 844system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 845system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 846system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction 847system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached 848system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 849system.cpu.rob.rob_reads 2555751551 # The number of ROB reads 850system.cpu.rob.rob_writes 2129995502 # The number of ROB writes 851system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself 852system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling 853system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 854system.cpu.committedInsts 857487967 # Number of Instructions Simulated 855system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated 856system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction 857system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads 858system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle 859system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads 860system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads 861system.cpu.int_regfile_writes 738733043 # number of integer regfile writes 862system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads 863system.cpu.fp_regfile_writes 782548 # number of floating regfile writes 864system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads 865system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes 866system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads 867system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes 868system.cpu.dcache.tags.replacements 9822587 # number of replacements 869system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use 870system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. 871system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. 872system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. 873system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. 874system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor 875system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy 876system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy 877system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 878system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 879system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id 880system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id 881system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 882system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses 883system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses 884system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits 885system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits 886system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits 887system.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits 888system.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits 889system.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits 890system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits 891system.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits 892system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits 893system.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits 894system.cpu.dcache.StoreCondReq_hits::cpu.data 3751270 # number of StoreCondReq hits 895system.cpu.dcache.StoreCondReq_hits::total 3751270 # number of StoreCondReq hits 896system.cpu.dcache.demand_hits::cpu.data 278328901 # number of demand (read+write) hits 897system.cpu.dcache.demand_hits::total 278328901 # number of demand (read+write) hits 898system.cpu.dcache.overall_hits::cpu.data 278710234 # number of overall hits 899system.cpu.dcache.overall_hits::total 278710234 # number of overall hits 900system.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses 901system.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses 902system.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses 903system.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses 904system.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses 905system.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses 906system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses 907system.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses 908system.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses 909system.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses 910system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 911system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 912system.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses 913system.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses 914system.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses 915system.cpu.dcache.overall_misses::total 22162626 # number of overall misses 916system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles 917system.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles 918system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles 919system.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles 920system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38655244426 # number of WriteInvalidateReq miss cycles 921system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38655244426 # number of WriteInvalidateReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6327424004 # number of LoadLockedReq miss cycles 923system.cpu.dcache.LoadLockedReq_miss_latency::total 6327424004 # number of LoadLockedReq miss cycles 924system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles 925system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles 926system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles 927system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles 928system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles 929system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles 930system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) 932system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) 934system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) 935system.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses) 936system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses) 937system.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses) 938system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses) 939system.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses) 940system.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses) 941system.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses) 942system.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses 943system.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses 944system.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses 945system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses 946system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses 947system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses 948system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses 949system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses 950system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses 951system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses 952system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses 953system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses 954system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses 955system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses 956system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 957system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 958system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses 959system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses 960system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses 961system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses 962system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency 963system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency 964system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency 965system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency 966system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency 967system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency 968system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency 969system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency 970system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency 971system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency 972system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency 973system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency 974system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency 975system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency 976system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked 977system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 978system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked 979system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 980system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked 981system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 982system.cpu.dcache.fast_writes 0 # number of fast writes performed 983system.cpu.dcache.cache_copies 0 # number of cache copies performed 984system.cpu.dcache.writebacks::writebacks 7597183 # number of writebacks 985system.cpu.dcache.writebacks::total 7597183 # number of writebacks 986system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4319062 # number of ReadReq MSHR hits 987system.cpu.dcache.ReadReq_mshr_hits::total 4319062 # number of ReadReq MSHR hits 988system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9426489 # number of WriteReq MSHR hits 989system.cpu.dcache.WriteReq_mshr_hits::total 9426489 # number of WriteReq MSHR hits 990system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7148 # number of WriteInvalidateReq MSHR hits 991system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7148 # number of WriteInvalidateReq MSHR hits 992system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220034 # number of LoadLockedReq MSHR hits 993system.cpu.dcache.LoadLockedReq_mshr_hits::total 220034 # number of LoadLockedReq MSHR hits 994system.cpu.dcache.demand_mshr_hits::cpu.data 13745551 # number of demand (read+write) MSHR hits 995system.cpu.dcache.demand_mshr_hits::total 13745551 # number of demand (read+write) MSHR hits 996system.cpu.dcache.overall_mshr_hits::cpu.data 13745551 # number of overall MSHR hits 997system.cpu.dcache.overall_mshr_hits::total 13745551 # number of overall MSHR hits 998system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5177976 # number of ReadReq MSHR misses 999system.cpu.dcache.ReadReq_mshr_misses::total 5177976 # number of ReadReq MSHR misses 1000system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041958 # number of WriteReq MSHR misses 1001system.cpu.dcache.WriteReq_mshr_misses::total 2041958 # number of WriteReq MSHR misses 1002system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190352 # number of SoftPFReq MSHR misses 1003system.cpu.dcache.SoftPFReq_mshr_misses::total 1190352 # number of SoftPFReq MSHR misses 1004system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226180 # number of WriteInvalidateReq MSHR misses 1005system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226180 # number of WriteInvalidateReq MSHR misses 1006system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230589 # number of LoadLockedReq MSHR misses 1007system.cpu.dcache.LoadLockedReq_mshr_misses::total 230589 # number of LoadLockedReq MSHR misses 1008system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 1009system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 1010system.cpu.dcache.demand_mshr_misses::cpu.data 7219934 # number of demand (read+write) MSHR misses 1011system.cpu.dcache.demand_mshr_misses::total 7219934 # number of demand (read+write) MSHR misses 1012system.cpu.dcache.overall_mshr_misses::cpu.data 8410286 # number of overall MSHR misses 1013system.cpu.dcache.overall_mshr_misses::total 8410286 # number of overall MSHR misses 1014system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70110899674 # number of ReadReq MSHR miss cycles 1015system.cpu.dcache.ReadReq_mshr_miss_latency::total 70110899674 # number of ReadReq MSHR miss cycles 1016system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53589743024 # number of WriteReq MSHR miss cycles 1017system.cpu.dcache.WriteReq_mshr_miss_latency::total 53589743024 # number of WriteReq MSHR miss cycles 1018system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18780468745 # number of SoftPFReq MSHR miss cycles 1019system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18780468745 # number of SoftPFReq MSHR miss cycles 1020system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35955294132 # number of WriteInvalidateReq MSHR miss cycles 1021system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35955294132 # number of WriteInvalidateReq MSHR miss cycles 1022system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles 1023system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles 1024system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles 1025system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles 1026system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles 1027system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles 1028system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles 1029system.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles 1030system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles 1031system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles 1032system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles 1033system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles 1034system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles 1035system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles 1036system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses 1037system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses 1038system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses 1039system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses 1040system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses 1041system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses 1042system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses 1043system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses 1044system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses 1045system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses 1046system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 1047system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 1048system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses 1049system.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses 1050system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses 1051system.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses 1052system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency 1053system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency 1054system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency 1055system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency 1056system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency 1057system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency 1058system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency 1059system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency 1060system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency 1061system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency 1062system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency 1063system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency 1064system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency 1065system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency 1066system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency 1067system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency 1068system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1069system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1070system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1071system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1072system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1073system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1074system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu.icache.tags.replacements 15084162 # number of replacements 1076system.cpu.icache.tags.tagsinuse 511.954207 # Cycle average of tags in use 1077system.cpu.icache.tags.total_refs 343955623 # Total number of references to valid blocks. 1078system.cpu.icache.tags.sampled_refs 15084674 # Sample count of references to valid blocks. 1079system.cpu.icache.tags.avg_refs 22.801661 # Average number of references to valid blocks. 1080system.cpu.icache.tags.warmup_cycle 14174936000 # Cycle when the warmup percentage was hit. 1081system.cpu.icache.tags.occ_blocks::cpu.inst 511.954207 # Average occupied blocks per requestor 1082system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy 1083system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy 1084system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1085system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 1086system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 1087system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 1088system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1089system.cpu.icache.tags.tag_accesses 374842526 # Number of tag accesses 1090system.cpu.icache.tags.data_accesses 374842526 # Number of data accesses 1091system.cpu.icache.ReadReq_hits::cpu.inst 343955623 # number of ReadReq hits 1092system.cpu.icache.ReadReq_hits::total 343955623 # number of ReadReq hits 1093system.cpu.icache.demand_hits::cpu.inst 343955623 # number of demand (read+write) hits 1094system.cpu.icache.demand_hits::total 343955623 # number of demand (read+write) hits 1095system.cpu.icache.overall_hits::cpu.inst 343955623 # number of overall hits 1096system.cpu.icache.overall_hits::total 343955623 # number of overall hits 1097system.cpu.icache.ReadReq_misses::cpu.inst 15802123 # number of ReadReq misses 1098system.cpu.icache.ReadReq_misses::total 15802123 # number of ReadReq misses 1099system.cpu.icache.demand_misses::cpu.inst 15802123 # number of demand (read+write) misses 1100system.cpu.icache.demand_misses::total 15802123 # number of demand (read+write) misses 1101system.cpu.icache.overall_misses::cpu.inst 15802123 # number of overall misses 1102system.cpu.icache.overall_misses::total 15802123 # number of overall misses 1103system.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846 # number of ReadReq miss cycles 1104system.cpu.icache.ReadReq_miss_latency::total 208192919846 # number of ReadReq miss cycles 1105system.cpu.icache.demand_miss_latency::cpu.inst 208192919846 # number of demand (read+write) miss cycles 1106system.cpu.icache.demand_miss_latency::total 208192919846 # number of demand (read+write) miss cycles 1107system.cpu.icache.overall_miss_latency::cpu.inst 208192919846 # number of overall miss cycles 1108system.cpu.icache.overall_miss_latency::total 208192919846 # number of overall miss cycles 1109system.cpu.icache.ReadReq_accesses::cpu.inst 359757746 # number of ReadReq accesses(hits+misses) 1110system.cpu.icache.ReadReq_accesses::total 359757746 # number of ReadReq accesses(hits+misses) 1111system.cpu.icache.demand_accesses::cpu.inst 359757746 # number of demand (read+write) accesses 1112system.cpu.icache.demand_accesses::total 359757746 # number of demand (read+write) accesses 1113system.cpu.icache.overall_accesses::cpu.inst 359757746 # number of overall (read+write) accesses 1114system.cpu.icache.overall_accesses::total 359757746 # number of overall (read+write) accesses 1115system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043924 # miss rate for ReadReq accesses 1116system.cpu.icache.ReadReq_miss_rate::total 0.043924 # miss rate for ReadReq accesses 1117system.cpu.icache.demand_miss_rate::cpu.inst 0.043924 # miss rate for demand accesses 1118system.cpu.icache.demand_miss_rate::total 0.043924 # miss rate for demand accesses 1119system.cpu.icache.overall_miss_rate::cpu.inst 0.043924 # miss rate for overall accesses 1120system.cpu.icache.overall_miss_rate::total 0.043924 # miss rate for overall accesses 1121system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793 # average ReadReq miss latency 1122system.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793 # average ReadReq miss latency 1123system.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency 1124system.cpu.icache.demand_avg_miss_latency::total 13174.996793 # average overall miss latency 1125system.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency 1126system.cpu.icache.overall_avg_miss_latency::total 13174.996793 # average overall miss latency 1127system.cpu.icache.blocked_cycles::no_mshrs 11061 # number of cycles access was blocked 1128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1129system.cpu.icache.blocked::no_mshrs 978 # number of cycles access was blocked 1130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1131system.cpu.icache.avg_blocked_cycles::no_mshrs 11.309816 # average number of cycles each access was blocked 1132system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1133system.cpu.icache.fast_writes 0 # number of fast writes performed 1134system.cpu.icache.cache_copies 0 # number of cache copies performed 1135system.cpu.icache.ReadReq_mshr_hits::cpu.inst 717343 # number of ReadReq MSHR hits 1136system.cpu.icache.ReadReq_mshr_hits::total 717343 # number of ReadReq MSHR hits 1137system.cpu.icache.demand_mshr_hits::cpu.inst 717343 # number of demand (read+write) MSHR hits 1138system.cpu.icache.demand_mshr_hits::total 717343 # number of demand (read+write) MSHR hits 1139system.cpu.icache.overall_mshr_hits::cpu.inst 717343 # number of overall MSHR hits 1140system.cpu.icache.overall_mshr_hits::total 717343 # number of overall MSHR hits 1141system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15084780 # number of ReadReq MSHR misses 1142system.cpu.icache.ReadReq_mshr_misses::total 15084780 # number of ReadReq MSHR misses 1143system.cpu.icache.demand_mshr_misses::cpu.inst 15084780 # number of demand (read+write) MSHR misses 1144system.cpu.icache.demand_mshr_misses::total 15084780 # number of demand (read+write) MSHR misses 1145system.cpu.icache.overall_mshr_misses::cpu.inst 15084780 # number of overall MSHR misses 1146system.cpu.icache.overall_mshr_misses::total 15084780 # number of overall MSHR misses 1147system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171798629050 # number of ReadReq MSHR miss cycles 1148system.cpu.icache.ReadReq_mshr_miss_latency::total 171798629050 # number of ReadReq MSHR miss cycles 1149system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171798629050 # number of demand (read+write) MSHR miss cycles 1150system.cpu.icache.demand_mshr_miss_latency::total 171798629050 # number of demand (read+write) MSHR miss cycles 1151system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171798629050 # number of overall MSHR miss cycles 1152system.cpu.icache.overall_mshr_miss_latency::total 171798629050 # number of overall MSHR miss cycles 1153system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1412899000 # number of ReadReq MSHR uncacheable cycles 1154system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1412899000 # number of ReadReq MSHR uncacheable cycles 1155system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1412899000 # number of overall MSHR uncacheable cycles 1156system.cpu.icache.overall_mshr_uncacheable_latency::total 1412899000 # number of overall MSHR uncacheable cycles 1157system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for ReadReq accesses 1158system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041930 # mshr miss rate for ReadReq accesses 1159system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for demand accesses 1160system.cpu.icache.demand_mshr_miss_rate::total 0.041930 # mshr miss rate for demand accesses 1161system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for overall accesses 1162system.cpu.icache.overall_mshr_miss_rate::total 0.041930 # mshr miss rate for overall accesses 1163system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032 # average ReadReq mshr miss latency 1164system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11388.872032 # average ReadReq mshr miss latency 1165system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency 1166system.cpu.icache.demand_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency 1167system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency 1168system.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency 1169system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1170system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1171system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1172system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1173system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1174system.cpu.l2cache.tags.replacements 1166252 # number of replacements 1175system.cpu.l2cache.tags.tagsinuse 65308.801684 # Cycle average of tags in use 1176system.cpu.l2cache.tags.total_refs 29080427 # Total number of references to valid blocks. 1177system.cpu.l2cache.tags.sampled_refs 1229042 # Sample count of references to valid blocks. 1178system.cpu.l2cache.tags.avg_refs 23.661052 # Average number of references to valid blocks. 1179system.cpu.l2cache.tags.warmup_cycle 2430267000 # Cycle when the warmup percentage was hit. 1180system.cpu.l2cache.tags.occ_blocks::writebacks 37210.550558 # Average occupied blocks per requestor 1181system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 324.848912 # Average occupied blocks per requestor 1182system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 496.111863 # Average occupied blocks per requestor 1183system.cpu.l2cache.tags.occ_blocks::cpu.inst 7620.063188 # Average occupied blocks per requestor 1184system.cpu.l2cache.tags.occ_blocks::cpu.data 19657.227164 # Average occupied blocks per requestor 1185system.cpu.l2cache.tags.occ_percent::writebacks 0.567788 # Average percentage of cache occupancy 1186system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004957 # Average percentage of cache occupancy 1187system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007570 # Average percentage of cache occupancy 1188system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116273 # Average percentage of cache occupancy 1189system.cpu.l2cache.tags.occ_percent::cpu.data 0.299945 # Average percentage of cache occupancy 1190system.cpu.l2cache.tags.occ_percent::total 0.996533 # Average percentage of cache occupancy 1191system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id 1192system.cpu.l2cache.tags.occ_task_id_blocks::1024 62489 # Occupied blocks per task id 1193system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 1194system.cpu.l2cache.tags.age_task_id_blocks_1023::4 300 # Occupied blocks per task id 1195system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1196system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id 1197system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2670 # Occupied blocks per task id 1198system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5157 # Occupied blocks per task id 1199system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id 1200system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id 1201system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953506 # Percentage of cache occupancy per task id 1202system.cpu.l2cache.tags.tag_accesses 273259305 # Number of tag accesses 1203system.cpu.l2cache.tags.data_accesses 273259305 # Number of data accesses 1204system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 799874 # number of ReadReq hits 1205system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299425 # number of ReadReq hits 1206system.cpu.l2cache.ReadReq_hits::cpu.inst 15000245 # number of ReadReq hits 1207system.cpu.l2cache.ReadReq_hits::cpu.data 6339023 # number of ReadReq hits 1208system.cpu.l2cache.ReadReq_hits::total 22438567 # number of ReadReq hits 1209system.cpu.l2cache.Writeback_hits::writebacks 7597183 # number of Writeback hits 1210system.cpu.l2cache.Writeback_hits::total 7597183 # number of Writeback hits 1211system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730326 # number of WriteInvalidateReq hits 1212system.cpu.l2cache.WriteInvalidateReq_hits::total 730326 # number of WriteInvalidateReq hits 1213system.cpu.l2cache.UpgradeReq_hits::cpu.data 9466 # number of UpgradeReq hits 1214system.cpu.l2cache.UpgradeReq_hits::total 9466 # number of UpgradeReq hits 1215system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1216system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 1217system.cpu.l2cache.ReadExReq_hits::cpu.data 1583904 # number of ReadExReq hits 1218system.cpu.l2cache.ReadExReq_hits::total 1583904 # number of ReadExReq hits 1219system.cpu.l2cache.demand_hits::cpu.dtb.walker 799874 # number of demand (read+write) hits 1220system.cpu.l2cache.demand_hits::cpu.itb.walker 299425 # number of demand (read+write) hits 1221system.cpu.l2cache.demand_hits::cpu.inst 15000245 # number of demand (read+write) hits 1222system.cpu.l2cache.demand_hits::cpu.data 7922927 # number of demand (read+write) hits 1223system.cpu.l2cache.demand_hits::total 24022471 # number of demand (read+write) hits 1224system.cpu.l2cache.overall_hits::cpu.dtb.walker 799874 # number of overall hits 1225system.cpu.l2cache.overall_hits::cpu.itb.walker 299425 # number of overall hits 1226system.cpu.l2cache.overall_hits::cpu.inst 15000245 # number of overall hits 1227system.cpu.l2cache.overall_hits::cpu.data 7922927 # number of overall hits 1228system.cpu.l2cache.overall_hits::total 24022471 # number of overall hits 1229system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3543 # number of ReadReq misses 1230system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3208 # number of ReadReq misses 1231system.cpu.l2cache.ReadReq_misses::cpu.inst 84445 # number of ReadReq misses 1232system.cpu.l2cache.ReadReq_misses::cpu.data 256196 # number of ReadReq misses 1233system.cpu.l2cache.ReadReq_misses::total 347392 # number of ReadReq misses 1234system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495854 # number of WriteInvalidateReq misses 1235system.cpu.l2cache.WriteInvalidateReq_misses::total 495854 # number of WriteInvalidateReq misses 1236system.cpu.l2cache.UpgradeReq_misses::cpu.data 34479 # number of UpgradeReq misses 1237system.cpu.l2cache.UpgradeReq_misses::total 34479 # number of UpgradeReq misses 1238system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1239system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1240system.cpu.l2cache.ReadExReq_misses::cpu.data 417812 # number of ReadExReq misses 1241system.cpu.l2cache.ReadExReq_misses::total 417812 # number of ReadExReq misses 1242system.cpu.l2cache.demand_misses::cpu.dtb.walker 3543 # number of demand (read+write) misses 1243system.cpu.l2cache.demand_misses::cpu.itb.walker 3208 # number of demand (read+write) misses 1244system.cpu.l2cache.demand_misses::cpu.inst 84445 # number of demand (read+write) misses 1245system.cpu.l2cache.demand_misses::cpu.data 674008 # number of demand (read+write) misses 1246system.cpu.l2cache.demand_misses::total 765204 # number of demand (read+write) misses 1247system.cpu.l2cache.overall_misses::cpu.dtb.walker 3543 # number of overall misses 1248system.cpu.l2cache.overall_misses::cpu.itb.walker 3208 # number of overall misses 1249system.cpu.l2cache.overall_misses::cpu.inst 84445 # number of overall misses 1250system.cpu.l2cache.overall_misses::cpu.data 674008 # number of overall misses 1251system.cpu.l2cache.overall_misses::total 765204 # number of overall misses 1252system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 284358999 # number of ReadReq miss cycles 1253system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 261200750 # number of ReadReq miss cycles 1254system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6500329478 # number of ReadReq miss cycles 1255system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21309046436 # number of ReadReq miss cycles 1256system.cpu.l2cache.ReadReq_miss_latency::total 28354935663 # number of ReadReq miss cycles 1257system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 3493350 # number of WriteInvalidateReq miss cycles 1258system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 3493350 # number of WriteInvalidateReq miss cycles 1259system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 414507203 # number of UpgradeReq miss cycles 1260system.cpu.l2cache.UpgradeReq_miss_latency::total 414507203 # number of UpgradeReq miss cycles 1261system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 72000 # number of SCUpgradeReq miss cycles 1262system.cpu.l2cache.SCUpgradeReq_miss_latency::total 72000 # number of SCUpgradeReq miss cycles 1263system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34565495113 # number of ReadExReq miss cycles 1264system.cpu.l2cache.ReadExReq_miss_latency::total 34565495113 # number of ReadExReq miss cycles 1265system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 284358999 # number of demand (read+write) miss cycles 1266system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 261200750 # number of demand (read+write) miss cycles 1267system.cpu.l2cache.demand_miss_latency::cpu.inst 6500329478 # number of demand (read+write) miss cycles 1268system.cpu.l2cache.demand_miss_latency::cpu.data 55874541549 # number of demand (read+write) miss cycles 1269system.cpu.l2cache.demand_miss_latency::total 62920430776 # number of demand (read+write) miss cycles 1270system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 284358999 # number of overall miss cycles 1271system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 261200750 # number of overall miss cycles 1272system.cpu.l2cache.overall_miss_latency::cpu.inst 6500329478 # number of overall miss cycles 1273system.cpu.l2cache.overall_miss_latency::cpu.data 55874541549 # number of overall miss cycles 1274system.cpu.l2cache.overall_miss_latency::total 62920430776 # number of overall miss cycles 1275system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 803417 # number of ReadReq accesses(hits+misses) 1276system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302633 # number of ReadReq accesses(hits+misses) 1277system.cpu.l2cache.ReadReq_accesses::cpu.inst 15084690 # number of ReadReq accesses(hits+misses) 1278system.cpu.l2cache.ReadReq_accesses::cpu.data 6595219 # number of ReadReq accesses(hits+misses) 1279system.cpu.l2cache.ReadReq_accesses::total 22785959 # number of ReadReq accesses(hits+misses) 1280system.cpu.l2cache.Writeback_accesses::writebacks 7597183 # number of Writeback accesses(hits+misses) 1281system.cpu.l2cache.Writeback_accesses::total 7597183 # number of Writeback accesses(hits+misses) 1282system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226180 # number of WriteInvalidateReq accesses(hits+misses) 1283system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226180 # number of WriteInvalidateReq accesses(hits+misses) 1284system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43945 # number of UpgradeReq accesses(hits+misses) 1285system.cpu.l2cache.UpgradeReq_accesses::total 43945 # number of UpgradeReq accesses(hits+misses) 1286system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1287system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 1288system.cpu.l2cache.ReadExReq_accesses::cpu.data 2001716 # number of ReadExReq accesses(hits+misses) 1289system.cpu.l2cache.ReadExReq_accesses::total 2001716 # number of ReadExReq accesses(hits+misses) 1290system.cpu.l2cache.demand_accesses::cpu.dtb.walker 803417 # number of demand (read+write) accesses 1291system.cpu.l2cache.demand_accesses::cpu.itb.walker 302633 # number of demand (read+write) accesses 1292system.cpu.l2cache.demand_accesses::cpu.inst 15084690 # number of demand (read+write) accesses 1293system.cpu.l2cache.demand_accesses::cpu.data 8596935 # number of demand (read+write) accesses 1294system.cpu.l2cache.demand_accesses::total 24787675 # number of demand (read+write) accesses 1295system.cpu.l2cache.overall_accesses::cpu.dtb.walker 803417 # number of overall (read+write) accesses 1296system.cpu.l2cache.overall_accesses::cpu.itb.walker 302633 # number of overall (read+write) accesses 1297system.cpu.l2cache.overall_accesses::cpu.inst 15084690 # number of overall (read+write) accesses 1298system.cpu.l2cache.overall_accesses::cpu.data 8596935 # number of overall (read+write) accesses 1299system.cpu.l2cache.overall_accesses::total 24787675 # number of overall (read+write) accesses 1300system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004410 # miss rate for ReadReq accesses 1301system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010600 # miss rate for ReadReq accesses 1302system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005598 # miss rate for ReadReq accesses 1303system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038846 # miss rate for ReadReq accesses 1304system.cpu.l2cache.ReadReq_miss_rate::total 0.015246 # miss rate for ReadReq accesses 1305system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404389 # miss rate for WriteInvalidateReq accesses 1306system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404389 # miss rate for WriteInvalidateReq accesses 1307system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784594 # miss rate for UpgradeReq accesses 1308system.cpu.l2cache.UpgradeReq_miss_rate::total 0.784594 # miss rate for UpgradeReq accesses 1309system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1310system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 1311system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.208727 # miss rate for ReadExReq accesses 1312system.cpu.l2cache.ReadExReq_miss_rate::total 0.208727 # miss rate for ReadExReq accesses 1313system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004410 # miss rate for demand accesses 1314system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010600 # miss rate for demand accesses 1315system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005598 # miss rate for demand accesses 1316system.cpu.l2cache.demand_miss_rate::cpu.data 0.078401 # miss rate for demand accesses 1317system.cpu.l2cache.demand_miss_rate::total 0.030870 # miss rate for demand accesses 1318system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004410 # miss rate for overall accesses 1319system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010600 # miss rate for overall accesses 1320system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005598 # miss rate for overall accesses 1321system.cpu.l2cache.overall_miss_rate::cpu.data 0.078401 # miss rate for overall accesses 1322system.cpu.l2cache.overall_miss_rate::total 0.030870 # miss rate for overall accesses 1323system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 80259.384420 # average ReadReq miss latency 1324system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81421.680175 # average ReadReq miss latency 1325system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76977.079496 # average ReadReq miss latency 1326system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83174.781948 # average ReadReq miss latency 1327system.cpu.l2cache.ReadReq_avg_miss_latency::total 81622.304667 # average ReadReq miss latency 1328system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 7.045118 # average WriteInvalidateReq miss latency 1329system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 7.045118 # average WriteInvalidateReq miss latency 1330system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12022.019287 # average UpgradeReq miss latency 1331system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12022.019287 # average UpgradeReq miss latency 1332system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 36000 # average SCUpgradeReq miss latency 1333system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 36000 # average SCUpgradeReq miss latency 1334system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82729.780650 # average ReadExReq miss latency 1335system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82729.780650 # average ReadExReq miss latency 1336system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency 1337system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency 1338system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency 1339system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency 1340system.cpu.l2cache.demand_avg_miss_latency::total 82227.001918 # average overall miss latency 1341system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency 1342system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency 1343system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency 1344system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency 1345system.cpu.l2cache.overall_avg_miss_latency::total 82227.001918 # average overall miss latency 1346system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1347system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1348system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1349system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1350system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1351system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1352system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1353system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1354system.cpu.l2cache.writebacks::writebacks 982720 # number of writebacks 1355system.cpu.l2cache.writebacks::total 982720 # number of writebacks 1356system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 1357system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits 1358system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1359system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits 1360system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1361system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits 1362system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3543 # number of ReadReq MSHR misses 1363system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3208 # number of ReadReq MSHR misses 1364system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84445 # number of ReadReq MSHR misses 1365system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256175 # number of ReadReq MSHR misses 1366system.cpu.l2cache.ReadReq_mshr_misses::total 347371 # number of ReadReq MSHR misses 1367system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495854 # number of WriteInvalidateReq MSHR misses 1368system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495854 # number of WriteInvalidateReq MSHR misses 1369system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34479 # number of UpgradeReq MSHR misses 1370system.cpu.l2cache.UpgradeReq_mshr_misses::total 34479 # number of UpgradeReq MSHR misses 1371system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1372system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1373system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 417812 # number of ReadExReq MSHR misses 1374system.cpu.l2cache.ReadExReq_mshr_misses::total 417812 # number of ReadExReq MSHR misses 1375system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3543 # number of demand (read+write) MSHR misses 1376system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3208 # number of demand (read+write) MSHR misses 1377system.cpu.l2cache.demand_mshr_misses::cpu.inst 84445 # number of demand (read+write) MSHR misses 1378system.cpu.l2cache.demand_mshr_misses::cpu.data 673987 # number of demand (read+write) MSHR misses 1379system.cpu.l2cache.demand_mshr_misses::total 765183 # number of demand (read+write) MSHR misses 1380system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3543 # number of overall MSHR misses 1381system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3208 # number of overall MSHR misses 1382system.cpu.l2cache.overall_mshr_misses::cpu.inst 84445 # number of overall MSHR misses 1383system.cpu.l2cache.overall_mshr_misses::cpu.data 673987 # number of overall MSHR misses 1384system.cpu.l2cache.overall_mshr_misses::total 765183 # number of overall MSHR misses 1385system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 240086499 # number of ReadReq MSHR miss cycles 1386system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 221074750 # number of ReadReq MSHR miss cycles 1387system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5441255518 # number of ReadReq MSHR miss cycles 1388system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18116835264 # number of ReadReq MSHR miss cycles 1389system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24019252031 # number of ReadReq MSHR miss cycles 1390system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 19575424791 # number of WriteInvalidateReq MSHR miss cycles 1391system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 19575424791 # number of WriteInvalidateReq MSHR miss cycles 1392system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345346475 # number of UpgradeReq MSHR miss cycles 1393system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345346475 # number of UpgradeReq MSHR miss cycles 1394system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70001 # number of SCUpgradeReq MSHR miss cycles 1395system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70001 # number of SCUpgradeReq MSHR miss cycles 1396system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29394156879 # number of ReadExReq MSHR miss cycles 1397system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29394156879 # number of ReadExReq MSHR miss cycles 1398system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 240086499 # number of demand (read+write) MSHR miss cycles 1399system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 221074750 # number of demand (read+write) MSHR miss cycles 1400system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5441255518 # number of demand (read+write) MSHR miss cycles 1401system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47510992143 # number of demand (read+write) MSHR miss cycles 1402system.cpu.l2cache.demand_mshr_miss_latency::total 53413408910 # number of demand (read+write) MSHR miss cycles 1403system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 240086499 # number of overall MSHR miss cycles 1404system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 221074750 # number of overall MSHR miss cycles 1405system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5441255518 # number of overall MSHR miss cycles 1406system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47510992143 # number of overall MSHR miss cycles 1407system.cpu.l2cache.overall_mshr_miss_latency::total 53413408910 # number of overall MSHR miss cycles 1408system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103864500 # number of ReadReq MSHR uncacheable cycles 1409system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289749251 # number of ReadReq MSHR uncacheable cycles 1410system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393613751 # number of ReadReq MSHR uncacheable cycles 1411system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176073500 # number of WriteReq MSHR uncacheable cycles 1412system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176073500 # number of WriteReq MSHR uncacheable cycles 1413system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103864500 # number of overall MSHR uncacheable cycles 1414system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465822751 # number of overall MSHR uncacheable cycles 1415system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569687251 # number of overall MSHR uncacheable cycles 1416system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for ReadReq accesses 1417system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for ReadReq accesses 1418system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for ReadReq accesses 1419system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038843 # mshr miss rate for ReadReq accesses 1420system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015245 # mshr miss rate for ReadReq accesses 1421system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404389 # mshr miss rate for WriteInvalidateReq accesses 1422system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404389 # mshr miss rate for WriteInvalidateReq accesses 1423system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784594 # mshr miss rate for UpgradeReq accesses 1424system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784594 # mshr miss rate for UpgradeReq accesses 1425system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1426system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 1427system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208727 # mshr miss rate for ReadExReq accesses 1428system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208727 # mshr miss rate for ReadExReq accesses 1429system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for demand accesses 1430system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for demand accesses 1431system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for demand accesses 1432system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for demand accesses 1433system.cpu.l2cache.demand_mshr_miss_rate::total 0.030869 # mshr miss rate for demand accesses 1434system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for overall accesses 1435system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for overall accesses 1436system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for overall accesses 1437system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for overall accesses 1438system.cpu.l2cache.overall_mshr_miss_rate::total 0.030869 # mshr miss rate for overall accesses 1439system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average ReadReq mshr miss latency 1440system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average ReadReq mshr miss latency 1441system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690 # average ReadReq mshr miss latency 1442system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628 # average ReadReq mshr miss latency 1443system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249 # average ReadReq mshr miss latency 1444system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840 # average WriteInvalidateReq mshr miss latency 1445system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840 # average WriteInvalidateReq mshr miss latency 1446system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534 # average UpgradeReq mshr miss latency 1447system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534 # average UpgradeReq mshr miss latency 1448system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency 1449system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency 1450system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307 # average ReadExReq mshr miss latency 1451system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307 # average ReadExReq mshr miss latency 1452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency 1453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency 1454system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency 1455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency 1456system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency 1457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency 1458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency 1459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency 1460system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency 1461system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency 1462system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1463system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1464system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1465system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1466system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1467system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1468system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1469system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1470system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1471system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution 1472system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution 1473system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution 1474system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution 1475system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution 1476system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution 1477system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution 1478system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution 1481system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution 1482system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution 1483system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) 1484system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) 1485system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) 1486system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) 1487system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) 1488system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) 1489system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) 1490system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) 1491system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) 1492system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) 1493system.cpu.toL2Bus.snoops 606880 # Total snoops (count) 1494system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram 1495system.cpu.toL2Bus.snoop_fanout::mean 5.003347 # Request fanout histogram 1496system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram 1497system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1498system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1499system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1500system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1501system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1502system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1503system.cpu.toL2Bus.snoop_fanout::5 34397489 99.67% 99.67% # Request fanout histogram 1504system.cpu.toL2Bus.snoop_fanout::6 115519 0.33% 100.00% # Request fanout histogram 1505system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1506system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1507system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1508system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram 1509system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) 1510system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1511system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) 1512system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1513system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) 1514system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1515system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) 1516system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1517system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) 1518system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1519system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) 1520system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1521system.iobus.trans_dist::ReadReq 40381 # Transaction distribution 1522system.iobus.trans_dist::ReadResp 40381 # Transaction distribution 1523system.iobus.trans_dist::WriteReq 136733 # Transaction distribution 1524system.iobus.trans_dist::WriteResp 30069 # Transaction distribution 1525system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 1526system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) 1527system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1528system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1531system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1534system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1535system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1536system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1537system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1538system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1539system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1540system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1541system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) 1542system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) 1543system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) 1544system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1545system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1546system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) 1548system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1549system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1550system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1551system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1552system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1553system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1554system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1555system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1556system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1557system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1558system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1559system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1560system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1561system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1562system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) 1563system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) 1564system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) 1565system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1566system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) 1569system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1570system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1571system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1572system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1573system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1574system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1575system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1576system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1577system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1578system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1579system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1580system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1581system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1582system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1583system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1584system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1585system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1586system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1587system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1588system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1589system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1590system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1591system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1592system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1593system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1594system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1595system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1596system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) 1597system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1598system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1599system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1600system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) 1601system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1602system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) 1603system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1604system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 1605system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1606system.iocache.tags.replacements 115461 # number of replacements 1607system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use 1608system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1609system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. 1610system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1611system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. 1612system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor 1613system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor 1614system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy 1615system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy 1616system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy 1617system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1618system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1619system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1620system.iocache.tags.tag_accesses 1039668 # Number of tag accesses 1621system.iocache.tags.data_accesses 1039668 # Number of data accesses 1622system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1623system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses 1624system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses 1625system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1626system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1627system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 1628system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 1629system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1630system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses 1631system.iocache.demand_misses::total 8855 # number of demand (read+write) misses 1632system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1633system.iocache.overall_misses::realview.ide 8815 # number of overall misses 1634system.iocache.overall_misses::total 8855 # number of overall misses 1635system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles 1636system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles 1637system.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles 1638system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles 1639system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles 1640system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles 1641system.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles 1642system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles 1643system.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles 1644system.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles 1645system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles 1646system.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles 1647system.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles 1648system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1649system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) 1650system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) 1651system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1652system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1653system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 1654system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 1655system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1656system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses 1657system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses 1658system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1659system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses 1660system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses 1661system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1662system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1663system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1664system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1665system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1666system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1667system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1668system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1669system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1670system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1671system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1672system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1673system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1674system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency 1675system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency 1676system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency 1677system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency 1678system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency 1679system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency 1680system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency 1681system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency 1682system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency 1683system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency 1684system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency 1685system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency 1686system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency 1687system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked 1688system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1689system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked 1690system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1691system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked 1692system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1693system.iocache.fast_writes 0 # number of fast writes performed 1694system.iocache.cache_copies 0 # number of cache copies performed 1695system.iocache.writebacks::writebacks 106631 # number of writebacks 1696system.iocache.writebacks::total 106631 # number of writebacks 1697system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1698system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses 1699system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses 1700system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1701system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1702system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 1703system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses 1704system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1705system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses 1706system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses 1707system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1708system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses 1709system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses 1710system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles 1711system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles 1712system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles 1713system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles 1714system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles 1715system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles 1716system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles 1717system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles 1718system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles 1719system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles 1720system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles 1721system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles 1722system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles 1723system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1724system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1725system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1726system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1727system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1728system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1729system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1730system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1731system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1732system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1733system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1734system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1735system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1736system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency 1737system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency 1738system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency 1739system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency 1740system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 1741system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency 1742system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency 1743system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency 1744system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency 1745system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency 1746system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency 1747system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency 1748system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency 1749system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1750system.membus.trans_dist::ReadReq 411277 # Transaction distribution 1751system.membus.trans_dist::ReadResp 411277 # Transaction distribution 1752system.membus.trans_dist::WriteReq 33858 # Transaction distribution 1753system.membus.trans_dist::WriteResp 33858 # Transaction distribution 1754system.membus.trans_dist::Writeback 1089351 # Transaction distribution 1755system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution 1756system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution 1757system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution 1758system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1759system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution 1760system.membus.trans_dist::ReadExReq 417183 # Transaction distribution 1761system.membus.trans_dist::ReadExResp 417183 # Transaction distribution 1762system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) 1763system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) 1764system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) 1765system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) 1766system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) 1767system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) 1768system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) 1769system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) 1770system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) 1771system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) 1772system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) 1773system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) 1774system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) 1775system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) 1776system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) 1777system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) 1778system.membus.snoops 3154 # Total snoops (count) 1779system.membus.snoop_fanout::samples 2500418 # Request fanout histogram 1780system.membus.snoop_fanout::mean 1 # Request fanout histogram 1781system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1782system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1783system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1784system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram 1785system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1786system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1787system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1788system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1789system.membus.snoop_fanout::total 2500418 # Request fanout histogram 1790system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) 1791system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1792system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) 1793system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1794system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) 1795system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1796system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) 1797system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1798system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) 1799system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1800system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) 1801system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1802system.realview.ethernet.txBytes 966 # Bytes Transmitted 1803system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1804system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1805system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1806system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1807system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1808system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1809system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1810system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1811system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 1812system.realview.ethernet.totPackets 3 # Total Packets 1813system.realview.ethernet.totBytes 966 # Total Bytes 1814system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1815system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 1816system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1817system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1818system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1819system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1820system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1821system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1822system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1823system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1824system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1825system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1826system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1827system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1828system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1829system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1830system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1831system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1832system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1833system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1834system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1835system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1836system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1837system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1838system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1839system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1840system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1841system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1842system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1843system.realview.ethernet.droppedPackets 0 # number of packets dropped 1844system.cpu.kern.inst.arm 0 # number of arm instructions executed 1845system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed 1846 1847---------- End Simulation Statistics ---------- 1848