stats.txt revision 11441
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311353Sandreas.hansson@arm.comsim_seconds 51.327140 # Number of seconds simulated 411441Sandreas.hansson@arm.comsim_ticks 51327139864000 # Number of ticks simulated 511441Sandreas.hansson@arm.comfinal_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711441Sandreas.hansson@arm.comhost_inst_rate 139665 # Simulator instruction rate (inst/s) 811441Sandreas.hansson@arm.comhost_op_rate 164109 # Simulator op (including micro ops) rate (op/s) 911441Sandreas.hansson@arm.comhost_tick_rate 8451911555 # Simulator tick rate (ticks/s) 1011441Sandreas.hansson@arm.comhost_mem_usage 688288 # Number of bytes of host memory used 1111441Sandreas.hansson@arm.comhost_seconds 6072.84 # Real time elapsed on the host 1211441Sandreas.hansson@arm.comsim_insts 848164321 # Number of instructions simulated 1311441Sandreas.hansson@arm.comsim_ops 996610207 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory 1711441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory 1811441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory 1911441Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory 2011441Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory 2111441Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 48132008 # Number of bytes read from this memory 2211441Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory 2311441Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory 2411441Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 68386496 # Number of bytes written to this memory 2510585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2611441Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 68407076 # Number of bytes written to this memory 2711441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory 2811441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 3383 # Number of read requests responded to by this memory 2911441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 104417 # Number of read requests responded to by this memory 3011441Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 649748 # Number of read requests responded to by this memory 3111441Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6922 # Number of read requests responded to by this memory 3211441Sandreas.hansson@arm.comsystem.physmem.num_reads::total 768028 # Number of read requests responded to by this memory 3311441Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1068539 # Number of write requests responded to by this memory 3410585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3511441Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1071112 # Number of write requests responded to by this memory 3611441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) 3711441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 4218 # Total read bandwidth from this memory (bytes/s) 3811441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 110307 # Total read bandwidth from this memory (bytes/s) 3911441Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 810157 # Total read bandwidth from this memory (bytes/s) 4011441Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8631 # Total read bandwidth from this memory (bytes/s) 4111441Sandreas.hansson@arm.comsystem.physmem.bw_read::total 937750 # Total read bandwidth from this memory (bytes/s) 4211441Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 110307 # Instruction read bandwidth from this memory (bytes/s) 4311441Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 110307 # Instruction read bandwidth from this memory (bytes/s) 4411441Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1332365 # Write bandwidth from this memory (bytes/s) 4511138Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) 4611441Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1332766 # Write bandwidth from this memory (bytes/s) 4711441Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1332365 # Total bandwidth to/from this memory (bytes/s) 4811441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) 4911441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 4218 # Total bandwidth to/from this memory (bytes/s) 5011441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 110307 # Total bandwidth to/from this memory (bytes/s) 5111441Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 810558 # Total bandwidth to/from this memory (bytes/s) 5211441Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8631 # Total bandwidth to/from this memory (bytes/s) 5311441Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2270516 # Total bandwidth to/from this memory (bytes/s) 5411441Sandreas.hansson@arm.comsystem.physmem.readReqs 768028 # Number of read requests accepted 5511441Sandreas.hansson@arm.comsystem.physmem.writeReqs 1071112 # Number of write requests accepted 5611441Sandreas.hansson@arm.comsystem.physmem.readBursts 768028 # Number of DRAM read bursts, including those serviced by the write queue 5711441Sandreas.hansson@arm.comsystem.physmem.writeBursts 1071112 # Number of DRAM write bursts, including those merged in the write queue 5811441Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 49106944 # Total number of bytes read from DRAM 5911441Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 46848 # Total number of bytes read from write queue 6011441Sandreas.hansson@arm.comsystem.physmem.bytesWritten 68406272 # Total number of bytes written to DRAM 6111441Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 48132008 # Total read bytes from the system interface side 6211441Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 68407076 # Total written bytes from the system interface side 6311441Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 732 # Number of DRAM read bursts serviced by the write queue 6411441Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 6511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6611441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 45073 # Per bank write bursts 6711441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 51507 # Per bank write bursts 6811441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 47331 # Per bank write bursts 6911441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 43047 # Per bank write bursts 7011441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 45469 # Per bank write bursts 7111441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 51901 # Per bank write bursts 7211441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 46387 # Per bank write bursts 7311441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 47163 # Per bank write bursts 7411441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 43832 # Per bank write bursts 7511441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 71407 # Per bank write bursts 7611441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 44269 # Per bank write bursts 7711441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 52269 # Per bank write bursts 7811441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 42900 # Per bank write bursts 7911441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 46591 # Per bank write bursts 8011441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 43222 # Per bank write bursts 8111441Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 44928 # Per bank write bursts 8211441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 64149 # Per bank write bursts 8311441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 68917 # Per bank write bursts 8411441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 66979 # Per bank write bursts 8511441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 64863 # Per bank write bursts 8611441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 67442 # Per bank write bursts 8711441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 70404 # Per bank write bursts 8811441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 66306 # Per bank write bursts 8911441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 67867 # Per bank write bursts 9011441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 65614 # Per bank write bursts 9111441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 70732 # Per bank write bursts 9211441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 65165 # Per bank write bursts 9311441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 71475 # Per bank write bursts 9411441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 63578 # Per bank write bursts 9511441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 66114 # Per bank write bursts 9611441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 64356 # Per bank write bursts 9711441Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 64887 # Per bank write bursts 9810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911441Sandreas.hansson@arm.comsystem.physmem.numWrRetry 30 # Number of times write queue was full causing retry 10011441Sandreas.hansson@arm.comsystem.physmem.totGap 51327138450500 # Total gap between requests 10110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 21272 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711441Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 746743 # Read request sizes (log2) 10810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411441Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1068539 # Write request sizes (log2) 11511441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 514973 # What read queue length does an incoming req see 11611441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 203448 # What read queue length does an incoming req see 11711441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 30161 # What read queue length does an incoming req see 11811441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 13041 # What read queue length does an incoming req see 11911441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 560 # What read queue length does an incoming req see 12011441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 583 # What read queue length does an incoming req see 12111441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see 12211441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1293 # What read queue length does an incoming req see 12311441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 823 # What read queue length does an incoming req see 12411441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 348 # What read queue length does an incoming req see 12511441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 378 # What read queue length does an incoming req see 12611441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 172 # What read queue length does an incoming req see 12711441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see 12811441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 144 # What read queue length does an incoming req see 12911441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see 13011441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see 13111441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see 13211441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see 13311441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see 13411441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 67 # What read queue length does an incoming req see 13511353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 13611441Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 13711353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 26679 # What write queue length does an incoming req see 16311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 32258 # What write queue length does an incoming req see 16411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 49491 # What write queue length does an incoming req see 16511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 54571 # What write queue length does an incoming req see 16611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 60622 # What write queue length does an incoming req see 16711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 60924 # What write queue length does an incoming req see 16811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 61854 # What write queue length does an incoming req see 16911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 62030 # What write queue length does an incoming req see 17011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 62034 # What write queue length does an incoming req see 17111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 69964 # What write queue length does an incoming req see 17211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 64040 # What write queue length does an incoming req see 17311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 77106 # What write queue length does an incoming req see 17411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 62260 # What write queue length does an incoming req see 17511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 64857 # What write queue length does an incoming req see 17611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 68599 # What write queue length does an incoming req see 17711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 60523 # What write queue length does an incoming req see 17811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 58973 # What write queue length does an incoming req see 17911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 57173 # What write queue length does an incoming req see 18011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3304 # What write queue length does an incoming req see 18111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1471 # What write queue length does an incoming req see 18211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1171 # What write queue length does an incoming req see 18311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 974 # What write queue length does an incoming req see 18411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 962 # What write queue length does an incoming req see 18511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 864 # What write queue length does an incoming req see 18611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 689 # What write queue length does an incoming req see 18711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 588 # What write queue length does an incoming req see 18811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 543 # What write queue length does an incoming req see 18911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 437 # What write queue length does an incoming req see 19011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see 19111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see 19211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see 19311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see 19411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see 19511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 213 # What write queue length does an incoming req see 19611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see 19711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 250 # What write queue length does an incoming req see 19811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 164 # What write queue length does an incoming req see 19911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see 20011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 154 # What write queue length does an incoming req see 20111441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see 20211441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see 20311441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see 20411441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 211 # What write queue length does an incoming req see 20511441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 105 # What write queue length does an incoming req see 20611441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see 20711441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 83 # What write queue length does an incoming req see 20811441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see 20911441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see 21011441Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see 21111441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 471440 # Bytes accessed per row activation 21211441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 249.263737 # Bytes accessed per row activation 21311441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 149.464196 # Bytes accessed per row activation 21411441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 290.749786 # Bytes accessed per row activation 21511441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 207824 44.08% 44.08% # Bytes accessed per row activation 21611441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 122155 25.91% 69.99% # Bytes accessed per row activation 21711441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 42779 9.07% 79.07% # Bytes accessed per row activation 21811441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 22709 4.82% 83.88% # Bytes accessed per row activation 21911441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 14933 3.17% 87.05% # Bytes accessed per row activation 22011441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 9495 2.01% 89.07% # Bytes accessed per row activation 22111441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 7568 1.61% 90.67% # Bytes accessed per row activation 22211441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 6030 1.28% 91.95% # Bytes accessed per row activation 22311441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 37947 8.05% 100.00% # Bytes accessed per row activation 22411441Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 471440 # Bytes accessed per row activation 22511441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 54191 # Reads before turning the bus around for writes 22611441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 14.158790 # Reads before turning the bus around for writes 22711441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 76.596487 # Reads before turning the bus around for writes 22811441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-511 54185 99.99% 99.99% # Reads before turning the bus around for writes 22911441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes 23011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 23111353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 23211441Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 54191 # Reads before turning the bus around for writes 23311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 54191 # Writes before turning the bus around for reads 23411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 19.723718 # Writes before turning the bus around for reads 23511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.774638 # Writes before turning the bus around for reads 23611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 8.948432 # Writes before turning the bus around for reads 23711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 40576 74.88% 74.88% # Writes before turning the bus around for reads 23811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 4593 8.48% 83.35% # Writes before turning the bus around for reads 23911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 5177 9.55% 92.90% # Writes before turning the bus around for reads 24011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 1373 2.53% 95.44% # Writes before turning the bus around for reads 24111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 420 0.78% 96.21% # Writes before turning the bus around for reads 24211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 248 0.46% 96.67% # Writes before turning the bus around for reads 24311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 301 0.56% 97.23% # Writes before turning the bus around for reads 24411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 130 0.24% 97.47% # Writes before turning the bus around for reads 24511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 393 0.73% 98.19% # Writes before turning the bus around for reads 24611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 142 0.26% 98.45% # Writes before turning the bus around for reads 24711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 38 0.07% 98.52% # Writes before turning the bus around for reads 24811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 61 0.11% 98.64% # Writes before turning the bus around for reads 24911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 323 0.60% 99.23% # Writes before turning the bus around for reads 25011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 40 0.07% 99.31% # Writes before turning the bus around for reads 25111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 24 0.04% 99.35% # Writes before turning the bus around for reads 25211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 111 0.20% 99.56% # Writes before turning the bus around for reads 25311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 181 0.33% 99.89% # Writes before turning the bus around for reads 25411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads 25511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads 25611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads 25711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 25811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads 25911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads 26011353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads 26111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads 26211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads 26311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 14 0.03% 99.95% # Writes before turning the bus around for reads 26411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads 26511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 3 0.01% 99.96% # Writes before turning the bus around for reads 26611441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 9 0.02% 99.97% # Writes before turning the bus around for reads 26711441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads 26811441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 26911441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 2 0.00% 99.98% # Writes before turning the bus around for reads 27011441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-171 2 0.00% 99.98% # Writes before turning the bus around for reads 27111441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 6 0.01% 99.99% # Writes before turning the bus around for reads 27211441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 27311441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 27411441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 27511441Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 54191 # Writes before turning the bus around for reads 27611441Sandreas.hansson@arm.comsystem.physmem.totQLat 15195806089 # Total ticks spent queuing 27711441Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 29582606089 # Total ticks spent from burst creation until serviced by the DRAM 27811441Sandreas.hansson@arm.comsystem.physmem.totBusLat 3836480000 # Total ticks spent in databus transfers 27911441Sandreas.hansson@arm.comsystem.physmem.avgQLat 19804.36 # Average queueing delay per DRAM burst 28010515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 28111441Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 38554.36 # Average memory access latency per DRAM burst 28211353Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s 28311353Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s 28411353Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s 28511353Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s 28610515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28711138Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 28811138Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 28911138Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 29011441Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 29111441Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing 29211441Sandreas.hansson@arm.comsystem.physmem.readRowHits 579763 # Number of row buffer hits during reads 29311441Sandreas.hansson@arm.comsystem.physmem.writeRowHits 784939 # Number of row buffer hits during writes 29411441Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads 29511441Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes 29611441Sandreas.hansson@arm.comsystem.physmem.avgGap 27908228.00 # Average gap between requests 29711353Sandreas.hansson@arm.comsystem.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined 29811441Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 1800088920 # Energy for activate commands per rank (pJ) 29911441Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 982191375 # Energy for precharge commands per rank (pJ) 30011441Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 2947417200 # Energy for read commands per rank (pJ) 30111441Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3479286960 # Energy for write commands per rank (pJ) 30211353Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) 30311441Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1235810088180 # Energy for active background per rank (pJ) 30411441Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 29712239669250 # Energy for precharge background per rank (pJ) 30511441Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 34309697958765 # Total energy per rank (pJ) 30611441Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.451396 # Core power per rank (mW) 30711441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 49428932348966 # Time in different power states 30811353Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states 30910628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 31011441Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 184281028534 # Time in different power states 31110628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 31211441Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 1763997480 # Energy for activate commands per rank (pJ) 31311441Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 962498625 # Energy for precharge commands per rank (pJ) 31411441Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 3037452600 # Energy for read commands per rank (pJ) 31511441Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3446848080 # Energy for write commands per rank (pJ) 31611353Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) 31711441Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1235330422065 # Energy for active background per rank (pJ) 31811441Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ) 31911441Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ) 32011441Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.450284 # Core power per rank (mW) 32111441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states 32211353Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states 32310628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 32411441Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states 32510628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 32611201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory 32710585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 32811201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory 32911201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory 33011201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 33111201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 33210585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 33311201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 33411201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 33510585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 33611167Sjthestness@gmail.comsystem.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 33711201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 33811201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 33911201Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 34010585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 34111167Sjthestness@gmail.comsystem.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 34210585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 34310585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 34410585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 34510585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 34610585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 34710585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 34811441Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 225024609 # Number of BP lookups 34911441Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted 35011441Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 12305268 # Number of conditional branches incorrect 35111441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 158924221 # Number of BTB lookups 35211441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 98148969 # Number of BTB hits 35310585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 35411441Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage 35511441Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target. 35611441Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions. 35711441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups. 35811441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits. 35911441Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses. 36011441Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches. 36110585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 36210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 36310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 37410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 37510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 38410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 38910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 39010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39111441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 947007 # Table walker walks requested 39211441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors 39311441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate 39411441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate 39511441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting 39611441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency 39711441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency 39811441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency 39911441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0-65535 508020 99.30% 99.30% # Table walker wait (enqueue to first request) latency 40011441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::65536-131071 2030 0.40% 99.70% # Table walker wait (enqueue to first request) latency 40111441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::131072-196607 1046 0.20% 99.90% # Table walker wait (enqueue to first request) latency 40211441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::196608-262143 222 0.04% 99.94% # Table walker wait (enqueue to first request) latency 40311441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::262144-327679 147 0.03% 99.97% # Table walker wait (enqueue to first request) latency 40411441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency 40511441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::393216-458751 54 0.01% 99.99% # Table walker wait (enqueue to first request) latency 40611353Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency 40711441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 40811441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 40911441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 41011441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 511600 # Table walker wait (enqueue to first request) latency 41111441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 486864 # Table walker service (enqueue to completion) latency 41211441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 22927.774491 # Table walker service (enqueue to completion) latency 41311441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197 # Table walker service (enqueue to completion) latency 41411441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088 # Table walker service (enqueue to completion) latency 41511441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 475438 97.65% 97.65% # Table walker service (enqueue to completion) latency 41611441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 7837 1.61% 99.26% # Table walker service (enqueue to completion) latency 41711441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 2530 0.52% 99.78% # Table walker service (enqueue to completion) latency 41811441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 265 0.05% 99.84% # Table walker service (enqueue to completion) latency 41911441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 545 0.11% 99.95% # Table walker service (enqueue to completion) latency 42011441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 113 0.02% 99.97% # Table walker service (enqueue to completion) latency 42111441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 104 0.02% 99.99% # Table walker service (enqueue to completion) latency 42211441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 16 0.00% 100.00% # Table walker service (enqueue to completion) latency 42311441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency 42411441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 42511441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 42611441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 42711441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 486864 # Table walker service (enqueue to completion) latency 42811441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 779668807876 # Table walker pending requests distribution 42911441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::mean 0.725507 # Table walker pending requests distribution 43011441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::stdev 0.522451 # Table walker pending requests distribution 43111441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0-1 777433889876 99.71% 99.71% # Table walker pending requests distribution 43211441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::2-3 1160253500 0.15% 99.86% # Table walker pending requests distribution 43311441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::4-5 513477500 0.07% 99.93% # Table walker pending requests distribution 43411441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::6-7 201866500 0.03% 99.95% # Table walker pending requests distribution 43511441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::8-9 152233500 0.02% 99.97% # Table walker pending requests distribution 43611441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::10-11 119773500 0.02% 99.99% # Table walker pending requests distribution 43711441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::12-13 32296000 0.00% 99.99% # Table walker pending requests distribution 43811441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::14-15 52448000 0.01% 100.00% # Table walker pending requests distribution 43911441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::16-17 2569500 0.00% 100.00% # Table walker pending requests distribution 44011441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 779668807876 # Table walker pending requests distribution 44111441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 155483 90.77% 90.77% # Table walker page sizes translated 44211441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 15816 9.23% 100.00% # Table walker page sizes translated 44311441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 171299 # Table walker page sizes translated 44411441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 947007 # Table walker requests started/completed, data/inst 44510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44611441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 947007 # Table walker requests started/completed, data/inst 44711441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171299 # Table walker requests started/completed, data/inst 44810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44911441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 171299 # Table walker requests started/completed, data/inst 45011441Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 1118306 # Table walker requests started/completed, data/inst 45110585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 45210585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 45311441Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 169398877 # DTB read hits 45411441Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 674798 # DTB read misses 45511441Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 147332912 # DTB write hits 45611441Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 272209 # DTB write misses 45711138Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 45810585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45911353Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 46011353Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID 46111441Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB 46211441Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions 46311441Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch 46410585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 46511441Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions 46611441Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 170073675 # DTB read accesses 46711441Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 147605121 # DTB write accesses 46810585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 46911441Sandreas.hansson@arm.comsystem.cpu.dtb.hits 316731789 # DTB hits 47011441Sandreas.hansson@arm.comsystem.cpu.dtb.misses 947007 # DTB misses 47111441Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 317678796 # DTB accesses 47210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 48910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 49610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 49710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 49810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 49910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50111441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 162102 # Table walker walks requested 50211441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors 50311441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate 50411441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate 50511441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting 50611441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency 50711441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency 50811441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency 50911441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0-32767 143046 99.21% 99.21% # Table walker wait (enqueue to first request) latency 51011441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::32768-65535 588 0.41% 99.62% # Table walker wait (enqueue to first request) latency 51111441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::65536-98303 94 0.07% 99.68% # Table walker wait (enqueue to first request) latency 51211441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::98304-131071 159 0.11% 99.79% # Table walker wait (enqueue to first request) latency 51311441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::131072-163839 224 0.16% 99.95% # Table walker wait (enqueue to first request) latency 51411441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::163840-196607 44 0.03% 99.98% # Table walker wait (enqueue to first request) latency 51511353Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency 51611441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::229376-262143 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency 51711441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency 51811441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 51911441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 52011441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 52111441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 52211441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 52311441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 144186 # Table walker wait (enqueue to first request) latency 52411441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 139421 # Table walker service (enqueue to completion) latency 52511441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 28788.855337 # Table walker service (enqueue to completion) latency 52611441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 23782.658152 # Table walker service (enqueue to completion) latency 52711441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 24182.866310 # Table walker service (enqueue to completion) latency 52811441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 136254 97.73% 97.73% # Table walker service (enqueue to completion) latency 52911441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 690 0.49% 98.22% # Table walker service (enqueue to completion) latency 53011441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 2101 1.51% 99.73% # Table walker service (enqueue to completion) latency 53111441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 136 0.10% 99.83% # Table walker service (enqueue to completion) latency 53211441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency 53311441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 47 0.03% 99.97% # Table walker service (enqueue to completion) latency 53411441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency 53511441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency 53611441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 53711441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53811441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 139421 # Table walker service (enqueue to completion) latency 53911441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 680881393568 # Table walker pending requests distribution 54011441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::mean 0.947864 # Table walker pending requests distribution 54111441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::stdev 0.222600 # Table walker pending requests distribution 54211441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 35543211356 5.22% 5.22% # Table walker pending requests distribution 54311441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::1 645294358712 94.77% 99.99% # Table walker pending requests distribution 54411441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::2 43207500 0.01% 100.00% # Table walker pending requests distribution 54511441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::3 580000 0.00% 100.00% # Table walker pending requests distribution 54611441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::4 36000 0.00% 100.00% # Table walker pending requests distribution 54711441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 680881393568 # Table walker pending requests distribution 54811441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 120022 98.78% 98.78% # Table walker page sizes translated 54911441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1483 1.22% 100.00% # Table walker page sizes translated 55011441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 121505 # Table walker page sizes translated 55110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 55211441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162102 # Table walker requests started/completed, data/inst 55311441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 162102 # Table walker requests started/completed, data/inst 55410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 55511441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121505 # Table walker requests started/completed, data/inst 55611441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 121505 # Table walker requests started/completed, data/inst 55711441Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 283607 # Table walker requests started/completed, data/inst 55811441Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 357007788 # ITB inst hits 55911441Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 162102 # ITB inst misses 56010585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 56110585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 56210585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 56310585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 56411138Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 56510585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56611353Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 56711353Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID 56811441Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB 56910585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57010585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57110585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57211441Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions 57310585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 57410585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 57511441Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 357169890 # ITB inst accesses 57611441Sandreas.hansson@arm.comsystem.cpu.itb.hits 357007788 # DTB hits 57711441Sandreas.hansson@arm.comsystem.cpu.itb.misses 162102 # DTB misses 57811441Sandreas.hansson@arm.comsystem.cpu.itb.accesses 357169890 # DTB accesses 57911441Sandreas.hansson@arm.comsystem.cpu.numCycles 1631144067 # number of cpu cycles simulated 58010585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 58110585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 58211441Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss 58311441Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed 58411441Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered 58511441Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken 58611441Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked 58711441Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing 58811441Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb 58911441Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 59011441Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps 59111441Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions 59211441Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR 59311441Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched 59411441Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed 59511441Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed 59611441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total) 59711441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total) 59811441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total) 59910585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 60011441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total) 60111441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total) 60211441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total) 60311441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total) 60410585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 60510585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 60610585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 60711441Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total) 60811441Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle 60911441Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle 61011441Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle 61111441Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked 61211441Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 434104674 # Number of cycles decode is running 61311441Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking 61411441Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing 61511441Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch 61611441Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction 61711441Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode 61811441Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode 61911441Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing 62011441Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle 62111441Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking 62211441Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst 62311441Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 438965882 # Number of cycles rename is running 62411441Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking 62511441Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename 62611441Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename 62711441Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full 62811441Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full 62911441Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full 63011441Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full 63111441Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers 63211441Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed 63311441Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made 63411441Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups 63511441Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups 63611441Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed 63711441Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing 63811441Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed 63911441Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed 64011441Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer 64111441Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit. 64211441Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit. 64311441Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads. 64411441Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores. 64511441Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec) 64611441Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ 64711441Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued 64811441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued 64911441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling 65011441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph 65111441Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed 65211441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle 65311441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle 65411441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle 65510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 65611441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle 65711441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle 65811441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle 65911441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle 66011441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle 66111441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle 66210585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 66310585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 66410585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 66510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 66610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 66710585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 66811441Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle 66910585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 67011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available 67111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available 67211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available 67311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available 67411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available 67511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available 67611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available 67711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available 67811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available 67911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available 68011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available 68111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available 68211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available 68311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available 68411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available 68511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available 68611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available 68711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available 68811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available 68911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available 69011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available 69111441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available 69211441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available 69311441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available 69411441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available 69511441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 667 0.00% 35.09% # attempts to use FU when none available 69611441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available 69711441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available 69811441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available 69911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 44277065 26.88% 61.97% # attempts to use FU when none available 70011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 62625013 38.03% 100.00% # attempts to use FU when none available 70110585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 70210585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 70311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued 70411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 720295550 68.88% 68.88% # Type of FU issued 70511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 2531326 0.24% 69.12% # Type of FU issued 70611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 122856 0.01% 69.13% # Type of FU issued 70711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued 70811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued 70911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued 71011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued 71111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued 71211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued 71311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued 71411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued 71511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued 71611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued 71711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued 71811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued 71911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued 72011441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued 72111441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued 72211441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued 72311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued 72411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued 72511441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued 72611441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued 72711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued 72811441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued 72911441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 119220 0.01% 69.14% # Type of FU issued 73011353Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued 73111353Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued 73211353Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued 73311441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued 73411441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued 73510585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 73610585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 73711441Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued 73811441Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.641106 # Inst issue rate 73911441Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested 74011441Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst) 74111441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads 74211441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes 74311441Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses 74411441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads 74511441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes 74611441Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses 74711441Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses 74811441Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses 74911441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores 75010585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 75111441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed 75211441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed 75311441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations 75411441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed 75510585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 75610585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 75711441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled 75811441Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked 75910585Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 76011441Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing 76111441Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking 76211441Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking 76311441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ 76410585Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 76511441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions 76611441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions 76711441Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 22818732 # Number of dispatched non-speculative instructions 76811441Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 57696 # Number of times the IQ has become full, causing a stall 76911441Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 6782714 # Number of times the LSQ has become full, causing a stall 77011441Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 143083 # Number of memory order violations 77111441Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 3464744 # Number of branches that were predicted taken incorrectly 77211441Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 5492402 # Number of branches that were predicted not taken incorrectly 77311441Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 8957146 # Number of branch mispredicts detected at execute 77411441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 1034225316 # Number of executed instructions 77511441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 169386893 # Number of load instructions executed 77611441Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 10574140 # Number of squashed instructions skipped in execute 77710585Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 77811441Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 235018 # number of nop insts executed 77911441Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 316715121 # number of memory reference insts executed 78011441Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 196182084 # Number of branches executed 78111441Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 147328228 # Number of stores executed 78211441Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.634049 # Inst execution rate 78311441Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 1029119140 # cumulative count of insts sent to commit 78411441Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back 78511441Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 437817967 # num instructions producing a value 78611441Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 708345311 # num instructions consuming a value 78711441Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.630417 # insts written-back per cycle 78811441Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back 78911441Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit 79011441Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards 79111441Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted 79211441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle 79311441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle 79411441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle 79510585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 79611441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle 79711441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle 79811441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle 79911441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle 80011441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle 80111441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle 80211441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle 80311441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle 80411441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle 80510585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 80610585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 80710585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 80811441Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle 80911441Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 848164321 # Number of instructions committed 81011441Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed 81110585Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 81211441Sandreas.hansson@arm.comsystem.cpu.commit.refs 304407284 # Number of memory references committed 81311441Sandreas.hansson@arm.comsystem.cpu.commit.loads 159650119 # Number of loads committed 81411441Sandreas.hansson@arm.comsystem.cpu.commit.membars 6926917 # Number of memory barriers committed 81511441Sandreas.hansson@arm.comsystem.cpu.commit.branches 189306416 # Number of branches committed 81611441Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 898488 # Number of committed floating point instructions. 81711441Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 915651510 # Number of committed integer instructions. 81811441Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 25281717 # Number of function calls committed. 81910585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 82011441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 689843263 69.22% 69.22% # Class of committed instruction 82111441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 2149527 0.22% 69.43% # Class of committed instruction 82211441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 98159 0.01% 69.44% # Class of committed instruction 82311336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction 82411336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction 82511336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction 82611336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction 82711336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction 82811336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction 82911336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction 83011336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction 83111336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction 83211336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction 83311336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction 83411336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction 83511336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction 83611336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction 83711336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction 83811336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction 83911336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction 84011336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction 84111336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction 84211336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction 84311336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction 84411336Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction 84511353Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction 84611353Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction 84711353Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 84811353Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 84911441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction 85011441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction 85110585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 85210585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 85311441Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 996610207 # Class of committed instruction 85411441Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached 85511441Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 2588836198 # The number of ROB reads 85611441Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 2108972650 # The number of ROB writes 85711441Sandreas.hansson@arm.comsystem.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself 85811441Sandreas.hansson@arm.comsystem.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling 85911441Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 86011441Sandreas.hansson@arm.comsystem.cpu.committedInsts 848164321 # Number of Instructions Simulated 86111441Sandreas.hansson@arm.comsystem.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated 86211441Sandreas.hansson@arm.comsystem.cpu.cpi 1.923146 # CPI: Cycles Per Instruction 86311441Sandreas.hansson@arm.comsystem.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads 86411441Sandreas.hansson@arm.comsystem.cpu.ipc 0.519981 # IPC: Instructions Per Cycle 86511441Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads 86611441Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 1223740669 # number of integer regfile reads 86711441Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 731349757 # number of integer regfile writes 86811441Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 1462624 # number of floating regfile reads 86911441Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 780384 # number of floating regfile writes 87011441Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 225040074 # number of cc regfile reads 87111441Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 225673032 # number of cc regfile writes 87211441Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads 87311441Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 26930699 # number of misc regfile writes 87411441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 9706309 # number of replacements 87511353Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use 87611441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. 87711441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks. 87811441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks. 87911201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. 88011353Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor 88111138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy 88211138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy 88310585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88411441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 88511441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id 88611441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 88710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88811441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses 88911441Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses 89011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits 89111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits 89211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits 89311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 128244124 # number of WriteReq hits 89411441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits 89511441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits 89611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits 89711441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits 89811441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516 # number of LoadLockedReq hits 89911441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits 90011441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits 90111441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits 90211441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 275426405 # number of demand (read+write) hits 90311441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 275426405 # number of demand (read+write) hits 90411441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 275804158 # number of overall hits 90511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 275804158 # number of overall hits 90611441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses 90711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses 90811441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses 90911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 11252664 # number of WriteReq misses 91011441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1170750 # number of SoftPFReq misses 91111441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1170750 # number of SoftPFReq misses 91211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1233990 # number of WriteLineReq misses 91311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1233990 # number of WriteLineReq misses 91411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 446459 # number of LoadLockedReq misses 91511441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses 91611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses 91711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses 91811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 20834670 # number of demand (read+write) misses 91911441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 20834670 # number of demand (read+write) misses 92011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 22005420 # number of overall misses 92111441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 22005420 # number of overall misses 92211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles 92311441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles 92411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles 92511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 444283559827 # number of WriteReq miss cycles 92611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52343559973 # number of WriteLineReq miss cycles 92711441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::total 52343559973 # number of WriteLineReq miss cycles 92811441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000 # number of LoadLockedReq miss cycles 92911441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles 93011441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles 93111441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles 93211441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 612836911827 # number of demand (read+write) miss cycles 93311441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 612836911827 # number of demand (read+write) miss cycles 93411441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 612836911827 # number of overall miss cycles 93511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 612836911827 # number of overall miss cycles 93611441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses) 93711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses) 93811441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses) 93911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 139496788 # number of WriteReq accesses(hits+misses) 94011441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 1548503 # number of SoftPFReq accesses(hits+misses) 94111441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 1548503 # number of SoftPFReq accesses(hits+misses) 94211353Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) 94311353Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) 94411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975 # number of LoadLockedReq accesses(hits+misses) 94511441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses) 94611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses) 94711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses) 94811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 296261075 # number of demand (read+write) accesses 94911441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 296261075 # number of demand (read+write) accesses 95011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 297809578 # number of overall (read+write) accesses 95111441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 297809578 # number of overall (read+write) accesses 95211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses 95311441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses 95411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses 95511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.080666 # miss rate for WriteReq accesses 95611441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756053 # miss rate for SoftPFReq accesses 95711441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.756053 # miss rate for SoftPFReq accesses 95811441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792311 # miss rate for WriteLineReq accesses 95911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.792311 # miss rate for WriteLineReq accesses 96011441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311 # miss rate for LoadLockedReq accesses 96111441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses 96211353Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses 96311353Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses 96411441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.070325 # miss rate for demand accesses 96511441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.070325 # miss rate for demand accesses 96611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.073891 # miss rate for overall accesses 96711441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.073891 # miss rate for overall accesses 96811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency 96911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency 97011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency 97111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523 # average WriteReq miss latency 97211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509 # average WriteLineReq miss latency 97311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509 # average WriteLineReq miss latency 97411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553 # average LoadLockedReq miss latency 97511441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency 97611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency 97711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency 97811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547 # average overall miss latency 97911441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 29414.284547 # average overall miss latency 98011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195 # average overall miss latency 98111441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 27849.362195 # average overall miss latency 98211441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked 98310585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 98411441Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked 98510585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 98611441Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked 98710585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 98810585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 98910585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 99011441Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks 99111441Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 7511281 # number of writebacks 99211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits 99311441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 4454269 # number of ReadReq MSHR hits 99411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 9249122 # number of WriteReq MSHR hits 99511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 9249122 # number of WriteReq MSHR hits 99611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130 # number of WriteLineReq MSHR hits 99711441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits 99811441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits 99911441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits 100011441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 13703391 # number of demand (read+write) MSHR hits 100111441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 13703391 # number of demand (read+write) MSHR hits 100211441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 13703391 # number of overall MSHR hits 100311441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 13703391 # number of overall MSHR hits 100411441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses 100511441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses 100611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses 100711441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2003542 # number of WriteReq MSHR misses 100811441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163937 # number of SoftPFReq MSHR misses 100911441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1163937 # number of SoftPFReq MSHR misses 101011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226860 # number of WriteLineReq MSHR misses 101111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::total 1226860 # number of WriteLineReq MSHR misses 101211441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409 # number of LoadLockedReq MSHR misses 101311441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses 101411441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses 101511441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses 101611441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 7131279 # number of demand (read+write) MSHR misses 101711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 7131279 # number of demand (read+write) MSHR misses 101811441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 8295216 # number of overall MSHR misses 101911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 8295216 # number of overall MSHR misses 102011138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 102111138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable 102211138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 102311138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 102411138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 102511138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses 102611441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84965736000 # number of ReadReq MSHR miss cycles 102711441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 84965736000 # number of ReadReq MSHR miss cycles 102811441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77538140437 # number of WriteReq MSHR miss cycles 102911441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 77538140437 # number of WriteReq MSHR miss cycles 103011441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23685156500 # number of SoftPFReq MSHR miss cycles 103111441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23685156500 # number of SoftPFReq MSHR miss cycles 103211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles 103311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50670413473 # number of WriteLineReq MSHR miss cycles 103411441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500 # number of LoadLockedReq MSHR miss cycles 103511441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles 103611441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles 103711441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles 103811441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437 # number of demand (read+write) MSHR miss cycles 103911441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles 104011441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles 104111441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 186189032937 # number of overall MSHR miss cycles 104211441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles 104311441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles 104411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228178464 # number of WriteReq MSHR uncacheable cycles 104511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles 104611441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420200464 # number of overall MSHR uncacheable cycles 104711441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 12420200464 # number of overall MSHR uncacheable cycles 104811441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses 104911441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses 105011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses 105111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014363 # mshr miss rate for WriteReq accesses 105211441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751653 # mshr miss rate for SoftPFReq accesses 105311441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751653 # mshr miss rate for SoftPFReq accesses 105411441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787733 # mshr miss rate for WriteLineReq accesses 105511441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787733 # mshr miss rate for WriteLineReq accesses 105611441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040 # mshr miss rate for LoadLockedReq accesses 105711441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses 105811353Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses 105911353Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses 106011441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses 106111441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses 106211441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027854 # mshr miss rate for overall accesses 106311441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.027854 # mshr miss rate for overall accesses 106411441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency 106511441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency 106611441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency 106711441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency 106811441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency 106911441Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency 107011441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency 107111441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency 107211441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311 # average LoadLockedReq mshr miss latency 107311441Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency 107411441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency 107511441Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency 107611441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency 107711441Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency 107811441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783 # average overall mshr miss latency 107911441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783 # average overall mshr miss latency 108011441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency 108111441Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency 108211441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125 # average WriteReq mshr uncacheable latency 108311441Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency 108411441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395 # average overall mshr uncacheable latency 108511441Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency 108610585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 108711441Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 15141033 # number of replacements 108811441Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use 108911441Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. 109011441Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks. 109111441Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks. 109211441Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. 109311441Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor 109411353Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy 109511353Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy 109610585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 109711441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 109811441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id 109911441Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id 110010585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 110111441Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses 110211441Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 371754919 # Number of data accesses 110311441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits 110411441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits 110511441Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits 110611441Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 340718799 # number of demand (read+write) hits 110711441Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 340718799 # number of overall hits 110811441Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 340718799 # number of overall hits 110911441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 15894345 # number of ReadReq misses 111011441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 15894345 # number of ReadReq misses 111111441Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 15894345 # number of demand (read+write) misses 111211441Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 15894345 # number of demand (read+write) misses 111311441Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 15894345 # number of overall misses 111411441Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 15894345 # number of overall misses 111511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 214960438379 # number of ReadReq miss cycles 111611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 214960438379 # number of ReadReq miss cycles 111711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 214960438379 # number of demand (read+write) miss cycles 111811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 214960438379 # number of demand (read+write) miss cycles 111911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 214960438379 # number of overall miss cycles 112011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 214960438379 # number of overall miss cycles 112111441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 356613144 # number of ReadReq accesses(hits+misses) 112211441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 356613144 # number of ReadReq accesses(hits+misses) 112311441Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 356613144 # number of demand (read+write) accesses 112411441Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 356613144 # number of demand (read+write) accesses 112511441Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 356613144 # number of overall (read+write) accesses 112611441Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 356613144 # number of overall (read+write) accesses 112711441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044570 # miss rate for ReadReq accesses 112811441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.044570 # miss rate for ReadReq accesses 112911441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.044570 # miss rate for demand accesses 113011441Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.044570 # miss rate for demand accesses 113111441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.044570 # miss rate for overall accesses 113211441Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.044570 # miss rate for overall accesses 113311441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13524.334496 # average ReadReq miss latency 113411441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13524.334496 # average ReadReq miss latency 113511441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency 113611441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13524.334496 # average overall miss latency 113711441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency 113811441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13524.334496 # average overall miss latency 113911441Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 23721 # number of cycles access was blocked 114010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 114111441Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1460 # number of cycles access was blocked 114210585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 114311441Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 16.247260 # average number of cycles each access was blocked 114410585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 114510585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 114610585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 114711441Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 15141033 # number of writebacks 114811441Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 15141033 # number of writebacks 114911441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 752570 # number of ReadReq MSHR hits 115011441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 752570 # number of ReadReq MSHR hits 115111441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 752570 # number of demand (read+write) MSHR hits 115211441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 752570 # number of demand (read+write) MSHR hits 115311441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 752570 # number of overall MSHR hits 115411441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 752570 # number of overall MSHR hits 115511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 15141775 # number of ReadReq MSHR misses 115611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 15141775 # number of ReadReq MSHR misses 115711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 15141775 # number of demand (read+write) MSHR misses 115811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 15141775 # number of demand (read+write) MSHR misses 115911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 15141775 # number of overall MSHR misses 116011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 15141775 # number of overall MSHR misses 116111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 116211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable 116311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 116411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses 116511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192682261392 # number of ReadReq MSHR miss cycles 116611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 192682261392 # number of ReadReq MSHR miss cycles 116711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 192682261392 # number of demand (read+write) MSHR miss cycles 116811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 192682261392 # number of demand (read+write) MSHR miss cycles 116911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 192682261392 # number of overall MSHR miss cycles 117011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 192682261392 # number of overall MSHR miss cycles 117111441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938500 # number of ReadReq MSHR uncacheable cycles 117211441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938500 # number of ReadReq MSHR uncacheable cycles 117311441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938500 # number of overall MSHR uncacheable cycles 117411441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 2684938500 # number of overall MSHR uncacheable cycles 117511441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042460 # mshr miss rate for ReadReq accesses 117611441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.042460 # mshr miss rate for ReadReq accesses 117711441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042460 # mshr miss rate for demand accesses 117811441Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.042460 # mshr miss rate for demand accesses 117911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042460 # mshr miss rate for overall accesses 118011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.042460 # mshr miss rate for overall accesses 118111441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12725.209653 # average ReadReq mshr miss latency 118211441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.209653 # average ReadReq mshr miss latency 118311441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency 118411441Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency 118511441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency 118611441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency 118711441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average ReadReq mshr uncacheable latency 118811441Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency 118911441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency 119011441Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency 119110585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 119211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 1146896 # number of replacements 119311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use 119411441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks. 119511441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1209243 # Sample count of references to valid blocks. 119611441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 38.281145 # Average number of references to valid blocks. 119711441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit. 119811441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589 # Average occupied blocks per requestor 119911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 299.826567 # Average occupied blocks per requestor 120011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 486.948403 # Average occupied blocks per requestor 120111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 7815.294504 # Average occupied blocks per requestor 120211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 19533.346332 # Average occupied blocks per requestor 120311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.567731 # Average percentage of cache occupancy 120411441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004575 # Average percentage of cache occupancy 120511441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007430 # Average percentage of cache occupancy 120611441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.119252 # Average percentage of cache occupancy 120711441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.298055 # Average percentage of cache occupancy 120811441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.997043 # Average percentage of cache occupancy 120911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id 121011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62053 # Occupied blocks per task id 121111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 121211441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 293 # Occupied blocks per task id 121311441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 121411353Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 573 # Occupied blocks per task id 121511441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2710 # Occupied blocks per task id 121611441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5168 # Occupied blocks per task id 121711441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 53538 # Occupied blocks per task id 121811441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id 121911441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id 122011441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses 122111441Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses 122211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits 122311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits 122411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits 122511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 7511281 # number of WritebackDirty hits 122611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 7511281 # number of WritebackDirty hits 122711441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 15138290 # number of WritebackClean hits 122811441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 15138290 # number of WritebackClean hits 122911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 9403 # number of UpgradeReq hits 123011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 9403 # number of UpgradeReq hits 123111441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits 123211441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits 123311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1568483 # number of ReadExReq hits 123411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1568483 # number of ReadExReq hits 123511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15058402 # number of ReadCleanReq hits 123611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 15058402 # number of ReadCleanReq hits 123711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 6260466 # number of ReadSharedReq hits 123811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 6260466 # number of ReadSharedReq hits 123911441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 727948 # number of InvalidateReq hits 124011441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 727948 # number of InvalidateReq hits 124111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 776137 # number of demand (read+write) hits 124211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 292808 # number of demand (read+write) hits 124311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 15058402 # number of demand (read+write) hits 124411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 7828949 # number of demand (read+write) hits 124511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 23956296 # number of demand (read+write) hits 124611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 776137 # number of overall hits 124711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 292808 # number of overall hits 124811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 15058402 # number of overall hits 124911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 7828949 # number of overall hits 125011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 23956296 # number of overall hits 125111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3559 # number of ReadReq misses 125211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3383 # number of ReadReq misses 125311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 6942 # number of ReadReq misses 125411441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 34253 # number of UpgradeReq misses 125511441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 34253 # number of UpgradeReq misses 125610726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 125710726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 125811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 394920 # number of ReadExReq misses 125911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 394920 # number of ReadExReq misses 126011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83161 # number of ReadCleanReq misses 126111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 83161 # number of ReadCleanReq misses 126211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 256104 # number of ReadSharedReq misses 126311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 256104 # number of ReadSharedReq misses 126411441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 498912 # number of InvalidateReq misses 126511441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 498912 # number of InvalidateReq misses 126611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 3559 # number of demand (read+write) misses 126711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 3383 # number of demand (read+write) misses 126811441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 83161 # number of demand (read+write) misses 126911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 651024 # number of demand (read+write) misses 127011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 741127 # number of demand (read+write) misses 127111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 3559 # number of overall misses 127211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 3383 # number of overall misses 127311441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 83161 # number of overall misses 127411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 651024 # number of overall misses 127511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 741127 # number of overall misses 127611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 488533500 # number of ReadReq miss cycles 127711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 465355000 # number of ReadReq miss cycles 127811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 953888500 # number of ReadReq miss cycles 127911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1389938500 # number of UpgradeReq miss cycles 128011441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 1389938500 # number of UpgradeReq miss cycles 128110892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 128210892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 128311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55004341000 # number of ReadExReq miss cycles 128411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 55004341000 # number of ReadExReq miss cycles 128511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11217317500 # number of ReadCleanReq miss cycles 128611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 11217317500 # number of ReadCleanReq miss cycles 128711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35747966000 # number of ReadSharedReq miss cycles 128811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 35747966000 # number of ReadSharedReq miss cycles 128911441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 7492000 # number of InvalidateReq miss cycles 129011441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::total 7492000 # number of InvalidateReq miss cycles 129111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 488533500 # number of demand (read+write) miss cycles 129211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 465355000 # number of demand (read+write) miss cycles 129311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11217317500 # number of demand (read+write) miss cycles 129411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 90752307000 # number of demand (read+write) miss cycles 129511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 102923513000 # number of demand (read+write) miss cycles 129611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 488533500 # number of overall miss cycles 129711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 465355000 # number of overall miss cycles 129811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11217317500 # number of overall miss cycles 129911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 90752307000 # number of overall miss cycles 130011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 102923513000 # number of overall miss cycles 130111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 779696 # number of ReadReq accesses(hits+misses) 130211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 296191 # number of ReadReq accesses(hits+misses) 130311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1075887 # number of ReadReq accesses(hits+misses) 130411441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 7511281 # number of WritebackDirty accesses(hits+misses) 130511441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 7511281 # number of WritebackDirty accesses(hits+misses) 130611441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 15138290 # number of WritebackClean accesses(hits+misses) 130711441Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 15138290 # number of WritebackClean accesses(hits+misses) 130811441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 43656 # number of UpgradeReq accesses(hits+misses) 130911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 43656 # number of UpgradeReq accesses(hits+misses) 131011441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) 131111441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) 131211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1963403 # number of ReadExReq accesses(hits+misses) 131311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1963403 # number of ReadExReq accesses(hits+misses) 131411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15141563 # number of ReadCleanReq accesses(hits+misses) 131511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 15141563 # number of ReadCleanReq accesses(hits+misses) 131611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6516570 # number of ReadSharedReq accesses(hits+misses) 131711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 6516570 # number of ReadSharedReq accesses(hits+misses) 131811441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226860 # number of InvalidateReq accesses(hits+misses) 131911441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1226860 # number of InvalidateReq accesses(hits+misses) 132011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 779696 # number of demand (read+write) accesses 132111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 296191 # number of demand (read+write) accesses 132211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 15141563 # number of demand (read+write) accesses 132311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 8479973 # number of demand (read+write) accesses 132411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 24697423 # number of demand (read+write) accesses 132511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 779696 # number of overall (read+write) accesses 132611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 296191 # number of overall (read+write) accesses 132711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 15141563 # number of overall (read+write) accesses 132811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 8479973 # number of overall (read+write) accesses 132911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 24697423 # number of overall (read+write) accesses 133011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004565 # miss rate for ReadReq accesses 133111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.011422 # miss rate for ReadReq accesses 133211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.006452 # miss rate for ReadReq accesses 133311441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784612 # miss rate for UpgradeReq accesses 133411441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.784612 # miss rate for UpgradeReq accesses 133511441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses 133611441Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses 133711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.201141 # miss rate for ReadExReq accesses 133811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.201141 # miss rate for ReadExReq accesses 133911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005492 # miss rate for ReadCleanReq accesses 134011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005492 # miss rate for ReadCleanReq accesses 134111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039300 # miss rate for ReadSharedReq accesses 134211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039300 # miss rate for ReadSharedReq accesses 134311441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.406658 # miss rate for InvalidateReq accesses 134411441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.406658 # miss rate for InvalidateReq accesses 134511441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004565 # miss rate for demand accesses 134611441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.011422 # miss rate for demand accesses 134711441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005492 # miss rate for demand accesses 134811441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.076772 # miss rate for demand accesses 134911441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.030008 # miss rate for demand accesses 135011441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004565 # miss rate for overall accesses 135111441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.011422 # miss rate for overall accesses 135211441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005492 # miss rate for overall accesses 135311441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.076772 # miss rate for overall accesses 135411441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.030008 # miss rate for overall accesses 135511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137267.069402 # average ReadReq miss latency 135611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137556.902158 # average ReadReq miss latency 135711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 137408.311726 # average ReadReq miss latency 135811441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40578.591656 # average UpgradeReq miss latency 135911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40578.591656 # average UpgradeReq miss latency 136010892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency 136110892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency 136211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139279.704750 # average ReadExReq miss latency 136311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 139279.704750 # average ReadExReq miss latency 136411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134886.755811 # average ReadCleanReq miss latency 136511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134886.755811 # average ReadCleanReq miss latency 136611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139583.786274 # average ReadSharedReq miss latency 136711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139583.786274 # average ReadSharedReq miss latency 136811441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 15.016676 # average InvalidateReq miss latency 136911441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::total 15.016676 # average InvalidateReq miss latency 137011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137267.069402 # average overall miss latency 137111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137556.902158 # average overall miss latency 137211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134886.755811 # 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number of cycles access was blocked 138110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 138210585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 138310585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 138410585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 138510585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 138610585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 138710585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 138811441Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 961909 # number of writebacks 138911441Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 961909 # 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number of WriteReq MSHR uncacheable 143211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 143311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 143411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 88668 # number of overall MSHR uncacheable misses 143511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 452886511 # number of ReadReq MSHR miss cycles 143611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 431525000 # number of ReadReq MSHR miss cycles 143711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 884411511 # number of ReadReq MSHR miss cycles 143811441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2329610000 # number of UpgradeReq MSHR miss cycles 143911441Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2329610000 # number of UpgradeReq MSHR miss cycles 144011336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 209000 # number of SCUpgradeReq MSHR miss cycles 144111336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 209000 # number of SCUpgradeReq MSHR miss cycles 144211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 51054116966 # number of ReadExReq MSHR miss cycles 144311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 51054116966 # number of ReadExReq MSHR miss cycles 144411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10385630163 # number of ReadCleanReq MSHR miss cycles 144511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10385630163 # number of ReadCleanReq MSHR miss cycles 144611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33183304813 # number of ReadSharedReq MSHR miss cycles 144711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33183304813 # number of ReadSharedReq MSHR miss cycles 144811441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 34870635000 # number of InvalidateReq MSHR miss cycles 144911441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 34870635000 # number of InvalidateReq MSHR miss cycles 145011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 452886511 # number of demand (read+write) MSHR miss cycles 145111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 431525000 # number of demand (read+write) MSHR miss cycles 145211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10385630163 # number of demand (read+write) MSHR miss cycles 145311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84237421779 # number of demand (read+write) MSHR miss cycles 145411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 95507463453 # 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number of ReadReq MSHR uncacheable cycles 146311441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836145500 # number of WriteReq MSHR uncacheable cycles 146411441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836145500 # number of WriteReq MSHR uncacheable cycles 146511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763500 # number of overall MSHR uncacheable cycles 146611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607041000 # number of overall MSHR uncacheable cycles 146711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025804500 # number of overall MSHR uncacheable cycles 146811441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for ReadReq accesses 146911441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011422 # 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average SCUpgradeReq mshr miss latency 150111336Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency 150211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129277.111734 # average ReadExReq mshr miss latency 150311441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129277.111734 # average ReadExReq mshr miss latency 150411441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124885.825844 # average ReadCleanReq mshr miss latency 150511441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124885.825844 # average ReadCleanReq mshr miss latency 150611441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129580.272072 # average ReadSharedReq mshr miss latency 150711441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129580.272072 # average ReadSharedReq mshr miss latency 150811441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69893.357947 # average InvalidateReq mshr miss latency 150911441Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69893.357947 # average InvalidateReq mshr miss latency 151011441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency 151111441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency 151211441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency 151311441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency 151411441Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency 151511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency 151611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency 151711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency 151811441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency 151911441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency 152011441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency 152111441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency 152211441Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency 152311441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency 152411441Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency 152511441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency 152611441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency 152711441Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency 152810585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 152911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter. 153011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data. 153111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 153211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. 153311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 153411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 153511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution 153611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution 153711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution 153811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution 153911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution 154011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution 154111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution 154211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution 154311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution 154411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 43666 # Transaction distribution 154511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1963403 # Transaction distribution 154611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1963403 # Transaction distribution 154711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 15141775 # Transaction distribution 154811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 6525421 # Transaction distribution 154911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1333524 # Transaction distribution 155011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1226860 # Transaction distribution 155111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45466959 # Packet count per connected master and slave (bytes) 155211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29342845 # Packet count per connected master and slave (bytes) 155311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 722067 # Packet count per connected master and slave (bytes) 155411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1919121 # Packet count per connected master and slave (bytes) 155511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 77450992 # Packet count per connected master and slave (bytes) 155611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1938426848 # Cumulative packet size per connected master and slave (bytes) 155711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023681310 # Cumulative packet size per connected master and slave (bytes) 155811441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2369528 # Cumulative packet size per connected master and slave (bytes) 155911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6237568 # Cumulative packet size per connected master and slave (bytes) 156011441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 2970715254 # Cumulative packet size per connected master and slave (bytes) 156111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 1868325 # Total snoops (count) 156211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 27924144 # Request fanout histogram 156311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.025024 # Request fanout histogram 156411441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.156198 # Request fanout histogram 156510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 156611441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 27225372 97.50% 97.50% # Request fanout histogram 156711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 698772 2.50% 100.00% # Request fanout histogram 156811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 156910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 157011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 157111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 157211441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 27924144 # Request fanout histogram 157311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 48365955497 # Layer occupancy (ticks) 157410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 157511441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1497386 # Layer occupancy (ticks) 157610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 157711441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks) 157810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 157911441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks) 158010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 158111441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks) 158210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 158311441Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks) 158410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 158511441Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40299 # Transaction distribution 158611441Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40299 # Transaction distribution 158710892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 158810892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136571 # Transaction distribution 158910726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 159010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 159111245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 159210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 159310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 159410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 159510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 159610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 159710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 159810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 159910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 160010892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 160110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 160210892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 160311441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) 160411441Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) 160510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 160610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 160711441Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353740 # Packet count per connected master and slave (bytes) 160810726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 160910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 161011245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 161110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 161210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 161310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 161410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 161510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 161610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 161710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 161810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 161910892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 162010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 162110892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 162211441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) 162311441Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) 162410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 162510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 162611441Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7492176 # Cumulative packet size per connected master and slave (bytes) 162711441Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 41885000 # Layer occupancy (ticks) 162810585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 162911353Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 163010585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 163111353Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks) 163210585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 163311201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 163410585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 163511245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 163611245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 163711201Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 163810585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 163911441Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) 164010585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 164111201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 164210585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 164311201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 164410585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 164511441Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) 164610585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 164711201Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 164810585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 164911441Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25104500 # Layer occupancy (ticks) 165010585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 165111441Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 36501000 # Layer occupancy (ticks) 165210585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 165311441Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks) 165410585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 165510892Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 165610585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 165711441Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks) 165810585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 165910892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 166010585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 166111441Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115459 # number of replacements 166211441Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use 166310585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 166411441Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. 166510585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 166611441Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit. 166711441Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor 166811441Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor 166911353Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy 167011353Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy 167111441Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy 167210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 167310585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 167410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 167511441Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1039659 # Number of tag accesses 167611441Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1039659 # Number of data accesses 167710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 167811441Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses 167911441Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8851 # number of ReadReq misses 168010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 168110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 168210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 168310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 168410585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 168511441Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses 168611441Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8854 # number of demand (read+write) misses 168710585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 168811441Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8814 # number of overall misses 168911441Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8854 # number of overall misses 169011441Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles 169111441Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles 169211441Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles 169310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 169410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 169511441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles 169611441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles 169711441Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles 169811441Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles 169911441Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles 170011441Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles 170111441Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles 170211441Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles 170310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 170411441Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) 170511441Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) 170610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 170710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 170810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 170910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 171010585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 171111441Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses 171211441Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses 171310585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 171411441Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses 171511441Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses 171610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 171710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 171810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 171910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 172010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 172110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 172210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 172310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 172410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 172510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 172610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 172710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 172810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 172911441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency 173011441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency 173111441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency 173210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 173310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 173411441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency 173511441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency 173611441Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency 173711441Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency 173811441Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency 173911441Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency 174011441Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency 174111441Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency 174211441Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked 174310585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 174411441Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked 174510585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 174611441Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked 174710585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174810585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 174910585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 175010726Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106630 # number of writebacks 175110726Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106630 # number of writebacks 175210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 175311441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses 175411441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses 175510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 175610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 175710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 175810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 175910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 176011441Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses 176111441Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses 176210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 176311441Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses 176411441Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses 176511441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles 176611441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles 176711441Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles 176810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 176910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 177011441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles 177111441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles 177211441Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles 177311441Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles 177411441Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles 177511441Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles 177611441Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles 177711441Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles 177810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 177910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 178010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 178110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 178210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 178310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 178410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 178510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 178610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 178710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 178810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 178910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 179010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 179111441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency 179211441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency 179311441Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency 179410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 179510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 179611441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency 179711441Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency 179811441Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency 179911441Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency 180011441Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency 180111441Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency 180211441Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency 180311441Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency 180410585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 180511201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 54972 # Transaction distribution 180611441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 410008 # Transaction distribution 180711138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33696 # Transaction distribution 180811138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33696 # Transaction distribution 180911441Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution 181011441Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 192763 # Transaction distribution 181111441Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 34977 # Transaction distribution 181210726Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 181311336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 8 # Transaction distribution 181411441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 394295 # Transaction distribution 181511441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 394295 # Transaction distribution 181611441Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 355036 # Transaction distribution 181711441Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 605480 # Transaction distribution 181810892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 181911201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 182011138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) 182111441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3207653 # Packet count per connected master and slave (bytes) 182211441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3337273 # Packet count per connected master and slave (bytes) 182311441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237899 # Packet count per connected master and slave (bytes) 182411441Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237899 # Packet count per connected master and slave (bytes) 182511441Sandreas.hansson@arm.comsystem.membus.pkt_count::total 3575172 # Packet count per connected master and slave (bytes) 182610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 182711201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) 182811138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) 182911441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109271756 # Cumulative packet size per connected master and slave (bytes) 183011441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 109441726 # Cumulative packet size per connected master and slave (bytes) 183111441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7267328 # Cumulative packet size per connected master and slave (bytes) 183211441Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7267328 # Cumulative packet size per connected master and slave (bytes) 183311441Sandreas.hansson@arm.comsystem.membus.pkt_size::total 116709054 # Cumulative packet size per connected master and slave (bytes) 183411441Sandreas.hansson@arm.comsystem.membus.snoops 2596 # Total snoops (count) 183511441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2739791 # Request fanout histogram 183610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 183710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 183810515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 183910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 184011441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2739791 100.00% 100.00% # Request fanout histogram 184110515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 184210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 184310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 184410515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 184511441Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2739791 # Request fanout histogram 184611441Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks) 184710515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 184811441Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) 184910515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 185011441Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks) 185110515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 185211441Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks) 185310585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 185411441Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks) 185510515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 185611441Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) 185710515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 185811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 185911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 186011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 186111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 186211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 186311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 186410515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 186510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 186610515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 186710515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 186810515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 186910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 187010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 187110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 187210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 187311138Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 187410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 187510515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 187610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 187711138Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 187810515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 187910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 188010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 188110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 188210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 188310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 188410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 188510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 188610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 188710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 188810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 188910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 189010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 189110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 189210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 189310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 189410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 189510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 189610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 189710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 189810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 189910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 190010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 190110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 190210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 190310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 190410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 190510515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 190611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 190711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 190811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 190911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 191010515SAli.Saidi@ARM.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 191111353Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed 191210515SAli.Saidi@ARM.com 191310515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1914