xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.331535                       # Number of seconds simulated
sim_ticks                                51331535316000                       # Number of ticks simulated
final_tick                               51331535316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  99693                       # Simulator instruction rate (inst/s)
host_op_rate                                   117139                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6054269729                       # Simulator tick rate (ticks/s)
host_mem_usage                                 687132                       # Number of bytes of host memory used
host_seconds                                  8478.57                       # Real time elapsed on the host
sim_insts                                   845255961                       # Number of instructions simulated
sim_ops                                     993175006                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       205184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       203136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5579360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          71974536                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        439872                       # Number of bytes read from this memory
system.physmem.bytes_read::total             78402088                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5579360                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5579360                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     67218688                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          67239268                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         3206                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         3174                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             103130                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1124615                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6873                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1240998                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1050292                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1052865                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           3997                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           3957                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               108693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1402150                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8569                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1527367                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          108693                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             108693                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1309501                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1309902                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1309501                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          3997                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          3957                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              108693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1402551                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8569                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2837269                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1240998                       # Number of read requests accepted
system.physmem.writeReqs                      1052865                       # Number of write requests accepted
system.physmem.readBursts                     1240998                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1052865                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 79374080                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     49792                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  67238272                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  78402088                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               67239268                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      778                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         323831                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               73630                       # Per bank write bursts
system.physmem.perBankRdBursts::1               80699                       # Per bank write bursts
system.physmem.perBankRdBursts::2               78276                       # Per bank write bursts
system.physmem.perBankRdBursts::3               74217                       # Per bank write bursts
system.physmem.perBankRdBursts::4               73666                       # Per bank write bursts
system.physmem.perBankRdBursts::5               79970                       # Per bank write bursts
system.physmem.perBankRdBursts::6               75195                       # Per bank write bursts
system.physmem.perBankRdBursts::7               74032                       # Per bank write bursts
system.physmem.perBankRdBursts::8               71713                       # Per bank write bursts
system.physmem.perBankRdBursts::9              100993                       # Per bank write bursts
system.physmem.perBankRdBursts::10              77049                       # Per bank write bursts
system.physmem.perBankRdBursts::11              78387                       # Per bank write bursts
system.physmem.perBankRdBursts::12              77207                       # Per bank write bursts
system.physmem.perBankRdBursts::13              77888                       # Per bank write bursts
system.physmem.perBankRdBursts::14              72930                       # Per bank write bursts
system.physmem.perBankRdBursts::15              74368                       # Per bank write bursts
system.physmem.perBankWrBursts::0               61890                       # Per bank write bursts
system.physmem.perBankWrBursts::1               67926                       # Per bank write bursts
system.physmem.perBankWrBursts::2               67010                       # Per bank write bursts
system.physmem.perBankWrBursts::3               65080                       # Per bank write bursts
system.physmem.perBankWrBursts::4               64889                       # Per bank write bursts
system.physmem.perBankWrBursts::5               68021                       # Per bank write bursts
system.physmem.perBankWrBursts::6               64968                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65143                       # Per bank write bursts
system.physmem.perBankWrBursts::8               62358                       # Per bank write bursts
system.physmem.perBankWrBursts::9               69100                       # Per bank write bursts
system.physmem.perBankWrBursts::10              64674                       # Per bank write bursts
system.physmem.perBankWrBursts::11              67475                       # Per bank write bursts
system.physmem.perBankWrBursts::12              66848                       # Per bank write bursts
system.physmem.perBankWrBursts::13              67005                       # Per bank write bursts
system.physmem.perBankWrBursts::14              63727                       # Per bank write bursts
system.physmem.perBankWrBursts::15              64484                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
system.physmem.totGap                    51331533904500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1219713                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1050292                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    631662                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    326376                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    149637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    126770                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       678                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       576                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       562                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1325                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       777                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       342                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      166                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      165                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      109                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       76                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    11849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    13848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    31106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    44112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    54434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    62830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    64146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    65206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    66402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    65786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    66222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    71472                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    66143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    80247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    84167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    64432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    68381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    61265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      801                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      540                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       67                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       475699                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      308.203229                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     177.287854                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     336.241632                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         186276     39.16%     39.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       111535     23.45%     62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        45072      9.47%     72.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        23389      4.92%     77.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18072      3.80%     80.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11535      2.42%     83.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        10579      2.22%     85.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         8108      1.70%     87.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        61133     12.85%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         475699                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         59810                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.735663                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      269.812069                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          59807     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           59810                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         59810                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.565591                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.987331                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.225331                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           56970     95.25%     95.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             839      1.40%     96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              56      0.09%     96.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             337      0.56%     97.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              42      0.07%     97.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             348      0.58%     97.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             200      0.33%     98.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              22      0.04%     98.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              64      0.11%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             127      0.21%     98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              27      0.05%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              38      0.06%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             506      0.85%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              29      0.05%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              24      0.04%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             125      0.21%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            25      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           59810                       # Writes before turning the bus around for reads
system.physmem.totQLat                    31819415784                       # Total ticks spent queuing
system.physmem.totMemAccLat               55073540784                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6201100000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25656.27                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44406.27                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.55                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.31                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.53                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.31                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.21                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1019502                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    795615                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.20                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.73                       # Row buffer hit rate for writes
system.physmem.avgGap                     22377767.94                       # Average gap between requests
system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1796611320                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  980293875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4755496200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3401526960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1234173509595                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29716310123250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34314143605920                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.480817                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49435613390416                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1714072620000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    181848672584                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1799673120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  981964500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4918173000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3406348080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1238619690855                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29712409964250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34314861858525                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.494809                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49429083175074                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1714072620000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    188374993676                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               223536271                       # Number of BP lookups
system.cpu.branchPred.condPredicted         149385948                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12169974                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            157736918                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               103109650                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             65.368115                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                30707782                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             342742                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    935593                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                935593                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15313                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154778                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore       425408                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       510185                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean  2222.203710                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 14681.416911                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535       506821     99.34%     99.34% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071         1912      0.37%     99.72% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607          970      0.19%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143          202      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679          151      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215           19      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751           50      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287           49      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::524288-589823            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       510185                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       473757                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23106.578900                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 18127.358359                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 20599.365275                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       462892     97.71%     97.71% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         7688      1.62%     99.33% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607         2250      0.47%     99.80% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          174      0.04%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679          494      0.10%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           87      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751          117      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287           41      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       473757                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 784064516876                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     0.722483                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev     0.520538                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1  781865994376     99.72%     99.72% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3    1176082000      0.15%     99.87% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5     477234000      0.06%     99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7     199500000      0.03%     99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9     146109500      0.02%     99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11    120981500      0.02%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13     26256500      0.00%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15     49725000      0.01%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17      2626500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::18-19         7500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 784064516876                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        154779     91.00%     91.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         15313      9.00%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       170092                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       935593                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       935593                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       170092                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       170092                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total      1105685                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    168870430                       # DTB read hits
system.cpu.dtb.read_misses                     669785                       # DTB read misses
system.cpu.dtb.write_hits                   146966916                       # DTB write hits
system.cpu.dtb.write_misses                    265808                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               39148                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    71844                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                        98                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   9429                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     69613                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                169540215                       # DTB read accesses
system.cpu.dtb.write_accesses               147232724                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         315837346                       # DTB hits
system.cpu.dtb.misses                          935593                       # DTB misses
system.cpu.dtb.accesses                     316772939                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    161130                       # Table walker walks requested
system.cpu.itb.walker.walksLong                161130                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1443                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       121427                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore        17608                       # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples       143522                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean  1275.602347                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev  9467.048086                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767       142512     99.30%     99.30% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535          586      0.41%     99.70% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303           51      0.04%     99.74% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071           83      0.06%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839          223      0.16%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607           32      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       143522                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       140478                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 29089.590541                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24285.230021                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 22670.988579                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       137385     97.80%     97.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071          891      0.63%     98.43% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607         1925      1.37%     99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           93      0.07%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679          119      0.08%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751           23      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       140478                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 668097269884                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean     0.944108                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev     0.230056                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0     37393446856      5.60%      5.60% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1    630652469528     94.40%     99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2        50695000      0.01%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3          657500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4            1000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 668097269884                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        121427     98.83%     98.83% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1443      1.17%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       122870                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161130                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       161130                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122870                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       122870                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       284000                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    355391745                       # ITB inst hits
system.cpu.itb.inst_misses                     161130                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               39148                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    52871                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    369048                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                355552875                       # ITB inst accesses
system.cpu.itb.hits                         355391745                       # DTB hits
system.cpu.itb.misses                          161130                       # DTB misses
system.cpu.itb.accesses                     355552875                       # DTB accesses
system.cpu.numCycles                       1639149006                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          642133876                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      997446842                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   223536271                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          133817432                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     910640256                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                25987402                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                    3814067                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                27748                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles       9296817                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      1023598                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          983                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 355005878                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               6082209                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                   48751                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples         1579931046                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.739715                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.145918                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0               1024858413     64.87%     64.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                213048750     13.48%     78.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 70422001      4.46%     82.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                271601882     17.19%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1579931046                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.136373                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.608515                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                522505611                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             567007663                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 431520293                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              49702709                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                9194770                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             33525771                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred               3859042                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1080875290                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              28941730                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                9194770                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                566963257                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                68325752                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles      370117398                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 436739828                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             128590041                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1061188804                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               6761282                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               5074872                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 331009                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 667465                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               77645177                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            20261                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1009236679                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1634390089                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1255037462                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1470821                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             943893813                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 65342863                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts           26761446                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts       23109655                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 101993436                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            172887729                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           150512713                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           9835963                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          8956761                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1026341207                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded            27052915                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1041697414                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3264017                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        60219112                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33542548                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         311458                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1579931046                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.659331                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.917837                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           935073091     59.18%     59.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           332737212     21.06%     80.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           233873919     14.80%     95.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            71794095      4.54%     99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6433566      0.41%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               19163      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1579931046                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                57548727     35.04%     35.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 100099      0.06%     35.10% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                   26751      0.02%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              757      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44132085     26.87%     62.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              62410380     38.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             717342377     68.86%     68.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2532202      0.24%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                122567      0.01%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   8      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         121087      0.01%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            172736633     16.58%     85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           148842483     14.29%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1041697414                       # Type of FU issued
system.cpu.iq.rate                           0.635511                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   164218799                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.157645                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3828331710                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1112806179                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1023834597                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             2476979                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             946356                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       909820                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1204359624                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1556578                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          4281868                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     13732493                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14369                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       140572                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      6281305                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2514322                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1544139                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                9194770                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 6870613                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               9053250                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1053615244                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             172887729                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            150512713                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts           22684457                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  56400                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8925068                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         140572                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3644333                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      5090402                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8734735                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1030574997                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             168857481                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10197714                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        221122                       # number of nop insts executed
system.cpu.iew.exec_refs                    315819616                       # number of memory reference insts executed
system.cpu.iew.exec_branches                195518777                       # Number of branches executed
system.cpu.iew.exec_stores                  146962135                       # Number of stores executed
system.cpu.iew.exec_rate                     0.628726                       # Inst execution rate
system.cpu.iew.wb_sent                     1025549780                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1024744417                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 436186320                       # num instructions producing a value
system.cpu.iew.wb_consumers                 705504935                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.625169                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.618261                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        51156578                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls        26741457                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           8371043                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1568002280                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.633402                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.269603                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0   1058124948     67.48%     67.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    286691231     18.28%     85.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    120053535      7.66%     93.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     36420041      2.32%     95.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     28336916      1.81%     97.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     13959603      0.89%     98.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8598360      0.55%     98.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4160425      0.27%     99.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     11657221      0.74%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1568002280                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            845255961                       # Number of instructions committed
system.cpu.commit.committedOps              993175006                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      303386643                       # Number of memory references committed
system.cpu.commit.loads                     159155235                       # Number of loads committed
system.cpu.commit.membars                     6901293                       # Number of memory barriers committed
system.cpu.commit.branches                  188640484                       # Number of branches committed
system.cpu.commit.fp_insts                     896738                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 912506063                       # Number of committed integer instructions.
system.cpu.commit.function_calls             25186659                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        687431731     69.22%     69.22% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2146648      0.22%     69.43% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv            97945      0.01%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       111997      0.01%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       159155235     16.02%     85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      144231408     14.52%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         993175006                       # Class of committed instruction
system.cpu.commit.bw_lim_events              11657221                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   2593153041                       # The number of ROB reads
system.cpu.rob.rob_writes                  2100498051                       # The number of ROB writes
system.cpu.timesIdled                         8123602                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        59217960                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                 101023921760                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   845255961                       # Number of Instructions Simulated
system.cpu.committedOps                     993175006                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.939234                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.939234                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.515668                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.515668                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1219925781                       # number of integer regfile reads
system.cpu.int_regfile_writes               728690424                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   1462315                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   782072                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 224390859                       # number of cc regfile reads
system.cpu.cc_regfile_writes                225039549                       # number of cc regfile writes
system.cpu.misc_regfile_reads              2563491272                       # number of misc regfile reads
system.cpu.misc_regfile_writes               26777143                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           9646522                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.972803                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           282175483                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9647034                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.249973                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.972803                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1232341715                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1232341715                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    146679057                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       146679057                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    127793945                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      127793945                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       377283                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        377283                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       324111                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       324111                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3281173                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3281173                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3676011                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3676011                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     274473002                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        274473002                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    274850285                       # number of overall hits
system.cpu.dcache.overall_hits::total       274850285                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9506685                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9506685                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data     11193954                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total     11193954                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1163770                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1163770                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1231562                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1231562                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       446112                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       446112                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     20700639                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       20700639                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     21864409                       # number of overall misses
system.cpu.dcache.overall_misses::total      21864409                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 165615263000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 165615263000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 435458645679                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 435458645679                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89047451888                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  89047451888                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6832433500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   6832433500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       275500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       275500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 601073908679                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 601073908679                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 601073908679                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 601073908679                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    156185742                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    156185742                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    138987899                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    138987899                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1541053                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1541053                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555673                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1555673                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3727285                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3727285                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3676016                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3676016                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    295173641                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    295173641                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    296714694                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    296714694                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060868                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.060868                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080539                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.080539                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755178                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.755178                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791659                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.791659                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119688                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119688                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.070130                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.070130                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.073688                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.073688                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17420.926748                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17420.926748                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38901.235942                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38901.235942                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72304.481535                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72304.481535                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15315.511576                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15315.511576                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55100                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55100                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29036.490549                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29036.490549                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27490.974427                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27490.974427                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     49516087                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1592102                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.101077                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      7469877                       # number of writebacks
system.cpu.dcache.writebacks::total           7469877                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4421127                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4421127                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9198347                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      9198347                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6981                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total         6981                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218536                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total       218536                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data     13619474                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total     13619474                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data     13619474                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total     13619474                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5085558                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5085558                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1995607                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1995607                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1156964                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1156964                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224581                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1224581                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227576                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       227576                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7081165                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7081165                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      8238129                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      8238129                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  83741631500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  83741631500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76263176167                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  76263176167                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22882989500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22882989500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87447550388                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87447550388                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3189935000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3189935000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       270500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       270500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160004807667                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 160004807667                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182887797167                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 182887797167                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192854000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192854000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228264964                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228264964                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12421118964                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  12421118964                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032561                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032561                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014358                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014358                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.750762                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.750762                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787171                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787171                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061057                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061057                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023990                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.023990                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027764                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.027764                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16466.557160                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16466.557160                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38215.528492                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38215.528492                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19778.480143                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19778.480143                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71410.180615                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71410.180615                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14017.009702                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14017.009702                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54100                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54100                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22595.831006                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22595.831006                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22200.161853                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22200.161853                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183884.256785                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183884.256785                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184836.923196                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184836.923196                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184360.717250                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184360.717250                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          14982836                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.916862                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           339236129                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          14983348                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             22.640876                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       24730722500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.916862                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999838                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999838                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         369968151                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        369968151                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    339236129                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       339236129                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     339236129                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        339236129                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    339236129                       # number of overall hits
system.cpu.icache.overall_hits::total       339236129                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     15748452                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      15748452                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     15748452                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       15748452                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     15748452                       # number of overall misses
system.cpu.icache.overall_misses::total      15748452                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 212811738878                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 212811738878                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 212811738878                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 212811738878                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 212811738878                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 212811738878                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    354984581                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    354984581                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    354984581                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    354984581                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    354984581                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    354984581                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044364                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.044364                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.044364                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.044364                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.044364                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.044364                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13513.184590                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13513.184590                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13513.184590                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13513.184590                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        22549                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              1395                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    16.164158                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks     14982836                       # number of writebacks
system.cpu.icache.writebacks::total          14982836                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst       764882                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total       764882                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst       764882                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total       764882                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst       764882                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total       764882                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     14983570                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     14983570                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     14983570                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     14983570                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     14983570                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     14983570                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190589950887                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 190589950887                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190589950887                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 190589950887                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190589950887                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 190589950887                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042209                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.042209                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.042209                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12719.929288                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1120546                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65234.831512                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           45882504                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1182138                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            38.813154                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      22908442500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37014.981518                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   292.089334                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   422.524862                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8026.847283                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19478.388514                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.564804                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004457                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006447                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122480                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.297217                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995405                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          295                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        61297                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          295                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2697                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5154                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52826                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004501                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.935318                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        407493288                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       407493288                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       779225                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       298670                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1077895                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      7469877                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      7469877                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     14980289                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     14980289                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         9372                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         9372                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1568886                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1568886                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14901485                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     14901485                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6220691                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6220691                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       731394                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       731394                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       779225                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       298670                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     14901485                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7789577                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        23768957                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       779225                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       298670                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     14901485                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7789577                       # number of overall hits
system.cpu.l2cache.overall_hits::total       23768957                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3206                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3174                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         6380                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        33876                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        33876                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       386656                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       386656                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        81874                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        81874                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       246229                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       246229                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       493187                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       493187                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         3206                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         3174                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        81874                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       632885                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        721139                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         3206                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         3174                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        81874                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       632885                       # number of overall misses
system.cpu.l2cache.overall_misses::total       721139                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    444507000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    436877000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    881384000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1421351500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total   1421351500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  53670750500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  53670750500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11020841000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  11020841000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  34201430000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  34201430000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  76472888000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total  76472888000                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    444507000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    436877000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11020841000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  87872180500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  99774405500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    444507000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    436877000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11020841000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  87872180500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  99774405500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       782431                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       301844                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1084275                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      7469877                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      7469877                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     14980289                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     14980289                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43248                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        43248                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1955542                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1955542                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14983359                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     14983359                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6466920                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      6466920                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224581                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1224581                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       782431                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       301844                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     14983359                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8422462                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     24490096                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       782431                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       301844                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     14983359                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8422462                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     24490096                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010515                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.005884                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783296                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783296                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.197723                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.197723                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005464                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005464                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038075                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038075                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.402739                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402739                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010515                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005464                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.075143                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.029446                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010515                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005464                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.075143                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.029446                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137642.407057                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 138147.962382                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41957.477270                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41957.477270                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138807.494258                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138807.494258                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134607.335662                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134607.335662                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138900.901194                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138900.901194                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155058.604546                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155058.604546                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 138356.690596                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 138356.690596                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       943662                       # number of writebacks
system.cpu.l2cache.writebacks::total           943662                       # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           19                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           19                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           19                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3206                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3174                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         6380                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33876                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        33876                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       386656                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       386656                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        81874                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        81874                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       246210                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       246210                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       493187                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       493187                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3206                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3174                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        81874                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       632866                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       721120                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3206                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3174                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        81874                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       632866                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       721120                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    405137000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    817584000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2397445500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2397445500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49804190500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49804190500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10202101000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10202101000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31736616500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31736616500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71541018000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71541018000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    405137000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10202101000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81540807000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  92560492000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    405137000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10202101000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  81540807000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  92560492000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5771724000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8190487000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836234500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836234500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607958500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14026721500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005884                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783296                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783296                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.197723                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.197723                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005464                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038072                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038072                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402739                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402739                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.029445                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.029445                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128147.962382                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70771.209706                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70771.209706                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128807.494258                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128807.494258                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124607.335662                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128900.599082                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128900.599082                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145058.604546                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145058.604546                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171379.654374                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148993.796842                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173202.590812                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173202.590812                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172291.366106                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158193.728290                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     49994853                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     25364266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3498                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2149                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2149                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq        1617841                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      23069110                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      8520195                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     14980289                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2361594                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        43251                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        43256                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1955542                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1955542                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     14983570                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      6475758                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1331245                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1224581                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     44989806                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29161893                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729252                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917892                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          76798843                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1918014176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017349854                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2414752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6259448                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2944038230                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1831110                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     27676926                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.025201                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.156737                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           26979426     97.48%     97.48% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             697500      2.52%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       27676926                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    47946942997                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1474889                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   22505485675                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13321051501                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     427763271                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1135810761                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40286                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40286                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230930                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230930                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353714                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492072                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             41870500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25173000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              168500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            36497500                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              129000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           565751099                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               44500                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147690000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115446                       # number of replacements
system.iocache.tags.tagsinuse               10.422238                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115462                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13103145499000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.543896                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.878342                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221494                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.429896                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651390                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039542                       # Number of tag accesses
system.iocache.tags.data_accesses             1039542                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8801                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8838                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8801                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8841                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8801                       # number of overall misses
system.iocache.overall_misses::total             8841                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1693888006                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1698957506                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13866022593                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13866022593                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1693888006                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1699308506                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1693888006                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1699308506                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8801                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8838                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8801                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8841                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8801                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8841                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 192465.402341                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 192233.254809                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129997.211740                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129997.211740                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 192207.726049                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 192207.726049                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         36226                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3621                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.004419                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8801                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8838                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8801                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8841                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8801                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8841                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1253838006                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1257057506                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8532822593                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8532822593                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1253838006                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1257258506                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1253838006                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1257258506                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142465.402341                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 142233.254809                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79997.211740                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79997.211740                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
system.membus.trans_dist::ReadResp             398274                       # Transaction distribution
system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1050292                       # Transaction distribution
system.membus.trans_dist::CleanEvict           182485                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            34687                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           34690                       # Transaction distribution
system.membus.trans_dist::ReadExReq            879035                       # Transaction distribution
system.membus.trans_dist::ReadExResp           879035                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        343302                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3662907                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3792527                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342336                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342336                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4134863                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138377164                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    138547134                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7264192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               145811326                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2632                       # Total snoops (count)
system.membus.snoop_fanout::samples           2687314                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2687314    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2687314                       # Request fanout histogram
system.membus.reqLayer0.occupancy           103976500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5452000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7124848125                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6613283400                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          227684837                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16105                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------