stats.txt revision 11138
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311138Sandreas.hansson@arm.comsim_seconds 51.291801 # Number of seconds simulated 411138Sandreas.hansson@arm.comsim_ticks 51291801227000 # Number of ticks simulated 511138Sandreas.hansson@arm.comfinal_tick 51291801227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711138Sandreas.hansson@arm.comhost_inst_rate 104106 # Simulator instruction rate (inst/s) 811138Sandreas.hansson@arm.comhost_op_rate 122333 # Simulator op (including micro ops) rate (op/s) 911138Sandreas.hansson@arm.comhost_tick_rate 6261768882 # Simulator tick rate (ticks/s) 1011138Sandreas.hansson@arm.comhost_mem_usage 729608 # Number of bytes of host memory used 1111138Sandreas.hansson@arm.comhost_seconds 8191.26 # Real time elapsed on the host 1211138Sandreas.hansson@arm.comsim_insts 852762944 # Number of instructions simulated 1311138Sandreas.hansson@arm.comsim_ops 1002063356 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 238464 # Number of bytes read from this memory 1711138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 234560 # Number of bytes read from this memory 1811138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 5768352 # Number of bytes read from this memory 1911138Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 75242504 # Number of bytes read from this memory 2011138Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 407680 # Number of bytes read from this memory 2111138Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 81891560 # Number of bytes read from this memory 2211138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 5768352 # Number of instructions bytes read from this memory 2311138Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5768352 # Number of instructions bytes read from this memory 2411138Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 69965824 # Number of bytes written to this memory 2510585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2611138Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 69986404 # Number of bytes written to this memory 2711138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 3726 # Number of read requests responded to by this memory 2811138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 3665 # Number of read requests responded to by this memory 2911138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 106083 # Number of read requests responded to by this memory 3011138Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1175677 # Number of read requests responded to by this memory 3111138Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6370 # Number of read requests responded to by this memory 3211138Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1295521 # Number of read requests responded to by this memory 3311138Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1093216 # Number of write requests responded to by this memory 3410585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3511138Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1095789 # Number of write requests responded to by this memory 3611138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 4649 # Total read bandwidth from this memory (bytes/s) 3711138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s) 3811138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 112461 # Total read bandwidth from this memory (bytes/s) 3911138Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 1466950 # Total read bandwidth from this memory (bytes/s) 4011138Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 7948 # Total read bandwidth from this memory (bytes/s) 4111138Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1596582 # Total read bandwidth from this memory (bytes/s) 4211138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 112461 # Instruction read bandwidth from this memory (bytes/s) 4311138Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 112461 # Instruction read bandwidth from this memory (bytes/s) 4411138Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1364074 # Write bandwidth from this memory (bytes/s) 4511138Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) 4611138Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1364475 # Write bandwidth from this memory (bytes/s) 4711138Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1364074 # Total bandwidth to/from this memory (bytes/s) 4811138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 4649 # Total bandwidth to/from this memory (bytes/s) 4911138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s) 5011138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 112461 # Total bandwidth to/from this memory (bytes/s) 5111138Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 1467351 # Total bandwidth to/from this memory (bytes/s) 5211138Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 7948 # Total bandwidth to/from this memory (bytes/s) 5311138Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2961057 # Total bandwidth to/from this memory (bytes/s) 5411138Sandreas.hansson@arm.comsystem.physmem.readReqs 1295521 # Number of read requests accepted 5511138Sandreas.hansson@arm.comsystem.physmem.writeReqs 1095789 # Number of write requests accepted 5611138Sandreas.hansson@arm.comsystem.physmem.readBursts 1295521 # Number of DRAM read bursts, including those serviced by the write queue 5711138Sandreas.hansson@arm.comsystem.physmem.writeBursts 1095789 # Number of DRAM write bursts, including those merged in the write queue 5811138Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 82863680 # Total number of bytes read from DRAM 5911138Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue 6011138Sandreas.hansson@arm.comsystem.physmem.bytesWritten 69985152 # Total number of bytes written to DRAM 6111138Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 81891560 # Total read bytes from the system interface side 6211138Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 69986404 # Total written bytes from the system interface side 6311138Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue 6411138Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 6511138Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 141837 # Number of requests that are neither read nor write 6611138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 78118 # Per bank write bursts 6711138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 81473 # Per bank write bursts 6811138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 82762 # Per bank write bursts 6911138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 80112 # Per bank write bursts 7011138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 77452 # Per bank write bursts 7111138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 84131 # Per bank write bursts 7211138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 77443 # Per bank write bursts 7311138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 77113 # Per bank write bursts 7411138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 74240 # Per bank write bursts 7511138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 104872 # Per bank write bursts 7611138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 79788 # Per bank write bursts 7711138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 80502 # Per bank write bursts 7811138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 82162 # Per bank write bursts 7911138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 82091 # Per bank write bursts 8011138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 76266 # Per bank write bursts 8111138Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 76220 # Per bank write bursts 8211138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 65460 # Per bank write bursts 8311138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 68510 # Per bank write bursts 8411138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 70351 # Per bank write bursts 8511138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 69772 # Per bank write bursts 8611138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 67735 # Per bank write bursts 8711138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 71090 # Per bank write bursts 8811138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 66311 # Per bank write bursts 8911138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 67773 # Per bank write bursts 9011138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 64800 # Per bank write bursts 9111138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 72411 # Per bank write bursts 9211138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 67462 # Per bank write bursts 9311138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 69064 # Per bank write bursts 9411138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 70238 # Per bank write bursts 9511138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 69848 # Per bank write bursts 9611138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 66451 # Per bank write bursts 9711138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 66242 # Per bank write bursts 9810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911138Sandreas.hansson@arm.comsystem.physmem.numWrRetry 28 # Number of times write queue was full causing retry 10011138Sandreas.hansson@arm.comsystem.physmem.totGap 51291799925500 # Total gap between requests 10110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 21272 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711138Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1274236 # Read request sizes (log2) 10810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411138Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1093216 # Write request sizes (log2) 11511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 662611 # What read queue length does an incoming req see 11611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 344322 # What read queue length does an incoming req see 11711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 153233 # What read queue length does an incoming req see 11811138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 129247 # What read queue length does an incoming req see 11911138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 652 # What read queue length does an incoming req see 12011138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see 12111138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 521 # What read queue length does an incoming req see 12211138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1152 # What read queue length does an incoming req see 12311138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 692 # What read queue length does an incoming req see 12411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 296 # What read queue length does an incoming req see 12511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see 12611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 199 # What read queue length does an incoming req see 12711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see 12811138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see 12911103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see 13011138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 121 # What read queue length does an incoming req see 13111138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see 13211138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see 13311138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see 13411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see 13511138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 13611138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 13711138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 13811138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 12367 # What write queue length does an incoming req see 16311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 14347 # What write queue length does an incoming req see 16411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 32552 # What write queue length does an incoming req see 16511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 46525 # What write queue length does an incoming req see 16611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 57756 # What write queue length does an incoming req see 16711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 65687 # What write queue length does an incoming req see 16811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 66815 # What write queue length does an incoming req see 16911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 67209 # What write queue length does an incoming req see 17011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 69682 # What write queue length does an incoming req see 17111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 68432 # What write queue length does an incoming req see 17211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 68922 # What write queue length does an incoming req see 17311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 74044 # What write queue length does an incoming req see 17411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 68990 # What write queue length does an incoming req see 17511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 82128 # What write queue length does an incoming req see 17611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 86951 # What write queue length does an incoming req see 17711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 67526 # What write queue length does an incoming req see 17811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 71071 # What write queue length does an incoming req see 17911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 63869 # What write queue length does an incoming req see 18011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1402 # What write queue length does an incoming req see 18111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 849 # What write queue length does an incoming req see 18211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 538 # What write queue length does an incoming req see 18311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see 18411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see 18511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 378 # What write queue length does an incoming req see 18611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 313 # What write queue length does an incoming req see 18711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 247 # What write queue length does an incoming req see 18811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 253 # What write queue length does an incoming req see 18911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see 19011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 259 # What write queue length does an incoming req see 19111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see 19211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see 19311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see 19411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 244 # What write queue length does an incoming req see 19511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 248 # What write queue length does an incoming req see 19611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 262 # What write queue length does an incoming req see 19711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 174 # What write queue length does an incoming req see 19811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see 19911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 194 # What write queue length does an incoming req see 20011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see 20111138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see 20211138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see 20311138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see 20411138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see 20511138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see 20611138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 75 # What write queue length does an incoming req see 20711138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 73 # What write queue length does an incoming req see 20811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see 20911138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 66 # What write queue length does an incoming req see 21011138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see 21111138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 505036 # Bytes accessed per row activation 21211138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 302.648619 # Bytes accessed per row activation 21311138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 174.485841 # Bytes accessed per row activation 21411138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 332.471265 # Bytes accessed per row activation 21511138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 200174 39.64% 39.64% # Bytes accessed per row activation 21611138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 119366 23.64% 63.27% # Bytes accessed per row activation 21711138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 47641 9.43% 72.70% # Bytes accessed per row activation 21811138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 24555 4.86% 77.57% # Bytes accessed per row activation 21911138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 19234 3.81% 81.37% # Bytes accessed per row activation 22011138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 12076 2.39% 83.77% # Bytes accessed per row activation 22111138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 11328 2.24% 86.01% # Bytes accessed per row activation 22211138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 8283 1.64% 87.65% # Bytes accessed per row activation 22311138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 62379 12.35% 100.00% # Bytes accessed per row activation 22411138Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 505036 # Bytes accessed per row activation 22511138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 62413 # Reads before turning the bus around for writes 22611138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 20.744284 # Reads before turning the bus around for writes 22711138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 264.086390 # Reads before turning the bus around for writes 22811138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-2047 62410 100.00% 100.00% # Reads before turning the bus around for writes 22910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 23010892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes 23110892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes 23211138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 62413 # Reads before turning the bus around for writes 23311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 62413 # Writes before turning the bus around for reads 23411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.520677 # Writes before turning the bus around for reads 23511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.965036 # Writes before turning the bus around for reads 23611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 7.067360 # Writes before turning the bus around for reads 23711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 59523 95.37% 95.37% # Writes before turning the bus around for reads 23811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 900 1.44% 96.81% # Writes before turning the bus around for reads 23911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 59 0.09% 96.91% # Writes before turning the bus around for reads 24011138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 320 0.51% 97.42% # Writes before turning the bus around for reads 24111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 34 0.05% 97.47% # Writes before turning the bus around for reads 24211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 343 0.55% 98.02% # Writes before turning the bus around for reads 24311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 222 0.36% 98.38% # Writes before turning the bus around for reads 24411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 19 0.03% 98.41% # Writes before turning the bus around for reads 24511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 51 0.08% 98.49% # Writes before turning the bus around for reads 24611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 131 0.21% 98.70% # Writes before turning the bus around for reads 24711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 29 0.05% 98.75% # Writes before turning the bus around for reads 24811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 40 0.06% 98.81% # Writes before turning the bus around for reads 24911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 504 0.81% 99.62% # Writes before turning the bus around for reads 25011138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 37 0.06% 99.68% # Writes before turning the bus around for reads 25111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 23 0.04% 99.71% # Writes before turning the bus around for reads 25211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 123 0.20% 99.91% # Writes before turning the bus around for reads 25311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 5 0.01% 99.92% # Writes before turning the bus around for reads 25411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 4 0.01% 99.93% # Writes before turning the bus around for reads 25511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads 25611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 25711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads 25811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads 25911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads 26011138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads 26111138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads 26211138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads 26311138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 24 0.04% 99.98% # Writes before turning the bus around for reads 26411138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 3 0.00% 99.99% # Writes before turning the bus around for reads 26511138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads 26611138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads 26711138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads 26811138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads 26911138Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 62413 # Writes before turning the bus around for reads 27011138Sandreas.hansson@arm.comsystem.physmem.totQLat 33295532684 # Total ticks spent queuing 27111138Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 57572001434 # Total ticks spent from burst creation until serviced by the DRAM 27211138Sandreas.hansson@arm.comsystem.physmem.totBusLat 6473725000 # Total ticks spent in databus transfers 27311138Sandreas.hansson@arm.comsystem.physmem.avgQLat 25715.90 # Average queueing delay per DRAM burst 27410515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27511138Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 44465.90 # Average memory access latency per DRAM burst 27611138Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s 27711138Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s 27811138Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.60 # Average system read bandwidth in MiByte/s 27911138Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.36 # Average system write bandwidth in MiByte/s 28010515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28111138Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 28211138Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 28311138Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 28411138Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 28511138Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing 28611138Sandreas.hansson@arm.comsystem.physmem.readRowHits 1061078 # Number of row buffer hits during reads 28711138Sandreas.hansson@arm.comsystem.physmem.writeRowHits 822147 # Number of row buffer hits during writes 28811138Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads 28911138Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 75.18 # Row buffer hit rate for writes 29011138Sandreas.hansson@arm.comsystem.physmem.avgGap 21449247.45 # Average gap between requests 29111138Sandreas.hansson@arm.comsystem.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined 29211138Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 1917609120 # Energy for activate commands per rank (pJ) 29311138Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1046314500 # Energy for precharge commands per rank (pJ) 29411138Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4981072200 # Energy for read commands per rank (pJ) 29511138Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3544572960 # Energy for write commands per rank (pJ) 29611138Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) 29711138Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1242137154015 # Energy for active background per rank (pJ) 29811138Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 29685484530000 # Energy for precharge background per rank (pJ) 29911138Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 34289242115835 # Total energy per rank (pJ) 30011138Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.513169 # Core power per rank (mW) 30111138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 49384250074028 # Time in different power states 30211138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1712745840000 # Time in different power states 30310628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30411138Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 194804679972 # Time in different power states 30510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30611138Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 1900463040 # Energy for activate commands per rank (pJ) 30711138Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1036959000 # Energy for precharge commands per rank (pJ) 30811138Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 5117892000 # Energy for read commands per rank (pJ) 30911138Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3541423680 # Energy for write commands per rank (pJ) 31011138Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) 31111138Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1242496599435 # Energy for active background per rank (pJ) 31211138Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 29685169227000 # Energy for precharge background per rank (pJ) 31311138Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 34289393427195 # Total energy per rank (pJ) 31411138Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.516119 # Core power per rank (mW) 31511138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 49383714226365 # Time in different power states 31611138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1712745840000 # Time in different power states 31710628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 31811138Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 195340926635 # Time in different power states 31910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 32010585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory 32110585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 32210585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory 32310585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory 32410585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory 32510585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory 32610585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 32710585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory 32810585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 32910585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 33011138Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 33110585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 33210585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 33310585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 33410585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 33511138Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) 33610585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 33710585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 33810585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 33910585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 34010585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 34110585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 34211138Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 225483777 # Number of BP lookups 34311138Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 150731207 # Number of conditional branches predicted 34411138Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 12226483 # Number of conditional branches incorrect 34511138Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 159238670 # Number of BTB lookups 34611138Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 104065621 # Number of BTB hits 34710585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 34811138Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 65.351978 # BTB Hit Percentage 34911138Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 30986634 # Number of times the RAS was used to get a target. 35011138Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 344493 # Number of incorrect RAS predictions. 35110585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 35210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 37810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 37910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 38010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38111138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 951545 # Table walker walks requested 38211138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 951545 # Table walker walks initiated with long descriptors 38311138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 16343 # Level at which table walker walks with long descriptors terminate 38411138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 155686 # Level at which table walker walks with long descriptors terminate 38511138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksSquashedBefore 435595 # Table walks squashed before starting 38611138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 515950 # Table walker wait (enqueue to first request) latency 38711138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::mean 2268.523113 # Table walker wait (enqueue to first request) latency 38811138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::stdev 15037.920153 # Table walker wait (enqueue to first request) latency 38911138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0-65535 512394 99.31% 99.31% # Table walker wait (enqueue to first request) latency 39011138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::65536-131071 1973 0.38% 99.69% # Table walker wait (enqueue to first request) latency 39111138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::131072-196607 1076 0.21% 99.90% # Table walker wait (enqueue to first request) latency 39211138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::196608-262143 204 0.04% 99.94% # Table walker wait (enqueue to first request) latency 39311138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency 39411138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency 39511138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::393216-458751 58 0.01% 99.99% # Table walker wait (enqueue to first request) latency 39611138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency 39711138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency 39811138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 39911138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 40011138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 515950 # Table walker wait (enqueue to first request) latency 40111138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 484012 # Table walker service (enqueue to completion) latency 40211138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 23030.337058 # Table walker service (enqueue to completion) latency 40311138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 17887.395943 # Table walker service (enqueue to completion) latency 40411138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 21586.118666 # Table walker service (enqueue to completion) latency 40511138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 472338 97.59% 97.59% # Table walker service (enqueue to completion) latency 40611138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 7777 1.61% 99.19% # Table walker service (enqueue to completion) latency 40711138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 2811 0.58% 99.78% # Table walker service (enqueue to completion) latency 40811138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 207 0.04% 99.82% # Table walker service (enqueue to completion) latency 40911138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 566 0.12% 99.94% # Table walker service (enqueue to completion) latency 41011138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.96% # Table walker service (enqueue to completion) latency 41111138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 146 0.03% 99.99% # Table walker service (enqueue to completion) latency 41211138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 21 0.00% 100.00% # Table walker service (enqueue to completion) latency 41311138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency 41411138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 41511138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 41611138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 484012 # Table walker service (enqueue to completion) latency 41711138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 787280100836 # Table walker pending requests distribution 41811138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::mean 0.726034 # Table walker pending requests distribution 41911138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::stdev 0.521586 # Table walker pending requests distribution 42011138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0-1 785046223336 99.72% 99.72% # Table walker pending requests distribution 42111138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::2-3 1194986000 0.15% 99.87% # Table walker pending requests distribution 42211138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::4-5 471189500 0.06% 99.93% # Table walker pending requests distribution 42311138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::6-7 205721500 0.03% 99.95% # Table walker pending requests distribution 42411138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::8-9 152825500 0.02% 99.97% # Table walker pending requests distribution 42511138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::10-11 122394500 0.02% 99.99% # Table walker pending requests distribution 42611138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::12-13 28887000 0.00% 99.99% # Table walker pending requests distribution 42711138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::14-15 55269000 0.01% 100.00% # Table walker pending requests distribution 42811138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::16-17 2572500 0.00% 100.00% # Table walker pending requests distribution 42911138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::18-19 32000 0.00% 100.00% # Table walker pending requests distribution 43011138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 787280100836 # Table walker pending requests distribution 43111138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 155687 90.50% 90.50% # Table walker page sizes translated 43211138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 16343 9.50% 100.00% # Table walker page sizes translated 43311138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 172030 # Table walker page sizes translated 43411138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951545 # Table walker requests started/completed, data/inst 43510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43611138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 951545 # Table walker requests started/completed, data/inst 43711138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172030 # Table walker requests started/completed, data/inst 43810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 43911138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 172030 # Table walker requests started/completed, data/inst 44011138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 1123575 # Table walker requests started/completed, data/inst 44110585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 44210585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 44311138Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 170217039 # DTB read hits 44411138Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 674912 # DTB read misses 44511138Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 148367148 # DTB write hits 44611138Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 276633 # DTB write misses 44711138Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 44810585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 44911138Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID 45011138Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID 45111138Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 72532 # Number of entries that have been flushed from TLB 45211138Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions 45311138Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 10694 # Number of TLB faults due to prefetch 45410585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 45511138Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 70020 # Number of TLB faults due to permissions restrictions 45611138Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 170891951 # DTB read accesses 45711138Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 148643781 # DTB write accesses 45810585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 45911138Sandreas.hansson@arm.comsystem.cpu.dtb.hits 318584187 # DTB hits 46011138Sandreas.hansson@arm.comsystem.cpu.dtb.misses 951545 # DTB misses 46111138Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 319535732 # DTB accesses 46210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 46310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 46410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 46710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 47110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 47210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 47410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 47710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 47910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 48010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 48110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 48210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 48310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 48410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 48510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 48610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 48710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 48810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 48910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 49010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 49111138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 161585 # Table walker walks requested 49211138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 161585 # Table walker walks initiated with long descriptors 49311138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1428 # Level at which table walker walks with long descriptors terminate 49411138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 121821 # Level at which table walker walks with long descriptors terminate 49511138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksSquashedBefore 17557 # Table walks squashed before starting 49611138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 144028 # Table walker wait (enqueue to first request) latency 49711138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::mean 1321.829783 # Table walker wait (enqueue to first request) latency 49811138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::stdev 9926.807145 # Table walker wait (enqueue to first request) latency 49911138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0-32767 142959 99.26% 99.26% # Table walker wait (enqueue to first request) latency 50011138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::32768-65535 572 0.40% 99.65% # Table walker wait (enqueue to first request) latency 50111138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::65536-98303 68 0.05% 99.70% # Table walker wait (enqueue to first request) latency 50211138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::98304-131071 87 0.06% 99.76% # Table walker wait (enqueue to first request) latency 50311138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.95% # Table walker wait (enqueue to first request) latency 50411138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::163840-196607 28 0.02% 99.97% # Table walker wait (enqueue to first request) latency 50511138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency 50611138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::229376-262143 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency 50711138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::262144-294911 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency 50811138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency 50911138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 51011138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 51111138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 51211138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 144028 # Table walker wait (enqueue to first request) latency 51311138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 140806 # Table walker service (enqueue to completion) latency 51411138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 29194.196270 # Table walker service (enqueue to completion) latency 51511138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 24049.387193 # Table walker service (enqueue to completion) latency 51611138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 24612.430029 # Table walker service (enqueue to completion) latency 51711138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 137481 97.64% 97.64% # Table walker service (enqueue to completion) latency 51811138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 705 0.50% 98.14% # Table walker service (enqueue to completion) latency 51911138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 2241 1.59% 99.73% # Table walker service (enqueue to completion) latency 52011138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 147 0.10% 99.84% # Table walker service (enqueue to completion) latency 52111138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 149 0.11% 99.94% # Table walker service (enqueue to completion) latency 52211138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 40 0.03% 99.97% # Table walker service (enqueue to completion) latency 52311138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-458751 28 0.02% 99.99% # Table walker service (enqueue to completion) latency 52411138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 52511138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 52611138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52711138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52811138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 52911138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 140806 # Table walker service (enqueue to completion) latency 53011138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 671312841344 # Table walker pending requests distribution 53111138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::mean 0.944614 # Table walker pending requests distribution 53211138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::stdev 0.229094 # Table walker pending requests distribution 53311138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 37236199060 5.55% 5.55% # Table walker pending requests distribution 53411138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::1 634022806284 94.45% 99.99% # Table walker pending requests distribution 53511138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::2 53008500 0.01% 100.00% # Table walker pending requests distribution 53611138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::3 825500 0.00% 100.00% # Table walker pending requests distribution 53710892Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution 53811138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 671312841344 # Table walker pending requests distribution 53911138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 121821 98.84% 98.84% # Table walker page sizes translated 54011138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1428 1.16% 100.00% # Table walker page sizes translated 54111138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 123249 # Table walker page sizes translated 54210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54311138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161585 # Table walker requests started/completed, data/inst 54411138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 161585 # Table walker requests started/completed, data/inst 54510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54611138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123249 # Table walker requests started/completed, data/inst 54711138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 123249 # Table walker requests started/completed, data/inst 54811138Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 284834 # Table walker requests started/completed, data/inst 54911138Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 358536824 # ITB inst hits 55011138Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 161585 # ITB inst misses 55110585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 55210585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 55310585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 55410585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 55511138Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 55610585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55711138Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID 55811138Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID 55911138Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 53279 # Number of entries that have been flushed from TLB 56010585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56110585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 56210585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56311138Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 371261 # Number of TLB faults due to permissions restrictions 56410585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 56510585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 56611138Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 358698409 # ITB inst accesses 56711138Sandreas.hansson@arm.comsystem.cpu.itb.hits 358536824 # DTB hits 56811138Sandreas.hansson@arm.comsystem.cpu.itb.misses 161585 # DTB misses 56911138Sandreas.hansson@arm.comsystem.cpu.itb.accesses 358698409 # DTB accesses 57011138Sandreas.hansson@arm.comsystem.cpu.numCycles 1657263364 # number of cpu cycles simulated 57110585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57210585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 57311138Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 646687588 # Number of cycles fetch is stalled on an Icache miss 57411138Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 1006138467 # Number of instructions fetch has processed 57511138Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 225483777 # Number of branches that fetch encountered 57611138Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 135052255 # Number of branches that fetch has predicted taken 57711138Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 923834525 # Number of cycles fetch has run and was not squashing or blocked 57811138Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 26119142 # Number of cycles fetch has spent squashing 57911138Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 3836248 # Number of cycles fetch has spent waiting for tlb 58011138Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 30247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 58111138Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 9382773 # Number of stall cycles due to pending traps 58211138Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 1057490 # Number of stall cycles due to pending quiesce instructions 58311138Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 1024 # Number of stall cycles due to full MSHR 58411138Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 358148752 # Number of cache lines fetched 58511138Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 6114742 # Number of outstanding Icache misses that were squashed 58611138Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed 58711138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 1597889466 # Number of instructions fetched each cycle (Total) 58811138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.737838 # Number of instructions fetched each cycle (Total) 58911138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.145066 # Number of instructions fetched each cycle (Total) 59010585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 59111138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 1037892560 64.95% 64.95% # Number of instructions fetched each cycle (Total) 59211138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 215037687 13.46% 78.41% # Number of instructions fetched each cycle (Total) 59311138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 70931005 4.44% 82.85% # Number of instructions fetched each cycle (Total) 59411138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 274028214 17.15% 100.00% # Number of instructions fetched each cycle (Total) 59510585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 59610585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 59710585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 59811138Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 1597889466 # Number of instructions fetched each cycle (Total) 59911138Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.136058 # Number of branch fetches per cycle 60011138Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.607108 # Number of inst fetches per cycle 60111138Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 525509961 # Number of cycles decode is idle 60211138Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 577968560 # Number of cycles decode is blocked 60311138Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 434692108 # Number of cycles decode is running 60411138Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 50467392 # Number of cycles decode is unblocking 60511138Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 9251445 # Number of cycles decode is squashing 60611138Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 33765808 # Number of times decode resolved a branch 60711138Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 3868232 # Number of times decode detected a branch misprediction 60811138Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 1090395947 # Number of instructions handled by decode 60911138Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 29075856 # Number of squashed instructions handled by decode 61011138Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 9251445 # Number of cycles rename is squashing 61111138Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 570461027 # Number of cycles rename is idle 61211138Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 71248505 # Number of cycles rename is blocking 61311138Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 374528556 # count of cycles rename stalled for serializing inst 61411138Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 440187114 # Number of cycles rename is running 61511138Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 132212819 # Number of cycles rename is unblocking 61611138Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 1070563825 # Number of instructions processed by rename 61711138Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 6799460 # Number of squashed instructions processed by rename 61811138Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 5139795 # Number of times rename has blocked due to ROB full 61911138Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 352432 # Number of times rename has blocked due to IQ full 62011138Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 543797 # Number of times rename has blocked due to LQ full 62111138Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 80592393 # Number of times rename has blocked due to SQ full 62211138Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 20524 # Number of times there has been no free registers 62311138Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 1018210604 # Number of destination operands rename has renamed 62411138Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 1650018567 # Number of register rename lookups that rename has made 62511138Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 1266293182 # Number of integer rename lookups 62611138Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 1471142 # Number of floating rename lookups 62711138Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 952425146 # Number of HB maps that are committed 62811138Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 65785455 # Number of HB maps that are undone due to squashing 62911138Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 27183969 # count of serializing insts renamed 63011138Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 23507268 # count of temporary serializing insts renamed 63111138Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 103615043 # count of insts added to the skid buffer 63211138Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 174251996 # Number of loads inserted to the mem dependence unit. 63311138Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 151954482 # Number of stores inserted to the mem dependence unit. 63411138Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 9963478 # Number of conflicting loads. 63511138Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 9058683 # Number of conflicting stores. 63611138Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 1035258502 # Number of instructions added to the IQ (excludes non-spec) 63711138Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 27485968 # Number of non-speculative instructions added to the IQ 63811138Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 1050977707 # Number of instructions issued 63911138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 3302134 # Number of squashed instructions issued 64011138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 60681110 # Number of squashed instructions iterated over during squash; mainly for profiling 64111138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 33832223 # Number of squashed operands that are examined and possibly removed from graph 64211138Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 315804 # Number of squashed non-spec instructions that were removed 64311138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 1597889466 # Number of insts issued each cycle 64411138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.657729 # Number of insts issued each cycle 64511138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 0.917270 # Number of insts issued each cycle 64610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 64711138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 947140839 59.27% 59.27% # Number of insts issued each cycle 64811138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 336074269 21.03% 80.31% # Number of insts issued each cycle 64911138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 235675867 14.75% 95.06% # Number of insts issued each cycle 65011138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 72461429 4.53% 99.59% # Number of insts issued each cycle 65111138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 6517893 0.41% 100.00% # Number of insts issued each cycle 65211138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle 65310585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 65410585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 65510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 65610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 65710585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 65810585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 65911138Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 1597889466 # Number of insts issued each cycle 66010585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 66111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 58047509 35.02% 35.02% # attempts to use FU when none available 66211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 99216 0.06% 35.08% # attempts to use FU when none available 66311138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 26736 0.02% 35.10% # attempts to use FU when none available 66411138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 35.10% # attempts to use FU when none available 66511138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 35.10% # attempts to use FU when none available 66611138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 35.10% # attempts to use FU when none available 66711138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 35.10% # attempts to use FU when none available 66811138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 35.10% # attempts to use FU when none available 66911138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.10% # attempts to use FU when none available 67011138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 35.10% # attempts to use FU when none available 67111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.10% # attempts to use FU when none available 67211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 35.10% # attempts to use FU when none available 67311138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 35.10% # attempts to use FU when none available 67411138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 35.10% # attempts to use FU when none available 67511138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 35.10% # attempts to use FU when none available 67611138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 35.10% # attempts to use FU when none available 67711138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.10% # attempts to use FU when none available 67811138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 35.10% # attempts to use FU when none available 67911138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.10% # attempts to use FU when none available 68011138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.10% # attempts to use FU when none available 68111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.10% # attempts to use FU when none available 68211138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.10% # attempts to use FU when none available 68311138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.10% # attempts to use FU when none available 68411138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.10% # attempts to use FU when none available 68511138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.10% # attempts to use FU when none available 68611138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 621 0.00% 35.10% # attempts to use FU when none available 68711138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.10% # attempts to use FU when none available 68811138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.10% # attempts to use FU when none available 68911138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.10% # attempts to use FU when none available 69011138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 44536420 26.87% 61.97% # attempts to use FU when none available 69111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 63031836 38.03% 100.00% # attempts to use FU when none available 69210585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 69310585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 69411138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued 69511138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 723805798 68.87% 68.87% # Type of FU issued 69611138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 2543227 0.24% 69.11% # Type of FU issued 69711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 122751 0.01% 69.12% # Type of FU issued 69811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued 69911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued 70011138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued 70111138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued 70211138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued 70311138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued 70411138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued 70511138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued 70611138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued 70711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued 70811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued 70911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued 71011138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued 71111138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued 71211138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued 71311138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued 71411138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued 71511138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued 71611138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued 71711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued 71811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued 71911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued 72011138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 120969 0.01% 69.13% # Type of FU issued 72111138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued 72211138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued 72311138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued 72411138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 174113455 16.57% 85.70% # Type of FU issued 72511138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 150271445 14.30% 100.00% # Type of FU issued 72610585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 72710585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 72811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 1050977707 # Type of FU issued 72911138Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.634165 # Inst issue rate 73011138Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 165742338 # FU busy when requested 73111138Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.157703 # FU busy rate (busy events/executed inst) 73211138Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 3866409671 # Number of integer instruction queue reads 73311138Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 1122621449 # Number of integer instruction queue writes 73411138Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 1032956403 # Number of integer instruction queue wakeup accesses 73511138Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 2479680 # Number of floating instruction queue reads 73611138Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 948183 # Number of floating instruction queue writes 73711138Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 910717 # Number of floating instruction queue wakeup accesses 73811138Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 1215162069 # Number of integer alu accesses 73911138Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 1557965 # Number of floating point alu accesses 74011138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 4345381 # Number of loads that had data forwarded from stores 74110585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 74211138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 13856832 # Number of loads squashed 74311138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 14557 # Number of memory responses ignored because the instruction is squashed 74411138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 145376 # Number of memory ordering violations 74511138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 6348158 # Number of stores squashed 74610585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 74710585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 74811138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 2556112 # Number of loads that were rescheduled 74911138Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 1569383 # Number of times an access to memory failed due to the cache being blocked 75010585Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 75111138Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 9251445 # Number of cycles IEW is squashing 75211138Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 7205871 # Number of cycles IEW is blocking 75311138Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 9780746 # Number of cycles IEW is unblocking 75411138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 1062967049 # Number of instructions dispatched to IQ 75510585Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 75611138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 174251996 # Number of dispatched load instructions 75711138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 151954482 # Number of dispatched store instructions 75811138Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 23081360 # Number of dispatched non-speculative instructions 75911138Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 59250 # Number of times the IQ has become full, causing a stall 76011138Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 9646548 # Number of times the LSQ has become full, causing a stall 76111138Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 145376 # Number of memory order violations 76211138Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 3669738 # Number of branches that were predicted taken incorrectly 76311138Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 5114532 # Number of branches that were predicted not taken incorrectly 76411138Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 8784270 # Number of branch mispredicts detected at execute 76511138Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 1039771083 # Number of executed instructions 76611138Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 170205641 # Number of load instructions executed 76711138Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 10266382 # Number of squashed instructions skipped in execute 76810585Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 76911138Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 222579 # number of nop insts executed 77011138Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 318568485 # number of memory reference insts executed 77111138Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 197267293 # Number of branches executed 77211138Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 148362844 # Number of stores executed 77311138Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.627402 # Inst execution rate 77411138Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 1034679114 # cumulative count of insts sent to commit 77511138Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 1033867120 # cumulative count of insts written-back 77611138Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 440084197 # num instructions producing a value 77711138Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 711913770 # num instructions consuming a value 77810585Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 77911138Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.623840 # insts written-back per cycle 78011138Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.618171 # average fanout of values written-back 78110585Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 78211138Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 51558670 # The number of squashed insts skipped by commit 78311138Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 27170164 # The number of times commit has been forced to stall to communicate backwards 78411138Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 8418357 # The number of times a branch was mispredicted 78511138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 1585876661 # Number of insts commited each cycle 78611138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.631867 # Number of insts commited each cycle 78711138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.268709 # Number of insts commited each cycle 78810585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 78911138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 1071299476 67.55% 67.55% # Number of insts commited each cycle 79011138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 289640402 18.26% 85.82% # Number of insts commited each cycle 79111138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 120963875 7.63% 93.44% # Number of insts commited each cycle 79211138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 36621114 2.31% 95.75% # Number of insts commited each cycle 79311138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 28592038 1.80% 97.56% # Number of insts commited each cycle 79411138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 14082122 0.89% 98.44% # Number of insts commited each cycle 79511138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 8687118 0.55% 98.99% # Number of insts commited each cycle 79611138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 4193736 0.26% 99.26% # Number of insts commited each cycle 79711138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 11796780 0.74% 100.00% # Number of insts commited each cycle 79810585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 79910585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 80010585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 80111138Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 1585876661 # Number of insts commited each cycle 80211138Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 852762944 # Number of instructions committed 80311138Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 1002063356 # Number of ops (including micro ops) committed 80410585Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 80511138Sandreas.hansson@arm.comsystem.cpu.commit.refs 306001487 # Number of memory references committed 80611138Sandreas.hansson@arm.comsystem.cpu.commit.loads 160395163 # Number of loads committed 80711138Sandreas.hansson@arm.comsystem.cpu.commit.membars 6971183 # Number of memory barriers committed 80811138Sandreas.hansson@arm.comsystem.cpu.commit.branches 190333133 # Number of branches committed 80911138Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 897329 # Number of committed floating point instructions. 81011138Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 920660333 # Number of committed integer instructions. 81111138Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 25420821 # Number of function calls committed. 81210585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 81311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 693695163 69.23% 69.23% # Class of committed instruction 81411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 2156692 0.22% 69.44% # Class of committed instruction 81511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 98172 0.01% 69.45% # Class of committed instruction 81611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction 81711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction 81811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction 81911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction 82011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction 82111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction 82211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction 82311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction 82411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction 82511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction 82611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction 82711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction 82811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction 82911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction 83011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction 83111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction 83211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction 83311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction 83411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction 83511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction 83611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction 83711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction 83811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 111800 0.01% 69.46% # Class of committed instruction 83911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction 84011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 84111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 84211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 160395163 16.01% 85.47% # Class of committed instruction 84311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 145606324 14.53% 100.00% # Class of committed instruction 84410585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 84510585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 84611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 1002063356 # Class of committed instruction 84711138Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 11796780 # number cycles where commit BW limit reached 84811138Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 2620126782 # The number of ROB reads 84911138Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 2119163855 # The number of ROB writes 85011138Sandreas.hansson@arm.comsystem.cpu.timesIdled 8145872 # Number of times that the entire CPU went into an idle state and unscheduled itself 85111138Sandreas.hansson@arm.comsystem.cpu.idleCycles 59373898 # Total number of cycles that the CPU has spent unscheduled due to idling 85211138Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 100926342082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 85311138Sandreas.hansson@arm.comsystem.cpu.committedInsts 852762944 # Number of Instructions Simulated 85411138Sandreas.hansson@arm.comsystem.cpu.committedOps 1002063356 # Number of Ops (including micro ops) Simulated 85511138Sandreas.hansson@arm.comsystem.cpu.cpi 1.943405 # CPI: Cycles Per Instruction 85611138Sandreas.hansson@arm.comsystem.cpu.cpi_total 1.943405 # CPI: Total CPI of All Threads 85711138Sandreas.hansson@arm.comsystem.cpu.ipc 0.514561 # IPC: Instructions Per Cycle 85811138Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.514561 # IPC: Total IPC of All Threads 85911138Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 1230978083 # number of integer regfile reads 86011138Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 734956592 # number of integer regfile writes 86111138Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 1462594 # number of floating regfile reads 86211138Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 785720 # number of floating regfile writes 86311138Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 226481409 # number of cc regfile reads 86411138Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 227147205 # number of cc regfile writes 86511138Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2590605655 # number of misc regfile reads 86611138Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 27218545 # number of misc regfile writes 86711138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 9745793 # number of replacements 86811138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.972785 # Cycle average of tags in use 86911138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 284478201 # Total number of references to valid blocks. 87011138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 9746305 # Sample count of references to valid blocks. 87111138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 29.188313 # Average number of references to valid blocks. 87211138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 2742937500 # Cycle when the warmup percentage was hit. 87311138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.972785 # Average occupied blocks per requestor 87411138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy 87511138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy 87610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 87711138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 87811138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id 87911138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 88010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88111138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1242843351 # Number of tag accesses 88211138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1242843351 # Number of data accesses 88311138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 147746281 # number of ReadReq hits 88411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 147746281 # number of ReadReq hits 88511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 128943597 # number of WriteReq hits 88611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 128943597 # number of WriteReq hits 88711138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 378897 # number of SoftPFReq hits 88811138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 378897 # number of SoftPFReq hits 88911138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 324717 # number of WriteLineReq hits 89011138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 324717 # number of WriteLineReq hits 89111138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3321055 # number of LoadLockedReq hits 89211138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3321055 # number of LoadLockedReq hits 89311138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3719262 # number of StoreCondReq hits 89411138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3719262 # number of StoreCondReq hits 89511138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 276689878 # number of demand (read+write) hits 89611138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 276689878 # number of demand (read+write) hits 89711138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 277068775 # number of overall hits 89811138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 277068775 # number of overall hits 89911138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 9599758 # number of ReadReq misses 90011138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 9599758 # number of ReadReq misses 90111138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 11373760 # number of WriteReq misses 90211138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 11373760 # number of WriteReq misses 90311138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1183380 # number of SoftPFReq misses 90411138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1183380 # number of SoftPFReq misses 90511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1233189 # number of WriteLineReq misses 90611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1233189 # number of WriteLineReq misses 90711138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 450358 # number of LoadLockedReq misses 90811138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 450358 # number of LoadLockedReq misses 90911138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 91011138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 91111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 20973518 # number of demand (read+write) misses 91211138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 20973518 # number of demand (read+write) misses 91311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 22156898 # number of overall misses 91411138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 22156898 # number of overall misses 91511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 170465804000 # number of ReadReq miss cycles 91611138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 170465804000 # number of ReadReq miss cycles 91711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 459745522921 # number of WriteReq miss cycles 91811138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 459745522921 # number of WriteReq miss cycles 91911138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 90424230789 # number of WriteLineReq miss cycles 92011138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::total 90424230789 # number of WriteLineReq miss cycles 92111138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6989283500 # number of LoadLockedReq miss cycles 92211138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 6989283500 # number of LoadLockedReq miss cycles 92311138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276500 # number of StoreCondReq miss cycles 92411138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 276500 # number of StoreCondReq miss cycles 92511138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 630211326921 # number of demand (read+write) miss cycles 92611138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 630211326921 # number of demand (read+write) miss cycles 92711138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 630211326921 # number of overall miss cycles 92811138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 630211326921 # number of overall miss cycles 92911138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 157346039 # number of ReadReq accesses(hits+misses) 93011138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 157346039 # number of ReadReq accesses(hits+misses) 93111138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 140317357 # number of WriteReq accesses(hits+misses) 93211138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 140317357 # number of WriteReq accesses(hits+misses) 93311138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 1562277 # number of SoftPFReq accesses(hits+misses) 93411138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 1562277 # number of SoftPFReq accesses(hits+misses) 93511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1557906 # number of WriteLineReq accesses(hits+misses) 93611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1557906 # number of WriteLineReq accesses(hits+misses) 93711138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3771413 # number of LoadLockedReq accesses(hits+misses) 93811138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3771413 # number of LoadLockedReq accesses(hits+misses) 93911138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3719267 # number of StoreCondReq accesses(hits+misses) 94011138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3719267 # number of StoreCondReq accesses(hits+misses) 94111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 297663396 # number of demand (read+write) accesses 94211138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 297663396 # number of demand (read+write) accesses 94311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 299225673 # number of overall (read+write) accesses 94411138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 299225673 # number of overall (read+write) accesses 94511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061010 # miss rate for ReadReq accesses 94611138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.061010 # miss rate for ReadReq accesses 94711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081057 # miss rate for WriteReq accesses 94811138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.081057 # miss rate for WriteReq accesses 94911138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757471 # miss rate for SoftPFReq accesses 95011138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.757471 # miss rate for SoftPFReq accesses 95111138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791568 # miss rate for WriteLineReq accesses 95211138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.791568 # miss rate for WriteLineReq accesses 95311138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119414 # miss rate for LoadLockedReq accesses 95411138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.119414 # miss rate for LoadLockedReq accesses 95511103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 95611103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 95711138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.070461 # miss rate for demand accesses 95811138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.070461 # miss rate for demand accesses 95911138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.074047 # miss rate for overall accesses 96011138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.074047 # miss rate for overall accesses 96111138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17757.302215 # average ReadReq miss latency 96211138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17757.302215 # average ReadReq miss latency 96311138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40421.595226 # average WriteReq miss latency 96411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 40421.595226 # average WriteReq miss latency 96511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 73325.524951 # average WriteLineReq miss latency 96611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 73325.524951 # average WriteLineReq miss latency 96711138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15519.394571 # average LoadLockedReq miss latency 96811138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15519.394571 # average LoadLockedReq miss latency 96911138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55300 # average StoreCondReq miss latency 97011138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 55300 # average StoreCondReq miss latency 97111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 30047.955089 # average overall miss latency 97211138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 30047.955089 # average overall miss latency 97311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 28443.120825 # average overall miss latency 97411138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 28443.120825 # average overall miss latency 97511138Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 50799342 # number of cycles access was blocked 97610585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97711138Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 1609216 # number of cycles access was blocked 97810585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 97911138Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 31.567758 # average number of cycles each access was blocked 98010585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 98110585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 98210585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 98311138Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 7545853 # number of writebacks 98411138Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 7545853 # number of writebacks 98511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 4464090 # number of ReadReq MSHR hits 98611138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 4464090 # number of ReadReq MSHR hits 98711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 9352283 # number of WriteReq MSHR hits 98811138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 9352283 # number of WriteReq MSHR hits 98911138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6863 # number of WriteLineReq MSHR hits 99011138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_hits::total 6863 # number of WriteLineReq MSHR hits 99111138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220342 # number of LoadLockedReq MSHR hits 99211138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 220342 # number of LoadLockedReq MSHR hits 99311138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 13816373 # number of demand (read+write) MSHR hits 99411138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 13816373 # number of demand (read+write) MSHR hits 99511138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 13816373 # number of overall MSHR hits 99611138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 13816373 # number of overall MSHR hits 99711138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5135668 # number of ReadReq MSHR misses 99811138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 5135668 # number of ReadReq MSHR misses 99911138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2021477 # number of WriteReq MSHR misses 100011138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2021477 # number of WriteReq MSHR misses 100111138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1176591 # number of SoftPFReq MSHR misses 100211138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1176591 # number of SoftPFReq MSHR misses 100311138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226326 # number of WriteLineReq MSHR misses 100411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::total 1226326 # number of WriteLineReq MSHR misses 100511138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230016 # number of LoadLockedReq MSHR misses 100611138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 230016 # number of LoadLockedReq MSHR misses 100711138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 100811138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 100911138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 7157145 # number of demand (read+write) MSHR misses 101011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 7157145 # number of demand (read+write) MSHR misses 101111138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 8333736 # number of overall MSHR misses 101211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 8333736 # number of overall MSHR misses 101311138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 101411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable 101511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 101611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 101711138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 101811138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses 101911138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85690864500 # number of ReadReq MSHR miss cycles 102011138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 85690864500 # number of ReadReq MSHR miss cycles 102111138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79882963880 # number of WriteReq MSHR miss cycles 102211138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 79882963880 # number of WriteReq MSHR miss cycles 102311138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 24040362000 # number of SoftPFReq MSHR miss cycles 102411138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 24040362000 # number of SoftPFReq MSHR miss cycles 102511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 88797727789 # number of WriteLineReq MSHR miss cycles 102611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 88797727789 # number of WriteLineReq MSHR miss cycles 102711138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3265448000 # number of LoadLockedReq MSHR miss cycles 102811138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3265448000 # number of LoadLockedReq MSHR miss cycles 102911138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles 103011138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles 103111138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 165573828380 # number of demand (read+write) MSHR miss cycles 103211138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 165573828380 # number of demand (read+write) MSHR miss cycles 103311138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 189614190380 # number of overall MSHR miss cycles 103411138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 189614190380 # number of overall MSHR miss cycles 103511138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829312500 # number of ReadReq MSHR uncacheable cycles 103611138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829312500 # number of ReadReq MSHR uncacheable cycles 103711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5836671467 # number of WriteReq MSHR uncacheable cycles 103811138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5836671467 # number of WriteReq MSHR uncacheable cycles 103911138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11665983967 # number of overall MSHR uncacheable cycles 104011138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 11665983967 # number of overall MSHR uncacheable cycles 104111138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032639 # mshr miss rate for ReadReq accesses 104211138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032639 # mshr miss rate for ReadReq accesses 104311138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014406 # mshr miss rate for WriteReq accesses 104411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014406 # mshr miss rate for WriteReq accesses 104511138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753126 # mshr miss rate for SoftPFReq accesses 104611138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753126 # mshr miss rate for SoftPFReq accesses 104711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787163 # mshr miss rate for WriteLineReq accesses 104811138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787163 # mshr miss rate for WriteLineReq accesses 104911138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060989 # mshr miss rate for LoadLockedReq accesses 105011138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060989 # mshr miss rate for LoadLockedReq accesses 105111103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 105211103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 105311138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024044 # mshr miss rate for demand accesses 105411138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.024044 # mshr miss rate for demand accesses 105511138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027851 # mshr miss rate for overall accesses 105611138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.027851 # mshr miss rate for overall accesses 105711138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16685.436929 # average ReadReq mshr miss latency 105811138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16685.436929 # average ReadReq mshr miss latency 105911138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39517.127269 # average WriteReq mshr miss latency 106011138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39517.127269 # average WriteReq mshr miss latency 106111138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20432.216463 # average SoftPFReq mshr miss latency 106211138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20432.216463 # average SoftPFReq mshr miss latency 106311138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72409.561396 # average WriteLineReq mshr miss latency 106411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72409.561396 # average WriteLineReq mshr miss latency 106511138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14196.612410 # average LoadLockedReq mshr miss latency 106611138Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14196.612410 # average LoadLockedReq mshr miss latency 106711138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency 106811138Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency 106911138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23134.060911 # average overall mshr miss latency 107011138Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 23134.060911 # average overall mshr miss latency 107111138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22752.603440 # average overall mshr miss latency 107211138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 22752.603440 # average overall mshr miss latency 107311138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173089.628244 # average ReadReq mshr uncacheable latency 107411138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173089.628244 # average ReadReq mshr uncacheable latency 107511138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173215.558731 # average WriteReq mshr uncacheable latency 107611138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173215.558731 # average WriteReq mshr uncacheable latency 107711138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173152.610310 # average overall mshr uncacheable latency 107811138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173152.610310 # average overall mshr uncacheable latency 107910585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 108011138Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 15058288 # number of replacements 108111138Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.916796 # Cycle average of tags in use 108211138Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 342301291 # Total number of references to valid blocks. 108311138Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 15058800 # Sample count of references to valid blocks. 108411138Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 22.730981 # Average number of references to valid blocks. 108511138Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 24732660500 # Cycle when the warmup percentage was hit. 108611138Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.916796 # Average occupied blocks per requestor 108711138Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999837 # Average percentage of cache occupancy 108811138Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999837 # Average percentage of cache occupancy 108910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 109011138Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 109111138Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id 109211138Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id 109310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 109411138Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 373186476 # Number of tag accesses 109511138Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 373186476 # Number of data accesses 109611138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 342301291 # number of ReadReq hits 109711138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 342301291 # number of ReadReq hits 109811138Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 342301291 # number of demand (read+write) hits 109911138Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 342301291 # number of demand (read+write) hits 110011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 342301291 # number of overall hits 110111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 342301291 # number of overall hits 110211138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 15826164 # number of ReadReq misses 110311138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 15826164 # number of ReadReq misses 110411138Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 15826164 # number of demand (read+write) misses 110511138Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 15826164 # number of demand (read+write) misses 110611138Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 15826164 # number of overall misses 110711138Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 15826164 # number of overall misses 110811138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 213799135380 # number of ReadReq miss cycles 110911138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 213799135380 # number of ReadReq miss cycles 111011138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 213799135380 # number of demand (read+write) miss cycles 111111138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 213799135380 # number of demand (read+write) miss cycles 111211138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 213799135380 # number of overall miss cycles 111311138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 213799135380 # number of overall miss cycles 111411138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 358127455 # number of ReadReq accesses(hits+misses) 111511138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 358127455 # number of ReadReq accesses(hits+misses) 111611138Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 358127455 # number of demand (read+write) accesses 111711138Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 358127455 # number of demand (read+write) accesses 111811138Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 358127455 # number of overall (read+write) accesses 111911138Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 358127455 # number of overall (read+write) accesses 112011138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044191 # miss rate for ReadReq accesses 112111138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.044191 # miss rate for ReadReq accesses 112211138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.044191 # miss rate for demand accesses 112311138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.044191 # miss rate for demand accesses 112411138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.044191 # miss rate for overall accesses 112511138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.044191 # miss rate for overall accesses 112611138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.220262 # average ReadReq miss latency 112711138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13509.220262 # average ReadReq miss latency 112811138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.220262 # average overall miss latency 112911138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13509.220262 # average overall miss latency 113011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.220262 # average overall miss latency 113111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13509.220262 # average overall miss latency 113211138Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 22973 # number of cycles access was blocked 113310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 113411138Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1424 # number of cycles access was blocked 113510585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 113611138Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 16.132725 # average number of cycles each access was blocked 113710585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 113810585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 113910585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 114011138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 767143 # number of ReadReq MSHR hits 114111138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 767143 # number of ReadReq MSHR hits 114211138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 767143 # number of demand (read+write) MSHR hits 114311138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 767143 # number of demand (read+write) MSHR hits 114411138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 767143 # number of overall MSHR hits 114511138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 767143 # number of overall MSHR hits 114611138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 15059021 # number of ReadReq MSHR misses 114711138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 15059021 # number of ReadReq MSHR misses 114811138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 15059021 # number of demand (read+write) MSHR misses 114911138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 15059021 # number of demand (read+write) MSHR misses 115011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 15059021 # number of overall MSHR misses 115111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 15059021 # number of overall MSHR misses 115210827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable 115310827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable 115410827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses 115510827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses 115611138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191438172888 # number of ReadReq MSHR miss cycles 115711138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 191438172888 # number of ReadReq MSHR miss cycles 115811138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 191438172888 # number of demand (read+write) MSHR miss cycles 115911138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 191438172888 # number of demand (read+write) MSHR miss cycles 116011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 191438172888 # number of overall MSHR miss cycles 116111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 191438172888 # number of overall MSHR miss cycles 116211138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684494000 # number of ReadReq MSHR uncacheable cycles 116311138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684494000 # number of ReadReq MSHR uncacheable cycles 116411138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684494000 # number of overall MSHR uncacheable cycles 116511138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 2684494000 # number of overall MSHR uncacheable cycles 116611138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042049 # mshr miss rate for ReadReq accesses 116711138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.042049 # mshr miss rate for ReadReq accesses 116811138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042049 # mshr miss rate for demand accesses 116911138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.042049 # mshr miss rate for demand accesses 117011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042049 # mshr miss rate for overall accesses 117111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.042049 # mshr miss rate for overall accesses 117211138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12712.524465 # average ReadReq mshr miss latency 117311138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12712.524465 # average ReadReq mshr miss latency 117411138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12712.524465 # average overall mshr miss latency 117511138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12712.524465 # average overall mshr miss latency 117611138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12712.524465 # average overall mshr miss latency 117711138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12712.524465 # average overall mshr miss latency 117811138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126062.174219 # average ReadReq mshr uncacheable latency 117911138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126062.174219 # average ReadReq mshr uncacheable latency 118011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126062.174219 # average overall mshr uncacheable latency 118111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126062.174219 # average overall mshr uncacheable latency 118210585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 118311138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 1176236 # number of replacements 118411138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65290.779301 # Cycle average of tags in use 118511138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 46162574 # Total number of references to valid blocks. 118611138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1238713 # Sample count of references to valid blocks. 118711138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 37.266561 # Average number of references to valid blocks. 118811138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 22917959500 # Cycle when the warmup percentage was hit. 118911138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 36954.336619 # Average occupied blocks per requestor 119011138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 291.683673 # Average occupied blocks per requestor 119111138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 428.373283 # Average occupied blocks per requestor 119211138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 7875.894606 # Average occupied blocks per requestor 119311138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 19740.491120 # Average occupied blocks per requestor 119411138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.563878 # Average percentage of cache occupancy 119511138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004451 # Average percentage of cache occupancy 119611138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006536 # Average percentage of cache occupancy 119711138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.120177 # Average percentage of cache occupancy 119811138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.301216 # Average percentage of cache occupancy 119911138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996258 # Average percentage of cache occupancy 120011138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 337 # Occupied blocks per task id 120111138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62140 # Occupied blocks per task id 120211138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 337 # Occupied blocks per task id 120311138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 120411138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 548 # Occupied blocks per task id 120511138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2678 # Occupied blocks per task id 120611138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5174 # Occupied blocks per task id 120711138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 53667 # Occupied blocks per task id 120811138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.005142 # Percentage of cache occupancy per task id 120911138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.948181 # Percentage of cache occupancy per task id 121011138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 410385011 # Number of tag accesses 121111138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 410385011 # Number of data accesses 121211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 782076 # number of ReadReq hits 121311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 296128 # number of ReadReq hits 121411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1078204 # number of ReadReq hits 121511138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 7545853 # number of Writeback hits 121611138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 7545853 # number of Writeback hits 121711138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 9384 # number of UpgradeReq hits 121811138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 9384 # number of UpgradeReq hits 121911138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 122011138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 122111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1569943 # number of ReadExReq hits 122211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1569943 # number of ReadExReq hits 122311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14973985 # number of ReadCleanReq hits 122411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 14973985 # number of ReadCleanReq hits 122511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 6275024 # number of ReadSharedReq hits 122611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 6275024 # number of ReadSharedReq hits 122711138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 724229 # number of InvalidateReq hits 122811138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 724229 # number of InvalidateReq hits 122911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 782076 # number of demand (read+write) hits 123011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 296128 # number of demand (read+write) hits 123111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 14973985 # number of demand (read+write) hits 123211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 7844967 # number of demand (read+write) hits 123311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 23897156 # number of demand (read+write) hits 123411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 782076 # number of overall hits 123511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 296128 # number of overall hits 123611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 14973985 # number of overall hits 123711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 7844967 # number of overall hits 123811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 23897156 # number of overall hits 123911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3726 # number of ReadReq misses 124011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3665 # number of ReadReq misses 124111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 7391 # number of ReadReq misses 124211138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 34382 # number of UpgradeReq misses 124311138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 34382 # number of UpgradeReq misses 124410726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 124510726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 124611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 411208 # number of ReadExReq misses 124711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 411208 # number of ReadExReq misses 124811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 84827 # number of ReadCleanReq misses 124911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 84827 # number of ReadCleanReq misses 125011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 263816 # number of ReadSharedReq misses 125111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 263816 # number of ReadSharedReq misses 125211138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 502095 # number of InvalidateReq misses 125311138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 502095 # number of InvalidateReq misses 125411138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 3726 # number of demand (read+write) misses 125511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 3665 # number of demand (read+write) misses 125611138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 84827 # number of demand (read+write) misses 125711138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 675024 # number of demand (read+write) misses 125811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 767242 # number of demand (read+write) misses 125911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 3726 # number of overall misses 126011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 3665 # number of overall misses 126111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 84827 # number of overall misses 126211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 675024 # number of overall misses 126311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 767242 # number of overall misses 126411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 518326000 # number of ReadReq miss cycles 126511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 506161500 # number of ReadReq miss cycles 126611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 1024487500 # number of ReadReq miss cycles 126711138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1432062500 # number of UpgradeReq miss cycles 126811138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 1432062500 # number of UpgradeReq miss cycles 126910892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 127010892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 127111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57210260500 # number of ReadExReq miss cycles 127211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 57210260500 # number of ReadExReq miss cycles 127311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11415315000 # number of ReadCleanReq miss cycles 127411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 11415315000 # number of ReadCleanReq miss cycles 127511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 36742519500 # number of ReadSharedReq miss cycles 127611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 36742519500 # number of ReadSharedReq miss cycles 127711138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 77896039000 # number of InvalidateReq miss cycles 127811138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::total 77896039000 # number of InvalidateReq miss cycles 127911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 518326000 # number of demand (read+write) miss cycles 128011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 506161500 # number of demand (read+write) miss cycles 128111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11415315000 # number of demand (read+write) miss cycles 128211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 93952780000 # number of demand (read+write) miss cycles 128311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 106392582500 # number of demand (read+write) miss cycles 128411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 518326000 # number of overall miss cycles 128511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 506161500 # number of overall miss cycles 128611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11415315000 # number of overall miss cycles 128711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 93952780000 # number of overall miss cycles 128811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 106392582500 # number of overall miss cycles 128911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 785802 # number of ReadReq accesses(hits+misses) 129011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 299793 # number of ReadReq accesses(hits+misses) 129111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1085595 # number of ReadReq accesses(hits+misses) 129211138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 7545853 # number of Writeback accesses(hits+misses) 129311138Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 7545853 # number of Writeback accesses(hits+misses) 129411138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 43766 # number of UpgradeReq accesses(hits+misses) 129511138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 43766 # number of UpgradeReq accesses(hits+misses) 129611138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 129711138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 129811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1981151 # number of ReadExReq accesses(hits+misses) 129911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1981151 # number of ReadExReq accesses(hits+misses) 130011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15058812 # number of ReadCleanReq accesses(hits+misses) 130111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 15058812 # number of ReadCleanReq accesses(hits+misses) 130211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6538840 # number of ReadSharedReq accesses(hits+misses) 130311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 6538840 # number of ReadSharedReq accesses(hits+misses) 130411138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226324 # number of InvalidateReq accesses(hits+misses) 130511138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1226324 # number of InvalidateReq accesses(hits+misses) 130611138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 785802 # number of demand (read+write) accesses 130711138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 299793 # number of demand (read+write) accesses 130811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 15058812 # number of demand (read+write) accesses 130911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 8519991 # number of demand (read+write) accesses 131011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 24664398 # number of demand (read+write) accesses 131111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 785802 # number of overall (read+write) accesses 131211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 299793 # number of overall (read+write) accesses 131311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 15058812 # number of overall (read+write) accesses 131411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 8519991 # number of overall (read+write) accesses 131511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 24664398 # number of overall (read+write) accesses 131611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004742 # miss rate for ReadReq accesses 131711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.012225 # miss rate for ReadReq accesses 131811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.006808 # miss rate for ReadReq accesses 131911138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785587 # miss rate for UpgradeReq accesses 132011138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.785587 # miss rate for UpgradeReq accesses 132111138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses 132211138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses 132311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.207560 # miss rate for ReadExReq accesses 132411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.207560 # miss rate for ReadExReq accesses 132511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005633 # miss rate for ReadCleanReq accesses 132611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005633 # miss rate for ReadCleanReq accesses 132711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040346 # miss rate for ReadSharedReq accesses 132811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040346 # miss rate for ReadSharedReq accesses 132911138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.409431 # miss rate for InvalidateReq accesses 133011138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.409431 # miss rate for InvalidateReq accesses 133111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004742 # miss rate for demand accesses 133211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.012225 # miss rate for demand accesses 133311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005633 # miss rate for demand accesses 133411138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.079228 # miss rate for demand accesses 133511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.031107 # miss rate for demand accesses 133611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004742 # miss rate for overall accesses 133711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.012225 # miss rate for overall accesses 133811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005633 # miss rate for overall accesses 133911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.079228 # miss rate for overall accesses 134011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.031107 # miss rate for overall accesses 134111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139110.574342 # average ReadReq miss latency 134211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138106.821282 # average ReadReq miss latency 134311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 138612.839940 # average ReadReq miss latency 134411138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41651.518236 # average UpgradeReq miss latency 134511138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41651.518236 # average UpgradeReq miss latency 134610892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency 134710892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency 134811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139127.304187 # average ReadExReq miss latency 134911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 139127.304187 # average ReadExReq miss latency 135011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134571.716553 # average ReadCleanReq miss latency 135111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134571.716553 # average ReadCleanReq miss latency 135211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139273.279483 # average ReadSharedReq miss latency 135311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139273.279483 # average ReadSharedReq miss latency 135411138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155142.032882 # average InvalidateReq miss latency 135511138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155142.032882 # average InvalidateReq miss latency 135611138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139110.574342 # average overall miss latency 135711138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138106.821282 # average overall miss latency 135811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134571.716553 # average overall miss latency 135911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 139184.354927 # average overall miss latency 136011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 138668.871751 # average overall miss latency 136111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139110.574342 # average overall miss latency 136211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138106.821282 # average overall miss latency 136311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134571.716553 # average overall miss latency 136411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 139184.354927 # average overall miss latency 136511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 138668.871751 # average overall miss latency 136610585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 136810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 136910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 137010585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 137110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 137210585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 137310585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 137411138Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 986586 # number of writebacks 137511138Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 986586 # number of writebacks 137611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 19 # number of ReadSharedReq MSHR hits 137711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 19 # number of ReadSharedReq MSHR hits 137811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits 137911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits 138011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits 138111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits 138211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3726 # number of ReadReq MSHR misses 138311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3665 # number of ReadReq MSHR misses 138411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 7391 # number of ReadReq MSHR misses 138511138Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1049 # number of CleanEvict MSHR misses 138611138Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 1049 # number of CleanEvict MSHR misses 138711138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34382 # number of UpgradeReq MSHR misses 138811138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 34382 # number of UpgradeReq MSHR misses 138910726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 139010726Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 139111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 411208 # number of ReadExReq MSHR misses 139211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 411208 # number of ReadExReq MSHR misses 139311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 84827 # number of ReadCleanReq MSHR misses 139411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 84827 # number of ReadCleanReq MSHR misses 139511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 263797 # number of ReadSharedReq MSHR misses 139611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 263797 # number of ReadSharedReq MSHR misses 139711138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 502095 # number of InvalidateReq MSHR misses 139811138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::total 502095 # number of InvalidateReq MSHR misses 139911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3726 # number of demand (read+write) MSHR misses 140011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3665 # number of demand (read+write) MSHR misses 140111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 84827 # number of demand (read+write) MSHR misses 140211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 675005 # number of demand (read+write) MSHR misses 140311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 767223 # number of demand (read+write) MSHR misses 140411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3726 # number of overall MSHR misses 140511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3665 # number of overall MSHR misses 140611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 84827 # number of overall MSHR misses 140711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 675005 # number of overall MSHR misses 140811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 767223 # number of overall MSHR misses 140910827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable 141011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 141111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 54973 # number of ReadReq MSHR uncacheable 141211138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 141311138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 141410827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses 141511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 141611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 88669 # number of overall MSHR uncacheable misses 141711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 481066000 # number of ReadReq MSHR miss cycles 141811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 469511500 # number of ReadReq MSHR miss cycles 141911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 950577500 # number of ReadReq MSHR miss cycles 142011138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2432996000 # number of UpgradeReq MSHR miss cycles 142111138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2432996000 # number of UpgradeReq MSHR miss cycles 142211138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212000 # number of SCUpgradeReq MSHR miss cycles 142311138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212000 # number of SCUpgradeReq MSHR miss cycles 142411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53098180500 # number of ReadExReq MSHR miss cycles 142511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53098180500 # number of ReadExReq MSHR miss cycles 142611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10567045000 # number of ReadCleanReq MSHR miss cycles 142711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10567045000 # number of ReadCleanReq MSHR miss cycles 142811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34102496000 # number of ReadSharedReq MSHR miss cycles 142911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34102496000 # number of ReadSharedReq MSHR miss cycles 143011138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 72875089000 # number of InvalidateReq MSHR miss cycles 143111138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 72875089000 # number of InvalidateReq MSHR miss cycles 143211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 481066000 # number of demand (read+write) MSHR miss cycles 143311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 469511500 # number of demand (read+write) MSHR miss cycles 143411138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10567045000 # number of demand (read+write) MSHR miss cycles 143511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87200676500 # number of demand (read+write) MSHR miss cycles 143611138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 98718299000 # number of demand (read+write) MSHR miss cycles 143711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 481066000 # number of overall MSHR miss cycles 143811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 469511500 # number of overall MSHR miss cycles 143911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10567045000 # number of overall MSHR miss cycles 144011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87200676500 # number of overall MSHR miss cycles 144111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 98718299000 # number of overall MSHR miss cycles 144211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418306500 # number of ReadReq MSHR uncacheable cycles 144311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5408329500 # number of ReadReq MSHR uncacheable cycles 144411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7826636000 # number of ReadReq MSHR uncacheable cycles 144511138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5444664000 # number of WriteReq MSHR uncacheable cycles 144611138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5444664000 # number of WriteReq MSHR uncacheable cycles 144711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418306500 # number of overall MSHR uncacheable cycles 144811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10852993500 # number of overall MSHR uncacheable cycles 144911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 13271300000 # number of overall MSHR uncacheable cycles 145011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for ReadReq accesses 145111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for ReadReq accesses 145211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006808 # mshr miss rate for ReadReq accesses 145310892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 145410892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 145511138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785587 # mshr miss rate for UpgradeReq accesses 145611138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785587 # mshr miss rate for UpgradeReq accesses 145711138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses 145811138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses 145911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207560 # mshr miss rate for ReadExReq accesses 146011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207560 # mshr miss rate for ReadExReq accesses 146111138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for ReadCleanReq accesses 146211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005633 # mshr miss rate for ReadCleanReq accesses 146311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040343 # mshr miss rate for ReadSharedReq accesses 146411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040343 # mshr miss rate for ReadSharedReq accesses 146511138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.409431 # mshr miss rate for InvalidateReq accesses 146611138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.409431 # mshr miss rate for InvalidateReq accesses 146711138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for demand accesses 146811138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for demand accesses 146911138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for demand accesses 147011138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for demand accesses 147111138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.031106 # mshr miss rate for demand accesses 147211138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for overall accesses 147311138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for overall accesses 147411138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for overall accesses 147511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for overall accesses 147611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.031106 # mshr miss rate for overall accesses 147711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average ReadReq mshr miss latency 147811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average ReadReq mshr miss latency 147911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128612.839940 # average ReadReq mshr miss latency 148011138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70763.655401 # average UpgradeReq mshr miss latency 148111138Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70763.655401 # average UpgradeReq mshr miss latency 148211138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency 148311138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency 148411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129127.304187 # average ReadExReq mshr miss latency 148511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129127.304187 # average ReadExReq mshr miss latency 148611138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124571.716553 # average ReadCleanReq mshr miss latency 148711138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124571.716553 # average ReadCleanReq mshr miss latency 148811138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129275.526257 # average ReadSharedReq mshr miss latency 148911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129275.526257 # average ReadSharedReq mshr miss latency 149011138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145142.032882 # average InvalidateReq mshr miss latency 149111138Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145142.032882 # average InvalidateReq mshr miss latency 149211138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency 149311138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency 149411138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency 149511138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency 149611138Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency 149711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency 149811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency 149911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency 150011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency 150111138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency 150211138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency 150311138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160589.390700 # average ReadReq mshr uncacheable latency 150411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142372.364615 # average ReadReq mshr uncacheable latency 150511138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161581.908832 # average WriteReq mshr uncacheable latency 150611138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161581.908832 # average WriteReq mshr uncacheable latency 150711138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency 150811138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161085.782349 # average overall mshr uncacheable latency 150911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149672.377043 # average overall mshr uncacheable latency 151010585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 151111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 50352882 # Total number of requests made to the snoop filter. 151211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 25547569 # Number of requests hitting in the snoop filter with a single holder of the requested data. 151311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 3505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 151411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. 151511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 151611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 151711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 1630756 # Transaction distribution 151811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 23229377 # Transaction distribution 151911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution 152011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution 152111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 8639097 # Transaction distribution 152211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 17453404 # Transaction distribution 152311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 43769 # Transaction distribution 152411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 152511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution 152611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1981151 # Transaction distribution 152711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1981151 # Transaction distribution 152811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 15059021 # Transaction distribution 152911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 6547690 # Transaction distribution 153011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1332988 # Transaction distribution 153111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1226324 # Transaction distribution 153211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45216170 # Packet count per connected master and slave (bytes) 153311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29460715 # Packet count per connected master and slave (bytes) 153411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728722 # Packet count per connected master and slave (bytes) 153511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1932656 # Packet count per connected master and slave (bytes) 153611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 77338263 # Packet count per connected master and slave (bytes) 153711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964104688 # Cumulative packet size per connected master and slave (bytes) 153811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1028452958 # Cumulative packet size per connected master and slave (bytes) 153911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2398344 # Cumulative packet size per connected master and slave (bytes) 154011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6286416 # Cumulative packet size per connected master and slave (bytes) 154111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 2001242406 # Cumulative packet size per connected master and slave (bytes) 154211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 1898399 # Total snoops (count) 154311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 52724879 # Request fanout histogram 154411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.013444 # Request fanout histogram 154511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.115165 # Request fanout histogram 154610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 154711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 52016056 98.66% 98.66% # Request fanout histogram 154811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 708823 1.34% 100.00% # Request fanout histogram 154911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 155010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 155111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 155211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 155311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 52724879 # Request fanout histogram 155411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 33221521499 # Layer occupancy (ticks) 155510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 155611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1449383 # Layer occupancy (ticks) 155710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 155811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 22617176752 # Layer occupancy (ticks) 155910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 156011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 13467693225 # Layer occupancy (ticks) 156110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 156211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 429237366 # Layer occupancy (ticks) 156310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 156411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1147199772 # Layer occupancy (ticks) 156510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 156611103Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadReq 40298 # Transaction distribution 156711103Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadResp 40298 # Transaction distribution 156810892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 156910892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136571 # Transaction distribution 157010726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 157110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 157210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 157310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 157410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 157510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 157610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 157710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 157810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 157910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 158010892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 158110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 158210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 158310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 158410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 158510892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 158611103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) 158711103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) 158810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 158910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 159011103Snilay@cs.wisc.edusystem.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes) 159110726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 159210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 159310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 159410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 159510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 159610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 159710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 159810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 159910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 160010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 160110892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 160210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 160310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 160410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 160510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 160610892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 160711103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 160811103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) 160910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 161010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 161111103Snilay@cs.wisc.edusystem.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) 161210726Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 161310585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 161410585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 161510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 161610585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 161710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 161810585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 161910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 162010585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 162110585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 162210585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 162310585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 162410585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 162510585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 162610585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 162710585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 162810585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 162910585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 163010585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 163110585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 163210892Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 163310585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 163410585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 163510585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 163610585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 163710585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 163810585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 163910585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 164011138Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 565777121 # Layer occupancy (ticks) 164110585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 164210585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 164310585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 164410892Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 164510585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 164611103Snilay@cs.wisc.edusystem.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks) 164710585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 164810892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 164910585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 165011103Snilay@cs.wisc.edusystem.iocache.tags.replacements 115458 # number of replacements 165111138Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.417924 # Cycle average of tags in use 165210585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 165311103Snilay@cs.wisc.edusystem.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. 165410585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 165511138Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13103107119000 # Cycle when the warmup percentage was hit. 165611138Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.546641 # Average occupied blocks per requestor 165711138Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.871282 # Average occupied blocks per requestor 165811138Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.221665 # Average percentage of cache occupancy 165911138Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.429455 # Average percentage of cache occupancy 166011138Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.651120 # Average percentage of cache occupancy 166110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 166210585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 166310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 166411103Snilay@cs.wisc.edusystem.iocache.tags.tag_accesses 1039650 # Number of tag accesses 166511103Snilay@cs.wisc.edusystem.iocache.tags.data_accesses 1039650 # Number of data accesses 166610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 166711103Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 166811103Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 166910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 167010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 167110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 167210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 167310585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 167411103Snilay@cs.wisc.edusystem.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses 167511103Snilay@cs.wisc.edusystem.iocache.demand_misses::total 8853 # number of demand (read+write) misses 167610585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 167711103Snilay@cs.wisc.edusystem.iocache.overall_misses::realview.ide 8813 # number of overall misses 167811103Snilay@cs.wisc.edusystem.iocache.overall_misses::total 8853 # number of overall misses 167911138Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5101000 # number of ReadReq miss cycles 168011138Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1670573105 # number of ReadReq miss cycles 168111138Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1675674105 # number of ReadReq miss cycles 168210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 168310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 168411138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13828326016 # number of WriteLineReq miss cycles 168511138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13828326016 # number of WriteLineReq miss cycles 168611138Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5452000 # number of demand (read+write) miss cycles 168711138Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1670573105 # number of demand (read+write) miss cycles 168811138Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1676025105 # number of demand (read+write) miss cycles 168911138Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5452000 # number of overall miss cycles 169011138Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1670573105 # number of overall miss cycles 169111138Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1676025105 # number of overall miss cycles 169210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 169311103Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) 169411103Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) 169510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 169610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 169710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 169810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 169910585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 170011103Snilay@cs.wisc.edusystem.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses 170111103Snilay@cs.wisc.edusystem.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses 170210585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 170311103Snilay@cs.wisc.edusystem.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses 170411103Snilay@cs.wisc.edusystem.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses 170510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 170610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 170710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 170810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 170910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 171010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 171110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 171210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 171310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 171410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 171510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 171610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 171710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 171811138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137864.864865 # average ReadReq miss latency 171911138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 189557.824237 # average ReadReq miss latency 172011138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 189341.706780 # average ReadReq miss latency 172110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 172210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 172311138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 129643.797495 # average WriteLineReq miss latency 172411138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 129643.797495 # average WriteLineReq miss latency 172511138Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 136300 # average overall miss latency 172611138Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency 172711138Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 189317.192477 # average overall miss latency 172811138Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 136300 # average overall miss latency 172911138Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency 173011138Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 189317.192477 # average overall miss latency 173111138Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 34546 # number of cycles access was blocked 173210585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173311138Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3397 # number of cycles access was blocked 173410585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 173511138Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 10.169561 # average number of cycles each access was blocked 173610585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 173710585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 173810585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 173910726Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106630 # number of writebacks 174010726Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106630 # number of writebacks 174110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 174211103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses 174311103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses 174410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 174510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 174610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 174710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 174810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 174911103Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses 175011103Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses 175110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 175211103Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses 175311103Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses 175411138Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3251000 # number of ReadReq MSHR miss cycles 175511138Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1229923105 # number of ReadReq MSHR miss cycles 175611138Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1233174105 # number of ReadReq MSHR miss cycles 175710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 175810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 175911138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8495126016 # number of WriteLineReq MSHR miss cycles 176011138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8495126016 # number of WriteLineReq MSHR miss cycles 176111138Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3452000 # number of demand (read+write) MSHR miss cycles 176211138Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1229923105 # number of demand (read+write) MSHR miss cycles 176311138Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1233375105 # number of demand (read+write) MSHR miss cycles 176411138Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3452000 # number of overall MSHR miss cycles 176511138Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1229923105 # number of overall MSHR miss cycles 176611138Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1233375105 # number of overall MSHR miss cycles 176710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 176810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 176910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 177010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 177110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 177210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 177310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 177410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 177510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 177610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 177710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 177810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 177910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 178011138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87864.864865 # average ReadReq mshr miss latency 178111138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139557.824237 # average ReadReq mshr miss latency 178211138Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 139341.706780 # average ReadReq mshr miss latency 178310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 178410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 178511138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79643.797495 # average WriteLineReq mshr miss latency 178611138Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 79643.797495 # average WriteLineReq mshr miss latency 178711138Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency 178811138Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency 178911138Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency 179011138Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency 179111138Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency 179211138Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency 179310585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 179411138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 54973 # Transaction distribution 179511138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 419838 # Transaction distribution 179611138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33696 # Transaction distribution 179711138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33696 # Transaction distribution 179811138Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1093216 # Transaction distribution 179911138Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 195829 # Transaction distribution 180011138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 35178 # Transaction distribution 180110726Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 180211138Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 35181 # Transaction distribution 180311138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 912510 # Transaction distribution 180411138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 912510 # Transaction distribution 180511138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 364865 # Transaction distribution 180610892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 180710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 180810892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 180910515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) 181011138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) 181111138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3830691 # Packet count per connected master and slave (bytes) 181211138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3960313 # Packet count per connected master and slave (bytes) 181311138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341363 # Packet count per connected master and slave (bytes) 181411138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 341363 # Packet count per connected master and slave (bytes) 181511138Sandreas.hansson@arm.comsystem.membus.pkt_count::total 4301676 # Packet count per connected master and slave (bytes) 181610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 181710515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) 181811138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) 181911138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144645964 # Cumulative packet size per connected master and slave (bytes) 182011138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 144815950 # Cumulative packet size per connected master and slave (bytes) 182111138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232000 # Cumulative packet size per connected master and slave (bytes) 182211138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7232000 # Cumulative packet size per connected master and slave (bytes) 182311138Sandreas.hansson@arm.comsystem.membus.pkt_size::total 152047950 # Cumulative packet size per connected master and slave (bytes) 182411138Sandreas.hansson@arm.comsystem.membus.snoops 3147 # Total snoops (count) 182511138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2799608 # Request fanout histogram 182610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 182710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 182810515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 182910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 183011138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2799608 100.00% 100.00% # Request fanout histogram 183110515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 183210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 183310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 183410515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 183511138Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2799608 # Request fanout histogram 183611138Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 104476500 # Layer occupancy (ticks) 183710515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 183810726Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) 183910515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 184011138Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 5464500 # Layer occupancy (ticks) 184110515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 184211138Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 7417701934 # Layer occupancy (ticks) 184310585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 184411138Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 6905958013 # Layer occupancy (ticks) 184510515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 184611138Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 228360981 # Layer occupancy (ticks) 184710515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 184810515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 184910515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 185010515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 185110515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 185210515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 185310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 185410515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 185510515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 185610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 185711138Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 185810515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 185910515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 186010515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 186111138Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 186210515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 186310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 186410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 186510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 186610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 186710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 186810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 186910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 187010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 187110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 187210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 187310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 187410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 187510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 187610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 187710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 187810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 187910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 188010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 188110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 188210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 188310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 188410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 188510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 188610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 188710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 188810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 188910515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 189011103Snilay@cs.wisc.edusystem.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 189111014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 189211014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 189311014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 189411014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 189511014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 189611014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 189711014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 189811014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 189911014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 190010515SAli.Saidi@ARM.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 190111138Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 19016 # number of quiesce instructions executed 190210515SAli.Saidi@ARM.com 190310515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1904