stats.txt revision 10628
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310628Sandreas.hansson@arm.comsim_seconds 51.320647 # Number of seconds simulated 410628Sandreas.hansson@arm.comsim_ticks 51320647066500 # Number of ticks simulated 510628Sandreas.hansson@arm.comfinal_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 114690 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 134762 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 6864170011 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 721888 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 7476.60 # Real time elapsed on the host 1210628Sandreas.hansson@arm.comsim_insts 857487967 # Number of instructions simulated 1310628Sandreas.hansson@arm.comsim_ops 1007562352 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory 1710628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory 1810628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory 1910628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory 2010628Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory 2110628Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 49637032 # Number of bytes read from this memory 2210628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory 2310628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory 2410628Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory 2510585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2610628Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 69739044 # Number of bytes written to this memory 2710628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory 2810628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory 2910628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory 3010628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory 3110628Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory 3210628Sandreas.hansson@arm.comsystem.physmem.num_reads::total 791544 # Number of read requests responded to by this memory 3310628Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory 3410585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3510628Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory 3610628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) 3710628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) 3810628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) 3910628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) 4010628Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) 4110628Sandreas.hansson@arm.comsystem.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) 4210628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) 4310628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) 4410628Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) 4510585Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) 4610628Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) 4710628Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) 4810628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) 4910628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) 5010628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) 5110628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) 5210628Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) 5310628Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) 5410628Sandreas.hansson@arm.comsystem.physmem.readReqs 791544 # Number of read requests accepted 5510628Sandreas.hansson@arm.comsystem.physmem.writeReqs 1694292 # Number of write requests accepted 5610628Sandreas.hansson@arm.comsystem.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue 5710628Sandreas.hansson@arm.comsystem.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue 5810628Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM 5910628Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue 6010628Sandreas.hansson@arm.comsystem.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM 6110628Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side 6210628Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side 6310628Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue 6410628Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one 6510628Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write 6610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 48315 # Per bank write bursts 6710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 50150 # Per bank write bursts 6810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 46175 # Per bank write bursts 6910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 46946 # Per bank write bursts 7010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 45323 # Per bank write bursts 7110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 52981 # Per bank write bursts 7210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 47646 # Per bank write bursts 7310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 48748 # Per bank write bursts 7410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 44337 # Per bank write bursts 7510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 72322 # Per bank write bursts 7610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 50834 # Per bank write bursts 7710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 50772 # Per bank write bursts 7810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 48451 # Per bank write bursts 7910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 47387 # Per bank write bursts 8010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 44232 # Per bank write bursts 8110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 46363 # Per bank write bursts 8210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 103979 # Per bank write bursts 8310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 105038 # Per bank write bursts 8410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 105754 # Per bank write bursts 8510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 105161 # Per bank write bursts 8610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 103562 # Per bank write bursts 8710628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 108435 # Per bank write bursts 8810628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 103867 # Per bank write bursts 8910628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 105467 # Per bank write bursts 9010628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 102645 # Per bank write bursts 9110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 108407 # Per bank write bursts 9210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 108582 # Per bank write bursts 9310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 107982 # Per bank write bursts 9410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 105330 # Per bank write bursts 9510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 105345 # Per bank write bursts 9610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 103911 # Per bank write bursts 9710628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 104029 # Per bank write bursts 9810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9910628Sandreas.hansson@arm.comsystem.physmem.numWrRetry 30 # Number of times write queue was full causing retry 10010628Sandreas.hansson@arm.comsystem.physmem.totGap 51320645833500 # Total gap between requests 10110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 21272 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10710628Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 770259 # Read request sizes (log2) 10810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11410628Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1691719 # Write request sizes (log2) 11510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see 11610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see 11710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see 11810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see 11910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see 12010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see 12110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see 12210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see 12310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see 12410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see 12510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see 12610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see 12710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see 12810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see 12910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see 13010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see 13110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see 13210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see 13310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see 13410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see 13510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 13610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 13710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see 16310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see 16410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see 16510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see 16610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see 16710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see 16810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see 16910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see 17010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see 17110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see 17210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see 17310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see 17410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see 17510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see 17610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see 17710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see 17810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see 17910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see 18010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see 18110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 3795 # What write queue length does an incoming req see 18210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 3522 # What write queue length does an incoming req see 18310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 3348 # What write queue length does an incoming req see 18410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 3077 # What write queue length does an incoming req see 18510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 3049 # What write queue length does an incoming req see 18610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2918 # What write queue length does an incoming req see 18710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 2900 # What write queue length does an incoming req see 18810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 2759 # What write queue length does an incoming req see 18910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 2637 # What write queue length does an incoming req see 19010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 2554 # What write queue length does an incoming req see 19110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 2529 # What write queue length does an incoming req see 19210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 2364 # What write queue length does an incoming req see 19310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see 19410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see 19510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see 19610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see 19710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see 19810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see 19910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see 20010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see 20110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see 20210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see 20310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see 20410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see 20510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see 20610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see 20710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see 20810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see 20910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see 21010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see 21110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation 21210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation 21310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation 21410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation 21510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation 21610628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation 21710628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation 21810628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation 21910628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation 22010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation 22110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation 22210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation 22310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation 22410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation 22510628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes 22610628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes 22710628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes 22810628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes 22910628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes 23010585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 23110585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 23210628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes 23310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads 23410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads 23510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads 23610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads 23710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads 23810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads 23910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads 24010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads 24110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads 24210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads 24310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads 24410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads 24510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads 24610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads 24710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads 24810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads 24910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads 25010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads 25110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads 25210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads 25310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads 25410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads 25510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads 25610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads 25710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads 25810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads 25910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads 26010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads 26110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads 26210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads 26310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads 26410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads 26510585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads 26610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads 26710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads 26810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads 26910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads 27010628Sandreas.hansson@arm.comsystem.physmem.totQLat 15484448260 # Total ticks spent queuing 27110628Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM 27210628Sandreas.hansson@arm.comsystem.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers 27310628Sandreas.hansson@arm.comsystem.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst 27410515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27510628Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst 27610585Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s 27710628Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s 27810585Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s 27910585Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s 28010515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28110585Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 28210585Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 28310585Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 28410585Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 28510628Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing 28610628Sandreas.hansson@arm.comsystem.physmem.readRowHits 603455 # Number of row buffer hits during reads 28710628Sandreas.hansson@arm.comsystem.physmem.writeRowHits 1355453 # Number of row buffer hits during writes 28810628Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads 28910628Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes 29010628Sandreas.hansson@arm.comsystem.physmem.avgGap 20645225.93 # Average gap between requests 29110585Sandreas.hansson@arm.comsystem.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined 29210628Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) 29310628Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) 29410628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) 29510628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) 29610628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) 29710628Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) 29810628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) 29910628Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) 30010628Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.473889 # Core power per rank (mW) 30110628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states 30210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states 30310628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30410628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states 30510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30610628Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) 30710628Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) 30810628Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) 30910628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) 31010628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) 31110628Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) 31210628Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) 31310628Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) 31410628Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.480369 # Core power per rank (mW) 31510628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states 31610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states 31710628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 31810628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states 31910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 32010585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory 32110585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 32210585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory 32310585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory 32410585Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory 32510585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory 32610585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 32710585Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory 32810585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 32910585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 33010585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 33110585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 33210585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 33310585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 33410585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 33510585Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 33610585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 33710585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 33810585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 33910585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 34010585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 34110585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 34210628Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 226505876 # Number of BP lookups 34310628Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted 34410628Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect 34510628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups 34610628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 104610641 # Number of BTB hits 34710585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 34810628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage 34910628Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. 35010628Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. 35110585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 35210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 37810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 37910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 38010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 931379 # Table walker walks requested 38210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors 38310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate 38410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate 38510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting 38610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency 38710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency 38810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency 38910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency 39010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency 39110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency 39210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency 39310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency 39410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency 39510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency 39610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency 39710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency 39810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency 39910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency 40010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency 40110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency 40210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 40310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency 40410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency 40510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency 40610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency 40710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency 40810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency 40910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency 41010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency 41110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency 41210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency 41310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency 41410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 41510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency 41610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 41710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency 41810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution 41910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution 42010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution 42110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution 42210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution 42310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution 42410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution 42510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution 42610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution 42710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution 42810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution 42910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution 43010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution 43110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated 43210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated 43310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated 43410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst 43510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst 43710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst 43810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 43910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst 44010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst 44110585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 44210585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 44310628Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 171278986 # DTB read hits 44410628Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 671795 # DTB read misses 44510628Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 149102166 # DTB write hits 44610628Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 259584 # DTB write misses 44710585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 44810585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 44910585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID 45010585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID 45110628Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB 45210628Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions 45310628Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch 45410585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 45510628Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions 45610628Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 171950781 # DTB read accesses 45710628Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 149361750 # DTB write accesses 45810585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 45910628Sandreas.hansson@arm.comsystem.cpu.dtb.hits 320381152 # DTB hits 46010628Sandreas.hansson@arm.comsystem.cpu.dtb.misses 931379 # DTB misses 46110628Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 321312531 # DTB accesses 46210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 46310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 46410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 46710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 47110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 47210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 47410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 47710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 47910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 48010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 48110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 48210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 48310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 48410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 48510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 48610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 48710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 48810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 48910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 49010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 49110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 161841 # Table walker walks requested 49210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors 49310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate 49410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate 49510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting 49610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency 49710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency 49810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency 49910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency 50010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency 50110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency 50210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency 50310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency 50410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency 50510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency 50610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 50710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency 50810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 50910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 51010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 51110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency 51210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency 51310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency 51410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency 51510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency 51610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency 51710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency 51810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency 51910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency 52010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency 52110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency 52210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency 52310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency 52410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency 52510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 52610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 52710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 52810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency 53110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution 53210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution 53310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution 53410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution 53510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution 53610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution 53710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution 53810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution 53910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated 54010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated 54110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated 54210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst 54410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst 54510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst 54710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst 54810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst 54910628Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 360168043 # ITB inst hits 55010628Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 161841 # ITB inst misses 55110585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 55210585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 55310585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 55410585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 55510585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 55610585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55710585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID 55810585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID 55910628Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB 56010585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56110585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 56210585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56310628Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions 56410585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 56510585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 56610628Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 360329884 # ITB inst accesses 56710628Sandreas.hansson@arm.comsystem.cpu.itb.hits 360168043 # DTB hits 56810628Sandreas.hansson@arm.comsystem.cpu.itb.misses 161841 # DTB misses 56910628Sandreas.hansson@arm.comsystem.cpu.itb.accesses 360329884 # DTB accesses 57010628Sandreas.hansson@arm.comsystem.cpu.numCycles 1576983833 # number of cpu cycles simulated 57110585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57210585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 57310628Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss 57410628Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed 57510628Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered 57610628Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken 57710628Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked 57810628Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing 57910628Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb 58010628Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 58110628Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps 58210628Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions 58310628Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR 58410628Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched 58510628Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed 58610628Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed 58710628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) 58810628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) 58910628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) 59010585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 59110628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) 59210628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) 59310628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) 59410628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) 59510585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 59610585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 59710585Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 59810628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) 59910628Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle 60010628Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle 60110628Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle 60210628Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked 60310628Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 436470729 # Number of cycles decode is running 60410628Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking 60510628Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing 60610628Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch 60710628Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction 60810628Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode 60910628Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode 61010628Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing 61110628Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle 61210628Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking 61310628Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst 61410628Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 442135288 # Number of cycles rename is running 61510628Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking 61610628Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename 61710628Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename 61810628Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full 61910628Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full 62010628Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full 62110628Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full 62210628Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers 62310628Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed 62410628Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made 62510628Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups 62610628Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups 62710628Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed 62810628Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing 62910628Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed 63010628Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed 63110628Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer 63210628Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. 63310628Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. 63410628Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. 63510628Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. 63610628Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) 63710628Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ 63810628Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued 63910628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued 64010628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling 64110628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph 64210628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed 64310628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle 64410628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle 64510628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle 64610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 64710628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle 64810628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle 64910628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle 65010628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle 65110628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle 65210628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle 65310585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 65410585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 65510585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 65610585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 65710585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 65810585Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 65910628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle 66010585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 66110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available 66210628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available 66310628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available 66410585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available 66510585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available 66610585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available 66710585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available 66810585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available 66910585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available 67010585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available 67110585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available 67210585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available 67310585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available 67410585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available 67510585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available 67610585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available 67710585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available 67810585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available 67910585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available 68010585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available 68110585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available 68210585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available 68310585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available 68410585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available 68510585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available 68610628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available 68710628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available 68810628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available 68910628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available 69010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available 69110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available 69210585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 69310585Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 69410628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued 69510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued 69610628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued 69710628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued 69810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued 69910585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued 70010585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued 70110585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued 70210585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued 70310585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued 70410585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued 70510585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued 70610585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued 70710585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued 70810585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued 70910585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued 71010585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued 71110585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued 71210585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued 71310585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued 71410585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued 71510585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued 71610585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued 71710585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued 71810585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued 71910585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued 72010628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued 72110585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued 72210585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued 72310585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued 72410628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued 72510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued 72610585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 72710585Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 72810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued 72910628Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.670005 # Inst issue rate 73010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested 73110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) 73210628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads 73310628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes 73410628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses 73510628Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads 73610628Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes 73710628Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses 73810628Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses 73910628Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses 74010628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores 74110585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 74210628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed 74310628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed 74410628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations 74510628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed 74610585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 74710585Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 74810628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled 74910628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked 75010585Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 75110628Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing 75210628Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking 75310628Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking 75410628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ 75510585Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 75610628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions 75710628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions 75810628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions 75910628Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall 76010628Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall 76110628Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations 76210628Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly 76310628Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly 76410628Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute 76510628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions 76610628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed 76710628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute 76810585Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 76910628Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 224348 # number of nop insts executed 77010628Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 320367802 # number of memory reference insts executed 77110628Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 198404489 # Number of branches executed 77210628Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 149099070 # Number of stores executed 77310628Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.662897 # Inst execution rate 77410628Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit 77510628Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back 77610628Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 442335874 # num instructions producing a value 77710628Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 715873221 # num instructions consuming a value 77810585Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 77910628Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.659130 # insts written-back per cycle 78010628Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back 78110585Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 78210628Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit 78310628Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards 78410628Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted 78510628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle 78610628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle 78710628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle 78810585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 78910628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle 79010628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle 79110628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle 79210628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle 79310628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle 79410628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle 79510628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle 79610628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle 79710628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle 79810585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 79910585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 80010585Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 80110628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle 80210628Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 857487967 # Number of instructions committed 80310628Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed 80410585Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 80510628Sandreas.hansson@arm.comsystem.cpu.commit.refs 307720812 # Number of memory references committed 80610628Sandreas.hansson@arm.comsystem.cpu.commit.loads 161382253 # Number of loads committed 80710628Sandreas.hansson@arm.comsystem.cpu.commit.membars 7017472 # Number of memory barriers committed 80810628Sandreas.hansson@arm.comsystem.cpu.commit.branches 191417503 # Number of branches committed 80910628Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. 81010628Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 925548459 # Number of committed integer instructions. 81110628Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 25509836 # Number of function calls committed. 81210585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 81310628Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction 81410628Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction 81510628Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction 81610585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction 81710585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction 81810585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction 81910585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction 82010585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction 82110585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction 82210585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction 82310585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction 82410585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction 82510585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction 82610585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction 82710585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction 82810585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction 82910585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction 83010585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction 83110585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction 83210585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction 83310585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction 83410585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction 83510585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction 83610585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction 83710585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction 83810585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction 83910585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction 84010585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 84110585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 84210628Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction 84310628Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction 84410585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 84510585Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 84610628Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction 84710628Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached 84810585Sandreas.hansson@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 84910628Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 2555751551 # The number of ROB reads 85010628Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 2129995502 # The number of ROB writes 85110628Sandreas.hansson@arm.comsystem.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself 85210628Sandreas.hansson@arm.comsystem.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling 85310628Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 85410628Sandreas.hansson@arm.comsystem.cpu.committedInsts 857487967 # Number of Instructions Simulated 85510628Sandreas.hansson@arm.comsystem.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated 85610628Sandreas.hansson@arm.comsystem.cpu.cpi 1.839074 # CPI: Cycles Per Instruction 85710628Sandreas.hansson@arm.comsystem.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads 85810628Sandreas.hansson@arm.comsystem.cpu.ipc 0.543752 # IPC: Instructions Per Cycle 85910628Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads 86010628Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 1237547063 # number of integer regfile reads 86110628Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 738733043 # number of integer regfile writes 86210628Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 1457540 # number of floating regfile reads 86310628Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 782548 # number of floating regfile writes 86410628Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 228190122 # number of cc regfile reads 86510628Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 228796042 # number of cc regfile writes 86610628Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads 86710628Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 27489325 # number of misc regfile writes 86810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 9822587 # number of replacements 86910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use 87010628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. 87110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. 87210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. 87310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. 87410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor 87510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy 87610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy 87710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 87810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 87910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id 88010628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id 88110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses 88310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses 88410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits 88510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits 88610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits 88710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits 88810628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits 88910628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits 89010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits 89110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits 89210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits 89310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits 89410628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3751270 # number of StoreCondReq hits 89510628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3751270 # number of StoreCondReq hits 89610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 278328901 # number of demand (read+write) hits 89710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 278328901 # number of demand (read+write) hits 89810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 278710234 # number of overall hits 89910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 278710234 # number of overall hits 90010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses 90110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses 90210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses 90310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses 90410628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses 90510628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses 90610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses 90710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses 90810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses 90910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses 91010585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 91110585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 91210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses 91310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses 91410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses 91510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 22162626 # number of overall misses 91610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles 91710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles 91810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles 91910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles 92010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38655244426 # number of WriteInvalidateReq miss cycles 92110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_latency::total 38655244426 # number of WriteInvalidateReq miss cycles 92210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6327424004 # number of LoadLockedReq miss cycles 92310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 6327424004 # number of LoadLockedReq miss cycles 92410585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles 92510585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles 92610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles 92710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles 92810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles 92910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles 93010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) 93110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) 93210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) 93310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) 93410628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) 93510628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses) 93610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses) 93710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses) 93810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses) 93910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses) 94010628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses) 94110628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses) 94210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses 94310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses 94410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses 94510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses 94610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses 94710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses 94810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses 94910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses 95010628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses 95110628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses 95210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses 95310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses 95410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses 95510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses 95610585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 95710585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 95810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses 95910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses 96010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses 96110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses 96210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency 96310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency 96410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency 96510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency 96610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency 96710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency 96810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency 96910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency 97010585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency 97110585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency 97210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency 97310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency 97410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency 97510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency 97610628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked 97710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97810628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked 97910585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 98010628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked 98110585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 98210585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 98310585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 98410628Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 7597183 # number of writebacks 98510628Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 7597183 # number of writebacks 98610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 4319062 # number of ReadReq MSHR hits 98710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 4319062 # number of ReadReq MSHR hits 98810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 9426489 # number of WriteReq MSHR hits 98910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 9426489 # number of WriteReq MSHR hits 99010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7148 # number of WriteInvalidateReq MSHR hits 99110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7148 # number of WriteInvalidateReq MSHR hits 99210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220034 # number of LoadLockedReq MSHR hits 99310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 220034 # number of LoadLockedReq MSHR hits 99410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 13745551 # number of demand (read+write) MSHR hits 99510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 13745551 # number of demand (read+write) MSHR hits 99610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 13745551 # number of overall MSHR hits 99710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 13745551 # number of overall MSHR hits 99810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5177976 # number of ReadReq MSHR misses 99910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 5177976 # number of ReadReq MSHR misses 100010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041958 # number of WriteReq MSHR misses 100110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2041958 # number of WriteReq MSHR misses 100210628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190352 # number of SoftPFReq MSHR misses 100310628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1190352 # number of SoftPFReq MSHR misses 100410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226180 # number of WriteInvalidateReq MSHR misses 100510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226180 # number of WriteInvalidateReq MSHR misses 100610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230589 # number of LoadLockedReq MSHR misses 100710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 230589 # number of LoadLockedReq MSHR misses 100810585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 100910585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 101010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 7219934 # number of demand (read+write) MSHR misses 101110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 7219934 # number of demand (read+write) MSHR misses 101210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 8410286 # number of overall MSHR misses 101310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 8410286 # number of overall MSHR misses 101410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70110899674 # number of ReadReq MSHR miss cycles 101510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 70110899674 # number of ReadReq MSHR miss cycles 101610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53589743024 # number of WriteReq MSHR miss cycles 101710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 53589743024 # number of WriteReq MSHR miss cycles 101810628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18780468745 # number of SoftPFReq MSHR miss cycles 101910628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18780468745 # number of SoftPFReq MSHR miss cycles 102010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35955294132 # number of WriteInvalidateReq MSHR miss cycles 102110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35955294132 # number of WriteInvalidateReq MSHR miss cycles 102210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles 102310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles 102410585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles 102510585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles 102610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles 102710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles 102810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles 102910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles 103010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles 103110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles 103210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles 103310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles 103410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles 103510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles 103610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses 103710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses 103810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses 103910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses 104010628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses 104110628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses 104210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses 104310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses 104410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses 104510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses 104610585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 104710585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 104810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses 104910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses 105010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses 105110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses 105210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency 105310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency 105410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency 105510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency 105610628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency 105710628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency 105810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency 105910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency 106010628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency 106110628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency 106210585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency 106310585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency 106410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency 106510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency 106610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency 106710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency 106810585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 106910585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 107010585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 107110585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 107210585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 107310585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 107410585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 107510628Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 15084162 # number of replacements 107610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.954207 # Cycle average of tags in use 107710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 343955623 # Total number of references to valid blocks. 107810628Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 15084674 # Sample count of references to valid blocks. 107910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 22.801661 # Average number of references to valid blocks. 108010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 14174936000 # Cycle when the warmup percentage was hit. 108110628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.954207 # Average occupied blocks per requestor 108210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy 108310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy 108410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 108510628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 108610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 108710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 108810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 108910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 374842526 # Number of tag accesses 109010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 374842526 # Number of data accesses 109110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 343955623 # number of ReadReq hits 109210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 343955623 # number of ReadReq hits 109310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 343955623 # number of demand (read+write) hits 109410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 343955623 # number of demand (read+write) hits 109510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 343955623 # number of overall hits 109610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 343955623 # number of overall hits 109710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 15802123 # number of ReadReq misses 109810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 15802123 # number of ReadReq misses 109910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 15802123 # number of demand (read+write) misses 110010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 15802123 # number of demand (read+write) misses 110110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 15802123 # number of overall misses 110210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 15802123 # number of overall misses 110310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846 # number of ReadReq miss cycles 110410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 208192919846 # number of ReadReq miss cycles 110510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 208192919846 # number of demand (read+write) miss cycles 110610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 208192919846 # number of demand (read+write) miss cycles 110710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 208192919846 # number of overall miss cycles 110810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 208192919846 # number of overall miss cycles 110910628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 359757746 # number of ReadReq accesses(hits+misses) 111010628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 359757746 # number of ReadReq accesses(hits+misses) 111110628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 359757746 # number of demand (read+write) accesses 111210628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 359757746 # number of demand (read+write) accesses 111310628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 359757746 # number of overall (read+write) accesses 111410628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 359757746 # number of overall (read+write) accesses 111510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043924 # miss rate for ReadReq accesses 111610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043924 # miss rate for ReadReq accesses 111710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043924 # miss rate for demand accesses 111810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.043924 # miss rate for demand accesses 111910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043924 # miss rate for overall accesses 112010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.043924 # miss rate for overall accesses 112110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793 # average ReadReq miss latency 112210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793 # average ReadReq miss latency 112310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency 112410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13174.996793 # average overall miss latency 112510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency 112610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13174.996793 # average overall miss latency 112710628Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 11061 # number of cycles access was blocked 112810585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 112910628Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 978 # number of cycles access was blocked 113010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 113110628Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 11.309816 # average number of cycles each access was blocked 113210585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 113310585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 113410585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 113510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 717343 # number of ReadReq MSHR hits 113610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 717343 # number of ReadReq MSHR hits 113710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 717343 # number of demand (read+write) MSHR hits 113810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 717343 # number of demand (read+write) MSHR hits 113910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 717343 # number of overall MSHR hits 114010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 717343 # number of overall MSHR hits 114110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 15084780 # number of ReadReq MSHR misses 114210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 15084780 # number of ReadReq MSHR misses 114310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 15084780 # number of demand (read+write) MSHR misses 114410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 15084780 # number of demand (read+write) MSHR misses 114510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 15084780 # number of overall MSHR misses 114610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 15084780 # number of overall MSHR misses 114710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171798629050 # number of ReadReq MSHR miss cycles 114810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 171798629050 # number of ReadReq MSHR miss cycles 114910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 171798629050 # number of demand (read+write) MSHR miss cycles 115010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 171798629050 # number of demand (read+write) MSHR miss cycles 115110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 171798629050 # number of overall MSHR miss cycles 115210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 171798629050 # number of overall MSHR miss cycles 115310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1412899000 # number of ReadReq MSHR uncacheable cycles 115410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1412899000 # number of ReadReq MSHR uncacheable cycles 115510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1412899000 # number of overall MSHR uncacheable cycles 115610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 1412899000 # number of overall MSHR uncacheable cycles 115710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for ReadReq accesses 115810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.041930 # mshr miss rate for ReadReq accesses 115910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for demand accesses 116010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.041930 # mshr miss rate for demand accesses 116110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for overall accesses 116210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.041930 # mshr miss rate for overall accesses 116310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032 # average ReadReq mshr miss latency 116410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11388.872032 # average ReadReq mshr miss latency 116510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency 116610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency 116710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency 116810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency 116910585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 117010585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 117110585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 117210585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 117310585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 117410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 1166252 # number of replacements 117510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65308.801684 # Cycle average of tags in use 117610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 29080427 # Total number of references to valid blocks. 117710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1229042 # Sample count of references to valid blocks. 117810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 23.661052 # Average number of references to valid blocks. 117910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 2430267000 # Cycle when the warmup percentage was hit. 118010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 37210.550558 # Average occupied blocks per requestor 118110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 324.848912 # Average occupied blocks per requestor 118210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 496.111863 # Average occupied blocks per requestor 118310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 7620.063188 # Average occupied blocks per requestor 118410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 19657.227164 # Average occupied blocks per requestor 118510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.567788 # Average percentage of cache occupancy 118610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004957 # Average percentage of cache occupancy 118710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007570 # Average percentage of cache occupancy 118810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.116273 # Average percentage of cache occupancy 118910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.299945 # Average percentage of cache occupancy 119010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996533 # Average percentage of cache occupancy 119110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id 119210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62489 # Occupied blocks per task id 119310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 119410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 300 # Occupied blocks per task id 119510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 119610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id 119710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2670 # Occupied blocks per task id 119810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5157 # Occupied blocks per task id 119910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id 120010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id 120110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.953506 # Percentage of cache occupancy per task id 120210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 273259305 # Number of tag accesses 120310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 273259305 # Number of data accesses 120410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 799874 # number of ReadReq hits 120510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299425 # number of ReadReq hits 120610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 15000245 # number of ReadReq hits 120710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 6339023 # number of ReadReq hits 120810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 22438567 # number of ReadReq hits 120910628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 7597183 # number of Writeback hits 121010628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 7597183 # number of Writeback hits 121110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730326 # number of WriteInvalidateReq hits 121210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_hits::total 730326 # number of WriteInvalidateReq hits 121310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 9466 # number of UpgradeReq hits 121410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 9466 # number of UpgradeReq hits 121510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 121610585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 121710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1583904 # number of ReadExReq hits 121810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1583904 # number of ReadExReq hits 121910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 799874 # number of demand (read+write) hits 122010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 299425 # number of demand (read+write) hits 122110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 15000245 # number of demand (read+write) hits 122210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 7922927 # number of demand (read+write) hits 122310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 24022471 # number of demand (read+write) hits 122410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 799874 # number of overall hits 122510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 299425 # number of overall hits 122610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 15000245 # number of overall hits 122710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 7922927 # number of overall hits 122810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 24022471 # number of overall hits 122910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3543 # number of ReadReq misses 123010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3208 # number of ReadReq misses 123110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 84445 # number of ReadReq misses 123210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 256196 # number of ReadReq misses 123310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 347392 # number of ReadReq misses 123410628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495854 # number of WriteInvalidateReq misses 123510628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_misses::total 495854 # number of WriteInvalidateReq misses 123610628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 34479 # number of UpgradeReq misses 123710628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 34479 # number of UpgradeReq misses 123810585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 123910585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 124010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 417812 # number of ReadExReq misses 124110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 417812 # number of ReadExReq misses 124210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 3543 # number of demand (read+write) misses 124310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 3208 # number of demand (read+write) misses 124410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 84445 # number of demand (read+write) misses 124510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 674008 # number of demand (read+write) misses 124610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 765204 # number of demand (read+write) misses 124710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 3543 # number of overall misses 124810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 3208 # number of overall misses 124910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 84445 # number of overall misses 125010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 674008 # number of overall misses 125110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 765204 # number of overall misses 125210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 284358999 # number of ReadReq miss cycles 125310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 261200750 # number of ReadReq miss cycles 125410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6500329478 # number of ReadReq miss cycles 125510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 21309046436 # number of ReadReq miss cycles 125610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 28354935663 # number of ReadReq miss cycles 125710628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 3493350 # number of WriteInvalidateReq miss cycles 125810628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_latency::total 3493350 # number of WriteInvalidateReq miss cycles 125910628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 414507203 # number of UpgradeReq miss cycles 126010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 414507203 # number of UpgradeReq miss cycles 126110585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 72000 # number of SCUpgradeReq miss cycles 126210585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 72000 # number of SCUpgradeReq miss cycles 126310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34565495113 # number of ReadExReq miss cycles 126410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 34565495113 # number of ReadExReq miss cycles 126510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 284358999 # number of demand (read+write) miss cycles 126610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 261200750 # number of demand (read+write) miss cycles 126710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 6500329478 # number of demand (read+write) miss cycles 126810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 55874541549 # number of demand (read+write) miss cycles 126910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 62920430776 # number of demand (read+write) miss cycles 127010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 284358999 # number of overall miss cycles 127110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 261200750 # number of overall miss cycles 127210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 6500329478 # number of overall miss cycles 127310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 55874541549 # number of overall miss cycles 127410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 62920430776 # number of overall miss cycles 127510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 803417 # number of ReadReq accesses(hits+misses) 127610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302633 # number of ReadReq accesses(hits+misses) 127710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 15084690 # number of ReadReq accesses(hits+misses) 127810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 6595219 # number of ReadReq accesses(hits+misses) 127910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 22785959 # number of ReadReq accesses(hits+misses) 128010628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 7597183 # number of Writeback accesses(hits+misses) 128110628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 7597183 # number of Writeback accesses(hits+misses) 128210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226180 # number of WriteInvalidateReq accesses(hits+misses) 128310628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_accesses::total 1226180 # number of WriteInvalidateReq accesses(hits+misses) 128410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 43945 # number of UpgradeReq accesses(hits+misses) 128510628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 43945 # number of UpgradeReq accesses(hits+misses) 128610585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 128710585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 128810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2001716 # number of ReadExReq accesses(hits+misses) 128910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 2001716 # number of ReadExReq accesses(hits+misses) 129010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 803417 # number of demand (read+write) accesses 129110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 302633 # number of demand (read+write) accesses 129210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 15084690 # number of demand (read+write) accesses 129310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 8596935 # number of demand (read+write) accesses 129410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 24787675 # number of demand (read+write) accesses 129510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 803417 # number of overall (read+write) accesses 129610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 302633 # number of overall (read+write) accesses 129710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 15084690 # number of overall (read+write) accesses 129810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 8596935 # number of overall (read+write) accesses 129910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 24787675 # number of overall (read+write) accesses 130010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004410 # miss rate for ReadReq accesses 130110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010600 # miss rate for ReadReq accesses 130210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005598 # miss rate for ReadReq accesses 130310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038846 # miss rate for ReadReq accesses 130410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.015246 # miss rate for ReadReq accesses 130510628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404389 # miss rate for WriteInvalidateReq accesses 130610628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404389 # miss rate for WriteInvalidateReq accesses 130710628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784594 # miss rate for UpgradeReq accesses 130810628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.784594 # miss rate for UpgradeReq accesses 130910585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 131010585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 131110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.208727 # miss rate for ReadExReq accesses 131210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.208727 # miss rate for ReadExReq accesses 131310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004410 # miss rate for demand accesses 131410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010600 # miss rate for demand accesses 131510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005598 # miss rate for demand accesses 131610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.078401 # miss rate for demand accesses 131710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.030870 # miss rate for demand accesses 131810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004410 # miss rate for overall accesses 131910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010600 # miss rate for overall accesses 132010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005598 # miss rate for overall accesses 132110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.078401 # miss rate for overall accesses 132210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.030870 # miss rate for overall accesses 132310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 80259.384420 # average ReadReq miss latency 132410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81421.680175 # average ReadReq miss latency 132510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76977.079496 # average ReadReq miss latency 132610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83174.781948 # average ReadReq miss latency 132710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 81622.304667 # average ReadReq miss latency 132810628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 7.045118 # average WriteInvalidateReq miss latency 132910628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 7.045118 # average WriteInvalidateReq miss latency 133010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12022.019287 # average UpgradeReq miss latency 133110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12022.019287 # average UpgradeReq miss latency 133210585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 36000 # average SCUpgradeReq miss latency 133310585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 36000 # average SCUpgradeReq miss latency 133410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82729.780650 # average ReadExReq miss latency 133510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 82729.780650 # average ReadExReq miss latency 133610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency 133710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency 133810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency 133910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency 134010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 82227.001918 # average overall miss latency 134110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency 134210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency 134310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency 134410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency 134510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 82227.001918 # average overall miss latency 134610585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 134710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 134810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 134910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 135010585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 135110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 135210585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 135310585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 135410628Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 982720 # number of writebacks 135510628Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 982720 # number of writebacks 135610585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 135710585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits 135810585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 135910585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits 136010585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 136110585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits 136210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3543 # number of ReadReq MSHR misses 136310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3208 # number of ReadReq MSHR misses 136410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84445 # number of ReadReq MSHR misses 136510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256175 # number of ReadReq MSHR misses 136610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 347371 # number of ReadReq MSHR misses 136710628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495854 # number of WriteInvalidateReq MSHR misses 136810628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495854 # number of WriteInvalidateReq MSHR misses 136910628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34479 # number of UpgradeReq MSHR misses 137010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 34479 # number of UpgradeReq MSHR misses 137110585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 137210585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 137310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 417812 # number of ReadExReq MSHR misses 137410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 417812 # number of ReadExReq MSHR misses 137510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3543 # number of demand (read+write) MSHR misses 137610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3208 # number of demand (read+write) MSHR misses 137710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 84445 # number of demand (read+write) MSHR misses 137810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 673987 # number of demand (read+write) MSHR misses 137910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 765183 # number of demand (read+write) MSHR misses 138010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3543 # number of overall MSHR misses 138110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3208 # number of overall MSHR misses 138210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 84445 # number of overall MSHR misses 138310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 673987 # number of overall MSHR misses 138410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 765183 # number of overall MSHR misses 138510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 240086499 # number of ReadReq MSHR miss cycles 138610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 221074750 # number of ReadReq MSHR miss cycles 138710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5441255518 # number of ReadReq MSHR miss cycles 138810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18116835264 # number of ReadReq MSHR miss cycles 138910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 24019252031 # number of ReadReq MSHR miss cycles 139010628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 19575424791 # number of WriteInvalidateReq MSHR miss cycles 139110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 19575424791 # number of WriteInvalidateReq MSHR miss cycles 139210628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345346475 # number of UpgradeReq MSHR miss cycles 139310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345346475 # number of UpgradeReq MSHR miss cycles 139410585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70001 # number of SCUpgradeReq MSHR miss cycles 139510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70001 # number of SCUpgradeReq MSHR miss cycles 139610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29394156879 # number of ReadExReq MSHR miss cycles 139710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29394156879 # number of ReadExReq MSHR miss cycles 139810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 240086499 # number of demand (read+write) MSHR miss cycles 139910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 221074750 # number of demand (read+write) MSHR miss cycles 140010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5441255518 # number of demand (read+write) MSHR miss cycles 140110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47510992143 # number of demand (read+write) MSHR miss cycles 140210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 53413408910 # number of demand (read+write) MSHR miss cycles 140310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 240086499 # number of overall MSHR miss cycles 140410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 221074750 # number of overall MSHR miss cycles 140510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5441255518 # number of overall MSHR miss cycles 140610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47510992143 # number of overall MSHR miss cycles 140710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 53413408910 # number of overall MSHR miss cycles 140810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103864500 # number of ReadReq MSHR uncacheable cycles 140910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289749251 # number of ReadReq MSHR uncacheable cycles 141010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393613751 # number of ReadReq MSHR uncacheable cycles 141110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176073500 # number of WriteReq MSHR uncacheable cycles 141210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176073500 # number of WriteReq MSHR uncacheable cycles 141310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103864500 # number of overall MSHR uncacheable cycles 141410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465822751 # number of overall MSHR uncacheable cycles 141510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569687251 # number of overall MSHR uncacheable cycles 141610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for ReadReq accesses 141710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for ReadReq accesses 141810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for ReadReq accesses 141910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038843 # mshr miss rate for ReadReq accesses 142010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015245 # mshr miss rate for ReadReq accesses 142110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404389 # mshr miss rate for WriteInvalidateReq accesses 142210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404389 # mshr miss rate for WriteInvalidateReq accesses 142310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784594 # mshr miss rate for UpgradeReq accesses 142410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784594 # mshr miss rate for UpgradeReq accesses 142510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 142610585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 142710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208727 # mshr miss rate for ReadExReq accesses 142810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208727 # mshr miss rate for ReadExReq accesses 142910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for demand accesses 143010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for demand accesses 143110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for demand accesses 143210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for demand accesses 143310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.030869 # mshr miss rate for demand accesses 143410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for overall accesses 143510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for overall accesses 143610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for overall accesses 143710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for overall accesses 143810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.030869 # mshr miss rate for overall accesses 143910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average ReadReq mshr miss latency 144010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average ReadReq mshr miss latency 144110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690 # average ReadReq mshr miss latency 144210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628 # average ReadReq mshr miss latency 144310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249 # average ReadReq mshr miss latency 144410628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840 # average WriteInvalidateReq mshr miss latency 144510628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840 # average WriteInvalidateReq mshr miss latency 144610628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534 # average UpgradeReq mshr miss latency 144710628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534 # average UpgradeReq mshr miss latency 144810585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency 144910585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency 145010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307 # average ReadExReq mshr miss latency 145110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307 # average ReadExReq mshr miss latency 145210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency 145310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency 145410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency 145510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency 145610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency 145710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency 145810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency 145910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency 146010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency 146110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency 146210585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 146310585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 146410585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 146510585Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 146610585Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 146710585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 146810585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 146910585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 147010585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 147110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution 147210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution 147310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution 147410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution 147510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution 147610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution 147710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution 147810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution 147910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 148010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution 148110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution 148210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution 148310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) 148410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) 148510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) 148610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) 148710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) 148810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) 148910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) 149010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) 149110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) 149210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) 149310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 606880 # Total snoops (count) 149410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram 149510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.003347 # Request fanout histogram 149610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram 149710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 149810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 149910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 150010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 150110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 150210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 150310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 34397489 99.67% 99.67% # Request fanout histogram 150410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 115519 0.33% 100.00% # Request fanout histogram 150510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 150610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 150710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 150810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram 150910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) 151010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 151110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) 151210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 151310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) 151410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 151510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) 151610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 151710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) 151810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 151910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) 152010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 152110628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40381 # Transaction distribution 152210628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40381 # Transaction distribution 152310585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136733 # Transaction distribution 152410585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 30069 # Transaction distribution 152510585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 152610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) 152710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 152810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 152910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 153010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 153110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 153210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 153310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 153410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 153510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 153610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 153710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 153810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 153910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 154010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 154110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) 154210628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) 154310628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) 154410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 154510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 154610628Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) 154710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) 154810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 154910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 155010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 155110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 155210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 155310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 155410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 155510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 155610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 155710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 155810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 155910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 156010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 156110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 156210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) 156310628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) 156410628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) 156510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 156610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 156710628Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) 156810585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) 156910585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 157010585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 157110585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 157210585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 157310585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 157410585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 157510585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 157610585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 157710585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 157810585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 157910585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 158010585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 158110585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 158210585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 158310585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 158410585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 158510585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 158610585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 158710585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 158810585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 158910585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 159010585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 159110585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 159210585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 159310585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 159410585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 159510585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 159610628Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) 159710585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 159810585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 159910585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 160010585Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) 160110585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 160210628Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) 160310585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 160410585Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 160510585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 160610628Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115461 # number of replacements 160710628Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use 160810585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 160910628Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. 161010585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 161110628Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. 161210628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor 161310628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor 161410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy 161510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy 161610628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy 161710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 161810585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 161910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 162010628Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1039668 # Number of tag accesses 162110628Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1039668 # Number of data accesses 162210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 162310628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses 162410628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8852 # number of ReadReq misses 162510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 162610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 162710585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 162810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 162910585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 163010628Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses 163110628Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8855 # number of demand (read+write) misses 163210585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 163310628Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8815 # number of overall misses 163410628Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8855 # number of overall misses 163510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles 163610628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles 163710628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles 163810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles 163910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles 164010628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles 164110628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles 164210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles 164310628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles 164410628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles 164510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles 164610628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles 164710628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles 164810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 164910628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) 165010628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) 165110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 165210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 165310585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 165410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 165510585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 165610628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses 165710628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses 165810585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 165910628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses 166010628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses 166110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 166210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 166310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 166410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 166510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 166610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 166710585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 166810585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 166910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 167010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 167110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 167210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 167310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 167410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency 167510628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency 167610628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency 167710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency 167810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency 167910628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency 168010628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency 168110585Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency 168210628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency 168310628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency 168410585Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency 168510628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency 168610628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency 168710628Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked 168810585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 168910628Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked 169010585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 169110628Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked 169210585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 169310585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 169410585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 169510585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106631 # number of writebacks 169610585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106631 # number of writebacks 169710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 169810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses 169910628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses 170010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 170110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 170210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 170310585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses 170410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 170510628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses 170610628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses 170710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 170810628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses 170910628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses 171010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles 171110628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles 171210628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles 171310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles 171410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles 171510628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles 171610628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles 171710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles 171810628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles 171910628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles 172010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles 172110628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles 172210628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles 172310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 172410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 172510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 172610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 172710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 172810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 172910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 173010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 173110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 173210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 173310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 173410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 173510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 173610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency 173710628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency 173810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency 173910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency 174010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 174110628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency 174210628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency 174310585Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency 174410628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency 174510628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency 174610585Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency 174710628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency 174810628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency 174910585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 175010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 411277 # Transaction distribution 175110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 411277 # Transaction distribution 175210585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33858 # Transaction distribution 175310585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33858 # Transaction distribution 175410628Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1089351 # Transaction distribution 175510628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution 175610628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution 175710628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 35261 # Transaction distribution 175810585Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 175910628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 35263 # Transaction distribution 176010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 417183 # Transaction distribution 176110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 417183 # Transaction distribution 176210515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) 176310515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) 176410585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) 176510628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) 176610628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) 176710628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) 176810628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) 176910628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) 177010515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) 177110515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) 177210585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) 177310628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) 177410628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) 177510628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) 177610628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) 177710628Sandreas.hansson@arm.comsystem.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) 177810628Sandreas.hansson@arm.comsystem.membus.snoops 3154 # Total snoops (count) 177910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2500418 # Request fanout histogram 178010515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 178110515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 178210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 178310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 178410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram 178510515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 178610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 178710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 178810515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 178910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2500418 # Request fanout histogram 179010628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) 179110515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 179210515SAli.Saidi@ARM.comsystem.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) 179310515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 179410628Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) 179510515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 179610628Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) 179710585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 179810628Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) 179910515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 180010628Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) 180110515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 180210515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 180310515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 180410515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 180510515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 180610515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 180710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 180810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 180910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 181010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 181110585Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 181210515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 181310515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 181410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 181510585Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 181610515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 181710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 181810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 181910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 182010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 182110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 182210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 182310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 182410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 182510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 182610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 182710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 182810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 182910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 183010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 183110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 183210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 183310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 183410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 183510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 183610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 183710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 183810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 183910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 184010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 184110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 184210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 184310515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 184410515SAli.Saidi@ARM.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 184510585Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed 184610515SAli.Saidi@ARM.com 184710515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1848