stats.txt revision 11441:0edcf757b6a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.389857 # Number of seconds simulated 4sim_ticks 47389857088000 # Number of ticks simulated 5final_tick 47389857088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 145229 # Simulator instruction rate (inst/s) 8host_op_rate 170794 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7499087776 # Simulator tick rate (ticks/s) 10host_mem_usage 767912 # Number of bytes of host memory used 11host_seconds 6319.42 # Real time elapsed on the host 12sim_insts 917760909 # Number of instructions simulated 13sim_ops 1079317478 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 104896 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 67648 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3518240 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 12875080 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 14592448 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 209856 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 206272 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3409696 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 12665040 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 18241216 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory 27system.physmem.bytes_read::total 66337496 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3518240 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3409696 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 6927936 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 83736832 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 83757416 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1639 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1057 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 70925 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 201186 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 228007 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 3279 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 3223 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 53320 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 197904 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 285019 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1052545 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1308388 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1310962 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2213 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1427 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 74240 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 271684 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 307923 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 4428 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 4353 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 71950 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 267252 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 384918 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9435 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1399825 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 74240 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 71950 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 146190 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1766978 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1767412 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1766978 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2213 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1427 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 74240 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 272119 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 307923 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 4428 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 4353 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 71950 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 267252 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 384918 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9435 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3167237 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1052545 # Number of read requests accepted 84system.physmem.writeReqs 1310962 # Number of write requests accepted 85system.physmem.readBursts 1052545 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1310962 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 67342528 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 20352 # Total number of bytes read from write queue 89system.physmem.bytesWritten 83756608 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 66337496 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 83757416 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 318 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 66733 # Per bank write bursts 96system.physmem.perBankRdBursts::1 71928 # Per bank write bursts 97system.physmem.perBankRdBursts::2 60670 # Per bank write bursts 98system.physmem.perBankRdBursts::3 68962 # Per bank write bursts 99system.physmem.perBankRdBursts::4 64861 # Per bank write bursts 100system.physmem.perBankRdBursts::5 72347 # Per bank write bursts 101system.physmem.perBankRdBursts::6 66642 # Per bank write bursts 102system.physmem.perBankRdBursts::7 70254 # Per bank write bursts 103system.physmem.perBankRdBursts::8 57646 # Per bank write bursts 104system.physmem.perBankRdBursts::9 82139 # Per bank write bursts 105system.physmem.perBankRdBursts::10 57944 # Per bank write bursts 106system.physmem.perBankRdBursts::11 62634 # Per bank write bursts 107system.physmem.perBankRdBursts::12 58488 # Per bank write bursts 108system.physmem.perBankRdBursts::13 63067 # Per bank write bursts 109system.physmem.perBankRdBursts::14 63784 # Per bank write bursts 110system.physmem.perBankRdBursts::15 64128 # Per bank write bursts 111system.physmem.perBankWrBursts::0 82746 # Per bank write bursts 112system.physmem.perBankWrBursts::1 86394 # Per bank write bursts 113system.physmem.perBankWrBursts::2 79376 # Per bank write bursts 114system.physmem.perBankWrBursts::3 84859 # Per bank write bursts 115system.physmem.perBankWrBursts::4 81483 # Per bank write bursts 116system.physmem.perBankWrBursts::5 87954 # Per bank write bursts 117system.physmem.perBankWrBursts::6 81083 # Per bank write bursts 118system.physmem.perBankWrBursts::7 85604 # Per bank write bursts 119system.physmem.perBankWrBursts::8 78166 # Per bank write bursts 120system.physmem.perBankWrBursts::9 81607 # Per bank write bursts 121system.physmem.perBankWrBursts::10 78637 # Per bank write bursts 122system.physmem.perBankWrBursts::11 81487 # Per bank write bursts 123system.physmem.perBankWrBursts::12 76226 # Per bank write bursts 124system.physmem.perBankWrBursts::13 79682 # Per bank write bursts 125system.physmem.perBankWrBursts::14 80516 # Per bank write bursts 126system.physmem.perBankWrBursts::15 82877 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 67 # Number of times write queue was full causing retry 129system.physmem.totGap 47389855480500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1031187 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1308388 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 475081 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 269839 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 74446 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 52901 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 38377 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 34235 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 31560 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 30053 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 26736 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 7334 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 3987 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 2417 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1591 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1204 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 701 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 610 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 497 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 402 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 102 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 25192 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 30313 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 42202 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 46715 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 53462 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 56984 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 62681 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 68834 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 74158 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 77826 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 82266 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 87664 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 86481 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 90056 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 101873 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 89446 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 81226 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 76109 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 12688 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 9562 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 8108 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 6575 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 5525 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 4656 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 3860 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 3225 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 2811 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 2313 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 2109 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 1888 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 1728 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 1474 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 1382 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 1115 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 1007 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 898 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 706 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 649 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 451 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 461 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 369 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 325 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 268 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 218 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 177 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 194 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 206 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 114 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 151 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1063862 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 142.028406 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 96.908483 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 188.947681 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 721844 67.85% 67.85% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 204911 19.26% 87.11% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 49859 4.69% 91.80% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 22222 2.09% 93.89% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 18303 1.72% 95.61% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 10788 1.01% 96.62% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 6944 0.65% 97.27% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 4476 0.42% 97.70% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 24515 2.30% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1063862 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 61379 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 17.142980 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 72.283129 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-511 61375 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 61379 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 61379 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 21.321576 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.114024 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 78.581580 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::0-127 61139 99.61% 99.61% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::128-255 150 0.24% 99.85% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::256-383 15 0.02% 99.88% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::384-511 13 0.02% 99.90% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::512-639 10 0.02% 99.92% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::640-767 5 0.01% 99.92% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::768-895 6 0.01% 99.93% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::896-1023 2 0.00% 99.94% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.94% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::1152-1279 3 0.00% 99.95% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::1280-1407 1 0.00% 99.95% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::1408-1535 3 0.00% 99.95% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::1536-1663 1 0.00% 99.95% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::1664-1791 2 0.00% 99.96% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::1792-1919 3 0.00% 99.96% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::1920-2047 1 0.00% 99.96% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::2048-2175 1 0.00% 99.97% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::2176-2303 2 0.00% 99.97% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::2432-2559 1 0.00% 99.97% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::2560-2687 2 0.00% 99.97% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::2944-3071 1 0.00% 99.98% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.98% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::3200-3327 1 0.00% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::3840-3967 2 0.00% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::3968-4095 3 0.00% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::4224-4351 3 0.00% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::4736-4863 1 0.00% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::5760-5887 1 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::6528-6655 1 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 61379 # Writes before turning the bus around for reads 299system.physmem.totQLat 45835808351 # Total ticks spent queuing 300system.physmem.totMemAccLat 65565064601 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 5261135000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 43560.76 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 62310.76 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 1.42 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.02 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 2.02 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 25.24 # Average write queue length when enqueuing 315system.physmem.readRowHits 793650 # Number of row buffer hits during reads 316system.physmem.writeRowHits 503408 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 75.43 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 38.47 # Row buffer hit rate for writes 319system.physmem.avgGap 20050651.63 # Average gap between requests 320system.physmem.pageHitRate 54.94 # Row buffer hit rate, read and write combined 321system.physmem_0.actEnergy 4147801560 # Energy for activate commands per rank (pJ) 322system.physmem_0.preEnergy 2263185375 # Energy for precharge commands per rank (pJ) 323system.physmem_0.readEnergy 4230649800 # Energy for read commands per rank (pJ) 324system.physmem_0.writeEnergy 4338353520 # Energy for write commands per rank (pJ) 325system.physmem_0.refreshEnergy 3095274664560 # Energy for refresh commands per rank (pJ) 326system.physmem_0.actBackEnergy 1171144383615 # Energy for active background per rank (pJ) 327system.physmem_0.preBackEnergy 27406590797250 # Energy for precharge background per rank (pJ) 328system.physmem_0.totalEnergy 31687989835680 # Total energy per rank (pJ) 329system.physmem_0.averagePower 668.666167 # Core power per rank (mW) 330system.physmem_0.memoryStateTime::IDLE 45593219352262 # Time in different power states 331system.physmem_0.memoryStateTime::REF 1582451260000 # Time in different power states 332system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 333system.physmem_0.memoryStateTime::ACT 214185512238 # Time in different power states 334system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 335system.physmem_1.actEnergy 3894995160 # Energy for activate commands per rank (pJ) 336system.physmem_1.preEnergy 2125245375 # Energy for precharge commands per rank (pJ) 337system.physmem_1.readEnergy 3976658400 # Energy for read commands per rank (pJ) 338system.physmem_1.writeEnergy 4142003040 # Energy for write commands per rank (pJ) 339system.physmem_1.refreshEnergy 3095274664560 # Energy for refresh commands per rank (pJ) 340system.physmem_1.actBackEnergy 1168941164895 # Energy for active background per rank (pJ) 341system.physmem_1.preBackEnergy 27408523445250 # Energy for precharge background per rank (pJ) 342system.physmem_1.totalEnergy 31686878176680 # Total energy per rank (pJ) 343system.physmem_1.averagePower 668.642709 # Core power per rank (mW) 344system.physmem_1.memoryStateTime::IDLE 45596430811261 # Time in different power states 345system.physmem_1.memoryStateTime::REF 1582451260000 # Time in different power states 346system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 347system.physmem_1.memoryStateTime::ACT 210971448239 # Time in different power states 348system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 349system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 357system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 362system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 375system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 376system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 377system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 378system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 379system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 380system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 381system.cpu0.branchPred.lookups 134064980 # Number of BP lookups 382system.cpu0.branchPred.condPredicted 88919550 # Number of conditional branches predicted 383system.cpu0.branchPred.condIncorrect 6498041 # Number of conditional branches incorrect 384system.cpu0.branchPred.BTBLookups 94483455 # Number of BTB lookups 385system.cpu0.branchPred.BTBHits 58137091 # Number of BTB hits 386system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 387system.cpu0.branchPred.BTBHitPct 61.531504 # BTB Hit Percentage 388system.cpu0.branchPred.usedRAS 17960348 # Number of times the RAS was used to get a target. 389system.cpu0.branchPred.RASInCorrect 169436 # Number of incorrect RAS predictions. 390system.cpu0.branchPred.indirectLookups 4224209 # Number of indirect predictor lookups. 391system.cpu0.branchPred.indirectHits 2670261 # Number of indirect target hits. 392system.cpu0.branchPred.indirectMisses 1553948 # Number of indirect misses. 393system.cpu0.branchPredindirectMispredicted 396228 # Number of mispredicted indirect branches. 394system.cpu_clk_domain.clock 500 # Clock period in ticks 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 404system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 405system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 406system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 407system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 408system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 410system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 411system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 412system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 413system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 414system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 416system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 419system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 420system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 421system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 422system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 423system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 424system.cpu0.dtb.walker.walks 535513 # Table walker walks requested 425system.cpu0.dtb.walker.walksLong 535513 # Table walker walks initiated with long descriptors 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11169 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 82857 # Level at which table walker walks with long descriptors terminate 428system.cpu0.dtb.walker.walksSquashedBefore 246420 # Table walks squashed before starting 429system.cpu0.dtb.walker.walkWaitTime::samples 289093 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::mean 2351.355792 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::stdev 14312.568858 # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::0-65535 286889 99.24% 99.24% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::65536-131071 1266 0.44% 99.68% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::131072-196607 685 0.24% 99.91% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.96% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::262144-327679 30 0.01% 99.97% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::327680-393215 61 0.02% 99.99% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::393216-458751 19 0.01% 100.00% # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkWaitTime::total 289093 # Table walker wait (enqueue to first request) latency 442system.cpu0.dtb.walker.walkCompletionTime::samples 272039 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::mean 19613.296255 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::gmean 17220.717357 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::stdev 14703.962270 # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::0-65535 270425 99.41% 99.41% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::65536-131071 632 0.23% 99.64% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::131072-196607 733 0.27% 99.91% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::196608-262143 61 0.02% 99.93% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::262144-327679 123 0.05% 99.98% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.01% 99.99% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::458752-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::720896-786431 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::total 272039 # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walksPending::samples 510275836160 # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::mean 0.563308 # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::stdev 0.548439 # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::0-1 509171724160 99.78% 99.78% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::2-3 565791000 0.11% 99.89% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::4-5 239447000 0.05% 99.94% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::6-7 119430500 0.02% 99.96% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::8-9 85504500 0.02% 99.98% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::10-11 55232500 0.01% 99.99% # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::12-13 15487000 0.00% 100.00% # Table walker pending requests distribution 469system.cpu0.dtb.walker.walksPending::14-15 22822000 0.00% 100.00% # Table walker pending requests distribution 470system.cpu0.dtb.walker.walksPending::16-17 392500 0.00% 100.00% # Table walker pending requests distribution 471system.cpu0.dtb.walker.walksPending::18-19 5000 0.00% 100.00% # Table walker pending requests distribution 472system.cpu0.dtb.walker.walksPending::total 510275836160 # Table walker pending requests distribution 473system.cpu0.dtb.walker.walkPageSizes::4K 82857 88.12% 88.12% # Table walker page sizes translated 474system.cpu0.dtb.walker.walkPageSizes::2M 11169 11.88% 100.00% # Table walker page sizes translated 475system.cpu0.dtb.walker.walkPageSizes::total 94026 # Table walker page sizes translated 476system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 535513 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 535513 # Table walker requests started/completed, data/inst 479system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94026 # Table walker requests started/completed, data/inst 480system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94026 # Table walker requests started/completed, data/inst 482system.cpu0.dtb.walker.walkRequestOrigin::total 629539 # Table walker requests started/completed, data/inst 483system.cpu0.dtb.inst_hits 0 # ITB inst hits 484system.cpu0.dtb.inst_misses 0 # ITB inst misses 485system.cpu0.dtb.read_hits 97385635 # DTB read hits 486system.cpu0.dtb.read_misses 369085 # DTB read misses 487system.cpu0.dtb.write_hits 80705124 # DTB write hits 488system.cpu0.dtb.write_misses 166428 # DTB write misses 489system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 490system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 491system.cpu0.dtb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID 492system.cpu0.dtb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID 493system.cpu0.dtb.flush_entries 34685 # Number of entries that have been flushed from TLB 494system.cpu0.dtb.align_faults 254 # Number of TLB faults due to alignment restrictions 495system.cpu0.dtb.prefetch_faults 6533 # Number of TLB faults due to prefetch 496system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 497system.cpu0.dtb.perms_faults 38231 # Number of TLB faults due to permissions restrictions 498system.cpu0.dtb.read_accesses 97754720 # DTB read accesses 499system.cpu0.dtb.write_accesses 80871552 # DTB write accesses 500system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 501system.cpu0.dtb.hits 178090759 # DTB hits 502system.cpu0.dtb.misses 535513 # DTB misses 503system.cpu0.dtb.accesses 178626272 # DTB accesses 504system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 510system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 511system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 512system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 513system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 514system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 515system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 516system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 517system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 518system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 519system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 520system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 521system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 522system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 523system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 524system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 525system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 526system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 527system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 528system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 529system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 530system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 531system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 532system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 533system.cpu0.itb.walker.walks 79425 # Table walker walks requested 534system.cpu0.itb.walker.walksLong 79425 # Table walker walks initiated with long descriptors 535system.cpu0.itb.walker.walksLongTerminationLevel::Level2 951 # Level at which table walker walks with long descriptors terminate 536system.cpu0.itb.walker.walksLongTerminationLevel::Level3 57153 # Level at which table walker walks with long descriptors terminate 537system.cpu0.itb.walker.walksSquashedBefore 9771 # Table walks squashed before starting 538system.cpu0.itb.walker.walkWaitTime::samples 69654 # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::mean 1061.827031 # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::stdev 8997.758844 # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::0-32767 69210 99.36% 99.36% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::32768-65535 270 0.39% 99.75% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::65536-98303 5 0.01% 99.76% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::98304-131071 37 0.05% 99.81% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::131072-163839 88 0.13% 99.94% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::163840-196607 29 0.04% 99.98% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 549system.cpu0.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency 550system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 551system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 552system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 553system.cpu0.itb.walker.walkWaitTime::total 69654 # Table walker wait (enqueue to first request) latency 554system.cpu0.itb.walker.walkCompletionTime::samples 67875 # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::mean 24239.233886 # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::gmean 22083.564087 # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::stdev 17866.594665 # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::0-65535 67243 99.07% 99.07% # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::65536-131071 67 0.10% 99.17% # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walkCompletionTime::131072-196607 462 0.68% 99.85% # Table walker service (enqueue to completion) latency 561system.cpu0.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.90% # Table walker service (enqueue to completion) latency 562system.cpu0.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.95% # Table walker service (enqueue to completion) latency 563system.cpu0.itb.walker.walkCompletionTime::327680-393215 16 0.02% 99.97% # Table walker service (enqueue to completion) latency 564system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency 565system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 566system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 567system.cpu0.itb.walker.walkCompletionTime::total 67875 # Table walker service (enqueue to completion) latency 568system.cpu0.itb.walker.walksPending::samples 394215499668 # Table walker pending requests distribution 569system.cpu0.itb.walker.walksPending::mean 0.849337 # Table walker pending requests distribution 570system.cpu0.itb.walker.walksPending::stdev 0.357871 # Table walker pending requests distribution 571system.cpu0.itb.walker.walksPending::0 59413822884 15.07% 15.07% # Table walker pending requests distribution 572system.cpu0.itb.walker.walksPending::1 334782784784 84.92% 100.00% # Table walker pending requests distribution 573system.cpu0.itb.walker.walksPending::2 17900000 0.00% 100.00% # Table walker pending requests distribution 574system.cpu0.itb.walker.walksPending::3 873000 0.00% 100.00% # Table walker pending requests distribution 575system.cpu0.itb.walker.walksPending::4 119000 0.00% 100.00% # Table walker pending requests distribution 576system.cpu0.itb.walker.walksPending::total 394215499668 # Table walker pending requests distribution 577system.cpu0.itb.walker.walkPageSizes::4K 57153 98.36% 98.36% # Table walker page sizes translated 578system.cpu0.itb.walker.walkPageSizes::2M 951 1.64% 100.00% # Table walker page sizes translated 579system.cpu0.itb.walker.walkPageSizes::total 58104 # Table walker page sizes translated 580system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 581system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79425 # Table walker requests started/completed, data/inst 582system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79425 # Table walker requests started/completed, data/inst 583system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 584system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58104 # Table walker requests started/completed, data/inst 585system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58104 # Table walker requests started/completed, data/inst 586system.cpu0.itb.walker.walkRequestOrigin::total 137529 # Table walker requests started/completed, data/inst 587system.cpu0.itb.inst_hits 209912640 # ITB inst hits 588system.cpu0.itb.inst_misses 79425 # ITB inst misses 589system.cpu0.itb.read_hits 0 # DTB read hits 590system.cpu0.itb.read_misses 0 # DTB read misses 591system.cpu0.itb.write_hits 0 # DTB write hits 592system.cpu0.itb.write_misses 0 # DTB write misses 593system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 594system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 595system.cpu0.itb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID 596system.cpu0.itb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID 597system.cpu0.itb.flush_entries 24340 # Number of entries that have been flushed from TLB 598system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 599system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 600system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 601system.cpu0.itb.perms_faults 193348 # Number of TLB faults due to permissions restrictions 602system.cpu0.itb.read_accesses 0 # DTB read accesses 603system.cpu0.itb.write_accesses 0 # DTB write accesses 604system.cpu0.itb.inst_accesses 209992065 # ITB inst accesses 605system.cpu0.itb.hits 209912640 # DTB hits 606system.cpu0.itb.misses 79425 # DTB misses 607system.cpu0.itb.accesses 209992065 # DTB accesses 608system.cpu0.numCycles 756853118 # number of cpu cycles simulated 609system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 610system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 611system.cpu0.fetch.icacheStallCycles 86258252 # Number of cycles fetch is stalled on an Icache miss 612system.cpu0.fetch.Insts 591637469 # Number of instructions fetch has processed 613system.cpu0.fetch.Branches 134064980 # Number of branches that fetch encountered 614system.cpu0.fetch.predictedBranches 78767700 # Number of branches that fetch has predicted taken 615system.cpu0.fetch.Cycles 626674135 # Number of cycles fetch has run and was not squashing or blocked 616system.cpu0.fetch.SquashCycles 13960220 # Number of cycles fetch has spent squashing 617system.cpu0.fetch.TlbCycles 1708629 # Number of cycles fetch has spent waiting for tlb 618system.cpu0.fetch.MiscStallCycles 309159 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 619system.cpu0.fetch.PendingTrapStallCycles 5578419 # Number of stall cycles due to pending traps 620system.cpu0.fetch.PendingQuiesceStallCycles 726023 # Number of stall cycles due to pending quiesce instructions 621system.cpu0.fetch.IcacheWaitRetryStallCycles 793198 # Number of stall cycles due to full MSHR 622system.cpu0.fetch.CacheLines 209720229 # Number of cache lines fetched 623system.cpu0.fetch.IcacheSquashes 1626111 # Number of outstanding Icache misses that were squashed 624system.cpu0.fetch.ItlbSquashes 25986 # Number of outstanding ITLB misses that were squashed 625system.cpu0.fetch.rateDist::samples 729027925 # Number of instructions fetched each cycle (Total) 626system.cpu0.fetch.rateDist::mean 0.950211 # Number of instructions fetched each cycle (Total) 627system.cpu0.fetch.rateDist::stdev 1.213293 # Number of instructions fetched each cycle (Total) 628system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.rateDist::0 397179270 54.48% 54.48% # Number of instructions fetched each cycle (Total) 630system.cpu0.fetch.rateDist::1 129433697 17.75% 72.23% # Number of instructions fetched each cycle (Total) 631system.cpu0.fetch.rateDist::2 43948284 6.03% 78.26% # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::3 158466674 21.74% 100.00% # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::total 729027925 # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.branchRate 0.177135 # Number of branch fetches per cycle 638system.cpu0.fetch.rate 0.781707 # Number of inst fetches per cycle 639system.cpu0.decode.IdleCycles 101905293 # Number of cycles decode is idle 640system.cpu0.decode.BlockedCycles 364135087 # Number of cycles decode is blocked 641system.cpu0.decode.RunCycles 222287988 # Number of cycles decode is running 642system.cpu0.decode.UnblockCycles 35712800 # Number of cycles decode is unblocking 643system.cpu0.decode.SquashCycles 4986757 # Number of cycles decode is squashing 644system.cpu0.decode.BranchResolved 19110947 # Number of times decode resolved a branch 645system.cpu0.decode.BranchMispred 2030964 # Number of times decode detected a branch misprediction 646system.cpu0.decode.DecodedInsts 613952929 # Number of instructions handled by decode 647system.cpu0.decode.SquashedInsts 22693715 # Number of squashed instructions handled by decode 648system.cpu0.rename.SquashCycles 4986757 # Number of cycles rename is squashing 649system.cpu0.rename.IdleCycles 135896080 # Number of cycles rename is idle 650system.cpu0.rename.BlockCycles 55064795 # Number of cycles rename is blocking 651system.cpu0.rename.serializeStallCycles 234892830 # count of cycles rename stalled for serializing inst 652system.cpu0.rename.RunCycles 223531264 # Number of cycles rename is running 653system.cpu0.rename.UnblockCycles 74656199 # Number of cycles rename is unblocking 654system.cpu0.rename.RenamedInsts 597354053 # Number of instructions processed by rename 655system.cpu0.rename.SquashedInsts 5967968 # Number of squashed instructions processed by rename 656system.cpu0.rename.ROBFullEvents 10658303 # Number of times rename has blocked due to ROB full 657system.cpu0.rename.IQFullEvents 242676 # Number of times rename has blocked due to IQ full 658system.cpu0.rename.LQFullEvents 277310 # Number of times rename has blocked due to LQ full 659system.cpu0.rename.SQFullEvents 41417072 # Number of times rename has blocked due to SQ full 660system.cpu0.rename.FullRegisterEvents 10715 # Number of times there has been no free registers 661system.cpu0.rename.RenamedOperands 569274330 # Number of destination operands rename has renamed 662system.cpu0.rename.RenameLookups 919727485 # Number of register rename lookups that rename has made 663system.cpu0.rename.int_rename_lookups 705445437 # Number of integer rename lookups 664system.cpu0.rename.fp_rename_lookups 845170 # Number of floating rename lookups 665system.cpu0.rename.CommittedMaps 513762865 # Number of HB maps that are committed 666system.cpu0.rename.UndoneMaps 55511456 # Number of HB maps that are undone due to squashing 667system.cpu0.rename.serializingInsts 14761622 # count of serializing insts renamed 668system.cpu0.rename.tempSerializingInsts 12913765 # count of temporary serializing insts renamed 669system.cpu0.rename.skidInsts 71848393 # count of insts added to the skid buffer 670system.cpu0.memDep0.insertedLoads 97600013 # Number of loads inserted to the mem dependence unit. 671system.cpu0.memDep0.insertedStores 83873039 # Number of stores inserted to the mem dependence unit. 672system.cpu0.memDep0.conflictingLoads 8761707 # Number of conflicting loads. 673system.cpu0.memDep0.conflictingStores 7520310 # Number of conflicting stores. 674system.cpu0.iq.iqInstsAdded 575959343 # Number of instructions added to the IQ (excludes non-spec) 675system.cpu0.iq.iqNonSpecInstsAdded 14902678 # Number of non-speculative instructions added to the IQ 676system.cpu0.iq.iqInstsIssued 580046321 # Number of instructions issued 677system.cpu0.iq.iqSquashedInstsIssued 2619697 # Number of squashed instructions issued 678system.cpu0.iq.iqSquashedInstsExamined 52147933 # Number of squashed instructions iterated over during squash; mainly for profiling 679system.cpu0.iq.iqSquashedOperandsExamined 33732364 # Number of squashed operands that are examined and possibly removed from graph 680system.cpu0.iq.iqSquashedNonSpecRemoved 256005 # Number of squashed non-spec instructions that were removed 681system.cpu0.iq.issued_per_cycle::samples 729027925 # Number of insts issued each cycle 682system.cpu0.iq.issued_per_cycle::mean 0.795643 # Number of insts issued each cycle 683system.cpu0.iq.issued_per_cycle::stdev 1.062696 # Number of insts issued each cycle 684system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::0 413752637 56.75% 56.75% # Number of insts issued each cycle 686system.cpu0.iq.issued_per_cycle::1 130387752 17.89% 74.64% # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::2 112730807 15.46% 90.10% # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::3 64434367 8.84% 98.94% # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::4 7717956 1.06% 100.00% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::5 4406 0.00% 100.00% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::total 729027925 # Number of insts issued each cycle 698system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 699system.cpu0.iq.fu_full::IntAlu 60438369 45.47% 45.47% # attempts to use FU when none available 700system.cpu0.iq.fu_full::IntMult 47042 0.04% 45.50% # attempts to use FU when none available 701system.cpu0.iq.fu_full::IntDiv 17968 0.01% 45.52% # attempts to use FU when none available 702system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.52% # attempts to use FU when none available 703system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.52% # attempts to use FU when none available 704system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.52% # attempts to use FU when none available 705system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.52% # attempts to use FU when none available 706system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.52% # attempts to use FU when none available 707system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.52% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.52% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.52% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.52% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.52% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.52% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.52% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.52% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.52% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.52% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.52% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.52% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.52% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.52% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.52% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.52% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.52% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 45.52% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.52% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.52% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.52% # attempts to use FU when none available 728system.cpu0.iq.fu_full::MemRead 34488153 25.95% 71.46% # attempts to use FU when none available 729system.cpu0.iq.fu_full::MemWrite 37935532 28.54% 100.00% # attempts to use FU when none available 730system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 731system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 732system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued 733system.cpu0.iq.FU_type_0::IntAlu 396224561 68.31% 68.31% # Type of FU issued 734system.cpu0.iq.FU_type_0::IntMult 1355740 0.23% 68.54% # Type of FU issued 735system.cpu0.iq.FU_type_0::IntDiv 69556 0.01% 68.55% # Type of FU issued 736system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.55% # Type of FU issued 737system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued 738system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued 739system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued 740system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.55% # Type of FU issued 741system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.55% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.55% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdFloatCvt 26 0.00% 68.55% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatMisc 78264 0.01% 68.57% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued 762system.cpu0.iq.FU_type_0::MemRead 100394563 17.31% 85.88% # Type of FU issued 763system.cpu0.iq.FU_type_0::MemWrite 81923573 14.12% 100.00% # Type of FU issued 764system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 765system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 766system.cpu0.iq.FU_type_0::total 580046321 # Type of FU issued 767system.cpu0.iq.rate 0.766392 # Inst issue rate 768system.cpu0.iq.fu_busy_cnt 132927074 # FU busy when requested 769system.cpu0.iq.fu_busy_rate 0.229166 # FU busy rate (busy events/executed inst) 770system.cpu0.iq.int_inst_queue_reads 2023285471 # Number of integer instruction queue reads 771system.cpu0.iq.int_inst_queue_writes 642599747 # Number of integer instruction queue writes 772system.cpu0.iq.int_inst_queue_wakeup_accesses 563357563 # Number of integer instruction queue wakeup accesses 773system.cpu0.iq.fp_inst_queue_reads 1381865 # Number of floating instruction queue reads 774system.cpu0.iq.fp_inst_queue_writes 550084 # Number of floating instruction queue writes 775system.cpu0.iq.fp_inst_queue_wakeup_accesses 513487 # Number of floating instruction queue wakeup accesses 776system.cpu0.iq.int_alu_accesses 712117129 # Number of integer alu accesses 777system.cpu0.iq.fp_alu_accesses 856256 # Number of floating point alu accesses 778system.cpu0.iew.lsq.thread0.forwLoads 2617003 # Number of loads that had data forwarded from stores 779system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 780system.cpu0.iew.lsq.thread0.squashedLoads 11923389 # Number of loads squashed 781system.cpu0.iew.lsq.thread0.ignoredResponses 15941 # Number of memory responses ignored because the instruction is squashed 782system.cpu0.iew.lsq.thread0.memOrderViolation 140828 # Number of memory ordering violations 783system.cpu0.iew.lsq.thread0.squashedStores 5327299 # Number of stores squashed 784system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 785system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 786system.cpu0.iew.lsq.thread0.rescheduledLoads 2590097 # Number of loads that were rescheduled 787system.cpu0.iew.lsq.thread0.cacheBlocked 4396592 # Number of times an access to memory failed due to the cache being blocked 788system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 789system.cpu0.iew.iewSquashCycles 4986757 # Number of cycles IEW is squashing 790system.cpu0.iew.iewBlockCycles 6158595 # Number of cycles IEW is blocking 791system.cpu0.iew.iewUnblockCycles 2729815 # Number of cycles IEW is unblocking 792system.cpu0.iew.iewDispatchedInsts 590987234 # Number of instructions dispatched to IQ 793system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 794system.cpu0.iew.iewDispLoadInsts 97600013 # Number of dispatched load instructions 795system.cpu0.iew.iewDispStoreInsts 83873039 # Number of dispatched store instructions 796system.cpu0.iew.iewDispNonSpecInsts 12685897 # Number of dispatched non-speculative instructions 797system.cpu0.iew.iewIQFullEvents 60837 # Number of times the IQ has become full, causing a stall 798system.cpu0.iew.iewLSQFullEvents 2608142 # Number of times the LSQ has become full, causing a stall 799system.cpu0.iew.memOrderViolationEvents 140828 # Number of memory order violations 800system.cpu0.iew.predictedTakenIncorrect 1838258 # Number of branches that were predicted taken incorrectly 801system.cpu0.iew.predictedNotTakenIncorrect 2998999 # Number of branches that were predicted not taken incorrectly 802system.cpu0.iew.branchMispredicts 4837257 # Number of branch mispredicts detected at execute 803system.cpu0.iew.iewExecutedInsts 572331002 # Number of executed instructions 804system.cpu0.iew.iewExecLoadInsts 97377740 # Number of load instructions executed 805system.cpu0.iew.iewExecSquashedInsts 7191247 # Number of squashed instructions skipped in execute 806system.cpu0.iew.exec_swp 0 # number of swp insts executed 807system.cpu0.iew.exec_nop 125213 # number of nop insts executed 808system.cpu0.iew.exec_refs 178083928 # number of memory reference insts executed 809system.cpu0.iew.exec_branches 107921948 # Number of branches executed 810system.cpu0.iew.exec_stores 80706188 # Number of stores executed 811system.cpu0.iew.exec_rate 0.756198 # Inst execution rate 812system.cpu0.iew.wb_sent 564585754 # cumulative count of insts sent to commit 813system.cpu0.iew.wb_count 563871050 # cumulative count of insts written-back 814system.cpu0.iew.wb_producers 273627354 # num instructions producing a value 815system.cpu0.iew.wb_consumers 449179775 # num instructions consuming a value 816system.cpu0.iew.wb_rate 0.745020 # insts written-back per cycle 817system.cpu0.iew.wb_fanout 0.609171 # average fanout of values written-back 818system.cpu0.commit.commitSquashedInsts 45416795 # The number of squashed insts skipped by commit 819system.cpu0.commit.commitNonSpecStalls 14646672 # The number of times commit has been forced to stall to communicate backwards 820system.cpu0.commit.branchMispredicts 4504688 # The number of times a branch was mispredicted 821system.cpu0.commit.committed_per_cycle::samples 720395645 # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::mean 0.747803 # Number of insts commited each cycle 823system.cpu0.commit.committed_per_cycle::stdev 1.555225 # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::0 485771326 67.43% 67.43% # Number of insts commited each cycle 826system.cpu0.commit.committed_per_cycle::1 120512789 16.73% 84.16% # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::2 52399936 7.27% 91.43% # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::3 17702861 2.46% 93.89% # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::4 12776683 1.77% 95.66% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::5 8497825 1.18% 96.84% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::6 5820958 0.81% 97.65% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::7 3534904 0.49% 98.14% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::8 13378363 1.86% 100.00% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::total 720395645 # Number of insts commited each cycle 838system.cpu0.commit.committedInsts 458462253 # Number of instructions committed 839system.cpu0.commit.committedOps 538714081 # Number of ops (including micro ops) committed 840system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 841system.cpu0.commit.refs 164222361 # Number of memory references committed 842system.cpu0.commit.loads 85676622 # Number of loads committed 843system.cpu0.commit.membars 3641024 # Number of memory barriers committed 844system.cpu0.commit.branches 102649552 # Number of branches committed 845system.cpu0.commit.fp_insts 504968 # Number of committed floating point instructions. 846system.cpu0.commit.int_insts 494164906 # Number of committed integer instructions. 847system.cpu0.commit.function_calls 13432281 # Number of function calls committed. 848system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 849system.cpu0.commit.op_class_0::IntAlu 373237846 69.28% 69.28% # Class of committed instruction 850system.cpu0.commit.op_class_0::IntMult 1127454 0.21% 69.49% # Class of committed instruction 851system.cpu0.commit.op_class_0::IntDiv 54738 0.01% 69.50% # Class of committed instruction 852system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction 853system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction 854system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction 855system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction 856system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction 857system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction 859system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.50% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.50% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.50% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatMisc 71640 0.01% 69.52% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction 878system.cpu0.commit.op_class_0::MemRead 85676622 15.90% 85.42% # Class of committed instruction 879system.cpu0.commit.op_class_0::MemWrite 78545739 14.58% 100.00% # Class of committed instruction 880system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 881system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 882system.cpu0.commit.op_class_0::total 538714081 # Class of committed instruction 883system.cpu0.commit.bw_lim_events 13378363 # number cycles where commit BW limit reached 884system.cpu0.rob.rob_reads 1287287379 # The number of ROB reads 885system.cpu0.rob.rob_writes 1176858570 # The number of ROB writes 886system.cpu0.timesIdled 934729 # Number of times that the entire CPU went into an idle state and unscheduled itself 887system.cpu0.idleCycles 27825193 # Total number of cycles that the CPU has spent unscheduled due to idling 888system.cpu0.quiesceCycles 94022861092 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 889system.cpu0.committedInsts 458462253 # Number of Instructions Simulated 890system.cpu0.committedOps 538714081 # Number of Ops (including micro ops) Simulated 891system.cpu0.cpi 1.650852 # CPI: Cycles Per Instruction 892system.cpu0.cpi_total 1.650852 # CPI: Total CPI of All Threads 893system.cpu0.ipc 0.605748 # IPC: Instructions Per Cycle 894system.cpu0.ipc_total 0.605748 # IPC: Total IPC of All Threads 895system.cpu0.int_regfile_reads 675960762 # number of integer regfile reads 896system.cpu0.int_regfile_writes 401183302 # number of integer regfile writes 897system.cpu0.fp_regfile_reads 830771 # number of floating regfile reads 898system.cpu0.fp_regfile_writes 428332 # number of floating regfile writes 899system.cpu0.cc_regfile_reads 124727892 # number of cc regfile reads 900system.cpu0.cc_regfile_writes 125481667 # number of cc regfile writes 901system.cpu0.misc_regfile_reads 1276105833 # number of misc regfile reads 902system.cpu0.misc_regfile_writes 14867290 # number of misc regfile writes 903system.cpu0.dcache.tags.replacements 5765600 # number of replacements 904system.cpu0.dcache.tags.tagsinuse 490.322435 # Cycle average of tags in use 905system.cpu0.dcache.tags.total_refs 152640999 # Total number of references to valid blocks. 906system.cpu0.dcache.tags.sampled_refs 5766111 # Sample count of references to valid blocks. 907system.cpu0.dcache.tags.avg_refs 26.472088 # Average number of references to valid blocks. 908system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. 909system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.322435 # Average occupied blocks per requestor 910system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957661 # Average percentage of cache occupancy 911system.cpu0.dcache.tags.occ_percent::total 0.957661 # Average percentage of cache occupancy 912system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 913system.cpu0.dcache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id 914system.cpu0.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id 915system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 916system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 917system.cpu0.dcache.tags.tag_accesses 340447274 # Number of tag accesses 918system.cpu0.dcache.tags.data_accesses 340447274 # Number of data accesses 919system.cpu0.dcache.ReadReq_hits::cpu0.data 79408561 # number of ReadReq hits 920system.cpu0.dcache.ReadReq_hits::total 79408561 # number of ReadReq hits 921system.cpu0.dcache.WriteReq_hits::cpu0.data 68334031 # number of WriteReq hits 922system.cpu0.dcache.WriteReq_hits::total 68334031 # number of WriteReq hits 923system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200433 # number of SoftPFReq hits 924system.cpu0.dcache.SoftPFReq_hits::total 200433 # number of SoftPFReq hits 925system.cpu0.dcache.WriteLineReq_hits::cpu0.data 174121 # number of WriteLineReq hits 926system.cpu0.dcache.WriteLineReq_hits::total 174121 # number of WriteLineReq hits 927system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1831958 # number of LoadLockedReq hits 928system.cpu0.dcache.LoadLockedReq_hits::total 1831958 # number of LoadLockedReq hits 929system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849907 # number of StoreCondReq hits 930system.cpu0.dcache.StoreCondReq_hits::total 1849907 # number of StoreCondReq hits 931system.cpu0.dcache.demand_hits::cpu0.data 147742592 # number of demand (read+write) hits 932system.cpu0.dcache.demand_hits::total 147742592 # number of demand (read+write) hits 933system.cpu0.dcache.overall_hits::cpu0.data 147943025 # number of overall hits 934system.cpu0.dcache.overall_hits::total 147943025 # number of overall hits 935system.cpu0.dcache.ReadReq_misses::cpu0.data 6387707 # number of ReadReq misses 936system.cpu0.dcache.ReadReq_misses::total 6387707 # number of ReadReq misses 937system.cpu0.dcache.WriteReq_misses::cpu0.data 7192656 # number of WriteReq misses 938system.cpu0.dcache.WriteReq_misses::total 7192656 # number of WriteReq misses 939system.cpu0.dcache.SoftPFReq_misses::cpu0.data 686822 # number of SoftPFReq misses 940system.cpu0.dcache.SoftPFReq_misses::total 686822 # number of SoftPFReq misses 941system.cpu0.dcache.WriteLineReq_misses::cpu0.data 795953 # number of WriteLineReq misses 942system.cpu0.dcache.WriteLineReq_misses::total 795953 # number of WriteLineReq misses 943system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 241297 # number of LoadLockedReq misses 944system.cpu0.dcache.LoadLockedReq_misses::total 241297 # number of LoadLockedReq misses 945system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189319 # number of StoreCondReq misses 946system.cpu0.dcache.StoreCondReq_misses::total 189319 # number of StoreCondReq misses 947system.cpu0.dcache.demand_misses::cpu0.data 13580363 # number of demand (read+write) misses 948system.cpu0.dcache.demand_misses::total 13580363 # number of demand (read+write) misses 949system.cpu0.dcache.overall_misses::cpu0.data 14267185 # number of overall misses 950system.cpu0.dcache.overall_misses::total 14267185 # number of overall misses 951system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102145338500 # number of ReadReq miss cycles 952system.cpu0.dcache.ReadReq_miss_latency::total 102145338500 # number of ReadReq miss cycles 953system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 163649518808 # number of WriteReq miss cycles 954system.cpu0.dcache.WriteReq_miss_latency::total 163649518808 # number of WriteReq miss cycles 955system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 49996037023 # number of WriteLineReq miss cycles 956system.cpu0.dcache.WriteLineReq_miss_latency::total 49996037023 # number of WriteLineReq miss cycles 957system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3671046500 # number of LoadLockedReq miss cycles 958system.cpu0.dcache.LoadLockedReq_miss_latency::total 3671046500 # number of LoadLockedReq miss cycles 959system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5304166500 # number of StoreCondReq miss cycles 960system.cpu0.dcache.StoreCondReq_miss_latency::total 5304166500 # number of StoreCondReq miss cycles 961system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5694500 # number of StoreCondFailReq miss cycles 962system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5694500 # number of StoreCondFailReq miss cycles 963system.cpu0.dcache.demand_miss_latency::cpu0.data 265794857308 # number of demand (read+write) miss cycles 964system.cpu0.dcache.demand_miss_latency::total 265794857308 # number of demand (read+write) miss cycles 965system.cpu0.dcache.overall_miss_latency::cpu0.data 265794857308 # number of overall miss cycles 966system.cpu0.dcache.overall_miss_latency::total 265794857308 # number of overall miss cycles 967system.cpu0.dcache.ReadReq_accesses::cpu0.data 85796268 # number of ReadReq accesses(hits+misses) 968system.cpu0.dcache.ReadReq_accesses::total 85796268 # number of ReadReq accesses(hits+misses) 969system.cpu0.dcache.WriteReq_accesses::cpu0.data 75526687 # number of WriteReq accesses(hits+misses) 970system.cpu0.dcache.WriteReq_accesses::total 75526687 # number of WriteReq accesses(hits+misses) 971system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 887255 # number of SoftPFReq accesses(hits+misses) 972system.cpu0.dcache.SoftPFReq_accesses::total 887255 # number of SoftPFReq accesses(hits+misses) 973system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 970074 # number of WriteLineReq accesses(hits+misses) 974system.cpu0.dcache.WriteLineReq_accesses::total 970074 # number of WriteLineReq accesses(hits+misses) 975system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2073255 # number of LoadLockedReq accesses(hits+misses) 976system.cpu0.dcache.LoadLockedReq_accesses::total 2073255 # number of LoadLockedReq accesses(hits+misses) 977system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2039226 # number of StoreCondReq accesses(hits+misses) 978system.cpu0.dcache.StoreCondReq_accesses::total 2039226 # number of StoreCondReq accesses(hits+misses) 979system.cpu0.dcache.demand_accesses::cpu0.data 161322955 # number of demand (read+write) accesses 980system.cpu0.dcache.demand_accesses::total 161322955 # number of demand (read+write) accesses 981system.cpu0.dcache.overall_accesses::cpu0.data 162210210 # number of overall (read+write) accesses 982system.cpu0.dcache.overall_accesses::total 162210210 # number of overall (read+write) accesses 983system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074452 # miss rate for ReadReq accesses 984system.cpu0.dcache.ReadReq_miss_rate::total 0.074452 # miss rate for ReadReq accesses 985system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095233 # miss rate for WriteReq accesses 986system.cpu0.dcache.WriteReq_miss_rate::total 0.095233 # miss rate for WriteReq accesses 987system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774098 # miss rate for SoftPFReq accesses 988system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774098 # miss rate for SoftPFReq accesses 989system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.820508 # miss rate for WriteLineReq accesses 990system.cpu0.dcache.WriteLineReq_miss_rate::total 0.820508 # miss rate for WriteLineReq accesses 991system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.116386 # miss rate for LoadLockedReq accesses 992system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.116386 # miss rate for LoadLockedReq accesses 993system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092839 # miss rate for StoreCondReq accesses 994system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092839 # miss rate for StoreCondReq accesses 995system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084181 # miss rate for demand accesses 996system.cpu0.dcache.demand_miss_rate::total 0.084181 # miss rate for demand accesses 997system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087955 # miss rate for overall accesses 998system.cpu0.dcache.overall_miss_rate::total 0.087955 # miss rate for overall accesses 999system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15990.924208 # average ReadReq miss latency 1000system.cpu0.dcache.ReadReq_avg_miss_latency::total 15990.924208 # average ReadReq miss latency 1001system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 22752.307188 # average WriteReq miss latency 1002system.cpu0.dcache.WriteReq_avg_miss_latency::total 22752.307188 # average WriteReq miss latency 1003system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62812.800533 # average WriteLineReq miss latency 1004system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62812.800533 # average WriteLineReq miss latency 1005system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.809123 # average LoadLockedReq miss latency 1006system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.809123 # average LoadLockedReq miss latency 1007system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28017.084920 # average StoreCondReq miss latency 1008system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28017.084920 # average StoreCondReq miss latency 1009system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1010system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1011system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19571.999460 # average overall miss latency 1012system.cpu0.dcache.demand_avg_miss_latency::total 19571.999460 # average overall miss latency 1013system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18629.803799 # average overall miss latency 1014system.cpu0.dcache.overall_avg_miss_latency::total 18629.803799 # average overall miss latency 1015system.cpu0.dcache.blocked_cycles::no_mshrs 15450587 # number of cycles access was blocked 1016system.cpu0.dcache.blocked_cycles::no_targets 24201430 # number of cycles access was blocked 1017system.cpu0.dcache.blocked::no_mshrs 734789 # number of cycles access was blocked 1018system.cpu0.dcache.blocked::no_targets 699058 # number of cycles access was blocked 1019system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.027243 # average number of cycles each access was blocked 1020system.cpu0.dcache.avg_blocked_cycles::no_targets 34.620060 # average number of cycles each access was blocked 1021system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1022system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1023system.cpu0.dcache.writebacks::writebacks 5765616 # number of writebacks 1024system.cpu0.dcache.writebacks::total 5765616 # number of writebacks 1025system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3289806 # number of ReadReq MSHR hits 1026system.cpu0.dcache.ReadReq_mshr_hits::total 3289806 # number of ReadReq MSHR hits 1027system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5763001 # number of WriteReq MSHR hits 1028system.cpu0.dcache.WriteReq_mshr_hits::total 5763001 # number of WriteReq MSHR hits 1029system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4255 # number of WriteLineReq MSHR hits 1030system.cpu0.dcache.WriteLineReq_mshr_hits::total 4255 # number of WriteLineReq MSHR hits 1031system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 124637 # number of LoadLockedReq MSHR hits 1032system.cpu0.dcache.LoadLockedReq_mshr_hits::total 124637 # number of LoadLockedReq MSHR hits 1033system.cpu0.dcache.demand_mshr_hits::cpu0.data 9052807 # number of demand (read+write) MSHR hits 1034system.cpu0.dcache.demand_mshr_hits::total 9052807 # number of demand (read+write) MSHR hits 1035system.cpu0.dcache.overall_mshr_hits::cpu0.data 9052807 # number of overall MSHR hits 1036system.cpu0.dcache.overall_mshr_hits::total 9052807 # number of overall MSHR hits 1037system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3097901 # number of ReadReq MSHR misses 1038system.cpu0.dcache.ReadReq_mshr_misses::total 3097901 # number of ReadReq MSHR misses 1039system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1429655 # number of WriteReq MSHR misses 1040system.cpu0.dcache.WriteReq_mshr_misses::total 1429655 # number of WriteReq MSHR misses 1041system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679876 # number of SoftPFReq MSHR misses 1042system.cpu0.dcache.SoftPFReq_mshr_misses::total 679876 # number of SoftPFReq MSHR misses 1043system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 791698 # number of WriteLineReq MSHR misses 1044system.cpu0.dcache.WriteLineReq_mshr_misses::total 791698 # number of WriteLineReq MSHR misses 1045system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116660 # number of LoadLockedReq MSHR misses 1046system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116660 # number of LoadLockedReq MSHR misses 1047system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189313 # number of StoreCondReq MSHR misses 1048system.cpu0.dcache.StoreCondReq_mshr_misses::total 189313 # number of StoreCondReq MSHR misses 1049system.cpu0.dcache.demand_mshr_misses::cpu0.data 4527556 # number of demand (read+write) MSHR misses 1050system.cpu0.dcache.demand_mshr_misses::total 4527556 # number of demand (read+write) MSHR misses 1051system.cpu0.dcache.overall_mshr_misses::cpu0.data 5207432 # number of overall MSHR misses 1052system.cpu0.dcache.overall_mshr_misses::total 5207432 # number of overall MSHR misses 1053system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19295 # number of ReadReq MSHR uncacheable 1054system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19295 # number of ReadReq MSHR uncacheable 1055system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 20724 # number of WriteReq MSHR uncacheable 1056system.cpu0.dcache.WriteReq_mshr_uncacheable::total 20724 # number of WriteReq MSHR uncacheable 1057system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40019 # number of overall MSHR uncacheable misses 1058system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40019 # number of overall MSHR uncacheable misses 1059system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47331591500 # number of ReadReq MSHR miss cycles 1060system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47331591500 # number of ReadReq MSHR miss cycles 1061system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38044472455 # number of WriteReq MSHR miss cycles 1062system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38044472455 # number of WriteReq MSHR miss cycles 1063system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16657786000 # number of SoftPFReq MSHR miss cycles 1064system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16657786000 # number of SoftPFReq MSHR miss cycles 1065system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 48937488023 # number of WriteLineReq MSHR miss cycles 1066system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 48937488023 # number of WriteLineReq MSHR miss cycles 1067system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1685431500 # number of LoadLockedReq MSHR miss cycles 1068system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1685431500 # number of LoadLockedReq MSHR miss cycles 1069system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5114922500 # number of StoreCondReq MSHR miss cycles 1070system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5114922500 # number of StoreCondReq MSHR miss cycles 1071system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5625500 # number of StoreCondFailReq MSHR miss cycles 1072system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5625500 # number of StoreCondFailReq MSHR miss cycles 1073system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85376063955 # number of demand (read+write) MSHR miss cycles 1074system.cpu0.dcache.demand_mshr_miss_latency::total 85376063955 # number of demand (read+write) MSHR miss cycles 1075system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102033849955 # number of overall MSHR miss cycles 1076system.cpu0.dcache.overall_mshr_miss_latency::total 102033849955 # number of overall MSHR miss cycles 1077system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3789852000 # number of ReadReq MSHR uncacheable cycles 1078system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3789852000 # number of ReadReq MSHR uncacheable cycles 1079system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3941977500 # number of WriteReq MSHR uncacheable cycles 1080system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3941977500 # number of WriteReq MSHR uncacheable cycles 1081system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7731829500 # number of overall MSHR uncacheable cycles 1082system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7731829500 # number of overall MSHR uncacheable cycles 1083system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036108 # mshr miss rate for ReadReq accesses 1084system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036108 # mshr miss rate for ReadReq accesses 1085system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018929 # mshr miss rate for WriteReq accesses 1086system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018929 # mshr miss rate for WriteReq accesses 1087system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.766269 # mshr miss rate for SoftPFReq accesses 1088system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.766269 # mshr miss rate for SoftPFReq accesses 1089system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.816121 # mshr miss rate for WriteLineReq accesses 1090system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.816121 # mshr miss rate for WriteLineReq accesses 1091system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056269 # mshr miss rate for LoadLockedReq accesses 1092system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056269 # mshr miss rate for LoadLockedReq accesses 1093system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092836 # mshr miss rate for StoreCondReq accesses 1094system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092836 # mshr miss rate for StoreCondReq accesses 1095system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028065 # mshr miss rate for demand accesses 1096system.cpu0.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses 1097system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032103 # mshr miss rate for overall accesses 1098system.cpu0.dcache.overall_mshr_miss_rate::total 0.032103 # mshr miss rate for overall accesses 1099system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15278.600414 # average ReadReq mshr miss latency 1100system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15278.600414 # average ReadReq mshr miss latency 1101system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26610.946316 # average WriteReq mshr miss latency 1102system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26610.946316 # average WriteReq mshr miss latency 1103system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24501.211986 # average SoftPFReq mshr miss latency 1104system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24501.211986 # average SoftPFReq mshr miss latency 1105system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61813.327838 # average WriteLineReq mshr miss latency 1106system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61813.327838 # average WriteLineReq mshr miss latency 1107system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14447.381279 # average LoadLockedReq mshr miss latency 1108system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14447.381279 # average LoadLockedReq mshr miss latency 1109system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27018.337357 # average StoreCondReq mshr miss latency 1110system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27018.337357 # average StoreCondReq mshr miss latency 1111system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1112system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1113system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18856.986850 # average overall mshr miss latency 1114system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18856.986850 # average overall mshr miss latency 1115system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19593.890032 # average overall mshr miss latency 1116system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19593.890032 # average overall mshr miss latency 1117system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196416.273646 # average ReadReq mshr uncacheable latency 1118system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196416.273646 # average ReadReq mshr uncacheable latency 1119system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 190213.158657 # average WriteReq mshr uncacheable latency 1120system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190213.158657 # average WriteReq mshr uncacheable latency 1121system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193203.965616 # average overall mshr uncacheable latency 1122system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193203.965616 # average overall mshr uncacheable latency 1123system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1124system.cpu0.icache.tags.replacements 5849403 # number of replacements 1125system.cpu0.icache.tags.tagsinuse 511.943926 # Cycle average of tags in use 1126system.cpu0.icache.tags.total_refs 203506939 # Total number of references to valid blocks. 1127system.cpu0.icache.tags.sampled_refs 5849915 # Sample count of references to valid blocks. 1128system.cpu0.icache.tags.avg_refs 34.788016 # Average number of references to valid blocks. 1129system.cpu0.icache.tags.warmup_cycle 18014203000 # Cycle when the warmup percentage was hit. 1130system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943926 # Average occupied blocks per requestor 1131system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999890 # Average percentage of cache occupancy 1132system.cpu0.icache.tags.occ_percent::total 0.999890 # Average percentage of cache occupancy 1133system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1134system.cpu0.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1135system.cpu0.icache.tags.age_task_id_blocks_1024::1 457 # Occupied blocks per task id 1136system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 1137system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1138system.cpu0.icache.tags.tag_accesses 425234482 # Number of tag accesses 1139system.cpu0.icache.tags.data_accesses 425234482 # Number of data accesses 1140system.cpu0.icache.ReadReq_hits::cpu0.inst 203506939 # number of ReadReq hits 1141system.cpu0.icache.ReadReq_hits::total 203506939 # number of ReadReq hits 1142system.cpu0.icache.demand_hits::cpu0.inst 203506939 # number of demand (read+write) hits 1143system.cpu0.icache.demand_hits::total 203506939 # number of demand (read+write) hits 1144system.cpu0.icache.overall_hits::cpu0.inst 203506939 # number of overall hits 1145system.cpu0.icache.overall_hits::total 203506939 # number of overall hits 1146system.cpu0.icache.ReadReq_misses::cpu0.inst 6185325 # number of ReadReq misses 1147system.cpu0.icache.ReadReq_misses::total 6185325 # number of ReadReq misses 1148system.cpu0.icache.demand_misses::cpu0.inst 6185325 # number of demand (read+write) misses 1149system.cpu0.icache.demand_misses::total 6185325 # number of demand (read+write) misses 1150system.cpu0.icache.overall_misses::cpu0.inst 6185325 # number of overall misses 1151system.cpu0.icache.overall_misses::total 6185325 # number of overall misses 1152system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 68820233655 # number of ReadReq miss cycles 1153system.cpu0.icache.ReadReq_miss_latency::total 68820233655 # number of ReadReq miss cycles 1154system.cpu0.icache.demand_miss_latency::cpu0.inst 68820233655 # number of demand (read+write) miss cycles 1155system.cpu0.icache.demand_miss_latency::total 68820233655 # number of demand (read+write) miss cycles 1156system.cpu0.icache.overall_miss_latency::cpu0.inst 68820233655 # number of overall miss cycles 1157system.cpu0.icache.overall_miss_latency::total 68820233655 # number of overall miss cycles 1158system.cpu0.icache.ReadReq_accesses::cpu0.inst 209692264 # number of ReadReq accesses(hits+misses) 1159system.cpu0.icache.ReadReq_accesses::total 209692264 # number of ReadReq accesses(hits+misses) 1160system.cpu0.icache.demand_accesses::cpu0.inst 209692264 # number of demand (read+write) accesses 1161system.cpu0.icache.demand_accesses::total 209692264 # number of demand (read+write) accesses 1162system.cpu0.icache.overall_accesses::cpu0.inst 209692264 # number of overall (read+write) accesses 1163system.cpu0.icache.overall_accesses::total 209692264 # number of overall (read+write) accesses 1164system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029497 # miss rate for ReadReq accesses 1165system.cpu0.icache.ReadReq_miss_rate::total 0.029497 # miss rate for ReadReq accesses 1166system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029497 # miss rate for demand accesses 1167system.cpu0.icache.demand_miss_rate::total 0.029497 # miss rate for demand accesses 1168system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029497 # miss rate for overall accesses 1169system.cpu0.icache.overall_miss_rate::total 0.029497 # miss rate for overall accesses 1170system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11126.373094 # average ReadReq miss latency 1171system.cpu0.icache.ReadReq_avg_miss_latency::total 11126.373094 # average ReadReq miss latency 1172system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11126.373094 # average overall miss latency 1173system.cpu0.icache.demand_avg_miss_latency::total 11126.373094 # average overall miss latency 1174system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11126.373094 # average overall miss latency 1175system.cpu0.icache.overall_avg_miss_latency::total 11126.373094 # average overall miss latency 1176system.cpu0.icache.blocked_cycles::no_mshrs 10317197 # number of cycles access was blocked 1177system.cpu0.icache.blocked_cycles::no_targets 1776 # number of cycles access was blocked 1178system.cpu0.icache.blocked::no_mshrs 708038 # number of cycles access was blocked 1179system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked 1180system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.571530 # average number of cycles each access was blocked 1181system.cpu0.icache.avg_blocked_cycles::no_targets 118.400000 # average number of cycles each access was blocked 1182system.cpu0.icache.fast_writes 0 # number of fast writes performed 1183system.cpu0.icache.cache_copies 0 # number of cache copies performed 1184system.cpu0.icache.writebacks::writebacks 5849403 # number of writebacks 1185system.cpu0.icache.writebacks::total 5849403 # number of writebacks 1186system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 335371 # number of ReadReq MSHR hits 1187system.cpu0.icache.ReadReq_mshr_hits::total 335371 # number of ReadReq MSHR hits 1188system.cpu0.icache.demand_mshr_hits::cpu0.inst 335371 # number of demand (read+write) MSHR hits 1189system.cpu0.icache.demand_mshr_hits::total 335371 # number of demand (read+write) MSHR hits 1190system.cpu0.icache.overall_mshr_hits::cpu0.inst 335371 # number of overall MSHR hits 1191system.cpu0.icache.overall_mshr_hits::total 335371 # number of overall MSHR hits 1192system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5849954 # number of ReadReq MSHR misses 1193system.cpu0.icache.ReadReq_mshr_misses::total 5849954 # number of ReadReq MSHR misses 1194system.cpu0.icache.demand_mshr_misses::cpu0.inst 5849954 # number of demand (read+write) MSHR misses 1195system.cpu0.icache.demand_mshr_misses::total 5849954 # number of demand (read+write) MSHR misses 1196system.cpu0.icache.overall_mshr_misses::cpu0.inst 5849954 # number of overall MSHR misses 1197system.cpu0.icache.overall_mshr_misses::total 5849954 # number of overall MSHR misses 1198system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1199system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1200system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1201system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 1202system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62003791719 # number of ReadReq MSHR miss cycles 1203system.cpu0.icache.ReadReq_mshr_miss_latency::total 62003791719 # number of ReadReq MSHR miss cycles 1204system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62003791719 # number of demand (read+write) MSHR miss cycles 1205system.cpu0.icache.demand_mshr_miss_latency::total 62003791719 # number of demand (read+write) MSHR miss cycles 1206system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62003791719 # number of overall MSHR miss cycles 1207system.cpu0.icache.overall_mshr_miss_latency::total 62003791719 # number of overall MSHR miss cycles 1208system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of ReadReq MSHR uncacheable cycles 1209system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780498 # number of ReadReq MSHR uncacheable cycles 1210system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of overall MSHR uncacheable cycles 1211system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780498 # number of overall MSHR uncacheable cycles 1212system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027898 # mshr miss rate for ReadReq accesses 1213system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027898 # mshr miss rate for ReadReq accesses 1214system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027898 # mshr miss rate for demand accesses 1215system.cpu0.icache.demand_mshr_miss_rate::total 0.027898 # mshr miss rate for demand accesses 1216system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027898 # mshr miss rate for overall accesses 1217system.cpu0.icache.overall_mshr_miss_rate::total 0.027898 # mshr miss rate for overall accesses 1218system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.022098 # average ReadReq mshr miss latency 1219system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.022098 # average ReadReq mshr miss latency 1220system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.022098 # average overall mshr miss latency 1221system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.022098 # average overall mshr miss latency 1222system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.022098 # average overall mshr miss latency 1223system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.022098 # average overall mshr miss latency 1224system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average ReadReq mshr uncacheable latency 1225system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651 # average ReadReq mshr uncacheable latency 1226system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average overall mshr uncacheable latency 1227system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651 # average overall mshr uncacheable latency 1228system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1229system.cpu0.l2cache.prefetcher.num_hwpf_issued 7728604 # number of hwpf issued 1230system.cpu0.l2cache.prefetcher.pfIdentified 7739029 # number of prefetch candidates identified 1231system.cpu0.l2cache.prefetcher.pfBufferHit 9391 # number of redundant prefetches already in prefetch queue 1232system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1233system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1234system.cpu0.l2cache.prefetcher.pfSpanPage 1009379 # number of prefetches not generated due to page crossing 1235system.cpu0.l2cache.tags.replacements 2564693 # number of replacements 1236system.cpu0.l2cache.tags.tagsinuse 16115.455050 # Cycle average of tags in use 1237system.cpu0.l2cache.tags.total_refs 16793989 # Total number of references to valid blocks. 1238system.cpu0.l2cache.tags.sampled_refs 2580455 # Sample count of references to valid blocks. 1239system.cpu0.l2cache.tags.avg_refs 6.508150 # Average number of references to valid blocks. 1240system.cpu0.l2cache.tags.warmup_cycle 3423391000 # Cycle when the warmup percentage was hit. 1241system.cpu0.l2cache.tags.occ_blocks::writebacks 15189.817195 # Average occupied blocks per requestor 1242system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.994619 # Average occupied blocks per requestor 1243system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 35.520086 # Average occupied blocks per requestor 1244system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.176107 # Average occupied blocks per requestor 1245system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 837.947042 # Average occupied blocks per requestor 1246system.cpu0.l2cache.tags.occ_percent::writebacks 0.927113 # Average percentage of cache occupancy 1247system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003173 # Average percentage of cache occupancy 1248system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002168 # Average percentage of cache occupancy 1249system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000011 # Average percentage of cache occupancy 1250system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051144 # Average percentage of cache occupancy 1251system.cpu0.l2cache.tags.occ_percent::total 0.983609 # Average percentage of cache occupancy 1252system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1242 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14441 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 78 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 110 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 653 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 401 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 26 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1001 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5348 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4520 # Occupied blocks per task id 1267system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3402 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.075806 # Percentage of cache occupancy per task id 1269system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 1270system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.881409 # Percentage of cache occupancy per task id 1271system.cpu0.l2cache.tags.tag_accesses 398023302 # Number of tag accesses 1272system.cpu0.l2cache.tags.data_accesses 398023302 # Number of data accesses 1273system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 546484 # number of ReadReq hits 1274system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 178619 # number of ReadReq hits 1275system.cpu0.l2cache.ReadReq_hits::total 725103 # number of ReadReq hits 1276system.cpu0.l2cache.WritebackDirty_hits::writebacks 3848803 # number of WritebackDirty hits 1277system.cpu0.l2cache.WritebackDirty_hits::total 3848803 # number of WritebackDirty hits 1278system.cpu0.l2cache.WritebackClean_hits::writebacks 7764047 # number of WritebackClean hits 1279system.cpu0.l2cache.WritebackClean_hits::total 7764047 # number of WritebackClean hits 1280system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 499 # number of UpgradeReq hits 1281system.cpu0.l2cache.UpgradeReq_hits::total 499 # number of UpgradeReq hits 1282system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits 1283system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits 1284system.cpu0.l2cache.ReadExReq_hits::cpu0.data 861581 # number of ReadExReq hits 1285system.cpu0.l2cache.ReadExReq_hits::total 861581 # number of ReadExReq hits 1286system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5300527 # number of ReadCleanReq hits 1287system.cpu0.l2cache.ReadCleanReq_hits::total 5300527 # number of ReadCleanReq hits 1288system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2904826 # number of ReadSharedReq hits 1289system.cpu0.l2cache.ReadSharedReq_hits::total 2904826 # number of ReadSharedReq hits 1290system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 194350 # number of InvalidateReq hits 1291system.cpu0.l2cache.InvalidateReq_hits::total 194350 # number of InvalidateReq hits 1292system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 546484 # number of demand (read+write) hits 1293system.cpu0.l2cache.demand_hits::cpu0.itb.walker 178619 # number of demand (read+write) hits 1294system.cpu0.l2cache.demand_hits::cpu0.inst 5300527 # number of demand (read+write) hits 1295system.cpu0.l2cache.demand_hits::cpu0.data 3766407 # number of demand (read+write) hits 1296system.cpu0.l2cache.demand_hits::total 9792037 # number of demand (read+write) hits 1297system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 546484 # number of overall hits 1298system.cpu0.l2cache.overall_hits::cpu0.itb.walker 178619 # number of overall hits 1299system.cpu0.l2cache.overall_hits::cpu0.inst 5300527 # number of overall hits 1300system.cpu0.l2cache.overall_hits::cpu0.data 3766407 # number of overall hits 1301system.cpu0.l2cache.overall_hits::total 9792037 # number of overall hits 1302system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11083 # number of ReadReq misses 1303system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7410 # number of ReadReq misses 1304system.cpu0.l2cache.ReadReq_misses::total 18493 # number of ReadReq misses 1305system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 1306system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 1307system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses 1308system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses 1309system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 259441 # number of UpgradeReq misses 1310system.cpu0.l2cache.UpgradeReq_misses::total 259441 # number of UpgradeReq misses 1311system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 189304 # number of SCUpgradeReq misses 1312system.cpu0.l2cache.SCUpgradeReq_misses::total 189304 # number of SCUpgradeReq misses 1313system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 1314system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1315system.cpu0.l2cache.ReadExReq_misses::cpu0.data 319873 # number of ReadExReq misses 1316system.cpu0.l2cache.ReadExReq_misses::total 319873 # number of ReadExReq misses 1317system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 549397 # number of ReadCleanReq misses 1318system.cpu0.l2cache.ReadCleanReq_misses::total 549397 # number of ReadCleanReq misses 1319system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 986020 # number of ReadSharedReq misses 1320system.cpu0.l2cache.ReadSharedReq_misses::total 986020 # number of ReadSharedReq misses 1321system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 595026 # number of InvalidateReq misses 1322system.cpu0.l2cache.InvalidateReq_misses::total 595026 # number of InvalidateReq misses 1323system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11083 # number of demand (read+write) misses 1324system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7410 # number of demand (read+write) misses 1325system.cpu0.l2cache.demand_misses::cpu0.inst 549397 # number of demand (read+write) misses 1326system.cpu0.l2cache.demand_misses::cpu0.data 1305893 # number of demand (read+write) misses 1327system.cpu0.l2cache.demand_misses::total 1873783 # number of demand (read+write) misses 1328system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11083 # number of overall misses 1329system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7410 # number of overall misses 1330system.cpu0.l2cache.overall_misses::cpu0.inst 549397 # number of overall misses 1331system.cpu0.l2cache.overall_misses::cpu0.data 1305893 # number of overall misses 1332system.cpu0.l2cache.overall_misses::total 1873783 # number of overall misses 1333system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 482796500 # number of ReadReq miss cycles 1334system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 312182000 # number of ReadReq miss cycles 1335system.cpu0.l2cache.ReadReq_miss_latency::total 794978500 # number of ReadReq miss cycles 1336system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3412861500 # number of UpgradeReq miss cycles 1337system.cpu0.l2cache.UpgradeReq_miss_latency::total 3412861500 # number of UpgradeReq miss cycles 1338system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1849978000 # number of SCUpgradeReq miss cycles 1339system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1849978000 # number of SCUpgradeReq miss cycles 1340system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5522000 # number of SCUpgradeFailReq miss cycles 1341system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5522000 # number of SCUpgradeFailReq miss cycles 1342system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 20457541498 # number of ReadExReq miss cycles 1343system.cpu0.l2cache.ReadExReq_miss_latency::total 20457541498 # number of ReadExReq miss cycles 1344system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 21120469998 # number of ReadCleanReq miss cycles 1345system.cpu0.l2cache.ReadCleanReq_miss_latency::total 21120469998 # number of ReadCleanReq miss cycles 1346system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40452425974 # number of ReadSharedReq miss cycles 1347system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40452425974 # number of ReadSharedReq miss cycles 1348system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 524579500 # number of InvalidateReq miss cycles 1349system.cpu0.l2cache.InvalidateReq_miss_latency::total 524579500 # number of InvalidateReq miss cycles 1350system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 482796500 # number of demand (read+write) miss cycles 1351system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 312182000 # number of demand (read+write) miss cycles 1352system.cpu0.l2cache.demand_miss_latency::cpu0.inst 21120469998 # number of demand (read+write) miss cycles 1353system.cpu0.l2cache.demand_miss_latency::cpu0.data 60909967472 # number of demand (read+write) miss cycles 1354system.cpu0.l2cache.demand_miss_latency::total 82825415970 # number of demand (read+write) miss cycles 1355system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 482796500 # number of overall miss cycles 1356system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 312182000 # number of overall miss cycles 1357system.cpu0.l2cache.overall_miss_latency::cpu0.inst 21120469998 # number of overall miss cycles 1358system.cpu0.l2cache.overall_miss_latency::cpu0.data 60909967472 # number of overall miss cycles 1359system.cpu0.l2cache.overall_miss_latency::total 82825415970 # number of overall miss cycles 1360system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 557567 # number of ReadReq accesses(hits+misses) 1361system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 186029 # number of ReadReq accesses(hits+misses) 1362system.cpu0.l2cache.ReadReq_accesses::total 743596 # number of ReadReq accesses(hits+misses) 1363system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3848804 # number of WritebackDirty accesses(hits+misses) 1364system.cpu0.l2cache.WritebackDirty_accesses::total 3848804 # number of WritebackDirty accesses(hits+misses) 1365system.cpu0.l2cache.WritebackClean_accesses::writebacks 7764049 # number of WritebackClean accesses(hits+misses) 1366system.cpu0.l2cache.WritebackClean_accesses::total 7764049 # number of WritebackClean accesses(hits+misses) 1367system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 259940 # number of UpgradeReq accesses(hits+misses) 1368system.cpu0.l2cache.UpgradeReq_accesses::total 259940 # number of UpgradeReq accesses(hits+misses) 1369system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189309 # number of SCUpgradeReq accesses(hits+misses) 1370system.cpu0.l2cache.SCUpgradeReq_accesses::total 189309 # number of SCUpgradeReq accesses(hits+misses) 1371system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1372system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1373system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1181454 # number of ReadExReq accesses(hits+misses) 1374system.cpu0.l2cache.ReadExReq_accesses::total 1181454 # number of ReadExReq accesses(hits+misses) 1375system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5849924 # number of ReadCleanReq accesses(hits+misses) 1376system.cpu0.l2cache.ReadCleanReq_accesses::total 5849924 # number of ReadCleanReq accesses(hits+misses) 1377system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3890846 # number of ReadSharedReq accesses(hits+misses) 1378system.cpu0.l2cache.ReadSharedReq_accesses::total 3890846 # number of ReadSharedReq accesses(hits+misses) 1379system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 789376 # number of InvalidateReq accesses(hits+misses) 1380system.cpu0.l2cache.InvalidateReq_accesses::total 789376 # number of InvalidateReq accesses(hits+misses) 1381system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 557567 # number of demand (read+write) accesses 1382system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 186029 # number of demand (read+write) accesses 1383system.cpu0.l2cache.demand_accesses::cpu0.inst 5849924 # number of demand (read+write) accesses 1384system.cpu0.l2cache.demand_accesses::cpu0.data 5072300 # number of demand (read+write) accesses 1385system.cpu0.l2cache.demand_accesses::total 11665820 # number of demand (read+write) accesses 1386system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 557567 # number of overall (read+write) accesses 1387system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 186029 # number of overall (read+write) accesses 1388system.cpu0.l2cache.overall_accesses::cpu0.inst 5849924 # number of overall (read+write) accesses 1389system.cpu0.l2cache.overall_accesses::cpu0.data 5072300 # number of overall (read+write) accesses 1390system.cpu0.l2cache.overall_accesses::total 11665820 # number of overall (read+write) accesses 1391system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019877 # miss rate for ReadReq accesses 1392system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039832 # miss rate for ReadReq accesses 1393system.cpu0.l2cache.ReadReq_miss_rate::total 0.024870 # miss rate for ReadReq accesses 1394system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 1395system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 1396system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1397system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1398system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998080 # miss rate for UpgradeReq accesses 1399system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998080 # miss rate for UpgradeReq accesses 1400system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999974 # miss rate for SCUpgradeReq accesses 1401system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999974 # miss rate for SCUpgradeReq accesses 1402system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1403system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1404system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.270745 # miss rate for ReadExReq accesses 1405system.cpu0.l2cache.ReadExReq_miss_rate::total 0.270745 # miss rate for ReadExReq accesses 1406system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.093915 # miss rate for ReadCleanReq accesses 1407system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.093915 # miss rate for ReadCleanReq accesses 1408system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.253420 # miss rate for ReadSharedReq accesses 1409system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.253420 # miss rate for ReadSharedReq accesses 1410system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.753793 # miss rate for InvalidateReq accesses 1411system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.753793 # miss rate for InvalidateReq accesses 1412system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019877 # miss rate for demand accesses 1413system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039832 # miss rate for demand accesses 1414system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.093915 # miss rate for demand accesses 1415system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.257456 # miss rate for demand accesses 1416system.cpu0.l2cache.demand_miss_rate::total 0.160622 # miss rate for demand accesses 1417system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019877 # miss rate for overall accesses 1418system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039832 # miss rate for overall accesses 1419system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.093915 # miss rate for overall accesses 1420system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.257456 # miss rate for overall accesses 1421system.cpu0.l2cache.overall_miss_rate::total 0.160622 # miss rate for overall accesses 1422system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43561.896598 # average ReadReq miss latency 1423system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42129.824561 # average ReadReq miss latency 1424system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42988.076570 # average ReadReq miss latency 1425system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13154.672931 # average UpgradeReq miss latency 1426system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13154.672931 # average UpgradeReq miss latency 1427system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9772.524616 # average SCUpgradeReq miss latency 1428system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9772.524616 # average SCUpgradeReq miss latency 1429system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1380500 # average SCUpgradeFailReq miss latency 1430system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1380500 # average SCUpgradeFailReq miss latency 1431system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63955.199401 # average ReadExReq miss latency 1432system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63955.199401 # average ReadExReq miss latency 1433system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38443.002051 # average ReadCleanReq miss latency 1434system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38443.002051 # average ReadCleanReq miss latency 1435system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41025.969021 # average ReadSharedReq miss latency 1436system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41025.969021 # average ReadSharedReq miss latency 1437system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 881.607694 # average InvalidateReq miss latency 1438system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 881.607694 # average InvalidateReq miss latency 1439system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43561.896598 # average overall miss latency 1440system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42129.824561 # average overall miss latency 1441system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38443.002051 # average overall miss latency 1442system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46642.387601 # average overall miss latency 1443system.cpu0.l2cache.demand_avg_miss_latency::total 44202.245388 # average overall miss latency 1444system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43561.896598 # average overall miss latency 1445system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42129.824561 # average overall miss latency 1446system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38443.002051 # average overall miss latency 1447system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46642.387601 # average overall miss latency 1448system.cpu0.l2cache.overall_avg_miss_latency::total 44202.245388 # average overall miss latency 1449system.cpu0.l2cache.blocked_cycles::no_mshrs 731 # number of cycles access was blocked 1450system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1451system.cpu0.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked 1452system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1453system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 91.375000 # average number of cycles each access was blocked 1454system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1455system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1456system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1457system.cpu0.l2cache.unused_prefetches 42139 # number of HardPF blocks evicted w/o reference 1458system.cpu0.l2cache.writebacks::writebacks 1615717 # number of writebacks 1459system.cpu0.l2cache.writebacks::total 1615717 # number of writebacks 1460system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 6 # number of ReadReq MSHR hits 1461system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 11 # number of ReadReq MSHR hits 1462system.cpu0.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 1463system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 41013 # number of ReadExReq MSHR hits 1464system.cpu0.l2cache.ReadExReq_mshr_hits::total 41013 # number of ReadExReq MSHR hits 1465system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 5 # number of ReadCleanReq MSHR hits 1466system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 1467system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5478 # number of ReadSharedReq MSHR hits 1468system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5478 # number of ReadSharedReq MSHR hits 1469system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 13 # number of InvalidateReq MSHR hits 1470system.cpu0.l2cache.InvalidateReq_mshr_hits::total 13 # number of InvalidateReq MSHR hits 1471system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 6 # number of demand (read+write) MSHR hits 1472system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 11 # number of demand (read+write) MSHR hits 1473system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits 1474system.cpu0.l2cache.demand_mshr_hits::cpu0.data 46491 # number of demand (read+write) MSHR hits 1475system.cpu0.l2cache.demand_mshr_hits::total 46513 # number of demand (read+write) MSHR hits 1476system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 6 # number of overall MSHR hits 1477system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 11 # number of overall MSHR hits 1478system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits 1479system.cpu0.l2cache.overall_mshr_hits::cpu0.data 46491 # number of overall MSHR hits 1480system.cpu0.l2cache.overall_mshr_hits::total 46513 # number of overall MSHR hits 1481system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11077 # number of ReadReq MSHR misses 1482system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7399 # number of ReadReq MSHR misses 1483system.cpu0.l2cache.ReadReq_mshr_misses::total 18476 # number of ReadReq MSHR misses 1484system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 1485system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 1486system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses 1487system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses 1488system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 765922 # number of HardPFReq MSHR misses 1489system.cpu0.l2cache.HardPFReq_mshr_misses::total 765922 # number of HardPFReq MSHR misses 1490system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 259441 # number of UpgradeReq MSHR misses 1491system.cpu0.l2cache.UpgradeReq_mshr_misses::total 259441 # number of UpgradeReq MSHR misses 1492system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 189304 # number of SCUpgradeReq MSHR misses 1493system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 189304 # number of SCUpgradeReq MSHR misses 1494system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1495system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1496system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 278860 # number of ReadExReq MSHR misses 1497system.cpu0.l2cache.ReadExReq_mshr_misses::total 278860 # number of ReadExReq MSHR misses 1498system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 549392 # number of ReadCleanReq MSHR misses 1499system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 549392 # number of ReadCleanReq MSHR misses 1500system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 980542 # number of ReadSharedReq MSHR misses 1501system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 980542 # number of ReadSharedReq MSHR misses 1502system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 595013 # number of InvalidateReq MSHR misses 1503system.cpu0.l2cache.InvalidateReq_mshr_misses::total 595013 # number of InvalidateReq MSHR misses 1504system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11077 # number of demand (read+write) MSHR misses 1505system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7399 # number of demand (read+write) MSHR misses 1506system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 549392 # number of demand (read+write) MSHR misses 1507system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1259402 # number of demand (read+write) MSHR misses 1508system.cpu0.l2cache.demand_mshr_misses::total 1827270 # number of demand (read+write) MSHR misses 1509system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11077 # number of overall MSHR misses 1510system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7399 # number of overall MSHR misses 1511system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 549392 # number of overall MSHR misses 1512system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1259402 # number of overall MSHR misses 1513system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 765922 # number of overall MSHR misses 1514system.cpu0.l2cache.overall_mshr_misses::total 2593192 # number of overall MSHR misses 1515system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1516system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19295 # number of ReadReq MSHR uncacheable 1517system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40588 # number of ReadReq MSHR uncacheable 1518system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 20724 # number of WriteReq MSHR uncacheable 1519system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 20724 # number of WriteReq MSHR uncacheable 1520system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1521system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40019 # number of overall MSHR uncacheable misses 1522system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 61312 # number of overall MSHR uncacheable misses 1523system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 416228500 # number of ReadReq MSHR miss cycles 1524system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 267583000 # number of ReadReq MSHR miss cycles 1525system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 683811500 # number of ReadReq MSHR miss cycles 1526system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48317121571 # number of HardPFReq MSHR miss cycles 1527system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 48317121571 # number of HardPFReq MSHR miss cycles 1528system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7648488996 # number of UpgradeReq MSHR miss cycles 1529system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7648488996 # number of UpgradeReq MSHR miss cycles 1530system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3692133999 # number of SCUpgradeReq MSHR miss cycles 1531system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3692133999 # number of SCUpgradeReq MSHR miss cycles 1532system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 5108000 # number of SCUpgradeFailReq MSHR miss cycles 1533system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5108000 # number of SCUpgradeFailReq MSHR miss cycles 1534system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16036130498 # number of ReadExReq MSHR miss cycles 1535system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16036130498 # number of ReadExReq MSHR miss cycles 1536system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17824036498 # number of ReadCleanReq MSHR miss cycles 1537system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17824036498 # number of ReadCleanReq MSHR miss cycles 1538system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34158749978 # number of ReadSharedReq MSHR miss cycles 1539system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34158749978 # number of ReadSharedReq MSHR miss cycles 1540system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 42060830499 # number of InvalidateReq MSHR miss cycles 1541system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 42060830499 # number of InvalidateReq MSHR miss cycles 1542system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 416228500 # number of demand (read+write) MSHR miss cycles 1543system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 267583000 # number of demand (read+write) MSHR miss cycles 1544system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17824036498 # number of demand (read+write) MSHR miss cycles 1545system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 50194880476 # number of demand (read+write) MSHR miss cycles 1546system.cpu0.l2cache.demand_mshr_miss_latency::total 68702728474 # number of demand (read+write) MSHR miss cycles 1547system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 416228500 # number of overall MSHR miss cycles 1548system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 267583000 # number of overall MSHR miss cycles 1549system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17824036498 # number of overall MSHR miss cycles 1550system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 50194880476 # number of overall MSHR miss cycles 1551system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48317121571 # number of overall MSHR miss cycles 1552system.cpu0.l2cache.overall_mshr_miss_latency::total 117019850045 # number of overall MSHR miss cycles 1553system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082000 # number of ReadReq MSHR uncacheable cycles 1554system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3635082000 # number of ReadReq MSHR uncacheable cycles 1555system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6415164000 # number of ReadReq MSHR uncacheable cycles 1556system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3780809967 # number of WriteReq MSHR uncacheable cycles 1557system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3780809967 # number of WriteReq MSHR uncacheable cycles 1558system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082000 # number of overall MSHR uncacheable cycles 1559system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7415891967 # number of overall MSHR uncacheable cycles 1560system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10195973967 # number of overall MSHR uncacheable cycles 1561system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019867 # mshr miss rate for ReadReq accesses 1562system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.039773 # mshr miss rate for ReadReq accesses 1563system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024847 # mshr miss rate for ReadReq accesses 1564system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 1565system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 1566system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1567system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1568system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1569system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1570system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998080 # mshr miss rate for UpgradeReq accesses 1571system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998080 # mshr miss rate for UpgradeReq accesses 1572system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999974 # mshr miss rate for SCUpgradeReq accesses 1573system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999974 # mshr miss rate for SCUpgradeReq accesses 1574system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1575system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1576system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236031 # mshr miss rate for ReadExReq accesses 1577system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236031 # mshr miss rate for ReadExReq accesses 1578system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093914 # mshr miss rate for ReadCleanReq accesses 1579system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093914 # mshr miss rate for ReadCleanReq accesses 1580system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.252013 # mshr miss rate for ReadSharedReq accesses 1581system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252013 # mshr miss rate for ReadSharedReq accesses 1582system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.753776 # mshr miss rate for InvalidateReq accesses 1583system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.753776 # mshr miss rate for InvalidateReq accesses 1584system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019867 # mshr miss rate for demand accesses 1585system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039773 # mshr miss rate for demand accesses 1586system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093914 # mshr miss rate for demand accesses 1587system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248290 # mshr miss rate for demand accesses 1588system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156635 # mshr miss rate for demand accesses 1589system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019867 # mshr miss rate for overall accesses 1590system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039773 # mshr miss rate for overall accesses 1591system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093914 # mshr miss rate for overall accesses 1592system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248290 # mshr miss rate for overall accesses 1593system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1594system.cpu0.l2cache.overall_mshr_miss_rate::total 0.222290 # mshr miss rate for overall accesses 1595system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084 # average ReadReq mshr miss latency 1596system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994 # average ReadReq mshr miss latency 1597system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37010.797792 # average ReadReq mshr miss latency 1598system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865 # average HardPFReq mshr miss latency 1599system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63083.605865 # average HardPFReq mshr miss latency 1600system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29480.648764 # average UpgradeReq mshr miss latency 1601system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29480.648764 # average UpgradeReq mshr miss latency 1602system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19503.729446 # average SCUpgradeReq mshr miss latency 1603system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19503.729446 # average SCUpgradeReq mshr miss latency 1604system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1277000 # average SCUpgradeFailReq mshr miss latency 1605system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1277000 # average SCUpgradeFailReq mshr miss latency 1606system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57506.026314 # average ReadExReq mshr miss latency 1607system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57506.026314 # average ReadExReq mshr miss latency 1608system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32443.203574 # average ReadCleanReq mshr miss latency 1609system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32443.203574 # average ReadCleanReq mshr miss latency 1610system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34836.600552 # average ReadSharedReq mshr miss latency 1611system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34836.600552 # average ReadSharedReq mshr miss latency 1612system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70688.926963 # average InvalidateReq mshr miss latency 1613system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70688.926963 # average InvalidateReq mshr miss latency 1614system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084 # average overall mshr miss latency 1615system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994 # average overall mshr miss latency 1616system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32443.203574 # average overall mshr miss latency 1617system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39856.122569 # average overall mshr miss latency 1618system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37598.564237 # average overall mshr miss latency 1619system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084 # average overall mshr miss latency 1620system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994 # average overall mshr miss latency 1621system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32443.203574 # average overall mshr miss latency 1622system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39856.122569 # average overall mshr miss latency 1623system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865 # average overall mshr miss latency 1624system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45125.794791 # average overall mshr miss latency 1625system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average ReadReq mshr uncacheable latency 1626system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188395.024618 # average ReadReq mshr uncacheable latency 1627system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158055.681482 # average ReadReq mshr uncacheable latency 1628system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182436.304140 # average WriteReq mshr uncacheable latency 1629system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182436.304140 # average WriteReq mshr uncacheable latency 1630system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average overall mshr uncacheable latency 1631system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185309.277268 # average overall mshr uncacheable latency 1632system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 166296.548261 # average overall mshr uncacheable latency 1633system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1634system.cpu0.toL2Bus.snoop_filter.tot_requests 24114479 # Total number of requests made to the snoop filter. 1635system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12402894 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1636system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2291 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1637system.cpu0.toL2Bus.snoop_filter.tot_snoops 1959388 # Total number of snoops made to the snoop filter. 1638system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1958967 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1639system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 421 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1640system.cpu0.toL2Bus.trans_dist::ReadReq 868302 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::ReadResp 10703945 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::WriteReq 20725 # Transaction distribution 1644system.cpu0.toL2Bus.trans_dist::WriteResp 20724 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471023 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::WritebackClean 7766214 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::CleanEvict 2549883 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::HardPFReq 981532 # Transaction distribution 1649system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1650system.cpu0.toL2Bus.trans_dist::UpgradeReq 467602 # Transaction distribution 1651system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343874 # Transaction distribution 1652system.cpu0.toL2Bus.trans_dist::UpgradeResp 514595 # Transaction distribution 1653system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution 1654system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 137 # Transaction distribution 1655system.cpu0.toL2Bus.trans_dist::ReadExReq 1212904 # Transaction distribution 1656system.cpu0.toL2Bus.trans_dist::ReadExResp 1189199 # Transaction distribution 1657system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5849954 # Transaction distribution 1658system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4880551 # Transaction distribution 1659system.cpu0.toL2Bus.trans_dist::InvalidateReq 848509 # Transaction distribution 1660system.cpu0.toL2Bus.trans_dist::InvalidateResp 789376 # Transaction distribution 1661system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17591867 # Packet count per connected master and slave (bytes) 1662system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18635587 # Packet count per connected master and slave (bytes) 1663system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390565 # Packet count per connected master and slave (bytes) 1664system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1180743 # Packet count per connected master and slave (bytes) 1665system.cpu0.toL2Bus.pkt_count::total 37798762 # Packet count per connected master and slave (bytes) 1666system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 749097616 # Cumulative packet size per connected master and slave (bytes) 1667system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 700307787 # Cumulative packet size per connected master and slave (bytes) 1668system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1488232 # Cumulative packet size per connected master and slave (bytes) 1669system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4460536 # Cumulative packet size per connected master and slave (bytes) 1670system.cpu0.toL2Bus.pkt_size::total 1455354171 # Cumulative packet size per connected master and slave (bytes) 1671system.cpu0.toL2Bus.snoops 6848442 # Total snoops (count) 1672system.cpu0.toL2Bus.snoop_fanout::samples 19646181 # Request fanout histogram 1673system.cpu0.toL2Bus.snoop_fanout::mean 0.117106 # Request fanout histogram 1674system.cpu0.toL2Bus.snoop_fanout::stdev 0.321630 # Request fanout histogram 1675system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1676system.cpu0.toL2Bus.snoop_fanout::0 17346012 88.29% 88.29% # Request fanout histogram 1677system.cpu0.toL2Bus.snoop_fanout::1 2299647 11.71% 100.00% # Request fanout histogram 1678system.cpu0.toL2Bus.snoop_fanout::2 522 0.00% 100.00% # Request fanout histogram 1679system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1680system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1681system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1682system.cpu0.toL2Bus.snoop_fanout::total 19646181 # Request fanout histogram 1683system.cpu0.toL2Bus.reqLayer0.occupancy 23957915414 # Layer occupancy (ticks) 1684system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1685system.cpu0.toL2Bus.snoopLayer0.occupancy 186819649 # Layer occupancy (ticks) 1686system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1687system.cpu0.toL2Bus.respLayer0.occupancy 8802550782 # Layer occupancy (ticks) 1688system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1689system.cpu0.toL2Bus.respLayer1.occupancy 8265265885 # Layer occupancy (ticks) 1690system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1691system.cpu0.toL2Bus.respLayer2.occupancy 204815934 # Layer occupancy (ticks) 1692system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1693system.cpu0.toL2Bus.respLayer3.occupancy 623887061 # Layer occupancy (ticks) 1694system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1695system.cpu1.branchPred.lookups 135174598 # Number of BP lookups 1696system.cpu1.branchPred.condPredicted 89157012 # Number of conditional branches predicted 1697system.cpu1.branchPred.condIncorrect 6771553 # Number of conditional branches incorrect 1698system.cpu1.branchPred.BTBLookups 95119508 # Number of BTB lookups 1699system.cpu1.branchPred.BTBHits 59219614 # Number of BTB hits 1700system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1701system.cpu1.branchPred.BTBHitPct 62.258116 # BTB Hit Percentage 1702system.cpu1.branchPred.usedRAS 18509493 # Number of times the RAS was used to get a target. 1703system.cpu1.branchPred.RASInCorrect 199065 # Number of incorrect RAS predictions. 1704system.cpu1.branchPred.indirectLookups 4260619 # Number of indirect predictor lookups. 1705system.cpu1.branchPred.indirectHits 2645570 # Number of indirect target hits. 1706system.cpu1.branchPred.indirectMisses 1615049 # Number of indirect misses. 1707system.cpu1.branchPredindirectMispredicted 400784 # Number of mispredicted indirect branches. 1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1709system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1710system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1711system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1712system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1713system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1714system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1715system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1716system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1717system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1718system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1719system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1720system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1721system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1722system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1723system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1724system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1725system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1726system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1727system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1728system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1729system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1730system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1731system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1732system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1733system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1734system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1735system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1736system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1737system.cpu1.dtb.walker.walks 620331 # Table walker walks requested 1738system.cpu1.dtb.walker.walksLong 620331 # Table walker walks initiated with long descriptors 1739system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13694 # Level at which table walker walks with long descriptors terminate 1740system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 99863 # Level at which table walker walks with long descriptors terminate 1741system.cpu1.dtb.walker.walksSquashedBefore 301286 # Table walks squashed before starting 1742system.cpu1.dtb.walker.walkWaitTime::samples 319045 # Table walker wait (enqueue to first request) latency 1743system.cpu1.dtb.walker.walkWaitTime::mean 2609.283957 # Table walker wait (enqueue to first request) latency 1744system.cpu1.dtb.walker.walkWaitTime::stdev 15339.812797 # Table walker wait (enqueue to first request) latency 1745system.cpu1.dtb.walker.walkWaitTime::0-65535 316072 99.07% 99.07% # Table walker wait (enqueue to first request) latency 1746system.cpu1.dtb.walker.walkWaitTime::65536-131071 1597 0.50% 99.57% # Table walker wait (enqueue to first request) latency 1747system.cpu1.dtb.walker.walkWaitTime::131072-196607 1113 0.35% 99.92% # Table walker wait (enqueue to first request) latency 1748system.cpu1.dtb.walker.walkWaitTime::196608-262143 132 0.04% 99.96% # Table walker wait (enqueue to first request) latency 1749system.cpu1.dtb.walker.walkWaitTime::262144-327679 45 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1750system.cpu1.dtb.walker.walkWaitTime::327680-393215 65 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1751system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1752system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1753system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1754system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1755system.cpu1.dtb.walker.walkWaitTime::total 319045 # Table walker wait (enqueue to first request) latency 1756system.cpu1.dtb.walker.walkCompletionTime::samples 336255 # Table walker service (enqueue to completion) latency 1757system.cpu1.dtb.walker.walkCompletionTime::mean 21304.924834 # Table walker service (enqueue to completion) latency 1758system.cpu1.dtb.walker.walkCompletionTime::gmean 17913.652779 # Table walker service (enqueue to completion) latency 1759system.cpu1.dtb.walker.walkCompletionTime::stdev 23319.449537 # Table walker service (enqueue to completion) latency 1760system.cpu1.dtb.walker.walkCompletionTime::0-65535 331614 98.62% 98.62% # Table walker service (enqueue to completion) latency 1761system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1015 0.30% 98.92% # Table walker service (enqueue to completion) latency 1762system.cpu1.dtb.walker.walkCompletionTime::131072-196607 2524 0.75% 99.67% # Table walker service (enqueue to completion) latency 1763system.cpu1.dtb.walker.walkCompletionTime::196608-262143 218 0.06% 99.74% # Table walker service (enqueue to completion) latency 1764system.cpu1.dtb.walker.walkCompletionTime::262144-327679 559 0.17% 99.90% # Table walker service (enqueue to completion) latency 1765system.cpu1.dtb.walker.walkCompletionTime::327680-393215 132 0.04% 99.94% # Table walker service (enqueue to completion) latency 1766system.cpu1.dtb.walker.walkCompletionTime::393216-458751 112 0.03% 99.98% # Table walker service (enqueue to completion) latency 1767system.cpu1.dtb.walker.walkCompletionTime::458752-524287 49 0.01% 99.99% # Table walker service (enqueue to completion) latency 1768system.cpu1.dtb.walker.walkCompletionTime::524288-589823 16 0.00% 100.00% # Table walker service (enqueue to completion) latency 1769system.cpu1.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency 1770system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1771system.cpu1.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1772system.cpu1.dtb.walker.walkCompletionTime::total 336255 # Table walker service (enqueue to completion) latency 1773system.cpu1.dtb.walker.walksPending::samples 493108416476 # Table walker pending requests distribution 1774system.cpu1.dtb.walker.walksPending::mean 0.613633 # Table walker pending requests distribution 1775system.cpu1.dtb.walker.walksPending::stdev 0.555238 # Table walker pending requests distribution 1776system.cpu1.dtb.walker.walksPending::0-1 491595088976 99.69% 99.69% # Table walker pending requests distribution 1777system.cpu1.dtb.walker.walksPending::2-3 828838000 0.17% 99.86% # Table walker pending requests distribution 1778system.cpu1.dtb.walker.walksPending::4-5 323227000 0.07% 99.93% # Table walker pending requests distribution 1779system.cpu1.dtb.walker.walksPending::6-7 140968000 0.03% 99.96% # Table walker pending requests distribution 1780system.cpu1.dtb.walker.walksPending::8-9 113706500 0.02% 99.98% # Table walker pending requests distribution 1781system.cpu1.dtb.walker.walksPending::10-11 58901000 0.01% 99.99% # Table walker pending requests distribution 1782system.cpu1.dtb.walker.walksPending::12-13 19970500 0.00% 99.99% # Table walker pending requests distribution 1783system.cpu1.dtb.walker.walksPending::14-15 26949000 0.01% 100.00% # Table walker pending requests distribution 1784system.cpu1.dtb.walker.walksPending::16-17 748000 0.00% 100.00% # Table walker pending requests distribution 1785system.cpu1.dtb.walker.walksPending::18-19 19500 0.00% 100.00% # Table walker pending requests distribution 1786system.cpu1.dtb.walker.walksPending::total 493108416476 # Table walker pending requests distribution 1787system.cpu1.dtb.walker.walkPageSizes::4K 99864 87.94% 87.94% # Table walker page sizes translated 1788system.cpu1.dtb.walker.walkPageSizes::2M 13694 12.06% 100.00% # Table walker page sizes translated 1789system.cpu1.dtb.walker.walkPageSizes::total 113558 # Table walker page sizes translated 1790system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 620331 # Table walker requests started/completed, data/inst 1791system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1792system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 620331 # Table walker requests started/completed, data/inst 1793system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 113558 # Table walker requests started/completed, data/inst 1794system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1795system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 113558 # Table walker requests started/completed, data/inst 1796system.cpu1.dtb.walker.walkRequestOrigin::total 733889 # Table walker requests started/completed, data/inst 1797system.cpu1.dtb.inst_hits 0 # ITB inst hits 1798system.cpu1.dtb.inst_misses 0 # ITB inst misses 1799system.cpu1.dtb.read_hits 99541236 # DTB read hits 1800system.cpu1.dtb.read_misses 446261 # DTB read misses 1801system.cpu1.dtb.write_hits 80566614 # DTB write hits 1802system.cpu1.dtb.write_misses 174070 # DTB write misses 1803system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1804system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1805system.cpu1.dtb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID 1806system.cpu1.dtb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID 1807system.cpu1.dtb.flush_entries 43247 # Number of entries that have been flushed from TLB 1808system.cpu1.dtb.align_faults 634 # Number of TLB faults due to alignment restrictions 1809system.cpu1.dtb.prefetch_faults 6731 # Number of TLB faults due to prefetch 1810system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1811system.cpu1.dtb.perms_faults 41159 # Number of TLB faults due to permissions restrictions 1812system.cpu1.dtb.read_accesses 99987497 # DTB read accesses 1813system.cpu1.dtb.write_accesses 80740684 # DTB write accesses 1814system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1815system.cpu1.dtb.hits 180107850 # DTB hits 1816system.cpu1.dtb.misses 620331 # DTB misses 1817system.cpu1.dtb.accesses 180728181 # DTB accesses 1818system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1820system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1821system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1822system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1823system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1824system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1825system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1826system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1827system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1828system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1829system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1830system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1831system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1832system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1833system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1834system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1835system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1836system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1837system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1838system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1839system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1840system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1841system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1842system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1843system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1844system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1845system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1846system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1847system.cpu1.itb.walker.walks 88034 # Table walker walks requested 1848system.cpu1.itb.walker.walksLong 88034 # Table walker walks initiated with long descriptors 1849system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1080 # Level at which table walker walks with long descriptors terminate 1850system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62024 # Level at which table walker walks with long descriptors terminate 1851system.cpu1.itb.walker.walksSquashedBefore 10531 # Table walks squashed before starting 1852system.cpu1.itb.walker.walkWaitTime::samples 77503 # Table walker wait (enqueue to first request) latency 1853system.cpu1.itb.walker.walkWaitTime::mean 1737.752087 # Table walker wait (enqueue to first request) latency 1854system.cpu1.itb.walker.walkWaitTime::stdev 13376.771603 # Table walker wait (enqueue to first request) latency 1855system.cpu1.itb.walker.walkWaitTime::0-32767 76531 98.75% 98.75% # Table walker wait (enqueue to first request) latency 1856system.cpu1.itb.walker.walkWaitTime::32768-65535 407 0.53% 99.27% # Table walker wait (enqueue to first request) latency 1857system.cpu1.itb.walker.walkWaitTime::65536-98303 54 0.07% 99.34% # Table walker wait (enqueue to first request) latency 1858system.cpu1.itb.walker.walkWaitTime::98304-131071 157 0.20% 99.54% # Table walker wait (enqueue to first request) latency 1859system.cpu1.itb.walker.walkWaitTime::131072-163839 274 0.35% 99.90% # Table walker wait (enqueue to first request) latency 1860system.cpu1.itb.walker.walkWaitTime::163840-196607 44 0.06% 99.95% # Table walker wait (enqueue to first request) latency 1861system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.96% # Table walker wait (enqueue to first request) latency 1862system.cpu1.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1863system.cpu1.itb.walker.walkWaitTime::262144-294911 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1864system.cpu1.itb.walker.walkWaitTime::294912-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1865system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1866system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1867system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1868system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1869system.cpu1.itb.walker.walkWaitTime::total 77503 # Table walker wait (enqueue to first request) latency 1870system.cpu1.itb.walker.walkCompletionTime::samples 73635 # Table walker service (enqueue to completion) latency 1871system.cpu1.itb.walker.walkCompletionTime::mean 28077.836627 # Table walker service (enqueue to completion) latency 1872system.cpu1.itb.walker.walkCompletionTime::gmean 23325.571005 # Table walker service (enqueue to completion) latency 1873system.cpu1.itb.walker.walkCompletionTime::stdev 31326.629409 # Table walker service (enqueue to completion) latency 1874system.cpu1.itb.walker.walkCompletionTime::0-65535 71135 96.60% 96.60% # Table walker service (enqueue to completion) latency 1875system.cpu1.itb.walker.walkCompletionTime::65536-131071 154 0.21% 96.81% # Table walker service (enqueue to completion) latency 1876system.cpu1.itb.walker.walkCompletionTime::131072-196607 1986 2.70% 99.51% # Table walker service (enqueue to completion) latency 1877system.cpu1.itb.walker.walkCompletionTime::196608-262143 113 0.15% 99.66% # Table walker service (enqueue to completion) latency 1878system.cpu1.itb.walker.walkCompletionTime::262144-327679 137 0.19% 99.85% # Table walker service (enqueue to completion) latency 1879system.cpu1.itb.walker.walkCompletionTime::327680-393215 53 0.07% 99.92% # Table walker service (enqueue to completion) latency 1880system.cpu1.itb.walker.walkCompletionTime::393216-458751 44 0.06% 99.98% # Table walker service (enqueue to completion) latency 1881system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1882system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1883system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1884system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1885system.cpu1.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1886system.cpu1.itb.walker.walkCompletionTime::total 73635 # Table walker service (enqueue to completion) latency 1887system.cpu1.itb.walker.walksPending::samples 428680982536 # Table walker pending requests distribution 1888system.cpu1.itb.walker.walksPending::mean 0.877576 # Table walker pending requests distribution 1889system.cpu1.itb.walker.walksPending::stdev 0.328123 # Table walker pending requests distribution 1890system.cpu1.itb.walker.walksPending::0 52527553308 12.25% 12.25% # Table walker pending requests distribution 1891system.cpu1.itb.walker.walksPending::1 376108944728 87.74% 99.99% # Table walker pending requests distribution 1892system.cpu1.itb.walker.walksPending::2 42347500 0.01% 100.00% # Table walker pending requests distribution 1893system.cpu1.itb.walker.walksPending::3 2103500 0.00% 100.00% # Table walker pending requests distribution 1894system.cpu1.itb.walker.walksPending::4 33500 0.00% 100.00% # Table walker pending requests distribution 1895system.cpu1.itb.walker.walksPending::total 428680982536 # Table walker pending requests distribution 1896system.cpu1.itb.walker.walkPageSizes::4K 62024 98.29% 98.29% # Table walker page sizes translated 1897system.cpu1.itb.walker.walkPageSizes::2M 1080 1.71% 100.00% # Table walker page sizes translated 1898system.cpu1.itb.walker.walkPageSizes::total 63104 # Table walker page sizes translated 1899system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1900system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 88034 # Table walker requests started/completed, data/inst 1901system.cpu1.itb.walker.walkRequestOrigin_Requested::total 88034 # Table walker requests started/completed, data/inst 1902system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1903system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63104 # Table walker requests started/completed, data/inst 1904system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63104 # Table walker requests started/completed, data/inst 1905system.cpu1.itb.walker.walkRequestOrigin::total 151138 # Table walker requests started/completed, data/inst 1906system.cpu1.itb.inst_hits 212987962 # ITB inst hits 1907system.cpu1.itb.inst_misses 88034 # ITB inst misses 1908system.cpu1.itb.read_hits 0 # DTB read hits 1909system.cpu1.itb.read_misses 0 # DTB read misses 1910system.cpu1.itb.write_hits 0 # DTB write hits 1911system.cpu1.itb.write_misses 0 # DTB write misses 1912system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1913system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1914system.cpu1.itb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID 1915system.cpu1.itb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID 1916system.cpu1.itb.flush_entries 31450 # Number of entries that have been flushed from TLB 1917system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1918system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1919system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1920system.cpu1.itb.perms_faults 212403 # Number of TLB faults due to permissions restrictions 1921system.cpu1.itb.read_accesses 0 # DTB read accesses 1922system.cpu1.itb.write_accesses 0 # DTB write accesses 1923system.cpu1.itb.inst_accesses 213075996 # ITB inst accesses 1924system.cpu1.itb.hits 212987962 # DTB hits 1925system.cpu1.itb.misses 88034 # DTB misses 1926system.cpu1.itb.accesses 213075996 # DTB accesses 1927system.cpu1.numCycles 763303942 # number of cpu cycles simulated 1928system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1929system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1930system.cpu1.fetch.icacheStallCycles 89198965 # Number of cycles fetch is stalled on an Icache miss 1931system.cpu1.fetch.Insts 599138491 # Number of instructions fetch has processed 1932system.cpu1.fetch.Branches 135174598 # Number of branches that fetch encountered 1933system.cpu1.fetch.predictedBranches 80374677 # Number of branches that fetch has predicted taken 1934system.cpu1.fetch.Cycles 631697152 # Number of cycles fetch has run and was not squashing or blocked 1935system.cpu1.fetch.SquashCycles 14629606 # Number of cycles fetch has spent squashing 1936system.cpu1.fetch.TlbCycles 2135822 # Number of cycles fetch has spent waiting for tlb 1937system.cpu1.fetch.MiscStallCycles 325301 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1938system.cpu1.fetch.PendingTrapStallCycles 6190061 # Number of stall cycles due to pending traps 1939system.cpu1.fetch.PendingQuiesceStallCycles 869593 # Number of stall cycles due to pending quiesce instructions 1940system.cpu1.fetch.IcacheWaitRetryStallCycles 862105 # Number of stall cycles due to full MSHR 1941system.cpu1.fetch.CacheLines 212754259 # Number of cache lines fetched 1942system.cpu1.fetch.IcacheSquashes 1709590 # Number of outstanding Icache misses that were squashed 1943system.cpu1.fetch.ItlbSquashes 28554 # Number of outstanding ITLB misses that were squashed 1944system.cpu1.fetch.rateDist::samples 738593802 # Number of instructions fetched each cycle (Total) 1945system.cpu1.fetch.rateDist::mean 0.951348 # Number of instructions fetched each cycle (Total) 1946system.cpu1.fetch.rateDist::stdev 1.213932 # Number of instructions fetched each cycle (Total) 1947system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1948system.cpu1.fetch.rateDist::0 402298959 54.47% 54.47% # Number of instructions fetched each cycle (Total) 1949system.cpu1.fetch.rateDist::1 130678569 17.69% 72.16% # Number of instructions fetched each cycle (Total) 1950system.cpu1.fetch.rateDist::2 44867308 6.07% 78.24% # Number of instructions fetched each cycle (Total) 1951system.cpu1.fetch.rateDist::3 160748966 21.76% 100.00% # Number of instructions fetched each cycle (Total) 1952system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1953system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1954system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1955system.cpu1.fetch.rateDist::total 738593802 # Number of instructions fetched each cycle (Total) 1956system.cpu1.fetch.branchRate 0.177091 # Number of branch fetches per cycle 1957system.cpu1.fetch.rate 0.784928 # Number of inst fetches per cycle 1958system.cpu1.decode.IdleCycles 106478117 # Number of cycles decode is idle 1959system.cpu1.decode.BlockedCycles 366845169 # Number of cycles decode is blocked 1960system.cpu1.decode.RunCycles 222515957 # Number of cycles decode is running 1961system.cpu1.decode.UnblockCycles 37512815 # Number of cycles decode is unblocking 1962system.cpu1.decode.SquashCycles 5241744 # Number of cycles decode is squashing 1963system.cpu1.decode.BranchResolved 19111386 # Number of times decode resolved a branch 1964system.cpu1.decode.BranchMispred 2112679 # Number of times decode detected a branch misprediction 1965system.cpu1.decode.DecodedInsts 619567000 # Number of instructions handled by decode 1966system.cpu1.decode.SquashedInsts 23338360 # Number of squashed instructions handled by decode 1967system.cpu1.rename.SquashCycles 5241744 # Number of cycles rename is squashing 1968system.cpu1.rename.IdleCycles 141946273 # Number of cycles rename is idle 1969system.cpu1.rename.BlockCycles 54617946 # Number of cycles rename is blocking 1970system.cpu1.rename.serializeStallCycles 243861784 # count of cycles rename stalled for serializing inst 1971system.cpu1.rename.RunCycles 224134357 # Number of cycles rename is running 1972system.cpu1.rename.UnblockCycles 68791698 # Number of cycles rename is unblocking 1973system.cpu1.rename.RenamedInsts 602126263 # Number of instructions processed by rename 1974system.cpu1.rename.SquashedInsts 6118576 # Number of squashed instructions processed by rename 1975system.cpu1.rename.ROBFullEvents 11056239 # Number of times rename has blocked due to ROB full 1976system.cpu1.rename.IQFullEvents 380631 # Number of times rename has blocked due to IQ full 1977system.cpu1.rename.LQFullEvents 940722 # Number of times rename has blocked due to LQ full 1978system.cpu1.rename.SQFullEvents 33286587 # Number of times rename has blocked due to SQ full 1979system.cpu1.rename.FullRegisterEvents 12083 # Number of times there has been no free registers 1980system.cpu1.rename.RenamedOperands 573060902 # Number of destination operands rename has renamed 1981system.cpu1.rename.RenameLookups 928019832 # Number of register rename lookups that rename has made 1982system.cpu1.rename.int_rename_lookups 710062229 # Number of integer rename lookups 1983system.cpu1.rename.fp_rename_lookups 649328 # Number of floating rename lookups 1984system.cpu1.rename.CommittedMaps 514926448 # Number of HB maps that are committed 1985system.cpu1.rename.UndoneMaps 58134448 # Number of HB maps that are undone due to squashing 1986system.cpu1.rename.serializingInsts 16118585 # count of serializing insts renamed 1987system.cpu1.rename.tempSerializingInsts 14068970 # count of temporary serializing insts renamed 1988system.cpu1.rename.skidInsts 75560239 # count of insts added to the skid buffer 1989system.cpu1.memDep0.insertedLoads 99853363 # Number of loads inserted to the mem dependence unit. 1990system.cpu1.memDep0.insertedStores 83838519 # Number of stores inserted to the mem dependence unit. 1991system.cpu1.memDep0.conflictingLoads 9473424 # Number of conflicting loads. 1992system.cpu1.memDep0.conflictingStores 8115334 # Number of conflicting stores. 1993system.cpu1.iq.iqInstsAdded 579120615 # Number of instructions added to the IQ (excludes non-spec) 1994system.cpu1.iq.iqNonSpecInstsAdded 16293769 # Number of non-speculative instructions added to the IQ 1995system.cpu1.iq.iqInstsIssued 584059770 # Number of instructions issued 1996system.cpu1.iq.iqSquashedInstsIssued 2714782 # Number of squashed instructions issued 1997system.cpu1.iq.iqSquashedInstsExamined 54810980 # Number of squashed instructions iterated over during squash; mainly for profiling 1998system.cpu1.iq.iqSquashedOperandsExamined 35376701 # Number of squashed operands that are examined and possibly removed from graph 1999system.cpu1.iq.iqSquashedNonSpecRemoved 290425 # Number of squashed non-spec instructions that were removed 2000system.cpu1.iq.issued_per_cycle::samples 738593802 # Number of insts issued each cycle 2001system.cpu1.iq.issued_per_cycle::mean 0.790773 # Number of insts issued each cycle 2002system.cpu1.iq.issued_per_cycle::stdev 1.055961 # Number of insts issued each cycle 2003system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2004system.cpu1.iq.issued_per_cycle::0 417929764 56.58% 56.58% # Number of insts issued each cycle 2005system.cpu1.iq.issued_per_cycle::1 136913052 18.54% 75.12% # Number of insts issued each cycle 2006system.cpu1.iq.issued_per_cycle::2 111746112 15.13% 90.25% # Number of insts issued each cycle 2007system.cpu1.iq.issued_per_cycle::3 64370034 8.72% 98.97% # Number of insts issued each cycle 2008system.cpu1.iq.issued_per_cycle::4 7629808 1.03% 100.00% # Number of insts issued each cycle 2009system.cpu1.iq.issued_per_cycle::5 5032 0.00% 100.00% # Number of insts issued each cycle 2010system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2011system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2012system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2013system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2014system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2015system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2016system.cpu1.iq.issued_per_cycle::total 738593802 # Number of insts issued each cycle 2017system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2018system.cpu1.iq.fu_full::IntAlu 58567749 44.20% 44.20% # attempts to use FU when none available 2019system.cpu1.iq.fu_full::IntMult 70680 0.05% 44.25% # attempts to use FU when none available 2020system.cpu1.iq.fu_full::IntDiv 16113 0.01% 44.26% # attempts to use FU when none available 2021system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.26% # attempts to use FU when none available 2022system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.26% # attempts to use FU when none available 2023system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.26% # attempts to use FU when none available 2024system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.26% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.26% # attempts to use FU when none available 2026system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.26% # attempts to use FU when none available 2027system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.26% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.26% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.26% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.26% # attempts to use FU when none available 2031system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.26% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.26% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.26% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.26% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.26% # attempts to use FU when none available 2036system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.26% # attempts to use FU when none available 2037system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.26% # attempts to use FU when none available 2038system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.26% # attempts to use FU when none available 2039system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.26% # attempts to use FU when none available 2040system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.26% # attempts to use FU when none available 2041system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.26% # attempts to use FU when none available 2042system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.26% # attempts to use FU when none available 2043system.cpu1.iq.fu_full::SimdFloatMisc 26 0.00% 44.26% # attempts to use FU when none available 2044system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.26% # attempts to use FU when none available 2045system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.26% # attempts to use FU when none available 2046system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.26% # attempts to use FU when none available 2047system.cpu1.iq.fu_full::MemRead 36085591 27.23% 71.50% # attempts to use FU when none available 2048system.cpu1.iq.fu_full::MemWrite 37772354 28.50% 100.00% # attempts to use FU when none available 2049system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2050system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2051system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued 2052system.cpu1.iq.FU_type_0::IntAlu 397950619 68.14% 68.14% # Type of FU issued 2053system.cpu1.iq.FU_type_0::IntMult 1394287 0.24% 68.37% # Type of FU issued 2054system.cpu1.iq.FU_type_0::IntDiv 80723 0.01% 68.39% # Type of FU issued 2055system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.39% # Type of FU issued 2056system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued 2057system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued 2058system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued 2059system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.39% # Type of FU issued 2060system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued 2061system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued 2062system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued 2063system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued 2064system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued 2065system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued 2066system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued 2067system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued 2068system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued 2069system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued 2070system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued 2071system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued 2072system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued 2073system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued 2074system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued 2075system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued 2076system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued 2077system.cpu1.iq.FU_type_0::SimdFloatMisc 45828 0.01% 68.40% # Type of FU issued 2078system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued 2079system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued 2080system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued 2081system.cpu1.iq.FU_type_0::MemRead 102773744 17.60% 85.99% # Type of FU issued 2082system.cpu1.iq.FU_type_0::MemWrite 81814529 14.01% 100.00% # Type of FU issued 2083system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2084system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2085system.cpu1.iq.FU_type_0::total 584059770 # Type of FU issued 2086system.cpu1.iq.rate 0.765173 # Inst issue rate 2087system.cpu1.iq.fu_busy_cnt 132512513 # FU busy when requested 2088system.cpu1.iq.fu_busy_rate 0.226882 # FU busy rate (busy events/executed inst) 2089system.cpu1.iq.int_inst_queue_reads 2040871763 # Number of integer instruction queue reads 2090system.cpu1.iq.int_inst_queue_writes 649951389 # Number of integer instruction queue writes 2091system.cpu1.iq.int_inst_queue_wakeup_accesses 566663887 # Number of integer instruction queue wakeup accesses 2092system.cpu1.iq.fp_inst_queue_reads 1068872 # Number of floating instruction queue reads 2093system.cpu1.iq.fp_inst_queue_writes 423239 # Number of floating instruction queue writes 2094system.cpu1.iq.fp_inst_queue_wakeup_accesses 394625 # Number of floating instruction queue wakeup accesses 2095system.cpu1.iq.int_alu_accesses 715907019 # Number of integer alu accesses 2096system.cpu1.iq.fp_alu_accesses 665228 # Number of floating point alu accesses 2097system.cpu1.iew.lsq.thread0.forwLoads 2663748 # Number of loads that had data forwarded from stores 2098system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2099system.cpu1.iew.lsq.thread0.squashedLoads 12784321 # Number of loads squashed 2100system.cpu1.iew.lsq.thread0.ignoredResponses 18121 # Number of memory responses ignored because the instruction is squashed 2101system.cpu1.iew.lsq.thread0.memOrderViolation 150654 # Number of memory ordering violations 2102system.cpu1.iew.lsq.thread0.squashedStores 5561892 # Number of stores squashed 2103system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2104system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2105system.cpu1.iew.lsq.thread0.rescheduledLoads 2706765 # Number of loads that were rescheduled 2106system.cpu1.iew.lsq.thread0.cacheBlocked 4288761 # Number of times an access to memory failed due to the cache being blocked 2107system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2108system.cpu1.iew.iewSquashCycles 5241744 # Number of cycles IEW is squashing 2109system.cpu1.iew.iewBlockCycles 8152179 # Number of cycles IEW is blocking 2110system.cpu1.iew.iewUnblockCycles 2696224 # Number of cycles IEW is unblocking 2111system.cpu1.iew.iewDispatchedInsts 595550479 # Number of instructions dispatched to IQ 2112system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2113system.cpu1.iew.iewDispLoadInsts 99853363 # Number of dispatched load instructions 2114system.cpu1.iew.iewDispStoreInsts 83838519 # Number of dispatched store instructions 2115system.cpu1.iew.iewDispNonSpecInsts 13801566 # Number of dispatched non-speculative instructions 2116system.cpu1.iew.iewIQFullEvents 59598 # Number of times the IQ has become full, causing a stall 2117system.cpu1.iew.iewLSQFullEvents 2567849 # Number of times the LSQ has become full, causing a stall 2118system.cpu1.iew.memOrderViolationEvents 150654 # Number of memory order violations 2119system.cpu1.iew.predictedTakenIncorrect 1960671 # Number of branches that were predicted taken incorrectly 2120system.cpu1.iew.predictedNotTakenIncorrect 3092522 # Number of branches that were predicted not taken incorrectly 2121system.cpu1.iew.branchMispredicts 5053193 # Number of branch mispredicts detected at execute 2122system.cpu1.iew.iewExecutedInsts 576018607 # Number of executed instructions 2123system.cpu1.iew.iewExecLoadInsts 99536730 # Number of load instructions executed 2124system.cpu1.iew.iewExecSquashedInsts 7427921 # Number of squashed instructions skipped in execute 2125system.cpu1.iew.exec_swp 0 # number of swp insts executed 2126system.cpu1.iew.exec_nop 136095 # number of nop insts executed 2127system.cpu1.iew.exec_refs 180100552 # number of memory reference insts executed 2128system.cpu1.iew.exec_branches 107831822 # Number of branches executed 2129system.cpu1.iew.exec_stores 80563822 # Number of stores executed 2130system.cpu1.iew.exec_rate 0.754639 # Inst execution rate 2131system.cpu1.iew.wb_sent 567845555 # cumulative count of insts sent to commit 2132system.cpu1.iew.wb_count 567058512 # cumulative count of insts written-back 2133system.cpu1.iew.wb_producers 275064587 # num instructions producing a value 2134system.cpu1.iew.wb_consumers 450436874 # num instructions consuming a value 2135system.cpu1.iew.wb_rate 0.742900 # insts written-back per cycle 2136system.cpu1.iew.wb_fanout 0.610662 # average fanout of values written-back 2137system.cpu1.commit.commitSquashedInsts 47911948 # The number of squashed insts skipped by commit 2138system.cpu1.commit.commitNonSpecStalls 16003344 # The number of times commit has been forced to stall to communicate backwards 2139system.cpu1.commit.branchMispredicts 4698494 # The number of times a branch was mispredicted 2140system.cpu1.commit.committed_per_cycle::samples 729478017 # Number of insts commited each cycle 2141system.cpu1.commit.committed_per_cycle::mean 0.741083 # Number of insts commited each cycle 2142system.cpu1.commit.committed_per_cycle::stdev 1.544204 # Number of insts commited each cycle 2143system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2144system.cpu1.commit.committed_per_cycle::0 491334549 67.35% 67.35% # Number of insts commited each cycle 2145system.cpu1.commit.committed_per_cycle::1 124605119 17.08% 84.44% # Number of insts commited each cycle 2146system.cpu1.commit.committed_per_cycle::2 52434637 7.19% 91.62% # Number of insts commited each cycle 2147system.cpu1.commit.committed_per_cycle::3 17448264 2.39% 94.02% # Number of insts commited each cycle 2148system.cpu1.commit.committed_per_cycle::4 12346698 1.69% 95.71% # Number of insts commited each cycle 2149system.cpu1.commit.committed_per_cycle::5 8646744 1.19% 96.89% # Number of insts commited each cycle 2150system.cpu1.commit.committed_per_cycle::6 5821113 0.80% 97.69% # Number of insts commited each cycle 2151system.cpu1.commit.committed_per_cycle::7 3490122 0.48% 98.17% # Number of insts commited each cycle 2152system.cpu1.commit.committed_per_cycle::8 13350771 1.83% 100.00% # Number of insts commited each cycle 2153system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2154system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2155system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2156system.cpu1.commit.committed_per_cycle::total 729478017 # Number of insts commited each cycle 2157system.cpu1.commit.committedInsts 459298656 # Number of instructions committed 2158system.cpu1.commit.committedOps 540603397 # Number of ops (including micro ops) committed 2159system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2160system.cpu1.commit.refs 165345668 # Number of memory references committed 2161system.cpu1.commit.loads 87069041 # Number of loads committed 2162system.cpu1.commit.membars 3858315 # Number of memory barriers committed 2163system.cpu1.commit.branches 102318506 # Number of branches committed 2164system.cpu1.commit.fp_insts 386565 # Number of committed floating point instructions. 2165system.cpu1.commit.int_insts 496515316 # Number of committed integer instructions. 2166system.cpu1.commit.function_calls 13693042 # Number of function calls committed. 2167system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2168system.cpu1.commit.op_class_0::IntAlu 374009133 69.18% 69.18% # Class of committed instruction 2169system.cpu1.commit.op_class_0::IntMult 1144857 0.21% 69.40% # Class of committed instruction 2170system.cpu1.commit.op_class_0::IntDiv 64258 0.01% 69.41% # Class of committed instruction 2171system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction 2172system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction 2173system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction 2174system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction 2175system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction 2176system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction 2177system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction 2178system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction 2179system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction 2180system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction 2181system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction 2182system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction 2183system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction 2184system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction 2185system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction 2186system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction 2187system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction 2188system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.41% # Class of committed instruction 2189system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction 2190system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.41% # Class of committed instruction 2191system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.41% # Class of committed instruction 2192system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction 2193system.cpu1.commit.op_class_0::SimdFloatMisc 39481 0.01% 69.41% # Class of committed instruction 2194system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.41% # Class of committed instruction 2195system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.41% # Class of committed instruction 2196system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.41% # Class of committed instruction 2197system.cpu1.commit.op_class_0::MemRead 87069041 16.11% 85.52% # Class of committed instruction 2198system.cpu1.commit.op_class_0::MemWrite 78276627 14.48% 100.00% # Class of committed instruction 2199system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2200system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2201system.cpu1.commit.op_class_0::total 540603397 # Class of committed instruction 2202system.cpu1.commit.bw_lim_events 13350771 # number cycles where commit BW limit reached 2203system.cpu1.rob.rob_reads 1300306905 # The number of ROB reads 2204system.cpu1.rob.rob_writes 1186107059 # The number of ROB writes 2205system.cpu1.timesIdled 1002683 # Number of times that the entire CPU went into an idle state and unscheduled itself 2206system.cpu1.idleCycles 24710140 # Total number of cycles that the CPU has spent unscheduled due to idling 2207system.cpu1.quiesceCycles 94016410262 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2208system.cpu1.committedInsts 459298656 # Number of Instructions Simulated 2209system.cpu1.committedOps 540603397 # Number of Ops (including micro ops) Simulated 2210system.cpu1.cpi 1.661890 # CPI: Cycles Per Instruction 2211system.cpu1.cpi_total 1.661890 # CPI: Total CPI of All Threads 2212system.cpu1.ipc 0.601724 # IPC: Instructions Per Cycle 2213system.cpu1.ipc_total 0.601724 # IPC: Total IPC of All Threads 2214system.cpu1.int_regfile_reads 679475596 # number of integer regfile reads 2215system.cpu1.int_regfile_writes 404035591 # number of integer regfile writes 2216system.cpu1.fp_regfile_reads 636627 # number of floating regfile reads 2217system.cpu1.fp_regfile_writes 333028 # number of floating regfile writes 2218system.cpu1.cc_regfile_reads 123323505 # number of cc regfile reads 2219system.cpu1.cc_regfile_writes 123972693 # number of cc regfile writes 2220system.cpu1.misc_regfile_reads 1293234240 # number of misc regfile reads 2221system.cpu1.misc_regfile_writes 15956756 # number of misc regfile writes 2222system.cpu1.dcache.tags.replacements 5664060 # number of replacements 2223system.cpu1.dcache.tags.tagsinuse 461.921265 # Cycle average of tags in use 2224system.cpu1.dcache.tags.total_refs 153938367 # Total number of references to valid blocks. 2225system.cpu1.dcache.tags.sampled_refs 5664570 # Sample count of references to valid blocks. 2226system.cpu1.dcache.tags.avg_refs 27.175649 # Average number of references to valid blocks. 2227system.cpu1.dcache.tags.warmup_cycle 8482615799500 # Cycle when the warmup percentage was hit. 2228system.cpu1.dcache.tags.occ_blocks::cpu1.data 461.921265 # Average occupied blocks per requestor 2229system.cpu1.dcache.tags.occ_percent::cpu1.data 0.902190 # Average percentage of cache occupancy 2230system.cpu1.dcache.tags.occ_percent::total 0.902190 # Average percentage of cache occupancy 2231system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 2232system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 2233system.cpu1.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id 2234system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 2235system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 2236system.cpu1.dcache.tags.tag_accesses 343399100 # Number of tag accesses 2237system.cpu1.dcache.tags.data_accesses 343399100 # Number of data accesses 2238system.cpu1.dcache.ReadReq_hits::cpu1.data 81011302 # number of ReadReq hits 2239system.cpu1.dcache.ReadReq_hits::total 81011302 # number of ReadReq hits 2240system.cpu1.dcache.WriteReq_hits::cpu1.data 68259476 # number of WriteReq hits 2241system.cpu1.dcache.WriteReq_hits::total 68259476 # number of WriteReq hits 2242system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190553 # number of SoftPFReq hits 2243system.cpu1.dcache.SoftPFReq_hits::total 190553 # number of SoftPFReq hits 2244system.cpu1.dcache.WriteLineReq_hits::cpu1.data 137870 # number of WriteLineReq hits 2245system.cpu1.dcache.WriteLineReq_hits::total 137870 # number of WriteLineReq hits 2246system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1767079 # number of LoadLockedReq hits 2247system.cpu1.dcache.LoadLockedReq_hits::total 1767079 # number of LoadLockedReq hits 2248system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1811409 # number of StoreCondReq hits 2249system.cpu1.dcache.StoreCondReq_hits::total 1811409 # number of StoreCondReq hits 2250system.cpu1.dcache.demand_hits::cpu1.data 149270778 # number of demand (read+write) hits 2251system.cpu1.dcache.demand_hits::total 149270778 # number of demand (read+write) hits 2252system.cpu1.dcache.overall_hits::cpu1.data 149461331 # number of overall hits 2253system.cpu1.dcache.overall_hits::total 149461331 # number of overall hits 2254system.cpu1.dcache.ReadReq_misses::cpu1.data 6609494 # number of ReadReq misses 2255system.cpu1.dcache.ReadReq_misses::total 6609494 # number of ReadReq misses 2256system.cpu1.dcache.WriteReq_misses::cpu1.data 7403019 # number of WriteReq misses 2257system.cpu1.dcache.WriteReq_misses::total 7403019 # number of WriteReq misses 2258system.cpu1.dcache.SoftPFReq_misses::cpu1.data 691160 # number of SoftPFReq misses 2259system.cpu1.dcache.SoftPFReq_misses::total 691160 # number of SoftPFReq misses 2260system.cpu1.dcache.WriteLineReq_misses::cpu1.data 462153 # number of WriteLineReq misses 2261system.cpu1.dcache.WriteLineReq_misses::total 462153 # number of WriteLineReq misses 2262system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 284407 # number of LoadLockedReq misses 2263system.cpu1.dcache.LoadLockedReq_misses::total 284407 # number of LoadLockedReq misses 2264system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195281 # number of StoreCondReq misses 2265system.cpu1.dcache.StoreCondReq_misses::total 195281 # number of StoreCondReq misses 2266system.cpu1.dcache.demand_misses::cpu1.data 14012513 # number of demand (read+write) misses 2267system.cpu1.dcache.demand_misses::total 14012513 # number of demand (read+write) misses 2268system.cpu1.dcache.overall_misses::cpu1.data 14703673 # number of overall misses 2269system.cpu1.dcache.overall_misses::total 14703673 # number of overall misses 2270system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 113682780000 # number of ReadReq miss cycles 2271system.cpu1.dcache.ReadReq_miss_latency::total 113682780000 # number of ReadReq miss cycles 2272system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 163432974267 # number of WriteReq miss cycles 2273system.cpu1.dcache.WriteReq_miss_latency::total 163432974267 # number of WriteReq miss cycles 2274system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19652724076 # number of WriteLineReq miss cycles 2275system.cpu1.dcache.WriteLineReq_miss_latency::total 19652724076 # number of WriteLineReq miss cycles 2276system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4573915000 # number of LoadLockedReq miss cycles 2277system.cpu1.dcache.LoadLockedReq_miss_latency::total 4573915000 # number of LoadLockedReq miss cycles 2278system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5496232500 # number of StoreCondReq miss cycles 2279system.cpu1.dcache.StoreCondReq_miss_latency::total 5496232500 # number of StoreCondReq miss cycles 2280system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5776500 # number of StoreCondFailReq miss cycles 2281system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5776500 # number of StoreCondFailReq miss cycles 2282system.cpu1.dcache.demand_miss_latency::cpu1.data 277115754267 # number of demand (read+write) miss cycles 2283system.cpu1.dcache.demand_miss_latency::total 277115754267 # number of demand (read+write) miss cycles 2284system.cpu1.dcache.overall_miss_latency::cpu1.data 277115754267 # number of overall miss cycles 2285system.cpu1.dcache.overall_miss_latency::total 277115754267 # number of overall miss cycles 2286system.cpu1.dcache.ReadReq_accesses::cpu1.data 87620796 # number of ReadReq accesses(hits+misses) 2287system.cpu1.dcache.ReadReq_accesses::total 87620796 # number of ReadReq accesses(hits+misses) 2288system.cpu1.dcache.WriteReq_accesses::cpu1.data 75662495 # number of WriteReq accesses(hits+misses) 2289system.cpu1.dcache.WriteReq_accesses::total 75662495 # number of WriteReq accesses(hits+misses) 2290system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 881713 # number of SoftPFReq accesses(hits+misses) 2291system.cpu1.dcache.SoftPFReq_accesses::total 881713 # number of SoftPFReq accesses(hits+misses) 2292system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 600023 # number of WriteLineReq accesses(hits+misses) 2293system.cpu1.dcache.WriteLineReq_accesses::total 600023 # number of WriteLineReq accesses(hits+misses) 2294system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2051486 # number of LoadLockedReq accesses(hits+misses) 2295system.cpu1.dcache.LoadLockedReq_accesses::total 2051486 # number of LoadLockedReq accesses(hits+misses) 2296system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2006690 # number of StoreCondReq accesses(hits+misses) 2297system.cpu1.dcache.StoreCondReq_accesses::total 2006690 # number of StoreCondReq accesses(hits+misses) 2298system.cpu1.dcache.demand_accesses::cpu1.data 163283291 # number of demand (read+write) accesses 2299system.cpu1.dcache.demand_accesses::total 163283291 # number of demand (read+write) accesses 2300system.cpu1.dcache.overall_accesses::cpu1.data 164165004 # number of overall (read+write) accesses 2301system.cpu1.dcache.overall_accesses::total 164165004 # number of overall (read+write) accesses 2302system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075433 # miss rate for ReadReq accesses 2303system.cpu1.dcache.ReadReq_miss_rate::total 0.075433 # miss rate for ReadReq accesses 2304system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097843 # miss rate for WriteReq accesses 2305system.cpu1.dcache.WriteReq_miss_rate::total 0.097843 # miss rate for WriteReq accesses 2306system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783883 # miss rate for SoftPFReq accesses 2307system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783883 # miss rate for SoftPFReq accesses 2308system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.770225 # miss rate for WriteLineReq accesses 2309system.cpu1.dcache.WriteLineReq_miss_rate::total 0.770225 # miss rate for WriteLineReq accesses 2310system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138635 # miss rate for LoadLockedReq accesses 2311system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138635 # miss rate for LoadLockedReq accesses 2312system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097315 # miss rate for StoreCondReq accesses 2313system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097315 # miss rate for StoreCondReq accesses 2314system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085817 # miss rate for demand accesses 2315system.cpu1.dcache.demand_miss_rate::total 0.085817 # miss rate for demand accesses 2316system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089566 # miss rate for overall accesses 2317system.cpu1.dcache.overall_miss_rate::total 0.089566 # miss rate for overall accesses 2318system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17199.921809 # average ReadReq miss latency 2319system.cpu1.dcache.ReadReq_avg_miss_latency::total 17199.921809 # average ReadReq miss latency 2320system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22076.530435 # average WriteReq miss latency 2321system.cpu1.dcache.WriteReq_avg_miss_latency::total 22076.530435 # average WriteReq miss latency 2322system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42524.281084 # average WriteLineReq miss latency 2323system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42524.281084 # average WriteLineReq miss latency 2324system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16082.287004 # average LoadLockedReq miss latency 2325system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16082.287004 # average LoadLockedReq miss latency 2326system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28145.249666 # average StoreCondReq miss latency 2327system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28145.249666 # average StoreCondReq miss latency 2328system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2329system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2330system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19776.306667 # average overall miss latency 2331system.cpu1.dcache.demand_avg_miss_latency::total 19776.306667 # average overall miss latency 2332system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18846.702743 # average overall miss latency 2333system.cpu1.dcache.overall_avg_miss_latency::total 18846.702743 # average overall miss latency 2334system.cpu1.dcache.blocked_cycles::no_mshrs 5374733 # number of cycles access was blocked 2335system.cpu1.dcache.blocked_cycles::no_targets 26726963 # number of cycles access was blocked 2336system.cpu1.dcache.blocked::no_mshrs 381404 # number of cycles access was blocked 2337system.cpu1.dcache.blocked::no_targets 750366 # number of cycles access was blocked 2338system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.091968 # average number of cycles each access was blocked 2339system.cpu1.dcache.avg_blocked_cycles::no_targets 35.618569 # average number of cycles each access was blocked 2340system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2341system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2342system.cpu1.dcache.writebacks::writebacks 5664164 # number of writebacks 2343system.cpu1.dcache.writebacks::total 5664164 # number of writebacks 2344system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3334691 # number of ReadReq MSHR hits 2345system.cpu1.dcache.ReadReq_mshr_hits::total 3334691 # number of ReadReq MSHR hits 2346system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5984035 # number of WriteReq MSHR hits 2347system.cpu1.dcache.WriteReq_mshr_hits::total 5984035 # number of WriteReq MSHR hits 2348system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3399 # number of WriteLineReq MSHR hits 2349system.cpu1.dcache.WriteLineReq_mshr_hits::total 3399 # number of WriteLineReq MSHR hits 2350system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 145205 # number of LoadLockedReq MSHR hits 2351system.cpu1.dcache.LoadLockedReq_mshr_hits::total 145205 # number of LoadLockedReq MSHR hits 2352system.cpu1.dcache.demand_mshr_hits::cpu1.data 9318726 # number of demand (read+write) MSHR hits 2353system.cpu1.dcache.demand_mshr_hits::total 9318726 # number of demand (read+write) MSHR hits 2354system.cpu1.dcache.overall_mshr_hits::cpu1.data 9318726 # number of overall MSHR hits 2355system.cpu1.dcache.overall_mshr_hits::total 9318726 # number of overall MSHR hits 2356system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3274803 # number of ReadReq MSHR misses 2357system.cpu1.dcache.ReadReq_mshr_misses::total 3274803 # number of ReadReq MSHR misses 2358system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1418984 # number of WriteReq MSHR misses 2359system.cpu1.dcache.WriteReq_mshr_misses::total 1418984 # number of WriteReq MSHR misses 2360system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 691046 # number of SoftPFReq MSHR misses 2361system.cpu1.dcache.SoftPFReq_mshr_misses::total 691046 # number of SoftPFReq MSHR misses 2362system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 458754 # number of WriteLineReq MSHR misses 2363system.cpu1.dcache.WriteLineReq_mshr_misses::total 458754 # number of WriteLineReq MSHR misses 2364system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 139202 # number of LoadLockedReq MSHR misses 2365system.cpu1.dcache.LoadLockedReq_mshr_misses::total 139202 # number of LoadLockedReq MSHR misses 2366system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195277 # number of StoreCondReq MSHR misses 2367system.cpu1.dcache.StoreCondReq_mshr_misses::total 195277 # number of StoreCondReq MSHR misses 2368system.cpu1.dcache.demand_mshr_misses::cpu1.data 4693787 # number of demand (read+write) MSHR misses 2369system.cpu1.dcache.demand_mshr_misses::total 4693787 # number of demand (read+write) MSHR misses 2370system.cpu1.dcache.overall_mshr_misses::cpu1.data 5384833 # number of overall MSHR misses 2371system.cpu1.dcache.overall_mshr_misses::total 5384833 # number of overall MSHR misses 2372system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 19232 # number of ReadReq MSHR uncacheable 2373system.cpu1.dcache.ReadReq_mshr_uncacheable::total 19232 # number of ReadReq MSHR uncacheable 2374system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17726 # number of WriteReq MSHR uncacheable 2375system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17726 # number of WriteReq MSHR uncacheable 2376system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 36958 # number of overall MSHR uncacheable misses 2377system.cpu1.dcache.overall_mshr_uncacheable_misses::total 36958 # number of overall MSHR uncacheable misses 2378system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 51262951500 # number of ReadReq MSHR miss cycles 2379system.cpu1.dcache.ReadReq_mshr_miss_latency::total 51262951500 # number of ReadReq MSHR miss cycles 2380system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34883587324 # number of WriteReq MSHR miss cycles 2381system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34883587324 # number of WriteReq MSHR miss cycles 2382system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16764876500 # number of SoftPFReq MSHR miss cycles 2383system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16764876500 # number of SoftPFReq MSHR miss cycles 2384system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19026160076 # number of WriteLineReq MSHR miss cycles 2385system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19026160076 # number of WriteLineReq MSHR miss cycles 2386system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2027619500 # number of LoadLockedReq MSHR miss cycles 2387system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2027619500 # number of LoadLockedReq MSHR miss cycles 2388system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5301023500 # number of StoreCondReq MSHR miss cycles 2389system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5301023500 # number of StoreCondReq MSHR miss cycles 2390system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5708500 # number of StoreCondFailReq MSHR miss cycles 2391system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5708500 # number of StoreCondFailReq MSHR miss cycles 2392system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 86146538824 # number of demand (read+write) MSHR miss cycles 2393system.cpu1.dcache.demand_mshr_miss_latency::total 86146538824 # number of demand (read+write) MSHR miss cycles 2394system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102911415324 # number of overall MSHR miss cycles 2395system.cpu1.dcache.overall_mshr_miss_latency::total 102911415324 # number of overall MSHR miss cycles 2396system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3119149500 # number of ReadReq MSHR uncacheable cycles 2397system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3119149500 # number of ReadReq MSHR uncacheable cycles 2398system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2971127000 # number of WriteReq MSHR uncacheable cycles 2399system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2971127000 # number of WriteReq MSHR uncacheable cycles 2400system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6090276500 # number of overall MSHR uncacheable cycles 2401system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6090276500 # number of overall MSHR uncacheable cycles 2402system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037375 # mshr miss rate for ReadReq accesses 2403system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037375 # mshr miss rate for ReadReq accesses 2404system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018754 # mshr miss rate for WriteReq accesses 2405system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018754 # mshr miss rate for WriteReq accesses 2406system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783754 # mshr miss rate for SoftPFReq accesses 2407system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783754 # mshr miss rate for SoftPFReq accesses 2408system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.764561 # mshr miss rate for WriteLineReq accesses 2409system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.764561 # mshr miss rate for WriteLineReq accesses 2410system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067854 # mshr miss rate for LoadLockedReq accesses 2411system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067854 # mshr miss rate for LoadLockedReq accesses 2412system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097313 # mshr miss rate for StoreCondReq accesses 2413system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097313 # mshr miss rate for StoreCondReq accesses 2414system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028746 # mshr miss rate for demand accesses 2415system.cpu1.dcache.demand_mshr_miss_rate::total 0.028746 # mshr miss rate for demand accesses 2416system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032801 # mshr miss rate for overall accesses 2417system.cpu1.dcache.overall_mshr_miss_rate::total 0.032801 # mshr miss rate for overall accesses 2418system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15653.751233 # average ReadReq mshr miss latency 2419system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15653.751233 # average ReadReq mshr miss latency 2420system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24583.495884 # average WriteReq mshr miss latency 2421system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24583.495884 # average WriteReq mshr miss latency 2422system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24260.145490 # average SoftPFReq mshr miss latency 2423system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24260.145490 # average SoftPFReq mshr miss latency 2424system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41473.556800 # average WriteLineReq mshr miss latency 2425system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41473.556800 # average WriteLineReq mshr miss latency 2426system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14566.022758 # average LoadLockedReq mshr miss latency 2427system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14566.022758 # average LoadLockedReq mshr miss latency 2428system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27146.174409 # average StoreCondReq mshr miss latency 2429system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27146.174409 # average StoreCondReq mshr miss latency 2430system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2431system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2432system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18353.312331 # average overall mshr miss latency 2433system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18353.312331 # average overall mshr miss latency 2434system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19111.347617 # average overall mshr miss latency 2435system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19111.347617 # average overall mshr miss latency 2436system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162185.394135 # average ReadReq mshr uncacheable latency 2437system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162185.394135 # average ReadReq mshr uncacheable latency 2438system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167614.069728 # average WriteReq mshr uncacheable latency 2439system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167614.069728 # average WriteReq mshr uncacheable latency 2440system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164789.125494 # average overall mshr uncacheable latency 2441system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 164789.125494 # average overall mshr uncacheable latency 2442system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2443system.cpu1.icache.tags.replacements 6084021 # number of replacements 2444system.cpu1.icache.tags.tagsinuse 501.481326 # Cycle average of tags in use 2445system.cpu1.icache.tags.total_refs 206310871 # Total number of references to valid blocks. 2446system.cpu1.icache.tags.sampled_refs 6084533 # Sample count of references to valid blocks. 2447system.cpu1.icache.tags.avg_refs 33.907429 # Average number of references to valid blocks. 2448system.cpu1.icache.tags.warmup_cycle 8522353869000 # Cycle when the warmup percentage was hit. 2449system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.481326 # Average occupied blocks per requestor 2450system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979456 # Average percentage of cache occupancy 2451system.cpu1.icache.tags.occ_percent::total 0.979456 # Average percentage of cache occupancy 2452system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2453system.cpu1.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 2454system.cpu1.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id 2455system.cpu1.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 2456system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2457system.cpu1.icache.tags.tag_accesses 431579068 # Number of tag accesses 2458system.cpu1.icache.tags.data_accesses 431579068 # Number of data accesses 2459system.cpu1.icache.ReadReq_hits::cpu1.inst 206310871 # number of ReadReq hits 2460system.cpu1.icache.ReadReq_hits::total 206310871 # number of ReadReq hits 2461system.cpu1.icache.demand_hits::cpu1.inst 206310871 # number of demand (read+write) hits 2462system.cpu1.icache.demand_hits::total 206310871 # number of demand (read+write) hits 2463system.cpu1.icache.overall_hits::cpu1.inst 206310871 # number of overall hits 2464system.cpu1.icache.overall_hits::total 206310871 # number of overall hits 2465system.cpu1.icache.ReadReq_misses::cpu1.inst 6436378 # number of ReadReq misses 2466system.cpu1.icache.ReadReq_misses::total 6436378 # number of ReadReq misses 2467system.cpu1.icache.demand_misses::cpu1.inst 6436378 # number of demand (read+write) misses 2468system.cpu1.icache.demand_misses::total 6436378 # number of demand (read+write) misses 2469system.cpu1.icache.overall_misses::cpu1.inst 6436378 # number of overall misses 2470system.cpu1.icache.overall_misses::total 6436378 # number of overall misses 2471system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 72269477183 # number of ReadReq miss cycles 2472system.cpu1.icache.ReadReq_miss_latency::total 72269477183 # number of ReadReq miss cycles 2473system.cpu1.icache.demand_miss_latency::cpu1.inst 72269477183 # number of demand (read+write) miss cycles 2474system.cpu1.icache.demand_miss_latency::total 72269477183 # number of demand (read+write) miss cycles 2475system.cpu1.icache.overall_miss_latency::cpu1.inst 72269477183 # number of overall miss cycles 2476system.cpu1.icache.overall_miss_latency::total 72269477183 # number of overall miss cycles 2477system.cpu1.icache.ReadReq_accesses::cpu1.inst 212747249 # number of ReadReq accesses(hits+misses) 2478system.cpu1.icache.ReadReq_accesses::total 212747249 # number of ReadReq accesses(hits+misses) 2479system.cpu1.icache.demand_accesses::cpu1.inst 212747249 # number of demand (read+write) accesses 2480system.cpu1.icache.demand_accesses::total 212747249 # number of demand (read+write) accesses 2481system.cpu1.icache.overall_accesses::cpu1.inst 212747249 # number of overall (read+write) accesses 2482system.cpu1.icache.overall_accesses::total 212747249 # number of overall (read+write) accesses 2483system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030254 # miss rate for ReadReq accesses 2484system.cpu1.icache.ReadReq_miss_rate::total 0.030254 # miss rate for ReadReq accesses 2485system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030254 # miss rate for demand accesses 2486system.cpu1.icache.demand_miss_rate::total 0.030254 # miss rate for demand accesses 2487system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030254 # miss rate for overall accesses 2488system.cpu1.icache.overall_miss_rate::total 0.030254 # miss rate for overall accesses 2489system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11228.283544 # average ReadReq miss latency 2490system.cpu1.icache.ReadReq_avg_miss_latency::total 11228.283544 # average ReadReq miss latency 2491system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11228.283544 # average overall miss latency 2492system.cpu1.icache.demand_avg_miss_latency::total 11228.283544 # average overall miss latency 2493system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11228.283544 # average overall miss latency 2494system.cpu1.icache.overall_avg_miss_latency::total 11228.283544 # average overall miss latency 2495system.cpu1.icache.blocked_cycles::no_mshrs 11099833 # number of cycles access was blocked 2496system.cpu1.icache.blocked_cycles::no_targets 317 # number of cycles access was blocked 2497system.cpu1.icache.blocked::no_mshrs 762485 # number of cycles access was blocked 2498system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked 2499system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.557444 # average number of cycles each access was blocked 2500system.cpu1.icache.avg_blocked_cycles::no_targets 79.250000 # average number of cycles each access was blocked 2501system.cpu1.icache.fast_writes 0 # number of fast writes performed 2502system.cpu1.icache.cache_copies 0 # number of cache copies performed 2503system.cpu1.icache.writebacks::writebacks 6084021 # number of writebacks 2504system.cpu1.icache.writebacks::total 6084021 # number of writebacks 2505system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 351808 # number of ReadReq MSHR hits 2506system.cpu1.icache.ReadReq_mshr_hits::total 351808 # number of ReadReq MSHR hits 2507system.cpu1.icache.demand_mshr_hits::cpu1.inst 351808 # number of demand (read+write) MSHR hits 2508system.cpu1.icache.demand_mshr_hits::total 351808 # number of demand (read+write) MSHR hits 2509system.cpu1.icache.overall_mshr_hits::cpu1.inst 351808 # number of overall MSHR hits 2510system.cpu1.icache.overall_mshr_hits::total 351808 # number of overall MSHR hits 2511system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6084570 # number of ReadReq MSHR misses 2512system.cpu1.icache.ReadReq_mshr_misses::total 6084570 # number of ReadReq MSHR misses 2513system.cpu1.icache.demand_mshr_misses::cpu1.inst 6084570 # number of demand (read+write) MSHR misses 2514system.cpu1.icache.demand_mshr_misses::total 6084570 # number of demand (read+write) MSHR misses 2515system.cpu1.icache.overall_mshr_misses::cpu1.inst 6084570 # number of overall MSHR misses 2516system.cpu1.icache.overall_mshr_misses::total 6084570 # number of overall MSHR misses 2517system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2518system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2519system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2520system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2521system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 65151824817 # number of ReadReq MSHR miss cycles 2522system.cpu1.icache.ReadReq_mshr_miss_latency::total 65151824817 # number of ReadReq MSHR miss cycles 2523system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 65151824817 # number of demand (read+write) MSHR miss cycles 2524system.cpu1.icache.demand_mshr_miss_latency::total 65151824817 # number of demand (read+write) MSHR miss cycles 2525system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 65151824817 # number of overall MSHR miss cycles 2526system.cpu1.icache.overall_mshr_miss_latency::total 65151824817 # number of overall MSHR miss cycles 2527system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9154498 # number of ReadReq MSHR uncacheable cycles 2528system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9154498 # number of ReadReq MSHR uncacheable cycles 2529system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9154498 # number of overall MSHR uncacheable cycles 2530system.cpu1.icache.overall_mshr_uncacheable_latency::total 9154498 # number of overall MSHR uncacheable cycles 2531system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028600 # mshr miss rate for ReadReq accesses 2532system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028600 # mshr miss rate for ReadReq accesses 2533system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028600 # mshr miss rate for demand accesses 2534system.cpu1.icache.demand_mshr_miss_rate::total 0.028600 # mshr miss rate for demand accesses 2535system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028600 # mshr miss rate for overall accesses 2536system.cpu1.icache.overall_mshr_miss_rate::total 0.028600 # mshr miss rate for overall accesses 2537system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10707.712265 # average ReadReq mshr miss latency 2538system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10707.712265 # average ReadReq mshr miss latency 2539system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10707.712265 # average overall mshr miss latency 2540system.cpu1.icache.demand_avg_mshr_miss_latency::total 10707.712265 # average overall mshr miss latency 2541system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10707.712265 # average overall mshr miss latency 2542system.cpu1.icache.overall_avg_mshr_miss_latency::total 10707.712265 # average overall mshr miss latency 2543system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507 # average ReadReq mshr uncacheable latency 2544system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136634.298507 # average ReadReq mshr uncacheable latency 2545system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507 # average overall mshr uncacheable latency 2546system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136634.298507 # average overall mshr uncacheable latency 2547system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2548system.cpu1.l2cache.prefetcher.num_hwpf_issued 7756566 # number of hwpf issued 2549system.cpu1.l2cache.prefetcher.pfIdentified 7763412 # number of prefetch candidates identified 2550system.cpu1.l2cache.prefetcher.pfBufferHit 6220 # number of redundant prefetches already in prefetch queue 2551system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2552system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2553system.cpu1.l2cache.prefetcher.pfSpanPage 969756 # number of prefetches not generated due to page crossing 2554system.cpu1.l2cache.tags.replacements 2332043 # number of replacements 2555system.cpu1.l2cache.tags.tagsinuse 13399.306231 # Cycle average of tags in use 2556system.cpu1.l2cache.tags.total_refs 17632836 # Total number of references to valid blocks. 2557system.cpu1.l2cache.tags.sampled_refs 2347889 # Sample count of references to valid blocks. 2558system.cpu1.l2cache.tags.avg_refs 7.510081 # Average number of references to valid blocks. 2559system.cpu1.l2cache.tags.warmup_cycle 9842790935000 # Cycle when the warmup percentage was hit. 2560system.cpu1.l2cache.tags.occ_blocks::writebacks 12578.549266 # Average occupied blocks per requestor 2561system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 73.835699 # Average occupied blocks per requestor 2562system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.403592 # Average occupied blocks per requestor 2563system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 671.517674 # Average occupied blocks per requestor 2564system.cpu1.l2cache.tags.occ_percent::writebacks 0.767734 # Average percentage of cache occupancy 2565system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004507 # Average percentage of cache occupancy 2566system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004602 # Average percentage of cache occupancy 2567system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040986 # Average percentage of cache occupancy 2568system.cpu1.l2cache.tags.occ_percent::total 0.817829 # Average percentage of cache occupancy 2569system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1168 # Occupied blocks per task id 2570system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id 2571system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14591 # Occupied blocks per task id 2572system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 2573system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 213 # Occupied blocks per task id 2574system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 557 # Occupied blocks per task id 2575system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 388 # Occupied blocks per task id 2576system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 2577system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2578system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id 2579system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 2580system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 2581system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 2582system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1235 # Occupied blocks per task id 2583system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4922 # Occupied blocks per task id 2584system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4629 # Occupied blocks per task id 2585system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3692 # Occupied blocks per task id 2586system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.071289 # Percentage of cache occupancy per task id 2587system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id 2588system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.890564 # Percentage of cache occupancy per task id 2589system.cpu1.l2cache.tags.tag_accesses 403369890 # Number of tag accesses 2590system.cpu1.l2cache.tags.data_accesses 403369890 # Number of data accesses 2591system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 629324 # number of ReadReq hits 2592system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 196368 # number of ReadReq hits 2593system.cpu1.l2cache.ReadReq_hits::total 825692 # number of ReadReq hits 2594system.cpu1.l2cache.WritebackDirty_hits::writebacks 3534370 # number of WritebackDirty hits 2595system.cpu1.l2cache.WritebackDirty_hits::total 3534370 # number of WritebackDirty hits 2596system.cpu1.l2cache.WritebackClean_hits::writebacks 8212493 # number of WritebackClean hits 2597system.cpu1.l2cache.WritebackClean_hits::total 8212493 # number of WritebackClean hits 2598system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 814 # number of UpgradeReq hits 2599system.cpu1.l2cache.UpgradeReq_hits::total 814 # number of UpgradeReq hits 2600system.cpu1.l2cache.ReadExReq_hits::cpu1.data 892249 # number of ReadExReq hits 2601system.cpu1.l2cache.ReadExReq_hits::total 892249 # number of ReadExReq hits 2602system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5494357 # number of ReadCleanReq hits 2603system.cpu1.l2cache.ReadCleanReq_hits::total 5494357 # number of ReadCleanReq hits 2604system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3102678 # number of ReadSharedReq hits 2605system.cpu1.l2cache.ReadSharedReq_hits::total 3102678 # number of ReadSharedReq hits 2606system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 175982 # number of InvalidateReq hits 2607system.cpu1.l2cache.InvalidateReq_hits::total 175982 # number of InvalidateReq hits 2608system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 629324 # number of demand (read+write) hits 2609system.cpu1.l2cache.demand_hits::cpu1.itb.walker 196368 # number of demand (read+write) hits 2610system.cpu1.l2cache.demand_hits::cpu1.inst 5494357 # number of demand (read+write) hits 2611system.cpu1.l2cache.demand_hits::cpu1.data 3994927 # number of demand (read+write) hits 2612system.cpu1.l2cache.demand_hits::total 10314976 # number of demand (read+write) hits 2613system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 629324 # number of overall hits 2614system.cpu1.l2cache.overall_hits::cpu1.itb.walker 196368 # number of overall hits 2615system.cpu1.l2cache.overall_hits::cpu1.inst 5494357 # number of overall hits 2616system.cpu1.l2cache.overall_hits::cpu1.data 3994927 # number of overall hits 2617system.cpu1.l2cache.overall_hits::total 10314976 # number of overall hits 2618system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13918 # number of ReadReq misses 2619system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10528 # number of ReadReq misses 2620system.cpu1.l2cache.ReadReq_misses::total 24446 # number of ReadReq misses 2621system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 2622system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 2623system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2624system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2625system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 231959 # number of UpgradeReq misses 2626system.cpu1.l2cache.UpgradeReq_misses::total 231959 # number of UpgradeReq misses 2627system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195268 # number of SCUpgradeReq misses 2628system.cpu1.l2cache.SCUpgradeReq_misses::total 195268 # number of SCUpgradeReq misses 2629system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 2630system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 2631system.cpu1.l2cache.ReadExReq_misses::cpu1.data 301055 # number of ReadExReq misses 2632system.cpu1.l2cache.ReadExReq_misses::total 301055 # number of ReadExReq misses 2633system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 590167 # number of ReadCleanReq misses 2634system.cpu1.l2cache.ReadCleanReq_misses::total 590167 # number of ReadCleanReq misses 2635system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 999846 # number of ReadSharedReq misses 2636system.cpu1.l2cache.ReadSharedReq_misses::total 999846 # number of ReadSharedReq misses 2637system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 280900 # number of InvalidateReq misses 2638system.cpu1.l2cache.InvalidateReq_misses::total 280900 # number of InvalidateReq misses 2639system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13918 # number of demand (read+write) misses 2640system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10528 # number of demand (read+write) misses 2641system.cpu1.l2cache.demand_misses::cpu1.inst 590167 # number of demand (read+write) misses 2642system.cpu1.l2cache.demand_misses::cpu1.data 1300901 # number of demand (read+write) misses 2643system.cpu1.l2cache.demand_misses::total 1915514 # number of demand (read+write) misses 2644system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13918 # number of overall misses 2645system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10528 # number of overall misses 2646system.cpu1.l2cache.overall_misses::cpu1.inst 590167 # number of overall misses 2647system.cpu1.l2cache.overall_misses::cpu1.data 1300901 # number of overall misses 2648system.cpu1.l2cache.overall_misses::total 1915514 # number of overall misses 2649system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 754019500 # number of ReadReq miss cycles 2650system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 658882500 # number of ReadReq miss cycles 2651system.cpu1.l2cache.ReadReq_miss_latency::total 1412902000 # number of ReadReq miss cycles 2652system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3524402500 # number of UpgradeReq miss cycles 2653system.cpu1.l2cache.UpgradeReq_miss_latency::total 3524402500 # number of UpgradeReq miss cycles 2654system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1953633500 # number of SCUpgradeReq miss cycles 2655system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1953633500 # number of SCUpgradeReq miss cycles 2656system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5605499 # number of SCUpgradeFailReq miss cycles 2657system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5605499 # number of SCUpgradeFailReq miss cycles 2658system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 17593545499 # number of ReadExReq miss cycles 2659system.cpu1.l2cache.ReadExReq_miss_latency::total 17593545499 # number of ReadExReq miss cycles 2660system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22728280000 # number of ReadCleanReq miss cycles 2661system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22728280000 # number of ReadCleanReq miss cycles 2662system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 43184825986 # number of ReadSharedReq miss cycles 2663system.cpu1.l2cache.ReadSharedReq_miss_latency::total 43184825986 # number of ReadSharedReq miss cycles 2664system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 414465000 # number of InvalidateReq miss cycles 2665system.cpu1.l2cache.InvalidateReq_miss_latency::total 414465000 # number of InvalidateReq miss cycles 2666system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 754019500 # number of demand (read+write) miss cycles 2667system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 658882500 # number of demand (read+write) miss cycles 2668system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22728280000 # number of demand (read+write) miss cycles 2669system.cpu1.l2cache.demand_miss_latency::cpu1.data 60778371485 # number of demand (read+write) miss cycles 2670system.cpu1.l2cache.demand_miss_latency::total 84919553485 # number of demand (read+write) miss cycles 2671system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 754019500 # number of overall miss cycles 2672system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 658882500 # number of overall miss cycles 2673system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22728280000 # number of overall miss cycles 2674system.cpu1.l2cache.overall_miss_latency::cpu1.data 60778371485 # number of overall miss cycles 2675system.cpu1.l2cache.overall_miss_latency::total 84919553485 # number of overall miss cycles 2676system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 643242 # number of ReadReq accesses(hits+misses) 2677system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 206896 # number of ReadReq accesses(hits+misses) 2678system.cpu1.l2cache.ReadReq_accesses::total 850138 # number of ReadReq accesses(hits+misses) 2679system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3534372 # number of WritebackDirty accesses(hits+misses) 2680system.cpu1.l2cache.WritebackDirty_accesses::total 3534372 # number of WritebackDirty accesses(hits+misses) 2681system.cpu1.l2cache.WritebackClean_accesses::writebacks 8212494 # number of WritebackClean accesses(hits+misses) 2682system.cpu1.l2cache.WritebackClean_accesses::total 8212494 # number of WritebackClean accesses(hits+misses) 2683system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 232773 # number of UpgradeReq accesses(hits+misses) 2684system.cpu1.l2cache.UpgradeReq_accesses::total 232773 # number of UpgradeReq accesses(hits+misses) 2685system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195268 # number of SCUpgradeReq accesses(hits+misses) 2686system.cpu1.l2cache.SCUpgradeReq_accesses::total 195268 # number of SCUpgradeReq accesses(hits+misses) 2687system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 2688system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 2689system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1193304 # number of ReadExReq accesses(hits+misses) 2690system.cpu1.l2cache.ReadExReq_accesses::total 1193304 # number of ReadExReq accesses(hits+misses) 2691system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6084524 # number of ReadCleanReq accesses(hits+misses) 2692system.cpu1.l2cache.ReadCleanReq_accesses::total 6084524 # number of ReadCleanReq accesses(hits+misses) 2693system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4102524 # number of ReadSharedReq accesses(hits+misses) 2694system.cpu1.l2cache.ReadSharedReq_accesses::total 4102524 # number of ReadSharedReq accesses(hits+misses) 2695system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 456882 # number of InvalidateReq accesses(hits+misses) 2696system.cpu1.l2cache.InvalidateReq_accesses::total 456882 # number of InvalidateReq accesses(hits+misses) 2697system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 643242 # number of demand (read+write) accesses 2698system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 206896 # number of demand (read+write) accesses 2699system.cpu1.l2cache.demand_accesses::cpu1.inst 6084524 # number of demand (read+write) accesses 2700system.cpu1.l2cache.demand_accesses::cpu1.data 5295828 # number of demand (read+write) accesses 2701system.cpu1.l2cache.demand_accesses::total 12230490 # number of demand (read+write) accesses 2702system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 643242 # number of overall (read+write) accesses 2703system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 206896 # number of overall (read+write) accesses 2704system.cpu1.l2cache.overall_accesses::cpu1.inst 6084524 # number of overall (read+write) accesses 2705system.cpu1.l2cache.overall_accesses::cpu1.data 5295828 # number of overall (read+write) accesses 2706system.cpu1.l2cache.overall_accesses::total 12230490 # number of overall (read+write) accesses 2707system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021637 # miss rate for ReadReq accesses 2708system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050885 # miss rate for ReadReq accesses 2709system.cpu1.l2cache.ReadReq_miss_rate::total 0.028755 # miss rate for ReadReq accesses 2710system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 2711system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 2712system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2713system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2714system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996503 # miss rate for UpgradeReq accesses 2715system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996503 # miss rate for UpgradeReq accesses 2716system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2717system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2718system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2719system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2720system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.252287 # miss rate for ReadExReq accesses 2721system.cpu1.l2cache.ReadExReq_miss_rate::total 0.252287 # miss rate for ReadExReq accesses 2722system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096995 # miss rate for ReadCleanReq accesses 2723system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096995 # miss rate for ReadCleanReq accesses 2724system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.243715 # miss rate for ReadSharedReq accesses 2725system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.243715 # miss rate for ReadSharedReq accesses 2726system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.614820 # miss rate for InvalidateReq accesses 2727system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.614820 # miss rate for InvalidateReq accesses 2728system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021637 # miss rate for demand accesses 2729system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050885 # miss rate for demand accesses 2730system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096995 # miss rate for demand accesses 2731system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.245646 # miss rate for demand accesses 2732system.cpu1.l2cache.demand_miss_rate::total 0.156618 # miss rate for demand accesses 2733system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021637 # miss rate for overall accesses 2734system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050885 # miss rate for overall accesses 2735system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096995 # miss rate for overall accesses 2736system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.245646 # miss rate for overall accesses 2737system.cpu1.l2cache.overall_miss_rate::total 0.156618 # miss rate for overall accesses 2738system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54175.851415 # average ReadReq miss latency 2739system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62583.824088 # average ReadReq miss latency 2740system.cpu1.l2cache.ReadReq_avg_miss_latency::total 57796.858382 # average ReadReq miss latency 2741system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15194.075246 # average UpgradeReq miss latency 2742system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15194.075246 # average UpgradeReq miss latency 2743system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10004.883033 # average SCUpgradeReq miss latency 2744system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10004.883033 # average SCUpgradeReq miss latency 2745system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622833.222222 # average SCUpgradeFailReq miss latency 2746system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622833.222222 # average SCUpgradeFailReq miss latency 2747system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58439.638933 # average ReadExReq miss latency 2748system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58439.638933 # average ReadExReq miss latency 2749system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38511.607731 # average ReadCleanReq miss latency 2750system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38511.607731 # average ReadCleanReq miss latency 2751system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43191.477474 # average ReadSharedReq miss latency 2752system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43191.477474 # average ReadSharedReq miss latency 2753system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1475.489498 # average InvalidateReq miss latency 2754system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1475.489498 # average InvalidateReq miss latency 2755system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54175.851415 # average overall miss latency 2756system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62583.824088 # average overall miss latency 2757system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38511.607731 # average overall miss latency 2758system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 46720.212749 # average overall miss latency 2759system.cpu1.l2cache.demand_avg_miss_latency::total 44332.515181 # average overall miss latency 2760system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54175.851415 # average overall miss latency 2761system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62583.824088 # average overall miss latency 2762system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38511.607731 # average overall miss latency 2763system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 46720.212749 # average overall miss latency 2764system.cpu1.l2cache.overall_avg_miss_latency::total 44332.515181 # average overall miss latency 2765system.cpu1.l2cache.blocked_cycles::no_mshrs 1668 # number of cycles access was blocked 2766system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2767system.cpu1.l2cache.blocked::no_mshrs 18 # number of cycles access was blocked 2768system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2769system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 92.666667 # average number of cycles each access was blocked 2770system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2771system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2772system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2773system.cpu1.l2cache.unused_prefetches 46928 # number of HardPF blocks evicted w/o reference 2774system.cpu1.l2cache.writebacks::writebacks 1248737 # number of writebacks 2775system.cpu1.l2cache.writebacks::total 1248737 # number of writebacks 2776system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits 2777system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 8 # number of ReadReq MSHR hits 2778system.cpu1.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 2779system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 53310 # number of ReadExReq MSHR hits 2780system.cpu1.l2cache.ReadExReq_mshr_hits::total 53310 # number of ReadExReq MSHR hits 2781system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits 2782system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 2783system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 6042 # number of ReadSharedReq MSHR hits 2784system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 6042 # number of ReadSharedReq MSHR hits 2785system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 6 # number of InvalidateReq MSHR hits 2786system.cpu1.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits 2787system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits 2788system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 8 # number of demand (read+write) MSHR hits 2789system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 2790system.cpu1.l2cache.demand_mshr_hits::cpu1.data 59352 # number of demand (read+write) MSHR hits 2791system.cpu1.l2cache.demand_mshr_hits::total 59366 # number of demand (read+write) MSHR hits 2792system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits 2793system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 8 # number of overall MSHR hits 2794system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 2795system.cpu1.l2cache.overall_mshr_hits::cpu1.data 59352 # number of overall MSHR hits 2796system.cpu1.l2cache.overall_mshr_hits::total 59366 # number of overall MSHR hits 2797system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13914 # number of ReadReq MSHR misses 2798system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10520 # number of ReadReq MSHR misses 2799system.cpu1.l2cache.ReadReq_mshr_misses::total 24434 # number of ReadReq MSHR misses 2800system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 2801system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 2802system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2803system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2804system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 810022 # number of HardPFReq MSHR misses 2805system.cpu1.l2cache.HardPFReq_mshr_misses::total 810022 # number of HardPFReq MSHR misses 2806system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 231959 # number of UpgradeReq MSHR misses 2807system.cpu1.l2cache.UpgradeReq_mshr_misses::total 231959 # number of UpgradeReq MSHR misses 2808system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195268 # number of SCUpgradeReq MSHR misses 2809system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195268 # number of SCUpgradeReq MSHR misses 2810system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 2811system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 2812system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 247745 # number of ReadExReq MSHR misses 2813system.cpu1.l2cache.ReadExReq_mshr_misses::total 247745 # number of ReadExReq MSHR misses 2814system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 590165 # number of ReadCleanReq MSHR misses 2815system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 590165 # number of ReadCleanReq MSHR misses 2816system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 993804 # number of ReadSharedReq MSHR misses 2817system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 993804 # number of ReadSharedReq MSHR misses 2818system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 280894 # number of InvalidateReq MSHR misses 2819system.cpu1.l2cache.InvalidateReq_mshr_misses::total 280894 # number of InvalidateReq MSHR misses 2820system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13914 # number of demand (read+write) MSHR misses 2821system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10520 # number of demand (read+write) MSHR misses 2822system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 590165 # number of demand (read+write) MSHR misses 2823system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1241549 # number of demand (read+write) MSHR misses 2824system.cpu1.l2cache.demand_mshr_misses::total 1856148 # number of demand (read+write) MSHR misses 2825system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13914 # number of overall MSHR misses 2826system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10520 # number of overall MSHR misses 2827system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 590165 # number of overall MSHR misses 2828system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1241549 # number of overall MSHR misses 2829system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 810022 # number of overall MSHR misses 2830system.cpu1.l2cache.overall_mshr_misses::total 2666170 # number of overall MSHR misses 2831system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2832system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 19232 # number of ReadReq MSHR uncacheable 2833system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 19299 # number of ReadReq MSHR uncacheable 2834system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17726 # number of WriteReq MSHR uncacheable 2835system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17726 # number of WriteReq MSHR uncacheable 2836system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2837system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 36958 # number of overall MSHR uncacheable misses 2838system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 37025 # number of overall MSHR uncacheable misses 2839system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 670350500 # number of ReadReq MSHR miss cycles 2840system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 595616000 # number of ReadReq MSHR miss cycles 2841system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1265966500 # number of ReadReq MSHR miss cycles 2842system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 58037263327 # number of HardPFReq MSHR miss cycles 2843system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 58037263327 # number of HardPFReq MSHR miss cycles 2844system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7346311996 # number of UpgradeReq MSHR miss cycles 2845system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7346311996 # number of UpgradeReq MSHR miss cycles 2846system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3833341496 # number of SCUpgradeReq MSHR miss cycles 2847system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3833341496 # number of SCUpgradeReq MSHR miss cycles 2848system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5197499 # number of SCUpgradeFailReq MSHR miss cycles 2849system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5197499 # number of SCUpgradeFailReq MSHR miss cycles 2850system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12807729999 # number of ReadExReq MSHR miss cycles 2851system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12807729999 # number of ReadExReq MSHR miss cycles 2852system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 19187264000 # number of ReadCleanReq MSHR miss cycles 2853system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19187264000 # number of ReadCleanReq MSHR miss cycles 2854system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 36825734486 # number of ReadSharedReq MSHR miss cycles 2855system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 36825734486 # number of ReadSharedReq MSHR miss cycles 2856system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 14981372997 # number of InvalidateReq MSHR miss cycles 2857system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 14981372997 # number of InvalidateReq MSHR miss cycles 2858system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 670350500 # number of demand (read+write) MSHR miss cycles 2859system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 595616000 # number of demand (read+write) MSHR miss cycles 2860system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19187264000 # number of demand (read+write) MSHR miss cycles 2861system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 49633464485 # number of demand (read+write) MSHR miss cycles 2862system.cpu1.l2cache.demand_mshr_miss_latency::total 70086694985 # number of demand (read+write) MSHR miss cycles 2863system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 670350500 # number of overall MSHR miss cycles 2864system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 595616000 # number of overall MSHR miss cycles 2865system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19187264000 # number of overall MSHR miss cycles 2866system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 49633464485 # number of overall MSHR miss cycles 2867system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 58037263327 # number of overall MSHR miss cycles 2868system.cpu1.l2cache.overall_mshr_miss_latency::total 128123958312 # number of overall MSHR miss cycles 2869system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8651000 # number of ReadReq MSHR uncacheable cycles 2870system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2965138000 # number of ReadReq MSHR uncacheable cycles 2871system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2973789000 # number of ReadReq MSHR uncacheable cycles 2872system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2838108000 # number of WriteReq MSHR uncacheable cycles 2873system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2838108000 # number of WriteReq MSHR uncacheable cycles 2874system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8651000 # number of overall MSHR uncacheable cycles 2875system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5803246000 # number of overall MSHR uncacheable cycles 2876system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5811897000 # number of overall MSHR uncacheable cycles 2877system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021631 # mshr miss rate for ReadReq accesses 2878system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050847 # mshr miss rate for ReadReq accesses 2879system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028741 # mshr miss rate for ReadReq accesses 2880system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 2881system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 2882system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2883system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2884system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2885system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2886system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996503 # mshr miss rate for UpgradeReq accesses 2887system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996503 # mshr miss rate for UpgradeReq accesses 2888system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2889system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2890system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2891system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2892system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207613 # mshr miss rate for ReadExReq accesses 2893system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207613 # mshr miss rate for ReadExReq accesses 2894system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.096994 # mshr miss rate for ReadCleanReq accesses 2895system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096994 # mshr miss rate for ReadCleanReq accesses 2896system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242242 # mshr miss rate for ReadSharedReq accesses 2897system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242242 # mshr miss rate for ReadSharedReq accesses 2898system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.614806 # mshr miss rate for InvalidateReq accesses 2899system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.614806 # mshr miss rate for InvalidateReq accesses 2900system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021631 # mshr miss rate for demand accesses 2901system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050847 # mshr miss rate for demand accesses 2902system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.096994 # mshr miss rate for demand accesses 2903system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234439 # mshr miss rate for demand accesses 2904system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151764 # mshr miss rate for demand accesses 2905system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021631 # mshr miss rate for overall accesses 2906system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050847 # mshr miss rate for overall accesses 2907system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.096994 # mshr miss rate for overall accesses 2908system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234439 # mshr miss rate for overall accesses 2909system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2910system.cpu1.l2cache.overall_mshr_miss_rate::total 0.217994 # mshr miss rate for overall accesses 2911system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941 # average ReadReq mshr miss latency 2912system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494 # average ReadReq mshr miss latency 2913system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 51811.676353 # average ReadReq mshr miss latency 2914system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357 # average HardPFReq mshr miss latency 2915system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 71648.996357 # average HardPFReq mshr miss latency 2916system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31670.734897 # average UpgradeReq mshr miss latency 2917system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31670.734897 # average UpgradeReq mshr miss latency 2918system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19631.181228 # average SCUpgradeReq mshr miss latency 2919system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19631.181228 # average SCUpgradeReq mshr miss latency 2920system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 577499.888889 # average SCUpgradeFailReq mshr miss latency 2921system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 577499.888889 # average SCUpgradeFailReq mshr miss latency 2922system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 51697.229002 # average ReadExReq mshr miss latency 2923system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 51697.229002 # average ReadExReq mshr miss latency 2924system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32511.694187 # average ReadCleanReq mshr miss latency 2925system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32511.694187 # average ReadCleanReq mshr miss latency 2926system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37055.329306 # average ReadSharedReq mshr miss latency 2927system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37055.329306 # average ReadSharedReq mshr miss latency 2928system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53334.613758 # average InvalidateReq mshr miss latency 2929system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53334.613758 # average InvalidateReq mshr miss latency 2930system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941 # average overall mshr miss latency 2931system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494 # average overall mshr miss latency 2932system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32511.694187 # average overall mshr miss latency 2933system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 39977.048417 # average overall mshr miss latency 2934system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 37759.216929 # average overall mshr miss latency 2935system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941 # average overall mshr miss latency 2936system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494 # average overall mshr miss latency 2937system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32511.694187 # average overall mshr miss latency 2938system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 39977.048417 # average overall mshr miss latency 2939system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357 # average overall mshr miss latency 2940system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 48055.434692 # average overall mshr miss latency 2941system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985 # average ReadReq mshr uncacheable latency 2942system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154177.308652 # average ReadReq mshr uncacheable latency 2943system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154090.315560 # average ReadReq mshr uncacheable latency 2944system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160109.895069 # average WriteReq mshr uncacheable latency 2945system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 160109.895069 # average WriteReq mshr uncacheable latency 2946system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985 # average overall mshr uncacheable latency 2947system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 157022.728503 # average overall mshr uncacheable latency 2948system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 156972.234976 # average overall mshr uncacheable latency 2949system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2950system.cpu1.toL2Bus.snoop_filter.tot_requests 24388069 # Total number of requests made to the snoop filter. 2951system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12550954 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2952system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1330 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2953system.cpu1.toL2Bus.snoop_filter.tot_snoops 2014096 # Total number of snoops made to the snoop filter. 2954system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2013701 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2955system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 395 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2956system.cpu1.toL2Bus.trans_dist::ReadReq 959951 # Transaction distribution 2957system.cpu1.toL2Bus.trans_dist::ReadResp 11237676 # Transaction distribution 2958system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2959system.cpu1.toL2Bus.trans_dist::WriteReq 17726 # Transaction distribution 2960system.cpu1.toL2Bus.trans_dist::WriteResp 17726 # Transaction distribution 2961system.cpu1.toL2Bus.trans_dist::WritebackDirty 4787619 # Transaction distribution 2962system.cpu1.toL2Bus.trans_dist::WritebackClean 8213812 # Transaction distribution 2963system.cpu1.toL2Bus.trans_dist::CleanEvict 2728404 # Transaction distribution 2964system.cpu1.toL2Bus.trans_dist::HardPFReq 1028067 # Transaction distribution 2965system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution 2966system.cpu1.toL2Bus.trans_dist::UpgradeReq 448479 # Transaction distribution 2967system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348012 # Transaction distribution 2968system.cpu1.toL2Bus.trans_dist::UpgradeResp 489399 # Transaction distribution 2969system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 78 # Transaction distribution 2970system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 137 # Transaction distribution 2971system.cpu1.toL2Bus.trans_dist::ReadExReq 1222080 # Transaction distribution 2972system.cpu1.toL2Bus.trans_dist::ReadExResp 1199432 # Transaction distribution 2973system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6084570 # Transaction distribution 2974system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5051662 # Transaction distribution 2975system.cpu1.toL2Bus.trans_dist::InvalidateReq 514998 # Transaction distribution 2976system.cpu1.toL2Bus.trans_dist::InvalidateResp 456882 # Transaction distribution 2977system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18253249 # Packet count per connected master and slave (bytes) 2978system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18257850 # Packet count per connected master and slave (bytes) 2979system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 433982 # Packet count per connected master and slave (bytes) 2980system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1356808 # Packet count per connected master and slave (bytes) 2981system.cpu1.toL2Bus.pkt_count::total 38301889 # Packet count per connected master and slave (bytes) 2982system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 778787952 # Cumulative packet size per connected master and slave (bytes) 2983system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707763692 # Cumulative packet size per connected master and slave (bytes) 2984system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1655168 # Cumulative packet size per connected master and slave (bytes) 2985system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5145936 # Cumulative packet size per connected master and slave (bytes) 2986system.cpu1.toL2Bus.pkt_size::total 1493352748 # Cumulative packet size per connected master and slave (bytes) 2987system.cpu1.toL2Bus.snoops 6663078 # Total snoops (count) 2988system.cpu1.toL2Bus.snoop_fanout::samples 19657279 # Request fanout histogram 2989system.cpu1.toL2Bus.snoop_fanout::mean 0.121604 # Request fanout histogram 2990system.cpu1.toL2Bus.snoop_fanout::stdev 0.326890 # Request fanout histogram 2991system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2992system.cpu1.toL2Bus.snoop_fanout::0 17267267 87.84% 87.84% # Request fanout histogram 2993system.cpu1.toL2Bus.snoop_fanout::1 2389617 12.16% 100.00% # Request fanout histogram 2994system.cpu1.toL2Bus.snoop_fanout::2 395 0.00% 100.00% # Request fanout histogram 2995system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2996system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2997system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2998system.cpu1.toL2Bus.snoop_fanout::total 19657279 # Request fanout histogram 2999system.cpu1.toL2Bus.reqLayer0.occupancy 24252664474 # Layer occupancy (ticks) 3000system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 3001system.cpu1.toL2Bus.snoopLayer0.occupancy 176228657 # Layer occupancy (ticks) 3002system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3003system.cpu1.toL2Bus.respLayer0.occupancy 9133388497 # Layer occupancy (ticks) 3004system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3005system.cpu1.toL2Bus.respLayer1.occupancy 8423069488 # Layer occupancy (ticks) 3006system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3007system.cpu1.toL2Bus.respLayer2.occupancy 227423320 # Layer occupancy (ticks) 3008system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 3009system.cpu1.toL2Bus.respLayer3.occupancy 714183249 # Layer occupancy (ticks) 3010system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 3011system.iobus.trans_dist::ReadReq 40322 # Transaction distribution 3012system.iobus.trans_dist::ReadResp 40322 # Transaction distribution 3013system.iobus.trans_dist::WriteReq 136632 # Transaction distribution 3014system.iobus.trans_dist::WriteResp 136632 # Transaction distribution 3015system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47654 # Packet count per connected master and slave (bytes) 3016system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 3017system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 3018system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 3019system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 3020system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 3021system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 3022system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 3023system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 3024system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3025system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3026system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 3027system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3028system.iobus.pkt_count_system.bridge.master::total 122588 # Packet count per connected master and slave (bytes) 3029system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231240 # Packet count per connected master and slave (bytes) 3030system.iobus.pkt_count_system.realview.ide.dma::total 231240 # Packet count per connected master and slave (bytes) 3031system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3032system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3033system.iobus.pkt_count::total 353908 # Packet count per connected master and slave (bytes) 3034system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47674 # Cumulative packet size per connected master and slave (bytes) 3035system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3036system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3037system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3038system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3039system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3040system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3041system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3042system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3043system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3044system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3045system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 3046system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3047system.iobus.pkt_size_system.bridge.master::total 155695 # Cumulative packet size per connected master and slave (bytes) 3048system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338976 # Cumulative packet size per connected master and slave (bytes) 3049system.iobus.pkt_size_system.realview.ide.dma::total 7338976 # Cumulative packet size per connected master and slave (bytes) 3050system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3051system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3052system.iobus.pkt_size::total 7496757 # Cumulative packet size per connected master and slave (bytes) 3053system.iobus.reqLayer0.occupancy 36957001 # Layer occupancy (ticks) 3054system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3055system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) 3056system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3057system.iobus.reqLayer2.occupancy 329000 # Layer occupancy (ticks) 3058system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3059system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 3060system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3061system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 3062system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3063system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3064system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3065system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 3066system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3067system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 3068system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3069system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3070system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3071system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) 3072system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3073system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 3074system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3075system.iobus.reqLayer23.occupancy 24079502 # Layer occupancy (ticks) 3076system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3077system.iobus.reqLayer24.occupancy 36400000 # Layer occupancy (ticks) 3078system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3079system.iobus.reqLayer25.occupancy 567357875 # Layer occupancy (ticks) 3080system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3081system.iobus.respLayer0.occupancy 92687000 # Layer occupancy (ticks) 3082system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3083system.iobus.respLayer3.occupancy 147936000 # Layer occupancy (ticks) 3084system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3085system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3086system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3087system.iocache.tags.replacements 115615 # number of replacements 3088system.iocache.tags.tagsinuse 11.303922 # Cycle average of tags in use 3089system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3090system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. 3091system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3092system.iocache.tags.warmup_cycle 9121269324000 # Cycle when the warmup percentage was hit. 3093system.iocache.tags.occ_blocks::realview.ethernet 7.412531 # Average occupied blocks per requestor 3094system.iocache.tags.occ_blocks::realview.ide 3.891391 # Average occupied blocks per requestor 3095system.iocache.tags.occ_percent::realview.ethernet 0.463283 # Average percentage of cache occupancy 3096system.iocache.tags.occ_percent::realview.ide 0.243212 # Average percentage of cache occupancy 3097system.iocache.tags.occ_percent::total 0.706495 # Average percentage of cache occupancy 3098system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3099system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3100system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3101system.iocache.tags.tag_accesses 1040937 # Number of tag accesses 3102system.iocache.tags.data_accesses 1040937 # Number of data accesses 3103system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3104system.iocache.ReadReq_misses::realview.ide 8892 # number of ReadReq misses 3105system.iocache.ReadReq_misses::total 8929 # number of ReadReq misses 3106system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3107system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3108system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3109system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3110system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3111system.iocache.demand_misses::realview.ide 8892 # number of demand (read+write) misses 3112system.iocache.demand_misses::total 8932 # number of demand (read+write) misses 3113system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3114system.iocache.overall_misses::realview.ide 8892 # number of overall misses 3115system.iocache.overall_misses::total 8932 # number of overall misses 3116system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles 3117system.iocache.ReadReq_miss_latency::realview.ide 1708541513 # number of ReadReq miss cycles 3118system.iocache.ReadReq_miss_latency::total 1713740013 # number of ReadReq miss cycles 3119system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3120system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3121system.iocache.WriteLineReq_miss_latency::realview.ide 13535070862 # number of WriteLineReq miss cycles 3122system.iocache.WriteLineReq_miss_latency::total 13535070862 # number of WriteLineReq miss cycles 3123system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles 3124system.iocache.demand_miss_latency::realview.ide 1708541513 # number of demand (read+write) miss cycles 3125system.iocache.demand_miss_latency::total 1714109013 # number of demand (read+write) miss cycles 3126system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles 3127system.iocache.overall_miss_latency::realview.ide 1708541513 # number of overall miss cycles 3128system.iocache.overall_miss_latency::total 1714109013 # number of overall miss cycles 3129system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3130system.iocache.ReadReq_accesses::realview.ide 8892 # number of ReadReq accesses(hits+misses) 3131system.iocache.ReadReq_accesses::total 8929 # number of ReadReq accesses(hits+misses) 3132system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3133system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3134system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3135system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3136system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3137system.iocache.demand_accesses::realview.ide 8892 # number of demand (read+write) accesses 3138system.iocache.demand_accesses::total 8932 # number of demand (read+write) accesses 3139system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3140system.iocache.overall_accesses::realview.ide 8892 # number of overall (read+write) accesses 3141system.iocache.overall_accesses::total 8932 # number of overall (read+write) accesses 3142system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3143system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3144system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3145system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3146system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3147system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3148system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3149system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3150system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3151system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3152system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3153system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3154system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3155system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency 3156system.iocache.ReadReq_avg_miss_latency::realview.ide 192143.669928 # average ReadReq miss latency 3157system.iocache.ReadReq_avg_miss_latency::total 191929.668832 # average ReadReq miss latency 3158system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3159system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3160system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126818.368769 # average WriteLineReq miss latency 3161system.iocache.WriteLineReq_avg_miss_latency::total 126818.368769 # average WriteLineReq miss latency 3162system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 3163system.iocache.demand_avg_miss_latency::realview.ide 192143.669928 # average overall miss latency 3164system.iocache.demand_avg_miss_latency::total 191906.517353 # average overall miss latency 3165system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency 3166system.iocache.overall_avg_miss_latency::realview.ide 192143.669928 # average overall miss latency 3167system.iocache.overall_avg_miss_latency::total 191906.517353 # average overall miss latency 3168system.iocache.blocked_cycles::no_mshrs 34688 # number of cycles access was blocked 3169system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3170system.iocache.blocked::no_mshrs 3476 # number of cycles access was blocked 3171system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3172system.iocache.avg_blocked_cycles::no_mshrs 9.979287 # average number of cycles each access was blocked 3173system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3174system.iocache.fast_writes 0 # number of fast writes performed 3175system.iocache.cache_copies 0 # number of cache copies performed 3176system.iocache.writebacks::writebacks 106693 # number of writebacks 3177system.iocache.writebacks::total 106693 # number of writebacks 3178system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3179system.iocache.ReadReq_mshr_misses::realview.ide 8892 # number of ReadReq MSHR misses 3180system.iocache.ReadReq_mshr_misses::total 8929 # number of ReadReq MSHR misses 3181system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3182system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3183system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3184system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3185system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3186system.iocache.demand_mshr_misses::realview.ide 8892 # number of demand (read+write) MSHR misses 3187system.iocache.demand_mshr_misses::total 8932 # number of demand (read+write) MSHR misses 3188system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3189system.iocache.overall_mshr_misses::realview.ide 8892 # number of overall MSHR misses 3190system.iocache.overall_mshr_misses::total 8932 # number of overall MSHR misses 3191system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles 3192system.iocache.ReadReq_mshr_miss_latency::realview.ide 1263941513 # number of ReadReq MSHR miss cycles 3193system.iocache.ReadReq_mshr_miss_latency::total 1267290013 # number of ReadReq MSHR miss cycles 3194system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3195system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3196system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8192379111 # number of WriteLineReq MSHR miss cycles 3197system.iocache.WriteLineReq_mshr_miss_latency::total 8192379111 # number of WriteLineReq MSHR miss cycles 3198system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles 3199system.iocache.demand_mshr_miss_latency::realview.ide 1263941513 # number of demand (read+write) MSHR miss cycles 3200system.iocache.demand_mshr_miss_latency::total 1267509013 # number of demand (read+write) MSHR miss cycles 3201system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles 3202system.iocache.overall_mshr_miss_latency::realview.ide 1263941513 # number of overall MSHR miss cycles 3203system.iocache.overall_mshr_miss_latency::total 1267509013 # number of overall MSHR miss cycles 3204system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3205system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3206system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3207system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3208system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3209system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3210system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3211system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3212system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3213system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3214system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3215system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3216system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3217system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency 3218system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142143.669928 # average ReadReq mshr miss latency 3219system.iocache.ReadReq_avg_mshr_miss_latency::total 141929.668832 # average ReadReq mshr miss latency 3220system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3221system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3222system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76759.417501 # average WriteLineReq mshr miss latency 3223system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76759.417501 # average WriteLineReq mshr miss latency 3224system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 3225system.iocache.demand_avg_mshr_miss_latency::realview.ide 142143.669928 # average overall mshr miss latency 3226system.iocache.demand_avg_mshr_miss_latency::total 141906.517353 # average overall mshr miss latency 3227system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency 3228system.iocache.overall_avg_mshr_miss_latency::realview.ide 142143.669928 # average overall mshr miss latency 3229system.iocache.overall_avg_mshr_miss_latency::total 141906.517353 # average overall mshr miss latency 3230system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3231system.l2c.tags.replacements 1503046 # number of replacements 3232system.l2c.tags.tagsinuse 63375.622092 # Cycle average of tags in use 3233system.l2c.tags.total_refs 6171586 # Total number of references to valid blocks. 3234system.l2c.tags.sampled_refs 1562708 # Sample count of references to valid blocks. 3235system.l2c.tags.avg_refs 3.949289 # Average number of references to valid blocks. 3236system.l2c.tags.warmup_cycle 4906135000 # Cycle when the warmup percentage was hit. 3237system.l2c.tags.occ_blocks::writebacks 21677.292557 # Average occupied blocks per requestor 3238system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.067014 # Average occupied blocks per requestor 3239system.l2c.tags.occ_blocks::cpu0.itb.walker 94.369601 # Average occupied blocks per requestor 3240system.l2c.tags.occ_blocks::cpu0.inst 3446.989039 # Average occupied blocks per requestor 3241system.l2c.tags.occ_blocks::cpu0.data 6115.798225 # Average occupied blocks per requestor 3242system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 4388.751690 # Average occupied blocks per requestor 3243system.l2c.tags.occ_blocks::cpu1.dtb.walker 261.257745 # Average occupied blocks per requestor 3244system.l2c.tags.occ_blocks::cpu1.itb.walker 419.349614 # Average occupied blocks per requestor 3245system.l2c.tags.occ_blocks::cpu1.inst 3918.629584 # Average occupied blocks per requestor 3246system.l2c.tags.occ_blocks::cpu1.data 8309.441217 # Average occupied blocks per requestor 3247system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14660.675806 # Average occupied blocks per requestor 3248system.l2c.tags.occ_percent::writebacks 0.330769 # Average percentage of cache occupancy 3249system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001268 # Average percentage of cache occupancy 3250system.l2c.tags.occ_percent::cpu0.itb.walker 0.001440 # Average percentage of cache occupancy 3251system.l2c.tags.occ_percent::cpu0.inst 0.052597 # Average percentage of cache occupancy 3252system.l2c.tags.occ_percent::cpu0.data 0.093320 # Average percentage of cache occupancy 3253system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.066967 # Average percentage of cache occupancy 3254system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003986 # Average percentage of cache occupancy 3255system.l2c.tags.occ_percent::cpu1.itb.walker 0.006399 # Average percentage of cache occupancy 3256system.l2c.tags.occ_percent::cpu1.inst 0.059794 # Average percentage of cache occupancy 3257system.l2c.tags.occ_percent::cpu1.data 0.126792 # Average percentage of cache occupancy 3258system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.223704 # Average percentage of cache occupancy 3259system.l2c.tags.occ_percent::total 0.967035 # Average percentage of cache occupancy 3260system.l2c.tags.occ_task_id_blocks::1022 9545 # Occupied blocks per task id 3261system.l2c.tags.occ_task_id_blocks::1023 198 # Occupied blocks per task id 3262system.l2c.tags.occ_task_id_blocks::1024 49919 # Occupied blocks per task id 3263system.l2c.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 3264system.l2c.tags.age_task_id_blocks_1022::2 721 # Occupied blocks per task id 3265system.l2c.tags.age_task_id_blocks_1022::3 554 # Occupied blocks per task id 3266system.l2c.tags.age_task_id_blocks_1022::4 8260 # Occupied blocks per task id 3267system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 3268system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 3269system.l2c.tags.age_task_id_blocks_1023::4 193 # Occupied blocks per task id 3270system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 3271system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id 3272system.l2c.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id 3273system.l2c.tags.age_task_id_blocks_1024::3 5698 # Occupied blocks per task id 3274system.l2c.tags.age_task_id_blocks_1024::4 40984 # Occupied blocks per task id 3275system.l2c.tags.occ_task_id_percent::1022 0.145645 # Percentage of cache occupancy per task id 3276system.l2c.tags.occ_task_id_percent::1023 0.003021 # Percentage of cache occupancy per task id 3277system.l2c.tags.occ_task_id_percent::1024 0.761703 # Percentage of cache occupancy per task id 3278system.l2c.tags.tag_accesses 78456956 # Number of tag accesses 3279system.l2c.tags.data_accesses 78456956 # Number of data accesses 3280system.l2c.WritebackDirty_hits::writebacks 2864457 # number of WritebackDirty hits 3281system.l2c.WritebackDirty_hits::total 2864457 # number of WritebackDirty hits 3282system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 3283system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 3284system.l2c.UpgradeReq_hits::cpu0.data 177336 # number of UpgradeReq hits 3285system.l2c.UpgradeReq_hits::cpu1.data 132362 # number of UpgradeReq hits 3286system.l2c.UpgradeReq_hits::total 309698 # number of UpgradeReq hits 3287system.l2c.SCUpgradeReq_hits::cpu0.data 38451 # number of SCUpgradeReq hits 3288system.l2c.SCUpgradeReq_hits::cpu1.data 42622 # number of SCUpgradeReq hits 3289system.l2c.SCUpgradeReq_hits::total 81073 # number of SCUpgradeReq hits 3290system.l2c.ReadExReq_hits::cpu0.data 52385 # number of ReadExReq hits 3291system.l2c.ReadExReq_hits::cpu1.data 53709 # number of ReadExReq hits 3292system.l2c.ReadExReq_hits::total 106094 # number of ReadExReq hits 3293system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6384 # number of ReadSharedReq hits 3294system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4273 # number of ReadSharedReq hits 3295system.l2c.ReadSharedReq_hits::cpu0.inst 499570 # number of ReadSharedReq hits 3296system.l2c.ReadSharedReq_hits::cpu0.data 608768 # number of ReadSharedReq hits 3297system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 311188 # number of ReadSharedReq hits 3298system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6757 # number of ReadSharedReq hits 3299system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4531 # number of ReadSharedReq hits 3300system.l2c.ReadSharedReq_hits::cpu1.inst 536739 # number of ReadSharedReq hits 3301system.l2c.ReadSharedReq_hits::cpu1.data 583922 # number of ReadSharedReq hits 3302system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292843 # number of ReadSharedReq hits 3303system.l2c.ReadSharedReq_hits::total 2854975 # number of ReadSharedReq hits 3304system.l2c.InvalidateReq_hits::cpu0.data 132875 # number of InvalidateReq hits 3305system.l2c.InvalidateReq_hits::cpu1.data 127159 # number of InvalidateReq hits 3306system.l2c.InvalidateReq_hits::total 260034 # number of InvalidateReq hits 3307system.l2c.demand_hits::cpu0.dtb.walker 6384 # number of demand (read+write) hits 3308system.l2c.demand_hits::cpu0.itb.walker 4273 # number of demand (read+write) hits 3309system.l2c.demand_hits::cpu0.inst 499570 # number of demand (read+write) hits 3310system.l2c.demand_hits::cpu0.data 661153 # number of demand (read+write) hits 3311system.l2c.demand_hits::cpu0.l2cache.prefetcher 311188 # number of demand (read+write) hits 3312system.l2c.demand_hits::cpu1.dtb.walker 6757 # number of demand (read+write) hits 3313system.l2c.demand_hits::cpu1.itb.walker 4531 # number of demand (read+write) hits 3314system.l2c.demand_hits::cpu1.inst 536739 # number of demand (read+write) hits 3315system.l2c.demand_hits::cpu1.data 637631 # number of demand (read+write) hits 3316system.l2c.demand_hits::cpu1.l2cache.prefetcher 292843 # number of demand (read+write) hits 3317system.l2c.demand_hits::total 2961069 # number of demand (read+write) hits 3318system.l2c.overall_hits::cpu0.dtb.walker 6384 # number of overall hits 3319system.l2c.overall_hits::cpu0.itb.walker 4273 # number of overall hits 3320system.l2c.overall_hits::cpu0.inst 499570 # number of overall hits 3321system.l2c.overall_hits::cpu0.data 661153 # number of overall hits 3322system.l2c.overall_hits::cpu0.l2cache.prefetcher 311188 # number of overall hits 3323system.l2c.overall_hits::cpu1.dtb.walker 6757 # number of overall hits 3324system.l2c.overall_hits::cpu1.itb.walker 4531 # number of overall hits 3325system.l2c.overall_hits::cpu1.inst 536739 # number of overall hits 3326system.l2c.overall_hits::cpu1.data 637631 # number of overall hits 3327system.l2c.overall_hits::cpu1.l2cache.prefetcher 292843 # number of overall hits 3328system.l2c.overall_hits::total 2961069 # number of overall hits 3329system.l2c.UpgradeReq_misses::cpu0.data 62895 # number of UpgradeReq misses 3330system.l2c.UpgradeReq_misses::cpu1.data 64271 # number of UpgradeReq misses 3331system.l2c.UpgradeReq_misses::total 127166 # number of UpgradeReq misses 3332system.l2c.SCUpgradeReq_misses::cpu0.data 12027 # number of SCUpgradeReq misses 3333system.l2c.SCUpgradeReq_misses::cpu1.data 12595 # number of SCUpgradeReq misses 3334system.l2c.SCUpgradeReq_misses::total 24622 # number of SCUpgradeReq misses 3335system.l2c.ReadExReq_misses::cpu0.data 80267 # number of ReadExReq misses 3336system.l2c.ReadExReq_misses::cpu1.data 60030 # number of ReadExReq misses 3337system.l2c.ReadExReq_misses::total 140297 # number of ReadExReq misses 3338system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1639 # number of ReadSharedReq misses 3339system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1057 # number of ReadSharedReq misses 3340system.l2c.ReadSharedReq_misses::cpu0.inst 49818 # number of ReadSharedReq misses 3341system.l2c.ReadSharedReq_misses::cpu0.data 124211 # number of ReadSharedReq misses 3342system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 228039 # number of ReadSharedReq misses 3343system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3279 # number of ReadSharedReq misses 3344system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3223 # number of ReadSharedReq misses 3345system.l2c.ReadSharedReq_misses::cpu1.inst 53421 # number of ReadSharedReq misses 3346system.l2c.ReadSharedReq_misses::cpu1.data 140654 # number of ReadSharedReq misses 3347system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 285232 # number of ReadSharedReq misses 3348system.l2c.ReadSharedReq_misses::total 890573 # number of ReadSharedReq misses 3349system.l2c.InvalidateReq_misses::cpu0.data 448396 # number of InvalidateReq misses 3350system.l2c.InvalidateReq_misses::cpu1.data 141685 # number of InvalidateReq misses 3351system.l2c.InvalidateReq_misses::total 590081 # number of InvalidateReq misses 3352system.l2c.demand_misses::cpu0.dtb.walker 1639 # number of demand (read+write) misses 3353system.l2c.demand_misses::cpu0.itb.walker 1057 # number of demand (read+write) misses 3354system.l2c.demand_misses::cpu0.inst 49818 # number of demand (read+write) misses 3355system.l2c.demand_misses::cpu0.data 204478 # number of demand (read+write) misses 3356system.l2c.demand_misses::cpu0.l2cache.prefetcher 228039 # number of demand (read+write) misses 3357system.l2c.demand_misses::cpu1.dtb.walker 3279 # number of demand (read+write) misses 3358system.l2c.demand_misses::cpu1.itb.walker 3223 # number of demand (read+write) misses 3359system.l2c.demand_misses::cpu1.inst 53421 # number of demand (read+write) misses 3360system.l2c.demand_misses::cpu1.data 200684 # number of demand (read+write) misses 3361system.l2c.demand_misses::cpu1.l2cache.prefetcher 285232 # number of demand (read+write) misses 3362system.l2c.demand_misses::total 1030870 # number of demand (read+write) misses 3363system.l2c.overall_misses::cpu0.dtb.walker 1639 # number of overall misses 3364system.l2c.overall_misses::cpu0.itb.walker 1057 # number of overall misses 3365system.l2c.overall_misses::cpu0.inst 49818 # number of overall misses 3366system.l2c.overall_misses::cpu0.data 204478 # number of overall misses 3367system.l2c.overall_misses::cpu0.l2cache.prefetcher 228039 # number of overall misses 3368system.l2c.overall_misses::cpu1.dtb.walker 3279 # number of overall misses 3369system.l2c.overall_misses::cpu1.itb.walker 3223 # number of overall misses 3370system.l2c.overall_misses::cpu1.inst 53421 # number of overall misses 3371system.l2c.overall_misses::cpu1.data 200684 # number of overall misses 3372system.l2c.overall_misses::cpu1.l2cache.prefetcher 285232 # number of overall misses 3373system.l2c.overall_misses::total 1030870 # number of overall misses 3374system.l2c.UpgradeReq_miss_latency::cpu0.data 1112376000 # number of UpgradeReq miss cycles 3375system.l2c.UpgradeReq_miss_latency::cpu1.data 1041657500 # number of UpgradeReq miss cycles 3376system.l2c.UpgradeReq_miss_latency::total 2154033500 # number of UpgradeReq miss cycles 3377system.l2c.SCUpgradeReq_miss_latency::cpu0.data 166517500 # number of SCUpgradeReq miss cycles 3378system.l2c.SCUpgradeReq_miss_latency::cpu1.data 204256500 # number of SCUpgradeReq miss cycles 3379system.l2c.SCUpgradeReq_miss_latency::total 370774000 # number of SCUpgradeReq miss cycles 3380system.l2c.ReadExReq_miss_latency::cpu0.data 11267452492 # number of ReadExReq miss cycles 3381system.l2c.ReadExReq_miss_latency::cpu1.data 8441524499 # number of ReadExReq miss cycles 3382system.l2c.ReadExReq_miss_latency::total 19708976991 # number of ReadExReq miss cycles 3383system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 239750000 # number of ReadSharedReq miss cycles 3384system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 155989500 # number of ReadSharedReq miss cycles 3385system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6853821500 # number of ReadSharedReq miss cycles 3386system.l2c.ReadSharedReq_miss_latency::cpu0.data 17860631492 # number of ReadSharedReq miss cycles 3387system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 42675512933 # number of ReadSharedReq miss cycles 3388system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 464430000 # number of ReadSharedReq miss cycles 3389system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 455098500 # number of ReadSharedReq miss cycles 3390system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7368110000 # number of ReadSharedReq miss cycles 3391system.l2c.ReadSharedReq_miss_latency::cpu1.data 20598242999 # number of ReadSharedReq miss cycles 3392system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 52661073904 # number of ReadSharedReq miss cycles 3393system.l2c.ReadSharedReq_miss_latency::total 149332660828 # number of ReadSharedReq miss cycles 3394system.l2c.InvalidateReq_miss_latency::cpu0.data 199010000 # number of InvalidateReq miss cycles 3395system.l2c.InvalidateReq_miss_latency::cpu1.data 130631000 # number of InvalidateReq miss cycles 3396system.l2c.InvalidateReq_miss_latency::total 329641000 # number of InvalidateReq miss cycles 3397system.l2c.demand_miss_latency::cpu0.dtb.walker 239750000 # number of demand (read+write) miss cycles 3398system.l2c.demand_miss_latency::cpu0.itb.walker 155989500 # number of demand (read+write) miss cycles 3399system.l2c.demand_miss_latency::cpu0.inst 6853821500 # number of demand (read+write) miss cycles 3400system.l2c.demand_miss_latency::cpu0.data 29128083984 # number of demand (read+write) miss cycles 3401system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 42675512933 # number of demand (read+write) miss cycles 3402system.l2c.demand_miss_latency::cpu1.dtb.walker 464430000 # number of demand (read+write) miss cycles 3403system.l2c.demand_miss_latency::cpu1.itb.walker 455098500 # number of demand (read+write) miss cycles 3404system.l2c.demand_miss_latency::cpu1.inst 7368110000 # number of demand (read+write) miss cycles 3405system.l2c.demand_miss_latency::cpu1.data 29039767498 # number of demand (read+write) miss cycles 3406system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 52661073904 # number of demand (read+write) miss cycles 3407system.l2c.demand_miss_latency::total 169041637819 # number of demand (read+write) miss cycles 3408system.l2c.overall_miss_latency::cpu0.dtb.walker 239750000 # number of overall miss cycles 3409system.l2c.overall_miss_latency::cpu0.itb.walker 155989500 # number of overall miss cycles 3410system.l2c.overall_miss_latency::cpu0.inst 6853821500 # number of overall miss cycles 3411system.l2c.overall_miss_latency::cpu0.data 29128083984 # number of overall miss cycles 3412system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 42675512933 # number of overall miss cycles 3413system.l2c.overall_miss_latency::cpu1.dtb.walker 464430000 # number of overall miss cycles 3414system.l2c.overall_miss_latency::cpu1.itb.walker 455098500 # number of overall miss cycles 3415system.l2c.overall_miss_latency::cpu1.inst 7368110000 # number of overall miss cycles 3416system.l2c.overall_miss_latency::cpu1.data 29039767498 # number of overall miss cycles 3417system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 52661073904 # number of overall miss cycles 3418system.l2c.overall_miss_latency::total 169041637819 # number of overall miss cycles 3419system.l2c.WritebackDirty_accesses::writebacks 2864457 # number of WritebackDirty accesses(hits+misses) 3420system.l2c.WritebackDirty_accesses::total 2864457 # number of WritebackDirty accesses(hits+misses) 3421system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 3422system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 3423system.l2c.UpgradeReq_accesses::cpu0.data 240231 # number of UpgradeReq accesses(hits+misses) 3424system.l2c.UpgradeReq_accesses::cpu1.data 196633 # number of UpgradeReq accesses(hits+misses) 3425system.l2c.UpgradeReq_accesses::total 436864 # number of UpgradeReq accesses(hits+misses) 3426system.l2c.SCUpgradeReq_accesses::cpu0.data 50478 # number of SCUpgradeReq accesses(hits+misses) 3427system.l2c.SCUpgradeReq_accesses::cpu1.data 55217 # number of SCUpgradeReq accesses(hits+misses) 3428system.l2c.SCUpgradeReq_accesses::total 105695 # number of SCUpgradeReq accesses(hits+misses) 3429system.l2c.ReadExReq_accesses::cpu0.data 132652 # number of ReadExReq accesses(hits+misses) 3430system.l2c.ReadExReq_accesses::cpu1.data 113739 # number of ReadExReq accesses(hits+misses) 3431system.l2c.ReadExReq_accesses::total 246391 # number of ReadExReq accesses(hits+misses) 3432system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8023 # number of ReadSharedReq accesses(hits+misses) 3433system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5330 # number of ReadSharedReq accesses(hits+misses) 3434system.l2c.ReadSharedReq_accesses::cpu0.inst 549388 # number of ReadSharedReq accesses(hits+misses) 3435system.l2c.ReadSharedReq_accesses::cpu0.data 732979 # number of ReadSharedReq accesses(hits+misses) 3436system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 539227 # number of ReadSharedReq accesses(hits+misses) 3437system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 10036 # number of ReadSharedReq accesses(hits+misses) 3438system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7754 # number of ReadSharedReq accesses(hits+misses) 3439system.l2c.ReadSharedReq_accesses::cpu1.inst 590160 # number of ReadSharedReq accesses(hits+misses) 3440system.l2c.ReadSharedReq_accesses::cpu1.data 724576 # number of ReadSharedReq accesses(hits+misses) 3441system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 578075 # number of ReadSharedReq accesses(hits+misses) 3442system.l2c.ReadSharedReq_accesses::total 3745548 # number of ReadSharedReq accesses(hits+misses) 3443system.l2c.InvalidateReq_accesses::cpu0.data 581271 # number of InvalidateReq accesses(hits+misses) 3444system.l2c.InvalidateReq_accesses::cpu1.data 268844 # number of InvalidateReq accesses(hits+misses) 3445system.l2c.InvalidateReq_accesses::total 850115 # number of InvalidateReq accesses(hits+misses) 3446system.l2c.demand_accesses::cpu0.dtb.walker 8023 # number of demand (read+write) accesses 3447system.l2c.demand_accesses::cpu0.itb.walker 5330 # number of demand (read+write) accesses 3448system.l2c.demand_accesses::cpu0.inst 549388 # number of demand (read+write) accesses 3449system.l2c.demand_accesses::cpu0.data 865631 # number of demand (read+write) accesses 3450system.l2c.demand_accesses::cpu0.l2cache.prefetcher 539227 # number of demand (read+write) accesses 3451system.l2c.demand_accesses::cpu1.dtb.walker 10036 # number of demand (read+write) accesses 3452system.l2c.demand_accesses::cpu1.itb.walker 7754 # number of demand (read+write) accesses 3453system.l2c.demand_accesses::cpu1.inst 590160 # number of demand (read+write) accesses 3454system.l2c.demand_accesses::cpu1.data 838315 # number of demand (read+write) accesses 3455system.l2c.demand_accesses::cpu1.l2cache.prefetcher 578075 # number of demand (read+write) accesses 3456system.l2c.demand_accesses::total 3991939 # number of demand (read+write) accesses 3457system.l2c.overall_accesses::cpu0.dtb.walker 8023 # number of overall (read+write) accesses 3458system.l2c.overall_accesses::cpu0.itb.walker 5330 # number of overall (read+write) accesses 3459system.l2c.overall_accesses::cpu0.inst 549388 # number of overall (read+write) accesses 3460system.l2c.overall_accesses::cpu0.data 865631 # number of overall (read+write) accesses 3461system.l2c.overall_accesses::cpu0.l2cache.prefetcher 539227 # number of overall (read+write) accesses 3462system.l2c.overall_accesses::cpu1.dtb.walker 10036 # number of overall (read+write) accesses 3463system.l2c.overall_accesses::cpu1.itb.walker 7754 # number of overall (read+write) accesses 3464system.l2c.overall_accesses::cpu1.inst 590160 # number of overall (read+write) accesses 3465system.l2c.overall_accesses::cpu1.data 838315 # number of overall (read+write) accesses 3466system.l2c.overall_accesses::cpu1.l2cache.prefetcher 578075 # number of overall (read+write) accesses 3467system.l2c.overall_accesses::total 3991939 # number of overall (read+write) accesses 3468system.l2c.UpgradeReq_miss_rate::cpu0.data 0.261811 # miss rate for UpgradeReq accesses 3469system.l2c.UpgradeReq_miss_rate::cpu1.data 0.326858 # miss rate for UpgradeReq accesses 3470system.l2c.UpgradeReq_miss_rate::total 0.291088 # miss rate for UpgradeReq accesses 3471system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.238262 # miss rate for SCUpgradeReq accesses 3472system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.228100 # miss rate for SCUpgradeReq accesses 3473system.l2c.SCUpgradeReq_miss_rate::total 0.232953 # miss rate for SCUpgradeReq accesses 3474system.l2c.ReadExReq_miss_rate::cpu0.data 0.605095 # miss rate for ReadExReq accesses 3475system.l2c.ReadExReq_miss_rate::cpu1.data 0.527787 # miss rate for ReadExReq accesses 3476system.l2c.ReadExReq_miss_rate::total 0.569408 # miss rate for ReadExReq accesses 3477system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.204288 # miss rate for ReadSharedReq accesses 3478system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.198311 # miss rate for ReadSharedReq accesses 3479system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.090679 # miss rate for ReadSharedReq accesses 3480system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.169461 # miss rate for ReadSharedReq accesses 3481system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.422900 # miss rate for ReadSharedReq accesses 3482system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.326724 # miss rate for ReadSharedReq accesses 3483system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.415656 # miss rate for ReadSharedReq accesses 3484system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090520 # miss rate for ReadSharedReq accesses 3485system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.194119 # miss rate for ReadSharedReq accesses 3486system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.493417 # miss rate for ReadSharedReq accesses 3487system.l2c.ReadSharedReq_miss_rate::total 0.237768 # miss rate for ReadSharedReq accesses 3488system.l2c.InvalidateReq_miss_rate::cpu0.data 0.771406 # miss rate for InvalidateReq accesses 3489system.l2c.InvalidateReq_miss_rate::cpu1.data 0.527016 # miss rate for InvalidateReq accesses 3490system.l2c.InvalidateReq_miss_rate::total 0.694119 # miss rate for InvalidateReq accesses 3491system.l2c.demand_miss_rate::cpu0.dtb.walker 0.204288 # miss rate for demand accesses 3492system.l2c.demand_miss_rate::cpu0.itb.walker 0.198311 # miss rate for demand accesses 3493system.l2c.demand_miss_rate::cpu0.inst 0.090679 # miss rate for demand accesses 3494system.l2c.demand_miss_rate::cpu0.data 0.236218 # miss rate for demand accesses 3495system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.422900 # miss rate for demand accesses 3496system.l2c.demand_miss_rate::cpu1.dtb.walker 0.326724 # miss rate for demand accesses 3497system.l2c.demand_miss_rate::cpu1.itb.walker 0.415656 # miss rate for demand accesses 3498system.l2c.demand_miss_rate::cpu1.inst 0.090520 # miss rate for demand accesses 3499system.l2c.demand_miss_rate::cpu1.data 0.239390 # miss rate for demand accesses 3500system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.493417 # miss rate for demand accesses 3501system.l2c.demand_miss_rate::total 0.258238 # miss rate for demand accesses 3502system.l2c.overall_miss_rate::cpu0.dtb.walker 0.204288 # miss rate for overall accesses 3503system.l2c.overall_miss_rate::cpu0.itb.walker 0.198311 # miss rate for overall accesses 3504system.l2c.overall_miss_rate::cpu0.inst 0.090679 # miss rate for overall accesses 3505system.l2c.overall_miss_rate::cpu0.data 0.236218 # miss rate for overall accesses 3506system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.422900 # miss rate for overall accesses 3507system.l2c.overall_miss_rate::cpu1.dtb.walker 0.326724 # miss rate for overall accesses 3508system.l2c.overall_miss_rate::cpu1.itb.walker 0.415656 # miss rate for overall accesses 3509system.l2c.overall_miss_rate::cpu1.inst 0.090520 # miss rate for overall accesses 3510system.l2c.overall_miss_rate::cpu1.data 0.239390 # miss rate for overall accesses 3511system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.493417 # miss rate for overall accesses 3512system.l2c.overall_miss_rate::total 0.258238 # miss rate for overall accesses 3513system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17686.238970 # average UpgradeReq miss latency 3514system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16207.270775 # average UpgradeReq miss latency 3515system.l2c.UpgradeReq_avg_miss_latency::total 16938.753283 # average UpgradeReq miss latency 3516system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13845.306394 # average SCUpgradeReq miss latency 3517system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16217.268757 # average SCUpgradeReq miss latency 3518system.l2c.SCUpgradeReq_avg_miss_latency::total 15058.646739 # average SCUpgradeReq miss latency 3519system.l2c.ReadExReq_avg_miss_latency::cpu0.data 140374.655736 # average ReadExReq miss latency 3520system.l2c.ReadExReq_avg_miss_latency::cpu1.data 140621.764101 # average ReadExReq miss latency 3521system.l2c.ReadExReq_avg_miss_latency::total 140480.387970 # average ReadExReq miss latency 3522system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146278.218426 # average ReadSharedReq miss latency 3523system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 147577.578051 # average ReadSharedReq miss latency 3524system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137577.211048 # average ReadSharedReq miss latency 3525system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 143792.671277 # average ReadSharedReq miss latency 3526system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327 # average ReadSharedReq miss latency 3527system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141637.694419 # average ReadSharedReq miss latency 3528system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141203.381942 # average ReadSharedReq miss latency 3529system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137925.347710 # average ReadSharedReq miss latency 3530system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146446.194200 # average ReadSharedReq miss latency 3531system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350 # average ReadSharedReq miss latency 3532system.l2c.ReadSharedReq_avg_miss_latency::total 167681.549775 # average ReadSharedReq miss latency 3533system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 443.826439 # average InvalidateReq miss latency 3534system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 921.981861 # average InvalidateReq miss latency 3535system.l2c.InvalidateReq_avg_miss_latency::total 558.636865 # average InvalidateReq miss latency 3536system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146278.218426 # average overall miss latency 3537system.l2c.demand_avg_miss_latency::cpu0.itb.walker 147577.578051 # average overall miss latency 3538system.l2c.demand_avg_miss_latency::cpu0.inst 137577.211048 # average overall miss latency 3539system.l2c.demand_avg_miss_latency::cpu0.data 142450.943300 # average overall miss latency 3540system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327 # average overall miss latency 3541system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141637.694419 # average overall miss latency 3542system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141203.381942 # average overall miss latency 3543system.l2c.demand_avg_miss_latency::cpu1.inst 137925.347710 # average overall miss latency 3544system.l2c.demand_avg_miss_latency::cpu1.data 144703.949981 # average overall miss latency 3545system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350 # average overall miss latency 3546system.l2c.demand_avg_miss_latency::total 163979.587939 # average overall miss latency 3547system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 146278.218426 # average overall miss latency 3548system.l2c.overall_avg_miss_latency::cpu0.itb.walker 147577.578051 # average overall miss latency 3549system.l2c.overall_avg_miss_latency::cpu0.inst 137577.211048 # average overall miss latency 3550system.l2c.overall_avg_miss_latency::cpu0.data 142450.943300 # average overall miss latency 3551system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327 # average overall miss latency 3552system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141637.694419 # average overall miss latency 3553system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141203.381942 # average overall miss latency 3554system.l2c.overall_avg_miss_latency::cpu1.inst 137925.347710 # average overall miss latency 3555system.l2c.overall_avg_miss_latency::cpu1.data 144703.949981 # average overall miss latency 3556system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350 # average overall miss latency 3557system.l2c.overall_avg_miss_latency::total 163979.587939 # average overall miss latency 3558system.l2c.blocked_cycles::no_mshrs 14431 # number of cycles access was blocked 3559system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3560system.l2c.blocked::no_mshrs 146 # number of cycles access was blocked 3561system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3562system.l2c.avg_blocked_cycles::no_mshrs 98.842466 # average number of cycles each access was blocked 3563system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3564system.l2c.fast_writes 0 # number of fast writes performed 3565system.l2c.cache_copies 0 # number of cache copies performed 3566system.l2c.writebacks::writebacks 1201695 # number of writebacks 3567system.l2c.writebacks::total 1201695 # number of writebacks 3568system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 163 # number of ReadSharedReq MSHR hits 3569system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 3570system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 145 # number of ReadSharedReq MSHR hits 3571system.l2c.ReadSharedReq_mshr_hits::cpu1.data 9 # number of ReadSharedReq MSHR hits 3572system.l2c.ReadSharedReq_mshr_hits::total 342 # number of ReadSharedReq MSHR hits 3573system.l2c.demand_mshr_hits::cpu0.inst 163 # number of demand (read+write) MSHR hits 3574system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 3575system.l2c.demand_mshr_hits::cpu1.inst 145 # number of demand (read+write) MSHR hits 3576system.l2c.demand_mshr_hits::cpu1.data 9 # number of demand (read+write) MSHR hits 3577system.l2c.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits 3578system.l2c.overall_mshr_hits::cpu0.inst 163 # number of overall MSHR hits 3579system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 3580system.l2c.overall_mshr_hits::cpu1.inst 145 # number of overall MSHR hits 3581system.l2c.overall_mshr_hits::cpu1.data 9 # number of overall MSHR hits 3582system.l2c.overall_mshr_hits::total 342 # number of overall MSHR hits 3583system.l2c.CleanEvict_mshr_misses::writebacks 53917 # number of CleanEvict MSHR misses 3584system.l2c.CleanEvict_mshr_misses::total 53917 # number of CleanEvict MSHR misses 3585system.l2c.UpgradeReq_mshr_misses::cpu0.data 62895 # number of UpgradeReq MSHR misses 3586system.l2c.UpgradeReq_mshr_misses::cpu1.data 64271 # number of UpgradeReq MSHR misses 3587system.l2c.UpgradeReq_mshr_misses::total 127166 # number of UpgradeReq MSHR misses 3588system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12027 # number of SCUpgradeReq MSHR misses 3589system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12595 # number of SCUpgradeReq MSHR misses 3590system.l2c.SCUpgradeReq_mshr_misses::total 24622 # number of SCUpgradeReq MSHR misses 3591system.l2c.ReadExReq_mshr_misses::cpu0.data 80267 # number of ReadExReq MSHR misses 3592system.l2c.ReadExReq_mshr_misses::cpu1.data 60030 # number of ReadExReq MSHR misses 3593system.l2c.ReadExReq_mshr_misses::total 140297 # number of ReadExReq MSHR misses 3594system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1639 # number of ReadSharedReq MSHR misses 3595system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1057 # number of ReadSharedReq MSHR misses 3596system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 49655 # number of ReadSharedReq MSHR misses 3597system.l2c.ReadSharedReq_mshr_misses::cpu0.data 124186 # number of ReadSharedReq MSHR misses 3598system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 228039 # number of ReadSharedReq MSHR misses 3599system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3279 # number of ReadSharedReq MSHR misses 3600system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 3223 # number of ReadSharedReq MSHR misses 3601system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 53276 # number of ReadSharedReq MSHR misses 3602system.l2c.ReadSharedReq_mshr_misses::cpu1.data 140645 # number of ReadSharedReq MSHR misses 3603system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 285232 # number of ReadSharedReq MSHR misses 3604system.l2c.ReadSharedReq_mshr_misses::total 890231 # number of ReadSharedReq MSHR misses 3605system.l2c.InvalidateReq_mshr_misses::cpu0.data 448396 # number of InvalidateReq MSHR misses 3606system.l2c.InvalidateReq_mshr_misses::cpu1.data 141685 # number of InvalidateReq MSHR misses 3607system.l2c.InvalidateReq_mshr_misses::total 590081 # number of InvalidateReq MSHR misses 3608system.l2c.demand_mshr_misses::cpu0.dtb.walker 1639 # number of demand (read+write) MSHR misses 3609system.l2c.demand_mshr_misses::cpu0.itb.walker 1057 # number of demand (read+write) MSHR misses 3610system.l2c.demand_mshr_misses::cpu0.inst 49655 # number of demand (read+write) MSHR misses 3611system.l2c.demand_mshr_misses::cpu0.data 204453 # number of demand (read+write) MSHR misses 3612system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 228039 # number of demand (read+write) MSHR misses 3613system.l2c.demand_mshr_misses::cpu1.dtb.walker 3279 # number of demand (read+write) MSHR misses 3614system.l2c.demand_mshr_misses::cpu1.itb.walker 3223 # number of demand (read+write) MSHR misses 3615system.l2c.demand_mshr_misses::cpu1.inst 53276 # number of demand (read+write) MSHR misses 3616system.l2c.demand_mshr_misses::cpu1.data 200675 # number of demand (read+write) MSHR misses 3617system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 285232 # number of demand (read+write) MSHR misses 3618system.l2c.demand_mshr_misses::total 1030528 # number of demand (read+write) MSHR misses 3619system.l2c.overall_mshr_misses::cpu0.dtb.walker 1639 # number of overall MSHR misses 3620system.l2c.overall_mshr_misses::cpu0.itb.walker 1057 # number of overall MSHR misses 3621system.l2c.overall_mshr_misses::cpu0.inst 49655 # number of overall MSHR misses 3622system.l2c.overall_mshr_misses::cpu0.data 204453 # number of overall MSHR misses 3623system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 228039 # number of overall MSHR misses 3624system.l2c.overall_mshr_misses::cpu1.dtb.walker 3279 # number of overall MSHR misses 3625system.l2c.overall_mshr_misses::cpu1.itb.walker 3223 # number of overall MSHR misses 3626system.l2c.overall_mshr_misses::cpu1.inst 53276 # number of overall MSHR misses 3627system.l2c.overall_mshr_misses::cpu1.data 200675 # number of overall MSHR misses 3628system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 285232 # number of overall MSHR misses 3629system.l2c.overall_mshr_misses::total 1030528 # number of overall MSHR misses 3630system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 3631system.l2c.ReadReq_mshr_uncacheable::cpu0.data 19295 # number of ReadReq MSHR uncacheable 3632system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 3633system.l2c.ReadReq_mshr_uncacheable::cpu1.data 19230 # number of ReadReq MSHR uncacheable 3634system.l2c.ReadReq_mshr_uncacheable::total 59885 # number of ReadReq MSHR uncacheable 3635system.l2c.WriteReq_mshr_uncacheable::cpu0.data 20724 # number of WriteReq MSHR uncacheable 3636system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17726 # number of WriteReq MSHR uncacheable 3637system.l2c.WriteReq_mshr_uncacheable::total 38450 # number of WriteReq MSHR uncacheable 3638system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 3639system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40019 # number of overall MSHR uncacheable misses 3640system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 3641system.l2c.overall_mshr_uncacheable_misses::cpu1.data 36956 # number of overall MSHR uncacheable misses 3642system.l2c.overall_mshr_uncacheable_misses::total 98335 # number of overall MSHR uncacheable misses 3643system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4446225996 # number of UpgradeReq MSHR miss cycles 3644system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4534639994 # number of UpgradeReq MSHR miss cycles 3645system.l2c.UpgradeReq_mshr_miss_latency::total 8980865990 # number of UpgradeReq MSHR miss cycles 3646system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 886749499 # number of SCUpgradeReq MSHR miss cycles 3647system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 926414497 # number of SCUpgradeReq MSHR miss cycles 3648system.l2c.SCUpgradeReq_mshr_miss_latency::total 1813163996 # number of SCUpgradeReq MSHR miss cycles 3649system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10464275798 # number of ReadExReq MSHR miss cycles 3650system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7840878904 # number of ReadExReq MSHR miss cycles 3651system.l2c.ReadExReq_mshr_miss_latency::total 18305154702 # number of ReadExReq MSHR miss cycles 3652system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 223351517 # number of ReadSharedReq MSHR miss cycles 3653system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 145414512 # number of ReadSharedReq MSHR miss cycles 3654system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6337103575 # number of ReadSharedReq MSHR miss cycles 3655system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 16614995089 # number of ReadSharedReq MSHR miss cycles 3656system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 40393654484 # number of ReadSharedReq MSHR miss cycles 3657system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 431629523 # number of ReadSharedReq MSHR miss cycles 3658system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 422863011 # number of ReadSharedReq MSHR miss cycles 3659system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6817728943 # number of ReadSharedReq MSHR miss cycles 3660system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 19190174661 # number of ReadSharedReq MSHR miss cycles 3661system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 49807612610 # number of ReadSharedReq MSHR miss cycles 3662system.l2c.ReadSharedReq_mshr_miss_latency::total 140384527925 # number of ReadSharedReq MSHR miss cycles 3663system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 31537249501 # number of InvalidateReq MSHR miss cycles 3664system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 9872026491 # number of InvalidateReq MSHR miss cycles 3665system.l2c.InvalidateReq_mshr_miss_latency::total 41409275992 # number of InvalidateReq MSHR miss cycles 3666system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 223351517 # number of demand (read+write) MSHR miss cycles 3667system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145414512 # number of demand (read+write) MSHR miss cycles 3668system.l2c.demand_mshr_miss_latency::cpu0.inst 6337103575 # number of demand (read+write) MSHR miss cycles 3669system.l2c.demand_mshr_miss_latency::cpu0.data 27079270887 # number of demand (read+write) MSHR miss cycles 3670system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 40393654484 # number of demand (read+write) MSHR miss cycles 3671system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 431629523 # number of demand (read+write) MSHR miss cycles 3672system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 422863011 # number of demand (read+write) MSHR miss cycles 3673system.l2c.demand_mshr_miss_latency::cpu1.inst 6817728943 # number of demand (read+write) MSHR miss cycles 3674system.l2c.demand_mshr_miss_latency::cpu1.data 27031053565 # number of demand (read+write) MSHR miss cycles 3675system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 49807612610 # number of demand (read+write) MSHR miss cycles 3676system.l2c.demand_mshr_miss_latency::total 158689682627 # number of demand (read+write) MSHR miss cycles 3677system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 223351517 # number of overall MSHR miss cycles 3678system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145414512 # number of overall MSHR miss cycles 3679system.l2c.overall_mshr_miss_latency::cpu0.inst 6337103575 # number of overall MSHR miss cycles 3680system.l2c.overall_mshr_miss_latency::cpu0.data 27079270887 # number of overall MSHR miss cycles 3681system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 40393654484 # number of overall MSHR miss cycles 3682system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 431629523 # number of overall MSHR miss cycles 3683system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 422863011 # number of overall MSHR miss cycles 3684system.l2c.overall_mshr_miss_latency::cpu1.inst 6817728943 # number of overall MSHR miss cycles 3685system.l2c.overall_mshr_miss_latency::cpu1.data 27031053565 # number of overall MSHR miss cycles 3686system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 49807612610 # number of overall MSHR miss cycles 3687system.l2c.overall_mshr_miss_latency::total 158689682627 # number of overall MSHR miss cycles 3688system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396807500 # number of ReadReq MSHR uncacheable cycles 3689system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3287554526 # number of ReadReq MSHR uncacheable cycles 3690system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7444500 # number of ReadReq MSHR uncacheable cycles 3691system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2618864514 # number of ReadReq MSHR uncacheable cycles 3692system.l2c.ReadReq_mshr_uncacheable_latency::total 8310671040 # number of ReadReq MSHR uncacheable cycles 3693system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3427997062 # number of WriteReq MSHR uncacheable cycles 3694system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2536356535 # number of WriteReq MSHR uncacheable cycles 3695system.l2c.WriteReq_mshr_uncacheable_latency::total 5964353597 # number of WriteReq MSHR uncacheable cycles 3696system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396807500 # number of overall MSHR uncacheable cycles 3697system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6715551588 # number of overall MSHR uncacheable cycles 3698system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7444500 # number of overall MSHR uncacheable cycles 3699system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5155221049 # number of overall MSHR uncacheable cycles 3700system.l2c.overall_mshr_uncacheable_latency::total 14275024637 # number of overall MSHR uncacheable cycles 3701system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3702system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3703system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.261811 # mshr miss rate for UpgradeReq accesses 3704system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.326858 # mshr miss rate for UpgradeReq accesses 3705system.l2c.UpgradeReq_mshr_miss_rate::total 0.291088 # mshr miss rate for UpgradeReq accesses 3706system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.238262 # mshr miss rate for SCUpgradeReq accesses 3707system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.228100 # mshr miss rate for SCUpgradeReq accesses 3708system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.232953 # mshr miss rate for SCUpgradeReq accesses 3709system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.605095 # mshr miss rate for ReadExReq accesses 3710system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.527787 # mshr miss rate for ReadExReq accesses 3711system.l2c.ReadExReq_mshr_miss_rate::total 0.569408 # mshr miss rate for ReadExReq accesses 3712system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.204288 # mshr miss rate for ReadSharedReq accesses 3713system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.198311 # mshr miss rate for ReadSharedReq accesses 3714system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.090382 # mshr miss rate for ReadSharedReq accesses 3715system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.169426 # mshr miss rate for ReadSharedReq accesses 3716system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.422900 # mshr miss rate for ReadSharedReq accesses 3717system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.326724 # mshr miss rate for ReadSharedReq accesses 3718system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.415656 # mshr miss rate for ReadSharedReq accesses 3719system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.090274 # mshr miss rate for ReadSharedReq accesses 3720system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.194107 # mshr miss rate for ReadSharedReq accesses 3721system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.493417 # mshr miss rate for ReadSharedReq accesses 3722system.l2c.ReadSharedReq_mshr_miss_rate::total 0.237677 # mshr miss rate for ReadSharedReq accesses 3723system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.771406 # mshr miss rate for InvalidateReq accesses 3724system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.527016 # mshr miss rate for InvalidateReq accesses 3725system.l2c.InvalidateReq_mshr_miss_rate::total 0.694119 # mshr miss rate for InvalidateReq accesses 3726system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.204288 # mshr miss rate for demand accesses 3727system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.198311 # mshr miss rate for demand accesses 3728system.l2c.demand_mshr_miss_rate::cpu0.inst 0.090382 # mshr miss rate for demand accesses 3729system.l2c.demand_mshr_miss_rate::cpu0.data 0.236190 # mshr miss rate for demand accesses 3730system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.422900 # mshr miss rate for demand accesses 3731system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.326724 # mshr miss rate for demand accesses 3732system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.415656 # mshr miss rate for demand accesses 3733system.l2c.demand_mshr_miss_rate::cpu1.inst 0.090274 # mshr miss rate for demand accesses 3734system.l2c.demand_mshr_miss_rate::cpu1.data 0.239379 # mshr miss rate for demand accesses 3735system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.493417 # mshr miss rate for demand accesses 3736system.l2c.demand_mshr_miss_rate::total 0.258152 # mshr miss rate for demand accesses 3737system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.204288 # mshr miss rate for overall accesses 3738system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.198311 # mshr miss rate for overall accesses 3739system.l2c.overall_mshr_miss_rate::cpu0.inst 0.090382 # mshr miss rate for overall accesses 3740system.l2c.overall_mshr_miss_rate::cpu0.data 0.236190 # mshr miss rate for overall accesses 3741system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.422900 # mshr miss rate for overall accesses 3742system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.326724 # mshr miss rate for overall accesses 3743system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.415656 # mshr miss rate for overall accesses 3744system.l2c.overall_mshr_miss_rate::cpu1.inst 0.090274 # mshr miss rate for overall accesses 3745system.l2c.overall_mshr_miss_rate::cpu1.data 0.239379 # mshr miss rate for overall accesses 3746system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.493417 # mshr miss rate for overall accesses 3747system.l2c.overall_mshr_miss_rate::total 0.258152 # mshr miss rate for overall accesses 3748system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70692.837205 # average UpgradeReq mshr miss latency 3749system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70554.993605 # average UpgradeReq mshr miss latency 3750system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70623.169637 # average UpgradeReq mshr miss latency 3751system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73729.899310 # average SCUpgradeReq mshr miss latency 3752system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.148233 # average SCUpgradeReq mshr miss latency 3753system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73639.996588 # average SCUpgradeReq mshr miss latency 3754system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 130368.343130 # average ReadExReq mshr miss latency 3755system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 130616.007063 # average ReadExReq mshr miss latency 3756system.l2c.ReadExReq_avg_mshr_miss_latency::total 130474.313079 # average ReadExReq mshr miss latency 3757system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709 # average ReadSharedReq mshr miss latency 3758system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035 # average ReadSharedReq mshr miss latency 3759system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127622.667909 # average ReadSharedReq mshr miss latency 3760system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 133791.209065 # average ReadSharedReq mshr miss latency 3761system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863 # average ReadSharedReq mshr miss latency 3762system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238 # average ReadSharedReq mshr miss latency 3763system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871 # average ReadSharedReq mshr miss latency 3764system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127969.985416 # average ReadSharedReq mshr miss latency 3765system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136444.058879 # average ReadSharedReq mshr miss latency 3766system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067 # average ReadSharedReq mshr miss latency 3767system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157694.494940 # average ReadSharedReq mshr miss latency 3768system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70333.476438 # average InvalidateReq mshr miss latency 3769system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69675.876000 # average InvalidateReq mshr miss latency 3770system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70175.579271 # average InvalidateReq mshr miss latency 3771system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709 # average overall mshr miss latency 3772system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035 # average overall mshr miss latency 3773system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127622.667909 # average overall mshr miss latency 3774system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132447.412789 # average overall mshr miss latency 3775system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863 # average overall mshr miss latency 3776system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238 # average overall mshr miss latency 3777system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871 # average overall mshr miss latency 3778system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127969.985416 # average overall mshr miss latency 3779system.l2c.demand_avg_mshr_miss_latency::cpu1.data 134700.653121 # average overall mshr miss latency 3780system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067 # average overall mshr miss latency 3781system.l2c.demand_avg_mshr_miss_latency::total 153988.715131 # average overall mshr miss latency 3782system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709 # average overall mshr miss latency 3783system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035 # average overall mshr miss latency 3784system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127622.667909 # average overall mshr miss latency 3785system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132447.412789 # average overall mshr miss latency 3786system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863 # average overall mshr miss latency 3787system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238 # average overall mshr miss latency 3788system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871 # average overall mshr miss latency 3789system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127969.985416 # average overall mshr miss latency 3790system.l2c.overall_avg_mshr_miss_latency::cpu1.data 134700.653121 # average overall mshr miss latency 3791system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067 # average overall mshr miss latency 3792system.l2c.overall_avg_mshr_miss_latency::total 153988.715131 # average overall mshr miss latency 3793system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average ReadReq mshr uncacheable latency 3794system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170383.753615 # average ReadReq mshr uncacheable latency 3795system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299 # average ReadReq mshr uncacheable latency 3796system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136186.402184 # average ReadReq mshr uncacheable latency 3797system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138777.173583 # average ReadReq mshr uncacheable latency 3798system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165411.940842 # average WriteReq mshr uncacheable latency 3799system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143086.795385 # average WriteReq mshr uncacheable latency 3800system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155119.729441 # average WriteReq mshr uncacheable latency 3801system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average overall mshr uncacheable latency 3802system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167809.080387 # average overall mshr uncacheable latency 3803system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299 # average overall mshr uncacheable latency 3804system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 139496.185978 # average overall mshr uncacheable latency 3805system.l2c.overall_avg_mshr_uncacheable_latency::total 145167.281609 # average overall mshr uncacheable latency 3806system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3807system.membus.trans_dist::ReadReq 59885 # Transaction distribution 3808system.membus.trans_dist::ReadResp 959045 # Transaction distribution 3809system.membus.trans_dist::WriteReq 38450 # Transaction distribution 3810system.membus.trans_dist::WriteResp 38450 # Transaction distribution 3811system.membus.trans_dist::WritebackDirty 1308388 # Transaction distribution 3812system.membus.trans_dist::CleanEvict 245549 # Transaction distribution 3813system.membus.trans_dist::UpgradeReq 443766 # Transaction distribution 3814system.membus.trans_dist::SCUpgradeReq 303375 # Transaction distribution 3815system.membus.trans_dist::UpgradeResp 24 # Transaction distribution 3816system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3817system.membus.trans_dist::ReadExReq 149775 # Transaction distribution 3818system.membus.trans_dist::ReadExResp 134703 # Transaction distribution 3819system.membus.trans_dist::ReadSharedReq 899160 # Transaction distribution 3820system.membus.trans_dist::InvalidateReq 692677 # Transaction distribution 3821system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122588 # Packet count per connected master and slave (bytes) 3822system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3823system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26142 # Packet count per connected master and slave (bytes) 3824system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4883481 # Packet count per connected master and slave (bytes) 3825system.membus.pkt_count_system.l2c.mem_side::total 5032287 # Packet count per connected master and slave (bytes) 3826system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238261 # Packet count per connected master and slave (bytes) 3827system.membus.pkt_count_system.iocache.mem_side::total 238261 # Packet count per connected master and slave (bytes) 3828system.membus.pkt_count::total 5270548 # Packet count per connected master and slave (bytes) 3829system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155695 # Cumulative packet size per connected master and slave (bytes) 3830system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3831system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52284 # Cumulative packet size per connected master and slave (bytes) 3832system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142819456 # Cumulative packet size per connected master and slave (bytes) 3833system.membus.pkt_size_system.l2c.mem_side::total 143027991 # Cumulative packet size per connected master and slave (bytes) 3834system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7275456 # Cumulative packet size per connected master and slave (bytes) 3835system.membus.pkt_size_system.iocache.mem_side::total 7275456 # Cumulative packet size per connected master and slave (bytes) 3836system.membus.pkt_size::total 150303447 # Cumulative packet size per connected master and slave (bytes) 3837system.membus.snoops 603397 # Total snoops (count) 3838system.membus.snoop_fanout::samples 4141095 # Request fanout histogram 3839system.membus.snoop_fanout::mean 1 # Request fanout histogram 3840system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3841system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3842system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3843system.membus.snoop_fanout::1 4141095 100.00% 100.00% # Request fanout histogram 3844system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3845system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3846system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3847system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3848system.membus.snoop_fanout::total 4141095 # Request fanout histogram 3849system.membus.reqLayer0.occupancy 97863497 # Layer occupancy (ticks) 3850system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3851system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3852system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3853system.membus.reqLayer2.occupancy 22133983 # Layer occupancy (ticks) 3854system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3855system.membus.reqLayer5.occupancy 9091243819 # Layer occupancy (ticks) 3856system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3857system.membus.respLayer2.occupancy 5543319054 # Layer occupancy (ticks) 3858system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3859system.membus.respLayer3.occupancy 45567476 # Layer occupancy (ticks) 3860system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3861system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3862system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3863system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3864system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3865system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3866system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3867system.realview.ethernet.txBytes 966 # Bytes Transmitted 3868system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3869system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3870system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3871system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3872system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3873system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3874system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3875system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3876system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3877system.realview.ethernet.totPackets 3 # Total Packets 3878system.realview.ethernet.totBytes 966 # Total Bytes 3879system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3880system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3881system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3882system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3883system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3884system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3885system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3886system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3887system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3888system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3889system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3890system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3891system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3892system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3893system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3894system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3895system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3896system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3897system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3898system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3899system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3900system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3901system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3902system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3903system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3904system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3905system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3906system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3907system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3908system.realview.ethernet.droppedPackets 0 # number of packets dropped 3909system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3910system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3911system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3912system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3913system.toL2Bus.snoop_filter.tot_requests 12058125 # Total number of requests made to the snoop filter. 3914system.toL2Bus.snoop_filter.hit_single_requests 6550145 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3915system.toL2Bus.snoop_filter.hit_multi_requests 1934123 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3916system.toL2Bus.snoop_filter.tot_snoops 145409 # Total number of snoops made to the snoop filter. 3917system.toL2Bus.snoop_filter.hit_single_snoops 132628 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3918system.toL2Bus.snoop_filter.hit_multi_snoops 12781 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3919system.toL2Bus.trans_dist::ReadReq 59887 # Transaction distribution 3920system.toL2Bus.trans_dist::ReadResp 4587364 # Transaction distribution 3921system.toL2Bus.trans_dist::WriteReq 38450 # Transaction distribution 3922system.toL2Bus.trans_dist::WriteResp 38450 # Transaction distribution 3923system.toL2Bus.trans_dist::WritebackDirty 4172911 # Transaction distribution 3924system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution 3925system.toL2Bus.trans_dist::CleanEvict 2698369 # Transaction distribution 3926system.toL2Bus.trans_dist::UpgradeReq 743738 # Transaction distribution 3927system.toL2Bus.trans_dist::SCUpgradeReq 384448 # Transaction distribution 3928system.toL2Bus.trans_dist::UpgradeResp 1128186 # Transaction distribution 3929system.toL2Bus.trans_dist::SCUpgradeFailReq 137 # Transaction distribution 3930system.toL2Bus.trans_dist::UpgradeFailResp 137 # Transaction distribution 3931system.toL2Bus.trans_dist::ReadExReq 300120 # Transaction distribution 3932system.toL2Bus.trans_dist::ReadExResp 300120 # Transaction distribution 3933system.toL2Bus.trans_dist::ReadSharedReq 4534724 # Transaction distribution 3934system.toL2Bus.trans_dist::InvalidateReq 956843 # Transaction distribution 3935system.toL2Bus.trans_dist::InvalidateResp 850115 # Transaction distribution 3936system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9259077 # Packet count per connected master and slave (bytes) 3937system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8380798 # Packet count per connected master and slave (bytes) 3938system.toL2Bus.pkt_count::total 17639875 # Packet count per connected master and slave (bytes) 3939system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229804683 # Cumulative packet size per connected master and slave (bytes) 3940system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 209683148 # Cumulative packet size per connected master and slave (bytes) 3941system.toL2Bus.pkt_size::total 439487831 # Cumulative packet size per connected master and slave (bytes) 3942system.toL2Bus.snoops 3155812 # Total snoops (count) 3943system.toL2Bus.snoop_fanout::samples 8637402 # Request fanout histogram 3944system.toL2Bus.snoop_fanout::mean 0.346247 # Request fanout histogram 3945system.toL2Bus.snoop_fanout::stdev 0.478873 # Request fanout histogram 3946system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3947system.toL2Bus.snoop_fanout::0 5659510 65.52% 65.52% # Request fanout histogram 3948system.toL2Bus.snoop_fanout::1 2965111 34.33% 99.85% # Request fanout histogram 3949system.toL2Bus.snoop_fanout::2 12781 0.15% 100.00% # Request fanout histogram 3950system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3951system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3952system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3953system.toL2Bus.snoop_fanout::total 8637402 # Request fanout histogram 3954system.toL2Bus.reqLayer0.occupancy 9396796139 # Layer occupancy (ticks) 3955system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3956system.toL2Bus.snoopLayer0.occupancy 2598429 # Layer occupancy (ticks) 3957system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3958system.toL2Bus.respLayer0.occupancy 4205091357 # Layer occupancy (ticks) 3959system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3960system.toL2Bus.respLayer1.occupancy 4119595686 # Layer occupancy (ticks) 3961system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3962system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3963system.cpu0.kern.inst.quiesce 5119 # number of quiesce instructions executed 3964system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3965system.cpu1.kern.inst.quiesce 13991 # number of quiesce instructions executed 3966 3967---------- End Simulation Statistics ---------- 3968