stats.txt revision 11680:b4d943429dc6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.688775 # Number of seconds simulated 4sim_ticks 51688774990000 # Number of ticks simulated 5final_tick 51688774990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 210815 # Simulator instruction rate (inst/s) 8host_op_rate 247704 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11507504763 # Simulator tick rate (ticks/s) 10host_mem_usage 684036 # Number of bytes of host memory used 11host_seconds 4491.74 # Real time elapsed on the host 12sim_insts 946928269 # Number of instructions simulated 13sim_ops 1112623169 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 401472 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 331520 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10196544 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 65400968 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 425152 # Number of bytes read from this memory 22system.physmem.bytes_read::total 76755656 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 10196544 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 10196544 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 93615936 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 93636516 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 6273 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5180 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 159321 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1021903 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6643 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1199320 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1462749 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 1465322 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 7767 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 6414 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 197268 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1265284 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 8225 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1484958 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 197268 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 197268 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1811146 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1811544 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1811146 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 7767 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 6414 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 197268 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1265682 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 8225 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3296502 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 1199320 # Number of read requests accepted 56system.physmem.writeReqs 1465322 # Number of write requests accepted 57system.physmem.readBursts 1199320 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1465322 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 76712512 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 43968 # Total number of bytes read from write queue 61system.physmem.bytesWritten 93634496 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 76755656 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 93636516 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 687 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 70144 # Per bank write bursts 68system.physmem.perBankRdBursts::1 74650 # Per bank write bursts 69system.physmem.perBankRdBursts::2 68418 # Per bank write bursts 70system.physmem.perBankRdBursts::3 68145 # Per bank write bursts 71system.physmem.perBankRdBursts::4 72367 # Per bank write bursts 72system.physmem.perBankRdBursts::5 76479 # Per bank write bursts 73system.physmem.perBankRdBursts::6 68140 # Per bank write bursts 74system.physmem.perBankRdBursts::7 71247 # Per bank write bursts 75system.physmem.perBankRdBursts::8 66581 # Per bank write bursts 76system.physmem.perBankRdBursts::9 125666 # Per bank write bursts 77system.physmem.perBankRdBursts::10 74635 # Per bank write bursts 78system.physmem.perBankRdBursts::11 76739 # Per bank write bursts 79system.physmem.perBankRdBursts::12 72169 # Per bank write bursts 80system.physmem.perBankRdBursts::13 75530 # Per bank write bursts 81system.physmem.perBankRdBursts::14 66172 # Per bank write bursts 82system.physmem.perBankRdBursts::15 71551 # Per bank write bursts 83system.physmem.perBankWrBursts::0 89120 # Per bank write bursts 84system.physmem.perBankWrBursts::1 91694 # Per bank write bursts 85system.physmem.perBankWrBursts::2 88427 # Per bank write bursts 86system.physmem.perBankWrBursts::3 87889 # Per bank write bursts 87system.physmem.perBankWrBursts::4 92386 # Per bank write bursts 88system.physmem.perBankWrBursts::5 94711 # Per bank write bursts 89system.physmem.perBankWrBursts::6 88472 # Per bank write bursts 90system.physmem.perBankWrBursts::7 91239 # Per bank write bursts 91system.physmem.perBankWrBursts::8 88274 # Per bank write bursts 92system.physmem.perBankWrBursts::9 94990 # Per bank write bursts 93system.physmem.perBankWrBursts::10 92874 # Per bank write bursts 94system.physmem.perBankWrBursts::11 94799 # Per bank write bursts 95system.physmem.perBankWrBursts::12 93039 # Per bank write bursts 96system.physmem.perBankWrBursts::13 95949 # Per bank write bursts 97system.physmem.perBankWrBursts::14 87664 # Per bank write bursts 98system.physmem.perBankWrBursts::15 91512 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 468 # Number of times write queue was full causing retry 101system.physmem.totGap 51688773130000 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 0 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 1199305 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 1462749 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 1127245 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 64919 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 779 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 491 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 476 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 609 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 509 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1056 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 628 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 296 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 301 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 207 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 165 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 29655 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 37473 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 78822 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 84952 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 87044 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 83743 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 88388 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 87662 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 88784 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 85626 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 88571 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 89853 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 87229 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 84323 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 82904 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 81964 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 79861 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 79771 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2782 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 2400 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 2080 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 1918 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 1552 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 1400 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 1354 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 1254 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 1171 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 1114 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 996 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 968 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 849 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 803 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 723 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 703 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 853 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 763 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 689 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 985 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 920 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 1056 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 910 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 634 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 1027 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 1982 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 1362 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 537 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 1066 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 662940 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 256.956322 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 154.084684 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 293.850288 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 284383 42.90% 42.90% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 170705 25.75% 68.65% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 61081 9.21% 77.86% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 33561 5.06% 82.92% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 23575 3.56% 86.48% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 15515 2.34% 88.82% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 11286 1.70% 90.52% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 9362 1.41% 91.93% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 53472 8.07% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 662940 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 77129 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 15.540445 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 141.912078 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 77126 100.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 77129 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 77129 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 18.968728 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 18.139558 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 8.416384 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-19 64621 83.78% 83.78% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20-23 3761 4.88% 88.66% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::24-27 3195 4.14% 92.80% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28-31 2420 3.14% 95.94% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32-35 1145 1.48% 97.42% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36-39 346 0.45% 97.87% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-43 199 0.26% 98.13% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::44-47 173 0.22% 98.35% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::48-51 112 0.15% 98.50% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52-55 62 0.08% 98.58% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::56-59 79 0.10% 98.68% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::60-63 69 0.09% 98.77% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::64-67 561 0.73% 99.50% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::68-71 77 0.10% 99.60% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::72-75 111 0.14% 99.74% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::76-79 54 0.07% 99.81% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::80-83 32 0.04% 99.85% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::84-87 4 0.01% 99.86% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 3 0.00% 99.86% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 3 0.00% 99.87% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::96-99 2 0.00% 99.87% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::100-103 2 0.00% 99.87% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::104-107 3 0.00% 99.88% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::108-111 13 0.02% 99.89% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::112-115 7 0.01% 99.90% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::116-119 2 0.00% 99.91% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::128-131 17 0.02% 99.93% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::132-135 5 0.01% 99.94% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::136-139 4 0.01% 99.94% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::140-143 12 0.02% 99.96% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::144-147 5 0.01% 99.97% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::168-171 1 0.00% 99.97% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::188-191 3 0.00% 99.98% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::192-195 12 0.02% 100.00% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::total 77129 # Writes before turning the bus around for reads 280system.physmem.totQLat 38956691672 # Total ticks spent queuing 281system.physmem.totMemAccLat 61431060422 # Total ticks spent from burst creation until serviced by the DRAM 282system.physmem.totBusLat 5993165000 # Total ticks spent in databus transfers 283system.physmem.avgQLat 32500.93 # Average queueing delay per DRAM burst 284system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 285system.physmem.avgMemAccLat 51250.93 # Average memory access latency per DRAM burst 286system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s 287system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s 288system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s 289system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s 290system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 291system.physmem.busUtil 0.03 # Data bus utilization in percentage 292system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 293system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 294system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 295system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing 296system.physmem.readRowHits 929087 # Number of row buffer hits during reads 297system.physmem.writeRowHits 1069644 # Number of row buffer hits during writes 298system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads 299system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes 300system.physmem.avgGap 19398017.87 # Average gap between requests 301system.physmem.pageHitRate 75.09 # Row buffer hit rate, read and write combined 302system.physmem_0.actEnergy 2341677240 # Energy for activate commands per rank (pJ) 303system.physmem_0.preEnergy 1244627175 # Energy for precharge commands per rank (pJ) 304system.physmem_0.readEnergy 4066872600 # Energy for read commands per rank (pJ) 305system.physmem_0.writeEnergy 3778956360 # Energy for write commands per rank (pJ) 306system.physmem_0.refreshEnergy 50725624560.000008 # Energy for refresh commands per rank (pJ) 307system.physmem_0.actBackEnergy 43528474080 # Energy for active background per rank (pJ) 308system.physmem_0.preBackEnergy 3238135680 # Energy for precharge background per rank (pJ) 309system.physmem_0.actPowerDownEnergy 96319832910 # Energy for active power-down per rank (pJ) 310system.physmem_0.prePowerDownEnergy 74142648000 # Energy for precharge power-down per rank (pJ) 311system.physmem_0.selfRefreshEnergy 12293580495315 # Energy for self refresh per rank (pJ) 312system.physmem_0.totalEnergy 12572988857670 # Total energy per rank (pJ) 313system.physmem_0.averagePower 243.244086 # Core power per rank (mW) 314system.physmem_0.totalIdleTime 51584838283234 # Total Idle time Per DRAM Rank 315system.physmem_0.memoryStateTime::IDLE 6009063000 # Time in different power states 316system.physmem_0.memoryStateTime::REF 21570724000 # Time in different power states 317system.physmem_0.memoryStateTime::SREF 51180529926500 # Time in different power states 318system.physmem_0.memoryStateTime::PRE_PDN 193079953190 # Time in different power states 319system.physmem_0.memoryStateTime::ACT 76356875016 # Time in different power states 320system.physmem_0.memoryStateTime::ACT_PDN 211228448294 # Time in different power states 321system.physmem_1.actEnergy 2391721500 # Energy for activate commands per rank (pJ) 322system.physmem_1.preEnergy 1271230125 # Energy for precharge commands per rank (pJ) 323system.physmem_1.readEnergy 4491367020 # Energy for read commands per rank (pJ) 324system.physmem_1.writeEnergy 3858107220 # Energy for write commands per rank (pJ) 325system.physmem_1.refreshEnergy 51763751520.000015 # Energy for refresh commands per rank (pJ) 326system.physmem_1.actBackEnergy 44789626440 # Energy for active background per rank (pJ) 327system.physmem_1.preBackEnergy 3183541920 # Energy for precharge background per rank (pJ) 328system.physmem_1.actPowerDownEnergy 99591324540 # Energy for active power-down per rank (pJ) 329system.physmem_1.prePowerDownEnergy 75005755680 # Energy for precharge power-down per rank (pJ) 330system.physmem_1.selfRefreshEnergy 12290774240265 # Energy for self refresh per rank (pJ) 331system.physmem_1.totalEnergy 12577142748300 # Total energy per rank (pJ) 332system.physmem_1.averagePower 243.324450 # Core power per rank (mW) 333system.physmem_1.totalIdleTime 51582206485554 # Total Idle time Per DRAM Rank 334system.physmem_1.memoryStateTime::IDLE 5783812250 # Time in different power states 335system.physmem_1.memoryStateTime::REF 22010710000 # Time in different power states 336system.physmem_1.memoryStateTime::SREF 51168482999000 # Time in different power states 337system.physmem_1.memoryStateTime::PRE_PDN 195327455894 # Time in different power states 338system.physmem_1.memoryStateTime::ACT 78768252696 # Time in different power states 339system.physmem_1.memoryStateTime::ACT_PDN 218401760160 # Time in different power states 340system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 341system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 346system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 347system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 349system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 357system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 358system.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 359system.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 360system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 361system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 362system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 363system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 364system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 365system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 366system.cpu.branchPred.lookups 261505306 # Number of BP lookups 367system.cpu.branchPred.condPredicted 182498706 # Number of conditional branches predicted 368system.cpu.branchPred.condIncorrect 12291836 # Number of conditional branches incorrect 369system.cpu.branchPred.BTBLookups 192874347 # Number of BTB lookups 370system.cpu.branchPred.BTBHits 130159045 # Number of BTB hits 371system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 372system.cpu.branchPred.BTBHitPct 67.483855 # BTB Hit Percentage 373system.cpu.branchPred.usedRAS 31722667 # Number of times the RAS was used to get a target. 374system.cpu.branchPred.RASInCorrect 2144910 # Number of incorrect RAS predictions. 375system.cpu.branchPred.indirectLookups 7175659 # Number of indirect predictor lookups. 376system.cpu.branchPred.indirectHits 5109497 # Number of indirect target hits. 377system.cpu.branchPred.indirectMisses 2066162 # Number of indirect misses. 378system.cpu.branchPredindirectMispredicted 844099 # Number of mispredicted indirect branches. 379system.cpu_clk_domain.clock 500 # Clock period in ticks 380system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 381system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 382system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 383system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 385system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 386system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 388system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 389system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 390system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 391system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 392system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 393system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 394system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 395system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 396system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 397system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 398system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 399system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 400system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 401system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 402system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 403system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 404system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 405system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 406system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 407system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 408system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 409system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 410system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 411system.cpu.dtb.walker.walks 574319 # Table walker walks requested 412system.cpu.dtb.walker.walksLong 574319 # Table walker walks initiated with long descriptors 413system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21733 # Level at which table walker walks with long descriptors terminate 414system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190269 # Level at which table walker walks with long descriptors terminate 415system.cpu.dtb.walker.walkWaitTime::samples 574319 # Table walker wait (enqueue to first request) latency 416system.cpu.dtb.walker.walkWaitTime::0 574319 100.00% 100.00% # Table walker wait (enqueue to first request) latency 417system.cpu.dtb.walker.walkWaitTime::total 574319 # Table walker wait (enqueue to first request) latency 418system.cpu.dtb.walker.walkCompletionTime::samples 212002 # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::mean 25745.962302 # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515 # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193 # Table walker service (enqueue to completion) latency 422system.cpu.dtb.walker.walkCompletionTime::0-65535 209468 98.80% 98.80% # Table walker service (enqueue to completion) latency 423system.cpu.dtb.walker.walkCompletionTime::65536-131071 2131 1.01% 99.81% # Table walker service (enqueue to completion) latency 424system.cpu.dtb.walker.walkCompletionTime::131072-196607 103 0.05% 99.86% # Table walker service (enqueue to completion) latency 425system.cpu.dtb.walker.walkCompletionTime::196608-262143 132 0.06% 99.92% # Table walker service (enqueue to completion) latency 426system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.96% # Table walker service (enqueue to completion) latency 427system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.98% # Table walker service (enqueue to completion) latency 428system.cpu.dtb.walker.walkCompletionTime::393216-458751 12 0.01% 99.98% # Table walker service (enqueue to completion) latency 429system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency 430system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 431system.cpu.dtb.walker.walkCompletionTime::589824-655359 29 0.01% 100.00% # Table walker service (enqueue to completion) latency 432system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 433system.cpu.dtb.walker.walkCompletionTime::total 212002 # Table walker service (enqueue to completion) latency 434system.cpu.dtb.walker.walksPending::samples 316311704 # Table walker pending requests distribution 435system.cpu.dtb.walker.walksPending::0 316311704 100.00% 100.00% # Table walker pending requests distribution 436system.cpu.dtb.walker.walksPending::total 316311704 # Table walker pending requests distribution 437system.cpu.dtb.walker.walkPageSizes::4K 190270 89.75% 89.75% # Table walker page sizes translated 438system.cpu.dtb.walker.walkPageSizes::2M 21733 10.25% 100.00% # Table walker page sizes translated 439system.cpu.dtb.walker.walkPageSizes::total 212003 # Table walker page sizes translated 440system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 574319 # Table walker requests started/completed, data/inst 441system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin_Requested::total 574319 # Table walker requests started/completed, data/inst 443system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 212003 # Table walker requests started/completed, data/inst 444system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.dtb.walker.walkRequestOrigin_Completed::total 212003 # Table walker requests started/completed, data/inst 446system.cpu.dtb.walker.walkRequestOrigin::total 786322 # Table walker requests started/completed, data/inst 447system.cpu.dtb.inst_hits 0 # ITB inst hits 448system.cpu.dtb.inst_misses 0 # ITB inst misses 449system.cpu.dtb.read_hits 182769858 # DTB read hits 450system.cpu.dtb.read_misses 473161 # DTB read misses 451system.cpu.dtb.write_hits 162201881 # DTB write hits 452system.cpu.dtb.write_misses 101158 # DTB write misses 453system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 454system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 455system.cpu.dtb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID 456system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID 457system.cpu.dtb.flush_entries 79796 # Number of entries that have been flushed from TLB 458system.cpu.dtb.align_faults 1477 # Number of TLB faults due to alignment restrictions 459system.cpu.dtb.prefetch_faults 15505 # Number of TLB faults due to prefetch 460system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 461system.cpu.dtb.perms_faults 23270 # Number of TLB faults due to permissions restrictions 462system.cpu.dtb.read_accesses 183243019 # DTB read accesses 463system.cpu.dtb.write_accesses 162303039 # DTB write accesses 464system.cpu.dtb.inst_accesses 0 # ITB inst accesses 465system.cpu.dtb.hits 344971739 # DTB hits 466system.cpu.dtb.misses 574319 # DTB misses 467system.cpu.dtb.accesses 345546058 # DTB accesses 468system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 469system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 473system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 474system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 475system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 476system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 477system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 478system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 479system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 480system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 481system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 482system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 483system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 484system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 485system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 486system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 487system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 488system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 489system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 490system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 491system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 492system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 493system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 494system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 495system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 496system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 497system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 498system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 499system.cpu.itb.walker.walks 135751 # Table walker walks requested 500system.cpu.itb.walker.walksLong 135751 # Table walker walks initiated with long descriptors 501system.cpu.itb.walker.walksLongTerminationLevel::Level2 1056 # Level at which table walker walks with long descriptors terminate 502system.cpu.itb.walker.walksLongTerminationLevel::Level3 117755 # Level at which table walker walks with long descriptors terminate 503system.cpu.itb.walker.walkWaitTime::samples 135751 # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::0 135751 100.00% 100.00% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::total 135751 # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkCompletionTime::samples 118811 # Table walker service (enqueue to completion) latency 507system.cpu.itb.walker.walkCompletionTime::mean 28810.606762 # Table walker service (enqueue to completion) latency 508system.cpu.itb.walker.walkCompletionTime::gmean 24143.293111 # Table walker service (enqueue to completion) latency 509system.cpu.itb.walker.walkCompletionTime::stdev 28291.561253 # Table walker service (enqueue to completion) latency 510system.cpu.itb.walker.walkCompletionTime::0-65535 115975 97.61% 97.61% # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walkCompletionTime::65536-131071 2399 2.02% 99.63% # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::131072-196607 123 0.10% 99.74% # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.82% # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::262144-327679 44 0.04% 99.86% # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.87% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.88% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.88% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.88% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::589824-655359 141 0.12% 100.00% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walkCompletionTime::total 118811 # Table walker service (enqueue to completion) latency 522system.cpu.itb.walker.walksPending::samples 315425204 # Table walker pending requests distribution 523system.cpu.itb.walker.walksPending::0 315425204 100.00% 100.00% # Table walker pending requests distribution 524system.cpu.itb.walker.walksPending::total 315425204 # Table walker pending requests distribution 525system.cpu.itb.walker.walkPageSizes::4K 117755 99.11% 99.11% # Table walker page sizes translated 526system.cpu.itb.walker.walkPageSizes::2M 1056 0.89% 100.00% # Table walker page sizes translated 527system.cpu.itb.walker.walkPageSizes::total 118811 # Table walker page sizes translated 528system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 529system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135751 # Table walker requests started/completed, data/inst 530system.cpu.itb.walker.walkRequestOrigin_Requested::total 135751 # Table walker requests started/completed, data/inst 531system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 532system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118811 # Table walker requests started/completed, data/inst 533system.cpu.itb.walker.walkRequestOrigin_Completed::total 118811 # Table walker requests started/completed, data/inst 534system.cpu.itb.walker.walkRequestOrigin::total 254562 # Table walker requests started/completed, data/inst 535system.cpu.itb.inst_hits 452655900 # ITB inst hits 536system.cpu.itb.inst_misses 135751 # ITB inst misses 537system.cpu.itb.read_hits 0 # DTB read hits 538system.cpu.itb.read_misses 0 # DTB read misses 539system.cpu.itb.write_hits 0 # DTB write hits 540system.cpu.itb.write_misses 0 # DTB write misses 541system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 542system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 543system.cpu.itb.flush_tlb_mva_asid 47051 # Number of times TLB was flushed by MVA & ASID 544system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID 545system.cpu.itb.flush_entries 57242 # Number of entries that have been flushed from TLB 546system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 547system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 548system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 549system.cpu.itb.perms_faults 322846 # Number of TLB faults due to permissions restrictions 550system.cpu.itb.read_accesses 0 # DTB read accesses 551system.cpu.itb.write_accesses 0 # DTB write accesses 552system.cpu.itb.inst_accesses 452791651 # ITB inst accesses 553system.cpu.itb.hits 452655900 # DTB hits 554system.cpu.itb.misses 135751 # DTB misses 555system.cpu.itb.accesses 452791651 # DTB accesses 556system.cpu.numPwrStateTransitions 33180 # Number of power state transitions 557system.cpu.pwrStateClkGateDist::samples 16590 # Distribution of time spent in the clock gated state 558system.cpu.pwrStateClkGateDist::mean 3039388324.246233 # Distribution of time spent in the clock gated state 559system.cpu.pwrStateClkGateDist::stdev 59640903157.908096 # Distribution of time spent in the clock gated state 560system.cpu.pwrStateClkGateDist::underflows 7293 43.96% 43.96% # Distribution of time spent in the clock gated state 561system.cpu.pwrStateClkGateDist::1000-5e+10 9262 55.83% 99.79% # Distribution of time spent in the clock gated state 562system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 563system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 564system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 570system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 571system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 572system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 573system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state 574system.cpu.pwrStateClkGateDist::total 16590 # Distribution of time spent in the clock gated state 575system.cpu.pwrStateResidencyTicks::ON 1265322690755 # Cumulative time (in ticks) in various power states 576system.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245 # Cumulative time (in ticks) in various power states 577system.cpu.numCycles 2530699433 # number of cpu cycles simulated 578system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 579system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 580system.cpu.committedInsts 946928269 # Number of instructions committed 581system.cpu.committedOps 1112623169 # Number of ops (including micro ops) committed 582system.cpu.discardedOps 97851669 # Number of ops (including micro ops) which were discarded before commit 583system.cpu.numFetchSuspends 7730 # Number of times Execute suspended instruction fetching 584system.cpu.quiesceCycles 100847957157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 585system.cpu.cpi 2.672536 # CPI: cycles per instruction 586system.cpu.ipc 0.374177 # IPC: instructions per cycle 587system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 588system.cpu.op_class_0::IntAlu 771151081 69.31% 69.31% # Class of committed instruction 589system.cpu.op_class_0::IntMult 2302642 0.21% 69.52% # Class of committed instruction 590system.cpu.op_class_0::IntDiv 99189 0.01% 69.53% # Class of committed instruction 591system.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction 592system.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction 593system.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction 594system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction 595system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction 596system.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction 597system.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction 598system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction 599system.cpu.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction 600system.cpu.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction 601system.cpu.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction 602system.cpu.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction 603system.cpu.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction 604system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction 605system.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction 606system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction 607system.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction 608system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction 609system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction 610system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction 611system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction 612system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction 613system.cpu.op_class_0::SimdFloatMisc 108989 0.01% 69.53% # Class of committed instruction 614system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction 615system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction 616system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction 617system.cpu.op_class_0::MemRead 177312606 15.94% 85.47% # Class of committed instruction 618system.cpu.op_class_0::MemWrite 161648619 14.53% 100.00% # Class of committed instruction 619system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 620system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 621system.cpu.op_class_0::total 1112623169 # Class of committed instruction 622system.cpu.kern.inst.arm 0 # number of arm instructions executed 623system.cpu.kern.inst.quiesce 16590 # number of quiesce instructions executed 624system.cpu.tickCycles 1791525295 # Number of cycles that the object actually ticked 625system.cpu.idleCycles 739174138 # Total number of cycles that the object has spent stopped 626system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 627system.cpu.dcache.tags.replacements 11091024 # number of replacements 628system.cpu.dcache.tags.tagsinuse 511.954083 # Cycle average of tags in use 629system.cpu.dcache.tags.total_refs 329234475 # Total number of references to valid blocks. 630system.cpu.dcache.tags.sampled_refs 11091536 # Sample count of references to valid blocks. 631system.cpu.dcache.tags.avg_refs 29.683398 # Average number of references to valid blocks. 632system.cpu.dcache.tags.warmup_cycle 4655908500 # Cycle when the warmup percentage was hit. 633system.cpu.dcache.tags.occ_blocks::cpu.data 511.954083 # Average occupied blocks per requestor 634system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy 635system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy 636system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 637system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 638system.cpu.dcache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 639system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 640system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 641system.cpu.dcache.tags.tag_accesses 1381544711 # Number of tag accesses 642system.cpu.dcache.tags.data_accesses 1381544711 # Number of data accesses 643system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 644system.cpu.dcache.ReadReq_hits::cpu.data 168600534 # number of ReadReq hits 645system.cpu.dcache.ReadReq_hits::total 168600534 # number of ReadReq hits 646system.cpu.dcache.WriteReq_hits::cpu.data 151416750 # number of WriteReq hits 647system.cpu.dcache.WriteReq_hits::total 151416750 # number of WriteReq hits 648system.cpu.dcache.SoftPFReq_hits::cpu.data 521238 # number of SoftPFReq hits 649system.cpu.dcache.SoftPFReq_hits::total 521238 # number of SoftPFReq hits 650system.cpu.dcache.WriteLineReq_hits::cpu.data 337307 # number of WriteLineReq hits 651system.cpu.dcache.WriteLineReq_hits::total 337307 # number of WriteLineReq hits 652system.cpu.dcache.LoadLockedReq_hits::cpu.data 4005998 # number of LoadLockedReq hits 653system.cpu.dcache.LoadLockedReq_hits::total 4005998 # number of LoadLockedReq hits 654system.cpu.dcache.StoreCondReq_hits::cpu.data 4318996 # number of StoreCondReq hits 655system.cpu.dcache.StoreCondReq_hits::total 4318996 # number of StoreCondReq hits 656system.cpu.dcache.demand_hits::cpu.data 320354591 # number of demand (read+write) hits 657system.cpu.dcache.demand_hits::total 320354591 # number of demand (read+write) hits 658system.cpu.dcache.overall_hits::cpu.data 320875829 # number of overall hits 659system.cpu.dcache.overall_hits::total 320875829 # number of overall hits 660system.cpu.dcache.ReadReq_misses::cpu.data 6093036 # number of ReadReq misses 661system.cpu.dcache.ReadReq_misses::total 6093036 # number of ReadReq misses 662system.cpu.dcache.WriteReq_misses::cpu.data 4287792 # number of WriteReq misses 663system.cpu.dcache.WriteReq_misses::total 4287792 # number of WriteReq misses 664system.cpu.dcache.SoftPFReq_misses::cpu.data 1473735 # number of SoftPFReq misses 665system.cpu.dcache.SoftPFReq_misses::total 1473735 # number of SoftPFReq misses 666system.cpu.dcache.WriteLineReq_misses::cpu.data 1243168 # number of WriteLineReq misses 667system.cpu.dcache.WriteLineReq_misses::total 1243168 # number of WriteLineReq misses 668system.cpu.dcache.LoadLockedReq_misses::cpu.data 314729 # number of LoadLockedReq misses 669system.cpu.dcache.LoadLockedReq_misses::total 314729 # number of LoadLockedReq misses 670system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 671system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 672system.cpu.dcache.demand_misses::cpu.data 11623996 # number of demand (read+write) misses 673system.cpu.dcache.demand_misses::total 11623996 # number of demand (read+write) misses 674system.cpu.dcache.overall_misses::cpu.data 13097731 # number of overall misses 675system.cpu.dcache.overall_misses::total 13097731 # number of overall misses 676system.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000 # number of ReadReq miss cycles 677system.cpu.dcache.ReadReq_miss_latency::total 107249746000 # number of ReadReq miss cycles 678system.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500 # number of WriteReq miss cycles 679system.cpu.dcache.WriteReq_miss_latency::total 169106972500 # number of WriteReq miss cycles 680system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27289591000 # number of WriteLineReq miss cycles 681system.cpu.dcache.WriteLineReq_miss_latency::total 27289591000 # number of WriteLineReq miss cycles 682system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5063641000 # number of LoadLockedReq miss cycles 683system.cpu.dcache.LoadLockedReq_miss_latency::total 5063641000 # number of LoadLockedReq miss cycles 684system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles 685system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles 686system.cpu.dcache.demand_miss_latency::cpu.data 303646309500 # number of demand (read+write) miss cycles 687system.cpu.dcache.demand_miss_latency::total 303646309500 # number of demand (read+write) miss cycles 688system.cpu.dcache.overall_miss_latency::cpu.data 303646309500 # number of overall miss cycles 689system.cpu.dcache.overall_miss_latency::total 303646309500 # number of overall miss cycles 690system.cpu.dcache.ReadReq_accesses::cpu.data 174693570 # number of ReadReq accesses(hits+misses) 691system.cpu.dcache.ReadReq_accesses::total 174693570 # number of ReadReq accesses(hits+misses) 692system.cpu.dcache.WriteReq_accesses::cpu.data 155704542 # number of WriteReq accesses(hits+misses) 693system.cpu.dcache.WriteReq_accesses::total 155704542 # number of WriteReq accesses(hits+misses) 694system.cpu.dcache.SoftPFReq_accesses::cpu.data 1994973 # number of SoftPFReq accesses(hits+misses) 695system.cpu.dcache.SoftPFReq_accesses::total 1994973 # number of SoftPFReq accesses(hits+misses) 696system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580475 # number of WriteLineReq accesses(hits+misses) 697system.cpu.dcache.WriteLineReq_accesses::total 1580475 # number of WriteLineReq accesses(hits+misses) 698system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4320727 # number of LoadLockedReq accesses(hits+misses) 699system.cpu.dcache.LoadLockedReq_accesses::total 4320727 # number of LoadLockedReq accesses(hits+misses) 700system.cpu.dcache.StoreCondReq_accesses::cpu.data 4318997 # number of StoreCondReq accesses(hits+misses) 701system.cpu.dcache.StoreCondReq_accesses::total 4318997 # number of StoreCondReq accesses(hits+misses) 702system.cpu.dcache.demand_accesses::cpu.data 331978587 # number of demand (read+write) accesses 703system.cpu.dcache.demand_accesses::total 331978587 # number of demand (read+write) accesses 704system.cpu.dcache.overall_accesses::cpu.data 333973560 # number of overall (read+write) accesses 705system.cpu.dcache.overall_accesses::total 333973560 # number of overall (read+write) accesses 706system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034878 # miss rate for ReadReq accesses 707system.cpu.dcache.ReadReq_miss_rate::total 0.034878 # miss rate for ReadReq accesses 708system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027538 # miss rate for WriteReq accesses 709system.cpu.dcache.WriteReq_miss_rate::total 0.027538 # miss rate for WriteReq accesses 710system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738724 # miss rate for SoftPFReq accesses 711system.cpu.dcache.SoftPFReq_miss_rate::total 0.738724 # miss rate for SoftPFReq accesses 712system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786579 # miss rate for WriteLineReq accesses 713system.cpu.dcache.WriteLineReq_miss_rate::total 0.786579 # miss rate for WriteLineReq accesses 714system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072842 # miss rate for LoadLockedReq accesses 715system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072842 # miss rate for LoadLockedReq accesses 716system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 717system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 718system.cpu.dcache.demand_miss_rate::cpu.data 0.035014 # miss rate for demand accesses 719system.cpu.dcache.demand_miss_rate::total 0.035014 # miss rate for demand accesses 720system.cpu.dcache.overall_miss_rate::cpu.data 0.039218 # miss rate for overall accesses 721system.cpu.dcache.overall_miss_rate::total 0.039218 # miss rate for overall accesses 722system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17602.020733 # average ReadReq miss latency 723system.cpu.dcache.ReadReq_avg_miss_latency::total 17602.020733 # average ReadReq miss latency 724system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39439.173472 # average WriteReq miss latency 725system.cpu.dcache.WriteReq_avg_miss_latency::total 39439.173472 # average WriteReq miss latency 726system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21951.651748 # average WriteLineReq miss latency 727system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21951.651748 # average WriteLineReq miss latency 728system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16088.892349 # average LoadLockedReq miss latency 729system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16088.892349 # average LoadLockedReq miss latency 730system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 731system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency 732system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.368719 # average overall miss latency 733system.cpu.dcache.demand_avg_miss_latency::total 26122.368719 # average overall miss latency 734system.cpu.dcache.overall_avg_miss_latency::cpu.data 23183.123054 # average overall miss latency 735system.cpu.dcache.overall_avg_miss_latency::total 23183.123054 # average overall miss latency 736system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked 737system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 738system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 739system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 740system.cpu.dcache.avg_blocked_cycles::no_mshrs 19 # average number of cycles each access was blocked 741system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 742system.cpu.dcache.writebacks::writebacks 8512101 # number of writebacks 743system.cpu.dcache.writebacks::total 8512101 # number of writebacks 744system.cpu.dcache.ReadReq_mshr_hits::cpu.data 311042 # number of ReadReq MSHR hits 745system.cpu.dcache.ReadReq_mshr_hits::total 311042 # number of ReadReq MSHR hits 746system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1897692 # number of WriteReq MSHR hits 747system.cpu.dcache.WriteReq_mshr_hits::total 1897692 # number of WriteReq MSHR hits 748system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits 749system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits 750system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70889 # number of LoadLockedReq MSHR hits 751system.cpu.dcache.LoadLockedReq_mshr_hits::total 70889 # number of LoadLockedReq MSHR hits 752system.cpu.dcache.demand_mshr_hits::cpu.data 2208886 # number of demand (read+write) MSHR hits 753system.cpu.dcache.demand_mshr_hits::total 2208886 # number of demand (read+write) MSHR hits 754system.cpu.dcache.overall_mshr_hits::cpu.data 2208886 # number of overall MSHR hits 755system.cpu.dcache.overall_mshr_hits::total 2208886 # number of overall MSHR hits 756system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5781994 # number of ReadReq MSHR misses 757system.cpu.dcache.ReadReq_mshr_misses::total 5781994 # number of ReadReq MSHR misses 758system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2390100 # number of WriteReq MSHR misses 759system.cpu.dcache.WriteReq_mshr_misses::total 2390100 # number of WriteReq MSHR misses 760system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466271 # number of SoftPFReq MSHR misses 761system.cpu.dcache.SoftPFReq_mshr_misses::total 1466271 # number of SoftPFReq MSHR misses 762system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1243016 # number of WriteLineReq MSHR misses 763system.cpu.dcache.WriteLineReq_mshr_misses::total 1243016 # number of WriteLineReq MSHR misses 764system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 243840 # number of LoadLockedReq MSHR misses 765system.cpu.dcache.LoadLockedReq_mshr_misses::total 243840 # number of LoadLockedReq MSHR misses 766system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 767system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 768system.cpu.dcache.demand_mshr_misses::cpu.data 9415110 # number of demand (read+write) MSHR misses 769system.cpu.dcache.demand_mshr_misses::total 9415110 # number of demand (read+write) MSHR misses 770system.cpu.dcache.overall_mshr_misses::cpu.data 10881381 # number of overall MSHR misses 771system.cpu.dcache.overall_mshr_misses::total 10881381 # number of overall MSHR misses 772system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 773system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable 774system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 775system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 776system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 777system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 778system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94763834000 # number of ReadReq MSHR miss cycles 779system.cpu.dcache.ReadReq_mshr_miss_latency::total 94763834000 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88482137000 # number of WriteReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency::total 88482137000 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25605238500 # number of SoftPFReq MSHR miss cycles 783system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25605238500 # number of SoftPFReq MSHR miss cycles 784system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26041674000 # number of WriteLineReq MSHR miss cycles 785system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26041674000 # number of WriteLineReq MSHR miss cycles 786system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3459340500 # number of LoadLockedReq MSHR miss cycles 787system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3459340500 # number of LoadLockedReq MSHR miss cycles 788system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles 789system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles 790system.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000 # number of demand (read+write) MSHR miss cycles 791system.cpu.dcache.demand_mshr_miss_latency::total 209287645000 # number of demand (read+write) MSHR miss cycles 792system.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500 # number of overall MSHR miss cycles 793system.cpu.dcache.overall_mshr_miss_latency::total 234892883500 # number of overall MSHR miss cycles 794system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231136500 # number of ReadReq MSHR uncacheable cycles 795system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231136500 # number of ReadReq MSHR uncacheable cycles 796system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231136500 # number of overall MSHR uncacheable cycles 797system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231136500 # number of overall MSHR uncacheable cycles 798system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033098 # mshr miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033098 # mshr miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015350 # mshr miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015350 # mshr miss rate for WriteReq accesses 802system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734983 # mshr miss rate for SoftPFReq accesses 803system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734983 # mshr miss rate for SoftPFReq accesses 804system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786483 # mshr miss rate for WriteLineReq accesses 805system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786483 # mshr miss rate for WriteLineReq accesses 806system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056435 # mshr miss rate for LoadLockedReq accesses 807system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056435 # mshr miss rate for LoadLockedReq accesses 808system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 809system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 810system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028361 # mshr miss rate for demand accesses 811system.cpu.dcache.demand_mshr_miss_rate::total 0.028361 # mshr miss rate for demand accesses 812system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032582 # mshr miss rate for overall accesses 813system.cpu.dcache.overall_mshr_miss_rate::total 0.032582 # mshr miss rate for overall accesses 814system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905 # average ReadReq mshr miss latency 815system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905 # average ReadReq mshr miss latency 816system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679 # average WriteReq mshr miss latency 817system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679 # average WriteReq mshr miss latency 818system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154 # average SoftPFReq mshr miss latency 819system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154 # average SoftPFReq mshr miss latency 820system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237 # average WriteLineReq mshr miss latency 821system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237 # average WriteLineReq mshr miss latency 822system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904 # average LoadLockedReq mshr miss latency 823system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904 # average LoadLockedReq mshr miss latency 824system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 825system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency 826system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293 # average overall mshr miss latency 827system.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293 # average overall mshr miss latency 828system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439 # average overall mshr miss latency 829system.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439 # average overall mshr miss latency 830system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094 # average ReadReq mshr uncacheable latency 831system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094 # average ReadReq mshr uncacheable latency 832system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633 # average overall mshr uncacheable latency 833system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633 # average overall mshr uncacheable latency 834system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 835system.cpu.icache.tags.replacements 24547500 # number of replacements 836system.cpu.icache.tags.tagsinuse 511.926335 # Cycle average of tags in use 837system.cpu.icache.tags.total_refs 427774095 # Total number of references to valid blocks. 838system.cpu.icache.tags.sampled_refs 24548012 # Sample count of references to valid blocks. 839system.cpu.icache.tags.avg_refs 17.426018 # Average number of references to valid blocks. 840system.cpu.icache.tags.warmup_cycle 21430762500 # Cycle when the warmup percentage was hit. 841system.cpu.icache.tags.occ_blocks::cpu.inst 511.926335 # Average occupied blocks per requestor 842system.cpu.icache.tags.occ_percent::cpu.inst 0.999856 # Average percentage of cache occupancy 843system.cpu.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy 844system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 845system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 846system.cpu.icache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id 847system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id 848system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 849system.cpu.icache.tags.tag_accesses 476870138 # Number of tag accesses 850system.cpu.icache.tags.data_accesses 476870138 # Number of data accesses 851system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 852system.cpu.icache.ReadReq_hits::cpu.inst 427774095 # number of ReadReq hits 853system.cpu.icache.ReadReq_hits::total 427774095 # number of ReadReq hits 854system.cpu.icache.demand_hits::cpu.inst 427774095 # number of demand (read+write) hits 855system.cpu.icache.demand_hits::total 427774095 # number of demand (read+write) hits 856system.cpu.icache.overall_hits::cpu.inst 427774095 # number of overall hits 857system.cpu.icache.overall_hits::total 427774095 # number of overall hits 858system.cpu.icache.ReadReq_misses::cpu.inst 24548022 # number of ReadReq misses 859system.cpu.icache.ReadReq_misses::total 24548022 # number of ReadReq misses 860system.cpu.icache.demand_misses::cpu.inst 24548022 # number of demand (read+write) misses 861system.cpu.icache.demand_misses::total 24548022 # number of demand (read+write) misses 862system.cpu.icache.overall_misses::cpu.inst 24548022 # number of overall misses 863system.cpu.icache.overall_misses::total 24548022 # number of overall misses 864system.cpu.icache.ReadReq_miss_latency::cpu.inst 329750158000 # number of ReadReq miss cycles 865system.cpu.icache.ReadReq_miss_latency::total 329750158000 # number of ReadReq miss cycles 866system.cpu.icache.demand_miss_latency::cpu.inst 329750158000 # number of demand (read+write) miss cycles 867system.cpu.icache.demand_miss_latency::total 329750158000 # number of demand (read+write) miss cycles 868system.cpu.icache.overall_miss_latency::cpu.inst 329750158000 # number of overall miss cycles 869system.cpu.icache.overall_miss_latency::total 329750158000 # number of overall miss cycles 870system.cpu.icache.ReadReq_accesses::cpu.inst 452322117 # number of ReadReq accesses(hits+misses) 871system.cpu.icache.ReadReq_accesses::total 452322117 # number of ReadReq accesses(hits+misses) 872system.cpu.icache.demand_accesses::cpu.inst 452322117 # number of demand (read+write) accesses 873system.cpu.icache.demand_accesses::total 452322117 # number of demand (read+write) accesses 874system.cpu.icache.overall_accesses::cpu.inst 452322117 # number of overall (read+write) accesses 875system.cpu.icache.overall_accesses::total 452322117 # number of overall (read+write) accesses 876system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses 877system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses 878system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses 879system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses 880system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses 881system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses 882system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13432.860619 # average ReadReq miss latency 883system.cpu.icache.ReadReq_avg_miss_latency::total 13432.860619 # average ReadReq miss latency 884system.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency 885system.cpu.icache.demand_avg_miss_latency::total 13432.860619 # average overall miss latency 886system.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619 # average overall miss latency 887system.cpu.icache.overall_avg_miss_latency::total 13432.860619 # average overall miss latency 888system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 889system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 890system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 891system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 892system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 893system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 894system.cpu.icache.writebacks::writebacks 24547500 # number of writebacks 895system.cpu.icache.writebacks::total 24547500 # number of writebacks 896system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24548022 # number of ReadReq MSHR misses 897system.cpu.icache.ReadReq_mshr_misses::total 24548022 # number of ReadReq MSHR misses 898system.cpu.icache.demand_mshr_misses::cpu.inst 24548022 # number of demand (read+write) MSHR misses 899system.cpu.icache.demand_mshr_misses::total 24548022 # number of demand (read+write) MSHR misses 900system.cpu.icache.overall_mshr_misses::cpu.inst 24548022 # number of overall MSHR misses 901system.cpu.icache.overall_mshr_misses::total 24548022 # number of overall MSHR misses 902system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable 903system.cpu.icache.ReadReq_mshr_uncacheable::total 52291 # number of ReadReq MSHR uncacheable 904system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses 905system.cpu.icache.overall_mshr_uncacheable_misses::total 52291 # number of overall MSHR uncacheable misses 906system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305202137000 # number of ReadReq MSHR miss cycles 907system.cpu.icache.ReadReq_mshr_miss_latency::total 305202137000 # number of ReadReq MSHR miss cycles 908system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305202137000 # number of demand (read+write) MSHR miss cycles 909system.cpu.icache.demand_mshr_miss_latency::total 305202137000 # number of demand (read+write) MSHR miss cycles 910system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305202137000 # number of overall MSHR miss cycles 911system.cpu.icache.overall_mshr_miss_latency::total 305202137000 # number of overall MSHR miss cycles 912system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4421533000 # number of ReadReq MSHR uncacheable cycles 913system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4421533000 # number of ReadReq MSHR uncacheable cycles 914system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4421533000 # number of overall MSHR uncacheable cycles 915system.cpu.icache.overall_mshr_uncacheable_latency::total 4421533000 # number of overall MSHR uncacheable cycles 916system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses 917system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses 918system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses 919system.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses 920system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses 921system.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses 922system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12432.860660 # average ReadReq mshr miss latency 923system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12432.860660 # average ReadReq mshr miss latency 924system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency 925system.cpu.icache.demand_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency 926system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12432.860660 # average overall mshr miss latency 927system.cpu.icache.overall_avg_mshr_miss_latency::total 12432.860660 # average overall mshr miss latency 928system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average ReadReq mshr uncacheable latency 929system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757 # average ReadReq mshr uncacheable latency 930system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average overall mshr uncacheable latency 931system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757 # average overall mshr uncacheable latency 932system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 933system.cpu.l2cache.tags.replacements 1591901 # number of replacements 934system.cpu.l2cache.tags.tagsinuse 65408.549959 # Cycle average of tags in use 935system.cpu.l2cache.tags.total_refs 69520908 # Total number of references to valid blocks. 936system.cpu.l2cache.tags.sampled_refs 1655396 # Sample count of references to valid blocks. 937system.cpu.l2cache.tags.avg_refs 41.996542 # Average number of references to valid blocks. 938system.cpu.l2cache.tags.warmup_cycle 6255171000 # Cycle when the warmup percentage was hit. 939system.cpu.l2cache.tags.occ_blocks::writebacks 9036.958133 # Average occupied blocks per requestor 940system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 433.683776 # Average occupied blocks per requestor 941system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 402.305370 # Average occupied blocks per requestor 942system.cpu.l2cache.tags.occ_blocks::cpu.inst 7871.756997 # Average occupied blocks per requestor 943system.cpu.l2cache.tags.occ_blocks::cpu.data 47663.845683 # Average occupied blocks per requestor 944system.cpu.l2cache.tags.occ_percent::writebacks 0.137893 # Average percentage of cache occupancy 945system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006617 # Average percentage of cache occupancy 946system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006139 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120113 # Average percentage of cache occupancy 948system.cpu.l2cache.tags.occ_percent::cpu.data 0.727293 # Average percentage of cache occupancy 949system.cpu.l2cache.tags.occ_percent::total 0.998055 # Average percentage of cache occupancy 950system.cpu.l2cache.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id 951system.cpu.l2cache.tags.occ_task_id_blocks::1024 63224 # Occupied blocks per task id 952system.cpu.l2cache.tags.age_task_id_blocks_1023::4 271 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 955system.cpu.l2cache.tags.age_task_id_blocks_1024::2 790 # Occupied blocks per task id 956system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5976 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56108 # Occupied blocks per task id 958system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id 959system.cpu.l2cache.tags.occ_task_id_percent::1024 0.964722 # Percentage of cache occupancy per task id 960system.cpu.l2cache.tags.tag_accesses 582399864 # Number of tag accesses 961system.cpu.l2cache.tags.data_accesses 582399864 # Number of data accesses 962system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 963system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 921588 # number of ReadReq hits 964system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 261482 # number of ReadReq hits 965system.cpu.l2cache.ReadReq_hits::total 1183070 # number of ReadReq hits 966system.cpu.l2cache.WritebackDirty_hits::writebacks 8512101 # number of WritebackDirty hits 967system.cpu.l2cache.WritebackDirty_hits::total 8512101 # number of WritebackDirty hits 968system.cpu.l2cache.WritebackClean_hits::writebacks 24543775 # number of WritebackClean hits 969system.cpu.l2cache.WritebackClean_hits::total 24543775 # number of WritebackClean hits 970system.cpu.l2cache.UpgradeReq_hits::cpu.data 29573 # number of UpgradeReq hits 971system.cpu.l2cache.UpgradeReq_hits::total 29573 # number of UpgradeReq hits 972system.cpu.l2cache.ReadExReq_hits::cpu.data 1660508 # number of ReadExReq hits 973system.cpu.l2cache.ReadExReq_hits::total 1660508 # number of ReadExReq hits 974system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24440962 # number of ReadCleanReq hits 975system.cpu.l2cache.ReadCleanReq_hits::total 24440962 # number of ReadCleanReq hits 976system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7164937 # number of ReadSharedReq hits 977system.cpu.l2cache.ReadSharedReq_hits::total 7164937 # number of ReadSharedReq hits 978system.cpu.l2cache.InvalidateReq_hits::cpu.data 700668 # number of InvalidateReq hits 979system.cpu.l2cache.InvalidateReq_hits::total 700668 # number of InvalidateReq hits 980system.cpu.l2cache.demand_hits::cpu.dtb.walker 921588 # number of demand (read+write) hits 981system.cpu.l2cache.demand_hits::cpu.itb.walker 261482 # number of demand (read+write) hits 982system.cpu.l2cache.demand_hits::cpu.inst 24440962 # number of demand (read+write) hits 983system.cpu.l2cache.demand_hits::cpu.data 8825445 # number of demand (read+write) hits 984system.cpu.l2cache.demand_hits::total 34449477 # number of demand (read+write) hits 985system.cpu.l2cache.overall_hits::cpu.dtb.walker 921588 # number of overall hits 986system.cpu.l2cache.overall_hits::cpu.itb.walker 261482 # number of overall hits 987system.cpu.l2cache.overall_hits::cpu.inst 24440962 # number of overall hits 988system.cpu.l2cache.overall_hits::cpu.data 8825445 # number of overall hits 989system.cpu.l2cache.overall_hits::total 34449477 # number of overall hits 990system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6273 # number of ReadReq misses 991system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5180 # number of ReadReq misses 992system.cpu.l2cache.ReadReq_misses::total 11453 # number of ReadReq misses 993system.cpu.l2cache.UpgradeReq_misses::cpu.data 4073 # number of UpgradeReq misses 994system.cpu.l2cache.UpgradeReq_misses::total 4073 # number of UpgradeReq misses 995system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 996system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 997system.cpu.l2cache.ReadExReq_misses::cpu.data 696158 # number of ReadExReq misses 998system.cpu.l2cache.ReadExReq_misses::total 696158 # number of ReadExReq misses 999system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107059 # number of ReadCleanReq misses 1000system.cpu.l2cache.ReadCleanReq_misses::total 107059 # number of ReadCleanReq misses 1001system.cpu.l2cache.ReadSharedReq_misses::cpu.data 326956 # number of ReadSharedReq misses 1002system.cpu.l2cache.ReadSharedReq_misses::total 326956 # number of ReadSharedReq misses 1003system.cpu.l2cache.InvalidateReq_misses::cpu.data 542348 # number of InvalidateReq misses 1004system.cpu.l2cache.InvalidateReq_misses::total 542348 # number of InvalidateReq misses 1005system.cpu.l2cache.demand_misses::cpu.dtb.walker 6273 # number of demand (read+write) misses 1006system.cpu.l2cache.demand_misses::cpu.itb.walker 5180 # number of demand (read+write) misses 1007system.cpu.l2cache.demand_misses::cpu.inst 107059 # number of demand (read+write) misses 1008system.cpu.l2cache.demand_misses::cpu.data 1023114 # number of demand (read+write) misses 1009system.cpu.l2cache.demand_misses::total 1141626 # number of demand (read+write) misses 1010system.cpu.l2cache.overall_misses::cpu.dtb.walker 6273 # number of overall misses 1011system.cpu.l2cache.overall_misses::cpu.itb.walker 5180 # number of overall misses 1012system.cpu.l2cache.overall_misses::cpu.inst 107059 # number of overall misses 1013system.cpu.l2cache.overall_misses::cpu.data 1023114 # number of overall misses 1014system.cpu.l2cache.overall_misses::total 1141626 # number of overall misses 1015system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 939749000 # number of ReadReq miss cycles 1016system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 683365000 # number of ReadReq miss cycles 1017system.cpu.l2cache.ReadReq_miss_latency::total 1623114000 # number of ReadReq miss cycles 1018system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72777000 # number of UpgradeReq miss cycles 1019system.cpu.l2cache.UpgradeReq_miss_latency::total 72777000 # number of UpgradeReq miss cycles 1020system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles 1021system.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles 1022system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66999821500 # number of ReadExReq miss cycles 1023system.cpu.l2cache.ReadExReq_miss_latency::total 66999821500 # number of ReadExReq miss cycles 1024system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11524194500 # number of ReadCleanReq miss cycles 1025system.cpu.l2cache.ReadCleanReq_miss_latency::total 11524194500 # number of ReadCleanReq miss cycles 1026system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37120013000 # number of ReadSharedReq miss cycles 1027system.cpu.l2cache.ReadSharedReq_miss_latency::total 37120013000 # number of ReadSharedReq miss cycles 1028system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 2135500 # number of InvalidateReq miss cycles 1029system.cpu.l2cache.InvalidateReq_miss_latency::total 2135500 # number of InvalidateReq miss cycles 1030system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 939749000 # number of demand (read+write) miss cycles 1031system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 683365000 # number of demand (read+write) miss cycles 1032system.cpu.l2cache.demand_miss_latency::cpu.inst 11524194500 # number of demand (read+write) miss cycles 1033system.cpu.l2cache.demand_miss_latency::cpu.data 104119834500 # number of demand (read+write) miss cycles 1034system.cpu.l2cache.demand_miss_latency::total 117267143000 # number of demand (read+write) miss cycles 1035system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 939749000 # number of overall miss cycles 1036system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 683365000 # number of overall miss cycles 1037system.cpu.l2cache.overall_miss_latency::cpu.inst 11524194500 # number of overall miss cycles 1038system.cpu.l2cache.overall_miss_latency::cpu.data 104119834500 # number of overall miss cycles 1039system.cpu.l2cache.overall_miss_latency::total 117267143000 # number of overall miss cycles 1040system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927861 # number of ReadReq accesses(hits+misses) 1041system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 266662 # number of ReadReq accesses(hits+misses) 1042system.cpu.l2cache.ReadReq_accesses::total 1194523 # number of ReadReq accesses(hits+misses) 1043system.cpu.l2cache.WritebackDirty_accesses::writebacks 8512101 # number of WritebackDirty accesses(hits+misses) 1044system.cpu.l2cache.WritebackDirty_accesses::total 8512101 # number of WritebackDirty accesses(hits+misses) 1045system.cpu.l2cache.WritebackClean_accesses::writebacks 24543775 # number of WritebackClean accesses(hits+misses) 1046system.cpu.l2cache.WritebackClean_accesses::total 24543775 # number of WritebackClean accesses(hits+misses) 1047system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33646 # number of UpgradeReq accesses(hits+misses) 1048system.cpu.l2cache.UpgradeReq_accesses::total 33646 # number of UpgradeReq accesses(hits+misses) 1049system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1050system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1051system.cpu.l2cache.ReadExReq_accesses::cpu.data 2356666 # number of ReadExReq accesses(hits+misses) 1052system.cpu.l2cache.ReadExReq_accesses::total 2356666 # number of ReadExReq accesses(hits+misses) 1053system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24548021 # number of ReadCleanReq accesses(hits+misses) 1054system.cpu.l2cache.ReadCleanReq_accesses::total 24548021 # number of ReadCleanReq accesses(hits+misses) 1055system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7491893 # number of ReadSharedReq accesses(hits+misses) 1056system.cpu.l2cache.ReadSharedReq_accesses::total 7491893 # number of ReadSharedReq accesses(hits+misses) 1057system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1243016 # number of InvalidateReq accesses(hits+misses) 1058system.cpu.l2cache.InvalidateReq_accesses::total 1243016 # number of InvalidateReq accesses(hits+misses) 1059system.cpu.l2cache.demand_accesses::cpu.dtb.walker 927861 # number of demand (read+write) accesses 1060system.cpu.l2cache.demand_accesses::cpu.itb.walker 266662 # number of demand (read+write) accesses 1061system.cpu.l2cache.demand_accesses::cpu.inst 24548021 # number of demand (read+write) accesses 1062system.cpu.l2cache.demand_accesses::cpu.data 9848559 # number of demand (read+write) accesses 1063system.cpu.l2cache.demand_accesses::total 35591103 # number of demand (read+write) accesses 1064system.cpu.l2cache.overall_accesses::cpu.dtb.walker 927861 # number of overall (read+write) accesses 1065system.cpu.l2cache.overall_accesses::cpu.itb.walker 266662 # number of overall (read+write) accesses 1066system.cpu.l2cache.overall_accesses::cpu.inst 24548021 # number of overall (read+write) accesses 1067system.cpu.l2cache.overall_accesses::cpu.data 9848559 # number of overall (read+write) accesses 1068system.cpu.l2cache.overall_accesses::total 35591103 # number of overall (read+write) accesses 1069system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006761 # miss rate for ReadReq accesses 1070system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.019425 # miss rate for ReadReq accesses 1071system.cpu.l2cache.ReadReq_miss_rate::total 0.009588 # miss rate for ReadReq accesses 1072system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.121055 # miss rate for UpgradeReq accesses 1073system.cpu.l2cache.UpgradeReq_miss_rate::total 0.121055 # miss rate for UpgradeReq accesses 1074system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1075system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1076system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.295400 # miss rate for ReadExReq accesses 1077system.cpu.l2cache.ReadExReq_miss_rate::total 0.295400 # miss rate for ReadExReq accesses 1078system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004361 # miss rate for ReadCleanReq accesses 1079system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004361 # miss rate for ReadCleanReq accesses 1080system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043641 # miss rate for ReadSharedReq accesses 1081system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043641 # miss rate for ReadSharedReq accesses 1082system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.436316 # miss rate for InvalidateReq accesses 1083system.cpu.l2cache.InvalidateReq_miss_rate::total 0.436316 # miss rate for InvalidateReq accesses 1084system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006761 # miss rate for demand accesses 1085system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.019425 # miss rate for demand accesses 1086system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004361 # miss rate for demand accesses 1087system.cpu.l2cache.demand_miss_rate::cpu.data 0.103885 # miss rate for demand accesses 1088system.cpu.l2cache.demand_miss_rate::total 0.032076 # miss rate for demand accesses 1089system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006761 # miss rate for overall accesses 1090system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.019425 # miss rate for overall accesses 1091system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004361 # miss rate for overall accesses 1092system.cpu.l2cache.overall_miss_rate::cpu.data 0.103885 # miss rate for overall accesses 1093system.cpu.l2cache.overall_miss_rate::total 0.032076 # miss rate for overall accesses 1094system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149808.544556 # average ReadReq miss latency 1095system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 131923.745174 # average ReadReq miss latency 1096system.cpu.l2cache.ReadReq_avg_miss_latency::total 141719.549463 # average ReadReq miss latency 1097system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17868.156150 # average UpgradeReq miss latency 1098system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17868.156150 # average UpgradeReq miss latency 1099system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 1100system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency 1101system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96242.263251 # average ReadExReq miss latency 1102system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96242.263251 # average ReadExReq miss latency 1103system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107643.397566 # average ReadCleanReq miss latency 1104system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107643.397566 # average ReadCleanReq miss latency 1105system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113532.135823 # average ReadSharedReq miss latency 1106system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113532.135823 # average ReadSharedReq miss latency 1107system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 3.937509 # average InvalidateReq miss latency 1108system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 3.937509 # average InvalidateReq miss latency 1109system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency 1110system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency 1111system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency 1112system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency 1113system.cpu.l2cache.demand_avg_miss_latency::total 102719.404604 # average overall miss latency 1114system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149808.544556 # average overall miss latency 1115system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 131923.745174 # average overall miss latency 1116system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107643.397566 # average overall miss latency 1117system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101767.578686 # average overall miss latency 1118system.cpu.l2cache.overall_avg_miss_latency::total 102719.404604 # average overall miss latency 1119system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1120system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1121system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1122system.cpu.l2cache.blocked::no_targets 0 # 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number of demand (read+write) MSHR hits 1134system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1135system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1136system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1137system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6273 # number of ReadReq MSHR misses 1138system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5180 # number of ReadReq MSHR misses 1139system.cpu.l2cache.ReadReq_mshr_misses::total 11453 # number of ReadReq MSHR misses 1140system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1141system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses 1142system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4073 # number of UpgradeReq MSHR misses 1143system.cpu.l2cache.UpgradeReq_mshr_misses::total 4073 # number of UpgradeReq MSHR misses 1144system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # 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number of demand (read+write) MSHR misses 1156system.cpu.l2cache.demand_mshr_misses::cpu.inst 107056 # number of demand (read+write) MSHR misses 1157system.cpu.l2cache.demand_mshr_misses::cpu.data 1023093 # number of demand (read+write) MSHR misses 1158system.cpu.l2cache.demand_mshr_misses::total 1141602 # number of demand (read+write) MSHR misses 1159system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6273 # number of overall MSHR misses 1160system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5180 # number of overall MSHR misses 1161system.cpu.l2cache.overall_mshr_misses::cpu.inst 107056 # number of overall MSHR misses 1162system.cpu.l2cache.overall_mshr_misses::cpu.data 1023093 # number of overall MSHR misses 1163system.cpu.l2cache.overall_mshr_misses::total 1141602 # number of overall MSHR misses 1164system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable 1165system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 1166system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85987 # 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number of InvalidateReq MSHR miss cycles 1186system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11199554001 # number of InvalidateReq MSHR miss cycles 1187system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 877019000 # number of demand (read+write) MSHR miss cycles 1188system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 631565000 # number of demand (read+write) MSHR miss cycles 1189system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10453433004 # number of demand (read+write) MSHR miss cycles 1190system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93887654549 # number of demand (read+write) MSHR miss cycles 1191system.cpu.l2cache.demand_mshr_miss_latency::total 105849671553 # number of demand (read+write) MSHR miss cycles 1192system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 877019000 # number of overall MSHR miss cycles 1193system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 631565000 # number of overall MSHR miss cycles 1194system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10453433004 # number of overall MSHR miss cycles 1195system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93887654549 # number of overall MSHR miss cycles 1196system.cpu.l2cache.overall_mshr_miss_latency::total 105849671553 # number of overall MSHR miss cycles 1197system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3611009000 # number of ReadReq MSHR uncacheable cycles 1198system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809783000 # number of ReadReq MSHR uncacheable cycles 1199system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420792000 # number of ReadReq MSHR uncacheable cycles 1200system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3611009000 # number of overall MSHR uncacheable cycles 1201system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809783000 # number of overall MSHR uncacheable cycles 1202system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420792000 # number of overall MSHR uncacheable cycles 1203system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for ReadReq accesses 1204system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for ReadReq accesses 1205system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009588 # mshr miss rate for ReadReq accesses 1206system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1207system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1208system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.121055 # mshr miss rate for UpgradeReq accesses 1209system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.121055 # mshr miss rate for UpgradeReq accesses 1210system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1211system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1212system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.295400 # mshr miss rate for ReadExReq accesses 1213system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.295400 # mshr miss rate for ReadExReq accesses 1214system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for ReadCleanReq accesses 1215system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004361 # mshr miss rate for ReadCleanReq accesses 1216system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043639 # mshr miss rate for ReadSharedReq accesses 1217system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043639 # mshr miss rate for ReadSharedReq accesses 1218system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.436316 # mshr miss rate for InvalidateReq accesses 1219system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.436316 # mshr miss rate for InvalidateReq accesses 1220system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for demand accesses 1221system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for demand accesses 1222system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for demand accesses 1223system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for demand accesses 1224system.cpu.l2cache.demand_mshr_miss_rate::total 0.032075 # mshr miss rate for demand accesses 1225system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006761 # mshr miss rate for overall accesses 1226system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019425 # mshr miss rate for overall accesses 1227system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004361 # mshr miss rate for overall accesses 1228system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.103883 # mshr miss rate for overall accesses 1229system.cpu.l2cache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses 1230system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average ReadReq mshr miss latency 1231system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average ReadReq mshr miss latency 1232system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463 # average ReadReq mshr miss latency 1233system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968 # average UpgradeReq mshr miss latency 1234system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968 # average UpgradeReq mshr miss latency 1235system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1236system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 1237system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534 # average ReadExReq mshr miss latency 1238system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534 # average ReadExReq mshr miss latency 1239system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871 # average ReadCleanReq mshr miss latency 1240system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871 # average ReadCleanReq mshr miss latency 1241system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613 # average ReadSharedReq mshr miss latency 1242system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613 # average ReadSharedReq mshr miss latency 1243system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014 # average InvalidateReq mshr miss latency 1244system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014 # average InvalidateReq mshr miss latency 1245system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency 1246system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency 1247system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency 1248system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency 1249system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency 1250system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556 # average overall mshr miss latency 1251system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174 # average overall mshr miss latency 1252system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871 # average overall mshr miss latency 1253system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829 # average overall mshr miss latency 1254system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670 # average overall mshr miss latency 1255system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average ReadReq mshr uncacheable latency 1256system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657 # average ReadReq mshr uncacheable latency 1257system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518 # average ReadReq mshr uncacheable latency 1258system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average overall mshr uncacheable latency 1259system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270 # average overall mshr uncacheable latency 1260system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624 # average overall mshr uncacheable latency 1261system.cpu.toL2Bus.snoop_filter.tot_requests 72021080 # Total number of requests made to the snoop filter. 1262system.cpu.toL2Bus.snoop_filter.hit_single_requests 36381496 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1263system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4425 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1264system.cpu.toL2Bus.snoop_filter.tot_snoops 1940 # Total number of snoops made to the snoop filter. 1265system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1940 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1266system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1267system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1268system.cpu.toL2Bus.trans_dist::ReadReq 1770978 # Transaction distribution 1269system.cpu.toL2Bus.trans_dist::ReadResp 33811680 # Transaction distribution 1270system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution 1271system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution 1272system.cpu.toL2Bus.trans_dist::WritebackDirty 9868219 # Transaction distribution 1273system.cpu.toL2Bus.trans_dist::WritebackClean 24547500 # Transaction distribution 1274system.cpu.toL2Bus.trans_dist::CleanEvict 2814706 # Transaction distribution 1275system.cpu.toL2Bus.trans_dist::UpgradeReq 33649 # Transaction distribution 1276system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1277system.cpu.toL2Bus.trans_dist::UpgradeResp 33650 # Transaction distribution 1278system.cpu.toL2Bus.trans_dist::ReadExReq 2356666 # Transaction distribution 1279system.cpu.toL2Bus.trans_dist::ReadExResp 2356666 # Transaction distribution 1280system.cpu.toL2Bus.trans_dist::ReadCleanReq 24548022 # Transaction distribution 1281system.cpu.toL2Bus.trans_dist::ReadSharedReq 7494335 # Transaction distribution 1282system.cpu.toL2Bus.trans_dist::InvalidateReq 1271849 # Transaction distribution 1283system.cpu.toL2Bus.trans_dist::InvalidateResp 1243016 # Transaction distribution 1284system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73748124 # Packet count per connected master and slave (bytes) 1285system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33477065 # Packet count per connected master and slave (bytes) 1286system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672528 # Packet count per connected master and slave (bytes) 1287system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2206986 # Packet count per connected master and slave (bytes) 1288system.cpu.toL2Bus.pkt_count::total 110104703 # Packet count per connected master and slave (bytes) 1289system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3145459904 # Cumulative packet size per connected master and slave (bytes) 1290system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1175323090 # Cumulative packet size per connected master and slave (bytes) 1291system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2133296 # Cumulative packet size per connected master and slave (bytes) 1292system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7422888 # Cumulative packet size per connected master and slave (bytes) 1293system.cpu.toL2Bus.pkt_size::total 4330339178 # Cumulative packet size per connected master and slave (bytes) 1294system.cpu.toL2Bus.snoops 2114439 # Total snoops (count) 1295system.cpu.toL2Bus.snoopTraffic 90765792 # Total snoop traffic (bytes) 1296system.cpu.toL2Bus.snoop_fanout::samples 39101108 # Request fanout histogram 1297system.cpu.toL2Bus.snoop_fanout::mean 0.018304 # Request fanout histogram 1298system.cpu.toL2Bus.snoop_fanout::stdev 0.134047 # Request fanout histogram 1299system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1300system.cpu.toL2Bus.snoop_fanout::0 38385418 98.17% 98.17% # Request fanout histogram 1301system.cpu.toL2Bus.snoop_fanout::1 715690 1.83% 100.00% # Request fanout histogram 1302system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1303system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1304system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1305system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1306system.cpu.toL2Bus.snoop_fanout::total 39101108 # Request fanout histogram 1307system.cpu.toL2Bus.reqLayer0.occupancy 69634684493 # Layer occupancy (ticks) 1308system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1309system.cpu.toL2Bus.snoopLayer0.occupancy 1487890 # Layer occupancy (ticks) 1310system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1311system.cpu.toL2Bus.respLayer0.occupancy 36904751913 # Layer occupancy (ticks) 1312system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1313system.cpu.toL2Bus.respLayer1.occupancy 15462672587 # Layer occupancy (ticks) 1314system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1315system.cpu.toL2Bus.respLayer2.occupancy 405908415 # Layer occupancy (ticks) 1316system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1317system.cpu.toL2Bus.respLayer3.occupancy 1279140469 # Layer occupancy (ticks) 1318system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1319system.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1320system.iobus.trans_dist::ReadReq 40325 # Transaction distribution 1321system.iobus.trans_dist::ReadResp 40325 # Transaction distribution 1322system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1323system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1324system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1327system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1328system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1329system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1330system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1331system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1332system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1333system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1334system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1335system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1336system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) 1339system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) 1340system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1342system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) 1343system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1344system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1345system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1346system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1347system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1348system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1349system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1350system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1351system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1352system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1353system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1354system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1355system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1356system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1357system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) 1358system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) 1359system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1360system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1361system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) 1362system.iobus.reqLayer0.occupancy 37691500 # Layer occupancy (ticks) 1363system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1364system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1365system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1366system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) 1367system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1368system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 1369system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1370system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 1371system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1372system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 1373system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1374system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1375system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1376system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 1377system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1378system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1379system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1380system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 1381system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1382system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1383system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1384system.iobus.reqLayer23.occupancy 25239000 # Layer occupancy (ticks) 1385system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1386system.iobus.reqLayer24.occupancy 36441500 # Layer occupancy (ticks) 1387system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1388system.iobus.reqLayer25.occupancy 569511366 # Layer occupancy (ticks) 1389system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1390system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1391system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1392system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) 1393system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1394system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1395system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1396system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1397system.iocache.tags.replacements 115486 # number of replacements 1398system.iocache.tags.tagsinuse 10.448155 # Cycle average of tags in use 1399system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1400system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. 1401system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1402system.iocache.tags.warmup_cycle 13141696144000 # Cycle when the warmup percentage was hit. 1403system.iocache.tags.occ_blocks::realview.ethernet 3.519387 # Average occupied blocks per requestor 1404system.iocache.tags.occ_blocks::realview.ide 6.928768 # Average occupied blocks per requestor 1405system.iocache.tags.occ_percent::realview.ethernet 0.219962 # Average percentage of cache occupancy 1406system.iocache.tags.occ_percent::realview.ide 0.433048 # Average percentage of cache occupancy 1407system.iocache.tags.occ_percent::total 0.653010 # Average percentage of cache occupancy 1408system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1409system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1410system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1411system.iocache.tags.tag_accesses 1039893 # Number of tag accesses 1412system.iocache.tags.data_accesses 1039893 # Number of data accesses 1413system.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1414system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1415system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses 1416system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses 1417system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1418system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1419system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1420system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1421system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1422system.iocache.demand_misses::realview.ide 115504 # number of demand (read+write) misses 1423system.iocache.demand_misses::total 115544 # number of demand (read+write) misses 1424system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1425system.iocache.overall_misses::realview.ide 115504 # number of overall misses 1426system.iocache.overall_misses::total 115544 # number of overall misses 1427system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles 1428system.iocache.ReadReq_miss_latency::realview.ide 2067712004 # number of ReadReq miss cycles 1429system.iocache.ReadReq_miss_latency::total 2072797504 # number of ReadReq miss cycles 1430system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1431system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1432system.iocache.WriteLineReq_miss_latency::realview.ide 13276938862 # number of WriteLineReq miss cycles 1433system.iocache.WriteLineReq_miss_latency::total 13276938862 # number of WriteLineReq miss cycles 1434system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles 1435system.iocache.demand_miss_latency::realview.ide 15344650866 # number of demand (read+write) miss cycles 1436system.iocache.demand_miss_latency::total 15350087366 # number of demand (read+write) miss cycles 1437system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles 1438system.iocache.overall_miss_latency::realview.ide 15344650866 # number of overall miss cycles 1439system.iocache.overall_miss_latency::total 15350087366 # number of overall miss cycles 1440system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1441system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) 1442system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) 1443system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1444system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1445system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1446system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1447system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1448system.iocache.demand_accesses::realview.ide 115504 # number of demand (read+write) accesses 1449system.iocache.demand_accesses::total 115544 # number of demand (read+write) accesses 1450system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1451system.iocache.overall_accesses::realview.ide 115504 # number of overall (read+write) accesses 1452system.iocache.overall_accesses::total 115544 # number of overall (read+write) accesses 1453system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1454system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1455system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1456system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1457system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1458system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1459system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1460system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1461system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1462system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1463system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1464system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1465system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1466system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency 1467system.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851 # average ReadReq miss latency 1468system.iocache.ReadReq_avg_miss_latency::total 233502.028163 # average ReadReq miss latency 1469system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1470system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1471system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692 # average WriteLineReq miss latency 1472system.iocache.WriteLineReq_avg_miss_latency::total 124474.413692 # average WriteLineReq miss latency 1473system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency 1474system.iocache.demand_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency 1475system.iocache.demand_avg_miss_latency::total 132850.579571 # average overall miss latency 1476system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency 1477system.iocache.overall_avg_miss_latency::realview.ide 132849.519203 # average overall miss latency 1478system.iocache.overall_avg_miss_latency::total 132850.579571 # average overall miss latency 1479system.iocache.blocked_cycles::no_mshrs 54006 # number of cycles access was blocked 1480system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1481system.iocache.blocked::no_mshrs 3503 # number of cycles access was blocked 1482system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1483system.iocache.avg_blocked_cycles::no_mshrs 15.417071 # average number of cycles each access was blocked 1484system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1485system.iocache.writebacks::writebacks 106631 # number of writebacks 1486system.iocache.writebacks::total 106631 # number of writebacks 1487system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1488system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses 1489system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses 1490system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1491system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1492system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1493system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1494system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1495system.iocache.demand_mshr_misses::realview.ide 115504 # number of demand (read+write) MSHR misses 1496system.iocache.demand_mshr_misses::total 115544 # number of demand (read+write) MSHR misses 1497system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1498system.iocache.overall_mshr_misses::realview.ide 115504 # number of overall MSHR misses 1499system.iocache.overall_mshr_misses::total 115544 # number of overall MSHR misses 1500system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles 1501system.iocache.ReadReq_mshr_miss_latency::realview.ide 1625712004 # number of ReadReq MSHR miss cycles 1502system.iocache.ReadReq_mshr_miss_latency::total 1628947504 # number of ReadReq MSHR miss cycles 1503system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1504system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1505system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7936726922 # number of WriteLineReq MSHR miss cycles 1506system.iocache.WriteLineReq_mshr_miss_latency::total 7936726922 # number of WriteLineReq MSHR miss cycles 1507system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles 1508system.iocache.demand_mshr_miss_latency::realview.ide 9562438926 # number of demand (read+write) MSHR miss cycles 1509system.iocache.demand_mshr_miss_latency::total 9565875426 # number of demand (read+write) MSHR miss cycles 1510system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles 1511system.iocache.overall_mshr_miss_latency::realview.ide 9562438926 # number of overall MSHR miss cycles 1512system.iocache.overall_mshr_miss_latency::total 9565875426 # number of overall MSHR miss cycles 1513system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1514system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1515system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1516system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1517system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1518system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1519system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1520system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1521system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1522system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1523system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1524system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1525system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1526system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency 1527system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851 # average ReadReq mshr miss latency 1528system.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163 # average ReadReq mshr miss latency 1529system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1530system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1531system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111 # average WriteLineReq mshr miss latency 1532system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111 # average WriteLineReq mshr miss latency 1533system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency 1534system.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency 1535system.iocache.demand_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency 1536system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency 1537system.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868 # average overall mshr miss latency 1538system.iocache.overall_avg_mshr_miss_latency::total 82789.893253 # average overall mshr miss latency 1539system.membus.snoop_filter.tot_requests 3510315 # Total number of requests made to the snoop filter. 1540system.membus.snoop_filter.hit_single_requests 1740308 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1541system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1542system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1543system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1544system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1545system.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1546system.membus.trans_dist::ReadReq 85987 # Transaction distribution 1547system.membus.trans_dist::ReadResp 540308 # Transaction distribution 1548system.membus.trans_dist::WriteReq 33707 # Transaction distribution 1549system.membus.trans_dist::WriteResp 33707 # Transaction distribution 1550system.membus.trans_dist::WritebackDirty 1462749 # Transaction distribution 1551system.membus.trans_dist::CleanEvict 243530 # Transaction distribution 1552system.membus.trans_dist::UpgradeReq 4703 # Transaction distribution 1553system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1554system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1555system.membus.trans_dist::ReadExReq 695596 # Transaction distribution 1556system.membus.trans_dist::ReadExResp 695596 # Transaction distribution 1557system.membus.trans_dist::ReadSharedReq 454321 # Transaction distribution 1558system.membus.trans_dist::InvalidateReq 648947 # Transaction distribution 1559system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1560system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1561system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) 1562system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4528935 # Packet count per connected master and slave (bytes) 1563system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4658587 # Packet count per connected master and slave (bytes) 1564system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237673 # Packet count per connected master and slave (bytes) 1565system.membus.pkt_count_system.iocache.mem_side::total 237673 # Packet count per connected master and slave (bytes) 1566system.membus.pkt_count::total 4896260 # Packet count per connected master and slave (bytes) 1567system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1568system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) 1570system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163142636 # Cumulative packet size per connected master and slave (bytes) 1571system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163313042 # Cumulative packet size per connected master and slave (bytes) 1572system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249536 # Cumulative packet size per connected master and slave (bytes) 1573system.membus.pkt_size_system.iocache.mem_side::total 7249536 # Cumulative packet size per connected master and slave (bytes) 1574system.membus.pkt_size::total 170562578 # Cumulative packet size per connected master and slave (bytes) 1575system.membus.snoops 2899 # Total snoops (count) 1576system.membus.snoopTraffic 185088 # Total snoop traffic (bytes) 1577system.membus.snoop_fanout::samples 1923263 # Request fanout histogram 1578system.membus.snoop_fanout::mean 0.016618 # Request fanout histogram 1579system.membus.snoop_fanout::stdev 0.127834 # Request fanout histogram 1580system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1581system.membus.snoop_fanout::0 1891303 98.34% 98.34% # Request fanout histogram 1582system.membus.snoop_fanout::1 31960 1.66% 100.00% # Request fanout histogram 1583system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1584system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1585system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1586system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1587system.membus.snoop_fanout::total 1923263 # Request fanout histogram 1588system.membus.reqLayer0.occupancy 99811000 # Layer occupancy (ticks) 1589system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1590system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) 1591system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1592system.membus.reqLayer2.occupancy 5612500 # Layer occupancy (ticks) 1593system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1594system.membus.reqLayer5.occupancy 9664854495 # Layer occupancy (ticks) 1595system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1596system.membus.respLayer2.occupancy 6432615655 # Layer occupancy (ticks) 1597system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1598system.membus.respLayer3.occupancy 44921497 # Layer occupancy (ticks) 1599system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1600system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1601system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1602system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1603system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1604system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1605system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1606system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1607system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1608system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1609system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1610system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1611system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1612system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1613system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1614system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1615system.realview.ethernet.txBytes 966 # Bytes Transmitted 1616system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1617system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1618system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1619system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1620system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1621system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1622system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1623system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1624system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1625system.realview.ethernet.totPackets 3 # Total Packets 1626system.realview.ethernet.totBytes 966 # Total Bytes 1627system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1628system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1629system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1630system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1631system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1632system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1633system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1634system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1635system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1636system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1637system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1638system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1639system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1640system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1641system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1642system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1643system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1644system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1645system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1646system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1647system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1648system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1649system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1650system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1651system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1652system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1653system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1654system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1655system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1656system.realview.ethernet.droppedPackets 0 # number of packets dropped 1657system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1658system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1659system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1660system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1661system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1662system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1663system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1664system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1665system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1666system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1667system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1668system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1669system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1670system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1671system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1672system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1673system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1674system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1675system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1676system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1677system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1678system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1679system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000 # Cumulative time (in ticks) in various power states 1680 1681---------- End Simulation Statistics ---------- 1682