stats.txt revision 11606:6b749761c398
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.687765 # Number of seconds simulated 4sim_ticks 51687764518000 # Number of ticks simulated 5final_tick 51687764518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 151884 # Simulator instruction rate (inst/s) 8host_op_rate 178474 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8204277049 # Simulator tick rate (ticks/s) 10host_mem_usage 687220 # Number of bytes of host memory used 11host_seconds 6300.10 # Real time elapsed on the host 12sim_insts 956884636 # Number of instructions simulated 13sim_ops 1124405089 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 423488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 359680 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10197440 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 68348040 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 416768 # Number of bytes read from this memory 22system.physmem.bytes_read::total 79745416 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 10197440 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 10197440 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 96812416 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 96832996 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 6617 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5620 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 159335 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1067951 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6512 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1246035 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1512694 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 1515267 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 8193 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 6959 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 197289 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1322325 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1542830 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 197289 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 197289 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1873024 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1873422 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1873024 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 8193 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 6959 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 197289 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1322723 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3416252 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 1246035 # Number of read requests accepted 56system.physmem.writeReqs 1515267 # Number of write requests accepted 57system.physmem.readBursts 1246035 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1515267 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 79703040 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 43200 # Total number of bytes read from write queue 61system.physmem.bytesWritten 96830656 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 79745416 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 96832996 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 675 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 74796 # Per bank write bursts 68system.physmem.perBankRdBursts::1 76131 # Per bank write bursts 69system.physmem.perBankRdBursts::2 70862 # Per bank write bursts 70system.physmem.perBankRdBursts::3 68837 # Per bank write bursts 71system.physmem.perBankRdBursts::4 72123 # Per bank write bursts 72system.physmem.perBankRdBursts::5 84628 # Per bank write bursts 73system.physmem.perBankRdBursts::6 78694 # Per bank write bursts 74system.physmem.perBankRdBursts::7 74893 # Per bank write bursts 75system.physmem.perBankRdBursts::8 72007 # Per bank write bursts 76system.physmem.perBankRdBursts::9 129561 # Per bank write bursts 77system.physmem.perBankRdBursts::10 74825 # Per bank write bursts 78system.physmem.perBankRdBursts::11 74032 # Per bank write bursts 79system.physmem.perBankRdBursts::12 72055 # Per bank write bursts 80system.physmem.perBankRdBursts::13 77727 # Per bank write bursts 81system.physmem.perBankRdBursts::14 71057 # Per bank write bursts 82system.physmem.perBankRdBursts::15 73132 # Per bank write bursts 83system.physmem.perBankWrBursts::0 93267 # Per bank write bursts 84system.physmem.perBankWrBursts::1 94026 # Per bank write bursts 85system.physmem.perBankWrBursts::2 93600 # Per bank write bursts 86system.physmem.perBankWrBursts::3 92665 # Per bank write bursts 87system.physmem.perBankWrBursts::4 94539 # Per bank write bursts 88system.physmem.perBankWrBursts::5 102396 # Per bank write bursts 89system.physmem.perBankWrBursts::6 95600 # Per bank write bursts 90system.physmem.perBankWrBursts::7 94740 # Per bank write bursts 91system.physmem.perBankWrBursts::8 92115 # Per bank write bursts 92system.physmem.perBankWrBursts::9 99710 # Per bank write bursts 93system.physmem.perBankWrBursts::10 92671 # Per bank write bursts 94system.physmem.perBankWrBursts::11 94633 # Per bank write bursts 95system.physmem.perBankWrBursts::12 92127 # Per bank write bursts 96system.physmem.perBankWrBursts::13 95527 # Per bank write bursts 97system.physmem.perBankWrBursts::14 92160 # Per bank write bursts 98system.physmem.perBankWrBursts::15 93203 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 30 # Number of times write queue was full causing retry 101system.physmem.totGap 51687762664000 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 0 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 1246020 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 1512694 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 1180646 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 58552 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 634 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 497 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 610 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 505 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1300 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 179 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 187 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 114 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 31478 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 39945 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 83104 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 89526 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 91633 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 87574 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 93055 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 92225 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 93220 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 90182 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 92806 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 94606 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 92258 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 89036 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 87252 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 83915 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 83414 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 82380 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1836 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 1645 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 1476 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 1315 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 971 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 998 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 886 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 686 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 632 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 592 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 464 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 405 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 381 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 229 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 168 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 180 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 145 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 106 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 79 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 686907 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 256.997398 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 154.492038 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 292.459663 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 294027 42.80% 42.80% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 175466 25.54% 68.35% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 64376 9.37% 77.72% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 35669 5.19% 82.91% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 24767 3.61% 86.52% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 16380 2.38% 88.90% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 12324 1.79% 90.70% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 10264 1.49% 92.19% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 53634 7.81% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 686907 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 80666 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 15.437595 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 138.740748 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 80664 100.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 80666 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 80666 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 18.756093 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.057108 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 7.363487 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 67894 84.17% 84.17% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 3915 4.85% 89.02% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 3350 4.15% 93.17% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 2485 3.08% 96.25% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 1103 1.37% 97.62% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 521 0.65% 98.27% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 244 0.30% 98.57% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 153 0.19% 98.76% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 79 0.10% 98.86% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 83 0.10% 98.96% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 83 0.10% 99.06% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 89 0.11% 99.17% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 450 0.56% 99.73% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 43 0.05% 99.78% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 41 0.05% 99.84% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 30 0.04% 99.87% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 23 0.03% 99.90% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 4 0.00% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::96-99 3 0.00% 99.92% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::108-111 9 0.01% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 18 0.02% 99.96% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::160-163 4 0.00% 99.99% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::172-175 5 0.01% 100.00% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::total 80666 # Writes before turning the bus around for reads 279system.physmem.totQLat 17151209707 # Total ticks spent queuing 280system.physmem.totMemAccLat 40501709707 # Total ticks spent from burst creation until serviced by the DRAM 281system.physmem.totBusLat 6226800000 # Total ticks spent in databus transfers 282system.physmem.avgQLat 13772.09 # Average queueing delay per DRAM burst 283system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 284system.physmem.avgMemAccLat 32522.09 # Average memory access latency per DRAM burst 285system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s 286system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s 287system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s 288system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s 289system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 290system.physmem.busUtil 0.03 # Data bus utilization in percentage 291system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 292system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 293system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 294system.physmem.avgWrQLen 25.30 # Average write queue length when enqueuing 295system.physmem.readRowHits 964137 # Number of row buffer hits during reads 296system.physmem.writeRowHits 1107294 # Number of row buffer hits during writes 297system.physmem.readRowHitRate 77.42 # Row buffer hit rate for reads 298system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes 299system.physmem.avgGap 18718619.94 # Average gap between requests 300system.physmem.pageHitRate 75.10 # Row buffer hit rate, read and write combined 301system.physmem_0.actEnergy 2629783800 # Energy for activate commands per rank (pJ) 302system.physmem_0.preEnergy 1434901875 # Energy for precharge commands per rank (pJ) 303system.physmem_0.readEnergy 4687519200 # Energy for read commands per rank (pJ) 304system.physmem_0.writeEnergy 4930197840 # Energy for write commands per rank (pJ) 305system.physmem_0.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) 306system.physmem_0.actBackEnergy 1305935149860 # Energy for active background per rank (pJ) 307system.physmem_0.preBackEnergy 29867098550250 # Energy for precharge background per rank (pJ) 308system.physmem_0.totalEnergy 34562709276105 # Total energy per rank (pJ) 309system.physmem_0.averagePower 668.682675 # Core power per rank (mW) 310system.physmem_0.memoryStateTime::IDLE 49685845654409 # Time in different power states 311system.physmem_0.memoryStateTime::REF 1725967880000 # Time in different power states 312system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 313system.physmem_0.memoryStateTime::ACT 275945978091 # Time in different power states 314system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 315system.physmem_1.actEnergy 2563233120 # Energy for activate commands per rank (pJ) 316system.physmem_1.preEnergy 1398589500 # Energy for precharge commands per rank (pJ) 317system.physmem_1.readEnergy 5026242000 # Energy for read commands per rank (pJ) 318system.physmem_1.writeEnergy 4873906080 # Energy for write commands per rank (pJ) 319system.physmem_1.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) 320system.physmem_1.actBackEnergy 1305717731910 # Energy for active background per rank (pJ) 321system.physmem_1.preBackEnergy 29867289276000 # Energy for precharge background per rank (pJ) 322system.physmem_1.totalEnergy 34562862151890 # Total energy per rank (pJ) 323system.physmem_1.averagePower 668.685632 # Core power per rank (mW) 324system.physmem_1.memoryStateTime::IDLE 49686132095770 # Time in different power states 325system.physmem_1.memoryStateTime::REF 1725967880000 # Time in different power states 326system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 327system.physmem_1.memoryStateTime::ACT 275664064230 # Time in different power states 328system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 329system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 330system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 331system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 332system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 333system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 334system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 335system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 336system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 337system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 338system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 346system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 347system.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 348system.bridge.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 349system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 350system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 351system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 352system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 353system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 354system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 355system.cpu.branchPred.lookups 264432116 # Number of BP lookups 356system.cpu.branchPred.condPredicted 184777930 # Number of conditional branches predicted 357system.cpu.branchPred.condIncorrect 12360480 # Number of conditional branches incorrect 358system.cpu.branchPred.BTBLookups 195121872 # Number of BTB lookups 359system.cpu.branchPred.BTBHits 131792442 # Number of BTB hits 360system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 361system.cpu.branchPred.BTBHitPct 67.543654 # BTB Hit Percentage 362system.cpu.branchPred.usedRAS 32005520 # Number of times the RAS was used to get a target. 363system.cpu.branchPred.RASInCorrect 2166164 # Number of incorrect RAS predictions. 364system.cpu.branchPred.indirectLookups 7202634 # Number of indirect predictor lookups. 365system.cpu.branchPred.indirectHits 5156312 # Number of indirect target hits. 366system.cpu.branchPred.indirectMisses 2046322 # Number of indirect misses. 367system.cpu.branchPredindirectMispredicted 848562 # Number of mispredicted indirect branches. 368system.cpu_clk_domain.clock 500 # Clock period in ticks 369system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 370system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 378system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 379system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 380system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 381system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 382system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 383system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 384system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 399system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 400system.cpu.dtb.walker.walks 584775 # Table walker walks requested 401system.cpu.dtb.walker.walksLong 584775 # Table walker walks initiated with long descriptors 402system.cpu.dtb.walker.walksLongTerminationLevel::Level2 23234 # Level at which table walker walks with long descriptors terminate 403system.cpu.dtb.walker.walksLongTerminationLevel::Level3 194431 # Level at which table walker walks with long descriptors terminate 404system.cpu.dtb.walker.walkWaitTime::samples 584775 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkWaitTime::0 584775 100.00% 100.00% # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkWaitTime::total 584775 # Table walker wait (enqueue to first request) latency 407system.cpu.dtb.walker.walkCompletionTime::samples 217665 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::mean 25428.727632 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::gmean 21638.505013 # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::stdev 16299.176879 # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::0-32767 136227 62.59% 62.59% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::32768-65535 78767 36.19% 98.77% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::65536-98303 1401 0.64% 99.42% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::98304-131071 854 0.39% 99.81% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::131072-163839 27 0.01% 99.82% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::163840-196607 133 0.06% 99.88% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::196608-229375 57 0.03% 99.91% # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::229376-262143 75 0.03% 99.94% # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::262144-294911 47 0.02% 99.96% # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::294912-327679 26 0.01% 99.98% # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency 422system.cpu.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency 423system.cpu.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency 424system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 425system.cpu.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 426system.cpu.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 427system.cpu.dtb.walker.walkCompletionTime::total 217665 # Table walker service (enqueue to completion) latency 428system.cpu.dtb.walker.walksPending::samples -10206296 # Table walker pending requests distribution 429system.cpu.dtb.walker.walksPending::0 -10206296 100.00% 100.00% # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::total -10206296 # Table walker pending requests distribution 431system.cpu.dtb.walker.walkPageSizes::4K 194432 89.33% 89.33% # Table walker page sizes translated 432system.cpu.dtb.walker.walkPageSizes::2M 23234 10.67% 100.00% # Table walker page sizes translated 433system.cpu.dtb.walker.walkPageSizes::total 217666 # Table walker page sizes translated 434system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 584775 # Table walker requests started/completed, data/inst 435system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 436system.cpu.dtb.walker.walkRequestOrigin_Requested::total 584775 # Table walker requests started/completed, data/inst 437system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 217666 # Table walker requests started/completed, data/inst 438system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Completed::total 217666 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin::total 802441 # Table walker requests started/completed, data/inst 441system.cpu.dtb.inst_hits 0 # ITB inst hits 442system.cpu.dtb.inst_misses 0 # ITB inst misses 443system.cpu.dtb.read_hits 184602893 # DTB read hits 444system.cpu.dtb.read_misses 481054 # DTB read misses 445system.cpu.dtb.write_hits 163948315 # DTB write hits 446system.cpu.dtb.write_misses 103721 # DTB write misses 447system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 448system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 449system.cpu.dtb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID 450system.cpu.dtb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID 451system.cpu.dtb.flush_entries 80755 # Number of entries that have been flushed from TLB 452system.cpu.dtb.align_faults 1436 # Number of TLB faults due to alignment restrictions 453system.cpu.dtb.prefetch_faults 15519 # Number of TLB faults due to prefetch 454system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 455system.cpu.dtb.perms_faults 23435 # Number of TLB faults due to permissions restrictions 456system.cpu.dtb.read_accesses 185083947 # DTB read accesses 457system.cpu.dtb.write_accesses 164052036 # DTB write accesses 458system.cpu.dtb.inst_accesses 0 # ITB inst accesses 459system.cpu.dtb.hits 348551208 # DTB hits 460system.cpu.dtb.misses 584775 # DTB misses 461system.cpu.dtb.accesses 349135983 # DTB accesses 462system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 463system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 472system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 473system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 474system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 475system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 476system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 477system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 478system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 479system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 480system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 481system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 482system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 483system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 484system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 485system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 486system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 487system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 488system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 489system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 490system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 491system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 492system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 493system.cpu.itb.walker.walks 136740 # Table walker walks requested 494system.cpu.itb.walker.walksLong 136740 # Table walker walks initiated with long descriptors 495system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate 496system.cpu.itb.walker.walksLongTerminationLevel::Level3 118526 # Level at which table walker walks with long descriptors terminate 497system.cpu.itb.walker.walkWaitTime::samples 136740 # Table walker wait (enqueue to first request) latency 498system.cpu.itb.walker.walkWaitTime::0 136740 100.00% 100.00% # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::total 136740 # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkCompletionTime::samples 119603 # Table walker service (enqueue to completion) latency 501system.cpu.itb.walker.walkCompletionTime::mean 27883.393393 # Table walker service (enqueue to completion) latency 502system.cpu.itb.walker.walkCompletionTime::gmean 23898.853743 # Table walker service (enqueue to completion) latency 503system.cpu.itb.walker.walkCompletionTime::stdev 18564.311346 # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walkCompletionTime::0-32767 67731 56.63% 56.63% # Table walker service (enqueue to completion) latency 505system.cpu.itb.walker.walkCompletionTime::32768-65535 48774 40.78% 97.41% # Table walker service (enqueue to completion) latency 506system.cpu.itb.walker.walkCompletionTime::65536-98303 1154 0.96% 98.37% # Table walker service (enqueue to completion) latency 507system.cpu.itb.walker.walkCompletionTime::98304-131071 1639 1.37% 99.74% # Table walker service (enqueue to completion) latency 508system.cpu.itb.walker.walkCompletionTime::131072-163839 37 0.03% 99.78% # Table walker service (enqueue to completion) latency 509system.cpu.itb.walker.walkCompletionTime::163840-196607 137 0.11% 99.89% # Table walker service (enqueue to completion) latency 510system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.93% # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walkCompletionTime::229376-262143 18 0.02% 99.94% # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::262144-294911 21 0.02% 99.96% # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::294912-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::327680-360447 18 0.02% 99.99% # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::360448-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::total 119603 # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walksPending::samples -10844796 # Table walker pending requests distribution 519system.cpu.itb.walker.walksPending::0 -10844796 100.00% 100.00% # Table walker pending requests distribution 520system.cpu.itb.walker.walksPending::total -10844796 # Table walker pending requests distribution 521system.cpu.itb.walker.walkPageSizes::4K 118526 99.10% 99.10% # Table walker page sizes translated 522system.cpu.itb.walker.walkPageSizes::2M 1077 0.90% 100.00% # Table walker page sizes translated 523system.cpu.itb.walker.walkPageSizes::total 119603 # Table walker page sizes translated 524system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 525system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136740 # Table walker requests started/completed, data/inst 526system.cpu.itb.walker.walkRequestOrigin_Requested::total 136740 # Table walker requests started/completed, data/inst 527system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 528system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119603 # Table walker requests started/completed, data/inst 529system.cpu.itb.walker.walkRequestOrigin_Completed::total 119603 # Table walker requests started/completed, data/inst 530system.cpu.itb.walker.walkRequestOrigin::total 256343 # Table walker requests started/completed, data/inst 531system.cpu.itb.inst_hits 457894474 # ITB inst hits 532system.cpu.itb.inst_misses 136740 # ITB inst misses 533system.cpu.itb.read_hits 0 # DTB read hits 534system.cpu.itb.read_misses 0 # DTB read misses 535system.cpu.itb.write_hits 0 # DTB write hits 536system.cpu.itb.write_misses 0 # DTB write misses 537system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 538system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 539system.cpu.itb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID 540system.cpu.itb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID 541system.cpu.itb.flush_entries 57885 # Number of entries that have been flushed from TLB 542system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 543system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 544system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 545system.cpu.itb.perms_faults 331252 # Number of TLB faults due to permissions restrictions 546system.cpu.itb.read_accesses 0 # DTB read accesses 547system.cpu.itb.write_accesses 0 # DTB write accesses 548system.cpu.itb.inst_accesses 458031214 # ITB inst accesses 549system.cpu.itb.hits 457894474 # DTB hits 550system.cpu.itb.misses 136740 # DTB misses 551system.cpu.itb.accesses 458031214 # DTB accesses 552system.cpu.numPwrStateTransitions 33262 # Number of power state transitions 553system.cpu.pwrStateClkGateDist::samples 16631 # Distribution of time spent in the clock gated state 554system.cpu.pwrStateClkGateDist::mean 3032078673.597498 # Distribution of time spent in the clock gated state 555system.cpu.pwrStateClkGateDist::stdev 59558384510.943253 # Distribution of time spent in the clock gated state 556system.cpu.pwrStateClkGateDist::underflows 7336 44.11% 44.11% # Distribution of time spent in the clock gated state 557system.cpu.pwrStateClkGateDist::1000-5e+10 9260 55.68% 99.79% # Distribution of time spent in the clock gated state 558system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 559system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 560system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 561system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 562system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 563system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 564system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state 570system.cpu.pwrStateClkGateDist::total 16631 # Distribution of time spent in the clock gated state 571system.cpu.pwrStateResidencyTicks::ON 1261264097400 # Cumulative time (in ticks) in various power states 572system.cpu.pwrStateResidencyTicks::CLK_GATED 50426500420600 # Cumulative time (in ticks) in various power states 573system.cpu.numCycles 2522582223 # number of cpu cycles simulated 574system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 576system.cpu.committedInsts 956884636 # Number of instructions committed 577system.cpu.committedOps 1124405089 # Number of ops (including micro ops) committed 578system.cpu.discardedOps 99545013 # Number of ops (including micro ops) which were discarded before commit 579system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching 580system.cpu.quiesceCycles 100854059486 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 581system.cpu.cpi 2.636245 # CPI: cycles per instruction 582system.cpu.ipc 0.379327 # IPC: instructions per cycle 583system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 584system.cpu.op_class_0::IntAlu 779381648 69.32% 69.32% # Class of committed instruction 585system.cpu.op_class_0::IntMult 2317785 0.21% 69.52% # Class of committed instruction 586system.cpu.op_class_0::IntDiv 99593 0.01% 69.53% # Class of committed instruction 587system.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction 588system.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction 589system.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction 590system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction 591system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction 592system.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction 593system.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction 594system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction 595system.cpu.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction 596system.cpu.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction 597system.cpu.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction 598system.cpu.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction 599system.cpu.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction 600system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction 601system.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction 602system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction 603system.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction 604system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction 605system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction 606system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction 607system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction 608system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction 609system.cpu.op_class_0::SimdFloatMisc 108729 0.01% 69.54% # Class of committed instruction 610system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction 611system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction 612system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction 613system.cpu.op_class_0::MemRead 179105650 15.93% 85.47% # Class of committed instruction 614system.cpu.op_class_0::MemWrite 163391641 14.53% 100.00% # Class of committed instruction 615system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 616system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 617system.cpu.op_class_0::total 1124405089 # Class of committed instruction 618system.cpu.kern.inst.arm 0 # number of arm instructions executed 619system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed 620system.cpu.tickCycles 1810679239 # Number of cycles that the object actually ticked 621system.cpu.idleCycles 711902984 # Total number of cycles that the object has spent stopped 622system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 623system.cpu.dcache.tags.replacements 11237287 # number of replacements 624system.cpu.dcache.tags.tagsinuse 511.957340 # Cycle average of tags in use 625system.cpu.dcache.tags.total_refs 332608189 # Total number of references to valid blocks. 626system.cpu.dcache.tags.sampled_refs 11237799 # Sample count of references to valid blocks. 627system.cpu.dcache.tags.avg_refs 29.597272 # Average number of references to valid blocks. 628system.cpu.dcache.tags.warmup_cycle 4326295500 # Cycle when the warmup percentage was hit. 629system.cpu.dcache.tags.occ_blocks::cpu.data 511.957340 # Average occupied blocks per requestor 630system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy 631system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy 632system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 633system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 634system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id 635system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 636system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 637system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 638system.cpu.dcache.tags.tag_accesses 1395920077 # Number of tag accesses 639system.cpu.dcache.tags.data_accesses 1395920077 # Number of data accesses 640system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 641system.cpu.dcache.ReadReq_hits::cpu.data 170244902 # number of ReadReq hits 642system.cpu.dcache.ReadReq_hits::total 170244902 # number of ReadReq hits 643system.cpu.dcache.WriteReq_hits::cpu.data 153016106 # number of WriteReq hits 644system.cpu.dcache.WriteReq_hits::total 153016106 # number of WriteReq hits 645system.cpu.dcache.SoftPFReq_hits::cpu.data 525044 # number of SoftPFReq hits 646system.cpu.dcache.SoftPFReq_hits::total 525044 # number of SoftPFReq hits 647system.cpu.dcache.WriteLineReq_hits::cpu.data 336678 # number of WriteLineReq hits 648system.cpu.dcache.WriteLineReq_hits::total 336678 # number of WriteLineReq hits 649system.cpu.dcache.LoadLockedReq_hits::cpu.data 4066137 # number of LoadLockedReq hits 650system.cpu.dcache.LoadLockedReq_hits::total 4066137 # number of LoadLockedReq hits 651system.cpu.dcache.StoreCondReq_hits::cpu.data 4385244 # number of StoreCondReq hits 652system.cpu.dcache.StoreCondReq_hits::total 4385244 # number of StoreCondReq hits 653system.cpu.dcache.demand_hits::cpu.data 323597686 # number of demand (read+write) hits 654system.cpu.dcache.demand_hits::total 323597686 # number of demand (read+write) hits 655system.cpu.dcache.overall_hits::cpu.data 324122730 # number of overall hits 656system.cpu.dcache.overall_hits::total 324122730 # number of overall hits 657system.cpu.dcache.ReadReq_misses::cpu.data 6163054 # number of ReadReq misses 658system.cpu.dcache.ReadReq_misses::total 6163054 # number of ReadReq misses 659system.cpu.dcache.WriteReq_misses::cpu.data 4362358 # number of WriteReq misses 660system.cpu.dcache.WriteReq_misses::total 4362358 # number of WriteReq misses 661system.cpu.dcache.SoftPFReq_misses::cpu.data 1504058 # number of SoftPFReq misses 662system.cpu.dcache.SoftPFReq_misses::total 1504058 # number of SoftPFReq misses 663system.cpu.dcache.WriteLineReq_misses::cpu.data 1246141 # number of WriteLineReq misses 664system.cpu.dcache.WriteLineReq_misses::total 1246141 # number of WriteLineReq misses 665system.cpu.dcache.LoadLockedReq_misses::cpu.data 320841 # number of LoadLockedReq misses 666system.cpu.dcache.LoadLockedReq_misses::total 320841 # number of LoadLockedReq misses 667system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 668system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 669system.cpu.dcache.demand_misses::cpu.data 11771553 # number of demand (read+write) misses 670system.cpu.dcache.demand_misses::total 11771553 # number of demand (read+write) misses 671system.cpu.dcache.overall_misses::cpu.data 13275611 # number of overall misses 672system.cpu.dcache.overall_misses::total 13275611 # number of overall misses 673system.cpu.dcache.ReadReq_miss_latency::cpu.data 101076172500 # number of ReadReq miss cycles 674system.cpu.dcache.ReadReq_miss_latency::total 101076172500 # number of ReadReq miss cycles 675system.cpu.dcache.WriteReq_miss_latency::cpu.data 157713428000 # number of WriteReq miss cycles 676system.cpu.dcache.WriteReq_miss_latency::total 157713428000 # number of WriteReq miss cycles 677system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27433825500 # number of WriteLineReq miss cycles 678system.cpu.dcache.WriteLineReq_miss_latency::total 27433825500 # number of WriteLineReq miss cycles 679system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4889648000 # number of LoadLockedReq miss cycles 680system.cpu.dcache.LoadLockedReq_miss_latency::total 4889648000 # number of LoadLockedReq miss cycles 681system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles 682system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles 683system.cpu.dcache.demand_miss_latency::cpu.data 286223426000 # number of demand (read+write) miss cycles 684system.cpu.dcache.demand_miss_latency::total 286223426000 # number of demand (read+write) miss cycles 685system.cpu.dcache.overall_miss_latency::cpu.data 286223426000 # number of overall miss cycles 686system.cpu.dcache.overall_miss_latency::total 286223426000 # number of overall miss cycles 687system.cpu.dcache.ReadReq_accesses::cpu.data 176407956 # number of ReadReq accesses(hits+misses) 688system.cpu.dcache.ReadReq_accesses::total 176407956 # number of ReadReq accesses(hits+misses) 689system.cpu.dcache.WriteReq_accesses::cpu.data 157378464 # number of WriteReq accesses(hits+misses) 690system.cpu.dcache.WriteReq_accesses::total 157378464 # number of WriteReq accesses(hits+misses) 691system.cpu.dcache.SoftPFReq_accesses::cpu.data 2029102 # number of SoftPFReq accesses(hits+misses) 692system.cpu.dcache.SoftPFReq_accesses::total 2029102 # number of SoftPFReq accesses(hits+misses) 693system.cpu.dcache.WriteLineReq_accesses::cpu.data 1582819 # number of WriteLineReq accesses(hits+misses) 694system.cpu.dcache.WriteLineReq_accesses::total 1582819 # number of WriteLineReq accesses(hits+misses) 695system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4386978 # number of LoadLockedReq accesses(hits+misses) 696system.cpu.dcache.LoadLockedReq_accesses::total 4386978 # number of LoadLockedReq accesses(hits+misses) 697system.cpu.dcache.StoreCondReq_accesses::cpu.data 4385245 # number of StoreCondReq accesses(hits+misses) 698system.cpu.dcache.StoreCondReq_accesses::total 4385245 # number of StoreCondReq accesses(hits+misses) 699system.cpu.dcache.demand_accesses::cpu.data 335369239 # number of demand (read+write) accesses 700system.cpu.dcache.demand_accesses::total 335369239 # number of demand (read+write) accesses 701system.cpu.dcache.overall_accesses::cpu.data 337398341 # number of overall (read+write) accesses 702system.cpu.dcache.overall_accesses::total 337398341 # number of overall (read+write) accesses 703system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034936 # miss rate for ReadReq accesses 704system.cpu.dcache.ReadReq_miss_rate::total 0.034936 # miss rate for ReadReq accesses 705system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027719 # miss rate for WriteReq accesses 706system.cpu.dcache.WriteReq_miss_rate::total 0.027719 # miss rate for WriteReq accesses 707system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.741243 # miss rate for SoftPFReq accesses 708system.cpu.dcache.SoftPFReq_miss_rate::total 0.741243 # miss rate for SoftPFReq accesses 709system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787292 # miss rate for WriteLineReq accesses 710system.cpu.dcache.WriteLineReq_miss_rate::total 0.787292 # miss rate for WriteLineReq accesses 711system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073135 # miss rate for LoadLockedReq accesses 712system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073135 # miss rate for LoadLockedReq accesses 713system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 714system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 715system.cpu.dcache.demand_miss_rate::cpu.data 0.035100 # miss rate for demand accesses 716system.cpu.dcache.demand_miss_rate::total 0.035100 # miss rate for demand accesses 717system.cpu.dcache.overall_miss_rate::cpu.data 0.039347 # miss rate for overall accesses 718system.cpu.dcache.overall_miss_rate::total 0.039347 # miss rate for overall accesses 719system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16400.338615 # average ReadReq miss latency 720system.cpu.dcache.ReadReq_avg_miss_latency::total 16400.338615 # average ReadReq miss latency 721system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36153.251980 # average WriteReq miss latency 722system.cpu.dcache.WriteReq_avg_miss_latency::total 36153.251980 # average WriteReq miss latency 723system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22015.025186 # average WriteLineReq miss latency 724system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22015.025186 # average WriteLineReq miss latency 725system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15240.097120 # average LoadLockedReq miss latency 726system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15240.097120 # average LoadLockedReq miss latency 727system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 728system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency 729system.cpu.dcache.demand_avg_miss_latency::cpu.data 24314.839852 # average overall miss latency 730system.cpu.dcache.demand_avg_miss_latency::total 24314.839852 # average overall miss latency 731system.cpu.dcache.overall_avg_miss_latency::cpu.data 21560.094372 # average overall miss latency 732system.cpu.dcache.overall_avg_miss_latency::total 21560.094372 # average overall miss latency 733system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 734system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 735system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 736system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 737system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 738system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 739system.cpu.dcache.writebacks::writebacks 8619796 # number of writebacks 740system.cpu.dcache.writebacks::total 8619796 # number of writebacks 741system.cpu.dcache.ReadReq_mshr_hits::cpu.data 315342 # number of ReadReq MSHR hits 742system.cpu.dcache.ReadReq_mshr_hits::total 315342 # number of ReadReq MSHR hits 743system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1930607 # number of WriteReq MSHR hits 744system.cpu.dcache.WriteReq_mshr_hits::total 1930607 # number of WriteReq MSHR hits 745system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 154 # number of WriteLineReq MSHR hits 746system.cpu.dcache.WriteLineReq_mshr_hits::total 154 # number of WriteLineReq MSHR hits 747system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70929 # number of LoadLockedReq MSHR hits 748system.cpu.dcache.LoadLockedReq_mshr_hits::total 70929 # number of LoadLockedReq MSHR hits 749system.cpu.dcache.demand_mshr_hits::cpu.data 2246103 # number of demand (read+write) MSHR hits 750system.cpu.dcache.demand_mshr_hits::total 2246103 # number of demand (read+write) MSHR hits 751system.cpu.dcache.overall_mshr_hits::cpu.data 2246103 # number of overall MSHR hits 752system.cpu.dcache.overall_mshr_hits::total 2246103 # number of overall MSHR hits 753system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5847712 # number of ReadReq MSHR misses 754system.cpu.dcache.ReadReq_mshr_misses::total 5847712 # number of ReadReq MSHR misses 755system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2431751 # number of WriteReq MSHR misses 756system.cpu.dcache.WriteReq_mshr_misses::total 2431751 # number of WriteReq MSHR misses 757system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1496531 # number of SoftPFReq MSHR misses 758system.cpu.dcache.SoftPFReq_mshr_misses::total 1496531 # number of SoftPFReq MSHR misses 759system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1245987 # number of WriteLineReq MSHR misses 760system.cpu.dcache.WriteLineReq_mshr_misses::total 1245987 # number of WriteLineReq MSHR misses 761system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 249912 # number of LoadLockedReq MSHR misses 762system.cpu.dcache.LoadLockedReq_mshr_misses::total 249912 # number of LoadLockedReq MSHR misses 763system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 764system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 765system.cpu.dcache.demand_mshr_misses::cpu.data 9525450 # number of demand (read+write) MSHR misses 766system.cpu.dcache.demand_mshr_misses::total 9525450 # number of demand (read+write) MSHR misses 767system.cpu.dcache.overall_mshr_misses::cpu.data 11021981 # number of overall MSHR misses 768system.cpu.dcache.overall_mshr_misses::total 11021981 # number of overall MSHR misses 769system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33698 # number of ReadReq MSHR uncacheable 770system.cpu.dcache.ReadReq_mshr_uncacheable::total 33698 # number of ReadReq MSHR uncacheable 771system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 772system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 773system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67405 # number of overall MSHR uncacheable misses 774system.cpu.dcache.overall_mshr_uncacheable_misses::total 67405 # number of overall MSHR uncacheable misses 775system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 89040002500 # number of ReadReq MSHR miss cycles 776system.cpu.dcache.ReadReq_mshr_miss_latency::total 89040002500 # number of ReadReq MSHR miss cycles 777system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82314078000 # number of WriteReq MSHR miss cycles 778system.cpu.dcache.WriteReq_mshr_miss_latency::total 82314078000 # number of WriteReq MSHR miss cycles 779system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 24215113000 # number of SoftPFReq MSHR miss cycles 780system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 24215113000 # number of SoftPFReq MSHR miss cycles 781system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26183606500 # number of WriteLineReq MSHR miss cycles 782system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26183606500 # number of WriteLineReq MSHR miss cycles 783system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3424677000 # number of LoadLockedReq MSHR miss cycles 784system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3424677000 # number of LoadLockedReq MSHR miss cycles 785system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles 786system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles 787system.cpu.dcache.demand_mshr_miss_latency::cpu.data 197537687000 # number of demand (read+write) MSHR miss cycles 788system.cpu.dcache.demand_mshr_miss_latency::total 197537687000 # number of demand (read+write) MSHR miss cycles 789system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221752800000 # number of overall MSHR miss cycles 790system.cpu.dcache.overall_mshr_miss_latency::total 221752800000 # number of overall MSHR miss cycles 791system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231251500 # number of ReadReq MSHR uncacheable cycles 792system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231251500 # number of ReadReq MSHR uncacheable cycles 793system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231251500 # number of overall MSHR uncacheable cycles 794system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231251500 # number of overall MSHR uncacheable cycles 795system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033149 # mshr miss rate for ReadReq accesses 796system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033149 # mshr miss rate for ReadReq accesses 797system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015452 # mshr miss rate for WriteReq accesses 798system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015452 # mshr miss rate for WriteReq accesses 799system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.737534 # mshr miss rate for SoftPFReq accesses 800system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.737534 # mshr miss rate for SoftPFReq accesses 801system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787195 # mshr miss rate for WriteLineReq accesses 802system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787195 # mshr miss rate for WriteLineReq accesses 803system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056967 # mshr miss rate for LoadLockedReq accesses 804system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056967 # mshr miss rate for LoadLockedReq accesses 805system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 806system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 807system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028403 # mshr miss rate for demand accesses 808system.cpu.dcache.demand_mshr_miss_rate::total 0.028403 # mshr miss rate for demand accesses 809system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032668 # mshr miss rate for overall accesses 810system.cpu.dcache.overall_mshr_miss_rate::total 0.032668 # mshr miss rate for overall accesses 811system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15226.468489 # average ReadReq mshr miss latency 812system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15226.468489 # average ReadReq mshr miss latency 813system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33849.714876 # average WriteReq mshr miss latency 814system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33849.714876 # average WriteReq mshr miss latency 815system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.829532 # average SoftPFReq mshr miss latency 816system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.829532 # average SoftPFReq mshr miss latency 817system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21014.349668 # average WriteLineReq mshr miss latency 818system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21014.349668 # average WriteLineReq mshr miss latency 819system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13703.531643 # average LoadLockedReq mshr miss latency 820system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13703.531643 # average LoadLockedReq mshr miss latency 821system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 822system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20737.885034 # average overall mshr miss latency 824system.cpu.dcache.demand_avg_mshr_miss_latency::total 20737.885034 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20119.141922 # average overall mshr miss latency 826system.cpu.dcache.overall_avg_mshr_miss_latency::total 20119.141922 # average overall mshr miss latency 827system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184914.579500 # average ReadReq mshr uncacheable latency 828system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184914.579500 # average ReadReq mshr uncacheable latency 829system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92444.944737 # average overall mshr uncacheable latency 830system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92444.944737 # average overall mshr uncacheable latency 831system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 832system.cpu.icache.tags.replacements 24740790 # number of replacements 833system.cpu.icache.tags.tagsinuse 511.930482 # Cycle average of tags in use 834system.cpu.icache.tags.total_refs 432810859 # Total number of references to valid blocks. 835system.cpu.icache.tags.sampled_refs 24741302 # Sample count of references to valid blocks. 836system.cpu.icache.tags.avg_refs 17.493455 # Average number of references to valid blocks. 837system.cpu.icache.tags.warmup_cycle 20587192500 # Cycle when the warmup percentage was hit. 838system.cpu.icache.tags.occ_blocks::cpu.inst 511.930482 # Average occupied blocks per requestor 839system.cpu.icache.tags.occ_percent::cpu.inst 0.999864 # Average percentage of cache occupancy 840system.cpu.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy 841system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 842system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 843system.cpu.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 844system.cpu.icache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id 845system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 846system.cpu.icache.tags.tag_accesses 482293482 # Number of tag accesses 847system.cpu.icache.tags.data_accesses 482293482 # Number of data accesses 848system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 849system.cpu.icache.ReadReq_hits::cpu.inst 432810859 # number of ReadReq hits 850system.cpu.icache.ReadReq_hits::total 432810859 # number of ReadReq hits 851system.cpu.icache.demand_hits::cpu.inst 432810859 # number of demand (read+write) hits 852system.cpu.icache.demand_hits::total 432810859 # number of demand (read+write) hits 853system.cpu.icache.overall_hits::cpu.inst 432810859 # number of overall hits 854system.cpu.icache.overall_hits::total 432810859 # number of overall hits 855system.cpu.icache.ReadReq_misses::cpu.inst 24741312 # number of ReadReq misses 856system.cpu.icache.ReadReq_misses::total 24741312 # number of ReadReq misses 857system.cpu.icache.demand_misses::cpu.inst 24741312 # number of demand (read+write) misses 858system.cpu.icache.demand_misses::total 24741312 # number of demand (read+write) misses 859system.cpu.icache.overall_misses::cpu.inst 24741312 # number of overall misses 860system.cpu.icache.overall_misses::total 24741312 # number of overall misses 861system.cpu.icache.ReadReq_miss_latency::cpu.inst 329592002500 # number of ReadReq miss cycles 862system.cpu.icache.ReadReq_miss_latency::total 329592002500 # number of ReadReq miss cycles 863system.cpu.icache.demand_miss_latency::cpu.inst 329592002500 # number of demand (read+write) miss cycles 864system.cpu.icache.demand_miss_latency::total 329592002500 # number of demand (read+write) miss cycles 865system.cpu.icache.overall_miss_latency::cpu.inst 329592002500 # number of overall miss cycles 866system.cpu.icache.overall_miss_latency::total 329592002500 # number of overall miss cycles 867system.cpu.icache.ReadReq_accesses::cpu.inst 457552171 # number of ReadReq accesses(hits+misses) 868system.cpu.icache.ReadReq_accesses::total 457552171 # number of ReadReq accesses(hits+misses) 869system.cpu.icache.demand_accesses::cpu.inst 457552171 # number of demand (read+write) accesses 870system.cpu.icache.demand_accesses::total 457552171 # number of demand (read+write) accesses 871system.cpu.icache.overall_accesses::cpu.inst 457552171 # number of overall (read+write) accesses 872system.cpu.icache.overall_accesses::total 457552171 # number of overall (read+write) accesses 873system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054073 # miss rate for ReadReq accesses 874system.cpu.icache.ReadReq_miss_rate::total 0.054073 # miss rate for ReadReq accesses 875system.cpu.icache.demand_miss_rate::cpu.inst 0.054073 # miss rate for demand accesses 876system.cpu.icache.demand_miss_rate::total 0.054073 # miss rate for demand accesses 877system.cpu.icache.overall_miss_rate::cpu.inst 0.054073 # miss rate for overall accesses 878system.cpu.icache.overall_miss_rate::total 0.054073 # miss rate for overall accesses 879system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13321.524845 # average ReadReq miss latency 880system.cpu.icache.ReadReq_avg_miss_latency::total 13321.524845 # average ReadReq miss latency 881system.cpu.icache.demand_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency 882system.cpu.icache.demand_avg_miss_latency::total 13321.524845 # average overall miss latency 883system.cpu.icache.overall_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency 884system.cpu.icache.overall_avg_miss_latency::total 13321.524845 # average overall miss latency 885system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 886system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 888system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 890system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 891system.cpu.icache.writebacks::writebacks 24740790 # number of writebacks 892system.cpu.icache.writebacks::total 24740790 # number of writebacks 893system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24741312 # number of ReadReq MSHR misses 894system.cpu.icache.ReadReq_mshr_misses::total 24741312 # number of ReadReq MSHR misses 895system.cpu.icache.demand_mshr_misses::cpu.inst 24741312 # number of demand (read+write) MSHR misses 896system.cpu.icache.demand_mshr_misses::total 24741312 # number of demand (read+write) MSHR misses 897system.cpu.icache.overall_mshr_misses::cpu.inst 24741312 # number of overall MSHR misses 898system.cpu.icache.overall_mshr_misses::total 24741312 # number of overall MSHR misses 899system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52293 # number of ReadReq MSHR uncacheable 900system.cpu.icache.ReadReq_mshr_uncacheable::total 52293 # number of ReadReq MSHR uncacheable 901system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52293 # number of overall MSHR uncacheable misses 902system.cpu.icache.overall_mshr_uncacheable_misses::total 52293 # number of overall MSHR uncacheable misses 903system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304850691500 # number of ReadReq MSHR miss cycles 904system.cpu.icache.ReadReq_mshr_miss_latency::total 304850691500 # number of ReadReq MSHR miss cycles 905system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304850691500 # number of demand (read+write) MSHR miss cycles 906system.cpu.icache.demand_mshr_miss_latency::total 304850691500 # number of demand (read+write) MSHR miss cycles 907system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304850691500 # number of overall MSHR miss cycles 908system.cpu.icache.overall_mshr_miss_latency::total 304850691500 # number of overall MSHR miss cycles 909system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4087122500 # number of ReadReq MSHR uncacheable cycles 910system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4087122500 # number of ReadReq MSHR uncacheable cycles 911system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4087122500 # number of overall MSHR uncacheable cycles 912system.cpu.icache.overall_mshr_uncacheable_latency::total 4087122500 # number of overall MSHR uncacheable cycles 913system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054073 # mshr miss rate for ReadReq accesses 914system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054073 # mshr miss rate for ReadReq accesses 915system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054073 # mshr miss rate for demand accesses 916system.cpu.icache.demand_mshr_miss_rate::total 0.054073 # mshr miss rate for demand accesses 917system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054073 # mshr miss rate for overall accesses 918system.cpu.icache.overall_mshr_miss_rate::total 0.054073 # mshr miss rate for overall accesses 919system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12321.524885 # average ReadReq mshr miss latency 920system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12321.524885 # average ReadReq mshr miss latency 921system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12321.524885 # average overall mshr miss latency 922system.cpu.icache.demand_avg_mshr_miss_latency::total 12321.524885 # average overall mshr miss latency 923system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12321.524885 # average overall mshr miss latency 924system.cpu.icache.overall_avg_mshr_miss_latency::total 12321.524885 # average overall mshr miss latency 925system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 78158.118677 # average ReadReq mshr uncacheable latency 926system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 78158.118677 # average ReadReq mshr uncacheable latency 927system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 78158.118677 # average overall mshr uncacheable latency 928system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 78158.118677 # average overall mshr uncacheable latency 929system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 930system.cpu.l2cache.tags.replacements 1647378 # number of replacements 931system.cpu.l2cache.tags.tagsinuse 65415.989966 # Cycle average of tags in use 932system.cpu.l2cache.tags.total_refs 70152651 # Total number of references to valid blocks. 933system.cpu.l2cache.tags.sampled_refs 1710758 # Sample count of references to valid blocks. 934system.cpu.l2cache.tags.avg_refs 41.006765 # Average number of references to valid blocks. 935system.cpu.l2cache.tags.warmup_cycle 5897369000 # Cycle when the warmup percentage was hit. 936system.cpu.l2cache.tags.occ_blocks::writebacks 9082.397486 # Average occupied blocks per requestor 937system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 468.031396 # Average occupied blocks per requestor 938system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 465.228429 # Average occupied blocks per requestor 939system.cpu.l2cache.tags.occ_blocks::cpu.inst 8079.882193 # Average occupied blocks per requestor 940system.cpu.l2cache.tags.occ_blocks::cpu.data 47320.450462 # Average occupied blocks per requestor 941system.cpu.l2cache.tags.occ_percent::writebacks 0.138586 # Average percentage of cache occupancy 942system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007142 # Average percentage of cache occupancy 943system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007099 # Average percentage of cache occupancy 944system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123289 # Average percentage of cache occupancy 945system.cpu.l2cache.tags.occ_percent::cpu.data 0.722053 # Average percentage of cache occupancy 946system.cpu.l2cache.tags.occ_percent::total 0.998169 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id 948system.cpu.l2cache.tags.occ_task_id_blocks::1024 63076 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id 951system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 952system.cpu.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5993 # Occupied blocks per task id 955system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55903 # Occupied blocks per task id 956system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id 957system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962463 # Percentage of cache occupancy per task id 958system.cpu.l2cache.tags.tag_accesses 587932179 # Number of tag accesses 959system.cpu.l2cache.tags.data_accesses 587932179 # Number of data accesses 960system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 961system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 928594 # number of ReadReq hits 962system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 259345 # number of ReadReq hits 963system.cpu.l2cache.ReadReq_hits::total 1187939 # number of ReadReq hits 964system.cpu.l2cache.WritebackDirty_hits::writebacks 8619796 # number of WritebackDirty hits 965system.cpu.l2cache.WritebackDirty_hits::total 8619796 # number of WritebackDirty hits 966system.cpu.l2cache.WritebackClean_hits::writebacks 24737128 # number of WritebackClean hits 967system.cpu.l2cache.WritebackClean_hits::total 24737128 # number of WritebackClean hits 968system.cpu.l2cache.UpgradeReq_hits::cpu.data 30047 # number of UpgradeReq hits 969system.cpu.l2cache.UpgradeReq_hits::total 30047 # number of UpgradeReq hits 970system.cpu.l2cache.ReadExReq_hits::cpu.data 1665980 # number of ReadExReq hits 971system.cpu.l2cache.ReadExReq_hits::total 1665980 # number of ReadExReq hits 972system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24634240 # number of ReadCleanReq hits 973system.cpu.l2cache.ReadCleanReq_hits::total 24634240 # number of ReadCleanReq hits 974system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7256699 # number of ReadSharedReq hits 975system.cpu.l2cache.ReadSharedReq_hits::total 7256699 # number of ReadSharedReq hits 976system.cpu.l2cache.InvalidateReq_hits::cpu.data 698207 # number of InvalidateReq hits 977system.cpu.l2cache.InvalidateReq_hits::total 698207 # number of InvalidateReq hits 978system.cpu.l2cache.demand_hits::cpu.dtb.walker 928594 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::cpu.itb.walker 259345 # number of demand (read+write) hits 980system.cpu.l2cache.demand_hits::cpu.inst 24634240 # number of demand (read+write) hits 981system.cpu.l2cache.demand_hits::cpu.data 8922679 # number of demand (read+write) hits 982system.cpu.l2cache.demand_hits::total 34744858 # number of demand (read+write) hits 983system.cpu.l2cache.overall_hits::cpu.dtb.walker 928594 # number of overall hits 984system.cpu.l2cache.overall_hits::cpu.itb.walker 259345 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.inst 24634240 # number of overall hits 986system.cpu.l2cache.overall_hits::cpu.data 8922679 # number of overall hits 987system.cpu.l2cache.overall_hits::total 34744858 # number of overall hits 988system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6617 # number of ReadReq misses 989system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5620 # number of ReadReq misses 990system.cpu.l2cache.ReadReq_misses::total 12237 # number of ReadReq misses 991system.cpu.l2cache.UpgradeReq_misses::cpu.data 4025 # number of UpgradeReq misses 992system.cpu.l2cache.UpgradeReq_misses::total 4025 # number of UpgradeReq misses 993system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 994system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 995system.cpu.l2cache.ReadExReq_misses::cpu.data 731868 # number of ReadExReq misses 996system.cpu.l2cache.ReadExReq_misses::total 731868 # number of ReadExReq misses 997system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107071 # number of ReadCleanReq misses 998system.cpu.l2cache.ReadCleanReq_misses::total 107071 # number of ReadCleanReq misses 999system.cpu.l2cache.ReadSharedReq_misses::cpu.data 337287 # number of ReadSharedReq misses 1000system.cpu.l2cache.ReadSharedReq_misses::total 337287 # number of ReadSharedReq misses 1001system.cpu.l2cache.InvalidateReq_misses::cpu.data 547780 # number of InvalidateReq misses 1002system.cpu.l2cache.InvalidateReq_misses::total 547780 # number of InvalidateReq misses 1003system.cpu.l2cache.demand_misses::cpu.dtb.walker 6617 # number of demand (read+write) misses 1004system.cpu.l2cache.demand_misses::cpu.itb.walker 5620 # number of demand (read+write) misses 1005system.cpu.l2cache.demand_misses::cpu.inst 107071 # number of demand (read+write) misses 1006system.cpu.l2cache.demand_misses::cpu.data 1069155 # number of demand (read+write) misses 1007system.cpu.l2cache.demand_misses::total 1188463 # number of demand (read+write) misses 1008system.cpu.l2cache.overall_misses::cpu.dtb.walker 6617 # number of overall misses 1009system.cpu.l2cache.overall_misses::cpu.itb.walker 5620 # number of overall misses 1010system.cpu.l2cache.overall_misses::cpu.inst 107071 # number of overall misses 1011system.cpu.l2cache.overall_misses::cpu.data 1069155 # number of overall misses 1012system.cpu.l2cache.overall_misses::total 1188463 # number of overall misses 1013system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 582961000 # number of ReadReq miss cycles 1014system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 496565500 # number of ReadReq miss cycles 1015system.cpu.l2cache.ReadReq_miss_latency::total 1079526500 # number of ReadReq miss cycles 1016system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72338500 # number of UpgradeReq miss cycles 1017system.cpu.l2cache.UpgradeReq_miss_latency::total 72338500 # number of UpgradeReq miss cycles 1018system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles 1019system.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles 1020system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 60704703500 # number of ReadExReq miss cycles 1021system.cpu.l2cache.ReadExReq_miss_latency::total 60704703500 # number of ReadExReq miss cycles 1022system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8853700500 # number of ReadCleanReq miss cycles 1023system.cpu.l2cache.ReadCleanReq_miss_latency::total 8853700500 # number of ReadCleanReq miss cycles 1024system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 28854909000 # number of ReadSharedReq miss cycles 1025system.cpu.l2cache.ReadSharedReq_miss_latency::total 28854909000 # number of ReadSharedReq miss cycles 1026system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 1874000 # number of InvalidateReq miss cycles 1027system.cpu.l2cache.InvalidateReq_miss_latency::total 1874000 # number of InvalidateReq miss cycles 1028system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 582961000 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 496565500 # number of demand (read+write) miss cycles 1030system.cpu.l2cache.demand_miss_latency::cpu.inst 8853700500 # number of demand (read+write) miss cycles 1031system.cpu.l2cache.demand_miss_latency::cpu.data 89559612500 # number of demand (read+write) miss cycles 1032system.cpu.l2cache.demand_miss_latency::total 99492839500 # number of demand (read+write) miss cycles 1033system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 582961000 # number of overall miss cycles 1034system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 496565500 # number of overall miss cycles 1035system.cpu.l2cache.overall_miss_latency::cpu.inst 8853700500 # number of overall miss cycles 1036system.cpu.l2cache.overall_miss_latency::cpu.data 89559612500 # number of overall miss cycles 1037system.cpu.l2cache.overall_miss_latency::total 99492839500 # number of overall miss cycles 1038system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 935211 # number of ReadReq accesses(hits+misses) 1039system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 264965 # number of ReadReq accesses(hits+misses) 1040system.cpu.l2cache.ReadReq_accesses::total 1200176 # number of ReadReq accesses(hits+misses) 1041system.cpu.l2cache.WritebackDirty_accesses::writebacks 8619796 # number of WritebackDirty accesses(hits+misses) 1042system.cpu.l2cache.WritebackDirty_accesses::total 8619796 # number of WritebackDirty accesses(hits+misses) 1043system.cpu.l2cache.WritebackClean_accesses::writebacks 24737128 # number of WritebackClean accesses(hits+misses) 1044system.cpu.l2cache.WritebackClean_accesses::total 24737128 # number of WritebackClean accesses(hits+misses) 1045system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34072 # number of UpgradeReq accesses(hits+misses) 1046system.cpu.l2cache.UpgradeReq_accesses::total 34072 # number of UpgradeReq accesses(hits+misses) 1047system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1048system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1049system.cpu.l2cache.ReadExReq_accesses::cpu.data 2397848 # number of ReadExReq accesses(hits+misses) 1050system.cpu.l2cache.ReadExReq_accesses::total 2397848 # number of ReadExReq accesses(hits+misses) 1051system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24741311 # number of ReadCleanReq accesses(hits+misses) 1052system.cpu.l2cache.ReadCleanReq_accesses::total 24741311 # number of ReadCleanReq accesses(hits+misses) 1053system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7593986 # number of ReadSharedReq accesses(hits+misses) 1054system.cpu.l2cache.ReadSharedReq_accesses::total 7593986 # number of ReadSharedReq accesses(hits+misses) 1055system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1245987 # number of InvalidateReq accesses(hits+misses) 1056system.cpu.l2cache.InvalidateReq_accesses::total 1245987 # number of InvalidateReq accesses(hits+misses) 1057system.cpu.l2cache.demand_accesses::cpu.dtb.walker 935211 # number of demand (read+write) accesses 1058system.cpu.l2cache.demand_accesses::cpu.itb.walker 264965 # number of demand (read+write) accesses 1059system.cpu.l2cache.demand_accesses::cpu.inst 24741311 # number of demand (read+write) accesses 1060system.cpu.l2cache.demand_accesses::cpu.data 9991834 # number of demand (read+write) accesses 1061system.cpu.l2cache.demand_accesses::total 35933321 # number of demand (read+write) accesses 1062system.cpu.l2cache.overall_accesses::cpu.dtb.walker 935211 # number of overall (read+write) accesses 1063system.cpu.l2cache.overall_accesses::cpu.itb.walker 264965 # number of overall (read+write) accesses 1064system.cpu.l2cache.overall_accesses::cpu.inst 24741311 # number of overall (read+write) accesses 1065system.cpu.l2cache.overall_accesses::cpu.data 9991834 # number of overall (read+write) accesses 1066system.cpu.l2cache.overall_accesses::total 35933321 # number of overall (read+write) accesses 1067system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007075 # miss rate for ReadReq accesses 1068system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.021210 # miss rate for ReadReq accesses 1069system.cpu.l2cache.ReadReq_miss_rate::total 0.010196 # miss rate for ReadReq accesses 1070system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.118132 # miss rate for UpgradeReq accesses 1071system.cpu.l2cache.UpgradeReq_miss_rate::total 0.118132 # miss rate for UpgradeReq accesses 1072system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1073system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1074system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.305219 # miss rate for ReadExReq accesses 1075system.cpu.l2cache.ReadExReq_miss_rate::total 0.305219 # miss rate for ReadExReq accesses 1076system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004328 # miss rate for ReadCleanReq accesses 1077system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004328 # miss rate for ReadCleanReq accesses 1078system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044415 # miss rate for ReadSharedReq accesses 1079system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044415 # miss rate for ReadSharedReq accesses 1080system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.439635 # miss rate for InvalidateReq accesses 1081system.cpu.l2cache.InvalidateReq_miss_rate::total 0.439635 # miss rate for InvalidateReq accesses 1082system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007075 # miss rate for demand accesses 1083system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.021210 # miss rate for demand accesses 1084system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004328 # miss rate for demand accesses 1085system.cpu.l2cache.demand_miss_rate::cpu.data 0.107003 # miss rate for demand accesses 1086system.cpu.l2cache.demand_miss_rate::total 0.033074 # miss rate for demand accesses 1087system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007075 # miss rate for overall accesses 1088system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.021210 # miss rate for overall accesses 1089system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004328 # miss rate for overall accesses 1090system.cpu.l2cache.overall_miss_rate::cpu.data 0.107003 # miss rate for overall accesses 1091system.cpu.l2cache.overall_miss_rate::total 0.033074 # miss rate for overall accesses 1092system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88100.498715 # average ReadReq miss latency 1093system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88356.850534 # average ReadReq miss latency 1094system.cpu.l2cache.ReadReq_avg_miss_latency::total 88218.231593 # average ReadReq miss latency 1095system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17972.298137 # average UpgradeReq miss latency 1096system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17972.298137 # average UpgradeReq miss latency 1097system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 1098system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency 1099system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82944.880088 # average ReadExReq miss latency 1100system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82944.880088 # average ReadExReq miss latency 1101system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82689.995424 # average ReadCleanReq miss latency 1102system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82689.995424 # average ReadCleanReq miss latency 1103system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85550.018234 # average ReadSharedReq miss latency 1104system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85550.018234 # average ReadSharedReq miss latency 1105system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 3.421081 # average InvalidateReq miss latency 1106system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 3.421081 # average InvalidateReq miss latency 1107system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88100.498715 # average overall miss latency 1108system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88356.850534 # average overall miss latency 1109system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82689.995424 # average overall miss latency 1110system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83766.724656 # average overall miss latency 1111system.cpu.l2cache.demand_avg_miss_latency::total 83715.554881 # average overall miss latency 1112system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88100.498715 # average overall miss latency 1113system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88356.850534 # average overall miss latency 1114system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82689.995424 # average overall miss latency 1115system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83766.724656 # average overall miss latency 1116system.cpu.l2cache.overall_avg_miss_latency::total 83715.554881 # average overall miss latency 1117system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1118system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1119system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1120system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1121system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1122system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1123system.cpu.l2cache.writebacks::writebacks 1406063 # number of writebacks 1124system.cpu.l2cache.writebacks::total 1406063 # number of writebacks 1125system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1126system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1127system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1128system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1129system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1130system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1131system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 1132system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1133system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1134system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1135system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6617 # number of ReadReq MSHR misses 1136system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5620 # number of ReadReq MSHR misses 1137system.cpu.l2cache.ReadReq_mshr_misses::total 12237 # number of ReadReq MSHR misses 1138system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1139system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses 1140system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4025 # number of UpgradeReq MSHR misses 1141system.cpu.l2cache.UpgradeReq_mshr_misses::total 4025 # number of UpgradeReq MSHR misses 1142system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1143system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1144system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 731868 # number of ReadExReq MSHR misses 1145system.cpu.l2cache.ReadExReq_mshr_misses::total 731868 # number of ReadExReq MSHR misses 1146system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107068 # number of ReadCleanReq MSHR misses 1147system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107068 # number of ReadCleanReq MSHR misses 1148system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 337266 # number of ReadSharedReq MSHR misses 1149system.cpu.l2cache.ReadSharedReq_mshr_misses::total 337266 # number of ReadSharedReq MSHR misses 1150system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 547780 # number of InvalidateReq MSHR misses 1151system.cpu.l2cache.InvalidateReq_mshr_misses::total 547780 # number of InvalidateReq MSHR misses 1152system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6617 # number of demand (read+write) MSHR misses 1153system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5620 # number of demand (read+write) MSHR misses 1154system.cpu.l2cache.demand_mshr_misses::cpu.inst 107068 # number of demand (read+write) MSHR misses 1155system.cpu.l2cache.demand_mshr_misses::cpu.data 1069134 # number of demand (read+write) MSHR misses 1156system.cpu.l2cache.demand_mshr_misses::total 1188439 # number of demand (read+write) MSHR misses 1157system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6617 # number of overall MSHR misses 1158system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5620 # number of overall MSHR misses 1159system.cpu.l2cache.overall_mshr_misses::cpu.inst 107068 # number of overall MSHR misses 1160system.cpu.l2cache.overall_mshr_misses::cpu.data 1069134 # number of overall MSHR misses 1161system.cpu.l2cache.overall_mshr_misses::total 1188439 # number of overall MSHR misses 1162system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52293 # 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number of ReadReq MSHR miss cycles 1173system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76811500 # number of UpgradeReq MSHR miss cycles 1174system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76811500 # number of UpgradeReq MSHR miss cycles 1175system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles 1176system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles 1177system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53386023001 # number of ReadExReq MSHR miss cycles 1178system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53386023001 # number of ReadExReq MSHR miss cycles 1179system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7782841501 # number of ReadCleanReq MSHR miss cycles 1180system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7782841501 # number of ReadCleanReq MSHR miss cycles 1181system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25481161022 # number of ReadSharedReq MSHR miss cycles 1182system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25481161022 # number of ReadSharedReq MSHR miss cycles 1183system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11306022501 # number of InvalidateReq MSHR miss cycles 1184system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11306022501 # number of InvalidateReq MSHR miss cycles 1185system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 516791000 # number of demand (read+write) MSHR miss cycles 1186system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 440365500 # number of demand (read+write) MSHR miss cycles 1187system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7782841501 # number of demand (read+write) MSHR miss cycles 1188system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78867184023 # number of demand (read+write) MSHR miss cycles 1189system.cpu.l2cache.demand_mshr_miss_latency::total 87607182024 # number of demand (read+write) MSHR miss cycles 1190system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 516791000 # number of overall MSHR miss cycles 1191system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 440365500 # number of overall MSHR miss cycles 1192system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7782841501 # number of overall MSHR miss cycles 1193system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78867184023 # number of overall MSHR miss cycles 1194system.cpu.l2cache.overall_mshr_miss_latency::total 87607182024 # number of overall MSHR miss cycles 1195system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3276571500 # number of ReadReq MSHR uncacheable cycles 1196system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809931000 # number of ReadReq MSHR uncacheable cycles 1197system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9086502500 # number of ReadReq MSHR uncacheable cycles 1198system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3276571500 # number of overall MSHR uncacheable cycles 1199system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809931000 # number of overall MSHR uncacheable cycles 1200system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9086502500 # number of overall MSHR uncacheable cycles 1201system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for ReadReq accesses 1202system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for ReadReq accesses 1203system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010196 # mshr miss rate for ReadReq accesses 1204system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1205system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1206system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.118132 # mshr miss rate for UpgradeReq accesses 1207system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.118132 # mshr miss rate for UpgradeReq accesses 1208system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1209system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1210system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.305219 # mshr miss rate for ReadExReq accesses 1211system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.305219 # mshr miss rate for ReadExReq accesses 1212system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for ReadCleanReq accesses 1213system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004327 # mshr miss rate for ReadCleanReq accesses 1214system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044412 # mshr miss rate for ReadSharedReq accesses 1215system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044412 # mshr miss rate for ReadSharedReq accesses 1216system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.439635 # mshr miss rate for InvalidateReq accesses 1217system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.439635 # mshr miss rate for InvalidateReq accesses 1218system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for demand accesses 1219system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for demand accesses 1220system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for demand accesses 1221system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for demand accesses 1222system.cpu.l2cache.demand_mshr_miss_rate::total 0.033073 # mshr miss rate for demand accesses 1223system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for overall accesses 1224system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for overall accesses 1225system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for overall accesses 1226system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for overall accesses 1227system.cpu.l2cache.overall_mshr_miss_rate::total 0.033073 # mshr miss rate for overall accesses 1228system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average ReadReq mshr miss latency 1229system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average ReadReq mshr miss latency 1230system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78218.231593 # average ReadReq mshr miss latency 1231system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19083.602484 # average UpgradeReq mshr miss latency 1232system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19083.602484 # average UpgradeReq mshr miss latency 1233system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1234system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 1235system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72944.879406 # average ReadExReq mshr miss latency 1236system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72944.879406 # average ReadExReq mshr miss latency 1237system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72690.640537 # average ReadCleanReq mshr miss latency 1238system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72690.640537 # average ReadCleanReq mshr miss latency 1239system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75552.119164 # average ReadSharedReq mshr miss latency 1240system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75552.119164 # average ReadSharedReq mshr miss latency 1241system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20639.713938 # average InvalidateReq mshr miss latency 1242system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20639.713938 # average InvalidateReq mshr miss latency 1243system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency 1244system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency 1245system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency 1246system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency 1247system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency 1248system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency 1249system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency 1250system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency 1251system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency 1252system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency 1253system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average ReadReq mshr uncacheable latency 1254system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172411.745504 # average ReadReq mshr uncacheable latency 1255system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105668.064100 # average ReadReq mshr uncacheable latency 1256system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average overall mshr uncacheable latency 1257system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.362436 # average overall mshr uncacheable latency 1258system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 75911.899113 # average overall mshr uncacheable latency 1259system.cpu.toL2Bus.snoop_filter.tot_requests 72719983 # Total number of requests made to the snoop filter. 1260system.cpu.toL2Bus.snoop_filter.hit_single_requests 36740859 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1261system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1262system.cpu.toL2Bus.snoop_filter.tot_snoops 1912 # Total number of snoops made to the snoop filter. 1263system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1912 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1264system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1265system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1266system.cpu.toL2Bus.trans_dist::ReadReq 1798088 # Transaction distribution 1267system.cpu.toL2Bus.trans_dist::ReadResp 34134170 # Transaction distribution 1268system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution 1269system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution 1270system.cpu.toL2Bus.trans_dist::WritebackDirty 10025859 # Transaction distribution 1271system.cpu.toL2Bus.trans_dist::WritebackClean 24740790 # Transaction distribution 1272system.cpu.toL2Bus.trans_dist::CleanEvict 2858806 # Transaction distribution 1273system.cpu.toL2Bus.trans_dist::UpgradeReq 34075 # Transaction distribution 1274system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1275system.cpu.toL2Bus.trans_dist::UpgradeResp 34076 # Transaction distribution 1276system.cpu.toL2Bus.trans_dist::ReadExReq 2397848 # Transaction distribution 1277system.cpu.toL2Bus.trans_dist::ReadExResp 2397848 # Transaction distribution 1278system.cpu.toL2Bus.trans_dist::ReadCleanReq 24741312 # Transaction distribution 1279system.cpu.toL2Bus.trans_dist::ReadSharedReq 7596551 # Transaction distribution 1280system.cpu.toL2Bus.trans_dist::InvalidateReq 1271756 # Transaction distribution 1281system.cpu.toL2Bus.trans_dist::InvalidateResp 1245987 # Transaction distribution 1282system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74327998 # Packet count per connected master and slave (bytes) 1283system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33916673 # Packet count per connected master and slave (bytes) 1284system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 673778 # Packet count per connected master and slave (bytes) 1285system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2238495 # Packet count per connected master and slave (bytes) 1286system.cpu.toL2Bus.pkt_count::total 111156944 # Packet count per connected master and slave (bytes) 1287system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3170201152 # Cumulative packet size per connected master and slave (bytes) 1288system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1191384986 # Cumulative packet size per connected master and slave (bytes) 1289system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2119720 # Cumulative packet size per connected master and slave (bytes) 1290system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7481688 # Cumulative packet size per connected master and slave (bytes) 1291system.cpu.toL2Bus.pkt_size::total 4371187546 # Cumulative packet size per connected master and slave (bytes) 1292system.cpu.toL2Bus.snoops 2188425 # Total snoops (count) 1293system.cpu.toL2Bus.snoopTraffic 94133704 # Total snoop traffic (bytes) 1294system.cpu.toL2Bus.snoop_fanout::samples 39520716 # Request fanout histogram 1295system.cpu.toL2Bus.snoop_fanout::mean 0.018595 # Request fanout histogram 1296system.cpu.toL2Bus.snoop_fanout::stdev 0.135091 # Request fanout histogram 1297system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1298system.cpu.toL2Bus.snoop_fanout::0 38785811 98.14% 98.14% # Request fanout histogram 1299system.cpu.toL2Bus.snoop_fanout::1 734905 1.86% 100.00% # Request fanout histogram 1300system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1301system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1302system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1303system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1304system.cpu.toL2Bus.snoop_fanout::total 39520716 # Request fanout histogram 1305system.cpu.toL2Bus.reqLayer0.occupancy 70288980496 # Layer occupancy (ticks) 1306system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1307system.cpu.toL2Bus.snoopLayer0.occupancy 1482392 # Layer occupancy (ticks) 1308system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1309system.cpu.toL2Bus.respLayer0.occupancy 37194713363 # Layer occupancy (ticks) 1310system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1311system.cpu.toL2Bus.respLayer1.occupancy 15679329987 # Layer occupancy (ticks) 1312system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1313system.cpu.toL2Bus.respLayer2.occupancy 408839447 # Layer occupancy (ticks) 1314system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1315system.cpu.toL2Bus.respLayer3.occupancy 1303303960 # Layer occupancy (ticks) 1316system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1317system.iobus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1318system.iobus.trans_dist::ReadReq 40309 # Transaction distribution 1319system.iobus.trans_dist::ReadResp 40309 # Transaction distribution 1320system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1321system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1322system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1323system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1324system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1327system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1328system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1329system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1330system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1331system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1332system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1333system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1334system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1335system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1336system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1339system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1340system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1342system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1343system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1344system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1345system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1346system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1347system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1348system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1349system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1350system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1351system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1352system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1353system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1354system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1355system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) 1356system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) 1357system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1358system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1359system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) 1360system.iobus.reqLayer0.occupancy 37793000 # Layer occupancy (ticks) 1361system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1362system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1363system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1364system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) 1365system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1366system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 1367system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1368system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) 1369system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1370system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) 1371system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1372system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 1373system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1374system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 1375system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1376system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1377system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1378system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 1379system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1380system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1381system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1382system.iobus.reqLayer23.occupancy 25128500 # Layer occupancy (ticks) 1383system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1384system.iobus.reqLayer24.occupancy 36456000 # Layer occupancy (ticks) 1385system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1386system.iobus.reqLayer25.occupancy 569339894 # Layer occupancy (ticks) 1387system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1388system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1389system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1390system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) 1391system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1392system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1393system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1394system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1395system.iocache.tags.replacements 115470 # number of replacements 1396system.iocache.tags.tagsinuse 10.448409 # Cycle average of tags in use 1397system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1398system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. 1399system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1400system.iocache.tags.warmup_cycle 13140724969000 # Cycle when the warmup percentage was hit. 1401system.iocache.tags.occ_blocks::realview.ethernet 3.519445 # Average occupied blocks per requestor 1402system.iocache.tags.occ_blocks::realview.ide 6.928964 # Average occupied blocks per requestor 1403system.iocache.tags.occ_percent::realview.ethernet 0.219965 # Average percentage of cache occupancy 1404system.iocache.tags.occ_percent::realview.ide 0.433060 # Average percentage of cache occupancy 1405system.iocache.tags.occ_percent::total 0.653026 # Average percentage of cache occupancy 1406system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1407system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1408system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1409system.iocache.tags.tag_accesses 1039749 # Number of tag accesses 1410system.iocache.tags.data_accesses 1039749 # Number of data accesses 1411system.iocache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1412system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1413system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses 1414system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses 1415system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1416system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1417system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1418system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1419system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1420system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses 1421system.iocache.demand_misses::total 115528 # number of demand (read+write) misses 1422system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1423system.iocache.overall_misses::realview.ide 115488 # number of overall misses 1424system.iocache.overall_misses::total 115528 # number of overall misses 1425system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles 1426system.iocache.ReadReq_miss_latency::realview.ide 1631024611 # number of ReadReq miss cycles 1427system.iocache.ReadReq_miss_latency::total 1636110611 # number of ReadReq miss cycles 1428system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1429system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1430system.iocache.WriteLineReq_miss_latency::realview.ide 12739251283 # number of WriteLineReq miss cycles 1431system.iocache.WriteLineReq_miss_latency::total 12739251283 # number of WriteLineReq miss cycles 1432system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles 1433system.iocache.demand_miss_latency::realview.ide 14370275894 # number of demand (read+write) miss cycles 1434system.iocache.demand_miss_latency::total 14375712894 # number of demand (read+write) miss cycles 1435system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles 1436system.iocache.overall_miss_latency::realview.ide 14370275894 # number of overall miss cycles 1437system.iocache.overall_miss_latency::total 14375712894 # number of overall miss cycles 1438system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1439system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) 1440system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) 1441system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1442system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1443system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1444system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1445system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1446system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses 1447system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses 1448system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1449system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses 1450system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses 1451system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1452system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1453system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1454system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1455system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1456system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1457system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1458system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1459system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1460system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1461system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1462system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1463system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1464system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency 1465system.iocache.ReadReq_avg_miss_latency::realview.ide 184839.597801 # average ReadReq miss latency 1466system.iocache.ReadReq_avg_miss_latency::total 184641.757251 # average ReadReq miss latency 1467system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1468system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1469system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119433.466615 # average WriteLineReq miss latency 1470system.iocache.WriteLineReq_avg_miss_latency::total 119433.466615 # average WriteLineReq miss latency 1471system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1472system.iocache.demand_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency 1473system.iocache.demand_avg_miss_latency::total 124434.880670 # average overall miss latency 1474system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1475system.iocache.overall_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency 1476system.iocache.overall_avg_miss_latency::total 124434.880670 # average overall miss latency 1477system.iocache.blocked_cycles::no_mshrs 31942 # number of cycles access was blocked 1478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1479system.iocache.blocked::no_mshrs 3389 # number of cycles access was blocked 1480system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1481system.iocache.avg_blocked_cycles::no_mshrs 9.425199 # average number of cycles each access was blocked 1482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1483system.iocache.writebacks::writebacks 106631 # number of writebacks 1484system.iocache.writebacks::total 106631 # number of writebacks 1485system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1486system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses 1487system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses 1488system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1489system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1490system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1491system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1492system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1493system.iocache.demand_mshr_misses::realview.ide 115488 # number of demand (read+write) MSHR misses 1494system.iocache.demand_mshr_misses::total 115528 # number of demand (read+write) MSHR misses 1495system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1496system.iocache.overall_mshr_misses::realview.ide 115488 # number of overall MSHR misses 1497system.iocache.overall_mshr_misses::total 115528 # number of overall MSHR misses 1498system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles 1499system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189824611 # number of ReadReq MSHR miss cycles 1500system.iocache.ReadReq_mshr_miss_latency::total 1193060611 # number of ReadReq MSHR miss cycles 1501system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1502system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1503system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7399114026 # number of WriteLineReq MSHR miss cycles 1504system.iocache.WriteLineReq_mshr_miss_latency::total 7399114026 # number of WriteLineReq MSHR miss cycles 1505system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles 1506system.iocache.demand_mshr_miss_latency::realview.ide 8588938637 # number of demand (read+write) MSHR miss cycles 1507system.iocache.demand_mshr_miss_latency::total 8592375637 # number of demand (read+write) MSHR miss cycles 1508system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles 1509system.iocache.overall_mshr_miss_latency::realview.ide 8588938637 # number of overall MSHR miss cycles 1510system.iocache.overall_mshr_miss_latency::total 8592375637 # number of overall MSHR miss cycles 1511system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1512system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1513system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1514system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1515system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1516system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1517system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1518system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1519system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1520system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1521system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1522system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1523system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1524system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency 1525system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134839.597801 # average ReadReq mshr miss latency 1526system.iocache.ReadReq_avg_mshr_miss_latency::total 134641.757251 # average ReadReq mshr miss latency 1527system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1528system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1529system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69368.428204 # average WriteLineReq mshr miss latency 1530system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69368.428204 # average WriteLineReq mshr miss latency 1531system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1532system.iocache.demand_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency 1533system.iocache.demand_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency 1534system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1535system.iocache.overall_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency 1536system.iocache.overall_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency 1537system.membus.snoop_filter.tot_requests 3617552 # Total number of requests made to the snoop filter. 1538system.membus.snoop_filter.hit_single_requests 1792214 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1539system.membus.snoop_filter.hit_multi_requests 3206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1540system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1541system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1542system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1543system.membus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1544system.membus.trans_dist::ReadReq 85991 # Transaction distribution 1545system.membus.trans_dist::ReadResp 551423 # Transaction distribution 1546system.membus.trans_dist::WriteReq 33707 # Transaction distribution 1547system.membus.trans_dist::WriteResp 33707 # Transaction distribution 1548system.membus.trans_dist::WritebackDirty 1512694 # Transaction distribution 1549system.membus.trans_dist::CleanEvict 249055 # Transaction distribution 1550system.membus.trans_dist::UpgradeReq 4641 # Transaction distribution 1551system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1552system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1553system.membus.trans_dist::ReadExReq 731311 # Transaction distribution 1554system.membus.trans_dist::ReadExResp 731311 # Transaction distribution 1555system.membus.trans_dist::ReadSharedReq 465432 # Transaction distribution 1556system.membus.trans_dist::InvalidateReq 654388 # Transaction distribution 1557system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1558system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1559system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) 1560system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4683490 # Packet count per connected master and slave (bytes) 1561system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4813146 # Packet count per connected master and slave (bytes) 1562system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237510 # Packet count per connected master and slave (bytes) 1563system.membus.pkt_count_system.iocache.mem_side::total 237510 # Packet count per connected master and slave (bytes) 1564system.membus.pkt_count::total 5050656 # Packet count per connected master and slave (bytes) 1565system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1566system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1567system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) 1568system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 169337260 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.pkt_size_system.cpu.l2cache.mem_side::total 169507674 # Cumulative packet size per connected master and slave (bytes) 1570system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7241152 # Cumulative packet size per connected master and slave (bytes) 1571system.membus.pkt_size_system.iocache.mem_side::total 7241152 # Cumulative packet size per connected master and slave (bytes) 1572system.membus.pkt_size::total 176748826 # Cumulative packet size per connected master and slave (bytes) 1573system.membus.snoops 3012 # Total snoops (count) 1574system.membus.snoopTraffic 192320 # Total snoop traffic (bytes) 1575system.membus.snoop_fanout::samples 1975472 # Request fanout histogram 1576system.membus.snoop_fanout::mean 0.014689 # Request fanout histogram 1577system.membus.snoop_fanout::stdev 0.120303 # Request fanout histogram 1578system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1579system.membus.snoop_fanout::0 1946455 98.53% 98.53% # Request fanout histogram 1580system.membus.snoop_fanout::1 29017 1.47% 100.00% # Request fanout histogram 1581system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1582system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1583system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1584system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1585system.membus.snoop_fanout::total 1975472 # Request fanout histogram 1586system.membus.reqLayer0.occupancy 99807500 # Layer occupancy (ticks) 1587system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1588system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) 1589system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1590system.membus.reqLayer2.occupancy 5588000 # Layer occupancy (ticks) 1591system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1592system.membus.reqLayer5.occupancy 9976212567 # Layer occupancy (ticks) 1593system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1594system.membus.respLayer2.occupancy 6680987810 # Layer occupancy (ticks) 1595system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1596system.membus.respLayer3.occupancy 44817130 # Layer occupancy (ticks) 1597system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1598system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1599system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1600system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1601system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1602system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1603system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1604system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1605system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1606system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1607system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1608system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1609system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1610system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1611system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1612system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1613system.realview.ethernet.txBytes 966 # Bytes Transmitted 1614system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1615system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1616system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1617system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1618system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1619system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1620system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1621system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1622system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1623system.realview.ethernet.totPackets 3 # Total Packets 1624system.realview.ethernet.totBytes 966 # Total Bytes 1625system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1626system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1627system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1628system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1629system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1630system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1631system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1632system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1633system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1634system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1635system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1636system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1637system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1638system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1639system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1640system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1641system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1642system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1643system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1644system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1645system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1646system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1647system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1648system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1649system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1650system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1651system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1652system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1653system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1654system.realview.ethernet.droppedPackets 0 # number of packets dropped 1655system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1656system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1657system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1658system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1659system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1660system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1661system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1662system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1663system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1664system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1665system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1666system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1667system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1668system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1669system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1670system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1671system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1672system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1673system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1674system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1675system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1676system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1677system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states 1678 1679---------- End Simulation Statistics ---------- 1680