stats.txt revision 11239:3be64e1f80ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.667600 # Number of seconds simulated 4sim_ticks 51667599599000 # Number of ticks simulated 5final_tick 51667599599000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 138912 # Simulator instruction rate (inst/s) 8host_op_rate 163218 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7778954181 # Simulator tick rate (ticks/s) 10host_mem_usage 682524 # Number of bytes of host memory used 11host_seconds 6641.97 # Real time elapsed on the host 12sim_insts 922648651 # Number of instructions simulated 13sim_ops 1084091117 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 355648 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 310272 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 9988672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 94253512 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory 21system.physmem.bytes_read::total 105321992 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 9988672 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 9988672 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 87921472 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 87942052 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 5557 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4848 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 156073 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1472724 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1645669 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1373773 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1376346 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 6883 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 6005 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 193326 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1824229 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 8011 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2038453 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 193326 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 193326 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1701675 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1702073 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1701675 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 6883 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 6005 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 193326 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1824627 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 8011 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3740527 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1645669 # Number of read requests accepted 55system.physmem.writeReqs 1376346 # Number of write requests accepted 56system.physmem.readBursts 1645669 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1376346 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 105266752 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 56064 # Total number of bytes read from write queue 60system.physmem.bytesWritten 87940608 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 105321992 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 87942052 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 876 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 378251 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 98784 # Per bank write bursts 67system.physmem.perBankRdBursts::1 105100 # Per bank write bursts 68system.physmem.perBankRdBursts::2 100845 # Per bank write bursts 69system.physmem.perBankRdBursts::3 95977 # Per bank write bursts 70system.physmem.perBankRdBursts::4 103819 # Per bank write bursts 71system.physmem.perBankRdBursts::5 113338 # Per bank write bursts 72system.physmem.perBankRdBursts::6 98145 # Per bank write bursts 73system.physmem.perBankRdBursts::7 99955 # Per bank write bursts 74system.physmem.perBankRdBursts::8 93968 # Per bank write bursts 75system.physmem.perBankRdBursts::9 154563 # Per bank write bursts 76system.physmem.perBankRdBursts::10 98779 # Per bank write bursts 77system.physmem.perBankRdBursts::11 100711 # Per bank write bursts 78system.physmem.perBankRdBursts::12 92945 # Per bank write bursts 79system.physmem.perBankRdBursts::13 97659 # Per bank write bursts 80system.physmem.perBankRdBursts::14 91699 # Per bank write bursts 81system.physmem.perBankRdBursts::15 98506 # Per bank write bursts 82system.physmem.perBankWrBursts::0 83240 # Per bank write bursts 83system.physmem.perBankWrBursts::1 87253 # Per bank write bursts 84system.physmem.perBankWrBursts::2 86416 # Per bank write bursts 85system.physmem.perBankWrBursts::3 83797 # Per bank write bursts 86system.physmem.perBankWrBursts::4 90075 # Per bank write bursts 87system.physmem.perBankWrBursts::5 95693 # Per bank write bursts 88system.physmem.perBankWrBursts::6 84431 # Per bank write bursts 89system.physmem.perBankWrBursts::7 87097 # Per bank write bursts 90system.physmem.perBankWrBursts::8 83064 # Per bank write bursts 91system.physmem.perBankWrBursts::9 88599 # Per bank write bursts 92system.physmem.perBankWrBursts::10 84727 # Per bank write bursts 93system.physmem.perBankWrBursts::11 86277 # Per bank write bursts 94system.physmem.perBankWrBursts::12 82015 # Per bank write bursts 95system.physmem.perBankWrBursts::13 84756 # Per bank write bursts 96system.physmem.perBankWrBursts::14 80845 # Per bank write bursts 97system.physmem.perBankWrBursts::15 85787 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 100system.physmem.totGap 51667597819500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1645654 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1373773 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1321004 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 317364 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 977 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 363 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 478 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 545 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 512 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1186 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 669 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 302 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 350 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 124 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 15051 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 17153 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 65956 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 81050 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 83118 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 82838 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 83953 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 83921 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 85569 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 84918 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 85424 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 90109 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 84668 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 83357 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 92346 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 82532 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 83696 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 80480 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1093 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 699 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 466 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 417 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 390 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 289 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 303 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 302 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 236 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 342 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 252 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 215 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 263 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 155 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 75 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 648118 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 298.103938 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 174.284544 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 324.148793 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 253468 39.11% 39.11% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 156556 24.16% 63.26% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 60545 9.34% 72.61% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 34961 5.39% 78.00% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 26042 4.02% 82.02% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 18689 2.88% 84.90% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 14146 2.18% 87.08% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 13035 2.01% 89.10% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 70676 10.90% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 648118 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 79768 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 20.619672 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 282.463170 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-4095 79765 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 79768 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 79768 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.225855 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 16.793439 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 6.200790 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 77436 97.08% 97.08% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 326 0.41% 97.49% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 71 0.09% 97.57% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 315 0.39% 97.97% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 43 0.05% 98.02% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 360 0.45% 98.47% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 211 0.26% 98.74% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 25 0.03% 98.77% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 65 0.08% 98.85% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 125 0.16% 99.01% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 20 0.03% 99.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 34 0.04% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 501 0.63% 99.70% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 33 0.04% 99.75% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 30 0.04% 99.78% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 120 0.15% 99.93% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 8 0.01% 99.94% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 3 0.00% 99.95% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 2 0.00% 99.95% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 4 0.01% 99.96% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 1 0.00% 99.96% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::120-123 1 0.00% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 23 0.03% 99.99% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 4 0.01% 99.99% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 1 0.00% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 79768 # Writes before turning the bus around for reads 268system.physmem.totQLat 26467861730 # Total ticks spent queuing 269system.physmem.totMemAccLat 57307730480 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 8223965000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 16091.91 # Average queueing delay per DRAM burst 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 273system.physmem.avgMemAccLat 34841.91 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 2.04 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 1.70 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 2.04 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 1.70 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.03 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 23.70 # Average write queue length when enqueuing 284system.physmem.readRowHits 1338706 # Number of row buffer hits during reads 285system.physmem.writeRowHits 1032034 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes 288system.physmem.avgGap 17097068.62 # Average gap between requests 289system.physmem.pageHitRate 78.53 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 2524404960 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 1377403500 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 6364503600 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 4523001120 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ) 295system.physmem_0.actBackEnergy 1325410671600 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 29837914926750 # Energy for precharge background per rank (pJ) 297system.physmem_0.totalEnergy 34552790914410 # Total energy per rank (pJ) 298system.physmem_0.averagePower 668.751704 # Core power per rank (mW) 299system.physmem_0.memoryStateTime::IDLE 49637080843701 # Time in different power states 300system.physmem_0.memoryStateTime::REF 1725294480000 # Time in different power states 301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 302system.physmem_0.memoryStateTime::ACT 305218373299 # Time in different power states 303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 304system.physmem_1.actEnergy 2375306640 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 1296050250 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 6464827200 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 4380881760 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ) 309system.physmem_1.actBackEnergy 1318079999925 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 29844345348750 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 34551618417405 # Total energy per rank (pJ) 312system.physmem_1.averagePower 668.729010 # Core power per rank (mW) 313system.physmem_1.memoryStateTime::IDLE 49647781129555 # Time in different power states 314system.physmem_1.memoryStateTime::REF 1725294480000 # Time in different power states 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 316system.physmem_1.memoryStateTime::ACT 294523106445 # Time in different power states 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 319system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 320system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 321system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 322system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 323system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 324system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 325system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 326system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 332system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 333system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 334system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 335system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 336system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 337system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 338system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 339system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 340system.cpu.branchPred.lookups 252640803 # Number of BP lookups 341system.cpu.branchPred.condPredicted 176566458 # Number of conditional branches predicted 342system.cpu.branchPred.condIncorrect 11942340 # Number of conditional branches incorrect 343system.cpu.branchPred.BTBLookups 185523828 # Number of BTB lookups 344system.cpu.branchPred.BTBHits 131623059 # Number of BTB hits 345system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 346system.cpu.branchPred.BTBHitPct 70.946714 # BTB Hit Percentage 347system.cpu.branchPred.usedRAS 30927608 # Number of times the RAS was used to get a target. 348system.cpu.branchPred.RASInCorrect 2129490 # Number of incorrect RAS predictions. 349system.cpu_clk_domain.clock 500 # Clock period in ticks 350system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 359system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 360system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 361system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 362system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 363system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 364system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 365system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 366system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 368system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 369system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 370system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 371system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 372system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 374system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 375system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 376system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 377system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 378system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 379system.cpu.dtb.walker.walks 561342 # Table walker walks requested 380system.cpu.dtb.walker.walksLong 561342 # Table walker walks initiated with long descriptors 381system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20890 # Level at which table walker walks with long descriptors terminate 382system.cpu.dtb.walker.walksLongTerminationLevel::Level3 179371 # Level at which table walker walks with long descriptors terminate 383system.cpu.dtb.walker.walkWaitTime::samples 561342 # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::0 561342 100.00% 100.00% # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkWaitTime::total 561342 # Table walker wait (enqueue to first request) latency 386system.cpu.dtb.walker.walkCompletionTime::samples 200261 # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::mean 26959.987217 # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::gmean 22796.816332 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::stdev 20928.483641 # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::0-65535 197960 98.85% 98.85% # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 98.85% # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::131072-196607 1973 0.99% 99.84% # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::196608-262143 53 0.03% 99.86% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::262144-327679 114 0.06% 99.92% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::327680-393215 41 0.02% 99.94% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::393216-458751 90 0.04% 99.99% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::total 200261 # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution 403system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution 404system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution 405system.cpu.dtb.walker.walkPageSizes::4K 179372 89.57% 89.57% # Table walker page sizes translated 406system.cpu.dtb.walker.walkPageSizes::2M 20890 10.43% 100.00% # Table walker page sizes translated 407system.cpu.dtb.walker.walkPageSizes::total 200262 # Table walker page sizes translated 408system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561342 # Table walker requests started/completed, data/inst 409system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 410system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561342 # Table walker requests started/completed, data/inst 411system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 200262 # Table walker requests started/completed, data/inst 412system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin_Completed::total 200262 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin::total 761604 # Table walker requests started/completed, data/inst 415system.cpu.dtb.inst_hits 0 # ITB inst hits 416system.cpu.dtb.inst_misses 0 # ITB inst misses 417system.cpu.dtb.read_hits 178417728 # DTB read hits 418system.cpu.dtb.read_misses 463663 # DTB read misses 419system.cpu.dtb.write_hits 158017805 # DTB write hits 420system.cpu.dtb.write_misses 97679 # DTB write misses 421system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 422system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 423system.cpu.dtb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID 424system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID 425system.cpu.dtb.flush_entries 77601 # Number of entries that have been flushed from TLB 426system.cpu.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions 427system.cpu.dtb.prefetch_faults 14410 # Number of TLB faults due to prefetch 428system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 429system.cpu.dtb.perms_faults 23069 # Number of TLB faults due to permissions restrictions 430system.cpu.dtb.read_accesses 178881391 # DTB read accesses 431system.cpu.dtb.write_accesses 158115484 # DTB write accesses 432system.cpu.dtb.inst_accesses 0 # ITB inst accesses 433system.cpu.dtb.hits 336435533 # DTB hits 434system.cpu.dtb.misses 561342 # DTB misses 435system.cpu.dtb.accesses 336996875 # DTB accesses 436system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 437system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 438system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 445system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 446system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 447system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 448system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 449system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 450system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 451system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 452system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 453system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 454system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 455system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 456system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 457system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 458system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 459system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 460system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 461system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 462system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 463system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 464system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 465system.cpu.itb.walker.walks 135051 # Table walker walks requested 466system.cpu.itb.walker.walksLong 135051 # Table walker walks initiated with long descriptors 467system.cpu.itb.walker.walksLongTerminationLevel::Level2 1071 # Level at which table walker walks with long descriptors terminate 468system.cpu.itb.walker.walksLongTerminationLevel::Level3 117673 # Level at which table walker walks with long descriptors terminate 469system.cpu.itb.walker.walkWaitTime::samples 135051 # Table walker wait (enqueue to first request) latency 470system.cpu.itb.walker.walkWaitTime::0 135051 100.00% 100.00% # Table walker wait (enqueue to first request) latency 471system.cpu.itb.walker.walkWaitTime::total 135051 # Table walker wait (enqueue to first request) latency 472system.cpu.itb.walker.walkCompletionTime::samples 118744 # Table walker service (enqueue to completion) latency 473system.cpu.itb.walker.walkCompletionTime::mean 30328.088156 # Table walker service (enqueue to completion) latency 474system.cpu.itb.walker.walkCompletionTime::gmean 25835.192345 # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::stdev 23534.472369 # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::0-32767 58823 49.54% 49.54% # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::32768-65535 57227 48.19% 97.73% # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.73% # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::98304-131071 5 0.00% 97.74% # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::131072-163839 2006 1.69% 99.43% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::163840-196607 464 0.39% 99.82% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::196608-229375 29 0.02% 99.84% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::229376-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::262144-294911 88 0.07% 99.94% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::294912-327679 29 0.02% 99.97% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::327680-360447 14 0.01% 99.98% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::360448-393215 13 0.01% 99.99% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::393216-425983 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::total 118744 # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution 493system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution 494system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution 495system.cpu.itb.walker.walkPageSizes::4K 117673 99.10% 99.10% # Table walker page sizes translated 496system.cpu.itb.walker.walkPageSizes::2M 1071 0.90% 100.00% # Table walker page sizes translated 497system.cpu.itb.walker.walkPageSizes::total 118744 # Table walker page sizes translated 498system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135051 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Requested::total 135051 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118744 # Table walker requests started/completed, data/inst 503system.cpu.itb.walker.walkRequestOrigin_Completed::total 118744 # Table walker requests started/completed, data/inst 504system.cpu.itb.walker.walkRequestOrigin::total 253795 # Table walker requests started/completed, data/inst 505system.cpu.itb.inst_hits 439141642 # ITB inst hits 506system.cpu.itb.inst_misses 135051 # ITB inst misses 507system.cpu.itb.read_hits 0 # DTB read hits 508system.cpu.itb.read_misses 0 # DTB read misses 509system.cpu.itb.write_hits 0 # DTB write hits 510system.cpu.itb.write_misses 0 # DTB write misses 511system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 512system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 513system.cpu.itb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID 514system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID 515system.cpu.itb.flush_entries 55572 # Number of entries that have been flushed from TLB 516system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 517system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 518system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 519system.cpu.itb.perms_faults 356769 # Number of TLB faults due to permissions restrictions 520system.cpu.itb.read_accesses 0 # DTB read accesses 521system.cpu.itb.write_accesses 0 # DTB write accesses 522system.cpu.itb.inst_accesses 439276693 # ITB inst accesses 523system.cpu.itb.hits 439141642 # DTB hits 524system.cpu.itb.misses 135051 # DTB misses 525system.cpu.itb.accesses 439276693 # DTB accesses 526system.cpu.numCycles 2565959423 # number of cpu cycles simulated 527system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 528system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529system.cpu.committedInsts 922648651 # Number of instructions committed 530system.cpu.committedOps 1084091117 # Number of ops (including micro ops) committed 531system.cpu.discardedOps 92858708 # Number of ops (including micro ops) which were discarded before commit 532system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching 533system.cpu.quiesceCycles 100770378430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 534system.cpu.cpi 2.781080 # CPI: cycles per instruction 535system.cpu.ipc 0.359573 # IPC: instructions per cycle 536system.cpu.kern.inst.arm 0 # number of arm instructions executed 537system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed 538system.cpu.tickCycles 1742118066 # Number of cycles that the object actually ticked 539system.cpu.idleCycles 823841357 # Total number of cycles that the object has spent stopped 540system.cpu.dcache.tags.replacements 10735802 # number of replacements 541system.cpu.dcache.tags.tagsinuse 511.930082 # Cycle average of tags in use 542system.cpu.dcache.tags.total_refs 320587267 # Total number of references to valid blocks. 543system.cpu.dcache.tags.sampled_refs 10736314 # Sample count of references to valid blocks. 544system.cpu.dcache.tags.avg_refs 29.860087 # Average number of references to valid blocks. 545system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. 546system.cpu.dcache.tags.occ_blocks::cpu.data 511.930082 # Average occupied blocks per requestor 547system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 548system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 549system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 550system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 551system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id 552system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 553system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 554system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 555system.cpu.dcache.tags.tag_accesses 1346721008 # Number of tag accesses 556system.cpu.dcache.tags.data_accesses 1346721008 # Number of data accesses 557system.cpu.dcache.ReadReq_hits::cpu.data 164117651 # number of ReadReq hits 558system.cpu.dcache.ReadReq_hits::total 164117651 # number of ReadReq hits 559system.cpu.dcache.WriteReq_hits::cpu.data 147554232 # number of WriteReq hits 560system.cpu.dcache.WriteReq_hits::total 147554232 # number of WriteReq hits 561system.cpu.dcache.SoftPFReq_hits::cpu.data 511700 # number of SoftPFReq hits 562system.cpu.dcache.SoftPFReq_hits::total 511700 # number of SoftPFReq hits 563system.cpu.dcache.WriteLineReq_hits::cpu.data 336216 # number of WriteLineReq hits 564system.cpu.dcache.WriteLineReq_hits::total 336216 # number of WriteLineReq hits 565system.cpu.dcache.LoadLockedReq_hits::cpu.data 3856271 # number of LoadLockedReq hits 566system.cpu.dcache.LoadLockedReq_hits::total 3856271 # number of LoadLockedReq hits 567system.cpu.dcache.StoreCondReq_hits::cpu.data 4163172 # number of StoreCondReq hits 568system.cpu.dcache.StoreCondReq_hits::total 4163172 # number of StoreCondReq hits 569system.cpu.dcache.demand_hits::cpu.data 311671883 # number of demand (read+write) hits 570system.cpu.dcache.demand_hits::total 311671883 # number of demand (read+write) hits 571system.cpu.dcache.overall_hits::cpu.data 312183583 # number of overall hits 572system.cpu.dcache.overall_hits::total 312183583 # number of overall hits 573system.cpu.dcache.ReadReq_misses::cpu.data 6375380 # number of ReadReq misses 574system.cpu.dcache.ReadReq_misses::total 6375380 # number of ReadReq misses 575system.cpu.dcache.WriteReq_misses::cpu.data 4133213 # number of WriteReq misses 576system.cpu.dcache.WriteReq_misses::total 4133213 # number of WriteReq misses 577system.cpu.dcache.SoftPFReq_misses::cpu.data 1400858 # number of SoftPFReq misses 578system.cpu.dcache.SoftPFReq_misses::total 1400858 # number of SoftPFReq misses 579system.cpu.dcache.WriteLineReq_misses::cpu.data 1238861 # number of WriteLineReq misses 580system.cpu.dcache.WriteLineReq_misses::total 1238861 # number of WriteLineReq misses 581system.cpu.dcache.LoadLockedReq_misses::cpu.data 308609 # number of LoadLockedReq misses 582system.cpu.dcache.LoadLockedReq_misses::total 308609 # number of LoadLockedReq misses 583system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 584system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 585system.cpu.dcache.demand_misses::cpu.data 10508593 # number of demand (read+write) misses 586system.cpu.dcache.demand_misses::total 10508593 # number of demand (read+write) misses 587system.cpu.dcache.overall_misses::cpu.data 11909451 # number of overall misses 588system.cpu.dcache.overall_misses::total 11909451 # number of overall misses 589system.cpu.dcache.ReadReq_miss_latency::cpu.data 117756219000 # number of ReadReq miss cycles 590system.cpu.dcache.ReadReq_miss_latency::total 117756219000 # number of ReadReq miss cycles 591system.cpu.dcache.WriteReq_miss_latency::cpu.data 201470838000 # number of WriteReq miss cycles 592system.cpu.dcache.WriteReq_miss_latency::total 201470838000 # number of WriteReq miss cycles 593system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84198421500 # number of WriteLineReq miss cycles 594system.cpu.dcache.WriteLineReq_miss_latency::total 84198421500 # number of WriteLineReq miss cycles 595system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5139608000 # number of LoadLockedReq miss cycles 596system.cpu.dcache.LoadLockedReq_miss_latency::total 5139608000 # number of LoadLockedReq miss cycles 597system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 598system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles 599system.cpu.dcache.demand_miss_latency::cpu.data 319227057000 # number of demand (read+write) miss cycles 600system.cpu.dcache.demand_miss_latency::total 319227057000 # number of demand (read+write) miss cycles 601system.cpu.dcache.overall_miss_latency::cpu.data 319227057000 # number of overall miss cycles 602system.cpu.dcache.overall_miss_latency::total 319227057000 # number of overall miss cycles 603system.cpu.dcache.ReadReq_accesses::cpu.data 170493031 # number of ReadReq accesses(hits+misses) 604system.cpu.dcache.ReadReq_accesses::total 170493031 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.WriteReq_accesses::cpu.data 151687445 # number of WriteReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::total 151687445 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.SoftPFReq_accesses::cpu.data 1912558 # number of SoftPFReq accesses(hits+misses) 608system.cpu.dcache.SoftPFReq_accesses::total 1912558 # number of SoftPFReq accesses(hits+misses) 609system.cpu.dcache.WriteLineReq_accesses::cpu.data 1575077 # number of WriteLineReq accesses(hits+misses) 610system.cpu.dcache.WriteLineReq_accesses::total 1575077 # number of WriteLineReq accesses(hits+misses) 611system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164880 # number of LoadLockedReq accesses(hits+misses) 612system.cpu.dcache.LoadLockedReq_accesses::total 4164880 # number of LoadLockedReq accesses(hits+misses) 613system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163173 # number of StoreCondReq accesses(hits+misses) 614system.cpu.dcache.StoreCondReq_accesses::total 4163173 # number of StoreCondReq accesses(hits+misses) 615system.cpu.dcache.demand_accesses::cpu.data 322180476 # number of demand (read+write) accesses 616system.cpu.dcache.demand_accesses::total 322180476 # number of demand (read+write) accesses 617system.cpu.dcache.overall_accesses::cpu.data 324093034 # number of overall (read+write) accesses 618system.cpu.dcache.overall_accesses::total 324093034 # number of overall (read+write) accesses 619system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037394 # miss rate for ReadReq accesses 620system.cpu.dcache.ReadReq_miss_rate::total 0.037394 # miss rate for ReadReq accesses 621system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027248 # miss rate for WriteReq accesses 622system.cpu.dcache.WriteReq_miss_rate::total 0.027248 # miss rate for WriteReq accesses 623system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732453 # miss rate for SoftPFReq accesses 624system.cpu.dcache.SoftPFReq_miss_rate::total 0.732453 # miss rate for SoftPFReq accesses 625system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786540 # miss rate for WriteLineReq accesses 626system.cpu.dcache.WriteLineReq_miss_rate::total 0.786540 # miss rate for WriteLineReq accesses 627system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074098 # miss rate for LoadLockedReq accesses 628system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074098 # miss rate for LoadLockedReq accesses 629system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 630system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 631system.cpu.dcache.demand_miss_rate::cpu.data 0.032617 # miss rate for demand accesses 632system.cpu.dcache.demand_miss_rate::total 0.032617 # miss rate for demand accesses 633system.cpu.dcache.overall_miss_rate::cpu.data 0.036747 # miss rate for overall accesses 634system.cpu.dcache.overall_miss_rate::total 0.036747 # miss rate for overall accesses 635system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18470.462780 # average ReadReq miss latency 636system.cpu.dcache.ReadReq_avg_miss_latency::total 18470.462780 # average ReadReq miss latency 637system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48744.363767 # average WriteReq miss latency 638system.cpu.dcache.WriteReq_avg_miss_latency::total 48744.363767 # average WriteReq miss latency 639system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67964.381395 # average WriteLineReq miss latency 640system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67964.381395 # average WriteLineReq miss latency 641system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16654.109245 # average LoadLockedReq miss latency 642system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16654.109245 # average LoadLockedReq miss latency 643system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 644system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 645system.cpu.dcache.demand_avg_miss_latency::cpu.data 30377.716313 # average overall miss latency 646system.cpu.dcache.demand_avg_miss_latency::total 30377.716313 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::cpu.data 26804.514918 # average overall miss latency 648system.cpu.dcache.overall_avg_miss_latency::total 26804.514918 # average overall miss latency 649system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.cpu.dcache.fast_writes 0 # number of fast writes performed 656system.cpu.dcache.cache_copies 0 # number of cache copies performed 657system.cpu.dcache.writebacks::writebacks 8239619 # number of writebacks 658system.cpu.dcache.writebacks::total 8239619 # number of writebacks 659system.cpu.dcache.ReadReq_mshr_hits::cpu.data 773301 # number of ReadReq MSHR hits 660system.cpu.dcache.ReadReq_mshr_hits::total 773301 # number of ReadReq MSHR hits 661system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821450 # number of WriteReq MSHR hits 662system.cpu.dcache.WriteReq_mshr_hits::total 1821450 # number of WriteReq MSHR hits 663system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 142 # number of WriteLineReq MSHR hits 664system.cpu.dcache.WriteLineReq_mshr_hits::total 142 # number of WriteLineReq MSHR hits 665system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70152 # number of LoadLockedReq MSHR hits 666system.cpu.dcache.LoadLockedReq_mshr_hits::total 70152 # number of LoadLockedReq MSHR hits 667system.cpu.dcache.demand_mshr_hits::cpu.data 2594751 # number of demand (read+write) MSHR hits 668system.cpu.dcache.demand_mshr_hits::total 2594751 # number of demand (read+write) MSHR hits 669system.cpu.dcache.overall_mshr_hits::cpu.data 2594751 # number of overall MSHR hits 670system.cpu.dcache.overall_mshr_hits::total 2594751 # number of overall MSHR hits 671system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5602079 # number of ReadReq MSHR misses 672system.cpu.dcache.ReadReq_mshr_misses::total 5602079 # number of ReadReq MSHR misses 673system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2311763 # number of WriteReq MSHR misses 674system.cpu.dcache.WriteReq_mshr_misses::total 2311763 # number of WriteReq MSHR misses 675system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1393294 # number of SoftPFReq MSHR misses 676system.cpu.dcache.SoftPFReq_mshr_misses::total 1393294 # number of SoftPFReq MSHR misses 677system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238719 # number of WriteLineReq MSHR misses 678system.cpu.dcache.WriteLineReq_mshr_misses::total 1238719 # number of WriteLineReq MSHR misses 679system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 238457 # number of LoadLockedReq MSHR misses 680system.cpu.dcache.LoadLockedReq_mshr_misses::total 238457 # number of LoadLockedReq MSHR misses 681system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 682system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 683system.cpu.dcache.demand_mshr_misses::cpu.data 7913842 # number of demand (read+write) MSHR misses 684system.cpu.dcache.demand_mshr_misses::total 7913842 # number of demand (read+write) MSHR misses 685system.cpu.dcache.overall_mshr_misses::cpu.data 9307136 # number of overall MSHR misses 686system.cpu.dcache.overall_mshr_misses::total 9307136 # number of overall MSHR misses 687system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 688system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 689system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 690system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 691system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 692system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 693system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96321163500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.ReadReq_mshr_miss_latency::total 96321163500 # number of ReadReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106904157500 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.WriteReq_mshr_miss_latency::total 106904157500 # number of WriteReq MSHR miss cycles 697system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26939627500 # number of SoftPFReq MSHR miss cycles 698system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26939627500 # number of SoftPFReq MSHR miss cycles 699system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 82952613500 # number of WriteLineReq MSHR miss cycles 700system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 82952613500 # number of WriteLineReq MSHR miss cycles 701system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3468831500 # number of LoadLockedReq MSHR miss cycles 702system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3468831500 # number of LoadLockedReq MSHR miss cycles 703system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 704system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles 705system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203225321000 # number of demand (read+write) MSHR miss cycles 706system.cpu.dcache.demand_mshr_miss_latency::total 203225321000 # number of demand (read+write) MSHR miss cycles 707system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230164948500 # number of overall MSHR miss cycles 708system.cpu.dcache.overall_mshr_miss_latency::total 230164948500 # number of overall MSHR miss cycles 709system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6198462000 # number of ReadReq MSHR uncacheable cycles 710system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6198462000 # number of ReadReq MSHR uncacheable cycles 711system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207588500 # number of WriteReq MSHR uncacheable cycles 712system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207588500 # number of WriteReq MSHR uncacheable cycles 713system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12406050500 # number of overall MSHR uncacheable cycles 714system.cpu.dcache.overall_mshr_uncacheable_latency::total 12406050500 # number of overall MSHR uncacheable cycles 715system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032858 # mshr miss rate for ReadReq accesses 716system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032858 # mshr miss rate for ReadReq accesses 717system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015240 # mshr miss rate for WriteReq accesses 718system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015240 # mshr miss rate for WriteReq accesses 719system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728498 # mshr miss rate for SoftPFReq accesses 720system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728498 # mshr miss rate for SoftPFReq accesses 721system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786450 # mshr miss rate for WriteLineReq accesses 722system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786450 # mshr miss rate for WriteLineReq accesses 723system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057254 # mshr miss rate for LoadLockedReq accesses 724system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057254 # mshr miss rate for LoadLockedReq accesses 725system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 726system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 727system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024563 # mshr miss rate for demand accesses 728system.cpu.dcache.demand_mshr_miss_rate::total 0.024563 # mshr miss rate for demand accesses 729system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028717 # mshr miss rate for overall accesses 730system.cpu.dcache.overall_mshr_miss_rate::total 0.028717 # mshr miss rate for overall accesses 731system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17193.824560 # average ReadReq mshr miss latency 732system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17193.824560 # average ReadReq mshr miss latency 733system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46243.562813 # average WriteReq mshr miss latency 734system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46243.562813 # average WriteReq mshr miss latency 735system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19335.206712 # average SoftPFReq mshr miss latency 736system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19335.206712 # average SoftPFReq mshr miss latency 737system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66966.449614 # average WriteLineReq mshr miss latency 738system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66966.449614 # average WriteLineReq mshr miss latency 739system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14546.989604 # average LoadLockedReq mshr miss latency 740system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14546.989604 # average LoadLockedReq mshr miss latency 741system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 742system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 743system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25679.729391 # average overall mshr miss latency 744system.cpu.dcache.demand_avg_mshr_miss_latency::total 25679.729391 # average overall mshr miss latency 745system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24729.943615 # average overall mshr miss latency 746system.cpu.dcache.overall_avg_mshr_miss_latency::total 24729.943615 # average overall mshr miss latency 747system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183946.998249 # average ReadReq mshr uncacheable latency 748system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183946.998249 # average ReadReq mshr uncacheable latency 749system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.649499 # average WriteReq mshr uncacheable latency 750system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.649499 # average WriteReq mshr uncacheable latency 751system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184057.838672 # average overall mshr uncacheable latency 752system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184057.838672 # average overall mshr uncacheable latency 753system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 754system.cpu.icache.tags.replacements 24189642 # number of replacements 755system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use 756system.cpu.icache.tags.total_refs 414582353 # Total number of references to valid blocks. 757system.cpu.icache.tags.sampled_refs 24190154 # Sample count of references to valid blocks. 758system.cpu.icache.tags.avg_refs 17.138475 # Average number of references to valid blocks. 759system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. 760system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor 761system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy 762system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy 763system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 764system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 765system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id 766system.cpu.icache.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id 767system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 768system.cpu.icache.tags.tag_accesses 462962680 # Number of tag accesses 769system.cpu.icache.tags.data_accesses 462962680 # Number of data accesses 770system.cpu.icache.ReadReq_hits::cpu.inst 414582353 # number of ReadReq hits 771system.cpu.icache.ReadReq_hits::total 414582353 # number of ReadReq hits 772system.cpu.icache.demand_hits::cpu.inst 414582353 # number of demand (read+write) hits 773system.cpu.icache.demand_hits::total 414582353 # number of demand (read+write) hits 774system.cpu.icache.overall_hits::cpu.inst 414582353 # number of overall hits 775system.cpu.icache.overall_hits::total 414582353 # number of overall hits 776system.cpu.icache.ReadReq_misses::cpu.inst 24190164 # number of ReadReq misses 777system.cpu.icache.ReadReq_misses::total 24190164 # number of ReadReq misses 778system.cpu.icache.demand_misses::cpu.inst 24190164 # number of demand (read+write) misses 779system.cpu.icache.demand_misses::total 24190164 # number of demand (read+write) misses 780system.cpu.icache.overall_misses::cpu.inst 24190164 # number of overall misses 781system.cpu.icache.overall_misses::total 24190164 # number of overall misses 782system.cpu.icache.ReadReq_miss_latency::cpu.inst 327340789000 # number of ReadReq miss cycles 783system.cpu.icache.ReadReq_miss_latency::total 327340789000 # number of ReadReq miss cycles 784system.cpu.icache.demand_miss_latency::cpu.inst 327340789000 # number of demand (read+write) miss cycles 785system.cpu.icache.demand_miss_latency::total 327340789000 # number of demand (read+write) miss cycles 786system.cpu.icache.overall_miss_latency::cpu.inst 327340789000 # number of overall miss cycles 787system.cpu.icache.overall_miss_latency::total 327340789000 # number of overall miss cycles 788system.cpu.icache.ReadReq_accesses::cpu.inst 438772517 # number of ReadReq accesses(hits+misses) 789system.cpu.icache.ReadReq_accesses::total 438772517 # number of ReadReq accesses(hits+misses) 790system.cpu.icache.demand_accesses::cpu.inst 438772517 # number of demand (read+write) accesses 791system.cpu.icache.demand_accesses::total 438772517 # number of demand (read+write) accesses 792system.cpu.icache.overall_accesses::cpu.inst 438772517 # number of overall (read+write) accesses 793system.cpu.icache.overall_accesses::total 438772517 # number of overall (read+write) accesses 794system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055131 # miss rate for ReadReq accesses 795system.cpu.icache.ReadReq_miss_rate::total 0.055131 # miss rate for ReadReq accesses 796system.cpu.icache.demand_miss_rate::cpu.inst 0.055131 # miss rate for demand accesses 797system.cpu.icache.demand_miss_rate::total 0.055131 # miss rate for demand accesses 798system.cpu.icache.overall_miss_rate::cpu.inst 0.055131 # miss rate for overall accesses 799system.cpu.icache.overall_miss_rate::total 0.055131 # miss rate for overall accesses 800system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13531.978907 # average ReadReq miss latency 801system.cpu.icache.ReadReq_avg_miss_latency::total 13531.978907 # average ReadReq miss latency 802system.cpu.icache.demand_avg_miss_latency::cpu.inst 13531.978907 # average overall miss latency 803system.cpu.icache.demand_avg_miss_latency::total 13531.978907 # average overall miss latency 804system.cpu.icache.overall_avg_miss_latency::cpu.inst 13531.978907 # average overall miss latency 805system.cpu.icache.overall_avg_miss_latency::total 13531.978907 # average overall miss latency 806system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.icache.fast_writes 0 # number of fast writes performed 813system.cpu.icache.cache_copies 0 # number of cache copies performed 814system.cpu.icache.writebacks::writebacks 24189642 # number of writebacks 815system.cpu.icache.writebacks::total 24189642 # number of writebacks 816system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24190164 # number of ReadReq MSHR misses 817system.cpu.icache.ReadReq_mshr_misses::total 24190164 # number of ReadReq MSHR misses 818system.cpu.icache.demand_mshr_misses::cpu.inst 24190164 # number of demand (read+write) MSHR misses 819system.cpu.icache.demand_mshr_misses::total 24190164 # number of demand (read+write) MSHR misses 820system.cpu.icache.overall_mshr_misses::cpu.inst 24190164 # number of overall MSHR misses 821system.cpu.icache.overall_mshr_misses::total 24190164 # number of overall MSHR misses 822system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 823system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 824system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 825system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 826system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303150626000 # number of ReadReq MSHR miss cycles 827system.cpu.icache.ReadReq_mshr_miss_latency::total 303150626000 # number of ReadReq MSHR miss cycles 828system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303150626000 # number of demand (read+write) MSHR miss cycles 829system.cpu.icache.demand_mshr_miss_latency::total 303150626000 # number of demand (read+write) MSHR miss cycles 830system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303150626000 # number of overall MSHR miss cycles 831system.cpu.icache.overall_mshr_miss_latency::total 303150626000 # number of overall MSHR miss cycles 832system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles 833system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles 834system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles 835system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles 836system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055131 # mshr miss rate for ReadReq accesses 837system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055131 # mshr miss rate for ReadReq accesses 838system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055131 # mshr miss rate for demand accesses 839system.cpu.icache.demand_mshr_miss_rate::total 0.055131 # mshr miss rate for demand accesses 840system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055131 # mshr miss rate for overall accesses 841system.cpu.icache.overall_mshr_miss_rate::total 0.055131 # mshr miss rate for overall accesses 842system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12531.978948 # average ReadReq mshr miss latency 843system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12531.978948 # average ReadReq mshr miss latency 844system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12531.978948 # average overall mshr miss latency 845system.cpu.icache.demand_avg_mshr_miss_latency::total 12531.978948 # average overall mshr miss latency 846system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12531.978948 # average overall mshr miss latency 847system.cpu.icache.overall_avg_mshr_miss_latency::total 12531.978948 # average overall mshr miss latency 848system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency 849system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency 850system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency 851system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency 852system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 853system.cpu.l2cache.tags.replacements 1495284 # number of replacements 854system.cpu.l2cache.tags.tagsinuse 65229.781494 # Cycle average of tags in use 855system.cpu.l2cache.tags.total_refs 65922487 # Total number of references to valid blocks. 856system.cpu.l2cache.tags.sampled_refs 1558468 # Sample count of references to valid blocks. 857system.cpu.l2cache.tags.avg_refs 42.299545 # Average number of references to valid blocks. 858system.cpu.l2cache.tags.warmup_cycle 36600562500 # Cycle when the warmup percentage was hit. 859system.cpu.l2cache.tags.occ_blocks::writebacks 36948.253650 # Average occupied blocks per requestor 860system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 327.788805 # Average occupied blocks per requestor 861system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 379.909026 # Average occupied blocks per requestor 862system.cpu.l2cache.tags.occ_blocks::cpu.inst 7890.502586 # Average occupied blocks per requestor 863system.cpu.l2cache.tags.occ_blocks::cpu.data 19683.327428 # Average occupied blocks per requestor 864system.cpu.l2cache.tags.occ_percent::writebacks 0.563786 # Average percentage of cache occupancy 865system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005002 # Average percentage of cache occupancy 866system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005797 # Average percentage of cache occupancy 867system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120400 # Average percentage of cache occupancy 868system.cpu.l2cache.tags.occ_percent::cpu.data 0.300344 # Average percentage of cache occupancy 869system.cpu.l2cache.tags.occ_percent::total 0.995327 # Average percentage of cache occupancy 870system.cpu.l2cache.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id 871system.cpu.l2cache.tags.occ_task_id_blocks::1024 62947 # Occupied blocks per task id 872system.cpu.l2cache.tags.age_task_id_blocks_1023::4 237 # Occupied blocks per task id 873system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 874system.cpu.l2cache.tags.age_task_id_blocks_1024::1 502 # Occupied blocks per task id 875system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2422 # Occupied blocks per task id 876system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id 877system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54486 # Occupied blocks per task id 878system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id 879system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960495 # Percentage of cache occupancy per task id 880system.cpu.l2cache.tags.tag_accesses 573928107 # Number of tag accesses 881system.cpu.l2cache.tags.data_accesses 573928107 # Number of data accesses 882system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 915811 # number of ReadReq hits 883system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 279303 # number of ReadReq hits 884system.cpu.l2cache.ReadReq_hits::total 1195114 # number of ReadReq hits 885system.cpu.l2cache.WritebackDirty_hits::writebacks 8239619 # number of WritebackDirty hits 886system.cpu.l2cache.WritebackDirty_hits::total 8239619 # number of WritebackDirty hits 887system.cpu.l2cache.WritebackClean_hits::writebacks 24185917 # number of WritebackClean hits 888system.cpu.l2cache.WritebackClean_hits::total 24185917 # number of WritebackClean hits 889system.cpu.l2cache.UpgradeReq_hits::cpu.data 10440 # number of UpgradeReq hits 890system.cpu.l2cache.UpgradeReq_hits::total 10440 # number of UpgradeReq hits 891system.cpu.l2cache.ReadExReq_hits::cpu.data 1637843 # number of ReadExReq hits 892system.cpu.l2cache.ReadExReq_hits::total 1637843 # number of ReadExReq hits 893system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24086368 # number of ReadCleanReq hits 894system.cpu.l2cache.ReadCleanReq_hits::total 24086368 # number of ReadCleanReq hits 895system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6914406 # number of ReadSharedReq hits 896system.cpu.l2cache.ReadSharedReq_hits::total 6914406 # number of ReadSharedReq hits 897system.cpu.l2cache.InvalidateReq_hits::cpu.data 709945 # number of InvalidateReq hits 898system.cpu.l2cache.InvalidateReq_hits::total 709945 # number of InvalidateReq hits 899system.cpu.l2cache.demand_hits::cpu.dtb.walker 915811 # number of demand (read+write) hits 900system.cpu.l2cache.demand_hits::cpu.itb.walker 279303 # number of demand (read+write) hits 901system.cpu.l2cache.demand_hits::cpu.inst 24086368 # number of demand (read+write) hits 902system.cpu.l2cache.demand_hits::cpu.data 8552249 # number of demand (read+write) hits 903system.cpu.l2cache.demand_hits::total 33833731 # number of demand (read+write) hits 904system.cpu.l2cache.overall_hits::cpu.dtb.walker 915811 # number of overall hits 905system.cpu.l2cache.overall_hits::cpu.itb.walker 279303 # number of overall hits 906system.cpu.l2cache.overall_hits::cpu.inst 24086368 # number of overall hits 907system.cpu.l2cache.overall_hits::cpu.data 8552249 # number of overall hits 908system.cpu.l2cache.overall_hits::total 33833731 # number of overall hits 909system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5557 # number of ReadReq misses 910system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4848 # number of ReadReq misses 911system.cpu.l2cache.ReadReq_misses::total 10405 # number of ReadReq misses 912system.cpu.l2cache.UpgradeReq_misses::cpu.data 37520 # number of UpgradeReq misses 913system.cpu.l2cache.UpgradeReq_misses::total 37520 # number of UpgradeReq misses 914system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 915system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 916system.cpu.l2cache.ReadExReq_misses::cpu.data 626190 # number of ReadExReq misses 917system.cpu.l2cache.ReadExReq_misses::total 626190 # number of ReadExReq misses 918system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 103793 # number of ReadCleanReq misses 919system.cpu.l2cache.ReadCleanReq_misses::total 103793 # number of ReadCleanReq misses 920system.cpu.l2cache.ReadSharedReq_misses::cpu.data 319194 # number of ReadSharedReq misses 921system.cpu.l2cache.ReadSharedReq_misses::total 319194 # number of ReadSharedReq misses 922system.cpu.l2cache.InvalidateReq_misses::cpu.data 528774 # number of InvalidateReq misses 923system.cpu.l2cache.InvalidateReq_misses::total 528774 # number of InvalidateReq misses 924system.cpu.l2cache.demand_misses::cpu.dtb.walker 5557 # number of demand (read+write) misses 925system.cpu.l2cache.demand_misses::cpu.itb.walker 4848 # number of demand (read+write) misses 926system.cpu.l2cache.demand_misses::cpu.inst 103793 # number of demand (read+write) misses 927system.cpu.l2cache.demand_misses::cpu.data 945384 # number of demand (read+write) misses 928system.cpu.l2cache.demand_misses::total 1059582 # number of demand (read+write) misses 929system.cpu.l2cache.overall_misses::cpu.dtb.walker 5557 # number of overall misses 930system.cpu.l2cache.overall_misses::cpu.itb.walker 4848 # number of overall misses 931system.cpu.l2cache.overall_misses::cpu.inst 103793 # number of overall misses 932system.cpu.l2cache.overall_misses::cpu.data 945384 # number of overall misses 933system.cpu.l2cache.overall_misses::total 1059582 # number of overall misses 934system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 763202000 # number of ReadReq miss cycles 935system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 663006000 # number of ReadReq miss cycles 936system.cpu.l2cache.ReadReq_miss_latency::total 1426208000 # number of ReadReq miss cycles 937system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1483103000 # number of UpgradeReq miss cycles 938system.cpu.l2cache.UpgradeReq_miss_latency::total 1483103000 # number of UpgradeReq miss cycles 939system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 940system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles 941system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83070292000 # number of ReadExReq miss cycles 942system.cpu.l2cache.ReadExReq_miss_latency::total 83070292000 # number of ReadExReq miss cycles 943system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13727586500 # number of ReadCleanReq miss cycles 944system.cpu.l2cache.ReadCleanReq_miss_latency::total 13727586500 # number of ReadCleanReq miss cycles 945system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42966847500 # number of ReadSharedReq miss cycles 946system.cpu.l2cache.ReadSharedReq_miss_latency::total 42966847500 # number of ReadSharedReq miss cycles 947system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73371785500 # number of InvalidateReq miss cycles 948system.cpu.l2cache.InvalidateReq_miss_latency::total 73371785500 # number of InvalidateReq miss cycles 949system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 763202000 # number of demand (read+write) miss cycles 950system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 663006000 # number of demand (read+write) miss cycles 951system.cpu.l2cache.demand_miss_latency::cpu.inst 13727586500 # number of demand (read+write) miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.data 126037139500 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::total 141190934000 # number of demand (read+write) miss cycles 954system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 763202000 # number of overall miss cycles 955system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 663006000 # number of overall miss cycles 956system.cpu.l2cache.overall_miss_latency::cpu.inst 13727586500 # number of overall miss cycles 957system.cpu.l2cache.overall_miss_latency::cpu.data 126037139500 # number of overall miss cycles 958system.cpu.l2cache.overall_miss_latency::total 141190934000 # number of overall miss cycles 959system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 921368 # number of ReadReq accesses(hits+misses) 960system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 284151 # number of ReadReq accesses(hits+misses) 961system.cpu.l2cache.ReadReq_accesses::total 1205519 # number of ReadReq accesses(hits+misses) 962system.cpu.l2cache.WritebackDirty_accesses::writebacks 8239619 # number of WritebackDirty accesses(hits+misses) 963system.cpu.l2cache.WritebackDirty_accesses::total 8239619 # number of WritebackDirty accesses(hits+misses) 964system.cpu.l2cache.WritebackClean_accesses::writebacks 24185917 # number of WritebackClean accesses(hits+misses) 965system.cpu.l2cache.WritebackClean_accesses::total 24185917 # number of WritebackClean accesses(hits+misses) 966system.cpu.l2cache.UpgradeReq_accesses::cpu.data 47960 # number of UpgradeReq accesses(hits+misses) 967system.cpu.l2cache.UpgradeReq_accesses::total 47960 # number of UpgradeReq accesses(hits+misses) 968system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 969system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 970system.cpu.l2cache.ReadExReq_accesses::cpu.data 2264033 # number of ReadExReq accesses(hits+misses) 971system.cpu.l2cache.ReadExReq_accesses::total 2264033 # number of ReadExReq accesses(hits+misses) 972system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24190161 # number of ReadCleanReq accesses(hits+misses) 973system.cpu.l2cache.ReadCleanReq_accesses::total 24190161 # number of ReadCleanReq accesses(hits+misses) 974system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7233600 # number of ReadSharedReq accesses(hits+misses) 975system.cpu.l2cache.ReadSharedReq_accesses::total 7233600 # number of ReadSharedReq accesses(hits+misses) 976system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238719 # number of InvalidateReq accesses(hits+misses) 977system.cpu.l2cache.InvalidateReq_accesses::total 1238719 # number of InvalidateReq accesses(hits+misses) 978system.cpu.l2cache.demand_accesses::cpu.dtb.walker 921368 # number of demand (read+write) accesses 979system.cpu.l2cache.demand_accesses::cpu.itb.walker 284151 # number of demand (read+write) accesses 980system.cpu.l2cache.demand_accesses::cpu.inst 24190161 # number of demand (read+write) accesses 981system.cpu.l2cache.demand_accesses::cpu.data 9497633 # number of demand (read+write) accesses 982system.cpu.l2cache.demand_accesses::total 34893313 # number of demand (read+write) accesses 983system.cpu.l2cache.overall_accesses::cpu.dtb.walker 921368 # number of overall (read+write) accesses 984system.cpu.l2cache.overall_accesses::cpu.itb.walker 284151 # number of overall (read+write) accesses 985system.cpu.l2cache.overall_accesses::cpu.inst 24190161 # number of overall (read+write) accesses 986system.cpu.l2cache.overall_accesses::cpu.data 9497633 # number of overall (read+write) accesses 987system.cpu.l2cache.overall_accesses::total 34893313 # number of overall (read+write) accesses 988system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006031 # miss rate for ReadReq accesses 989system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017061 # miss rate for ReadReq accesses 990system.cpu.l2cache.ReadReq_miss_rate::total 0.008631 # miss rate for ReadReq accesses 991system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782319 # miss rate for UpgradeReq accesses 992system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782319 # miss rate for UpgradeReq accesses 993system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 994system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 995system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.276582 # miss rate for ReadExReq accesses 996system.cpu.l2cache.ReadExReq_miss_rate::total 0.276582 # miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004291 # miss rate for ReadCleanReq accesses 998system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004291 # miss rate for ReadCleanReq accesses 999system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044127 # miss rate for ReadSharedReq accesses 1000system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044127 # miss rate for ReadSharedReq accesses 1001system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.426872 # miss rate for InvalidateReq accesses 1002system.cpu.l2cache.InvalidateReq_miss_rate::total 0.426872 # miss rate for InvalidateReq accesses 1003system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006031 # miss rate for demand accesses 1004system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017061 # miss rate for demand accesses 1005system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004291 # miss rate for demand accesses 1006system.cpu.l2cache.demand_miss_rate::cpu.data 0.099539 # miss rate for demand accesses 1007system.cpu.l2cache.demand_miss_rate::total 0.030366 # miss rate for demand accesses 1008system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006031 # miss rate for overall accesses 1009system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017061 # miss rate for overall accesses 1010system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004291 # miss rate for overall accesses 1011system.cpu.l2cache.overall_miss_rate::cpu.data 0.099539 # miss rate for overall accesses 1012system.cpu.l2cache.overall_miss_rate::total 0.030366 # miss rate for overall accesses 1013system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137340.651431 # average ReadReq miss latency 1014system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136758.663366 # average ReadReq miss latency 1015system.cpu.l2cache.ReadReq_avg_miss_latency::total 137069.485824 # average ReadReq miss latency 1016system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39528.331557 # average UpgradeReq miss latency 1017system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39528.331557 # average UpgradeReq miss latency 1018system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1019system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132659.882783 # average ReadExReq miss latency 1021system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132659.882783 # average ReadExReq miss latency 1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132259.270856 # average ReadCleanReq miss latency 1023system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132259.270856 # average ReadCleanReq miss latency 1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134610.448505 # average ReadSharedReq miss latency 1025system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134610.448505 # average ReadSharedReq miss latency 1026system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138758.307897 # average InvalidateReq miss latency 1027system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138758.307897 # average InvalidateReq miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137340.651431 # average overall miss latency 1029system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136758.663366 # average overall miss latency 1030system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132259.270856 # average overall miss latency 1031system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133318.460541 # average overall miss latency 1032system.cpu.l2cache.demand_avg_miss_latency::total 133251.540702 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137340.651431 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136758.663366 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132259.270856 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133318.460541 # average overall miss latency 1037system.cpu.l2cache.overall_avg_miss_latency::total 133251.540702 # average overall miss latency 1038system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1041system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1043system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1044system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1045system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1046system.cpu.l2cache.writebacks::writebacks 1267142 # number of writebacks 1047system.cpu.l2cache.writebacks::total 1267142 # number of writebacks 1048system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1049system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1050system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1051system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1053system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1054system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 1055system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1056system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1057system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1058system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5557 # number of ReadReq MSHR misses 1059system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4848 # number of ReadReq MSHR misses 1060system.cpu.l2cache.ReadReq_mshr_misses::total 10405 # number of ReadReq MSHR misses 1061system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses 1062system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses 1063system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37520 # number of UpgradeReq MSHR misses 1064system.cpu.l2cache.UpgradeReq_mshr_misses::total 37520 # number of UpgradeReq MSHR misses 1065system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1066system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 626190 # number of ReadExReq MSHR misses 1068system.cpu.l2cache.ReadExReq_mshr_misses::total 626190 # number of ReadExReq MSHR misses 1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 103790 # number of ReadCleanReq MSHR misses 1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 103790 # number of ReadCleanReq MSHR misses 1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 319173 # number of ReadSharedReq MSHR misses 1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 319173 # number of ReadSharedReq MSHR misses 1073system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 528774 # number of InvalidateReq MSHR misses 1074system.cpu.l2cache.InvalidateReq_mshr_misses::total 528774 # number of InvalidateReq MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5557 # number of demand (read+write) MSHR misses 1076system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4848 # number of demand (read+write) MSHR misses 1077system.cpu.l2cache.demand_mshr_misses::cpu.inst 103790 # number of demand (read+write) MSHR misses 1078system.cpu.l2cache.demand_mshr_misses::cpu.data 945363 # number of demand (read+write) MSHR misses 1079system.cpu.l2cache.demand_mshr_misses::total 1059558 # number of demand (read+write) MSHR misses 1080system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5557 # number of overall MSHR misses 1081system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4848 # number of overall MSHR misses 1082system.cpu.l2cache.overall_mshr_misses::cpu.inst 103790 # number of overall MSHR misses 1083system.cpu.l2cache.overall_mshr_misses::cpu.data 945363 # number of overall MSHR misses 1084system.cpu.l2cache.overall_mshr_misses::total 1059558 # number of overall MSHR misses 1085system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 1086system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 1087system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable 1088system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 1089system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 1090system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 1091system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 1092system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses 1093system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 707632000 # number of ReadReq MSHR miss cycles 1094system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 614526000 # number of ReadReq MSHR miss cycles 1095system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1322158000 # number of ReadReq MSHR miss cycles 1096system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2655683000 # number of UpgradeReq MSHR miss cycles 1097system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2655683000 # number of UpgradeReq MSHR miss cycles 1098system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1099system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles 1100system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 76808392000 # number of ReadExReq MSHR miss cycles 1101system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 76808392000 # number of ReadExReq MSHR miss cycles 1102system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12689415000 # number of ReadCleanReq MSHR miss cycles 1103system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12689415000 # number of ReadCleanReq MSHR miss cycles 1104system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39772846000 # number of ReadSharedReq MSHR miss cycles 1105system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39772846000 # number of ReadSharedReq MSHR miss cycles 1106system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 68084045500 # number of InvalidateReq MSHR miss cycles 1107system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 68084045500 # number of InvalidateReq MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 707632000 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 614526000 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12689415000 # number of demand (read+write) MSHR miss cycles 1111system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116581238000 # number of demand (read+write) MSHR miss cycles 1112system.cpu.l2cache.demand_mshr_miss_latency::total 130592811000 # number of demand (read+write) MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 707632000 # number of overall MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 614526000 # number of overall MSHR miss cycles 1115system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12689415000 # number of overall MSHR miss cycles 1116system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116581238000 # number of overall MSHR miss cycles 1117system.cpu.l2cache.overall_mshr_miss_latency::total 130592811000 # number of overall MSHR miss cycles 1118system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles 1119system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777189500 # number of ReadReq MSHR uncacheable cycles 1120system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11713263500 # number of ReadReq MSHR uncacheable cycles 1121system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819359500 # number of WriteReq MSHR uncacheable cycles 1122system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819359500 # number of WriteReq MSHR uncacheable cycles 1123system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles 1124system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11596549000 # number of overall MSHR uncacheable cycles 1125system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17532623000 # number of overall MSHR uncacheable cycles 1126system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for ReadReq accesses 1127system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for ReadReq accesses 1128system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008631 # mshr miss rate for ReadReq accesses 1129system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1130system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1131system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782319 # mshr miss rate for UpgradeReq accesses 1132system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782319 # mshr miss rate for UpgradeReq accesses 1133system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1134system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1135system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.276582 # mshr miss rate for ReadExReq accesses 1136system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.276582 # mshr miss rate for ReadExReq accesses 1137system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for ReadCleanReq accesses 1138system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004291 # mshr miss rate for ReadCleanReq accesses 1139system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044124 # mshr miss rate for ReadSharedReq accesses 1140system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044124 # mshr miss rate for ReadSharedReq accesses 1141system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.426872 # mshr miss rate for InvalidateReq accesses 1142system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.426872 # mshr miss rate for InvalidateReq accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for demand accesses 1146system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099537 # mshr miss rate for demand accesses 1147system.cpu.l2cache.demand_mshr_miss_rate::total 0.030366 # mshr miss rate for demand accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for overall accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for overall accesses 1150system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for overall accesses 1151system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099537 # mshr miss rate for overall accesses 1152system.cpu.l2cache.overall_mshr_miss_rate::total 0.030366 # mshr miss rate for overall accesses 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average ReadReq mshr miss latency 1154system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average ReadReq mshr miss latency 1155system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127069.485824 # average ReadReq mshr miss latency 1156system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70780.463753 # average UpgradeReq mshr miss latency 1157system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70780.463753 # average UpgradeReq mshr miss latency 1158system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1159system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1160system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122659.882783 # average ReadExReq mshr miss latency 1161system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122659.882783 # average ReadExReq mshr miss latency 1162system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122260.477888 # average ReadCleanReq mshr miss latency 1163system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122260.477888 # average ReadCleanReq mshr miss latency 1164system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124612.188374 # average ReadSharedReq mshr miss latency 1165system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124612.188374 # average ReadSharedReq mshr miss latency 1166system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128758.307897 # average InvalidateReq mshr miss latency 1167system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128758.307897 # average InvalidateReq mshr miss latency 1168system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency 1169system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency 1170system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency 1171system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency 1172system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency 1173system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency 1174system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency 1175system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency 1178system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency 1179system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171445.217675 # average ReadReq mshr uncacheable latency 1180system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136191.236658 # average ReadReq mshr uncacheable latency 1181system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.551831 # average WriteReq mshr uncacheable latency 1182system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.551831 # average WriteReq mshr uncacheable latency 1183system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency 1184system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172047.965224 # average overall mshr uncacheable latency 1185system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146456.687717 # average overall mshr uncacheable latency 1186system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1187system.cpu.toL2Bus.snoop_filter.tot_requests 70595106 # Total number of requests made to the snoop filter. 1188system.cpu.toL2Bus.snoop_filter.hit_single_requests 35668602 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1189system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4412 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1190system.cpu.toL2Bus.snoop_filter.tot_snoops 2257 # Total number of snoops made to the snoop filter. 1191system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2257 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1192system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1193system.cpu.toL2Bus.trans_dist::ReadReq 1731880 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::ReadResp 33156424 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::WritebackDirty 9613409 # Transaction distribution 1198system.cpu.toL2Bus.trans_dist::WritebackClean 24185917 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::CleanEvict 2732498 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::UpgradeReq 47963 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::UpgradeResp 47964 # Transaction distribution 1203system.cpu.toL2Bus.trans_dist::ReadExReq 2264033 # Transaction distribution 1204system.cpu.toL2Bus.trans_dist::ReadExResp 2264033 # Transaction distribution 1205system.cpu.toL2Bus.trans_dist::ReadCleanReq 24190164 # Transaction distribution 1206system.cpu.toL2Bus.trans_dist::ReadSharedReq 7242479 # Transaction distribution 1207system.cpu.toL2Bus.trans_dist::InvalidateReq 1345383 # Transaction distribution 1208system.cpu.toL2Bus.trans_dist::InvalidateResp 1238719 # Transaction distribution 1209system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72670859 # Packet count per connected master and slave (bytes) 1210system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32439334 # Packet count per connected master and slave (bytes) 1211system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687653 # Packet count per connected master and slave (bytes) 1212system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163740 # Packet count per connected master and slave (bytes) 1213system.cpu.toL2Bus.pkt_count::total 107961586 # Packet count per connected master and slave (bytes) 1214system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3099416704 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135424530 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2273208 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7370944 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu.toL2Bus.pkt_size::total 4244485386 # Cumulative packet size per connected master and slave (bytes) 1219system.cpu.toL2Bus.snoops 2167477 # Total snoops (count) 1220system.cpu.toL2Bus.snoop_fanout::samples 38466398 # Request fanout histogram 1221system.cpu.toL2Bus.snoop_fanout::mean 0.018246 # Request fanout histogram 1222system.cpu.toL2Bus.snoop_fanout::stdev 0.133841 # Request fanout histogram 1223system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1224system.cpu.toL2Bus.snoop_fanout::0 37764532 98.18% 98.18% # Request fanout histogram 1225system.cpu.toL2Bus.snoop_fanout::1 701866 1.82% 100.00% # Request fanout histogram 1226system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1227system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1230system.cpu.toL2Bus.snoop_fanout::total 38466398 # Request fanout histogram 1231system.cpu.toL2Bus.reqLayer0.occupancy 68278869995 # Layer occupancy (ticks) 1232system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1233system.cpu.toL2Bus.snoopLayer0.occupancy 1476392 # Layer occupancy (ticks) 1234system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1235system.cpu.toL2Bus.respLayer0.occupancy 36370852681 # Layer occupancy (ticks) 1236system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1237system.cpu.toL2Bus.respLayer1.occupancy 14941078957 # Layer occupancy (ticks) 1238system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1239system.cpu.toL2Bus.respLayer2.occupancy 403557888 # Layer occupancy (ticks) 1240system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1241system.cpu.toL2Bus.respLayer3.occupancy 1242412419 # Layer occupancy (ticks) 1242system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1243system.iobus.trans_dist::ReadReq 40327 # Transaction distribution 1244system.iobus.trans_dist::ReadResp 40327 # Transaction distribution 1245system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1246system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1247system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1252system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1253system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1254system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1255system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1256system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1257system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1258system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1259system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1260system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1261system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1262system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1263system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231012 # Packet count per connected master and slave (bytes) 1264system.iobus.pkt_count_system.realview.ide.dma::total 231012 # Packet count per connected master and slave (bytes) 1265system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1266system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1267system.iobus.pkt_count::total 353796 # Packet count per connected master and slave (bytes) 1268system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1273system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1274system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1275system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1276system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1277system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1278system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1279system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1280system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1281system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1282system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1283system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1284system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334480 # Cumulative packet size per connected master and slave (bytes) 1285system.iobus.pkt_size_system.realview.ide.dma::total 7334480 # Cumulative packet size per connected master and slave (bytes) 1286system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1287system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1288system.iobus.pkt_size::total 7492400 # Cumulative packet size per connected master and slave (bytes) 1289system.iobus.reqLayer0.occupancy 42171500 # Layer occupancy (ticks) 1290system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1291system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1292system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1293system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1294system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1295system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1296system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 1298system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1299system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 1300system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1301system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1302system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1303system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1304system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1305system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 1306system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1307system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 1308system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1309system.iobus.reqLayer23.occupancy 25807000 # Layer occupancy (ticks) 1310system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1311system.iobus.reqLayer24.occupancy 170000 # Layer occupancy (ticks) 1312system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1313system.iobus.reqLayer25.occupancy 34147000 # Layer occupancy (ticks) 1314system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1315system.iobus.reqLayer26.occupancy 120500 # Layer occupancy (ticks) 1316system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1317system.iobus.reqLayer27.occupancy 565729644 # Layer occupancy (ticks) 1318system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1319system.iobus.reqLayer28.occupancy 42000 # Layer occupancy (ticks) 1320system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1321system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1322system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1323system.iobus.respLayer3.occupancy 147772000 # Layer occupancy (ticks) 1324system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1325system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1326system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1327system.iocache.tags.replacements 115488 # number of replacements 1328system.iocache.tags.tagsinuse 10.440019 # Cycle average of tags in use 1329system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1330system.iocache.tags.sampled_refs 115504 # Sample count of references to valid blocks. 1331system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1332system.iocache.tags.warmup_cycle 13160148501000 # Cycle when the warmup percentage was hit. 1333system.iocache.tags.occ_blocks::realview.ethernet 3.520841 # Average occupied blocks per requestor 1334system.iocache.tags.occ_blocks::realview.ide 6.919178 # Average occupied blocks per requestor 1335system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy 1336system.iocache.tags.occ_percent::realview.ide 0.432449 # Average percentage of cache occupancy 1337system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy 1338system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1339system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1340system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1341system.iocache.tags.tag_accesses 1039911 # Number of tag accesses 1342system.iocache.tags.data_accesses 1039911 # Number of data accesses 1343system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1344system.iocache.ReadReq_misses::realview.ide 8842 # number of ReadReq misses 1345system.iocache.ReadReq_misses::total 8879 # number of ReadReq misses 1346system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1347system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1348system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1349system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1350system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1351system.iocache.demand_misses::realview.ide 8842 # number of demand (read+write) misses 1352system.iocache.demand_misses::total 8882 # number of demand (read+write) misses 1353system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1354system.iocache.overall_misses::realview.ide 8842 # number of overall misses 1355system.iocache.overall_misses::total 8882 # number of overall misses 1356system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles 1357system.iocache.ReadReq_miss_latency::realview.ide 1658170108 # number of ReadReq miss cycles 1358system.iocache.ReadReq_miss_latency::total 1663256608 # number of ReadReq miss cycles 1359system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1360system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1361system.iocache.WriteLineReq_miss_latency::realview.ide 13863609036 # number of WriteLineReq miss cycles 1362system.iocache.WriteLineReq_miss_latency::total 13863609036 # number of WriteLineReq miss cycles 1363system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles 1364system.iocache.demand_miss_latency::realview.ide 1658170108 # number of demand (read+write) miss cycles 1365system.iocache.demand_miss_latency::total 1663607608 # number of demand (read+write) miss cycles 1366system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles 1367system.iocache.overall_miss_latency::realview.ide 1658170108 # number of overall miss cycles 1368system.iocache.overall_miss_latency::total 1663607608 # number of overall miss cycles 1369system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1370system.iocache.ReadReq_accesses::realview.ide 8842 # number of ReadReq accesses(hits+misses) 1371system.iocache.ReadReq_accesses::total 8879 # number of ReadReq accesses(hits+misses) 1372system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1373system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1374system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1375system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1376system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1377system.iocache.demand_accesses::realview.ide 8842 # number of demand (read+write) accesses 1378system.iocache.demand_accesses::total 8882 # number of demand (read+write) accesses 1379system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1380system.iocache.overall_accesses::realview.ide 8842 # number of overall (read+write) accesses 1381system.iocache.overall_accesses::total 8882 # number of overall (read+write) accesses 1382system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1383system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1385system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1387system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1388system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1389system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1390system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1391system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1392system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1393system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1394system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1395system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency 1396system.iocache.ReadReq_avg_miss_latency::realview.ide 187533.375707 # average ReadReq miss latency 1397system.iocache.ReadReq_avg_miss_latency::total 187324.767204 # average ReadReq miss latency 1398system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1399system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1400system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.584077 # average WriteLineReq miss latency 1401system.iocache.WriteLineReq_avg_miss_latency::total 129974.584077 # average WriteLineReq miss latency 1402system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency 1403system.iocache.demand_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency 1404system.iocache.demand_avg_miss_latency::total 187301.014186 # average overall miss latency 1405system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency 1406system.iocache.overall_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency 1407system.iocache.overall_avg_miss_latency::total 187301.014186 # average overall miss latency 1408system.iocache.blocked_cycles::no_mshrs 34622 # number of cycles access was blocked 1409system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1410system.iocache.blocked::no_mshrs 3502 # number of cycles access was blocked 1411system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1412system.iocache.avg_blocked_cycles::no_mshrs 9.886351 # average number of cycles each access was blocked 1413system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1414system.iocache.fast_writes 0 # number of fast writes performed 1415system.iocache.cache_copies 0 # number of cache copies performed 1416system.iocache.writebacks::writebacks 106631 # number of writebacks 1417system.iocache.writebacks::total 106631 # number of writebacks 1418system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1419system.iocache.ReadReq_mshr_misses::realview.ide 8842 # number of ReadReq MSHR misses 1420system.iocache.ReadReq_mshr_misses::total 8879 # number of ReadReq MSHR misses 1421system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1422system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1423system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1424system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1425system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1426system.iocache.demand_mshr_misses::realview.ide 8842 # number of demand (read+write) MSHR misses 1427system.iocache.demand_mshr_misses::total 8882 # number of demand (read+write) MSHR misses 1428system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1429system.iocache.overall_mshr_misses::realview.ide 8842 # number of overall MSHR misses 1430system.iocache.overall_mshr_misses::total 8882 # number of overall MSHR misses 1431system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles 1432system.iocache.ReadReq_mshr_miss_latency::realview.ide 1216070108 # number of ReadReq MSHR miss cycles 1433system.iocache.ReadReq_mshr_miss_latency::total 1219306608 # number of ReadReq MSHR miss cycles 1434system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1435system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1436system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530409036 # number of WriteLineReq MSHR miss cycles 1437system.iocache.WriteLineReq_mshr_miss_latency::total 8530409036 # number of WriteLineReq MSHR miss cycles 1438system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles 1439system.iocache.demand_mshr_miss_latency::realview.ide 1216070108 # number of demand (read+write) MSHR miss cycles 1440system.iocache.demand_mshr_miss_latency::total 1219507608 # number of demand (read+write) MSHR miss cycles 1441system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles 1442system.iocache.overall_mshr_miss_latency::realview.ide 1216070108 # number of overall MSHR miss cycles 1443system.iocache.overall_mshr_miss_latency::total 1219507608 # number of overall MSHR miss cycles 1444system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1445system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1446system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1447system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1448system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1449system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1450system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1451system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1452system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1453system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1454system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1455system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1456system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1457system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency 1458system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137533.375707 # average ReadReq mshr miss latency 1459system.iocache.ReadReq_avg_mshr_miss_latency::total 137324.767204 # average ReadReq mshr miss latency 1460system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1461system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1462system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.584077 # average WriteLineReq mshr miss latency 1463system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.584077 # average WriteLineReq mshr miss latency 1464system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency 1465system.iocache.demand_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency 1466system.iocache.demand_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency 1467system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency 1468system.iocache.overall_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency 1469system.iocache.overall_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency 1470system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1471system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1472system.membus.trans_dist::ReadResp 528253 # Transaction distribution 1473system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1474system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1475system.membus.trans_dist::WritebackDirty 1373773 # Transaction distribution 1476system.membus.trans_dist::CleanEvict 233285 # Transaction distribution 1477system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution 1478system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1479system.membus.trans_dist::UpgradeResp 38309 # Transaction distribution 1480system.membus.trans_dist::ReadExReq 1154179 # Transaction distribution 1481system.membus.trans_dist::ReadExResp 1154179 # Transaction distribution 1482system.membus.trans_dist::ReadSharedReq 442247 # Transaction distribution 1483system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 1484system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 1485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1486system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1487system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) 1488system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4854992 # Packet count per connected master and slave (bytes) 1489system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4984644 # Packet count per connected master and slave (bytes) 1490system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341559 # Packet count per connected master and slave (bytes) 1491system.membus.pkt_count_system.iocache.mem_side::total 341559 # Packet count per connected master and slave (bytes) 1492system.membus.pkt_count::total 5326203 # Packet count per connected master and slave (bytes) 1493system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1494system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1495system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) 1496system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186025772 # Cumulative packet size per connected master and slave (bytes) 1497system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186196178 # Cumulative packet size per connected master and slave (bytes) 1498system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7238272 # Cumulative packet size per connected master and slave (bytes) 1499system.membus.pkt_size_system.iocache.mem_side::total 7238272 # Cumulative packet size per connected master and slave (bytes) 1500system.membus.pkt_size::total 193434450 # Cumulative packet size per connected master and slave (bytes) 1501system.membus.snoops 3077 # Total snoops (count) 1502system.membus.snoop_fanout::samples 3470793 # Request fanout histogram 1503system.membus.snoop_fanout::mean 1 # Request fanout histogram 1504system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1505system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1506system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1507system.membus.snoop_fanout::1 3470793 100.00% 100.00% # Request fanout histogram 1508system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1509system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1510system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1511system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1512system.membus.snoop_fanout::total 3470793 # Request fanout histogram 1513system.membus.reqLayer0.occupancy 102553500 # Layer occupancy (ticks) 1514system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1515system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1516system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1517system.membus.reqLayer2.occupancy 5511000 # Layer occupancy (ticks) 1518system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1519system.membus.reqLayer5.occupancy 9297161713 # Layer occupancy (ticks) 1520system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1521system.membus.respLayer2.occupancy 8798501817 # Layer occupancy (ticks) 1522system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1523system.membus.respLayer3.occupancy 227863618 # Layer occupancy (ticks) 1524system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1525system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1526system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1527system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1528system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1529system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1530system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1531system.realview.ethernet.txBytes 966 # Bytes Transmitted 1532system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1533system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1534system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1535system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1536system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1537system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1538system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1539system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1540system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1541system.realview.ethernet.totPackets 3 # Total Packets 1542system.realview.ethernet.totBytes 966 # Total Bytes 1543system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1544system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1545system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1546system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1547system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1548system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1549system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1550system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1551system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1552system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1553system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1554system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1555system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1556system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1557system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1558system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1559system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1560system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1561system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1562system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1563system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1564system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1565system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1566system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1567system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1568system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1569system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1570system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1571system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1572system.realview.ethernet.droppedPackets 0 # number of packets dropped 1573system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1574system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1575system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1576system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1577 1578---------- End Simulation Statistics ---------- 1579