stats.txt revision 10852:5b58b4cccfd7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.610037 # Number of seconds simulated 4sim_ticks 51610036853000 # Number of ticks simulated 5final_tick 51610036853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 188716 # Simulator instruction rate (inst/s) 8host_op_rate 221745 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10246213919 # Simulator tick rate (ticks/s) 10host_mem_usage 724572 # Number of bytes of host memory used 11host_seconds 5036.99 # Real time elapsed on the host 12sim_insts 950561948 # Number of instructions simulated 13sim_ops 1116924449 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 410048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 340288 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10352448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 67122824 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 411200 # Number of bytes read from this memory 21system.physmem.bytes_read::total 78636808 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10352448 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10352448 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 95202624 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 95223204 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 6407 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5317 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 161757 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1048807 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6425 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1228713 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1487541 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1490114 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 7945 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 6593 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 200590 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1300577 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7967 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1523673 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 200590 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 200590 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1844653 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1845052 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1844653 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 7945 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 6593 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 200590 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1300976 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7967 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3368725 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1228713 # Number of read requests accepted 55system.physmem.writeReqs 2143008 # Number of write requests accepted 56system.physmem.readBursts 1228713 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 2143008 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 78600192 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 37440 # Total number of bytes read from write queue 60system.physmem.bytesWritten 133928256 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 78636808 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 137008420 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 585 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 50360 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 39728 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 75722 # Per bank write bursts 67system.physmem.perBankRdBursts::1 79954 # Per bank write bursts 68system.physmem.perBankRdBursts::2 72878 # Per bank write bursts 69system.physmem.perBankRdBursts::3 71278 # Per bank write bursts 70system.physmem.perBankRdBursts::4 72651 # Per bank write bursts 71system.physmem.perBankRdBursts::5 79829 # Per bank write bursts 72system.physmem.perBankRdBursts::6 73600 # Per bank write bursts 73system.physmem.perBankRdBursts::7 73320 # Per bank write bursts 74system.physmem.perBankRdBursts::8 65239 # Per bank write bursts 75system.physmem.perBankRdBursts::9 127420 # Per bank write bursts 76system.physmem.perBankRdBursts::10 73665 # Per bank write bursts 77system.physmem.perBankRdBursts::11 77478 # Per bank write bursts 78system.physmem.perBankRdBursts::12 72459 # Per bank write bursts 79system.physmem.perBankRdBursts::13 72712 # Per bank write bursts 80system.physmem.perBankRdBursts::14 69098 # Per bank write bursts 81system.physmem.perBankRdBursts::15 70825 # Per bank write bursts 82system.physmem.perBankWrBursts::0 130775 # Per bank write bursts 83system.physmem.perBankWrBursts::1 132563 # Per bank write bursts 84system.physmem.perBankWrBursts::2 131683 # Per bank write bursts 85system.physmem.perBankWrBursts::3 133448 # Per bank write bursts 86system.physmem.perBankWrBursts::4 132375 # Per bank write bursts 87system.physmem.perBankWrBursts::5 136941 # Per bank write bursts 88system.physmem.perBankWrBursts::6 129100 # Per bank write bursts 89system.physmem.perBankWrBursts::7 132855 # Per bank write bursts 90system.physmem.perBankWrBursts::8 124239 # Per bank write bursts 91system.physmem.perBankWrBursts::9 131924 # Per bank write bursts 92system.physmem.perBankWrBursts::10 130753 # Per bank write bursts 93system.physmem.perBankWrBursts::11 132768 # Per bank write bursts 94system.physmem.perBankWrBursts::12 128150 # Per bank write bursts 95system.physmem.perBankWrBursts::13 130180 # Per bank write bursts 96system.physmem.perBankWrBursts::14 126529 # Per bank write bursts 97system.physmem.perBankWrBursts::15 128346 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 140 # Number of times write queue was full causing retry 100system.physmem.totGap 51610035211500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1228698 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 2140435 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1157126 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 64351 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 755 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 546 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 482 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 776 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 503 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1798 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 175 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 113 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 104 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 52200 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 61876 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 103140 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 107216 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 115340 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 154284 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 127380 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 116704 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 115742 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 109222 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 108713 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 142144 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 115995 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 110189 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 122630 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 110947 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 107019 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 104847 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 5989 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 5575 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 6143 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 7595 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 8109 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 7187 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 6881 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 8026 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 6843 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 6405 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 5844 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 5760 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 4978 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 3912 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 3857 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 3012 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 2330 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 1631 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 1213 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 768 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 1002 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 546 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 495 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 484 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 447 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 404 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 345 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 339 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 179 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 312 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 733749 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 289.646732 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 167.469062 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 324.982397 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 301017 41.02% 41.02% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 179214 24.42% 65.45% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 65174 8.88% 74.33% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 36623 4.99% 79.32% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 25257 3.44% 82.76% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 17346 2.36% 85.13% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 13099 1.79% 86.91% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 11628 1.58% 88.50% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 84391 11.50% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 733749 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 100720 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 12.193388 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 124.138953 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-1023 100718 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 100720 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 100720 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.776698 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.274786 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 17.101890 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-31 96977 96.28% 96.28% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::32-47 2012 2.00% 98.28% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::48-63 404 0.40% 98.68% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::64-79 303 0.30% 98.98% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::80-95 157 0.16% 99.14% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::96-111 153 0.15% 99.29% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::112-127 320 0.32% 99.61% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::128-143 134 0.13% 99.74% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::144-159 20 0.02% 99.76% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::160-175 11 0.01% 99.77% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-191 66 0.07% 99.84% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::192-207 35 0.03% 99.87% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::208-223 14 0.01% 99.89% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::224-239 5 0.00% 99.89% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::256-271 7 0.01% 99.90% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::272-287 6 0.01% 99.91% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::288-303 7 0.01% 99.91% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::320-335 8 0.01% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::336-351 12 0.01% 99.94% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::352-367 21 0.02% 99.96% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::368-383 5 0.00% 99.97% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::384-399 5 0.00% 99.97% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::496-511 2 0.00% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::512-527 5 0.00% 99.99% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::528-543 5 0.00% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::544-559 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::total 100720 # Writes before turning the bus around for reads 275system.physmem.totQLat 16983547454 # Total ticks spent queuing 276system.physmem.totMemAccLat 40010947454 # Total ticks spent from burst creation until serviced by the DRAM 277system.physmem.totBusLat 6140640000 # Total ticks spent in databus transfers 278system.physmem.avgQLat 13828.81 # Average queueing delay per DRAM burst 279system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 280system.physmem.avgMemAccLat 32578.81 # Average memory access latency per DRAM burst 281system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s 282system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s 283system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s 284system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s 285system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 286system.physmem.busUtil 0.03 # Data bus utilization in percentage 287system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 288system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 289system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 290system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing 291system.physmem.readRowHits 948457 # Number of row buffer hits during reads 292system.physmem.writeRowHits 1638549 # Number of row buffer hits during writes 293system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads 294system.physmem.writeRowHitRate 78.30 # Row buffer hit rate for writes 295system.physmem.avgGap 15306733.63 # Average gap between requests 296system.physmem.pageHitRate 77.90 # Row buffer hit rate, read and write combined 297system.physmem_0.actEnergy 2845387440 # Energy for activate commands per rank (pJ) 298system.physmem_0.preEnergy 1552542750 # Energy for precharge commands per rank (pJ) 299system.physmem_0.readEnergy 4674001800 # Energy for read commands per rank (pJ) 300system.physmem_0.writeEnergy 6867115200 # Energy for write commands per rank (pJ) 301system.physmem_0.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ) 302system.physmem_0.actBackEnergy 1311782988195 # Energy for active background per rank (pJ) 303system.physmem_0.preBackEnergy 29815330787250 # Energy for precharge background per rank (pJ) 304system.physmem_0.totalEnergy 34513969041435 # Total energy per rank (pJ) 305system.physmem_0.averagePower 668.745387 # Core power per rank (mW) 306system.physmem_0.memoryStateTime::IDLE 49599639397461 # Time in different power states 307system.physmem_0.memoryStateTime::REF 1723372300000 # Time in different power states 308system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 309system.physmem_0.memoryStateTime::ACT 287019858539 # Time in different power states 310system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.physmem_1.actEnergy 2701755000 # Energy for activate commands per rank (pJ) 312system.physmem_1.preEnergy 1474171875 # Energy for precharge commands per rank (pJ) 313system.physmem_1.readEnergy 4905342000 # Energy for read commands per rank (pJ) 314system.physmem_1.writeEnergy 6693120720 # Energy for write commands per rank (pJ) 315system.physmem_1.refreshEnergy 3370916218800 # Energy for refresh commands per rank (pJ) 316system.physmem_1.actBackEnergy 1303897064130 # Energy for active background per rank (pJ) 317system.physmem_1.preBackEnergy 29822248264500 # Energy for precharge background per rank (pJ) 318system.physmem_1.totalEnergy 34512835937025 # Total energy per rank (pJ) 319system.physmem_1.averagePower 668.723432 # Core power per rank (mW) 320system.physmem_1.memoryStateTime::IDLE 49611170347429 # Time in different power states 321system.physmem_1.memoryStateTime::REF 1723372300000 # Time in different power states 322system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 323system.physmem_1.memoryStateTime::ACT 275493728071 # Time in different power states 324system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 325system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 333system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 340system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 341system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 342system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 343system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 344system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 345system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 346system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 347system.cpu.branchPred.lookups 260902420 # Number of BP lookups 348system.cpu.branchPred.condPredicted 182959992 # Number of conditional branches predicted 349system.cpu.branchPred.condIncorrect 12222887 # Number of conditional branches incorrect 350system.cpu.branchPred.BTBLookups 194114900 # Number of BTB lookups 351system.cpu.branchPred.BTBHits 136429435 # Number of BTB hits 352system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 353system.cpu.branchPred.BTBHitPct 70.282825 # BTB Hit Percentage 354system.cpu.branchPred.usedRAS 31730781 # Number of times the RAS was used to get a target. 355system.cpu.branchPred.RASInCorrect 2172348 # Number of incorrect RAS predictions. 356system.cpu_clk_domain.clock 500 # Clock period in ticks 357system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 366system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 367system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 368system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 369system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 370system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 371system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 372system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 373system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 374system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 375system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 376system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 377system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 378system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 386system.cpu.dtb.walker.walks 588227 # Table walker walks requested 387system.cpu.dtb.walker.walksLong 588227 # Table walker walks initiated with long descriptors 388system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22315 # Level at which table walker walks with long descriptors terminate 389system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191623 # Level at which table walker walks with long descriptors terminate 390system.cpu.dtb.walker.walkWaitTime::samples 588227 # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::0 588227 100.00% 100.00% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::total 588227 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkCompletionTime::samples 213938 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::mean 24858.035959 # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::gmean 21008.300307 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::stdev 15796.225820 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::0-65535 211313 98.77% 98.77% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::65536-131071 2233 1.04% 99.82% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::131072-196607 146 0.07% 99.89% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::196608-262143 117 0.05% 99.94% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::262144-327679 91 0.04% 99.98% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::total 213938 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution 408system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution 409system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution 410system.cpu.dtb.walker.walkPageSizes::4K 191624 89.57% 89.57% # Table walker page sizes translated 411system.cpu.dtb.walker.walkPageSizes::2M 22315 10.43% 100.00% # Table walker page sizes translated 412system.cpu.dtb.walker.walkPageSizes::total 213939 # Table walker page sizes translated 413system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 588227 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Requested::total 588227 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213939 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213939 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin::total 802166 # Table walker requests started/completed, data/inst 420system.cpu.dtb.inst_hits 0 # ITB inst hits 421system.cpu.dtb.inst_misses 0 # ITB inst misses 422system.cpu.dtb.read_hits 183548892 # DTB read hits 423system.cpu.dtb.read_misses 485969 # DTB read misses 424system.cpu.dtb.write_hits 162881584 # DTB write hits 425system.cpu.dtb.write_misses 102258 # DTB write misses 426system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 427system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu.dtb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID 429system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 430system.cpu.dtb.flush_entries 79791 # Number of entries that have been flushed from TLB 431system.cpu.dtb.align_faults 811 # Number of TLB faults due to alignment restrictions 432system.cpu.dtb.prefetch_faults 15585 # Number of TLB faults due to prefetch 433system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu.dtb.perms_faults 23526 # Number of TLB faults due to permissions restrictions 435system.cpu.dtb.read_accesses 184034861 # DTB read accesses 436system.cpu.dtb.write_accesses 162983842 # DTB write accesses 437system.cpu.dtb.inst_accesses 0 # ITB inst accesses 438system.cpu.dtb.hits 346430476 # DTB hits 439system.cpu.dtb.misses 588227 # DTB misses 440system.cpu.dtb.accesses 347018703 # DTB accesses 441system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 450system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 451system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 452system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 453system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 454system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 456system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 459system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 460system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 461system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 462system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 464system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 470system.cpu.itb.walker.walks 136538 # Table walker walks requested 471system.cpu.itb.walker.walksLong 136538 # Table walker walks initiated with long descriptors 472system.cpu.itb.walker.walksLongTerminationLevel::Level2 1085 # Level at which table walker walks with long descriptors terminate 473system.cpu.itb.walker.walksLongTerminationLevel::Level3 118818 # Level at which table walker walks with long descriptors terminate 474system.cpu.itb.walker.walkWaitTime::samples 136538 # Table walker wait (enqueue to first request) latency 475system.cpu.itb.walker.walkWaitTime::0 136538 100.00% 100.00% # Table walker wait (enqueue to first request) latency 476system.cpu.itb.walker.walkWaitTime::total 136538 # Table walker wait (enqueue to first request) latency 477system.cpu.itb.walker.walkCompletionTime::samples 119903 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::mean 27208.529278 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::gmean 23313.702861 # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::stdev 17744.151968 # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::0-65535 116996 97.58% 97.58% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::65536-131071 2625 2.19% 99.76% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::131072-196607 168 0.14% 99.90% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::196608-262143 53 0.04% 99.95% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::262144-327679 37 0.03% 99.98% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::total 119903 # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution 493system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution 494system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution 495system.cpu.itb.walker.walkPageSizes::4K 118818 99.10% 99.10% # Table walker page sizes translated 496system.cpu.itb.walker.walkPageSizes::2M 1085 0.90% 100.00% # Table walker page sizes translated 497system.cpu.itb.walker.walkPageSizes::total 119903 # Table walker page sizes translated 498system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136538 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Requested::total 136538 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119903 # Table walker requests started/completed, data/inst 503system.cpu.itb.walker.walkRequestOrigin_Completed::total 119903 # Table walker requests started/completed, data/inst 504system.cpu.itb.walker.walkRequestOrigin::total 256441 # Table walker requests started/completed, data/inst 505system.cpu.itb.inst_hits 454119408 # ITB inst hits 506system.cpu.itb.inst_misses 136538 # ITB inst misses 507system.cpu.itb.read_hits 0 # DTB read hits 508system.cpu.itb.read_misses 0 # DTB read misses 509system.cpu.itb.write_hits 0 # DTB write hits 510system.cpu.itb.write_misses 0 # DTB write misses 511system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 512system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 513system.cpu.itb.flush_tlb_mva_asid 47246 # Number of times TLB was flushed by MVA & ASID 514system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 515system.cpu.itb.flush_entries 57195 # Number of entries that have been flushed from TLB 516system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 517system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 518system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 519system.cpu.itb.perms_faults 369083 # Number of TLB faults due to permissions restrictions 520system.cpu.itb.read_accesses 0 # DTB read accesses 521system.cpu.itb.write_accesses 0 # DTB write accesses 522system.cpu.itb.inst_accesses 454255946 # ITB inst accesses 523system.cpu.itb.hits 454119408 # DTB hits 524system.cpu.itb.misses 136538 # DTB misses 525system.cpu.itb.accesses 454255946 # DTB accesses 526system.cpu.numCycles 2495798541 # number of cpu cycles simulated 527system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 528system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529system.cpu.committedInsts 950561948 # Number of instructions committed 530system.cpu.committedOps 1116924449 # Number of ops (including micro ops) committed 531system.cpu.discardedOps 97483728 # Number of ops (including micro ops) which were discarded before commit 532system.cpu.numFetchSuspends 7747 # Number of times Execute suspended instruction fetching 533system.cpu.quiesceCycles 100725440428 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 534system.cpu.cpi 2.625603 # CPI: cycles per instruction 535system.cpu.ipc 0.380865 # IPC: instructions per cycle 536system.cpu.kern.inst.arm 0 # number of arm instructions executed 537system.cpu.kern.inst.quiesce 16607 # number of quiesce instructions executed 538system.cpu.tickCycles 1794634441 # Number of cycles that the object actually ticked 539system.cpu.idleCycles 701164100 # Total number of cycles that the object has spent stopped 540system.cpu.dcache.tags.replacements 11128908 # number of replacements 541system.cpu.dcache.tags.tagsinuse 511.957332 # Cycle average of tags in use 542system.cpu.dcache.tags.total_refs 330012577 # Total number of references to valid blocks. 543system.cpu.dcache.tags.sampled_refs 11129420 # Sample count of references to valid blocks. 544system.cpu.dcache.tags.avg_refs 29.652271 # Average number of references to valid blocks. 545system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. 546system.cpu.dcache.tags.occ_blocks::cpu.data 511.957332 # Average occupied blocks per requestor 547system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy 548system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy 549system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 550system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 551system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id 552system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 553system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 554system.cpu.dcache.tags.tag_accesses 1386837426 # Number of tag accesses 555system.cpu.dcache.tags.data_accesses 1386837426 # Number of data accesses 556system.cpu.dcache.ReadReq_hits::cpu.data 168701491 # number of ReadReq hits 557system.cpu.dcache.ReadReq_hits::total 168701491 # number of ReadReq hits 558system.cpu.dcache.WriteReq_hits::cpu.data 152033429 # number of WriteReq hits 559system.cpu.dcache.WriteReq_hits::total 152033429 # number of WriteReq hits 560system.cpu.dcache.SoftPFReq_hits::cpu.data 523995 # number of SoftPFReq hits 561system.cpu.dcache.SoftPFReq_hits::total 523995 # number of SoftPFReq hits 562system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits 563system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits 564system.cpu.dcache.LoadLockedReq_hits::cpu.data 4025252 # number of LoadLockedReq hits 565system.cpu.dcache.LoadLockedReq_hits::total 4025252 # number of LoadLockedReq hits 566system.cpu.dcache.StoreCondReq_hits::cpu.data 4342024 # number of StoreCondReq hits 567system.cpu.dcache.StoreCondReq_hits::total 4342024 # number of StoreCondReq hits 568system.cpu.dcache.demand_hits::cpu.data 320734920 # number of demand (read+write) hits 569system.cpu.dcache.demand_hits::total 320734920 # number of demand (read+write) hits 570system.cpu.dcache.overall_hits::cpu.data 321258915 # number of overall hits 571system.cpu.dcache.overall_hits::total 321258915 # number of overall hits 572system.cpu.dcache.ReadReq_misses::cpu.data 6599201 # number of ReadReq misses 573system.cpu.dcache.ReadReq_misses::total 6599201 # number of ReadReq misses 574system.cpu.dcache.WriteReq_misses::cpu.data 4320372 # number of WriteReq misses 575system.cpu.dcache.WriteReq_misses::total 4320372 # number of WriteReq misses 576system.cpu.dcache.SoftPFReq_misses::cpu.data 1481368 # number of SoftPFReq misses 577system.cpu.dcache.SoftPFReq_misses::total 1481368 # number of SoftPFReq misses 578system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244671 # number of WriteInvalidateReq misses 579system.cpu.dcache.WriteInvalidateReq_misses::total 1244671 # number of WriteInvalidateReq misses 580system.cpu.dcache.LoadLockedReq_misses::cpu.data 318506 # number of LoadLockedReq misses 581system.cpu.dcache.LoadLockedReq_misses::total 318506 # number of LoadLockedReq misses 582system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 583system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 584system.cpu.dcache.demand_misses::cpu.data 10919573 # number of demand (read+write) misses 585system.cpu.dcache.demand_misses::total 10919573 # number of demand (read+write) misses 586system.cpu.dcache.overall_misses::cpu.data 12400941 # number of overall misses 587system.cpu.dcache.overall_misses::total 12400941 # number of overall misses 588system.cpu.dcache.ReadReq_miss_latency::cpu.data 107641538217 # number of ReadReq miss cycles 589system.cpu.dcache.ReadReq_miss_latency::total 107641538217 # number of ReadReq miss cycles 590system.cpu.dcache.WriteReq_miss_latency::cpu.data 155110738831 # number of WriteReq miss cycles 591system.cpu.dcache.WriteReq_miss_latency::total 155110738831 # number of WriteReq miss cycles 592system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35571203201 # number of WriteInvalidateReq miss cycles 593system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35571203201 # number of WriteInvalidateReq miss cycles 594system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4850646421 # number of LoadLockedReq miss cycles 595system.cpu.dcache.LoadLockedReq_miss_latency::total 4850646421 # number of LoadLockedReq miss cycles 596system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 597system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles 598system.cpu.dcache.demand_miss_latency::cpu.data 262752277048 # number of demand (read+write) miss cycles 599system.cpu.dcache.demand_miss_latency::total 262752277048 # number of demand (read+write) miss cycles 600system.cpu.dcache.overall_miss_latency::cpu.data 262752277048 # number of overall miss cycles 601system.cpu.dcache.overall_miss_latency::total 262752277048 # number of overall miss cycles 602system.cpu.dcache.ReadReq_accesses::cpu.data 175300692 # number of ReadReq accesses(hits+misses) 603system.cpu.dcache.ReadReq_accesses::total 175300692 # number of ReadReq accesses(hits+misses) 604system.cpu.dcache.WriteReq_accesses::cpu.data 156353801 # number of WriteReq accesses(hits+misses) 605system.cpu.dcache.WriteReq_accesses::total 156353801 # number of WriteReq accesses(hits+misses) 606system.cpu.dcache.SoftPFReq_accesses::cpu.data 2005363 # number of SoftPFReq accesses(hits+misses) 607system.cpu.dcache.SoftPFReq_accesses::total 2005363 # number of SoftPFReq accesses(hits+misses) 608system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581358 # number of WriteInvalidateReq accesses(hits+misses) 609system.cpu.dcache.WriteInvalidateReq_accesses::total 1581358 # number of WriteInvalidateReq accesses(hits+misses) 610system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4343758 # number of LoadLockedReq accesses(hits+misses) 611system.cpu.dcache.LoadLockedReq_accesses::total 4343758 # number of LoadLockedReq accesses(hits+misses) 612system.cpu.dcache.StoreCondReq_accesses::cpu.data 4342025 # number of StoreCondReq accesses(hits+misses) 613system.cpu.dcache.StoreCondReq_accesses::total 4342025 # number of StoreCondReq accesses(hits+misses) 614system.cpu.dcache.demand_accesses::cpu.data 331654493 # number of demand (read+write) accesses 615system.cpu.dcache.demand_accesses::total 331654493 # number of demand (read+write) accesses 616system.cpu.dcache.overall_accesses::cpu.data 333659856 # number of overall (read+write) accesses 617system.cpu.dcache.overall_accesses::total 333659856 # number of overall (read+write) accesses 618system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037645 # miss rate for ReadReq accesses 619system.cpu.dcache.ReadReq_miss_rate::total 0.037645 # miss rate for ReadReq accesses 620system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027632 # miss rate for WriteReq accesses 621system.cpu.dcache.WriteReq_miss_rate::total 0.027632 # miss rate for WriteReq accesses 622system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738703 # miss rate for SoftPFReq accesses 623system.cpu.dcache.SoftPFReq_miss_rate::total 0.738703 # miss rate for SoftPFReq accesses 624system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787090 # miss rate for WriteInvalidateReq accesses 625system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787090 # miss rate for WriteInvalidateReq accesses 626system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073325 # miss rate for LoadLockedReq accesses 627system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073325 # miss rate for LoadLockedReq accesses 628system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 629system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 630system.cpu.dcache.demand_miss_rate::cpu.data 0.032925 # miss rate for demand accesses 631system.cpu.dcache.demand_miss_rate::total 0.032925 # miss rate for demand accesses 632system.cpu.dcache.overall_miss_rate::cpu.data 0.037166 # miss rate for overall accesses 633system.cpu.dcache.overall_miss_rate::total 0.037166 # miss rate for overall accesses 634system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16311.298628 # average ReadReq miss latency 635system.cpu.dcache.ReadReq_avg_miss_latency::total 16311.298628 # average ReadReq miss latency 636system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35902.172042 # average WriteReq miss latency 637system.cpu.dcache.WriteReq_avg_miss_latency::total 35902.172042 # average WriteReq miss latency 638system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28578.799700 # average WriteInvalidateReq miss latency 639system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28578.799700 # average WriteInvalidateReq miss latency 640system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15229.372197 # average LoadLockedReq miss latency 641system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15229.372197 # average LoadLockedReq miss latency 642system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 643system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 644system.cpu.dcache.demand_avg_miss_latency::cpu.data 24062.504738 # average overall miss latency 645system.cpu.dcache.demand_avg_miss_latency::total 24062.504738 # average overall miss latency 646system.cpu.dcache.overall_avg_miss_latency::cpu.data 21188.091859 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::total 21188.091859 # average overall miss latency 648system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked 649system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 654system.cpu.dcache.fast_writes 0 # number of fast writes performed 655system.cpu.dcache.cache_copies 0 # number of cache copies performed 656system.cpu.dcache.writebacks::writebacks 8539693 # number of writebacks 657system.cpu.dcache.writebacks::total 8539693 # number of writebacks 658system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803144 # number of ReadReq MSHR hits 659system.cpu.dcache.ReadReq_mshr_hits::total 803144 # number of ReadReq MSHR hits 660system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904565 # number of WriteReq MSHR hits 661system.cpu.dcache.WriteReq_mshr_hits::total 1904565 # number of WriteReq MSHR hits 662system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 147 # number of WriteInvalidateReq MSHR hits 663system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 147 # number of WriteInvalidateReq MSHR hits 664system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69655 # number of LoadLockedReq MSHR hits 665system.cpu.dcache.LoadLockedReq_mshr_hits::total 69655 # number of LoadLockedReq MSHR hits 666system.cpu.dcache.demand_mshr_hits::cpu.data 2707709 # number of demand (read+write) MSHR hits 667system.cpu.dcache.demand_mshr_hits::total 2707709 # number of demand (read+write) MSHR hits 668system.cpu.dcache.overall_mshr_hits::cpu.data 2707709 # number of overall MSHR hits 669system.cpu.dcache.overall_mshr_hits::total 2707709 # number of overall MSHR hits 670system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5796057 # number of ReadReq MSHR misses 671system.cpu.dcache.ReadReq_mshr_misses::total 5796057 # number of ReadReq MSHR misses 672system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2415807 # number of WriteReq MSHR misses 673system.cpu.dcache.WriteReq_mshr_misses::total 2415807 # number of WriteReq MSHR misses 674system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473891 # number of SoftPFReq MSHR misses 675system.cpu.dcache.SoftPFReq_mshr_misses::total 1473891 # number of SoftPFReq MSHR misses 676system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244524 # number of WriteInvalidateReq MSHR misses 677system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244524 # number of WriteInvalidateReq MSHR misses 678system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 248851 # number of LoadLockedReq MSHR misses 679system.cpu.dcache.LoadLockedReq_mshr_misses::total 248851 # number of LoadLockedReq MSHR misses 680system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 681system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 682system.cpu.dcache.demand_mshr_misses::cpu.data 8211864 # number of demand (read+write) MSHR misses 683system.cpu.dcache.demand_mshr_misses::total 8211864 # number of demand (read+write) MSHR misses 684system.cpu.dcache.overall_mshr_misses::cpu.data 9685755 # number of overall MSHR misses 685system.cpu.dcache.overall_mshr_misses::total 9685755 # number of overall MSHR misses 686system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 687system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable 688system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable 689system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable 690system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses 691system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85294782786 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 85294782786 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79878018296 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 79878018296 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23078167080 # number of SoftPFReq MSHR miss cycles 697system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23078167080 # number of SoftPFReq MSHR miss cycles 698system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33700697799 # number of WriteInvalidateReq MSHR miss cycles 699system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33700697799 # number of WriteInvalidateReq MSHR miss cycles 700system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3279664007 # number of LoadLockedReq MSHR miss cycles 701system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3279664007 # number of LoadLockedReq MSHR miss cycles 702system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles 703system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles 704system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165172801082 # number of demand (read+write) MSHR miss cycles 705system.cpu.dcache.demand_mshr_miss_latency::total 165172801082 # number of demand (read+write) MSHR miss cycles 706system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188250968162 # number of overall MSHR miss cycles 707system.cpu.dcache.overall_mshr_miss_latency::total 188250968162 # number of overall MSHR miss cycles 708system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5750649000 # number of ReadReq MSHR uncacheable cycles 709system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5750649000 # number of ReadReq MSHR uncacheable cycles 710system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5615353750 # number of WriteReq MSHR uncacheable cycles 711system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5615353750 # number of WriteReq MSHR uncacheable cycles 712system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11366002750 # number of overall MSHR uncacheable cycles 713system.cpu.dcache.overall_mshr_uncacheable_latency::total 11366002750 # number of overall MSHR uncacheable cycles 714system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033064 # mshr miss rate for ReadReq accesses 715system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033064 # mshr miss rate for ReadReq accesses 716system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015451 # mshr miss rate for WriteReq accesses 717system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015451 # mshr miss rate for WriteReq accesses 718system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.734975 # mshr miss rate for SoftPFReq accesses 719system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.734975 # mshr miss rate for SoftPFReq accesses 720system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786997 # mshr miss rate for WriteInvalidateReq accesses 721system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786997 # mshr miss rate for WriteInvalidateReq accesses 722system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057289 # mshr miss rate for LoadLockedReq accesses 723system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057289 # mshr miss rate for LoadLockedReq accesses 724system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 725system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 726system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024760 # mshr miss rate for demand accesses 727system.cpu.dcache.demand_mshr_miss_rate::total 0.024760 # mshr miss rate for demand accesses 728system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029029 # mshr miss rate for overall accesses 729system.cpu.dcache.overall_mshr_miss_rate::total 0.029029 # mshr miss rate for overall accesses 730system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14716.001376 # average ReadReq mshr miss latency 731system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14716.001376 # average ReadReq mshr miss latency 732system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33064.735012 # average WriteReq mshr miss latency 733system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33064.735012 # average WriteReq mshr miss latency 734system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15657.987653 # average SoftPFReq mshr miss latency 735system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15657.987653 # average SoftPFReq mshr miss latency 736system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27079.186740 # average WriteInvalidateReq mshr miss latency 737system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.186740 # average WriteInvalidateReq mshr miss latency 738system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13179.227759 # average LoadLockedReq mshr miss latency 739system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13179.227759 # average LoadLockedReq mshr miss latency 740system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 741system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 742system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20113.923110 # average overall mshr miss latency 743system.cpu.dcache.demand_avg_mshr_miss_latency::total 20113.923110 # average overall mshr miss latency 744system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19435.858966 # average overall mshr miss latency 745system.cpu.dcache.overall_avg_mshr_miss_latency::total 19435.858966 # average overall mshr miss latency 746system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170662.660256 # average ReadReq mshr uncacheable latency 747system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170662.660256 # average ReadReq mshr uncacheable latency 748system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166602.989171 # average WriteReq mshr uncacheable latency 749system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166602.989171 # average WriteReq mshr uncacheable latency 750system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168632.553671 # average overall mshr uncacheable latency 751system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168632.553671 # average overall mshr uncacheable latency 752system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.cpu.icache.tags.replacements 24596775 # number of replacements 754system.cpu.icache.tags.tagsinuse 511.926998 # Cycle average of tags in use 755system.cpu.icache.tags.total_refs 429140951 # Total number of references to valid blocks. 756system.cpu.icache.tags.sampled_refs 24597287 # Sample count of references to valid blocks. 757system.cpu.icache.tags.avg_refs 17.446678 # Average number of references to valid blocks. 758system.cpu.icache.tags.warmup_cycle 22329177250 # Cycle when the warmup percentage was hit. 759system.cpu.icache.tags.occ_blocks::cpu.inst 511.926998 # Average occupied blocks per requestor 760system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy 761system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy 762system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 763system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 764system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 765system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id 766system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 767system.cpu.icache.tags.tag_accesses 478335544 # Number of tag accesses 768system.cpu.icache.tags.data_accesses 478335544 # Number of data accesses 769system.cpu.icache.ReadReq_hits::cpu.inst 429140951 # number of ReadReq hits 770system.cpu.icache.ReadReq_hits::total 429140951 # number of ReadReq hits 771system.cpu.icache.demand_hits::cpu.inst 429140951 # number of demand (read+write) hits 772system.cpu.icache.demand_hits::total 429140951 # number of demand (read+write) hits 773system.cpu.icache.overall_hits::cpu.inst 429140951 # number of overall hits 774system.cpu.icache.overall_hits::total 429140951 # number of overall hits 775system.cpu.icache.ReadReq_misses::cpu.inst 24597297 # number of ReadReq misses 776system.cpu.icache.ReadReq_misses::total 24597297 # number of ReadReq misses 777system.cpu.icache.demand_misses::cpu.inst 24597297 # number of demand (read+write) misses 778system.cpu.icache.demand_misses::total 24597297 # number of demand (read+write) misses 779system.cpu.icache.overall_misses::cpu.inst 24597297 # number of overall misses 780system.cpu.icache.overall_misses::total 24597297 # number of overall misses 781system.cpu.icache.ReadReq_miss_latency::cpu.inst 327843901768 # number of ReadReq miss cycles 782system.cpu.icache.ReadReq_miss_latency::total 327843901768 # number of ReadReq miss cycles 783system.cpu.icache.demand_miss_latency::cpu.inst 327843901768 # number of demand (read+write) miss cycles 784system.cpu.icache.demand_miss_latency::total 327843901768 # number of demand (read+write) miss cycles 785system.cpu.icache.overall_miss_latency::cpu.inst 327843901768 # number of overall miss cycles 786system.cpu.icache.overall_miss_latency::total 327843901768 # number of overall miss cycles 787system.cpu.icache.ReadReq_accesses::cpu.inst 453738248 # number of ReadReq accesses(hits+misses) 788system.cpu.icache.ReadReq_accesses::total 453738248 # number of ReadReq accesses(hits+misses) 789system.cpu.icache.demand_accesses::cpu.inst 453738248 # number of demand (read+write) accesses 790system.cpu.icache.demand_accesses::total 453738248 # number of demand (read+write) accesses 791system.cpu.icache.overall_accesses::cpu.inst 453738248 # number of overall (read+write) accesses 792system.cpu.icache.overall_accesses::total 453738248 # number of overall (read+write) accesses 793system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054210 # miss rate for ReadReq accesses 794system.cpu.icache.ReadReq_miss_rate::total 0.054210 # miss rate for ReadReq accesses 795system.cpu.icache.demand_miss_rate::cpu.inst 0.054210 # miss rate for demand accesses 796system.cpu.icache.demand_miss_rate::total 0.054210 # miss rate for demand accesses 797system.cpu.icache.overall_miss_rate::cpu.inst 0.054210 # miss rate for overall accesses 798system.cpu.icache.overall_miss_rate::total 0.054210 # miss rate for overall accesses 799system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13328.452381 # average ReadReq miss latency 800system.cpu.icache.ReadReq_avg_miss_latency::total 13328.452381 # average ReadReq miss latency 801system.cpu.icache.demand_avg_miss_latency::cpu.inst 13328.452381 # average overall miss latency 802system.cpu.icache.demand_avg_miss_latency::total 13328.452381 # average overall miss latency 803system.cpu.icache.overall_avg_miss_latency::cpu.inst 13328.452381 # average overall miss latency 804system.cpu.icache.overall_avg_miss_latency::total 13328.452381 # average overall miss latency 805system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 806system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 807system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 808system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 809system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 810system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 811system.cpu.icache.fast_writes 0 # number of fast writes performed 812system.cpu.icache.cache_copies 0 # number of cache copies performed 813system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24597297 # number of ReadReq MSHR misses 814system.cpu.icache.ReadReq_mshr_misses::total 24597297 # number of ReadReq MSHR misses 815system.cpu.icache.demand_mshr_misses::cpu.inst 24597297 # number of demand (read+write) MSHR misses 816system.cpu.icache.demand_mshr_misses::total 24597297 # number of demand (read+write) MSHR misses 817system.cpu.icache.overall_mshr_misses::cpu.inst 24597297 # number of overall MSHR misses 818system.cpu.icache.overall_mshr_misses::total 24597297 # number of overall MSHR misses 819system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable 820system.cpu.icache.ReadReq_mshr_uncacheable::total 52294 # number of ReadReq MSHR uncacheable 821system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses 822system.cpu.icache.overall_mshr_uncacheable_misses::total 52294 # number of overall MSHR uncacheable misses 823system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290898201664 # number of ReadReq MSHR miss cycles 824system.cpu.icache.ReadReq_mshr_miss_latency::total 290898201664 # number of ReadReq MSHR miss cycles 825system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290898201664 # number of demand (read+write) MSHR miss cycles 826system.cpu.icache.demand_mshr_miss_latency::total 290898201664 # number of demand (read+write) MSHR miss cycles 827system.cpu.icache.overall_mshr_miss_latency::cpu.inst 290898201664 # number of overall MSHR miss cycles 828system.cpu.icache.overall_mshr_miss_latency::total 290898201664 # number of overall MSHR miss cycles 829system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles 830system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles 831system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4024065500 # number of overall MSHR uncacheable cycles 832system.cpu.icache.overall_mshr_uncacheable_latency::total 4024065500 # number of overall MSHR uncacheable cycles 833system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for ReadReq accesses 834system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054210 # mshr miss rate for ReadReq accesses 835system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for demand accesses 836system.cpu.icache.demand_mshr_miss_rate::total 0.054210 # mshr miss rate for demand accesses 837system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054210 # mshr miss rate for overall accesses 838system.cpu.icache.overall_mshr_miss_rate::total 0.054210 # mshr miss rate for overall accesses 839system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11826.429614 # average ReadReq mshr miss latency 840system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11826.429614 # average ReadReq mshr miss latency 841system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11826.429614 # average overall mshr miss latency 842system.cpu.icache.demand_avg_mshr_miss_latency::total 11826.429614 # average overall mshr miss latency 843system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11826.429614 # average overall mshr miss latency 844system.cpu.icache.overall_avg_mshr_miss_latency::total 11826.429614 # average overall mshr miss latency 845system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average ReadReq mshr uncacheable latency 846system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976 # average ReadReq mshr uncacheable latency 847system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average overall mshr uncacheable latency 848system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976 # average overall mshr uncacheable latency 849system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 850system.cpu.l2cache.tags.replacements 1624472 # number of replacements 851system.cpu.l2cache.tags.tagsinuse 65307.335302 # Cycle average of tags in use 852system.cpu.l2cache.tags.total_refs 40176051 # Total number of references to valid blocks. 853system.cpu.l2cache.tags.sampled_refs 1687699 # Sample count of references to valid blocks. 854system.cpu.l2cache.tags.avg_refs 23.805223 # Average number of references to valid blocks. 855system.cpu.l2cache.tags.warmup_cycle 6393601000 # Cycle when the warmup percentage was hit. 856system.cpu.l2cache.tags.occ_blocks::writebacks 36145.263997 # Average occupied blocks per requestor 857system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 333.648075 # Average occupied blocks per requestor 858system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 422.733439 # Average occupied blocks per requestor 859system.cpu.l2cache.tags.occ_blocks::cpu.inst 8142.717924 # Average occupied blocks per requestor 860system.cpu.l2cache.tags.occ_blocks::cpu.data 20262.971868 # Average occupied blocks per requestor 861system.cpu.l2cache.tags.occ_percent::writebacks 0.551533 # Average percentage of cache occupancy 862system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005091 # Average percentage of cache occupancy 863system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006450 # Average percentage of cache occupancy 864system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124248 # Average percentage of cache occupancy 865system.cpu.l2cache.tags.occ_percent::cpu.data 0.309188 # Average percentage of cache occupancy 866system.cpu.l2cache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy 867system.cpu.l2cache.tags.occ_task_id_blocks::1023 253 # Occupied blocks per task id 868system.cpu.l2cache.tags.occ_task_id_blocks::1024 62974 # Occupied blocks per task id 869system.cpu.l2cache.tags.age_task_id_blocks_1023::4 253 # Occupied blocks per task id 870system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 871system.cpu.l2cache.tags.age_task_id_blocks_1024::1 498 # Occupied blocks per task id 872system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id 873system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5584 # Occupied blocks per task id 874system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54389 # Occupied blocks per task id 875system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003860 # Percentage of cache occupancy per task id 876system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960907 # Percentage of cache occupancy per task id 877system.cpu.l2cache.tags.tag_accesses 369553553 # Number of tag accesses 878system.cpu.l2cache.tags.data_accesses 369553553 # Number of data accesses 879system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 980236 # number of ReadReq hits 880system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 284775 # number of ReadReq hits 881system.cpu.l2cache.ReadReq_hits::cpu.inst 24487803 # number of ReadReq hits 882system.cpu.l2cache.ReadReq_hits::cpu.data 7183333 # number of ReadReq hits 883system.cpu.l2cache.ReadReq_hits::total 32936147 # number of ReadReq hits 884system.cpu.l2cache.Writeback_hits::writebacks 8539693 # number of Writeback hits 885system.cpu.l2cache.Writeback_hits::total 8539693 # number of Writeback hits 886system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 698094 # number of WriteInvalidateReq hits 887system.cpu.l2cache.WriteInvalidateReq_hits::total 698094 # number of WriteInvalidateReq hits 888system.cpu.l2cache.UpgradeReq_hits::cpu.data 10791 # number of UpgradeReq hits 889system.cpu.l2cache.UpgradeReq_hits::total 10791 # number of UpgradeReq hits 890system.cpu.l2cache.ReadExReq_hits::cpu.data 1651497 # number of ReadExReq hits 891system.cpu.l2cache.ReadExReq_hits::total 1651497 # number of ReadExReq hits 892system.cpu.l2cache.demand_hits::cpu.dtb.walker 980236 # number of demand (read+write) hits 893system.cpu.l2cache.demand_hits::cpu.itb.walker 284775 # number of demand (read+write) hits 894system.cpu.l2cache.demand_hits::cpu.inst 24487803 # number of demand (read+write) hits 895system.cpu.l2cache.demand_hits::cpu.data 8834830 # number of demand (read+write) hits 896system.cpu.l2cache.demand_hits::total 34587644 # number of demand (read+write) hits 897system.cpu.l2cache.overall_hits::cpu.dtb.walker 980236 # number of overall hits 898system.cpu.l2cache.overall_hits::cpu.itb.walker 284775 # number of overall hits 899system.cpu.l2cache.overall_hits::cpu.inst 24487803 # number of overall hits 900system.cpu.l2cache.overall_hits::cpu.data 8834830 # number of overall hits 901system.cpu.l2cache.overall_hits::total 34587644 # number of overall hits 902system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6407 # number of ReadReq misses 903system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5317 # number of ReadReq misses 904system.cpu.l2cache.ReadReq_misses::cpu.inst 109491 # number of ReadReq misses 905system.cpu.l2cache.ReadReq_misses::cpu.data 335212 # number of ReadReq misses 906system.cpu.l2cache.ReadReq_misses::total 456427 # number of ReadReq misses 907system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 546430 # number of WriteInvalidateReq misses 908system.cpu.l2cache.WriteInvalidateReq_misses::total 546430 # number of WriteInvalidateReq misses 909system.cpu.l2cache.UpgradeReq_misses::cpu.data 38901 # number of UpgradeReq misses 910system.cpu.l2cache.UpgradeReq_misses::total 38901 # number of UpgradeReq misses 911system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 912system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 913system.cpu.l2cache.ReadExReq_misses::cpu.data 714872 # number of ReadExReq misses 914system.cpu.l2cache.ReadExReq_misses::total 714872 # number of ReadExReq misses 915system.cpu.l2cache.demand_misses::cpu.dtb.walker 6407 # number of demand (read+write) misses 916system.cpu.l2cache.demand_misses::cpu.itb.walker 5317 # number of demand (read+write) misses 917system.cpu.l2cache.demand_misses::cpu.inst 109491 # number of demand (read+write) misses 918system.cpu.l2cache.demand_misses::cpu.data 1050084 # number of demand (read+write) misses 919system.cpu.l2cache.demand_misses::total 1171299 # number of demand (read+write) misses 920system.cpu.l2cache.overall_misses::cpu.dtb.walker 6407 # number of overall misses 921system.cpu.l2cache.overall_misses::cpu.itb.walker 5317 # number of overall misses 922system.cpu.l2cache.overall_misses::cpu.inst 109491 # number of overall misses 923system.cpu.l2cache.overall_misses::cpu.data 1050084 # number of overall misses 924system.cpu.l2cache.overall_misses::total 1171299 # number of overall misses 925system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 560042000 # number of ReadReq miss cycles 926system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 465198251 # number of ReadReq miss cycles 927system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8958985804 # number of ReadReq miss cycles 928system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28447834598 # number of ReadReq miss cycles 929system.cpu.l2cache.ReadReq_miss_latency::total 38432060653 # number of ReadReq miss cycles 930system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 6247800 # number of WriteInvalidateReq miss cycles 931system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 6247800 # number of WriteInvalidateReq miss cycles 932system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 584783300 # number of UpgradeReq miss cycles 933system.cpu.l2cache.UpgradeReq_miss_latency::total 584783300 # number of UpgradeReq miss cycles 934system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 935system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles 936system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58773696620 # number of ReadExReq miss cycles 937system.cpu.l2cache.ReadExReq_miss_latency::total 58773696620 # number of ReadExReq miss cycles 938system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 560042000 # number of demand (read+write) miss cycles 939system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 465198251 # number of demand (read+write) miss cycles 940system.cpu.l2cache.demand_miss_latency::cpu.inst 8958985804 # number of demand (read+write) miss cycles 941system.cpu.l2cache.demand_miss_latency::cpu.data 87221531218 # number of demand (read+write) miss cycles 942system.cpu.l2cache.demand_miss_latency::total 97205757273 # number of demand (read+write) miss cycles 943system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 560042000 # number of overall miss cycles 944system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 465198251 # number of overall miss cycles 945system.cpu.l2cache.overall_miss_latency::cpu.inst 8958985804 # number of overall miss cycles 946system.cpu.l2cache.overall_miss_latency::cpu.data 87221531218 # number of overall miss cycles 947system.cpu.l2cache.overall_miss_latency::total 97205757273 # number of overall miss cycles 948system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 986643 # number of ReadReq accesses(hits+misses) 949system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 290092 # number of ReadReq accesses(hits+misses) 950system.cpu.l2cache.ReadReq_accesses::cpu.inst 24597294 # number of ReadReq accesses(hits+misses) 951system.cpu.l2cache.ReadReq_accesses::cpu.data 7518545 # number of ReadReq accesses(hits+misses) 952system.cpu.l2cache.ReadReq_accesses::total 33392574 # number of ReadReq accesses(hits+misses) 953system.cpu.l2cache.Writeback_accesses::writebacks 8539693 # number of Writeback accesses(hits+misses) 954system.cpu.l2cache.Writeback_accesses::total 8539693 # number of Writeback accesses(hits+misses) 955system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244524 # number of WriteInvalidateReq accesses(hits+misses) 956system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244524 # number of WriteInvalidateReq accesses(hits+misses) 957system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49692 # number of UpgradeReq accesses(hits+misses) 958system.cpu.l2cache.UpgradeReq_accesses::total 49692 # number of UpgradeReq accesses(hits+misses) 959system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 960system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 961system.cpu.l2cache.ReadExReq_accesses::cpu.data 2366369 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadExReq_accesses::total 2366369 # number of ReadExReq accesses(hits+misses) 963system.cpu.l2cache.demand_accesses::cpu.dtb.walker 986643 # number of demand (read+write) accesses 964system.cpu.l2cache.demand_accesses::cpu.itb.walker 290092 # number of demand (read+write) accesses 965system.cpu.l2cache.demand_accesses::cpu.inst 24597294 # number of demand (read+write) accesses 966system.cpu.l2cache.demand_accesses::cpu.data 9884914 # number of demand (read+write) accesses 967system.cpu.l2cache.demand_accesses::total 35758943 # number of demand (read+write) accesses 968system.cpu.l2cache.overall_accesses::cpu.dtb.walker 986643 # number of overall (read+write) accesses 969system.cpu.l2cache.overall_accesses::cpu.itb.walker 290092 # number of overall (read+write) accesses 970system.cpu.l2cache.overall_accesses::cpu.inst 24597294 # number of overall (read+write) accesses 971system.cpu.l2cache.overall_accesses::cpu.data 9884914 # number of overall (read+write) accesses 972system.cpu.l2cache.overall_accesses::total 35758943 # number of overall (read+write) accesses 973system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006494 # miss rate for ReadReq accesses 974system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018329 # miss rate for ReadReq accesses 975system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004451 # miss rate for ReadReq accesses 976system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044585 # miss rate for ReadReq accesses 977system.cpu.l2cache.ReadReq_miss_rate::total 0.013669 # miss rate for ReadReq accesses 978system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.439067 # miss rate for WriteInvalidateReq accesses 979system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.439067 # miss rate for WriteInvalidateReq accesses 980system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782842 # miss rate for UpgradeReq accesses 981system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782842 # miss rate for UpgradeReq accesses 982system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 983system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 984system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.302097 # miss rate for ReadExReq accesses 985system.cpu.l2cache.ReadExReq_miss_rate::total 0.302097 # miss rate for ReadExReq accesses 986system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006494 # miss rate for demand accesses 987system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018329 # miss rate for demand accesses 988system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004451 # miss rate for demand accesses 989system.cpu.l2cache.demand_miss_rate::cpu.data 0.106231 # miss rate for demand accesses 990system.cpu.l2cache.demand_miss_rate::total 0.032755 # miss rate for demand accesses 991system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006494 # miss rate for overall accesses 992system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018329 # miss rate for overall accesses 993system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004451 # miss rate for overall accesses 994system.cpu.l2cache.overall_miss_rate::cpu.data 0.106231 # miss rate for overall accesses 995system.cpu.l2cache.overall_miss_rate::total 0.032755 # miss rate for overall accesses 996system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87410.956766 # average ReadReq miss latency 997system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87492.618206 # average ReadReq miss latency 998system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81823.947210 # average ReadReq miss latency 999system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84865.203507 # average ReadReq miss latency 1000system.cpu.l2cache.ReadReq_avg_miss_latency::total 84201.987729 # average ReadReq miss latency 1001system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 11.433852 # average WriteInvalidateReq miss latency 1002system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 11.433852 # average WriteInvalidateReq miss latency 1003system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15032.603275 # average UpgradeReq miss latency 1004system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15032.603275 # average UpgradeReq miss latency 1005system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1006system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1007system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82215.692627 # average ReadExReq miss latency 1008system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82215.692627 # average ReadExReq miss latency 1009system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87410.956766 # average overall miss latency 1010system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87492.618206 # average overall miss latency 1011system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81823.947210 # average overall miss latency 1012system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83061.480051 # average overall miss latency 1013system.cpu.l2cache.demand_avg_miss_latency::total 82989.703972 # average overall miss latency 1014system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87410.956766 # average overall miss latency 1015system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87492.618206 # average overall miss latency 1016system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81823.947210 # average overall miss latency 1017system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83061.480051 # average overall miss latency 1018system.cpu.l2cache.overall_avg_miss_latency::total 82989.703972 # average overall miss latency 1019system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1020system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1021system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1022system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1023system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1024system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1025system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1026system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1027system.cpu.l2cache.writebacks::writebacks 1380910 # number of writebacks 1028system.cpu.l2cache.writebacks::total 1380910 # number of writebacks 1029system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1030system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 1031system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits 1032system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1033system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1034system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits 1035system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1036system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1037system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits 1038system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6407 # number of ReadReq MSHR misses 1039system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5317 # number of ReadReq MSHR misses 1040system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 109489 # number of ReadReq MSHR misses 1041system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 335191 # number of ReadReq MSHR misses 1042system.cpu.l2cache.ReadReq_mshr_misses::total 456404 # number of ReadReq MSHR misses 1043system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 546430 # number of WriteInvalidateReq MSHR misses 1044system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 546430 # number of WriteInvalidateReq MSHR misses 1045system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38901 # number of UpgradeReq MSHR misses 1046system.cpu.l2cache.UpgradeReq_mshr_misses::total 38901 # number of UpgradeReq MSHR misses 1047system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1048system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1049system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 714872 # number of ReadExReq MSHR misses 1050system.cpu.l2cache.ReadExReq_mshr_misses::total 714872 # number of ReadExReq MSHR misses 1051system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6407 # number of demand (read+write) MSHR misses 1052system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5317 # number of demand (read+write) MSHR misses 1053system.cpu.l2cache.demand_mshr_misses::cpu.inst 109489 # number of demand (read+write) MSHR misses 1054system.cpu.l2cache.demand_mshr_misses::cpu.data 1050063 # number of demand (read+write) MSHR misses 1055system.cpu.l2cache.demand_mshr_misses::total 1171276 # number of demand (read+write) MSHR misses 1056system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6407 # number of overall MSHR misses 1057system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5317 # number of overall MSHR misses 1058system.cpu.l2cache.overall_mshr_misses::cpu.inst 109489 # number of overall MSHR misses 1059system.cpu.l2cache.overall_mshr_misses::cpu.data 1050063 # number of overall MSHR misses 1060system.cpu.l2cache.overall_mshr_misses::total 1171276 # number of overall MSHR misses 1061system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable 1062system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable 1063system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85990 # number of ReadReq MSHR uncacheable 1064system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable 1065system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable 1066system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses 1067system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses 1068system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119695 # number of overall MSHR uncacheable misses 1069system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 479479000 # number of ReadReq MSHR miss cycles 1070system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 398285251 # number of ReadReq MSHR miss cycles 1071system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7586646696 # number of ReadReq MSHR miss cycles 1072system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24249187152 # number of ReadReq MSHR miss cycles 1073system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32713598099 # number of ReadReq MSHR miss cycles 1074system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18411194701 # number of WriteInvalidateReq MSHR miss cycles 1075system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18411194701 # number of WriteInvalidateReq MSHR miss cycles 1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 691147894 # number of UpgradeReq MSHR miss cycles 1077system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 691147894 # number of UpgradeReq MSHR miss cycles 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 67500 # number of SCUpgradeReq MSHR miss cycles 1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 67500 # number of SCUpgradeReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49837354880 # number of ReadExReq MSHR miss cycles 1081system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49837354880 # number of ReadExReq MSHR miss cycles 1082system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 479479000 # number of demand (read+write) MSHR miss cycles 1083system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 398285251 # number of demand (read+write) MSHR miss cycles 1084system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7586646696 # number of demand (read+write) MSHR miss cycles 1085system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 74086542032 # number of demand (read+write) MSHR miss cycles 1086system.cpu.l2cache.demand_mshr_miss_latency::total 82550952979 # number of demand (read+write) MSHR miss cycles 1087system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 479479000 # number of overall MSHR miss cycles 1088system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 398285251 # number of overall MSHR miss cycles 1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7586646696 # number of overall MSHR miss cycles 1090system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 74086542032 # number of overall MSHR miss cycles 1091system.cpu.l2cache.overall_mshr_miss_latency::total 82550952979 # number of overall MSHR miss cycles 1092system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3108920000 # number of ReadReq MSHR uncacheable cycles 1093system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5278320250 # number of ReadReq MSHR uncacheable cycles 1094system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8387240250 # number of ReadReq MSHR uncacheable cycles 1095system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176274500 # number of WriteReq MSHR uncacheable cycles 1096system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176274500 # number of WriteReq MSHR uncacheable cycles 1097system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3108920000 # number of overall MSHR uncacheable cycles 1098system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454594750 # number of overall MSHR uncacheable cycles 1099system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13563514750 # number of overall MSHR uncacheable cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for ReadReq accesses 1101system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for ReadReq accesses 1102system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for ReadReq accesses 1103system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044582 # mshr miss rate for ReadReq accesses 1104system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses 1105system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.439067 # mshr miss rate for WriteInvalidateReq accesses 1106system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.439067 # mshr miss rate for WriteInvalidateReq accesses 1107system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782842 # mshr miss rate for UpgradeReq accesses 1108system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782842 # mshr miss rate for UpgradeReq accesses 1109system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1110system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1111system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.302097 # mshr miss rate for ReadExReq accesses 1112system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.302097 # mshr miss rate for ReadExReq accesses 1113system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for demand accesses 1114system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for demand accesses 1115system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for demand accesses 1116system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.106229 # mshr miss rate for demand accesses 1117system.cpu.l2cache.demand_mshr_miss_rate::total 0.032755 # mshr miss rate for demand accesses 1118system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006494 # mshr miss rate for overall accesses 1119system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018329 # mshr miss rate for overall accesses 1120system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004451 # mshr miss rate for overall accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.106229 # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::total 0.032755 # mshr miss rate for overall accesses 1123system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average ReadReq mshr miss latency 1124system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average ReadReq mshr miss latency 1125system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69291.405493 # average ReadReq mshr miss latency 1126system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72344.386192 # average ReadReq mshr miss latency 1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71676.843540 # average ReadReq mshr miss latency 1128system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33693.601561 # average WriteInvalidateReq mshr miss latency 1129system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33693.601561 # average WriteInvalidateReq mshr miss latency 1130system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17766.841315 # average UpgradeReq mshr miss latency 1131system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17766.841315 # average UpgradeReq mshr miss latency 1132system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency 1133system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency 1134system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69715.074699 # average ReadExReq mshr miss latency 1135system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69715.074699 # average ReadExReq mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74836.741064 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74907.889976 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69291.405493 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70554.378196 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70479.505240 # average overall mshr miss latency 1146system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency 1147system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156645.306565 # average ReadReq mshr uncacheable latency 1148system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97537.390976 # average ReadReq mshr uncacheable latency 1149system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153575.864115 # average WriteReq mshr uncacheable latency 1150system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153575.864115 # average WriteReq mshr uncacheable latency 1151system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency 1152system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155110.380410 # average overall mshr uncacheable latency 1153system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113317.304399 # average overall mshr uncacheable latency 1154system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1155system.cpu.toL2Bus.trans_dist::ReadReq 33924038 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadResp 33915953 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::Writeback 8539693 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351286 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244524 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::UpgradeReq 49695 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::UpgradeResp 49696 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::ReadExReq 2366369 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadExResp 2366369 # Transaction distribution 1167system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49299178 # Packet count per connected master and slave (bytes) 1168system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31033537 # Packet count per connected master and slave (bytes) 1169system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 698041 # Packet count per connected master and slave (bytes) 1170system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2292039 # Packet count per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_count::total 83322795 # Packet count per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577573568 # Cumulative packet size per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1259064522 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2320736 # Cumulative packet size per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7893144 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_size::total 2846851970 # Cumulative packet size per connected master and slave (bytes) 1177system.cpu.toL2Bus.snoops 553019 # Total snoops (count) 1178system.cpu.toL2Bus.snoop_fanout::samples 46264787 # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::mean 1.039533 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::stdev 0.194859 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::1 44435816 96.05% 96.05% # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::2 1828971 3.95% 100.00% # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::total 46264787 # Request fanout histogram 1189system.cpu.toL2Bus.reqLayer0.occupancy 32875768488 # Layer occupancy (ticks) 1190system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1191system.cpu.toL2Bus.snoopLayer0.occupancy 1167000 # Layer occupancy (ticks) 1192system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1193system.cpu.toL2Bus.respLayer0.occupancy 37011580552 # Layer occupancy (ticks) 1194system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1195system.cpu.toL2Bus.respLayer1.occupancy 15738706286 # Layer occupancy (ticks) 1196system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1197system.cpu.toL2Bus.respLayer2.occupancy 408640707 # Layer occupancy (ticks) 1198system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1199system.cpu.toL2Bus.respLayer3.occupancy 1306185489 # Layer occupancy (ticks) 1200system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1201system.iobus.trans_dist::ReadReq 40309 # Transaction distribution 1202system.iobus.trans_dist::ReadResp 40309 # Transaction distribution 1203system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1204system.iobus.trans_dist::WriteResp 29907 # Transaction distribution 1205system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 1206system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1208system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1209system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1213system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1214system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1215system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1219system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1220system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) 1223system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) 1224system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1225system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1226system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) 1227system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1233system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1234system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1241system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1242system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1243system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) 1244system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) 1245system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1246system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1247system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) 1248system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 1249system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1250system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1251system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1252system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1253system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1254system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1255system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1256system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1257system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1258system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1259system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1260system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1261system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1262system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1263system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1264system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1265system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1266system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1267system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1268system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1269system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1270system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1271system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1272system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1273system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1274system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1275system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1276system.iobus.reqLayer27.occupancy 606954435 # Layer occupancy (ticks) 1277system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1278system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1279system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1280system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1281system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1282system.iobus.respLayer3.occupancy 148397760 # Layer occupancy (ticks) 1283system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1284system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) 1285system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1286system.iocache.tags.replacements 115470 # number of replacements 1287system.iocache.tags.tagsinuse 10.439534 # Cycle average of tags in use 1288system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1289system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. 1290system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1291system.iocache.tags.warmup_cycle 13142420796000 # Cycle when the warmup percentage was hit. 1292system.iocache.tags.occ_blocks::realview.ethernet 3.524742 # Average occupied blocks per requestor 1293system.iocache.tags.occ_blocks::realview.ide 6.914791 # Average occupied blocks per requestor 1294system.iocache.tags.occ_percent::realview.ethernet 0.220296 # Average percentage of cache occupancy 1295system.iocache.tags.occ_percent::realview.ide 0.432174 # Average percentage of cache occupancy 1296system.iocache.tags.occ_percent::total 0.652471 # Average percentage of cache occupancy 1297system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1298system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1299system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1300system.iocache.tags.tag_accesses 1039749 # Number of tag accesses 1301system.iocache.tags.data_accesses 1039749 # Number of data accesses 1302system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1303system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses 1304system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses 1305system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1306system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1307system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 1308system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 1309system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1310system.iocache.demand_misses::realview.ide 8824 # number of demand (read+write) misses 1311system.iocache.demand_misses::total 8864 # number of demand (read+write) misses 1312system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1313system.iocache.overall_misses::realview.ide 8824 # number of overall misses 1314system.iocache.overall_misses::total 8864 # number of overall misses 1315system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles 1316system.iocache.ReadReq_miss_latency::realview.ide 1602204582 # number of ReadReq miss cycles 1317system.iocache.ReadReq_miss_latency::total 1607276582 # number of ReadReq miss cycles 1318system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles 1319system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles 1320system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19806517093 # number of WriteInvalidateReq miss cycles 1321system.iocache.WriteInvalidateReq_miss_latency::total 19806517093 # number of WriteInvalidateReq miss cycles 1322system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles 1323system.iocache.demand_miss_latency::realview.ide 1602204582 # number of demand (read+write) miss cycles 1324system.iocache.demand_miss_latency::total 1607629082 # number of demand (read+write) miss cycles 1325system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles 1326system.iocache.overall_miss_latency::realview.ide 1602204582 # number of overall miss cycles 1327system.iocache.overall_miss_latency::total 1607629082 # number of overall miss cycles 1328system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1329system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) 1330system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) 1331system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1332system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1333system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 1334system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 1335system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1336system.iocache.demand_accesses::realview.ide 8824 # number of demand (read+write) accesses 1337system.iocache.demand_accesses::total 8864 # number of demand (read+write) accesses 1338system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1339system.iocache.overall_accesses::realview.ide 8824 # number of overall (read+write) accesses 1340system.iocache.overall_accesses::total 8864 # number of overall (read+write) accesses 1341system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1342system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1343system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1344system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1345system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1346system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1347system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1348system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1349system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1350system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1351system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1352system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1353system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1354system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency 1355system.iocache.ReadReq_avg_miss_latency::realview.ide 181573.502040 # average ReadReq miss latency 1356system.iocache.ReadReq_avg_miss_latency::total 181387.719445 # average ReadReq miss latency 1357system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency 1358system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency 1359system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185690.740015 # average WriteInvalidateReq miss latency 1360system.iocache.WriteInvalidateReq_avg_miss_latency::total 185690.740015 # average WriteInvalidateReq miss latency 1361system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency 1362system.iocache.demand_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency 1363system.iocache.demand_avg_miss_latency::total 181366.096796 # average overall miss latency 1364system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency 1365system.iocache.overall_avg_miss_latency::realview.ide 181573.502040 # average overall miss latency 1366system.iocache.overall_avg_miss_latency::total 181366.096796 # average overall miss latency 1367system.iocache.blocked_cycles::no_mshrs 109809 # number of cycles access was blocked 1368system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1369system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked 1370system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1371system.iocache.avg_blocked_cycles::no_mshrs 6.797635 # average number of cycles each access was blocked 1372system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1373system.iocache.fast_writes 0 # number of fast writes performed 1374system.iocache.cache_copies 0 # number of cache copies performed 1375system.iocache.writebacks::writebacks 106631 # number of writebacks 1376system.iocache.writebacks::total 106631 # number of writebacks 1377system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1378system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses 1379system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses 1380system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1381system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1382system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 1383system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses 1384system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1385system.iocache.demand_mshr_misses::realview.ide 8824 # number of demand (read+write) MSHR misses 1386system.iocache.demand_mshr_misses::total 8864 # number of demand (read+write) MSHR misses 1387system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1388system.iocache.overall_mshr_misses::realview.ide 8824 # number of overall MSHR misses 1389system.iocache.overall_mshr_misses::total 8864 # number of overall MSHR misses 1390system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles 1391system.iocache.ReadReq_mshr_miss_latency::realview.ide 1142260060 # number of ReadReq MSHR miss cycles 1392system.iocache.ReadReq_mshr_miss_latency::total 1145402060 # number of ReadReq MSHR miss cycles 1393system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles 1394system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles 1395system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14259947135 # number of WriteInvalidateReq MSHR miss cycles 1396system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14259947135 # number of WriteInvalidateReq MSHR miss cycles 1397system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles 1398system.iocache.demand_mshr_miss_latency::realview.ide 1142260060 # number of demand (read+write) MSHR miss cycles 1399system.iocache.demand_mshr_miss_latency::total 1145595560 # number of demand (read+write) MSHR miss cycles 1400system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles 1401system.iocache.overall_mshr_miss_latency::realview.ide 1142260060 # number of overall MSHR miss cycles 1402system.iocache.overall_mshr_miss_latency::total 1145595560 # number of overall MSHR miss cycles 1403system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1404system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1405system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1406system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1407system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1408system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1409system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1410system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1411system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1412system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1413system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1414system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1415system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1416system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency 1417system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129449.236174 # average ReadReq mshr miss latency 1418system.iocache.ReadReq_avg_mshr_miss_latency::total 129263.295339 # average ReadReq mshr miss latency 1419system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency 1420system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency 1421system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133690.346649 # average WriteInvalidateReq mshr miss latency 1422system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133690.346649 # average WriteInvalidateReq mshr miss latency 1423system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency 1424system.iocache.demand_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency 1425system.iocache.demand_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency 1426system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency 1427system.iocache.overall_avg_mshr_miss_latency::realview.ide 129449.236174 # average overall mshr miss latency 1428system.iocache.overall_avg_mshr_miss_latency::total 129241.376354 # average overall mshr miss latency 1429system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1430system.membus.trans_dist::ReadReq 551255 # Transaction distribution 1431system.membus.trans_dist::ReadResp 551255 # Transaction distribution 1432system.membus.trans_dist::WriteReq 33705 # Transaction distribution 1433system.membus.trans_dist::WriteResp 33705 # Transaction distribution 1434system.membus.trans_dist::Writeback 1487541 # Transaction distribution 1435system.membus.trans_dist::WriteInvalidateReq 652894 # Transaction distribution 1436system.membus.trans_dist::WriteInvalidateResp 652894 # Transaction distribution 1437system.membus.trans_dist::UpgradeReq 39734 # Transaction distribution 1438system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1439system.membus.trans_dist::UpgradeResp 39735 # Transaction distribution 1440system.membus.trans_dist::ReadExReq 714242 # Transaction distribution 1441system.membus.trans_dist::ReadExResp 714242 # Transaction distribution 1442system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1443system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1444system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6912 # Packet count per connected master and slave (bytes) 1445system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5003208 # Packet count per connected master and slave (bytes) 1446system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5132856 # Packet count per connected master and slave (bytes) 1447system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335248 # Packet count per connected master and slave (bytes) 1448system.membus.pkt_count_system.iocache.mem_side::total 335248 # Packet count per connected master and slave (bytes) 1449system.membus.pkt_count::total 5468104 # Packet count per connected master and slave (bytes) 1450system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1451system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1452system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes) 1453system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201583148 # Cumulative packet size per connected master and slave (bytes) 1454system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201753546 # Cumulative packet size per connected master and slave (bytes) 1455system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14062080 # Cumulative packet size per connected master and slave (bytes) 1456system.membus.pkt_size_system.iocache.mem_side::total 14062080 # Cumulative packet size per connected master and slave (bytes) 1457system.membus.pkt_size::total 215815626 # Cumulative packet size per connected master and slave (bytes) 1458system.membus.snoops 3099 # Total snoops (count) 1459system.membus.snoop_fanout::samples 3479513 # Request fanout histogram 1460system.membus.snoop_fanout::mean 1 # Request fanout histogram 1461system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1462system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1463system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1464system.membus.snoop_fanout::1 3479513 100.00% 100.00% # Request fanout histogram 1465system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1466system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1467system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1468system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1469system.membus.snoop_fanout::total 3479513 # Request fanout histogram 1470system.membus.reqLayer0.occupancy 102597500 # Layer occupancy (ticks) 1471system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1472system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1473system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1474system.membus.reqLayer2.occupancy 5574500 # Layer occupancy (ticks) 1475system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1476system.membus.reqLayer5.occupancy 12409067173 # Layer occupancy (ticks) 1477system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1478system.membus.respLayer2.occupancy 7217145927 # Layer occupancy (ticks) 1479system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1480system.membus.respLayer3.occupancy 151545740 # Layer occupancy (ticks) 1481system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1482system.realview.ethernet.txBytes 966 # Bytes Transmitted 1483system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1484system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1485system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1486system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1487system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1488system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1489system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1490system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1491system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1492system.realview.ethernet.totPackets 3 # Total Packets 1493system.realview.ethernet.totBytes 966 # Total Bytes 1494system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1495system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1496system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1497system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1498system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1499system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1500system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1501system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1502system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1503system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1504system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1505system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1506system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1507system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1508system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1509system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1510system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1511system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1512system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1513system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1514system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1515system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1516system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1517system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1518system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1519system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1520system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1521system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1522system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1523system.realview.ethernet.droppedPackets 0 # number of packets dropped 1524 1525---------- End Simulation Statistics ---------- 1526