stats.txt revision 11441:0edcf757b6a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.535940 # Number of seconds simulated 4sim_ticks 47535940136000 # Number of ticks simulated 5final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 225035 # Simulator instruction rate (inst/s) 8host_op_rate 264677 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11911388135 # Simulator tick rate (ticks/s) 10host_mem_usage 769700 # Number of bytes of host memory used 11host_seconds 3990.80 # Real time elapsed on the host 12sim_insts 898069628 # Number of instructions simulated 13sim_ops 1056270581 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 14782784 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 150400 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 127744 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3048640 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 9523856 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 12507584 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 413056 # Number of bytes read from this memory 27system.physmem.bytes_read::total 63147416 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 8161024 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3048640 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 11209664 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 75703424 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 75724008 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1402 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 127516 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 222570 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 230981 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2350 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1996 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 47635 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 148823 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 195431 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6454 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 986704 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1182866 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1185440 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2081 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1888 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 171681 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 299640 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 310981 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3164 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2687 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 64133 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 200351 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 263118 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 8689 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1328414 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 171681 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 64133 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 235815 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1592551 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1592984 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1592551 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2081 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1888 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 171681 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 300073 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 310981 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3164 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2687 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 64133 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 200351 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 263118 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 8689 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2921398 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 986704 # Number of read requests accepted 84system.physmem.writeReqs 1185440 # Number of write requests accepted 85system.physmem.readBursts 986704 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1185440 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 63115328 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue 89system.physmem.bytesWritten 75722560 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 63147416 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 75724008 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 63842 # Per bank write bursts 96system.physmem.perBankRdBursts::1 66317 # Per bank write bursts 97system.physmem.perBankRdBursts::2 58522 # Per bank write bursts 98system.physmem.perBankRdBursts::3 64863 # Per bank write bursts 99system.physmem.perBankRdBursts::4 59095 # Per bank write bursts 100system.physmem.perBankRdBursts::5 67998 # Per bank write bursts 101system.physmem.perBankRdBursts::6 58322 # Per bank write bursts 102system.physmem.perBankRdBursts::7 56006 # Per bank write bursts 103system.physmem.perBankRdBursts::8 52486 # Per bank write bursts 104system.physmem.perBankRdBursts::9 111449 # Per bank write bursts 105system.physmem.perBankRdBursts::10 50777 # Per bank write bursts 106system.physmem.perBankRdBursts::11 58061 # Per bank write bursts 107system.physmem.perBankRdBursts::12 51458 # Per bank write bursts 108system.physmem.perBankRdBursts::13 52890 # Per bank write bursts 109system.physmem.perBankRdBursts::14 54883 # Per bank write bursts 110system.physmem.perBankRdBursts::15 59208 # Per bank write bursts 111system.physmem.perBankWrBursts::0 77123 # Per bank write bursts 112system.physmem.perBankWrBursts::1 81948 # Per bank write bursts 113system.physmem.perBankWrBursts::2 74623 # Per bank write bursts 114system.physmem.perBankWrBursts::3 80009 # Per bank write bursts 115system.physmem.perBankWrBursts::4 75007 # Per bank write bursts 116system.physmem.perBankWrBursts::5 80611 # Per bank write bursts 117system.physmem.perBankWrBursts::6 72005 # Per bank write bursts 118system.physmem.perBankWrBursts::7 72012 # Per bank write bursts 119system.physmem.perBankWrBursts::8 68266 # Per bank write bursts 120system.physmem.perBankWrBursts::9 73887 # Per bank write bursts 121system.physmem.perBankWrBursts::10 67546 # Per bank write bursts 122system.physmem.perBankWrBursts::11 72517 # Per bank write bursts 123system.physmem.perBankWrBursts::12 68786 # Per bank write bursts 124system.physmem.perBankWrBursts::13 69993 # Per bank write bursts 125system.physmem.perBankWrBursts::14 72865 # Per bank write bursts 126system.physmem.perBankWrBursts::15 75967 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 44 # Number of times write queue was full causing retry 129system.physmem.totGap 47535938023500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 986674 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1182866 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 668450 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 115815 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 42206 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 32986 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 28484 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 26396 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 23877 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 21311 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 18072 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 3298 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1045 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 854 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 616 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 345 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 301 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 189 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 31147 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 37996 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 51637 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 54968 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 59491 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 61707 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 64761 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 68893 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 71932 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 72504 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 73761 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 76926 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 74288 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 75236 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 82718 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 68266 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 65794 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 4098 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 2036 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1439 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1105 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 896 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 640 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 509 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 526 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 444 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 386 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 373 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 288 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 232 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 251 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 147 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 178 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 188 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 200 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 135 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 984595 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 141.009629 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 96.339121 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 189.114371 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 670707 68.12% 68.12% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 190612 19.36% 87.48% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 44448 4.51% 91.99% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 20648 2.10% 94.09% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 14900 1.51% 95.60% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 9763 0.99% 96.60% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 5507 0.56% 97.16% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 4424 0.45% 97.60% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 23586 2.40% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 984595 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 61315 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 16.083617 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 159.391032 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 61313 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 61315 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 61315 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 19.296502 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.510563 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 8.190386 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 48917 79.78% 79.78% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 5503 8.97% 88.75% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 3053 4.98% 93.73% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 1653 2.70% 96.43% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 478 0.78% 97.21% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 276 0.45% 97.66% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 266 0.43% 98.09% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 90 0.15% 98.24% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 261 0.43% 98.67% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 71 0.12% 98.78% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 38 0.06% 98.84% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 55 0.09% 98.93% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 246 0.40% 99.33% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 32 0.05% 99.39% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 47 0.08% 99.46% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 156 0.25% 99.89% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::112-115 1 0.00% 99.90% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 24 0.04% 99.95% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::total 61315 # Writes before turning the bus around for reads 302system.physmem.totQLat 31916274746 # Total ticks spent queuing 303system.physmem.totMemAccLat 50407093496 # Total ticks spent from burst creation until serviced by the DRAM 304system.physmem.totBusLat 4930885000 # Total ticks spent in databus transfers 305system.physmem.avgQLat 32363.64 # Average queueing delay per DRAM burst 306system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 307system.physmem.avgMemAccLat 51113.64 # Average memory access latency per DRAM burst 308system.physmem.avgRdBW 1.33 # Average DRAM read bandwidth in MiByte/s 309system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s 310system.physmem.avgRdBWSys 1.33 # Average system read bandwidth in MiByte/s 311system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s 312system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 313system.physmem.busUtil 0.02 # Data bus utilization in percentage 314system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 315system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 316system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 317system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing 318system.physmem.readRowHits 734466 # Number of row buffer hits during reads 319system.physmem.writeRowHits 450279 # Number of row buffer hits during writes 320system.physmem.readRowHitRate 74.48 # Row buffer hit rate for reads 321system.physmem.writeRowHitRate 38.06 # Row buffer hit rate for writes 322system.physmem.avgGap 21884340.09 # Average gap between requests 323system.physmem.pageHitRate 54.61 # Row buffer hit rate, read and write combined 324system.physmem_0.actEnergy 3920933520 # Energy for activate commands per rank (pJ) 325system.physmem_0.preEnergy 2139398250 # Energy for precharge commands per rank (pJ) 326system.physmem_0.readEnergy 3860672400 # Energy for read commands per rank (pJ) 327system.physmem_0.writeEnergy 3974430240 # Energy for write commands per rank (pJ) 328system.physmem_0.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) 329system.physmem_0.actBackEnergy 1203845511330 # Energy for active background per rank (pJ) 330system.physmem_0.preBackEnergy 27465556979250 # Energy for precharge background per rank (pJ) 331system.physmem_0.totalEnergy 31788114192270 # Total energy per rank (pJ) 332system.physmem_0.averagePower 668.717535 # Core power per rank (mW) 333system.physmem_0.memoryStateTime::IDLE 45690953287273 # Time in different power states 334system.physmem_0.memoryStateTime::REF 1587329380000 # Time in different power states 335system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 336system.physmem_0.memoryStateTime::ACT 257656491727 # Time in different power states 337system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 338system.physmem_1.actEnergy 3522604680 # Energy for activate commands per rank (pJ) 339system.physmem_1.preEnergy 1922056125 # Energy for precharge commands per rank (pJ) 340system.physmem_1.readEnergy 3831445800 # Energy for read commands per rank (pJ) 341system.physmem_1.writeEnergy 3692478960 # Energy for write commands per rank (pJ) 342system.physmem_1.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) 343system.physmem_1.actBackEnergy 1196085851100 # Energy for active background per rank (pJ) 344system.physmem_1.preBackEnergy 27472363698750 # Energy for precharge background per rank (pJ) 345system.physmem_1.totalEnergy 31786234402695 # Total energy per rank (pJ) 346system.physmem_1.averagePower 668.677991 # Core power per rank (mW) 347system.physmem_1.memoryStateTime::IDLE 45702273449121 # Time in different power states 348system.physmem_1.memoryStateTime::REF 1587329380000 # Time in different power states 349system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 350system.physmem_1.memoryStateTime::ACT 246336261879 # Time in different power states 351system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 352system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 357system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 358system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 359system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 360system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 363system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 365system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 378system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 379system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 380system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 381system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 382system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 383system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 384system.cpu0.branchPred.lookups 146462396 # Number of BP lookups 385system.cpu0.branchPred.condPredicted 102364881 # Number of conditional branches predicted 386system.cpu0.branchPred.condIncorrect 6839955 # Number of conditional branches incorrect 387system.cpu0.branchPred.BTBLookups 108739004 # Number of BTB lookups 388system.cpu0.branchPred.BTBHits 75372629 # Number of BTB hits 389system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 390system.cpu0.branchPred.BTBHitPct 69.315173 # BTB Hit Percentage 391system.cpu0.branchPred.usedRAS 17612403 # Number of times the RAS was used to get a target. 392system.cpu0.branchPred.RASInCorrect 1195732 # Number of incorrect RAS predictions. 393system.cpu0.branchPred.indirectLookups 3915449 # Number of indirect predictor lookups. 394system.cpu0.branchPred.indirectHits 2665463 # Number of indirect target hits. 395system.cpu0.branchPred.indirectMisses 1249986 # Number of indirect misses. 396system.cpu0.branchPredindirectMispredicted 447212 # Number of mispredicted indirect branches. 397system.cpu_clk_domain.clock 500 # Clock period in ticks 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 405system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 406system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 407system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 408system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 409system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 410system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 411system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 412system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 413system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 414system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 415system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 416system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 417system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 418system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 419system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 420system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 421system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 422system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 423system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 424system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 425system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 426system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 427system.cpu0.dtb.walker.walks 302048 # Table walker walks requested 428system.cpu0.dtb.walker.walksLong 302048 # Table walker walks initiated with long descriptors 429system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10564 # Level at which table walker walks with long descriptors terminate 430system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84260 # Level at which table walker walks with long descriptors terminate 431system.cpu0.dtb.walker.walkWaitTime::samples 302048 # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::0 302048 100.00% 100.00% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::total 302048 # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkCompletionTime::samples 94824 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::0-65535 93928 99.06% 99.06% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.18% 99.23% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::131072-196607 600 0.63% 99.86% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.90% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::262144-327679 32 0.03% 99.93% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::393216-458751 34 0.04% 99.98% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::total 94824 # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 452system.cpu0.dtb.walker.walkPageSizes::4K 84260 88.86% 88.86% # Table walker page sizes translated 453system.cpu0.dtb.walker.walkPageSizes::2M 10564 11.14% 100.00% # Table walker page sizes translated 454system.cpu0.dtb.walker.walkPageSizes::total 94824 # Table walker page sizes translated 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302048 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302048 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94824 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94824 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin::total 396872 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.inst_hits 0 # ITB inst hits 463system.cpu0.dtb.inst_misses 0 # ITB inst misses 464system.cpu0.dtb.read_hits 94909868 # DTB read hits 465system.cpu0.dtb.read_misses 253021 # DTB read misses 466system.cpu0.dtb.write_hits 83284387 # DTB write hits 467system.cpu0.dtb.write_misses 49027 # DTB write misses 468system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 469system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 470system.cpu0.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 471system.cpu0.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 472system.cpu0.dtb.flush_entries 38313 # Number of entries that have been flushed from TLB 473system.cpu0.dtb.align_faults 2113 # Number of TLB faults due to alignment restrictions 474system.cpu0.dtb.prefetch_faults 10577 # Number of TLB faults due to prefetch 475system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 476system.cpu0.dtb.perms_faults 10792 # Number of TLB faults due to permissions restrictions 477system.cpu0.dtb.read_accesses 95162889 # DTB read accesses 478system.cpu0.dtb.write_accesses 83333414 # DTB write accesses 479system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 480system.cpu0.dtb.hits 178194255 # DTB hits 481system.cpu0.dtb.misses 302048 # DTB misses 482system.cpu0.dtb.accesses 178496303 # DTB accesses 483system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 492system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 493system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 494system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 495system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 496system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 499system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 501system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 502system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 506system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 507system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 508system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 509system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 510system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 511system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 512system.cpu0.itb.walker.walks 66529 # Table walker walks requested 513system.cpu0.itb.walker.walksLong 66529 # Table walker walks initiated with long descriptors 514system.cpu0.itb.walker.walksLongTerminationLevel::Level2 603 # Level at which table walker walks with long descriptors terminate 515system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54822 # Level at which table walker walks with long descriptors terminate 516system.cpu0.itb.walker.walkWaitTime::samples 66529 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::0 66529 100.00% 100.00% # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::total 66529 # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkCompletionTime::samples 55425 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::0-32767 51379 92.70% 92.70% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::32768-65535 3140 5.67% 98.37% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::65536-98303 12 0.02% 98.39% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.39% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::131072-163839 536 0.97% 99.36% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::163840-196607 270 0.49% 99.84% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::196608-229375 8 0.01% 99.86% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.88% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.91% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.96% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::total 55425 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 540system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 541system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 542system.cpu0.itb.walker.walkPageSizes::4K 54822 98.91% 98.91% # Table walker page sizes translated 543system.cpu0.itb.walker.walkPageSizes::2M 603 1.09% 100.00% # Table walker page sizes translated 544system.cpu0.itb.walker.walkPageSizes::total 55425 # Table walker page sizes translated 545system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66529 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66529 # Table walker requests started/completed, data/inst 548system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 549system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55425 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55425 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin::total 121954 # Table walker requests started/completed, data/inst 552system.cpu0.itb.inst_hits 260612167 # ITB inst hits 553system.cpu0.itb.inst_misses 66529 # ITB inst misses 554system.cpu0.itb.read_hits 0 # DTB read hits 555system.cpu0.itb.read_misses 0 # DTB read misses 556system.cpu0.itb.write_hits 0 # DTB write hits 557system.cpu0.itb.write_misses 0 # DTB write misses 558system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 559system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 560system.cpu0.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 561system.cpu0.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 562system.cpu0.itb.flush_entries 27578 # Number of entries that have been flushed from TLB 563system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 564system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 565system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 566system.cpu0.itb.perms_faults 178681 # Number of TLB faults due to permissions restrictions 567system.cpu0.itb.read_accesses 0 # DTB read accesses 568system.cpu0.itb.write_accesses 0 # DTB write accesses 569system.cpu0.itb.inst_accesses 260678696 # ITB inst accesses 570system.cpu0.itb.hits 260612167 # DTB hits 571system.cpu0.itb.misses 66529 # DTB misses 572system.cpu0.itb.accesses 260678696 # DTB accesses 573system.cpu0.numCycles 1099930824 # number of cpu cycles simulated 574system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 576system.cpu0.committedInsts 487305462 # Number of instructions committed 577system.cpu0.committedOps 572197777 # Number of ops (including micro ops) committed 578system.cpu0.discardedOps 47186623 # Number of ops (including micro ops) which were discarded before commit 579system.cpu0.numFetchSuspends 4440 # Number of times Execute suspended instruction fetching 580system.cpu0.quiesceCycles 93972724601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 581system.cpu0.cpi 2.257169 # CPI: cycles per instruction 582system.cpu0.ipc 0.443033 # IPC: instructions per cycle 583system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 584system.cpu0.op_class_0::IntAlu 396450876 69.29% 69.29% # Class of committed instruction 585system.cpu0.op_class_0::IntMult 1302433 0.23% 69.51% # Class of committed instruction 586system.cpu0.op_class_0::IntDiv 64217 0.01% 69.52% # Class of committed instruction 587system.cpu0.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 588system.cpu0.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 589system.cpu0.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 590system.cpu0.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 591system.cpu0.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 592system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 593system.cpu0.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 594system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 595system.cpu0.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 596system.cpu0.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 597system.cpu0.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 598system.cpu0.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 599system.cpu0.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 600system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 601system.cpu0.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 602system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 603system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 604system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction 605system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 606system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction 607system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction 608system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 609system.cpu0.op_class_0::SimdFloatMisc 76920 0.01% 69.54% # Class of committed instruction 610system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction 611system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction 612system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction 613system.cpu0.op_class_0::MemRead 91382938 15.97% 85.51% # Class of committed instruction 614system.cpu0.op_class_0::MemWrite 82920392 14.49% 100.00% # Class of committed instruction 615system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 616system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 617system.cpu0.op_class_0::total 572197777 # Class of committed instruction 618system.cpu0.kern.inst.arm 0 # number of arm instructions executed 619system.cpu0.kern.inst.quiesce 13277 # number of quiesce instructions executed 620system.cpu0.tickCycles 780613530 # Number of cycles that the object actually ticked 621system.cpu0.idleCycles 319317294 # Total number of cycles that the object has spent stopped 622system.cpu0.dcache.tags.replacements 5972011 # number of replacements 623system.cpu0.dcache.tags.tagsinuse 508.033077 # Cycle average of tags in use 624system.cpu0.dcache.tags.total_refs 169168179 # Total number of references to valid blocks. 625system.cpu0.dcache.tags.sampled_refs 5972523 # Sample count of references to valid blocks. 626system.cpu0.dcache.tags.avg_refs 28.324408 # Average number of references to valid blocks. 627system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 628system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.033077 # Average occupied blocks per requestor 629system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992252 # Average percentage of cache occupancy 630system.cpu0.dcache.tags.occ_percent::total 0.992252 # Average percentage of cache occupancy 631system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 632system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 633system.cpu0.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id 634system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 635system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 636system.cpu0.dcache.tags.tag_accesses 359361260 # Number of tag accesses 637system.cpu0.dcache.tags.data_accesses 359361260 # Number of data accesses 638system.cpu0.dcache.ReadReq_hits::cpu0.data 87043361 # number of ReadReq hits 639system.cpu0.dcache.ReadReq_hits::total 87043361 # number of ReadReq hits 640system.cpu0.dcache.WriteReq_hits::cpu0.data 77242749 # number of WriteReq hits 641system.cpu0.dcache.WriteReq_hits::total 77242749 # number of WriteReq hits 642system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits 643system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits 644system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits 645system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits 646system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits 647system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits 648system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits 649system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits 650system.cpu0.dcache.demand_hits::cpu0.data 164286110 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 164286110 # number of demand (read+write) hits 652system.cpu0.dcache.overall_hits::cpu0.data 164591140 # number of overall hits 653system.cpu0.dcache.overall_hits::total 164591140 # number of overall hits 654system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses 658system.cpu0.dcache.SoftPFReq_misses::cpu0.data 661742 # number of SoftPFReq misses 659system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses 660system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses 661system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses 662system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 # number of LoadLockedReq misses 663system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses 664system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses 665system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses 666system.cpu0.dcache.demand_misses::cpu0.data 6153573 # number of demand (read+write) misses 667system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses 668system.cpu0.dcache.overall_misses::cpu0.data 6815315 # number of overall misses 669system.cpu0.dcache.overall_misses::total 6815315 # number of overall misses 670system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles 671system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51167444000 # number of WriteLineReq miss cycles 675system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2860725000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.LoadLockedReq_miss_latency::total 2860725000 # number of LoadLockedReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles 681system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles 682system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500 # number of demand (read+write) miss cycles 683system.cpu0.dcache.demand_miss_latency::total 126172350500 # number of demand (read+write) miss cycles 684system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500 # number of overall miss cycles 685system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles 686system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.WriteReq_accesses::total 79702974 # number of WriteReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 966772 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1134952 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.WriteLineReq_accesses::total 1134952 # number of WriteLineReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses) 697system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses) 698system.cpu0.dcache.demand_accesses::cpu0.data 170439683 # number of demand (read+write) accesses 699system.cpu0.dcache.demand_accesses::total 170439683 # number of demand (read+write) accesses 700system.cpu0.dcache.overall_accesses::cpu0.data 171406455 # number of overall (read+write) accesses 701system.cpu0.dcache.overall_accesses::total 171406455 # number of overall (read+write) accesses 702system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses 703system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::total 0.030867 # miss rate for WriteReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.684486 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.SoftPFReq_miss_rate::total 0.684486 # miss rate for SoftPFReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.747073 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.WriteLineReq_miss_rate::total 0.747073 # miss rate for WriteLineReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses 713system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses 714system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036104 # miss rate for demand accesses 715system.cpu0.dcache.demand_miss_rate::total 0.036104 # miss rate for demand accesses 716system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039761 # miss rate for overall accesses 717system.cpu0.dcache.overall_miss_rate::total 0.039761 # miss rate for overall accesses 718system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency 719system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency 721system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640 # average WriteLineReq miss latency 723system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199 # average overall miss latency 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu0.dcache.fast_writes 0 # number of fast writes performed 741system.cpu0.dcache.cache_copies 0 # number of cache copies performed 742system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks 743system.cpu0.dcache.writebacks::total 5972043 # number of writebacks 744system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits 745system.cpu0.dcache.ReadReq_mshr_hits::total 444932 # number of ReadReq MSHR hits 746system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012331 # number of WriteReq MSHR hits 747system.cpu0.dcache.WriteReq_mshr_hits::total 1012331 # number of WriteReq MSHR hits 748system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits 749system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits 750system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 # number of LoadLockedReq MSHR hits 751system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits 752system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits 753system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits 754system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457263 # number of demand (read+write) MSHR hits 755system.cpu0.dcache.demand_mshr_hits::total 1457263 # number of demand (read+write) MSHR hits 756system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457263 # number of overall MSHR hits 757system.cpu0.dcache.overall_mshr_hits::total 1457263 # number of overall MSHR hits 758system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses 759system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses 760system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses 761system.cpu0.dcache.WriteReq_mshr_misses::total 1447894 # number of WriteReq MSHR misses 762system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660170 # number of SoftPFReq MSHR misses 763system.cpu0.dcache.SoftPFReq_mshr_misses::total 660170 # number of SoftPFReq MSHR misses 764system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 847802 # number of WriteLineReq MSHR misses 765system.cpu0.dcache.WriteLineReq_mshr_misses::total 847802 # number of WriteLineReq MSHR misses 766system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 # number of LoadLockedReq MSHR misses 767system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses 768system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses 769system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses 770system.cpu0.dcache.demand_mshr_misses::cpu0.data 4696310 # number of demand (read+write) MSHR misses 771system.cpu0.dcache.demand_mshr_misses::total 4696310 # number of demand (read+write) MSHR misses 772system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356480 # number of overall MSHR misses 773system.cpu0.dcache.overall_mshr_misses::total 5356480 # number of overall MSHR misses 774system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable 775system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable 776system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 777system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable 778system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses 779system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62700 # number of overall MSHR uncacheable misses 780system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50756784000 # number of ReadReq MSHR miss cycles 781system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50756784000 # number of ReadReq MSHR miss cycles 782system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36350818500 # number of WriteReq MSHR miss cycles 783system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36350818500 # number of WriteReq MSHR miss cycles 784system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16579433500 # number of SoftPFReq MSHR miss cycles 785system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16579433500 # number of SoftPFReq MSHR miss cycles 786system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50311370000 # number of WriteLineReq MSHR miss cycles 787system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50311370000 # number of WriteLineReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1783759500 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 # number of StoreCondReq MSHR miss cycles 791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles 792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles 793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 87107602500 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 87107602500 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000 # number of overall MSHR miss cycles 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5837295500 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5837295500 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11878686500 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11878686500 # number of overall MSHR uncacheable cycles 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018166 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.682860 # mshr miss rate for SoftPFReq accesses 809system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses 810system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses 811system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses 812system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses 813system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses 814system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses 815system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses 816system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027554 # mshr miss rate for demand accesses 817system.cpu0.dcache.demand_mshr_miss_rate::total 0.027554 # mshr miss rate for demand accesses 818system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031250 # mshr miss rate for overall accesses 819system.cpu0.dcache.overall_mshr_miss_rate::total 0.031250 # mshr miss rate for overall accesses 820system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency 821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency 822system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency 823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency 824system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency 825system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency 826system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency 827system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency 828system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency 829system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency 830system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 # average StoreCondReq mshr miss latency 831system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency 832system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 833system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 834system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674 # average overall mshr miss latency 835system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674 # average overall mshr miss latency 836system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531 # average overall mshr miss latency 837system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531 # average overall mshr miss latency 838system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency 839system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency 840system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398 # average WriteReq mshr uncacheable latency 841system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398 # average WriteReq mshr uncacheable latency 842system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247 # average overall mshr uncacheable latency 843system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247 # average overall mshr uncacheable latency 844system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 845system.cpu0.icache.tags.replacements 10516028 # number of replacements 846system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use 847system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. 848system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks. 849system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks. 850system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit. 851system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor 852system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy 853system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy 854system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 855system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 856system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 857system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 858system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 859system.cpu0.icache.tags.tag_accesses 531372181 # Number of tag accesses 860system.cpu0.icache.tags.data_accesses 531372181 # Number of data accesses 861system.cpu0.icache.ReadReq_hits::cpu0.inst 249911266 # number of ReadReq hits 862system.cpu0.icache.ReadReq_hits::total 249911266 # number of ReadReq hits 863system.cpu0.icache.demand_hits::cpu0.inst 249911266 # number of demand (read+write) hits 864system.cpu0.icache.demand_hits::total 249911266 # number of demand (read+write) hits 865system.cpu0.icache.overall_hits::cpu0.inst 249911266 # number of overall hits 866system.cpu0.icache.overall_hits::total 249911266 # number of overall hits 867system.cpu0.icache.ReadReq_misses::cpu0.inst 10516550 # number of ReadReq misses 868system.cpu0.icache.ReadReq_misses::total 10516550 # number of ReadReq misses 869system.cpu0.icache.demand_misses::cpu0.inst 10516550 # number of demand (read+write) misses 870system.cpu0.icache.demand_misses::total 10516550 # number of demand (read+write) misses 871system.cpu0.icache.overall_misses::cpu0.inst 10516550 # number of overall misses 872system.cpu0.icache.overall_misses::total 10516550 # number of overall misses 873system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 109481334000 # number of ReadReq miss cycles 874system.cpu0.icache.ReadReq_miss_latency::total 109481334000 # number of ReadReq miss cycles 875system.cpu0.icache.demand_miss_latency::cpu0.inst 109481334000 # number of demand (read+write) miss cycles 876system.cpu0.icache.demand_miss_latency::total 109481334000 # number of demand (read+write) miss cycles 877system.cpu0.icache.overall_miss_latency::cpu0.inst 109481334000 # number of overall miss cycles 878system.cpu0.icache.overall_miss_latency::total 109481334000 # number of overall miss cycles 879system.cpu0.icache.ReadReq_accesses::cpu0.inst 260427816 # number of ReadReq accesses(hits+misses) 880system.cpu0.icache.ReadReq_accesses::total 260427816 # number of ReadReq accesses(hits+misses) 881system.cpu0.icache.demand_accesses::cpu0.inst 260427816 # number of demand (read+write) accesses 882system.cpu0.icache.demand_accesses::total 260427816 # number of demand (read+write) accesses 883system.cpu0.icache.overall_accesses::cpu0.inst 260427816 # number of overall (read+write) accesses 884system.cpu0.icache.overall_accesses::total 260427816 # number of overall (read+write) accesses 885system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040382 # miss rate for ReadReq accesses 886system.cpu0.icache.ReadReq_miss_rate::total 0.040382 # miss rate for ReadReq accesses 887system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040382 # miss rate for demand accesses 888system.cpu0.icache.demand_miss_rate::total 0.040382 # miss rate for demand accesses 889system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040382 # miss rate for overall accesses 890system.cpu0.icache.overall_miss_rate::total 0.040382 # miss rate for overall accesses 891system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10410.384965 # average ReadReq miss latency 892system.cpu0.icache.ReadReq_avg_miss_latency::total 10410.384965 # average ReadReq miss latency 893system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency 894system.cpu0.icache.demand_avg_miss_latency::total 10410.384965 # average overall miss latency 895system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency 896system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency 897system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 898system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 899system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 900system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 901system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 902system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 903system.cpu0.icache.fast_writes 0 # number of fast writes performed 904system.cpu0.icache.cache_copies 0 # number of cache copies performed 905system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks 906system.cpu0.icache.writebacks::total 10516028 # number of writebacks 907system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses 908system.cpu0.icache.ReadReq_mshr_misses::total 10516550 # number of ReadReq MSHR misses 909system.cpu0.icache.demand_mshr_misses::cpu0.inst 10516550 # number of demand (read+write) MSHR misses 910system.cpu0.icache.demand_mshr_misses::total 10516550 # number of demand (read+write) MSHR misses 911system.cpu0.icache.overall_mshr_misses::cpu0.inst 10516550 # number of overall MSHR misses 912system.cpu0.icache.overall_mshr_misses::total 10516550 # number of overall MSHR misses 913system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 914system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 915system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 916system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 917system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104223059500 # number of ReadReq MSHR miss cycles 918system.cpu0.icache.ReadReq_mshr_miss_latency::total 104223059500 # number of ReadReq MSHR miss cycles 919system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104223059500 # number of demand (read+write) MSHR miss cycles 920system.cpu0.icache.demand_mshr_miss_latency::total 104223059500 # number of demand (read+write) MSHR miss cycles 921system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104223059500 # number of overall MSHR miss cycles 922system.cpu0.icache.overall_mshr_miss_latency::total 104223059500 # number of overall MSHR miss cycles 923system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 924system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 925system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 926system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 927system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for ReadReq accesses 928system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040382 # mshr miss rate for ReadReq accesses 929system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for demand accesses 930system.cpu0.icache.demand_mshr_miss_rate::total 0.040382 # mshr miss rate for demand accesses 931system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for overall accesses 932system.cpu0.icache.overall_mshr_miss_rate::total 0.040382 # mshr miss rate for overall accesses 933system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average ReadReq mshr miss latency 934system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9910.385012 # average ReadReq mshr miss latency 935system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 936system.cpu0.icache.demand_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 937system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 938system.cpu0.icache.overall_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 939system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 940system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 941system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 942system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 943system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 944system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued 945system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified 946system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue 947system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 948system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 949system.cpu0.l2cache.prefetcher.pfSpanPage 1038823 # number of prefetches not generated due to page crossing 950system.cpu0.l2cache.tags.replacements 2850300 # number of replacements 951system.cpu0.l2cache.tags.tagsinuse 16126.746563 # Cycle average of tags in use 952system.cpu0.l2cache.tags.total_refs 26039957 # Total number of references to valid blocks. 953system.cpu0.l2cache.tags.sampled_refs 2866458 # Sample count of references to valid blocks. 954system.cpu0.l2cache.tags.avg_refs 9.084367 # Average number of references to valid blocks. 955system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. 956system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.163009 # Average occupied blocks per requestor 957system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.302883 # Average occupied blocks per requestor 958system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.950246 # Average occupied blocks per requestor 959system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 696.330425 # Average occupied blocks per requestor 960system.cpu0.l2cache.tags.occ_percent::writebacks 0.932505 # Average percentage of cache occupancy 961system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004596 # Average percentage of cache occupancy 962system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004697 # Average percentage of cache occupancy 963system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.042501 # Average percentage of cache occupancy 964system.cpu0.l2cache.tags.occ_percent::total 0.984298 # Average percentage of cache occupancy 965system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1240 # Occupied blocks per task id 966system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id 967system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14860 # Occupied blocks per task id 968system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id 969system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 522 # Occupied blocks per task id 970system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 622 # Occupied blocks per task id 971system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id 972system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 975system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 976system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1092 # Occupied blocks per task id 977system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5314 # Occupied blocks per task id 978system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7823 # Occupied blocks per task id 979system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id 980system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.075684 # Percentage of cache occupancy per task id 981system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id 982system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.906982 # Percentage of cache occupancy per task id 983system.cpu0.l2cache.tags.tag_accesses 554897291 # Number of tag accesses 984system.cpu0.l2cache.tags.data_accesses 554897291 # Number of data accesses 985system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 569819 # number of ReadReq hits 986system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 172472 # number of ReadReq hits 987system.cpu0.l2cache.ReadReq_hits::total 742291 # number of ReadReq hits 988system.cpu0.l2cache.WritebackDirty_hits::writebacks 3893367 # number of WritebackDirty hits 989system.cpu0.l2cache.WritebackDirty_hits::total 3893367 # number of WritebackDirty hits 990system.cpu0.l2cache.WritebackClean_hits::writebacks 12591574 # number of WritebackClean hits 991system.cpu0.l2cache.WritebackClean_hits::total 12591574 # number of WritebackClean hits 992system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 369 # number of UpgradeReq hits 993system.cpu0.l2cache.UpgradeReq_hits::total 369 # number of UpgradeReq hits 994system.cpu0.l2cache.ReadExReq_hits::cpu0.data 917893 # number of ReadExReq hits 995system.cpu0.l2cache.ReadExReq_hits::total 917893 # number of ReadExReq hits 996system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9767058 # number of ReadCleanReq hits 997system.cpu0.l2cache.ReadCleanReq_hits::total 9767058 # number of ReadCleanReq hits 998system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3005656 # number of ReadSharedReq hits 999system.cpu0.l2cache.ReadSharedReq_hits::total 3005656 # number of ReadSharedReq hits 1000system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 229746 # number of InvalidateReq hits 1001system.cpu0.l2cache.InvalidateReq_hits::total 229746 # number of InvalidateReq hits 1002system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 569819 # number of demand (read+write) hits 1003system.cpu0.l2cache.demand_hits::cpu0.itb.walker 172472 # number of demand (read+write) hits 1004system.cpu0.l2cache.demand_hits::cpu0.inst 9767058 # number of demand (read+write) hits 1005system.cpu0.l2cache.demand_hits::cpu0.data 3923549 # number of demand (read+write) hits 1006system.cpu0.l2cache.demand_hits::total 14432898 # number of demand (read+write) hits 1007system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 569819 # number of overall hits 1008system.cpu0.l2cache.overall_hits::cpu0.itb.walker 172472 # number of overall hits 1009system.cpu0.l2cache.overall_hits::cpu0.inst 9767058 # number of overall hits 1010system.cpu0.l2cache.overall_hits::cpu0.data 3923549 # number of overall hits 1011system.cpu0.l2cache.overall_hits::total 14432898 # number of overall hits 1012system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11861 # number of ReadReq misses 1013system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8276 # number of ReadReq misses 1014system.cpu0.l2cache.ReadReq_misses::total 20137 # number of ReadReq misses 1015system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 1016system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 1017system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 260415 # number of UpgradeReq misses 1018system.cpu0.l2cache.UpgradeReq_misses::total 260415 # number of UpgradeReq misses 1019system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200530 # number of SCUpgradeReq misses 1020system.cpu0.l2cache.SCUpgradeReq_misses::total 200530 # number of SCUpgradeReq misses 1021system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 1022system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1023system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278151 # number of ReadExReq misses 1024system.cpu0.l2cache.ReadExReq_misses::total 278151 # number of ReadExReq misses 1025system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 749491 # number of ReadCleanReq misses 1026system.cpu0.l2cache.ReadCleanReq_misses::total 749491 # number of ReadCleanReq misses 1027system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1029564 # number of ReadSharedReq misses 1028system.cpu0.l2cache.ReadSharedReq_misses::total 1029564 # number of ReadSharedReq misses 1029system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 615811 # number of InvalidateReq misses 1030system.cpu0.l2cache.InvalidateReq_misses::total 615811 # number of InvalidateReq misses 1031system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11861 # number of demand (read+write) misses 1032system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8276 # number of demand (read+write) misses 1033system.cpu0.l2cache.demand_misses::cpu0.inst 749491 # number of demand (read+write) misses 1034system.cpu0.l2cache.demand_misses::cpu0.data 1307715 # number of demand (read+write) misses 1035system.cpu0.l2cache.demand_misses::total 2077343 # number of demand (read+write) misses 1036system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11861 # number of overall misses 1037system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8276 # number of overall misses 1038system.cpu0.l2cache.overall_misses::cpu0.inst 749491 # number of overall misses 1039system.cpu0.l2cache.overall_misses::cpu0.data 1307715 # number of overall misses 1040system.cpu0.l2cache.overall_misses::total 2077343 # number of overall misses 1041system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 476400500 # number of ReadReq miss cycles 1042system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 367251000 # number of ReadReq miss cycles 1043system.cpu0.l2cache.ReadReq_miss_latency::total 843651500 # number of ReadReq miss cycles 1044system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3484637000 # number of UpgradeReq miss cycles 1045system.cpu0.l2cache.UpgradeReq_miss_latency::total 3484637000 # number of UpgradeReq miss cycles 1046system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2105132000 # number of SCUpgradeReq miss cycles 1047system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2105132000 # number of SCUpgradeReq miss cycles 1048system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5326000 # number of SCUpgradeFailReq miss cycles 1049system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5326000 # number of SCUpgradeFailReq miss cycles 1050system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18710306493 # number of ReadExReq miss cycles 1051system.cpu0.l2cache.ReadExReq_miss_latency::total 18710306493 # number of ReadExReq miss cycles 1052system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29430808500 # number of ReadCleanReq miss cycles 1053system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29430808500 # number of ReadCleanReq miss cycles 1054system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43223836490 # number of ReadSharedReq miss cycles 1055system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43223836490 # number of ReadSharedReq miss cycles 1056system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 408693500 # number of InvalidateReq miss cycles 1057system.cpu0.l2cache.InvalidateReq_miss_latency::total 408693500 # number of InvalidateReq miss cycles 1058system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 476400500 # number of demand (read+write) miss cycles 1059system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 367251000 # number of demand (read+write) miss cycles 1060system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29430808500 # number of demand (read+write) miss cycles 1061system.cpu0.l2cache.demand_miss_latency::cpu0.data 61934142983 # number of demand (read+write) miss cycles 1062system.cpu0.l2cache.demand_miss_latency::total 92208602983 # number of demand (read+write) miss cycles 1063system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 476400500 # number of overall miss cycles 1064system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 367251000 # number of overall miss cycles 1065system.cpu0.l2cache.overall_miss_latency::cpu0.inst 29430808500 # number of overall miss cycles 1066system.cpu0.l2cache.overall_miss_latency::cpu0.data 61934142983 # number of overall miss cycles 1067system.cpu0.l2cache.overall_miss_latency::total 92208602983 # number of overall miss cycles 1068system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 581680 # number of ReadReq accesses(hits+misses) 1069system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 180748 # number of ReadReq accesses(hits+misses) 1070system.cpu0.l2cache.ReadReq_accesses::total 762428 # number of ReadReq accesses(hits+misses) 1071system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3893369 # number of WritebackDirty accesses(hits+misses) 1072system.cpu0.l2cache.WritebackDirty_accesses::total 3893369 # number of WritebackDirty accesses(hits+misses) 1073system.cpu0.l2cache.WritebackClean_accesses::writebacks 12591574 # number of WritebackClean accesses(hits+misses) 1074system.cpu0.l2cache.WritebackClean_accesses::total 12591574 # number of WritebackClean accesses(hits+misses) 1075system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 260784 # number of UpgradeReq accesses(hits+misses) 1076system.cpu0.l2cache.UpgradeReq_accesses::total 260784 # number of UpgradeReq accesses(hits+misses) 1077system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200530 # number of SCUpgradeReq accesses(hits+misses) 1078system.cpu0.l2cache.SCUpgradeReq_accesses::total 200530 # number of SCUpgradeReq accesses(hits+misses) 1079system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1080system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1081system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196044 # number of ReadExReq accesses(hits+misses) 1082system.cpu0.l2cache.ReadExReq_accesses::total 1196044 # number of ReadExReq accesses(hits+misses) 1083system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 10516549 # number of ReadCleanReq accesses(hits+misses) 1084system.cpu0.l2cache.ReadCleanReq_accesses::total 10516549 # number of ReadCleanReq accesses(hits+misses) 1085system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4035220 # number of ReadSharedReq accesses(hits+misses) 1086system.cpu0.l2cache.ReadSharedReq_accesses::total 4035220 # number of ReadSharedReq accesses(hits+misses) 1087system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 845557 # number of InvalidateReq accesses(hits+misses) 1088system.cpu0.l2cache.InvalidateReq_accesses::total 845557 # number of InvalidateReq accesses(hits+misses) 1089system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 581680 # number of demand (read+write) accesses 1090system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 180748 # number of demand (read+write) accesses 1091system.cpu0.l2cache.demand_accesses::cpu0.inst 10516549 # number of demand (read+write) accesses 1092system.cpu0.l2cache.demand_accesses::cpu0.data 5231264 # number of demand (read+write) accesses 1093system.cpu0.l2cache.demand_accesses::total 16510241 # number of demand (read+write) accesses 1094system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 581680 # number of overall (read+write) accesses 1095system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 180748 # number of overall (read+write) accesses 1096system.cpu0.l2cache.overall_accesses::cpu0.inst 10516549 # number of overall (read+write) accesses 1097system.cpu0.l2cache.overall_accesses::cpu0.data 5231264 # number of overall (read+write) accesses 1098system.cpu0.l2cache.overall_accesses::total 16510241 # number of overall (read+write) accesses 1099system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020391 # miss rate for ReadReq accesses 1100system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045788 # miss rate for ReadReq accesses 1101system.cpu0.l2cache.ReadReq_miss_rate::total 0.026412 # miss rate for ReadReq accesses 1102system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1103system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1104system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998585 # miss rate for UpgradeReq accesses 1105system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998585 # miss rate for UpgradeReq accesses 1106system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1107system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1108system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1109system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1110system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.232559 # miss rate for ReadExReq accesses 1111system.cpu0.l2cache.ReadExReq_miss_rate::total 0.232559 # miss rate for ReadExReq accesses 1112system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071268 # miss rate for ReadCleanReq accesses 1113system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071268 # miss rate for ReadCleanReq accesses 1114system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255144 # miss rate for ReadSharedReq accesses 1115system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255144 # miss rate for ReadSharedReq accesses 1116system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728290 # miss rate for InvalidateReq accesses 1117system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728290 # miss rate for InvalidateReq accesses 1118system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020391 # miss rate for demand accesses 1119system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045788 # miss rate for demand accesses 1120system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071268 # miss rate for demand accesses 1121system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.249981 # miss rate for demand accesses 1122system.cpu0.l2cache.demand_miss_rate::total 0.125821 # miss rate for demand accesses 1123system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020391 # miss rate for overall accesses 1124system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045788 # miss rate for overall accesses 1125system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071268 # miss rate for overall accesses 1126system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.249981 # miss rate for overall accesses 1127system.cpu0.l2cache.overall_miss_rate::total 0.125821 # miss rate for overall accesses 1128system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40165.289605 # average ReadReq miss latency 1129system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44375.422910 # average ReadReq miss latency 1130system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41895.590207 # average ReadReq miss latency 1131system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13381.091719 # average UpgradeReq miss latency 1132system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13381.091719 # average UpgradeReq miss latency 1133system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10497.840722 # average SCUpgradeReq miss latency 1134system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10497.840722 # average SCUpgradeReq miss latency 1135system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1065200 # average SCUpgradeFailReq miss latency 1136system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1065200 # average SCUpgradeFailReq miss latency 1137system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67266.723805 # average ReadExReq miss latency 1138system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67266.723805 # average ReadExReq miss latency 1139system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39267.727698 # average ReadCleanReq miss latency 1140system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39267.727698 # average ReadCleanReq miss latency 1141system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41982.661097 # average ReadSharedReq miss latency 1142system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41982.661097 # average ReadSharedReq miss latency 1143system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 663.667099 # average InvalidateReq miss latency 1144system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 663.667099 # average InvalidateReq miss latency 1145system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40165.289605 # average overall miss latency 1146system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44375.422910 # average overall miss latency 1147system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39267.727698 # average overall miss latency 1148system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 47360.581612 # average overall miss latency 1149system.cpu0.l2cache.demand_avg_miss_latency::total 44387.760222 # average overall miss latency 1150system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40165.289605 # average overall miss latency 1151system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44375.422910 # average overall miss latency 1152system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39267.727698 # average overall miss latency 1153system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47360.581612 # average overall miss latency 1154system.cpu0.l2cache.overall_avg_miss_latency::total 44387.760222 # average overall miss latency 1155system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1156system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1157system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1158system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1159system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1160system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1161system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1162system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1163system.cpu0.l2cache.unused_prefetches 49728 # number of HardPF blocks evicted w/o reference 1164system.cpu0.l2cache.writebacks::writebacks 1630983 # number of writebacks 1165system.cpu0.l2cache.writebacks::total 1630983 # number of writebacks 1166system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1167system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 1168system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1169system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9619 # number of ReadExReq MSHR hits 1170system.cpu0.l2cache.ReadExReq_mshr_hits::total 9619 # number of ReadExReq MSHR hits 1171system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits 1172system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 1173system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1673 # number of ReadSharedReq MSHR hits 1174system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1673 # number of ReadSharedReq MSHR hits 1175system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1176system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits 1177system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 1178system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11292 # number of demand (read+write) MSHR hits 1179system.cpu0.l2cache.demand_mshr_hits::total 11302 # number of demand (read+write) MSHR hits 1180system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1181system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits 1182system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 1183system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11292 # number of overall MSHR hits 1184system.cpu0.l2cache.overall_mshr_hits::total 11302 # number of overall MSHR hits 1185system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11860 # number of ReadReq MSHR misses 1186system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8274 # number of ReadReq MSHR misses 1187system.cpu0.l2cache.ReadReq_mshr_misses::total 20134 # number of ReadReq MSHR misses 1188system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 1189system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 1190system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 816392 # number of HardPFReq MSHR misses 1191system.cpu0.l2cache.HardPFReq_mshr_misses::total 816392 # number of HardPFReq MSHR misses 1192system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 260415 # number of UpgradeReq MSHR misses 1193system.cpu0.l2cache.UpgradeReq_mshr_misses::total 260415 # number of UpgradeReq MSHR misses 1194system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200530 # number of SCUpgradeReq MSHR misses 1195system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200530 # number of SCUpgradeReq MSHR misses 1196system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1197system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1198system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 268532 # number of ReadExReq MSHR misses 1199system.cpu0.l2cache.ReadExReq_mshr_misses::total 268532 # number of ReadExReq MSHR misses 1200system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 749484 # number of ReadCleanReq MSHR misses 1201system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 749484 # number of ReadCleanReq MSHR misses 1202system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1027891 # number of ReadSharedReq MSHR misses 1203system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1027891 # number of ReadSharedReq MSHR misses 1204system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 615811 # number of InvalidateReq MSHR misses 1205system.cpu0.l2cache.InvalidateReq_mshr_misses::total 615811 # number of InvalidateReq MSHR misses 1206system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11860 # number of demand (read+write) MSHR misses 1207system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8274 # number of demand (read+write) MSHR misses 1208system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 749484 # number of demand (read+write) MSHR misses 1209system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1296423 # number of demand (read+write) MSHR misses 1210system.cpu0.l2cache.demand_mshr_misses::total 2066041 # number of demand (read+write) MSHR misses 1211system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11860 # number of overall MSHR misses 1212system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8274 # number of overall MSHR misses 1213system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 749484 # number of overall MSHR misses 1214system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1296423 # number of overall MSHR misses 1215system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 816392 # number of overall MSHR misses 1216system.cpu0.l2cache.overall_mshr_misses::total 2882433 # number of overall MSHR misses 1217system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 1218system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable 1219system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83861 # number of ReadReq MSHR uncacheable 1220system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 1221system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable 1222system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 1223system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses 1224system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115009 # number of overall MSHR uncacheable misses 1225system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 405225500 # number of ReadReq MSHR miss cycles 1226system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 317581000 # number of ReadReq MSHR miss cycles 1227system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 722806500 # number of ReadReq MSHR miss cycles 1228system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 46297805758 # number of HardPFReq MSHR miss cycles 1229system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 46297805758 # number of HardPFReq MSHR miss cycles 1230system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7801522496 # number of UpgradeReq MSHR miss cycles 1231system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7801522496 # number of UpgradeReq MSHR miss cycles 1232system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3985601996 # number of SCUpgradeReq MSHR miss cycles 1233system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3985601996 # number of SCUpgradeReq MSHR miss cycles 1234system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4972000 # number of SCUpgradeFailReq MSHR miss cycles 1235system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4972000 # number of SCUpgradeFailReq MSHR miss cycles 1236system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15679279493 # number of ReadExReq MSHR miss cycles 1237system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15679279493 # number of ReadExReq MSHR miss cycles 1238system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 24933652500 # number of ReadCleanReq MSHR miss cycles 1239system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 24933652500 # number of ReadCleanReq MSHR miss cycles 1240system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36914926990 # number of ReadSharedReq MSHR miss cycles 1241system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36914926990 # number of ReadSharedReq MSHR miss cycles 1242system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 43692307000 # number of InvalidateReq MSHR miss cycles 1243system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 43692307000 # number of InvalidateReq MSHR miss cycles 1244system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 405225500 # number of demand (read+write) MSHR miss cycles 1245system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 317581000 # number of demand (read+write) MSHR miss cycles 1246system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 24933652500 # number of demand (read+write) MSHR miss cycles 1247system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 52594206483 # number of demand (read+write) MSHR miss cycles 1248system.cpu0.l2cache.demand_mshr_miss_latency::total 78250665483 # number of demand (read+write) MSHR miss cycles 1249system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 405225500 # number of overall MSHR miss cycles 1250system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 317581000 # number of overall MSHR miss cycles 1251system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 24933652500 # number of overall MSHR miss cycles 1252system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 52594206483 # number of overall MSHR miss cycles 1253system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 46297805758 # number of overall MSHR miss cycles 1254system.cpu0.l2cache.overall_mshr_miss_latency::total 124548471241 # number of overall MSHR miss cycles 1255system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 1256system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788797000 # number of ReadReq MSHR uncacheable cycles 1257system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12784952000 # number of ReadReq MSHR uncacheable cycles 1258system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5603650500 # number of WriteReq MSHR uncacheable cycles 1259system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5603650500 # number of WriteReq MSHR uncacheable cycles 1260system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 1261system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11392447500 # number of overall MSHR uncacheable cycles 1262system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18388602500 # number of overall MSHR uncacheable cycles 1263system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for ReadReq accesses 1264system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for ReadReq accesses 1265system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026408 # mshr miss rate for ReadReq accesses 1266system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1267system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1268system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1269system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1270system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses 1271system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998585 # mshr miss rate for UpgradeReq accesses 1272system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1273system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1274system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1275system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1276system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224517 # mshr miss rate for ReadExReq accesses 1277system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224517 # mshr miss rate for ReadExReq accesses 1278system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for ReadCleanReq accesses 1279system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071267 # mshr miss rate for ReadCleanReq accesses 1280system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254730 # mshr miss rate for ReadSharedReq accesses 1281system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254730 # mshr miss rate for ReadSharedReq accesses 1282system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728290 # mshr miss rate for InvalidateReq accesses 1283system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728290 # mshr miss rate for InvalidateReq accesses 1284system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for demand accesses 1285system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for demand accesses 1286system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for demand accesses 1287system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for demand accesses 1288system.cpu0.l2cache.demand_mshr_miss_rate::total 0.125137 # mshr miss rate for demand accesses 1289system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for overall accesses 1290system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for overall accesses 1291system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for overall accesses 1292system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for overall accesses 1293system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1294system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174585 # mshr miss rate for overall accesses 1295system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average ReadReq mshr miss latency 1296system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average ReadReq mshr miss latency 1297system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364 # average ReadReq mshr miss latency 1298system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average HardPFReq mshr miss latency 1299system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890 # average HardPFReq mshr miss latency 1300system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116 # average UpgradeReq mshr miss latency 1301system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116 # average UpgradeReq mshr miss latency 1302system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328 # average SCUpgradeReq mshr miss latency 1303system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328 # average SCUpgradeReq mshr miss latency 1304system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 994400 # average SCUpgradeFailReq mshr miss latency 1305system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 994400 # average SCUpgradeFailReq mshr miss latency 1306system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967 # average ReadExReq mshr miss latency 1307system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967 # average ReadExReq mshr miss latency 1308system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average ReadCleanReq mshr miss latency 1309system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218 # average ReadCleanReq mshr miss latency 1310system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977 # average ReadSharedReq mshr miss latency 1311system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977 # average ReadSharedReq mshr miss latency 1312system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813 # average InvalidateReq mshr miss latency 1313system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813 # average InvalidateReq mshr miss latency 1314system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency 1315system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency 1316system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency 1317system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency 1318system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491 # average overall mshr miss latency 1319system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency 1320system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency 1321system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency 1322system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency 1323system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency 1324system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency 1325system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 1326system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency 1327system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency 1328system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency 1329system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency 1330system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 1331system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency 1332system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency 1333system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1334system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. 1335system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1336system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1337system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter. 1338system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1339system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1340system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution 1341system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution 1342system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 1343system.cpu0.toL2Bus.trans_dist::WriteReq 31149 # Transaction distribution 1344system.cpu0.toL2Bus.trans_dist::WriteResp 31148 # Transaction distribution 1345system.cpu0.toL2Bus.trans_dist::WritebackDirty 5528357 # Transaction distribution 1346system.cpu0.toL2Bus.trans_dist::WritebackClean 12594701 # Transaction distribution 1347system.cpu0.toL2Bus.trans_dist::CleanEvict 3060195 # Transaction distribution 1348system.cpu0.toL2Bus.trans_dist::HardPFReq 1058289 # Transaction distribution 1349system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 1350system.cpu0.toL2Bus.trans_dist::UpgradeReq 483217 # Transaction distribution 1351system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361321 # Transaction distribution 1352system.cpu0.toL2Bus.trans_dist::UpgradeResp 533499 # Transaction distribution 1353system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution 1354system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 1355system.cpu0.toL2Bus.trans_dist::ReadExReq 1230571 # Transaction distribution 1356system.cpu0.toL2Bus.trans_dist::ReadExResp 1205955 # Transaction distribution 1357system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10516550 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5115631 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::InvalidateReq 898497 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::InvalidateResp 845557 # Transaction distribution 1361system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 31653744 # Packet count per connected master and slave (bytes) 1362system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19358528 # Packet count per connected master and slave (bytes) 1363system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 379556 # Packet count per connected master and slave (bytes) 1364system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1223236 # Packet count per connected master and slave (bytes) 1365system.cpu0.toL2Bus.pkt_count::total 52615064 # Packet count per connected master and slave (bytes) 1366system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1349432640 # Cumulative packet size per connected master and slave (bytes) 1367system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 724409976 # Cumulative packet size per connected master and slave (bytes) 1368system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1445984 # Cumulative packet size per connected master and slave (bytes) 1369system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4653440 # Cumulative packet size per connected master and slave (bytes) 1370system.cpu0.toL2Bus.pkt_size::total 2079942040 # Cumulative packet size per connected master and slave (bytes) 1371system.cpu0.toL2Bus.snoops 7567377 # Total snoops (count) 1372system.cpu0.toL2Bus.snoop_fanout::samples 25314697 # Request fanout histogram 1373system.cpu0.toL2Bus.snoop_fanout::mean 0.102016 # Request fanout histogram 1374system.cpu0.toL2Bus.snoop_fanout::stdev 0.302732 # Request fanout histogram 1375system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1376system.cpu0.toL2Bus.snoop_fanout::0 22732690 89.80% 89.80% # Request fanout histogram 1377system.cpu0.toL2Bus.snoop_fanout::1 2581520 10.20% 100.00% # Request fanout histogram 1378system.cpu0.toL2Bus.snoop_fanout::2 487 0.00% 100.00% # Request fanout histogram 1379system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1380system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1381system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1382system.cpu0.toL2Bus.snoop_fanout::total 25314697 # Request fanout histogram 1383system.cpu0.toL2Bus.reqLayer0.occupancy 33752723480 # Layer occupancy (ticks) 1384system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1385system.cpu0.toL2Bus.snoopLayer0.occupancy 205163062 # Layer occupancy (ticks) 1386system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1387system.cpu0.toL2Bus.respLayer0.occupancy 15856801952 # Layer occupancy (ticks) 1388system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1389system.cpu0.toL2Bus.respLayer1.occupancy 8551593856 # Layer occupancy (ticks) 1390system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1391system.cpu0.toL2Bus.respLayer2.occupancy 198848419 # Layer occupancy (ticks) 1392system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1393system.cpu0.toL2Bus.respLayer3.occupancy 641675758 # Layer occupancy (ticks) 1394system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1395system.cpu1.branchPred.lookups 127453033 # Number of BP lookups 1396system.cpu1.branchPred.condPredicted 91217282 # Number of conditional branches predicted 1397system.cpu1.branchPred.condIncorrect 5663830 # Number of conditional branches incorrect 1398system.cpu1.branchPred.BTBLookups 96224557 # Number of BTB lookups 1399system.cpu1.branchPred.BTBHits 67852361 # Number of BTB hits 1400system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1401system.cpu1.branchPred.BTBHitPct 70.514600 # BTB Hit Percentage 1402system.cpu1.branchPred.usedRAS 14431851 # Number of times the RAS was used to get a target. 1403system.cpu1.branchPred.RASInCorrect 916644 # Number of incorrect RAS predictions. 1404system.cpu1.branchPred.indirectLookups 3338859 # Number of indirect predictor lookups. 1405system.cpu1.branchPred.indirectHits 2197659 # Number of indirect target hits. 1406system.cpu1.branchPred.indirectMisses 1141200 # Number of indirect misses. 1407system.cpu1.branchPredindirectMispredicted 412569 # Number of mispredicted indirect branches. 1408system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1409system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1410system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1411system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1412system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1413system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1414system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1415system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1416system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1417system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1418system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1419system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1420system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1421system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1422system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1423system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1424system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1425system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1426system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1427system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1428system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1429system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1430system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1431system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1432system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1433system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1434system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1435system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1436system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1437system.cpu1.dtb.walker.walks 261031 # Table walker walks requested 1438system.cpu1.dtb.walker.walksLong 261031 # Table walker walks initiated with long descriptors 1439system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9619 # Level at which table walker walks with long descriptors terminate 1440system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80662 # Level at which table walker walks with long descriptors terminate 1441system.cpu1.dtb.walker.walkWaitTime::samples 261031 # Table walker wait (enqueue to first request) latency 1442system.cpu1.dtb.walker.walkWaitTime::0 261031 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1443system.cpu1.dtb.walker.walkWaitTime::total 261031 # Table walker wait (enqueue to first request) latency 1444system.cpu1.dtb.walker.walkCompletionTime::samples 90281 # Table walker service (enqueue to completion) latency 1445system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371 # Table walker service (enqueue to completion) latency 1446system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865 # Table walker service (enqueue to completion) latency 1447system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155 # Table walker service (enqueue to completion) latency 1448system.cpu1.dtb.walker.walkCompletionTime::0-65535 88920 98.49% 98.49% # Table walker service (enqueue to completion) latency 1449system.cpu1.dtb.walker.walkCompletionTime::65536-131071 187 0.21% 98.70% # Table walker service (enqueue to completion) latency 1450system.cpu1.dtb.walker.walkCompletionTime::131072-196607 992 1.10% 99.80% # Table walker service (enqueue to completion) latency 1451system.cpu1.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.85% # Table walker service (enqueue to completion) latency 1452system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.90% # Table walker service (enqueue to completion) latency 1453system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.03% 99.92% # Table walker service (enqueue to completion) latency 1454system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.04% 99.96% # Table walker service (enqueue to completion) latency 1455system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency 1456system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 1457system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1458system.cpu1.dtb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1459system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1460system.cpu1.dtb.walker.walkCompletionTime::total 90281 # Table walker service (enqueue to completion) latency 1461system.cpu1.dtb.walker.walksPending::samples 1786242352 # Table walker pending requests distribution 1462system.cpu1.dtb.walker.walksPending::0 1786242352 100.00% 100.00% # Table walker pending requests distribution 1463system.cpu1.dtb.walker.walksPending::total 1786242352 # Table walker pending requests distribution 1464system.cpu1.dtb.walker.walkPageSizes::4K 80662 89.35% 89.35% # Table walker page sizes translated 1465system.cpu1.dtb.walker.walkPageSizes::2M 9619 10.65% 100.00% # Table walker page sizes translated 1466system.cpu1.dtb.walker.walkPageSizes::total 90281 # Table walker page sizes translated 1467system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261031 # Table walker requests started/completed, data/inst 1468system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1469system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261031 # Table walker requests started/completed, data/inst 1470system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90281 # Table walker requests started/completed, data/inst 1471system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1472system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90281 # Table walker requests started/completed, data/inst 1473system.cpu1.dtb.walker.walkRequestOrigin::total 351312 # Table walker requests started/completed, data/inst 1474system.cpu1.dtb.inst_hits 0 # ITB inst hits 1475system.cpu1.dtb.inst_misses 0 # ITB inst misses 1476system.cpu1.dtb.read_hits 80497438 # DTB read hits 1477system.cpu1.dtb.read_misses 213464 # DTB read misses 1478system.cpu1.dtb.write_hits 70911031 # DTB write hits 1479system.cpu1.dtb.write_misses 47567 # DTB write misses 1480system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1481system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1482system.cpu1.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 1483system.cpu1.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 1484system.cpu1.dtb.flush_entries 37751 # Number of entries that have been flushed from TLB 1485system.cpu1.dtb.align_faults 1110 # Number of TLB faults due to alignment restrictions 1486system.cpu1.dtb.prefetch_faults 7072 # Number of TLB faults due to prefetch 1487system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1488system.cpu1.dtb.perms_faults 11967 # Number of TLB faults due to permissions restrictions 1489system.cpu1.dtb.read_accesses 80710902 # DTB read accesses 1490system.cpu1.dtb.write_accesses 70958598 # DTB write accesses 1491system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1492system.cpu1.dtb.hits 151408469 # DTB hits 1493system.cpu1.dtb.misses 261031 # DTB misses 1494system.cpu1.dtb.accesses 151669500 # DTB accesses 1495system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1496system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1497system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1498system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1499system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1500system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1501system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1502system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1503system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1504system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1505system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1506system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1507system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1508system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1509system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1510system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1511system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1512system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1513system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1514system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1515system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1516system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1517system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1518system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1519system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1520system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1521system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1522system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1523system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1524system.cpu1.itb.walker.walks 64962 # Table walker walks requested 1525system.cpu1.itb.walker.walksLong 64962 # Table walker walks initiated with long descriptors 1526system.cpu1.itb.walker.walksLongTerminationLevel::Level2 549 # Level at which table walker walks with long descriptors terminate 1527system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55482 # Level at which table walker walks with long descriptors terminate 1528system.cpu1.itb.walker.walkWaitTime::samples 64962 # Table walker wait (enqueue to first request) latency 1529system.cpu1.itb.walker.walkWaitTime::0 64962 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1530system.cpu1.itb.walker.walkWaitTime::total 64962 # Table walker wait (enqueue to first request) latency 1531system.cpu1.itb.walker.walkCompletionTime::samples 56031 # Table walker service (enqueue to completion) latency 1532system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577 # Table walker service (enqueue to completion) latency 1533system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661 # Table walker service (enqueue to completion) latency 1534system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124 # Table walker service (enqueue to completion) latency 1535system.cpu1.itb.walker.walkCompletionTime::0-65535 54737 97.69% 97.69% # Table walker service (enqueue to completion) latency 1536system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.71% # Table walker service (enqueue to completion) latency 1537system.cpu1.itb.walker.walkCompletionTime::131072-196607 1140 2.03% 99.74% # Table walker service (enqueue to completion) latency 1538system.cpu1.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.82% # Table walker service (enqueue to completion) latency 1539system.cpu1.itb.walker.walkCompletionTime::262144-327679 63 0.11% 99.93% # Table walker service (enqueue to completion) latency 1540system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency 1541system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency 1542system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1543system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1544system.cpu1.itb.walker.walkCompletionTime::total 56031 # Table walker service (enqueue to completion) latency 1545system.cpu1.itb.walker.walksPending::samples 1785244852 # Table walker pending requests distribution 1546system.cpu1.itb.walker.walksPending::0 1785244852 100.00% 100.00% # Table walker pending requests distribution 1547system.cpu1.itb.walker.walksPending::total 1785244852 # Table walker pending requests distribution 1548system.cpu1.itb.walker.walkPageSizes::4K 55482 99.02% 99.02% # Table walker page sizes translated 1549system.cpu1.itb.walker.walkPageSizes::2M 549 0.98% 100.00% # Table walker page sizes translated 1550system.cpu1.itb.walker.walkPageSizes::total 56031 # Table walker page sizes translated 1551system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1552system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64962 # Table walker requests started/completed, data/inst 1553system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64962 # Table walker requests started/completed, data/inst 1554system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1555system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56031 # Table walker requests started/completed, data/inst 1556system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56031 # Table walker requests started/completed, data/inst 1557system.cpu1.itb.walker.walkRequestOrigin::total 120993 # Table walker requests started/completed, data/inst 1558system.cpu1.itb.inst_hits 225980528 # ITB inst hits 1559system.cpu1.itb.inst_misses 64962 # ITB inst misses 1560system.cpu1.itb.read_hits 0 # DTB read hits 1561system.cpu1.itb.read_misses 0 # DTB read misses 1562system.cpu1.itb.write_hits 0 # DTB write hits 1563system.cpu1.itb.write_misses 0 # DTB write misses 1564system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1565system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1566system.cpu1.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 1567system.cpu1.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 1568system.cpu1.itb.flush_entries 26783 # Number of entries that have been flushed from TLB 1569system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1570system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1571system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1572system.cpu1.itb.perms_faults 166792 # Number of TLB faults due to permissions restrictions 1573system.cpu1.itb.read_accesses 0 # DTB read accesses 1574system.cpu1.itb.write_accesses 0 # DTB write accesses 1575system.cpu1.itb.inst_accesses 226045490 # ITB inst accesses 1576system.cpu1.itb.hits 225980528 # DTB hits 1577system.cpu1.itb.misses 64962 # DTB misses 1578system.cpu1.itb.accesses 226045490 # DTB accesses 1579system.cpu1.numCycles 884296043 # number of cpu cycles simulated 1580system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1581system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1582system.cpu1.committedInsts 410764166 # Number of instructions committed 1583system.cpu1.committedOps 484072804 # Number of ops (including micro ops) committed 1584system.cpu1.discardedOps 46607969 # Number of ops (including micro ops) which were discarded before commit 1585system.cpu1.numFetchSuspends 5245 # Number of times Execute suspended instruction fetching 1586system.cpu1.quiesceCycles 94188329171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1587system.cpu1.cpi 2.152807 # CPI: cycles per instruction 1588system.cpu1.ipc 0.464510 # IPC: instructions per cycle 1589system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1590system.cpu1.op_class_0::IntAlu 334821764 69.17% 69.17% # Class of committed instruction 1591system.cpu1.op_class_0::IntMult 956339 0.20% 69.37% # Class of committed instruction 1592system.cpu1.op_class_0::IntDiv 55233 0.01% 69.38% # Class of committed instruction 1593system.cpu1.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction 1594system.cpu1.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction 1595system.cpu1.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction 1596system.cpu1.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction 1597system.cpu1.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction 1598system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction 1599system.cpu1.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction 1600system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction 1601system.cpu1.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction 1602system.cpu1.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction 1603system.cpu1.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction 1604system.cpu1.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction 1605system.cpu1.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction 1606system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction 1607system.cpu1.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction 1608system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction 1609system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction 1610system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction 1611system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction 1612system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction 1613system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction 1614system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction 1615system.cpu1.op_class_0::SimdFloatMisc 37353 0.01% 69.38% # Class of committed instruction 1616system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction 1617system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction 1618system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction 1619system.cpu1.op_class_0::MemRead 77588616 16.03% 85.41% # Class of committed instruction 1620system.cpu1.op_class_0::MemWrite 70613457 14.59% 100.00% # Class of committed instruction 1621system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1622system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1623system.cpu1.op_class_0::total 484072804 # Class of committed instruction 1624system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1625system.cpu1.kern.inst.quiesce 5362 # number of quiesce instructions executed 1626system.cpu1.tickCycles 676945147 # Number of cycles that the object actually ticked 1627system.cpu1.idleCycles 207350896 # Total number of cycles that the object has spent stopped 1628system.cpu1.dcache.tags.replacements 5011869 # number of replacements 1629system.cpu1.dcache.tags.tagsinuse 436.764256 # Cycle average of tags in use 1630system.cpu1.dcache.tags.total_refs 143763031 # Total number of references to valid blocks. 1631system.cpu1.dcache.tags.sampled_refs 5012381 # Sample count of references to valid blocks. 1632system.cpu1.dcache.tags.avg_refs 28.681585 # Average number of references to valid blocks. 1633system.cpu1.dcache.tags.warmup_cycle 8498279834500 # Cycle when the warmup percentage was hit. 1634system.cpu1.dcache.tags.occ_blocks::cpu1.data 436.764256 # Average occupied blocks per requestor 1635system.cpu1.dcache.tags.occ_percent::cpu1.data 0.853055 # Average percentage of cache occupancy 1636system.cpu1.dcache.tags.occ_percent::total 0.853055 # Average percentage of cache occupancy 1637system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1638system.cpu1.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 1639system.cpu1.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id 1640system.cpu1.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 1641system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1642system.cpu1.dcache.tags.tag_accesses 305397096 # Number of tag accesses 1643system.cpu1.dcache.tags.data_accesses 305397096 # Number of data accesses 1644system.cpu1.dcache.ReadReq_hits::cpu1.data 73662807 # number of ReadReq hits 1645system.cpu1.dcache.ReadReq_hits::total 73662807 # number of ReadReq hits 1646system.cpu1.dcache.WriteReq_hits::cpu1.data 66040616 # number of WriteReq hits 1647system.cpu1.dcache.WriteReq_hits::total 66040616 # number of WriteReq hits 1648system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits 1649system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits 1650system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits 1651system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits 1652system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits 1653system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits 1654system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits 1655system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits 1656system.cpu1.dcache.demand_hits::cpu1.data 139703423 # number of demand (read+write) hits 1657system.cpu1.dcache.demand_hits::total 139703423 # number of demand (read+write) hits 1658system.cpu1.dcache.overall_hits::cpu1.data 139904287 # number of overall hits 1659system.cpu1.dcache.overall_hits::total 139904287 # number of overall hits 1660system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses 1661system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses 1662system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses 1663system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses 1664system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses 1665system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses 1666system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses 1667system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses 1668system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses 1669system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses 1670system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses 1671system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses 1672system.cpu1.dcache.demand_misses::cpu1.data 5471070 # number of demand (read+write) misses 1673system.cpu1.dcache.demand_misses::total 5471070 # number of demand (read+write) misses 1674system.cpu1.dcache.overall_misses::cpu1.data 6120062 # number of overall misses 1675system.cpu1.dcache.overall_misses::total 6120062 # number of overall misses 1676system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles 1677system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles 1678system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles 1679system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles 1680system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles 1681system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles 1682system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles 1683system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles 1684system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 # number of StoreCondReq miss cycles 1685system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles 1686system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles 1687system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles 1688system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000 # number of demand (read+write) miss cycles 1689system.cpu1.dcache.demand_miss_latency::total 103432662000 # number of demand (read+write) miss cycles 1690system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000 # number of overall miss cycles 1691system.cpu1.dcache.overall_miss_latency::total 103432662000 # number of overall miss cycles 1692system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) 1693system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) 1694system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) 1695system.cpu1.dcache.WriteReq_accesses::total 68318489 # number of WriteReq accesses(hits+misses) 1696system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 849856 # number of SoftPFReq accesses(hits+misses) 1697system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses) 1698system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses) 1699system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses) 1700system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 # number of LoadLockedReq accesses(hits+misses) 1701system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) 1702system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) 1703system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) 1704system.cpu1.dcache.demand_accesses::cpu1.data 145174493 # number of demand (read+write) accesses 1705system.cpu1.dcache.demand_accesses::total 145174493 # number of demand (read+write) accesses 1706system.cpu1.dcache.overall_accesses::cpu1.data 146024349 # number of overall (read+write) accesses 1707system.cpu1.dcache.overall_accesses::total 146024349 # number of overall (read+write) accesses 1708system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses 1709system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses 1710system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses 1711system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses 1712system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses 1713system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses 1714system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses 1715system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses 1716system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses 1717system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses 1718system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses 1719system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses 1720system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses 1721system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses 1722system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses 1723system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses 1724system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency 1725system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency 1726system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency 1727system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency 1728system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency 1729system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency 1730system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency 1731system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency 1732system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency 1733system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency 1734system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1735system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1736system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency 1737system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency 1738system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency 1739system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency 1740system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1741system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1742system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1743system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1744system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1745system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1746system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1747system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1748system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks 1749system.cpu1.dcache.writebacks::total 5011891 # number of writebacks 1750system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits 1751system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits 1752system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 943211 # number of WriteReq MSHR hits 1753system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits 1754system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 1755system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 1756system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 # number of LoadLockedReq MSHR hits 1757system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits 1758system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits 1759system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits 1760system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310532 # number of demand (read+write) MSHR hits 1761system.cpu1.dcache.demand_mshr_hits::total 1310532 # number of demand (read+write) MSHR hits 1762system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310532 # number of overall MSHR hits 1763system.cpu1.dcache.overall_mshr_hits::total 1310532 # number of overall MSHR hits 1764system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses 1765system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses 1766system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses 1767system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses 1768system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648629 # number of SoftPFReq MSHR misses 1769system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses 1770system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses 1771system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses 1772system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses 1773system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses 1774system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses 1775system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses 1776system.cpu1.dcache.demand_mshr_misses::cpu1.data 4160538 # number of demand (read+write) MSHR misses 1777system.cpu1.dcache.demand_mshr_misses::total 4160538 # number of demand (read+write) MSHR misses 1778system.cpu1.dcache.overall_mshr_misses::cpu1.data 4809167 # number of overall MSHR misses 1779system.cpu1.dcache.overall_mshr_misses::total 4809167 # number of overall MSHR misses 1780system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable 1781system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable 1782system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 1783system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable 1784system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses 1785system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses 1786system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41329046000 # number of ReadReq MSHR miss cycles 1787system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles 1788system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30034339000 # number of WriteReq MSHR miss cycles 1789system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30034339000 # number of WriteReq MSHR miss cycles 1790system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15914789000 # number of SoftPFReq MSHR miss cycles 1791system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15914789000 # number of SoftPFReq MSHR miss cycles 1792system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14484285500 # number of WriteLineReq MSHR miss cycles 1793system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14484285500 # number of WriteLineReq MSHR miss cycles 1794system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1714801500 # number of LoadLockedReq MSHR miss cycles 1795system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles 1796system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 # number of StoreCondReq MSHR miss cycles 1797system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles 1798system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles 1799system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles 1800system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71363385000 # number of demand (read+write) MSHR miss cycles 1801system.cpu1.dcache.demand_mshr_miss_latency::total 71363385000 # number of demand (read+write) MSHR miss cycles 1802system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87278174000 # number of overall MSHR miss cycles 1803system.cpu1.dcache.overall_mshr_miss_latency::total 87278174000 # number of overall MSHR miss cycles 1804system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles 1805system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles 1806system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1094820000 # number of WriteReq MSHR uncacheable cycles 1807system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1094820000 # number of WriteReq MSHR uncacheable cycles 1808system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2014553500 # number of overall MSHR uncacheable cycles 1809system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2014553500 # number of overall MSHR uncacheable cycles 1810system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses 1811system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses 1812system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses 1813system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses 1814system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses 1815system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses 1816system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses 1817system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses 1818system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses 1819system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses 1820system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses 1821system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses 1822system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028659 # mshr miss rate for demand accesses 1823system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses 1824system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses 1825system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses 1826system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency 1827system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency 1828system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency 1829system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency 1830system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency 1831system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency 1832system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency 1833system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency 1834system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency 1835system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency 1836system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency 1837system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency 1838system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1839system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1840system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583 # average overall mshr miss latency 1841system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583 # average overall mshr miss latency 1842system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457 # average overall mshr miss latency 1843system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457 # average overall mshr miss latency 1844system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency 1845system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency 1846system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894 # average WriteReq mshr uncacheable latency 1847system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894 # average WriteReq mshr uncacheable latency 1848system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557 # average overall mshr uncacheable latency 1849system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557 # average overall mshr uncacheable latency 1850system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1851system.cpu1.icache.tags.replacements 8449872 # number of replacements 1852system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use 1853system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. 1854system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks. 1855system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks. 1856system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit. 1857system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.781387 # Average occupied blocks per requestor 1858system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989807 # Average percentage of cache occupancy 1859system.cpu1.icache.tags.occ_percent::total 0.989807 # Average percentage of cache occupancy 1860system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1861system.cpu1.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 1862system.cpu1.icache.tags.age_task_id_blocks_1024::1 365 # Occupied blocks per task id 1863system.cpu1.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 1864system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1865system.cpu1.icache.tags.tag_accesses 460065662 # Number of tag accesses 1866system.cpu1.icache.tags.data_accesses 460065662 # Number of data accesses 1867system.cpu1.icache.ReadReq_hits::cpu1.inst 217357255 # number of ReadReq hits 1868system.cpu1.icache.ReadReq_hits::total 217357255 # number of ReadReq hits 1869system.cpu1.icache.demand_hits::cpu1.inst 217357255 # number of demand (read+write) hits 1870system.cpu1.icache.demand_hits::total 217357255 # number of demand (read+write) hits 1871system.cpu1.icache.overall_hits::cpu1.inst 217357255 # number of overall hits 1872system.cpu1.icache.overall_hits::total 217357255 # number of overall hits 1873system.cpu1.icache.ReadReq_misses::cpu1.inst 8450384 # number of ReadReq misses 1874system.cpu1.icache.ReadReq_misses::total 8450384 # number of ReadReq misses 1875system.cpu1.icache.demand_misses::cpu1.inst 8450384 # number of demand (read+write) misses 1876system.cpu1.icache.demand_misses::total 8450384 # number of demand (read+write) misses 1877system.cpu1.icache.overall_misses::cpu1.inst 8450384 # number of overall misses 1878system.cpu1.icache.overall_misses::total 8450384 # number of overall misses 1879system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88216596500 # number of ReadReq miss cycles 1880system.cpu1.icache.ReadReq_miss_latency::total 88216596500 # number of ReadReq miss cycles 1881system.cpu1.icache.demand_miss_latency::cpu1.inst 88216596500 # number of demand (read+write) miss cycles 1882system.cpu1.icache.demand_miss_latency::total 88216596500 # number of demand (read+write) miss cycles 1883system.cpu1.icache.overall_miss_latency::cpu1.inst 88216596500 # number of overall miss cycles 1884system.cpu1.icache.overall_miss_latency::total 88216596500 # number of overall miss cycles 1885system.cpu1.icache.ReadReq_accesses::cpu1.inst 225807639 # number of ReadReq accesses(hits+misses) 1886system.cpu1.icache.ReadReq_accesses::total 225807639 # number of ReadReq accesses(hits+misses) 1887system.cpu1.icache.demand_accesses::cpu1.inst 225807639 # number of demand (read+write) accesses 1888system.cpu1.icache.demand_accesses::total 225807639 # number of demand (read+write) accesses 1889system.cpu1.icache.overall_accesses::cpu1.inst 225807639 # number of overall (read+write) accesses 1890system.cpu1.icache.overall_accesses::total 225807639 # number of overall (read+write) accesses 1891system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037423 # miss rate for ReadReq accesses 1892system.cpu1.icache.ReadReq_miss_rate::total 0.037423 # miss rate for ReadReq accesses 1893system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037423 # miss rate for demand accesses 1894system.cpu1.icache.demand_miss_rate::total 0.037423 # miss rate for demand accesses 1895system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037423 # miss rate for overall accesses 1896system.cpu1.icache.overall_miss_rate::total 0.037423 # miss rate for overall accesses 1897system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10439.359501 # average ReadReq miss latency 1898system.cpu1.icache.ReadReq_avg_miss_latency::total 10439.359501 # average ReadReq miss latency 1899system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency 1900system.cpu1.icache.demand_avg_miss_latency::total 10439.359501 # average overall miss latency 1901system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency 1902system.cpu1.icache.overall_avg_miss_latency::total 10439.359501 # average overall miss latency 1903system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1904system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1905system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1906system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1907system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1908system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1909system.cpu1.icache.fast_writes 0 # number of fast writes performed 1910system.cpu1.icache.cache_copies 0 # number of cache copies performed 1911system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks 1912system.cpu1.icache.writebacks::total 8449872 # number of writebacks 1913system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses 1914system.cpu1.icache.ReadReq_mshr_misses::total 8450384 # number of ReadReq MSHR misses 1915system.cpu1.icache.demand_mshr_misses::cpu1.inst 8450384 # number of demand (read+write) MSHR misses 1916system.cpu1.icache.demand_mshr_misses::total 8450384 # number of demand (read+write) MSHR misses 1917system.cpu1.icache.overall_mshr_misses::cpu1.inst 8450384 # number of overall MSHR misses 1918system.cpu1.icache.overall_mshr_misses::total 8450384 # number of overall MSHR misses 1919system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 1920system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 1921system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 1922system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 1923system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83991404500 # number of ReadReq MSHR miss cycles 1924system.cpu1.icache.ReadReq_mshr_miss_latency::total 83991404500 # number of ReadReq MSHR miss cycles 1925system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83991404500 # number of demand (read+write) MSHR miss cycles 1926system.cpu1.icache.demand_mshr_miss_latency::total 83991404500 # number of demand (read+write) MSHR miss cycles 1927system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83991404500 # number of overall MSHR miss cycles 1928system.cpu1.icache.overall_mshr_miss_latency::total 83991404500 # number of overall MSHR miss cycles 1929system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13018000 # number of ReadReq MSHR uncacheable cycles 1930system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13018000 # number of ReadReq MSHR uncacheable cycles 1931system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13018000 # number of overall MSHR uncacheable cycles 1932system.cpu1.icache.overall_mshr_uncacheable_latency::total 13018000 # number of overall MSHR uncacheable cycles 1933system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for ReadReq accesses 1934system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037423 # mshr miss rate for ReadReq accesses 1935system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for demand accesses 1936system.cpu1.icache.demand_mshr_miss_rate::total 0.037423 # mshr miss rate for demand accesses 1937system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for overall accesses 1938system.cpu1.icache.overall_mshr_miss_rate::total 0.037423 # mshr miss rate for overall accesses 1939system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average ReadReq mshr miss latency 1940system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9939.359501 # average ReadReq mshr miss latency 1941system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1942system.cpu1.icache.demand_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1943system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1944system.cpu1.icache.overall_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1945system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average ReadReq mshr uncacheable latency 1946system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624 # average ReadReq mshr uncacheable latency 1947system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average overall mshr uncacheable latency 1948system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency 1949system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1950system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued 1951system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified 1952system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue 1953system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1954system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1955system.cpu1.l2cache.prefetcher.pfSpanPage 851890 # number of prefetches not generated due to page crossing 1956system.cpu1.l2cache.tags.replacements 2314380 # number of replacements 1957system.cpu1.l2cache.tags.tagsinuse 13359.571881 # Cycle average of tags in use 1958system.cpu1.l2cache.tags.total_refs 21237271 # Total number of references to valid blocks. 1959system.cpu1.l2cache.tags.sampled_refs 2330274 # Sample count of references to valid blocks. 1960system.cpu1.l2cache.tags.avg_refs 9.113637 # Average number of references to valid blocks. 1961system.cpu1.l2cache.tags.warmup_cycle 10056444277000 # Cycle when the warmup percentage was hit. 1962system.cpu1.l2cache.tags.occ_blocks::writebacks 12441.859609 # Average occupied blocks per requestor 1963system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.856295 # Average occupied blocks per requestor 1964system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.323629 # Average occupied blocks per requestor 1965system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 805.532348 # Average occupied blocks per requestor 1966system.cpu1.l2cache.tags.occ_percent::writebacks 0.759391 # Average percentage of cache occupancy 1967system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003226 # Average percentage of cache occupancy 1968system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003621 # Average percentage of cache occupancy 1969system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.049166 # Average percentage of cache occupancy 1970system.cpu1.l2cache.tags.occ_percent::total 0.815404 # Average percentage of cache occupancy 1971system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id 1972system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id 1973system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14801 # Occupied blocks per task id 1974system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 1975system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 1976system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id 1977system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 596 # Occupied blocks per task id 1978system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id 1979system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1980system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id 1981system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id 1982system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1983system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1984system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 643 # Occupied blocks per task id 1985system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id 1986system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8033 # Occupied blocks per task id 1987system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 613 # Occupied blocks per task id 1988system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id 1989system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id 1990system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903381 # Percentage of cache occupancy per task id 1991system.cpu1.l2cache.tags.tag_accesses 455510636 # Number of tag accesses 1992system.cpu1.l2cache.tags.data_accesses 455510636 # Number of data accesses 1993system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 505028 # number of ReadReq hits 1994system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 167261 # number of ReadReq hits 1995system.cpu1.l2cache.ReadReq_hits::total 672289 # number of ReadReq hits 1996system.cpu1.l2cache.WritebackDirty_hits::writebacks 3161302 # number of WritebackDirty hits 1997system.cpu1.l2cache.WritebackDirty_hits::total 3161302 # number of WritebackDirty hits 1998system.cpu1.l2cache.WritebackClean_hits::writebacks 10298649 # number of WritebackClean hits 1999system.cpu1.l2cache.WritebackClean_hits::total 10298649 # number of WritebackClean hits 2000system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 586 # number of UpgradeReq hits 2001system.cpu1.l2cache.UpgradeReq_hits::total 586 # number of UpgradeReq hits 2002system.cpu1.l2cache.ReadExReq_hits::cpu1.data 836670 # number of ReadExReq hits 2003system.cpu1.l2cache.ReadExReq_hits::total 836670 # number of ReadExReq hits 2004system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 7769081 # number of ReadCleanReq hits 2005system.cpu1.l2cache.ReadCleanReq_hits::total 7769081 # number of ReadCleanReq hits 2006system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2629380 # number of ReadSharedReq hits 2007system.cpu1.l2cache.ReadSharedReq_hits::total 2629380 # number of ReadSharedReq hits 2008system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161838 # number of InvalidateReq hits 2009system.cpu1.l2cache.InvalidateReq_hits::total 161838 # number of InvalidateReq hits 2010system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 505028 # number of demand (read+write) hits 2011system.cpu1.l2cache.demand_hits::cpu1.itb.walker 167261 # number of demand (read+write) hits 2012system.cpu1.l2cache.demand_hits::cpu1.inst 7769081 # number of demand (read+write) hits 2013system.cpu1.l2cache.demand_hits::cpu1.data 3466050 # number of demand (read+write) hits 2014system.cpu1.l2cache.demand_hits::total 11907420 # number of demand (read+write) hits 2015system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 505028 # number of overall hits 2016system.cpu1.l2cache.overall_hits::cpu1.itb.walker 167261 # number of overall hits 2017system.cpu1.l2cache.overall_hits::cpu1.inst 7769081 # number of overall hits 2018system.cpu1.l2cache.overall_hits::cpu1.data 3466050 # number of overall hits 2019system.cpu1.l2cache.overall_hits::total 11907420 # number of overall hits 2020system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12572 # number of ReadReq misses 2021system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9247 # number of ReadReq misses 2022system.cpu1.l2cache.ReadReq_misses::total 21819 # number of ReadReq misses 2023system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 231248 # number of UpgradeReq misses 2024system.cpu1.l2cache.UpgradeReq_misses::total 231248 # number of UpgradeReq misses 2025system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 199403 # number of SCUpgradeReq misses 2026system.cpu1.l2cache.SCUpgradeReq_misses::total 199403 # number of SCUpgradeReq misses 2027system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 2028system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 2029system.cpu1.l2cache.ReadExReq_misses::cpu1.data 268541 # number of ReadExReq misses 2030system.cpu1.l2cache.ReadExReq_misses::total 268541 # number of ReadExReq misses 2031system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 681303 # number of ReadCleanReq misses 2032system.cpu1.l2cache.ReadCleanReq_misses::total 681303 # number of ReadCleanReq misses 2033system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 964682 # number of ReadSharedReq misses 2034system.cpu1.l2cache.ReadSharedReq_misses::total 964682 # number of ReadSharedReq misses 2035system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 246204 # number of InvalidateReq misses 2036system.cpu1.l2cache.InvalidateReq_misses::total 246204 # number of InvalidateReq misses 2037system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12572 # number of demand (read+write) misses 2038system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9247 # number of demand (read+write) misses 2039system.cpu1.l2cache.demand_misses::cpu1.inst 681303 # number of demand (read+write) misses 2040system.cpu1.l2cache.demand_misses::cpu1.data 1233223 # number of demand (read+write) misses 2041system.cpu1.l2cache.demand_misses::total 1936345 # number of demand (read+write) misses 2042system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12572 # number of overall misses 2043system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9247 # number of overall misses 2044system.cpu1.l2cache.overall_misses::cpu1.inst 681303 # number of overall misses 2045system.cpu1.l2cache.overall_misses::cpu1.data 1233223 # number of overall misses 2046system.cpu1.l2cache.overall_misses::total 1936345 # number of overall misses 2047system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 598416500 # number of ReadReq miss cycles 2048system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 470191500 # number of ReadReq miss cycles 2049system.cpu1.l2cache.ReadReq_miss_latency::total 1068608000 # number of ReadReq miss cycles 2050system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3369487000 # number of UpgradeReq miss cycles 2051system.cpu1.l2cache.UpgradeReq_miss_latency::total 3369487000 # number of UpgradeReq miss cycles 2052system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1909793500 # number of SCUpgradeReq miss cycles 2053system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1909793500 # number of SCUpgradeReq miss cycles 2054system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4827998 # number of SCUpgradeFailReq miss cycles 2055system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4827998 # number of SCUpgradeFailReq miss cycles 2056system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14090220498 # number of ReadExReq miss cycles 2057system.cpu1.l2cache.ReadExReq_miss_latency::total 14090220498 # number of ReadExReq miss cycles 2058system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24409955000 # number of ReadCleanReq miss cycles 2059system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24409955000 # number of ReadCleanReq miss cycles 2060system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36192984491 # number of ReadSharedReq miss cycles 2061system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36192984491 # number of ReadSharedReq miss cycles 2062system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 484898500 # number of InvalidateReq miss cycles 2063system.cpu1.l2cache.InvalidateReq_miss_latency::total 484898500 # number of InvalidateReq miss cycles 2064system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 598416500 # number of demand (read+write) miss cycles 2065system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 470191500 # number of demand (read+write) miss cycles 2066system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24409955000 # number of demand (read+write) miss cycles 2067system.cpu1.l2cache.demand_miss_latency::cpu1.data 50283204989 # number of demand (read+write) miss cycles 2068system.cpu1.l2cache.demand_miss_latency::total 75761767989 # number of demand (read+write) miss cycles 2069system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 598416500 # number of overall miss cycles 2070system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 470191500 # number of overall miss cycles 2071system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24409955000 # number of overall miss cycles 2072system.cpu1.l2cache.overall_miss_latency::cpu1.data 50283204989 # number of overall miss cycles 2073system.cpu1.l2cache.overall_miss_latency::total 75761767989 # number of overall miss cycles 2074system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 517600 # number of ReadReq accesses(hits+misses) 2075system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176508 # number of ReadReq accesses(hits+misses) 2076system.cpu1.l2cache.ReadReq_accesses::total 694108 # number of ReadReq accesses(hits+misses) 2077system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3161302 # number of WritebackDirty accesses(hits+misses) 2078system.cpu1.l2cache.WritebackDirty_accesses::total 3161302 # number of WritebackDirty accesses(hits+misses) 2079system.cpu1.l2cache.WritebackClean_accesses::writebacks 10298649 # number of WritebackClean accesses(hits+misses) 2080system.cpu1.l2cache.WritebackClean_accesses::total 10298649 # number of WritebackClean accesses(hits+misses) 2081system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 231834 # number of UpgradeReq accesses(hits+misses) 2082system.cpu1.l2cache.UpgradeReq_accesses::total 231834 # number of UpgradeReq accesses(hits+misses) 2083system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199403 # number of SCUpgradeReq accesses(hits+misses) 2084system.cpu1.l2cache.SCUpgradeReq_accesses::total 199403 # number of SCUpgradeReq accesses(hits+misses) 2085system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 2086system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 2087system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1105211 # number of ReadExReq accesses(hits+misses) 2088system.cpu1.l2cache.ReadExReq_accesses::total 1105211 # number of ReadExReq accesses(hits+misses) 2089system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8450384 # number of ReadCleanReq accesses(hits+misses) 2090system.cpu1.l2cache.ReadCleanReq_accesses::total 8450384 # number of ReadCleanReq accesses(hits+misses) 2091system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3594062 # number of ReadSharedReq accesses(hits+misses) 2092system.cpu1.l2cache.ReadSharedReq_accesses::total 3594062 # number of ReadSharedReq accesses(hits+misses) 2093system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 408042 # number of InvalidateReq accesses(hits+misses) 2094system.cpu1.l2cache.InvalidateReq_accesses::total 408042 # number of InvalidateReq accesses(hits+misses) 2095system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 517600 # number of demand (read+write) accesses 2096system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176508 # number of demand (read+write) accesses 2097system.cpu1.l2cache.demand_accesses::cpu1.inst 8450384 # number of demand (read+write) accesses 2098system.cpu1.l2cache.demand_accesses::cpu1.data 4699273 # number of demand (read+write) accesses 2099system.cpu1.l2cache.demand_accesses::total 13843765 # number of demand (read+write) accesses 2100system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 517600 # number of overall (read+write) accesses 2101system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176508 # number of overall (read+write) accesses 2102system.cpu1.l2cache.overall_accesses::cpu1.inst 8450384 # number of overall (read+write) accesses 2103system.cpu1.l2cache.overall_accesses::cpu1.data 4699273 # number of overall (read+write) accesses 2104system.cpu1.l2cache.overall_accesses::total 13843765 # number of overall (read+write) accesses 2105system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024289 # miss rate for ReadReq accesses 2106system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052389 # miss rate for ReadReq accesses 2107system.cpu1.l2cache.ReadReq_miss_rate::total 0.031435 # miss rate for ReadReq accesses 2108system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997472 # miss rate for UpgradeReq accesses 2109system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997472 # miss rate for UpgradeReq accesses 2110system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2111system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2112system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2113system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2114system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.242977 # miss rate for ReadExReq accesses 2115system.cpu1.l2cache.ReadExReq_miss_rate::total 0.242977 # miss rate for ReadExReq accesses 2116system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.080624 # miss rate for ReadCleanReq accesses 2117system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.080624 # miss rate for ReadCleanReq accesses 2118system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.268410 # miss rate for ReadSharedReq accesses 2119system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.268410 # miss rate for ReadSharedReq accesses 2120system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.603379 # miss rate for InvalidateReq accesses 2121system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.603379 # miss rate for InvalidateReq accesses 2122system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024289 # miss rate for demand accesses 2123system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052389 # miss rate for demand accesses 2124system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.080624 # miss rate for demand accesses 2125system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.262428 # miss rate for demand accesses 2126system.cpu1.l2cache.demand_miss_rate::total 0.139871 # miss rate for demand accesses 2127system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024289 # miss rate for overall accesses 2128system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052389 # miss rate for overall accesses 2129system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.080624 # miss rate for overall accesses 2130system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.262428 # miss rate for overall accesses 2131system.cpu1.l2cache.overall_miss_rate::total 0.139871 # miss rate for overall accesses 2132system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47599.148902 # average ReadReq miss latency 2133system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 50848.004758 # average ReadReq miss latency 2134system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48976.030066 # average ReadReq miss latency 2135system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14570.880613 # average UpgradeReq miss latency 2136system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14570.880613 # average UpgradeReq miss latency 2137system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9577.556506 # average SCUpgradeReq miss latency 2138system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9577.556506 # average SCUpgradeReq miss latency 2139system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 965599.600000 # average SCUpgradeFailReq miss latency 2140system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 965599.600000 # average SCUpgradeFailReq miss latency 2141system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52469.531647 # average ReadExReq miss latency 2142system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52469.531647 # average ReadExReq miss latency 2143system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35828.339226 # average ReadCleanReq miss latency 2144system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35828.339226 # average ReadCleanReq miss latency 2145system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37518.046870 # average ReadSharedReq miss latency 2146system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37518.046870 # average ReadSharedReq miss latency 2147system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1969.498871 # average InvalidateReq miss latency 2148system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1969.498871 # average InvalidateReq miss latency 2149system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47599.148902 # average overall miss latency 2150system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 50848.004758 # average overall miss latency 2151system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35828.339226 # average overall miss latency 2152system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40773.813811 # average overall miss latency 2153system.cpu1.l2cache.demand_avg_miss_latency::total 39126.172242 # average overall miss latency 2154system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47599.148902 # average overall miss latency 2155system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 50848.004758 # average overall miss latency 2156system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35828.339226 # average overall miss latency 2157system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40773.813811 # average overall miss latency 2158system.cpu1.l2cache.overall_avg_miss_latency::total 39126.172242 # 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number of demand (read+write) MSHR hits 2182system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7268 # number of demand (read+write) MSHR hits 2183system.cpu1.l2cache.demand_mshr_hits::total 7272 # number of demand (read+write) MSHR hits 2184system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits 2185system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2186system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7268 # number of overall MSHR hits 2187system.cpu1.l2cache.overall_mshr_hits::total 7272 # number of overall MSHR hits 2188system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12572 # number of ReadReq MSHR misses 2189system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9244 # number of ReadReq MSHR misses 2190system.cpu1.l2cache.ReadReq_mshr_misses::total 21816 # number of ReadReq MSHR misses 2191system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 768164 # number of HardPFReq MSHR misses 2192system.cpu1.l2cache.HardPFReq_mshr_misses::total 768164 # number of HardPFReq MSHR misses 2193system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 231248 # number of UpgradeReq MSHR misses 2194system.cpu1.l2cache.UpgradeReq_mshr_misses::total 231248 # number of UpgradeReq MSHR misses 2195system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199403 # number of SCUpgradeReq MSHR misses 2196system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199403 # number of SCUpgradeReq MSHR misses 2197system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2198system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2199system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 262063 # number of ReadExReq MSHR misses 2200system.cpu1.l2cache.ReadExReq_mshr_misses::total 262063 # number of ReadExReq MSHR misses 2201system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 681302 # number of ReadCleanReq MSHR misses 2202system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 681302 # number of ReadCleanReq MSHR misses 2203system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 963892 # number of ReadSharedReq MSHR misses 2204system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 963892 # number of ReadSharedReq MSHR misses 2205system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 246191 # number of InvalidateReq MSHR misses 2206system.cpu1.l2cache.InvalidateReq_mshr_misses::total 246191 # number of InvalidateReq MSHR misses 2207system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12572 # number of demand (read+write) MSHR misses 2208system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9244 # number of demand (read+write) MSHR misses 2209system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 681302 # number of demand (read+write) MSHR misses 2210system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1225955 # number of demand (read+write) MSHR misses 2211system.cpu1.l2cache.demand_mshr_misses::total 1929073 # number of demand (read+write) MSHR misses 2212system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12572 # number of overall MSHR misses 2213system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9244 # number of overall MSHR misses 2214system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 681302 # number of overall MSHR misses 2215system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1225955 # number of overall MSHR misses 2216system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 768164 # number of overall MSHR misses 2217system.cpu1.l2cache.overall_mshr_misses::total 2697237 # number of overall MSHR misses 2218system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2219system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable 2220system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7430 # number of ReadReq MSHR uncacheable 2221system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 2222system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable 2223system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2224system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses 2225system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 15071 # number of overall MSHR uncacheable misses 2226system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of ReadReq MSHR miss cycles 2227system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 414677500 # number of ReadReq MSHR miss cycles 2228system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 937662000 # number of ReadReq MSHR miss cycles 2229system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38779162359 # number of HardPFReq MSHR miss cycles 2230system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 38779162359 # number of HardPFReq MSHR miss cycles 2231system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7121255497 # number of UpgradeReq MSHR miss cycles 2232system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7121255497 # number of UpgradeReq MSHR miss cycles 2233system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3827966500 # number of SCUpgradeReq MSHR miss cycles 2234system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3827966500 # number of SCUpgradeReq MSHR miss cycles 2235system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4485998 # number of SCUpgradeFailReq MSHR miss cycles 2236system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4485998 # number of SCUpgradeFailReq MSHR miss cycles 2237system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11549115998 # number of ReadExReq MSHR miss cycles 2238system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11549115998 # number of ReadExReq MSHR miss cycles 2239system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322130500 # number of ReadCleanReq MSHR miss cycles 2240system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322130500 # number of ReadCleanReq MSHR miss cycles 2241system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30349496491 # number of ReadSharedReq MSHR miss cycles 2242system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30349496491 # number of ReadSharedReq MSHR miss cycles 2243system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11223039500 # number of InvalidateReq MSHR miss cycles 2244system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11223039500 # number of InvalidateReq MSHR miss cycles 2245system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of demand (read+write) MSHR miss cycles 2246system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 414677500 # number of demand (read+write) MSHR miss cycles 2247system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322130500 # number of demand (read+write) MSHR miss cycles 2248system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41898612489 # number of demand (read+write) MSHR miss cycles 2249system.cpu1.l2cache.demand_mshr_miss_latency::total 63158404989 # number of demand (read+write) MSHR miss cycles 2250system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of overall MSHR miss cycles 2251system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 414677500 # number of overall MSHR miss cycles 2252system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322130500 # number of overall MSHR miss cycles 2253system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41898612489 # number of overall MSHR miss cycles 2254system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38779162359 # number of overall MSHR miss cycles 2255system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348 # number of overall MSHR miss cycles 2256system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12274000 # number of ReadReq MSHR uncacheable cycles 2257system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860931500 # number of ReadReq MSHR uncacheable cycles 2258system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 873205500 # number of ReadReq MSHR uncacheable cycles 2259system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1037437000 # number of WriteReq MSHR uncacheable cycles 2260system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1037437000 # number of WriteReq MSHR uncacheable cycles 2261system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12274000 # number of overall MSHR uncacheable cycles 2262system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1898368500 # number of overall MSHR uncacheable cycles 2263system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1910642500 # number of overall MSHR uncacheable cycles 2264system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for ReadReq accesses 2265system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for ReadReq accesses 2266system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.031430 # mshr miss rate for ReadReq accesses 2267system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2268system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2269system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997472 # mshr miss rate for UpgradeReq accesses 2270system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997472 # mshr miss rate for UpgradeReq accesses 2271system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2272system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2273system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2274system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2275system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.237116 # mshr miss rate for ReadExReq accesses 2276system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.237116 # mshr miss rate for ReadExReq accesses 2277system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for ReadCleanReq accesses 2278system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080624 # mshr miss rate for ReadCleanReq accesses 2279system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.268190 # mshr miss rate for ReadSharedReq accesses 2280system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.268190 # mshr miss rate for ReadSharedReq accesses 2281system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.603347 # mshr miss rate for InvalidateReq accesses 2282system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.603347 # mshr miss rate for InvalidateReq accesses 2283system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for demand accesses 2284system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for demand accesses 2285system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for demand accesses 2286system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for demand accesses 2287system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139346 # mshr miss rate for demand accesses 2288system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for overall accesses 2289system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for overall accesses 2290system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for overall accesses 2291system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for overall accesses 2292system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2293system.cpu1.l2cache.overall_mshr_miss_rate::total 0.194834 # mshr miss rate for overall accesses 2294system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average ReadReq mshr miss latency 2295system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average ReadReq mshr miss latency 2296system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42980.473047 # average ReadReq mshr miss latency 2297system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average HardPFReq mshr miss latency 2298system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50482.920781 # average HardPFReq mshr miss latency 2299system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30794.884700 # average UpgradeReq mshr miss latency 2300system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30794.884700 # average UpgradeReq mshr miss latency 2301system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19197.135951 # average SCUpgradeReq mshr miss latency 2302system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951 # average SCUpgradeReq mshr miss latency 2303system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000 # average SCUpgradeFailReq mshr miss latency 2304system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000 # average SCUpgradeFailReq mshr miss latency 2305system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428 # average ReadExReq mshr miss latency 2306system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428 # average ReadExReq mshr miss latency 2307system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average ReadCleanReq mshr miss latency 2308system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467 # average ReadCleanReq mshr miss latency 2309system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700 # average ReadSharedReq mshr miss latency 2310system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700 # average ReadSharedReq mshr miss latency 2311system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224 # average InvalidateReq mshr miss latency 2312system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224 # average InvalidateReq mshr miss latency 2313system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency 2314system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency 2315system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency 2316system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency 2317system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687 # average overall mshr miss latency 2318system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency 2319system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency 2320system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency 2321system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency 2322system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency 2323system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency 2324system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency 2325system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency 2326system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency 2327system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency 2328system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency 2329system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency 2330system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency 2331system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency 2332system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2333system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. 2334system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2335system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2336system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter. 2337system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2338system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2339system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution 2340system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution 2341system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2342system.cpu1.toL2Bus.trans_dist::WriteReq 7641 # Transaction distribution 2343system.cpu1.toL2Bus.trans_dist::WriteResp 7641 # Transaction distribution 2344system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342023 # Transaction distribution 2345system.cpu1.toL2Bus.trans_dist::WritebackClean 10300458 # Transaction distribution 2346system.cpu1.toL2Bus.trans_dist::CleanEvict 2852323 # Transaction distribution 2347system.cpu1.toL2Bus.trans_dist::HardPFReq 992320 # Transaction distribution 2348system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution 2349system.cpu1.toL2Bus.trans_dist::UpgradeReq 439929 # Transaction distribution 2350system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 359269 # Transaction distribution 2351system.cpu1.toL2Bus.trans_dist::UpgradeResp 498097 # Transaction distribution 2352system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution 2353system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 2354system.cpu1.toL2Bus.trans_dist::ReadExReq 1135001 # Transaction distribution 2355system.cpu1.toL2Bus.trans_dist::ReadExResp 1111432 # Transaction distribution 2356system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8450384 # Transaction distribution 2357system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4652967 # Transaction distribution 2358system.cpu1.toL2Bus.trans_dist::InvalidateReq 462443 # Transaction distribution 2359system.cpu1.toL2Bus.trans_dist::InvalidateResp 408042 # Transaction distribution 2360system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25350826 # Packet count per connected master and slave (bytes) 2361system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16287327 # Packet count per connected master and slave (bytes) 2362system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370687 # Packet count per connected master and slave (bytes) 2363system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1094902 # Packet count per connected master and slave (bytes) 2364system.cpu1.toL2Bus.pkt_count::total 43103742 # Packet count per connected master and slave (bytes) 2365system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1081622336 # Cumulative packet size per connected master and slave (bytes) 2366system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 628052039 # Cumulative packet size per connected master and slave (bytes) 2367system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1412064 # Cumulative packet size per connected master and slave (bytes) 2368system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4140800 # Cumulative packet size per connected master and slave (bytes) 2369system.cpu1.toL2Bus.pkt_size::total 1715227239 # Cumulative packet size per connected master and slave (bytes) 2370system.cpu1.toL2Bus.snoops 6782222 # Total snoops (count) 2371system.cpu1.toL2Bus.snoop_fanout::samples 21311973 # Request fanout histogram 2372system.cpu1.toL2Bus.snoop_fanout::mean 0.112849 # Request fanout histogram 2373system.cpu1.toL2Bus.snoop_fanout::stdev 0.316459 # Request fanout histogram 2374system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2375system.cpu1.toL2Bus.snoop_fanout::0 18907277 88.72% 88.72% # Request fanout histogram 2376system.cpu1.toL2Bus.snoop_fanout::1 2404354 11.28% 100.00% # Request fanout histogram 2377system.cpu1.toL2Bus.snoop_fanout::2 342 0.00% 100.00% # Request fanout histogram 2378system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2379system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2380system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2381system.cpu1.toL2Bus.snoop_fanout::total 21311973 # Request fanout histogram 2382system.cpu1.toL2Bus.reqLayer0.occupancy 27584218481 # Layer occupancy (ticks) 2383system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2384system.cpu1.toL2Bus.snoopLayer0.occupancy 185839513 # Layer occupancy (ticks) 2385system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2386system.cpu1.toL2Bus.respLayer0.occupancy 12678955503 # Layer occupancy (ticks) 2387system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2388system.cpu1.toL2Bus.respLayer1.occupancy 7484332893 # Layer occupancy (ticks) 2389system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2390system.cpu1.toL2Bus.respLayer2.occupancy 194250357 # Layer occupancy (ticks) 2391system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2392system.cpu1.toL2Bus.respLayer3.occupancy 577391819 # Layer occupancy (ticks) 2393system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2394system.iobus.trans_dist::ReadReq 40390 # Transaction distribution 2395system.iobus.trans_dist::ReadResp 40390 # Transaction distribution 2396system.iobus.trans_dist::WriteReq 136973 # Transaction distribution 2397system.iobus.trans_dist::WriteResp 136973 # Transaction distribution 2398system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) 2399system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2400system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2401system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2402system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2403system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2404system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2405system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2406system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2407system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2408system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2409system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 2410system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2411system.iobus.pkt_count_system.bridge.master::total 122924 # Packet count per connected master and slave (bytes) 2412system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231722 # Packet count per connected master and slave (bytes) 2413system.iobus.pkt_count_system.realview.ide.dma::total 231722 # Packet count per connected master and slave (bytes) 2414system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2415system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2416system.iobus.pkt_count::total 354726 # Packet count per connected master and slave (bytes) 2417system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) 2418system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2419system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2420system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2421system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2422system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2423system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2424system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2425system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2426system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2427system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2428system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 2429system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2430system.iobus.pkt_size_system.bridge.master::total 155939 # Cumulative packet size per connected master and slave (bytes) 2431system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355240 # Cumulative packet size per connected master and slave (bytes) 2432system.iobus.pkt_size_system.realview.ide.dma::total 7355240 # Cumulative packet size per connected master and slave (bytes) 2433system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2434system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2435system.iobus.pkt_size::total 7513265 # Cumulative packet size per connected master and slave (bytes) 2436system.iobus.reqLayer0.occupancy 42523001 # Layer occupancy (ticks) 2437system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2438system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 2439system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2440system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) 2441system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2442system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 2443system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2444system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) 2445system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2446system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 2447system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2448system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 2449system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2450system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 2451system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2452system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 2453system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2454system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) 2455system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2456system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 2457system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2458system.iobus.reqLayer23.occupancy 25802501 # Layer occupancy (ticks) 2459system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2460system.iobus.reqLayer24.occupancy 36398001 # Layer occupancy (ticks) 2461system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2462system.iobus.reqLayer25.occupancy 568577386 # Layer occupancy (ticks) 2463system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2464system.iobus.respLayer0.occupancy 92938000 # Layer occupancy (ticks) 2465system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2466system.iobus.respLayer3.occupancy 148162000 # Layer occupancy (ticks) 2467system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2468system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2469system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2470system.iocache.tags.replacements 115843 # number of replacements 2471system.iocache.tags.tagsinuse 11.310828 # Cycle average of tags in use 2472system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2473system.iocache.tags.sampled_refs 115859 # Sample count of references to valid blocks. 2474system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2475system.iocache.tags.warmup_cycle 9138959017000 # Cycle when the warmup percentage was hit. 2476system.iocache.tags.occ_blocks::realview.ethernet 3.826637 # Average occupied blocks per requestor 2477system.iocache.tags.occ_blocks::realview.ide 7.484190 # Average occupied blocks per requestor 2478system.iocache.tags.occ_percent::realview.ethernet 0.239165 # Average percentage of cache occupancy 2479system.iocache.tags.occ_percent::realview.ide 0.467762 # Average percentage of cache occupancy 2480system.iocache.tags.occ_percent::total 0.706927 # Average percentage of cache occupancy 2481system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2482system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2483system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2484system.iocache.tags.tag_accesses 1043106 # Number of tag accesses 2485system.iocache.tags.data_accesses 1043106 # Number of data accesses 2486system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2487system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses 2488system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses 2489system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2490system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2491system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2492system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2493system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2494system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses 2495system.iocache.demand_misses::total 8917 # number of demand (read+write) misses 2496system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2497system.iocache.overall_misses::realview.ide 8877 # number of overall misses 2498system.iocache.overall_misses::total 8917 # number of overall misses 2499system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2500system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles 2501system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles 2502system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2503system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2504system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles 2505system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles 2506system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 2507system.iocache.demand_miss_latency::realview.ide 1651659585 # number of demand (read+write) miss cycles 2508system.iocache.demand_miss_latency::total 1657228085 # number of demand (read+write) miss cycles 2509system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 2510system.iocache.overall_miss_latency::realview.ide 1651659585 # number of overall miss cycles 2511system.iocache.overall_miss_latency::total 1657228085 # number of overall miss cycles 2512system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2513system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) 2514system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) 2515system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2516system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2517system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2518system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2519system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2520system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses 2521system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses 2522system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2523system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses 2524system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses 2525system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2526system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2527system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2528system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2529system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2530system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2531system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2532system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2533system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2534system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2535system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2536system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2537system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2538system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2539system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency 2540system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency 2541system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2542system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2543system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency 2544system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency 2545system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2546system.iocache.demand_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency 2547system.iocache.demand_avg_miss_latency::total 185850.407648 # average overall miss latency 2548system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2549system.iocache.overall_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency 2550system.iocache.overall_avg_miss_latency::total 185850.407648 # average overall miss latency 2551system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked 2552system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2553system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked 2554system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2555system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked 2556system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2557system.iocache.fast_writes 0 # number of fast writes performed 2558system.iocache.cache_copies 0 # number of cache copies performed 2559system.iocache.writebacks::writebacks 106951 # number of writebacks 2560system.iocache.writebacks::total 106951 # number of writebacks 2561system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2562system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses 2563system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses 2564system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2565system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2566system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2567system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2568system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2569system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses 2570system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses 2571system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2572system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses 2573system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses 2574system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2575system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles 2576system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles 2577system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2578system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2579system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles 2580system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles 2581system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 2582system.iocache.demand_mshr_miss_latency::realview.ide 1207809585 # number of demand (read+write) MSHR miss cycles 2583system.iocache.demand_mshr_miss_latency::total 1211378085 # number of demand (read+write) MSHR miss cycles 2584system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 2585system.iocache.overall_mshr_miss_latency::realview.ide 1207809585 # number of overall MSHR miss cycles 2586system.iocache.overall_mshr_miss_latency::total 1211378085 # number of overall MSHR miss cycles 2587system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2588system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2589system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2590system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2591system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2592system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2593system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2594system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2595system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2596system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2597system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2598system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2599system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2600system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2601system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311 # average ReadReq mshr miss latency 2602system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906 # average ReadReq mshr miss latency 2603system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2604system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2605system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency 2606system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency 2607system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2608system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency 2609system.iocache.demand_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency 2610system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2611system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency 2612system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency 2613system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2614system.l2c.tags.replacements 1387428 # number of replacements 2615system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use 2616system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. 2617system.l2c.tags.sampled_refs 1448331 # Sample count of references to valid blocks. 2618system.l2c.tags.avg_refs 4.585924 # Average number of references to valid blocks. 2619system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. 2620system.l2c.tags.occ_blocks::writebacks 22018.288167 # Average occupied blocks per requestor 2621system.l2c.tags.occ_blocks::cpu0.dtb.walker 94.707462 # Average occupied blocks per requestor 2622system.l2c.tags.occ_blocks::cpu0.itb.walker 112.653017 # Average occupied blocks per requestor 2623system.l2c.tags.occ_blocks::cpu0.inst 5422.209579 # Average occupied blocks per requestor 2624system.l2c.tags.occ_blocks::cpu0.data 6394.892392 # Average occupied blocks per requestor 2625system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5645.972820 # Average occupied blocks per requestor 2626system.l2c.tags.occ_blocks::cpu1.dtb.walker 238.578829 # Average occupied blocks per requestor 2627system.l2c.tags.occ_blocks::cpu1.itb.walker 322.014833 # Average occupied blocks per requestor 2628system.l2c.tags.occ_blocks::cpu1.inst 3724.645789 # Average occupied blocks per requestor 2629system.l2c.tags.occ_blocks::cpu1.data 6574.117531 # Average occupied blocks per requestor 2630system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13003.177099 # Average occupied blocks per requestor 2631system.l2c.tags.occ_percent::writebacks 0.335972 # Average percentage of cache occupancy 2632system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001445 # Average percentage of cache occupancy 2633system.l2c.tags.occ_percent::cpu0.itb.walker 0.001719 # Average percentage of cache occupancy 2634system.l2c.tags.occ_percent::cpu0.inst 0.082736 # Average percentage of cache occupancy 2635system.l2c.tags.occ_percent::cpu0.data 0.097578 # Average percentage of cache occupancy 2636system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.086151 # Average percentage of cache occupancy 2637system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003640 # Average percentage of cache occupancy 2638system.l2c.tags.occ_percent::cpu1.itb.walker 0.004914 # Average percentage of cache occupancy 2639system.l2c.tags.occ_percent::cpu1.inst 0.056834 # Average percentage of cache occupancy 2640system.l2c.tags.occ_percent::cpu1.data 0.100313 # Average percentage of cache occupancy 2641system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198413 # Average percentage of cache occupancy 2642system.l2c.tags.occ_percent::total 0.969715 # Average percentage of cache occupancy 2643system.l2c.tags.occ_task_id_blocks::1022 10329 # Occupied blocks per task id 2644system.l2c.tags.occ_task_id_blocks::1023 221 # Occupied blocks per task id 2645system.l2c.tags.occ_task_id_blocks::1024 50353 # Occupied blocks per task id 2646system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 2647system.l2c.tags.age_task_id_blocks_1022::2 518 # Occupied blocks per task id 2648system.l2c.tags.age_task_id_blocks_1022::3 2097 # Occupied blocks per task id 2649system.l2c.tags.age_task_id_blocks_1022::4 7705 # Occupied blocks per task id 2650system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 2651system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id 2652system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 2653system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id 2654system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id 2655system.l2c.tags.age_task_id_blocks_1024::3 13754 # Occupied blocks per task id 2656system.l2c.tags.age_task_id_blocks_1024::4 33762 # Occupied blocks per task id 2657system.l2c.tags.occ_task_id_percent::1022 0.157608 # Percentage of cache occupancy per task id 2658system.l2c.tags.occ_task_id_percent::1023 0.003372 # Percentage of cache occupancy per task id 2659system.l2c.tags.occ_task_id_percent::1024 0.768326 # Percentage of cache occupancy per task id 2660system.l2c.tags.tag_accesses 81054625 # Number of tag accesses 2661system.l2c.tags.data_accesses 81054625 # Number of data accesses 2662system.l2c.WritebackDirty_hits::writebacks 2804232 # number of WritebackDirty hits 2663system.l2c.WritebackDirty_hits::total 2804232 # number of WritebackDirty hits 2664system.l2c.UpgradeReq_hits::cpu0.data 166858 # number of UpgradeReq hits 2665system.l2c.UpgradeReq_hits::cpu1.data 141079 # number of UpgradeReq hits 2666system.l2c.UpgradeReq_hits::total 307937 # number of UpgradeReq hits 2667system.l2c.SCUpgradeReq_hits::cpu0.data 43211 # number of SCUpgradeReq hits 2668system.l2c.SCUpgradeReq_hits::cpu1.data 40746 # number of SCUpgradeReq hits 2669system.l2c.SCUpgradeReq_hits::total 83957 # number of SCUpgradeReq hits 2670system.l2c.ReadExReq_hits::cpu0.data 52655 # number of ReadExReq hits 2671system.l2c.ReadExReq_hits::cpu1.data 61293 # number of ReadExReq hits 2672system.l2c.ReadExReq_hits::total 113948 # number of ReadExReq hits 2673system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6392 # number of ReadSharedReq hits 2674system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4086 # number of ReadSharedReq hits 2675system.l2c.ReadSharedReq_hits::cpu0.inst 674086 # number of ReadSharedReq hits 2676system.l2c.ReadSharedReq_hits::cpu0.data 617640 # number of ReadSharedReq hits 2677system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 331682 # number of ReadSharedReq hits 2678system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 7229 # number of ReadSharedReq hits 2679system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5312 # number of ReadSharedReq hits 2680system.l2c.ReadSharedReq_hits::cpu1.inst 633543 # number of ReadSharedReq hits 2681system.l2c.ReadSharedReq_hits::cpu1.data 593468 # number of ReadSharedReq hits 2682system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 330392 # number of ReadSharedReq hits 2683system.l2c.ReadSharedReq_hits::total 3203830 # number of ReadSharedReq hits 2684system.l2c.InvalidateReq_hits::cpu0.data 133432 # number of InvalidateReq hits 2685system.l2c.InvalidateReq_hits::cpu1.data 138176 # number of InvalidateReq hits 2686system.l2c.InvalidateReq_hits::total 271608 # number of InvalidateReq hits 2687system.l2c.demand_hits::cpu0.dtb.walker 6392 # number of demand (read+write) hits 2688system.l2c.demand_hits::cpu0.itb.walker 4086 # number of demand (read+write) hits 2689system.l2c.demand_hits::cpu0.inst 674086 # number of demand (read+write) hits 2690system.l2c.demand_hits::cpu0.data 670295 # number of demand (read+write) hits 2691system.l2c.demand_hits::cpu0.l2cache.prefetcher 331682 # number of demand (read+write) hits 2692system.l2c.demand_hits::cpu1.dtb.walker 7229 # number of demand (read+write) hits 2693system.l2c.demand_hits::cpu1.itb.walker 5312 # number of demand (read+write) hits 2694system.l2c.demand_hits::cpu1.inst 633543 # number of demand (read+write) hits 2695system.l2c.demand_hits::cpu1.data 654761 # number of demand (read+write) hits 2696system.l2c.demand_hits::cpu1.l2cache.prefetcher 330392 # number of demand (read+write) hits 2697system.l2c.demand_hits::total 3317778 # number of demand (read+write) hits 2698system.l2c.overall_hits::cpu0.dtb.walker 6392 # number of overall hits 2699system.l2c.overall_hits::cpu0.itb.walker 4086 # number of overall hits 2700system.l2c.overall_hits::cpu0.inst 674086 # number of overall hits 2701system.l2c.overall_hits::cpu0.data 670295 # number of overall hits 2702system.l2c.overall_hits::cpu0.l2cache.prefetcher 331682 # number of overall hits 2703system.l2c.overall_hits::cpu1.dtb.walker 7229 # number of overall hits 2704system.l2c.overall_hits::cpu1.itb.walker 5312 # number of overall hits 2705system.l2c.overall_hits::cpu1.inst 633543 # number of overall hits 2706system.l2c.overall_hits::cpu1.data 654761 # number of overall hits 2707system.l2c.overall_hits::cpu1.l2cache.prefetcher 330392 # number of overall hits 2708system.l2c.overall_hits::total 3317778 # number of overall hits 2709system.l2c.UpgradeReq_misses::cpu0.data 63565 # number of UpgradeReq misses 2710system.l2c.UpgradeReq_misses::cpu1.data 62220 # number of UpgradeReq misses 2711system.l2c.UpgradeReq_misses::total 125785 # number of UpgradeReq misses 2712system.l2c.SCUpgradeReq_misses::cpu0.data 13487 # number of SCUpgradeReq misses 2713system.l2c.SCUpgradeReq_misses::cpu1.data 11849 # number of SCUpgradeReq misses 2714system.l2c.SCUpgradeReq_misses::total 25336 # number of SCUpgradeReq misses 2715system.l2c.ReadExReq_misses::cpu0.data 80559 # number of ReadExReq misses 2716system.l2c.ReadExReq_misses::cpu1.data 50978 # number of ReadExReq misses 2717system.l2c.ReadExReq_misses::total 131537 # number of ReadExReq misses 2718system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses 2719system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1402 # number of ReadSharedReq misses 2720system.l2c.ReadSharedReq_misses::cpu0.inst 75397 # number of ReadSharedReq misses 2721system.l2c.ReadSharedReq_misses::cpu0.data 144871 # number of ReadSharedReq misses 2722system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 231057 # number of ReadSharedReq misses 2723system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2351 # number of ReadSharedReq misses 2724system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1996 # number of ReadSharedReq misses 2725system.l2c.ReadSharedReq_misses::cpu1.inst 47759 # number of ReadSharedReq misses 2726system.l2c.ReadSharedReq_misses::cpu1.data 100866 # number of ReadSharedReq misses 2727system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 195589 # number of ReadSharedReq misses 2728system.l2c.ReadSharedReq_misses::total 802834 # number of ReadSharedReq misses 2729system.l2c.InvalidateReq_misses::cpu0.data 470568 # number of InvalidateReq misses 2730system.l2c.InvalidateReq_misses::cpu1.data 95260 # number of InvalidateReq misses 2731system.l2c.InvalidateReq_misses::total 565828 # number of InvalidateReq misses 2732system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses 2733system.l2c.demand_misses::cpu0.itb.walker 1402 # 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number of overall misses 2746system.l2c.overall_misses::cpu0.data 225430 # number of overall misses 2747system.l2c.overall_misses::cpu0.l2cache.prefetcher 231057 # number of overall misses 2748system.l2c.overall_misses::cpu1.dtb.walker 2351 # number of overall misses 2749system.l2c.overall_misses::cpu1.itb.walker 1996 # number of overall misses 2750system.l2c.overall_misses::cpu1.inst 47759 # number of overall misses 2751system.l2c.overall_misses::cpu1.data 151844 # number of overall misses 2752system.l2c.overall_misses::cpu1.l2cache.prefetcher 195589 # number of overall misses 2753system.l2c.overall_misses::total 934371 # number of overall misses 2754system.l2c.UpgradeReq_miss_latency::cpu0.data 1159828500 # number of UpgradeReq miss cycles 2755system.l2c.UpgradeReq_miss_latency::cpu1.data 1086354500 # number of UpgradeReq miss cycles 2756system.l2c.UpgradeReq_miss_latency::total 2246183000 # number of UpgradeReq miss cycles 2757system.l2c.SCUpgradeReq_miss_latency::cpu0.data 232119500 # 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number of ReadSharedReq miss cycles 2768system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 328460500 # number of ReadSharedReq miss cycles 2769system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 280819500 # number of ReadSharedReq miss cycles 2770system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6431697000 # number of ReadSharedReq miss cycles 2771system.l2c.ReadSharedReq_miss_latency::cpu1.data 14230471500 # number of ReadSharedReq miss cycles 2772system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32826320681 # number of ReadSharedReq miss cycles 2773system.l2c.ReadSharedReq_miss_latency::total 125256809936 # number of ReadSharedReq miss cycles 2774system.l2c.InvalidateReq_miss_latency::cpu0.data 174062000 # number of InvalidateReq miss cycles 2775system.l2c.InvalidateReq_miss_latency::cpu1.data 150333500 # number of InvalidateReq miss cycles 2776system.l2c.InvalidateReq_miss_latency::total 324395500 # number of InvalidateReq miss cycles 2777system.l2c.demand_miss_latency::cpu0.dtb.walker 218104500 # number of demand (read+write) miss cycles 2778system.l2c.demand_miss_latency::cpu0.itb.walker 197814500 # number of demand (read+write) miss cycles 2779system.l2c.demand_miss_latency::cpu0.inst 10138484000 # number of demand (read+write) miss cycles 2780system.l2c.demand_miss_latency::cpu0.data 31372323000 # number of demand (read+write) miss cycles 2781system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 40382282755 # number of demand (read+write) miss cycles 2782system.l2c.demand_miss_latency::cpu1.dtb.walker 328460500 # number of demand (read+write) miss cycles 2783system.l2c.demand_miss_latency::cpu1.itb.walker 280819500 # number of demand (read+write) miss cycles 2784system.l2c.demand_miss_latency::cpu1.inst 6431697000 # number of demand (read+write) miss cycles 2785system.l2c.demand_miss_latency::cpu1.data 21027960500 # number of demand (read+write) miss cycles 2786system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32826320681 # number of demand (read+write) miss cycles 2787system.l2c.demand_miss_latency::total 143204266936 # number of demand (read+write) miss cycles 2788system.l2c.overall_miss_latency::cpu0.dtb.walker 218104500 # number of overall miss cycles 2789system.l2c.overall_miss_latency::cpu0.itb.walker 197814500 # number of overall miss cycles 2790system.l2c.overall_miss_latency::cpu0.inst 10138484000 # number of overall miss cycles 2791system.l2c.overall_miss_latency::cpu0.data 31372323000 # number of overall miss cycles 2792system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 40382282755 # number of overall miss cycles 2793system.l2c.overall_miss_latency::cpu1.dtb.walker 328460500 # number of overall miss cycles 2794system.l2c.overall_miss_latency::cpu1.itb.walker 280819500 # number of overall miss cycles 2795system.l2c.overall_miss_latency::cpu1.inst 6431697000 # number of overall miss cycles 2796system.l2c.overall_miss_latency::cpu1.data 21027960500 # number of overall miss cycles 2797system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32826320681 # number of overall miss cycles 2798system.l2c.overall_miss_latency::total 143204266936 # number of overall miss cycles 2799system.l2c.WritebackDirty_accesses::writebacks 2804232 # number of WritebackDirty accesses(hits+misses) 2800system.l2c.WritebackDirty_accesses::total 2804232 # number of WritebackDirty accesses(hits+misses) 2801system.l2c.UpgradeReq_accesses::cpu0.data 230423 # number of UpgradeReq accesses(hits+misses) 2802system.l2c.UpgradeReq_accesses::cpu1.data 203299 # number of UpgradeReq accesses(hits+misses) 2803system.l2c.UpgradeReq_accesses::total 433722 # number of UpgradeReq accesses(hits+misses) 2804system.l2c.SCUpgradeReq_accesses::cpu0.data 56698 # number of SCUpgradeReq accesses(hits+misses) 2805system.l2c.SCUpgradeReq_accesses::cpu1.data 52595 # number of SCUpgradeReq accesses(hits+misses) 2806system.l2c.SCUpgradeReq_accesses::total 109293 # number of SCUpgradeReq accesses(hits+misses) 2807system.l2c.ReadExReq_accesses::cpu0.data 133214 # number of ReadExReq accesses(hits+misses) 2808system.l2c.ReadExReq_accesses::cpu1.data 112271 # number of ReadExReq accesses(hits+misses) 2809system.l2c.ReadExReq_accesses::total 245485 # number of ReadExReq accesses(hits+misses) 2810system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7938 # number of ReadSharedReq accesses(hits+misses) 2811system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5488 # number of ReadSharedReq accesses(hits+misses) 2812system.l2c.ReadSharedReq_accesses::cpu0.inst 749483 # number of ReadSharedReq accesses(hits+misses) 2813system.l2c.ReadSharedReq_accesses::cpu0.data 762511 # number of ReadSharedReq accesses(hits+misses) 2814system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 562739 # number of ReadSharedReq accesses(hits+misses) 2815system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9580 # number of ReadSharedReq accesses(hits+misses) 2816system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7308 # number of ReadSharedReq accesses(hits+misses) 2817system.l2c.ReadSharedReq_accesses::cpu1.inst 681302 # number of ReadSharedReq accesses(hits+misses) 2818system.l2c.ReadSharedReq_accesses::cpu1.data 694334 # number of ReadSharedReq accesses(hits+misses) 2819system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 525981 # number of ReadSharedReq accesses(hits+misses) 2820system.l2c.ReadSharedReq_accesses::total 4006664 # number of ReadSharedReq accesses(hits+misses) 2821system.l2c.InvalidateReq_accesses::cpu0.data 604000 # number of InvalidateReq accesses(hits+misses) 2822system.l2c.InvalidateReq_accesses::cpu1.data 233436 # number of InvalidateReq accesses(hits+misses) 2823system.l2c.InvalidateReq_accesses::total 837436 # number of InvalidateReq accesses(hits+misses) 2824system.l2c.demand_accesses::cpu0.dtb.walker 7938 # number of demand (read+write) accesses 2825system.l2c.demand_accesses::cpu0.itb.walker 5488 # number of demand (read+write) accesses 2826system.l2c.demand_accesses::cpu0.inst 749483 # number of demand (read+write) accesses 2827system.l2c.demand_accesses::cpu0.data 895725 # number of demand (read+write) accesses 2828system.l2c.demand_accesses::cpu0.l2cache.prefetcher 562739 # number of demand (read+write) accesses 2829system.l2c.demand_accesses::cpu1.dtb.walker 9580 # number of demand (read+write) accesses 2830system.l2c.demand_accesses::cpu1.itb.walker 7308 # number of demand (read+write) accesses 2831system.l2c.demand_accesses::cpu1.inst 681302 # number of demand (read+write) accesses 2832system.l2c.demand_accesses::cpu1.data 806605 # number of demand (read+write) accesses 2833system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525981 # number of demand (read+write) accesses 2834system.l2c.demand_accesses::total 4252149 # number of demand (read+write) accesses 2835system.l2c.overall_accesses::cpu0.dtb.walker 7938 # number of overall (read+write) accesses 2836system.l2c.overall_accesses::cpu0.itb.walker 5488 # number of overall (read+write) accesses 2837system.l2c.overall_accesses::cpu0.inst 749483 # number of overall (read+write) accesses 2838system.l2c.overall_accesses::cpu0.data 895725 # number of overall (read+write) accesses 2839system.l2c.overall_accesses::cpu0.l2cache.prefetcher 562739 # number of overall (read+write) accesses 2840system.l2c.overall_accesses::cpu1.dtb.walker 9580 # number of overall (read+write) accesses 2841system.l2c.overall_accesses::cpu1.itb.walker 7308 # number of overall (read+write) accesses 2842system.l2c.overall_accesses::cpu1.inst 681302 # number of overall (read+write) accesses 2843system.l2c.overall_accesses::cpu1.data 806605 # number of overall (read+write) accesses 2844system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525981 # number of overall (read+write) accesses 2845system.l2c.overall_accesses::total 4252149 # number of overall (read+write) accesses 2846system.l2c.UpgradeReq_miss_rate::cpu0.data 0.275862 # miss rate for UpgradeReq accesses 2847system.l2c.UpgradeReq_miss_rate::cpu1.data 0.306052 # miss rate for UpgradeReq accesses 2848system.l2c.UpgradeReq_miss_rate::total 0.290013 # miss rate for UpgradeReq accesses 2849system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.237874 # miss rate for SCUpgradeReq accesses 2850system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.225288 # miss rate for SCUpgradeReq accesses 2851system.l2c.SCUpgradeReq_miss_rate::total 0.231817 # miss rate for SCUpgradeReq accesses 2852system.l2c.ReadExReq_miss_rate::cpu0.data 0.604734 # miss rate for ReadExReq accesses 2853system.l2c.ReadExReq_miss_rate::cpu1.data 0.454062 # miss rate for ReadExReq accesses 2854system.l2c.ReadExReq_miss_rate::total 0.535825 # miss rate for ReadExReq accesses 2855system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for ReadSharedReq accesses 2856system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.255466 # miss rate for ReadSharedReq accesses 2857system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100599 # miss rate for ReadSharedReq accesses 2858system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.189992 # miss rate for ReadSharedReq accesses 2859system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for ReadSharedReq accesses 2860system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for ReadSharedReq accesses 2861system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.273125 # miss rate for ReadSharedReq accesses 2862system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.070100 # miss rate for ReadSharedReq accesses 2863system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.145270 # miss rate for ReadSharedReq accesses 2864system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for ReadSharedReq accesses 2865system.l2c.ReadSharedReq_miss_rate::total 0.200375 # miss rate for ReadSharedReq accesses 2866system.l2c.InvalidateReq_miss_rate::cpu0.data 0.779086 # miss rate for InvalidateReq accesses 2867system.l2c.InvalidateReq_miss_rate::cpu1.data 0.408078 # miss rate for InvalidateReq accesses 2868system.l2c.InvalidateReq_miss_rate::total 0.675667 # miss rate for InvalidateReq accesses 2869system.l2c.demand_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for demand accesses 2870system.l2c.demand_miss_rate::cpu0.itb.walker 0.255466 # miss rate for demand accesses 2871system.l2c.demand_miss_rate::cpu0.inst 0.100599 # miss rate for demand accesses 2872system.l2c.demand_miss_rate::cpu0.data 0.251673 # miss rate for demand accesses 2873system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for demand accesses 2874system.l2c.demand_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for demand accesses 2875system.l2c.demand_miss_rate::cpu1.itb.walker 0.273125 # miss rate for demand accesses 2876system.l2c.demand_miss_rate::cpu1.inst 0.070100 # miss rate for demand accesses 2877system.l2c.demand_miss_rate::cpu1.data 0.188251 # miss rate for demand accesses 2878system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for demand accesses 2879system.l2c.demand_miss_rate::total 0.219741 # miss rate for demand accesses 2880system.l2c.overall_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for overall accesses 2881system.l2c.overall_miss_rate::cpu0.itb.walker 0.255466 # miss rate for overall accesses 2882system.l2c.overall_miss_rate::cpu0.inst 0.100599 # miss rate for overall accesses 2883system.l2c.overall_miss_rate::cpu0.data 0.251673 # miss rate for overall accesses 2884system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for overall accesses 2885system.l2c.overall_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for overall accesses 2886system.l2c.overall_miss_rate::cpu1.itb.walker 0.273125 # miss rate for overall accesses 2887system.l2c.overall_miss_rate::cpu1.inst 0.070100 # miss rate for overall accesses 2888system.l2c.overall_miss_rate::cpu1.data 0.188251 # miss rate for overall accesses 2889system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for overall accesses 2890system.l2c.overall_miss_rate::total 0.219741 # miss rate for overall accesses 2891system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18246.338394 # average UpgradeReq miss latency 2892system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17459.892318 # average UpgradeReq miss latency 2893system.l2c.UpgradeReq_avg_miss_latency::total 17857.320030 # average UpgradeReq miss latency 2894system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17210.610217 # average SCUpgradeReq miss latency 2895system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17669.929952 # average SCUpgradeReq miss latency 2896system.l2c.SCUpgradeReq_avg_miss_latency::total 17425.422324 # average SCUpgradeReq miss latency 2897system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138407.477749 # average ReadExReq miss latency 2898system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133341.617953 # average ReadExReq miss latency 2899system.l2c.ReadExReq_avg_miss_latency::total 136444.171602 # average ReadExReq miss latency 2900system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average ReadSharedReq miss latency 2901system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141094.507846 # average ReadSharedReq miss latency 2902system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134468.002706 # average ReadSharedReq miss latency 2903system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139588.703053 # average ReadSharedReq miss latency 2904system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average ReadSharedReq miss latency 2905system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average ReadSharedReq miss latency 2906system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140691.132265 # average ReadSharedReq miss latency 2907system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134669.842333 # average ReadSharedReq miss latency 2908system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141082.936768 # average ReadSharedReq miss latency 2909system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average ReadSharedReq miss latency 2910system.l2c.ReadSharedReq_avg_miss_latency::total 156018.317530 # average ReadSharedReq miss latency 2911system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 369.897656 # average InvalidateReq miss latency 2912system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1578.138778 # average InvalidateReq miss latency 2913system.l2c.InvalidateReq_avg_miss_latency::total 573.311148 # average InvalidateReq miss latency 2914system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency 2915system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency 2916system.l2c.demand_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency 2917system.l2c.demand_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency 2918system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency 2919system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency 2920system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency 2921system.l2c.demand_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency 2922system.l2c.demand_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency 2923system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency 2924system.l2c.demand_avg_miss_latency::total 153262.747812 # average overall miss latency 2925system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency 2926system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency 2927system.l2c.overall_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency 2928system.l2c.overall_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency 2929system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency 2930system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency 2931system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency 2932system.l2c.overall_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency 2933system.l2c.overall_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency 2934system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency 2935system.l2c.overall_avg_miss_latency::total 153262.747812 # average overall miss latency 2936system.l2c.blocked_cycles::no_mshrs 971 # number of cycles access was blocked 2937system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2938system.l2c.blocked::no_mshrs 13 # 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number of overall MSHR misses 3008system.l2c.overall_mshr_misses::cpu1.data 151813 # number of overall MSHR misses 3009system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 195589 # number of overall MSHR misses 3010system.l2c.overall_mshr_misses::total 933948 # number of overall MSHR misses 3011system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 3012system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable 3013system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 3014system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7335 # number of ReadReq MSHR uncacheable 3015system.l2c.ReadReq_mshr_uncacheable::total 91289 # number of ReadReq MSHR uncacheable 3016system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 3017system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 3018system.l2c.WriteReq_mshr_uncacheable::total 38789 # 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number of ReadSharedReq MSHR miss cycles 3038system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 304834024 # number of ReadSharedReq MSHR miss cycles 3039system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 260849021 # number of ReadSharedReq MSHR miss cycles 3040system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5931658488 # number of ReadSharedReq MSHR miss cycles 3041system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13217891635 # number of ReadSharedReq MSHR miss cycles 3042system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30868571958 # number of ReadSharedReq MSHR miss cycles 3043system.l2c.ReadSharedReq_mshr_miss_latency::total 117179725536 # number of ReadSharedReq MSHR miss cycles 3044system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 32895409499 # number of InvalidateReq MSHR miss cycles 3045system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 6658686499 # number of InvalidateReq MSHR miss cycles 3046system.l2c.InvalidateReq_mshr_miss_latency::total 39554095998 # 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number of overall MSHR miss cycles 3066system.l2c.overall_mshr_miss_latency::cpu1.data 19505265139 # number of overall MSHR miss cycles 3067system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30868571958 # number of overall MSHR miss cycles 3068system.l2c.overall_mshr_miss_latency::total 133811260722 # number of overall MSHR miss cycles 3069system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles 3070system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5220688053 # number of ReadReq MSHR uncacheable cycles 3071system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10320500 # number of ReadReq MSHR uncacheable cycles 3072system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 728734017 # number of ReadReq MSHR uncacheable cycles 3073system.l2c.ReadReq_mshr_uncacheable_latency::total 11857408570 # number of ReadReq MSHR uncacheable cycles 3074system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5073884538 # number of WriteReq MSHR uncacheable cycles 3075system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 907395547 # number of WriteReq MSHR uncacheable cycles 3076system.l2c.WriteReq_mshr_uncacheable_latency::total 5981280085 # number of WriteReq MSHR uncacheable cycles 3077system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles 3078system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10294572591 # number of overall MSHR uncacheable cycles 3079system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10320500 # number of overall MSHR uncacheable cycles 3080system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1636129564 # number of overall MSHR uncacheable cycles 3081system.l2c.overall_mshr_uncacheable_latency::total 17838688655 # number of overall MSHR uncacheable cycles 3082system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3083system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3084system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for UpgradeReq accesses 3085system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.306052 # mshr miss rate for UpgradeReq accesses 3086system.l2c.UpgradeReq_mshr_miss_rate::total 0.290013 # mshr miss rate for UpgradeReq accesses 3087system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.237874 # mshr miss rate for SCUpgradeReq accesses 3088system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225288 # mshr miss rate for SCUpgradeReq accesses 3089system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.231817 # mshr miss rate for SCUpgradeReq accesses 3090system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.604734 # mshr miss rate for ReadExReq accesses 3091system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454062 # mshr miss rate for ReadExReq accesses 3092system.l2c.ReadExReq_mshr_miss_rate::total 0.535825 # mshr miss rate for ReadExReq accesses 3093system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for ReadSharedReq accesses 3094system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for ReadSharedReq accesses 3095system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for ReadSharedReq accesses 3096system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189967 # mshr miss rate for ReadSharedReq accesses 3097system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for ReadSharedReq accesses 3098system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for ReadSharedReq accesses 3099system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for ReadSharedReq accesses 3100system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for ReadSharedReq accesses 3101system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.145225 # mshr miss rate for ReadSharedReq accesses 3102system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for ReadSharedReq accesses 3103system.l2c.ReadSharedReq_mshr_miss_rate::total 0.200269 # mshr miss rate for ReadSharedReq accesses 3104system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779086 # mshr miss rate for InvalidateReq accesses 3105system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.408078 # mshr miss rate for InvalidateReq accesses 3106system.l2c.InvalidateReq_mshr_miss_rate::total 0.675667 # mshr miss rate for InvalidateReq accesses 3107system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for demand accesses 3108system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for demand accesses 3109system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for demand accesses 3110system.l2c.demand_mshr_miss_rate::cpu0.data 0.251652 # mshr miss rate for demand accesses 3111system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for demand accesses 3112system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for demand accesses 3113system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for demand accesses 3114system.l2c.demand_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for demand accesses 3115system.l2c.demand_mshr_miss_rate::cpu1.data 0.188212 # mshr miss rate for demand accesses 3116system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for demand accesses 3117system.l2c.demand_mshr_miss_rate::total 0.219641 # mshr miss rate for demand accesses 3118system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for overall accesses 3119system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for overall accesses 3120system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for overall accesses 3121system.l2c.overall_mshr_miss_rate::cpu0.data 0.251652 # mshr miss rate for overall accesses 3122system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for overall accesses 3123system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for overall accesses 3124system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for overall accesses 3125system.l2c.overall_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for overall accesses 3126system.l2c.overall_mshr_miss_rate::cpu1.data 0.188212 # mshr miss rate for overall accesses 3127system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for overall accesses 3128system.l2c.overall_mshr_miss_rate::total 0.219641 # mshr miss rate for overall accesses 3129system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70511.570770 # average UpgradeReq mshr miss latency 3130system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70744.197959 # average UpgradeReq mshr miss latency 3131system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70626.640641 # average UpgradeReq mshr miss latency 3132system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73589.975384 # average SCUpgradeReq mshr miss latency 3133system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73559.456325 # average SCUpgradeReq mshr miss latency 3134system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73575.702400 # average SCUpgradeReq mshr miss latency 3135system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128404.792537 # average ReadExReq mshr miss latency 3136system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123335.036761 # average ReadExReq mshr miss latency 3137system.l2c.ReadExReq_avg_mshr_miss_latency::total 126439.976478 # average ReadExReq mshr miss latency 3138system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average ReadSharedReq mshr miss latency 3139system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average ReadSharedReq mshr miss latency 3140system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average ReadSharedReq mshr miss latency 3141system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129589.310186 # average ReadSharedReq mshr miss latency 3142system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average ReadSharedReq mshr miss latency 3143system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average ReadSharedReq mshr miss latency 3144system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average ReadSharedReq mshr miss latency 3145system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average ReadSharedReq mshr miss latency 3146system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131084.361928 # average ReadSharedReq mshr miss latency 3147system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average ReadSharedReq mshr miss latency 3148system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146034.545309 # average ReadSharedReq mshr miss latency 3149system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69905.751133 # average InvalidateReq mshr miss latency 3150system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69900.131209 # average InvalidateReq mshr miss latency 3151system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69904.804990 # average InvalidateReq mshr miss latency 3152system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average overall mshr miss latency 3153system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average overall mshr miss latency 3154system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average overall mshr miss latency 3155system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129165.978772 # average overall mshr miss latency 3156system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average overall mshr miss latency 3157system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average overall mshr miss latency 3158system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average overall mshr miss latency 3159system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average overall mshr miss latency 3160system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency 3161system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency 3162system.l2c.demand_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency 3163system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average overall mshr miss latency 3164system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average overall mshr miss latency 3165system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average overall mshr miss latency 3166system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129165.978772 # average overall mshr miss latency 3167system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average overall mshr miss latency 3168system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average overall mshr miss latency 3169system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average overall mshr miss latency 3170system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average overall mshr miss latency 3171system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency 3172system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency 3173system.l2c.overall_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency 3174system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 3175system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424 # average ReadReq mshr uncacheable latency 3176system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency 3177system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency 3178system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency 3179system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753 # average WriteReq mshr uncacheable latency 3180system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002 # average WriteReq mshr uncacheable latency 3181system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836 # average WriteReq mshr uncacheable latency 3182system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 3183system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency 3184system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency 3185system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency 3186system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency 3187system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3188system.membus.trans_dist::ReadReq 91289 # Transaction distribution 3189system.membus.trans_dist::ReadResp 902614 # Transaction distribution 3190system.membus.trans_dist::WriteReq 38789 # Transaction distribution 3191system.membus.trans_dist::WriteResp 38789 # Transaction distribution 3192system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution 3193system.membus.trans_dist::CleanEvict 259673 # Transaction distribution 3194system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution 3195system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution 3196system.membus.trans_dist::UpgradeResp 22 # Transaction distribution 3197system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3198system.membus.trans_dist::ReadExReq 143483 # Transaction distribution 3199system.membus.trans_dist::ReadExResp 126149 # Transaction distribution 3200system.membus.trans_dist::ReadSharedReq 811325 # Transaction distribution 3201system.membus.trans_dist::InvalidateReq 668729 # Transaction distribution 3202system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122924 # Packet count per connected master and slave (bytes) 3203system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3204system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27208 # Packet count per connected master and slave (bytes) 3205system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4633500 # Packet count per connected master and slave (bytes) 3206system.membus.pkt_count_system.l2c.mem_side::total 4783684 # Packet count per connected master and slave (bytes) 3207system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238198 # Packet count per connected master and slave (bytes) 3208system.membus.pkt_count_system.iocache.mem_side::total 238198 # Packet count per connected master and slave (bytes) 3209system.membus.pkt_count::total 5021882 # Packet count per connected master and slave (bytes) 3210system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155939 # Cumulative packet size per connected master and slave (bytes) 3211system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3212system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54416 # Cumulative packet size per connected master and slave (bytes) 3213system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 131613504 # Cumulative packet size per connected master and slave (bytes) 3214system.membus.pkt_size_system.l2c.mem_side::total 131825183 # Cumulative packet size per connected master and slave (bytes) 3215system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257920 # Cumulative packet size per connected master and slave (bytes) 3216system.membus.pkt_size_system.iocache.mem_side::total 7257920 # Cumulative packet size per connected master and slave (bytes) 3217system.membus.pkt_size::total 139083103 # Cumulative packet size per connected master and slave (bytes) 3218system.membus.snoops 621301 # Total snoops (count) 3219system.membus.snoop_fanout::samples 3957559 # Request fanout histogram 3220system.membus.snoop_fanout::mean 1 # Request fanout histogram 3221system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3222system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3223system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3224system.membus.snoop_fanout::1 3957559 100.00% 100.00% # Request fanout histogram 3225system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3226system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3227system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3228system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3229system.membus.snoop_fanout::total 3957559 # Request fanout histogram 3230system.membus.reqLayer0.occupancy 105148497 # Layer occupancy (ticks) 3231system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3232system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3233system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3234system.membus.reqLayer2.occupancy 22946496 # Layer occupancy (ticks) 3235system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3236system.membus.reqLayer5.occupancy 8356686345 # Layer occupancy (ticks) 3237system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3238system.membus.respLayer2.occupancy 5285705581 # Layer occupancy (ticks) 3239system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3240system.membus.respLayer3.occupancy 45456154 # Layer occupancy (ticks) 3241system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3242system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3243system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3244system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3245system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3246system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3247system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3248system.realview.ethernet.txBytes 966 # Bytes Transmitted 3249system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3250system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3251system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3252system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3253system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3254system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3255system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3256system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3257system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3258system.realview.ethernet.totPackets 3 # Total Packets 3259system.realview.ethernet.totBytes 966 # Total Bytes 3260system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3261system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3262system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3263system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3264system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3265system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3266system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3267system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3268system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3269system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3270system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3271system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3272system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3273system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3274system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3275system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3276system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3277system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3278system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3279system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3280system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3281system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3282system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3283system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3284system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3285system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3286system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3287system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3288system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3289system.realview.ethernet.droppedPackets 0 # number of packets dropped 3290system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3291system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3292system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3293system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3294system.toL2Bus.snoop_filter.tot_requests 12610950 # Total number of requests made to the snoop filter. 3295system.toL2Bus.snoop_filter.hit_single_requests 6824430 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3296system.toL2Bus.snoop_filter.hit_multi_requests 2134576 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3297system.toL2Bus.snoop_filter.tot_snoops 142334 # Total number of snoops made to the snoop filter. 3298system.toL2Bus.snoop_filter.hit_single_snoops 128133 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3299system.toL2Bus.snoop_filter.hit_multi_snoops 14201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3300system.toL2Bus.trans_dist::ReadReq 91291 # Transaction distribution 3301system.toL2Bus.trans_dist::ReadResp 4901304 # Transaction distribution 3302system.toL2Bus.trans_dist::WriteReq 38789 # Transaction distribution 3303system.toL2Bus.trans_dist::WriteResp 38789 # Transaction distribution 3304system.toL2Bus.trans_dist::WritebackDirty 3987141 # Transaction distribution 3305system.toL2Bus.trans_dist::CleanEvict 3034318 # Transaction distribution 3306system.toL2Bus.trans_dist::UpgradeReq 743952 # Transaction distribution 3307system.toL2Bus.trans_dist::SCUpgradeReq 399827 # Transaction distribution 3308system.toL2Bus.trans_dist::UpgradeResp 1143779 # Transaction distribution 3309system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution 3310system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 3311system.toL2Bus.trans_dist::ReadExReq 302895 # Transaction distribution 3312system.toL2Bus.trans_dist::ReadExResp 302895 # Transaction distribution 3313system.toL2Bus.trans_dist::ReadSharedReq 4817262 # Transaction distribution 3314system.toL2Bus.trans_dist::InvalidateReq 944420 # Transaction distribution 3315system.toL2Bus.trans_dist::InvalidateResp 837436 # Transaction distribution 3316system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10209362 # Packet count per connected master and slave (bytes) 3317system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8295779 # Packet count per connected master and slave (bytes) 3318system.toL2Bus.pkt_count::total 18505141 # Packet count per connected master and slave (bytes) 3319system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250153960 # Cumulative packet size per connected master and slave (bytes) 3320system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 205145975 # Cumulative packet size per connected master and slave (bytes) 3321system.toL2Bus.pkt_size::total 455299935 # Cumulative packet size per connected master and slave (bytes) 3322system.toL2Bus.snoops 3080857 # Total snoops (count) 3323system.toL2Bus.snoop_fanout::samples 8841930 # Request fanout histogram 3324system.toL2Bus.snoop_fanout::mean 0.362342 # Request fanout histogram 3325system.toL2Bus.snoop_fanout::stdev 0.484007 # Request fanout histogram 3326system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3327system.toL2Bus.snoop_fanout::0 5652330 63.93% 63.93% # Request fanout histogram 3328system.toL2Bus.snoop_fanout::1 3175399 35.91% 99.84% # Request fanout histogram 3329system.toL2Bus.snoop_fanout::2 14201 0.16% 100.00% # Request fanout histogram 3330system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3331system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3332system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3333system.toL2Bus.snoop_fanout::total 8841930 # Request fanout histogram 3334system.toL2Bus.reqLayer0.occupancy 9598709952 # Layer occupancy (ticks) 3335system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3336system.toL2Bus.snoopLayer0.occupancy 2569910 # Layer occupancy (ticks) 3337system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3338system.toL2Bus.respLayer0.occupancy 4696248682 # Layer occupancy (ticks) 3339system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3340system.toL2Bus.respLayer1.occupancy 4118726891 # Layer occupancy (ticks) 3341system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3342 3343---------- End Simulation Statistics ---------- 3344