stats.txt revision 11376:a6968f06a5e0
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.454492 # Number of seconds simulated 4sim_ticks 47454492026000 # Number of ticks simulated 5final_tick 47454492026000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 326065 # Simulator instruction rate (inst/s) 8host_op_rate 383423 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16260643539 # Simulator tick rate (ticks/s) 10host_mem_usage 772552 # Number of bytes of host memory used 11host_seconds 2918.37 # Real time elapsed on the host 12sim_insts 951575519 # Number of instructions simulated 13sim_ops 1118968402 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 233088 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 210624 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7916672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 17537736 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 18153728 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 166400 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 132160 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3894272 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 12497872 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 21171968 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 432064 # Number of bytes read from this memory 27system.physmem.bytes_read::total 82346584 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 7916672 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3894272 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 11810944 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 92922304 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 92942888 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 3642 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 3291 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 123698 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 274040 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 283652 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2600 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2065 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 60848 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 195292 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 330812 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6751 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1286691 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1451911 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1454485 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 4912 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 4438 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 166827 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 369570 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 382550 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3507 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2785 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 82063 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 263365 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 446153 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9105 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1735275 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 166827 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 82063 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 248890 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1958135 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1958569 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1958135 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 4912 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 4438 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 166827 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 370003 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 382550 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3507 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2785 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 82063 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 263365 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 446153 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9105 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3693844 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1286691 # Number of read requests accepted 84system.physmem.writeReqs 1454485 # Number of write requests accepted 85system.physmem.readBursts 1286691 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1454485 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 82317440 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 30784 # Total number of bytes read from write queue 89system.physmem.bytesWritten 92941888 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 82346584 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 92942888 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 481 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 68545 # Per bank write bursts 96system.physmem.perBankRdBursts::1 77862 # Per bank write bursts 97system.physmem.perBankRdBursts::2 76461 # Per bank write bursts 98system.physmem.perBankRdBursts::3 81936 # Per bank write bursts 99system.physmem.perBankRdBursts::4 74664 # Per bank write bursts 100system.physmem.perBankRdBursts::5 81822 # Per bank write bursts 101system.physmem.perBankRdBursts::6 81067 # Per bank write bursts 102system.physmem.perBankRdBursts::7 83827 # Per bank write bursts 103system.physmem.perBankRdBursts::8 73756 # Per bank write bursts 104system.physmem.perBankRdBursts::9 133954 # Per bank write bursts 105system.physmem.perBankRdBursts::10 75964 # Per bank write bursts 106system.physmem.perBankRdBursts::11 77586 # Per bank write bursts 107system.physmem.perBankRdBursts::12 69247 # Per bank write bursts 108system.physmem.perBankRdBursts::13 78127 # Per bank write bursts 109system.physmem.perBankRdBursts::14 73347 # Per bank write bursts 110system.physmem.perBankRdBursts::15 78045 # Per bank write bursts 111system.physmem.perBankWrBursts::0 83788 # Per bank write bursts 112system.physmem.perBankWrBursts::1 90226 # Per bank write bursts 113system.physmem.perBankWrBursts::2 90168 # Per bank write bursts 114system.physmem.perBankWrBursts::3 95983 # Per bank write bursts 115system.physmem.perBankWrBursts::4 89513 # Per bank write bursts 116system.physmem.perBankWrBursts::5 93413 # Per bank write bursts 117system.physmem.perBankWrBursts::6 92742 # Per bank write bursts 118system.physmem.perBankWrBursts::7 93553 # Per bank write bursts 119system.physmem.perBankWrBursts::8 87937 # Per bank write bursts 120system.physmem.perBankWrBursts::9 94416 # Per bank write bursts 121system.physmem.perBankWrBursts::10 91588 # Per bank write bursts 122system.physmem.perBankWrBursts::11 94818 # Per bank write bursts 123system.physmem.perBankWrBursts::12 85405 # Per bank write bursts 124system.physmem.perBankWrBursts::13 92349 # Per bank write bursts 125system.physmem.perBankWrBursts::14 86484 # Per bank write bursts 126system.physmem.perBankWrBursts::15 89834 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 36 # Number of times write queue was full causing retry 129system.physmem.totGap 47454489913500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1286661 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1451911 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 827173 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 164897 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 63225 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 47515 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 40751 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 37481 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 33938 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 30502 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 26328 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 5741 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 2483 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1712 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1354 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 989 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 645 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 527 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 427 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 343 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 34612 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 41901 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 58265 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 63048 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 69768 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 73771 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 78937 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 85048 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 89045 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 90562 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 92833 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 96249 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 94408 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 95986 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 105469 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 93952 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 86808 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 83066 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 4836 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 2469 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1685 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1217 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 978 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 762 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 465 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 413 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 418 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 367 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 375 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 388 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 299 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 254 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 212 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 99 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1224605 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 143.114986 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 97.246112 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 190.672457 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 830563 67.82% 67.82% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 233051 19.03% 86.85% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 57759 4.72% 91.57% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 27718 2.26% 93.83% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 20623 1.68% 95.52% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 13112 1.07% 96.59% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 7173 0.59% 97.17% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 5754 0.47% 97.64% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 28852 2.36% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1224605 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 77530 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 16.589449 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 141.842916 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 77527 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 77530 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 77530 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 18.731033 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.088703 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.268543 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 64617 83.34% 83.34% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 6035 7.78% 91.13% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 3056 3.94% 95.07% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 1620 2.09% 97.16% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 474 0.61% 97.77% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 277 0.36% 98.13% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 269 0.35% 98.48% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 83 0.11% 98.58% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 290 0.37% 98.96% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 69 0.09% 99.05% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 30 0.04% 99.08% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 52 0.07% 99.15% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 249 0.32% 99.47% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 33 0.04% 99.52% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 40 0.05% 99.57% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 110 0.14% 99.71% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 167 0.22% 99.92% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::120-123 3 0.00% 99.94% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::128-131 15 0.02% 99.96% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::total 77530 # Writes before turning the bus around for reads 303system.physmem.totQLat 47048753044 # Total ticks spent queuing 304system.physmem.totMemAccLat 71165190544 # Total ticks spent from burst creation until serviced by the DRAM 305system.physmem.totBusLat 6431050000 # Total ticks spent in databus transfers 306system.physmem.avgQLat 36579.37 # Average queueing delay per DRAM burst 307system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 308system.physmem.avgMemAccLat 55329.37 # Average memory access latency per DRAM burst 309system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s 310system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s 311system.physmem.avgRdBWSys 1.74 # Average system read bandwidth in MiByte/s 312system.physmem.avgWrBWSys 1.96 # Average system write bandwidth in MiByte/s 313system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 314system.physmem.busUtil 0.03 # Data bus utilization in percentage 315system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 316system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 317system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 318system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing 319system.physmem.readRowHits 962295 # Number of row buffer hits during reads 320system.physmem.writeRowHits 551527 # Number of row buffer hits during writes 321system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads 322system.physmem.writeRowHitRate 37.98 # Row buffer hit rate for writes 323system.physmem.avgGap 17311726.76 # Average gap between requests 324system.physmem.pageHitRate 55.28 # Row buffer hit rate, read and write combined 325system.physmem_0.actEnergy 4656869280 # Energy for activate commands per rank (pJ) 326system.physmem_0.preEnergy 2540950500 # Energy for precharge commands per rank (pJ) 327system.physmem_0.readEnergy 4884235200 # Energy for read commands per rank (pJ) 328system.physmem_0.writeEnergy 4726421280 # Energy for write commands per rank (pJ) 329system.physmem_0.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) 330system.physmem_0.actBackEnergy 1219171959180 # Energy for active background per rank (pJ) 331system.physmem_0.preBackEnergy 27403246221750 # Energy for precharge background per rank (pJ) 332system.physmem_0.totalEnergy 31738723386870 # Total energy per rank (pJ) 333system.physmem_0.averagePower 668.824424 # Core power per rank (mW) 334system.physmem_0.memoryStateTime::IDLE 45587152483743 # Time in different power states 335system.physmem_0.memoryStateTime::REF 1584609520000 # Time in different power states 336system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 337system.physmem_0.memoryStateTime::ACT 282729931257 # Time in different power states 338system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 339system.physmem_1.actEnergy 4601144520 # Energy for activate commands per rank (pJ) 340system.physmem_1.preEnergy 2510545125 # Energy for precharge commands per rank (pJ) 341system.physmem_1.readEnergy 5148202800 # Energy for read commands per rank (pJ) 342system.physmem_1.writeEnergy 4683944880 # Energy for write commands per rank (pJ) 343system.physmem_1.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ) 344system.physmem_1.actBackEnergy 1221460881390 # Energy for active background per rank (pJ) 345system.physmem_1.preBackEnergy 27401238395250 # Energy for precharge background per rank (pJ) 346system.physmem_1.totalEnergy 31739139843645 # Total energy per rank (pJ) 347system.physmem_1.averagePower 668.833200 # Core power per rank (mW) 348system.physmem_1.memoryStateTime::IDLE 45583769039323 # Time in different power states 349system.physmem_1.memoryStateTime::REF 1584609520000 # Time in different power states 350system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 351system.physmem_1.memoryStateTime::ACT 286113375677 # Time in different power states 352system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 353system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 358system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 359system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 360system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 361system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 363system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 365system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 366system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 379system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 380system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 381system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 382system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 383system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 384system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 385system.cpu0.branchPred.lookups 147959066 # Number of BP lookups 386system.cpu0.branchPred.condPredicted 105493690 # Number of conditional branches predicted 387system.cpu0.branchPred.condIncorrect 6448516 # Number of conditional branches incorrect 388system.cpu0.branchPred.BTBLookups 111296242 # Number of BTB lookups 389system.cpu0.branchPred.BTBHits 81329533 # Number of BTB hits 390system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 391system.cpu0.branchPred.BTBHitPct 73.074824 # BTB Hit Percentage 392system.cpu0.branchPred.usedRAS 17161750 # Number of times the RAS was used to get a target. 393system.cpu0.branchPred.RASInCorrect 1109253 # Number of incorrect RAS predictions. 394system.cpu_clk_domain.clock 500 # Clock period in ticks 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 404system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 405system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 406system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 407system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 408system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 410system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 411system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 412system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 413system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 414system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 416system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 419system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 420system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 421system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 422system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 423system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 424system.cpu0.dtb.walker.walks 300034 # Table walker walks requested 425system.cpu0.dtb.walker.walksLong 300034 # Table walker walks initiated with long descriptors 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11904 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91094 # Level at which table walker walks with long descriptors terminate 428system.cpu0.dtb.walker.walkWaitTime::samples 300034 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::0 300034 100.00% 100.00% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::total 300034 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkCompletionTime::samples 102998 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::0-65535 100872 97.94% 97.94% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::65536-131071 180 0.17% 98.11% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1639 1.59% 99.70% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::196608-262143 73 0.07% 99.77% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::262144-327679 76 0.07% 99.85% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::327680-393215 46 0.04% 99.89% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.07% 99.96% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::458752-524287 28 0.03% 99.99% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::total 102998 # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 451system.cpu0.dtb.walker.walkPageSizes::4K 91094 88.44% 88.44% # Table walker page sizes translated 452system.cpu0.dtb.walker.walkPageSizes::2M 11904 11.56% 100.00% # Table walker page sizes translated 453system.cpu0.dtb.walker.walkPageSizes::total 102998 # Table walker page sizes translated 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 300034 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 300034 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102998 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102998 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin::total 403032 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.inst_hits 0 # ITB inst hits 462system.cpu0.dtb.inst_misses 0 # ITB inst misses 463system.cpu0.dtb.read_hits 94891169 # DTB read hits 464system.cpu0.dtb.read_misses 247198 # DTB read misses 465system.cpu0.dtb.write_hits 84318368 # DTB write hits 466system.cpu0.dtb.write_misses 52836 # DTB write misses 467system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 468system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 469system.cpu0.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 470system.cpu0.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 471system.cpu0.dtb.flush_entries 40307 # Number of entries that have been flushed from TLB 472system.cpu0.dtb.align_faults 1747 # Number of TLB faults due to alignment restrictions 473system.cpu0.dtb.prefetch_faults 9392 # Number of TLB faults due to prefetch 474system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 475system.cpu0.dtb.perms_faults 12141 # Number of TLB faults due to permissions restrictions 476system.cpu0.dtb.read_accesses 95138367 # DTB read accesses 477system.cpu0.dtb.write_accesses 84371204 # DTB write accesses 478system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 479system.cpu0.dtb.hits 179209537 # DTB hits 480system.cpu0.dtb.misses 300034 # DTB misses 481system.cpu0.dtb.accesses 179509571 # DTB accesses 482system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 491system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 492system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 493system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 494system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 495system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 496system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 499system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 500system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 501system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 502system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 503system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 504system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 505system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 506system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 507system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 508system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 509system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 510system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 511system.cpu0.itb.walker.walks 71231 # Table walker walks requested 512system.cpu0.itb.walker.walksLong 71231 # Table walker walks initiated with long descriptors 513system.cpu0.itb.walker.walksLongTerminationLevel::Level2 667 # Level at which table walker walks with long descriptors terminate 514system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60897 # Level at which table walker walks with long descriptors terminate 515system.cpu0.itb.walker.walkWaitTime::samples 71231 # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::0 71231 100.00% 100.00% # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::total 71231 # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkCompletionTime::samples 61564 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::mean 29116.975830 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::0-65535 59287 96.30% 96.30% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::65536-131071 14 0.02% 96.32% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::131072-196607 2011 3.27% 99.59% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::196608-262143 94 0.15% 99.74% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::262144-327679 85 0.14% 99.88% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::327680-393215 46 0.07% 99.96% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::total 61564 # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 533system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 534system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 535system.cpu0.itb.walker.walkPageSizes::4K 60897 98.92% 98.92% # Table walker page sizes translated 536system.cpu0.itb.walker.walkPageSizes::2M 667 1.08% 100.00% # Table walker page sizes translated 537system.cpu0.itb.walker.walkPageSizes::total 61564 # Table walker page sizes translated 538system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 539system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 71231 # Table walker requests started/completed, data/inst 540system.cpu0.itb.walker.walkRequestOrigin_Requested::total 71231 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61564 # Table walker requests started/completed, data/inst 543system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61564 # Table walker requests started/completed, data/inst 544system.cpu0.itb.walker.walkRequestOrigin::total 132795 # Table walker requests started/completed, data/inst 545system.cpu0.itb.inst_hits 264582301 # ITB inst hits 546system.cpu0.itb.inst_misses 71231 # ITB inst misses 547system.cpu0.itb.read_hits 0 # DTB read hits 548system.cpu0.itb.read_misses 0 # DTB read misses 549system.cpu0.itb.write_hits 0 # DTB write hits 550system.cpu0.itb.write_misses 0 # DTB write misses 551system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 552system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 553system.cpu0.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 554system.cpu0.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 555system.cpu0.itb.flush_entries 28772 # Number of entries that have been flushed from TLB 556system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 557system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 558system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 559system.cpu0.itb.perms_faults 223649 # Number of TLB faults due to permissions restrictions 560system.cpu0.itb.read_accesses 0 # DTB read accesses 561system.cpu0.itb.write_accesses 0 # DTB write accesses 562system.cpu0.itb.inst_accesses 264653532 # ITB inst accesses 563system.cpu0.itb.hits 264582301 # DTB hits 564system.cpu0.itb.misses 71231 # DTB misses 565system.cpu0.itb.accesses 264653532 # DTB accesses 566system.cpu0.numCycles 1106984671 # number of cpu cycles simulated 567system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 568system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 569system.cpu0.committedInsts 488099503 # Number of instructions committed 570system.cpu0.committedOps 574418730 # Number of ops (including micro ops) committed 571system.cpu0.discardedOps 50785821 # Number of ops (including micro ops) which were discarded before commit 572system.cpu0.numFetchSuspends 5453 # Number of times Execute suspended instruction fetching 573system.cpu0.quiesceCycles 93802885102 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 574system.cpu0.cpi 2.267949 # CPI: cycles per instruction 575system.cpu0.ipc 0.440927 # IPC: instructions per cycle 576system.cpu0.kern.inst.arm 0 # number of arm instructions executed 577system.cpu0.kern.inst.quiesce 5643 # number of quiesce instructions executed 578system.cpu0.tickCycles 789747765 # Number of cycles that the object actually ticked 579system.cpu0.idleCycles 317236906 # Total number of cycles that the object has spent stopped 580system.cpu0.dcache.tags.replacements 6140209 # number of replacements 581system.cpu0.dcache.tags.tagsinuse 501.783411 # Cycle average of tags in use 582system.cpu0.dcache.tags.total_refs 169967706 # Total number of references to valid blocks. 583system.cpu0.dcache.tags.sampled_refs 6140721 # Sample count of references to valid blocks. 584system.cpu0.dcache.tags.avg_refs 27.678787 # Average number of references to valid blocks. 585system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 586system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.783411 # Average occupied blocks per requestor 587system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980046 # Average percentage of cache occupancy 588system.cpu0.dcache.tags.occ_percent::total 0.980046 # Average percentage of cache occupancy 589system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 590system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 591system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id 592system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 593system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 594system.cpu0.dcache.tags.tag_accesses 361643482 # Number of tag accesses 595system.cpu0.dcache.tags.data_accesses 361643482 # Number of data accesses 596system.cpu0.dcache.ReadReq_hits::cpu0.data 86800691 # number of ReadReq hits 597system.cpu0.dcache.ReadReq_hits::total 86800691 # number of ReadReq hits 598system.cpu0.dcache.WriteReq_hits::cpu0.data 78258675 # number of WriteReq hits 599system.cpu0.dcache.WriteReq_hits::total 78258675 # number of WriteReq hits 600system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268918 # number of SoftPFReq hits 601system.cpu0.dcache.SoftPFReq_hits::total 268918 # number of SoftPFReq hits 602system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127943 # number of WriteLineReq hits 603system.cpu0.dcache.WriteLineReq_hits::total 127943 # number of WriteLineReq hits 604system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1971519 # number of LoadLockedReq hits 605system.cpu0.dcache.LoadLockedReq_hits::total 1971519 # number of LoadLockedReq hits 606system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1943002 # number of StoreCondReq hits 607system.cpu0.dcache.StoreCondReq_hits::total 1943002 # number of StoreCondReq hits 608system.cpu0.dcache.demand_hits::cpu0.data 165059366 # number of demand (read+write) hits 609system.cpu0.dcache.demand_hits::total 165059366 # number of demand (read+write) hits 610system.cpu0.dcache.overall_hits::cpu0.data 165328284 # number of overall hits 611system.cpu0.dcache.overall_hits::total 165328284 # number of overall hits 612system.cpu0.dcache.ReadReq_misses::cpu0.data 3776237 # number of ReadReq misses 613system.cpu0.dcache.ReadReq_misses::total 3776237 # number of ReadReq misses 614system.cpu0.dcache.WriteReq_misses::cpu0.data 2642039 # number of WriteReq misses 615system.cpu0.dcache.WriteReq_misses::total 2642039 # number of WriteReq misses 616system.cpu0.dcache.SoftPFReq_misses::cpu0.data 748095 # number of SoftPFReq misses 617system.cpu0.dcache.SoftPFReq_misses::total 748095 # number of SoftPFReq misses 618system.cpu0.dcache.WriteLineReq_misses::cpu0.data 774634 # number of WriteLineReq misses 619system.cpu0.dcache.WriteLineReq_misses::total 774634 # number of WriteLineReq misses 620system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 182353 # number of LoadLockedReq misses 621system.cpu0.dcache.LoadLockedReq_misses::total 182353 # number of LoadLockedReq misses 622system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209431 # number of StoreCondReq misses 623system.cpu0.dcache.StoreCondReq_misses::total 209431 # number of StoreCondReq misses 624system.cpu0.dcache.demand_misses::cpu0.data 6418276 # number of demand (read+write) misses 625system.cpu0.dcache.demand_misses::total 6418276 # number of demand (read+write) misses 626system.cpu0.dcache.overall_misses::cpu0.data 7166371 # number of overall misses 627system.cpu0.dcache.overall_misses::total 7166371 # number of overall misses 628system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 71342778500 # number of ReadReq miss cycles 629system.cpu0.dcache.ReadReq_miss_latency::total 71342778500 # number of ReadReq miss cycles 630system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67996340500 # number of WriteReq miss cycles 631system.cpu0.dcache.WriteReq_miss_latency::total 67996340500 # number of WriteReq miss cycles 632system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46419090000 # number of WriteLineReq miss cycles 633system.cpu0.dcache.WriteLineReq_miss_latency::total 46419090000 # number of WriteLineReq miss cycles 634system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3111811500 # number of LoadLockedReq miss cycles 635system.cpu0.dcache.LoadLockedReq_miss_latency::total 3111811500 # number of LoadLockedReq miss cycles 636system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5902963500 # number of StoreCondReq miss cycles 637system.cpu0.dcache.StoreCondReq_miss_latency::total 5902963500 # number of StoreCondReq miss cycles 638system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7077000 # number of StoreCondFailReq miss cycles 639system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7077000 # number of StoreCondFailReq miss cycles 640system.cpu0.dcache.demand_miss_latency::cpu0.data 139339119000 # number of demand (read+write) miss cycles 641system.cpu0.dcache.demand_miss_latency::total 139339119000 # number of demand (read+write) miss cycles 642system.cpu0.dcache.overall_miss_latency::cpu0.data 139339119000 # number of overall miss cycles 643system.cpu0.dcache.overall_miss_latency::total 139339119000 # number of overall miss cycles 644system.cpu0.dcache.ReadReq_accesses::cpu0.data 90576928 # number of ReadReq accesses(hits+misses) 645system.cpu0.dcache.ReadReq_accesses::total 90576928 # number of ReadReq accesses(hits+misses) 646system.cpu0.dcache.WriteReq_accesses::cpu0.data 80900714 # number of WriteReq accesses(hits+misses) 647system.cpu0.dcache.WriteReq_accesses::total 80900714 # number of WriteReq accesses(hits+misses) 648system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1017013 # number of SoftPFReq accesses(hits+misses) 649system.cpu0.dcache.SoftPFReq_accesses::total 1017013 # number of SoftPFReq accesses(hits+misses) 650system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 902577 # number of WriteLineReq accesses(hits+misses) 651system.cpu0.dcache.WriteLineReq_accesses::total 902577 # number of WriteLineReq accesses(hits+misses) 652system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2153872 # number of LoadLockedReq accesses(hits+misses) 653system.cpu0.dcache.LoadLockedReq_accesses::total 2153872 # number of LoadLockedReq accesses(hits+misses) 654system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2152433 # number of StoreCondReq accesses(hits+misses) 655system.cpu0.dcache.StoreCondReq_accesses::total 2152433 # number of StoreCondReq accesses(hits+misses) 656system.cpu0.dcache.demand_accesses::cpu0.data 171477642 # number of demand (read+write) accesses 657system.cpu0.dcache.demand_accesses::total 171477642 # number of demand (read+write) accesses 658system.cpu0.dcache.overall_accesses::cpu0.data 172494655 # number of overall (read+write) accesses 659system.cpu0.dcache.overall_accesses::total 172494655 # number of overall (read+write) accesses 660system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041691 # miss rate for ReadReq accesses 661system.cpu0.dcache.ReadReq_miss_rate::total 0.041691 # miss rate for ReadReq accesses 662system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032658 # miss rate for WriteReq accesses 663system.cpu0.dcache.WriteReq_miss_rate::total 0.032658 # miss rate for WriteReq accesses 664system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.735581 # miss rate for SoftPFReq accesses 665system.cpu0.dcache.SoftPFReq_miss_rate::total 0.735581 # miss rate for SoftPFReq accesses 666system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858247 # miss rate for WriteLineReq accesses 667system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858247 # miss rate for WriteLineReq accesses 668system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084663 # miss rate for LoadLockedReq accesses 669system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084663 # miss rate for LoadLockedReq accesses 670system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097300 # miss rate for StoreCondReq accesses 671system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097300 # miss rate for StoreCondReq accesses 672system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037429 # miss rate for demand accesses 673system.cpu0.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses 674system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041545 # miss rate for overall accesses 675system.cpu0.dcache.overall_miss_rate::total 0.041545 # miss rate for overall accesses 676system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18892.558518 # average ReadReq miss latency 677system.cpu0.dcache.ReadReq_avg_miss_latency::total 18892.558518 # average ReadReq miss latency 678system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25736.312182 # average WriteReq miss latency 679system.cpu0.dcache.WriteReq_avg_miss_latency::total 25736.312182 # average WriteReq miss latency 680system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59923.899545 # average WriteLineReq miss latency 681system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59923.899545 # average WriteLineReq miss latency 682system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17064.767237 # average LoadLockedReq miss latency 683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17064.767237 # average LoadLockedReq miss latency 684system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28185.719879 # average StoreCondReq miss latency 685system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28185.719879 # average StoreCondReq miss latency 686system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 688system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21709.742460 # average overall miss latency 689system.cpu0.dcache.demand_avg_miss_latency::total 21709.742460 # average overall miss latency 690system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19443.469924 # average overall miss latency 691system.cpu0.dcache.overall_avg_miss_latency::total 19443.469924 # average overall miss latency 692system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 693system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 695system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 696system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 697system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 698system.cpu0.dcache.fast_writes 0 # number of fast writes performed 699system.cpu0.dcache.cache_copies 0 # number of cache copies performed 700system.cpu0.dcache.writebacks::writebacks 6140232 # number of writebacks 701system.cpu0.dcache.writebacks::total 6140232 # number of writebacks 702system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 470815 # number of ReadReq MSHR hits 703system.cpu0.dcache.ReadReq_mshr_hits::total 470815 # number of ReadReq MSHR hits 704system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1099674 # number of WriteReq MSHR hits 705system.cpu0.dcache.WriteReq_mshr_hits::total 1099674 # number of WriteReq MSHR hits 706system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 78 # number of WriteLineReq MSHR hits 707system.cpu0.dcache.WriteLineReq_mshr_hits::total 78 # number of WriteLineReq MSHR hits 708system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45572 # number of LoadLockedReq MSHR hits 709system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45572 # number of LoadLockedReq MSHR hits 710system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 53 # number of StoreCondReq MSHR hits 711system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits 712system.cpu0.dcache.demand_mshr_hits::cpu0.data 1570489 # number of demand (read+write) MSHR hits 713system.cpu0.dcache.demand_mshr_hits::total 1570489 # number of demand (read+write) MSHR hits 714system.cpu0.dcache.overall_mshr_hits::cpu0.data 1570489 # number of overall MSHR hits 715system.cpu0.dcache.overall_mshr_hits::total 1570489 # number of overall MSHR hits 716system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3305422 # number of ReadReq MSHR misses 717system.cpu0.dcache.ReadReq_mshr_misses::total 3305422 # number of ReadReq MSHR misses 718system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1542365 # number of WriteReq MSHR misses 719system.cpu0.dcache.WriteReq_mshr_misses::total 1542365 # number of WriteReq MSHR misses 720system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 746538 # number of SoftPFReq MSHR misses 721system.cpu0.dcache.SoftPFReq_mshr_misses::total 746538 # number of SoftPFReq MSHR misses 722system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 774556 # number of WriteLineReq MSHR misses 723system.cpu0.dcache.WriteLineReq_mshr_misses::total 774556 # number of WriteLineReq MSHR misses 724system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136781 # number of LoadLockedReq MSHR misses 725system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136781 # number of LoadLockedReq MSHR misses 726system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209378 # number of StoreCondReq MSHR misses 727system.cpu0.dcache.StoreCondReq_mshr_misses::total 209378 # number of StoreCondReq MSHR misses 728system.cpu0.dcache.demand_mshr_misses::cpu0.data 4847787 # number of demand (read+write) MSHR misses 729system.cpu0.dcache.demand_mshr_misses::total 4847787 # number of demand (read+write) MSHR misses 730system.cpu0.dcache.overall_mshr_misses::cpu0.data 5594325 # number of overall MSHR misses 731system.cpu0.dcache.overall_mshr_misses::total 5594325 # number of overall MSHR misses 732system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15086 # number of ReadReq MSHR uncacheable 733system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15086 # number of ReadReq MSHR uncacheable 734system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable 735system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15976 # number of WriteReq MSHR uncacheable 736system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses 737system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31062 # number of overall MSHR uncacheable misses 738system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56024435500 # number of ReadReq MSHR miss cycles 739system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56024435500 # number of ReadReq MSHR miss cycles 740system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39191815000 # number of WriteReq MSHR miss cycles 741system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39191815000 # number of WriteReq MSHR miss cycles 742system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 20208395000 # number of SoftPFReq MSHR miss cycles 743system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20208395000 # number of SoftPFReq MSHR miss cycles 744system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45637665000 # number of WriteLineReq MSHR miss cycles 745system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45637665000 # number of WriteLineReq MSHR miss cycles 746system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2043982500 # number of LoadLockedReq MSHR miss cycles 747system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2043982500 # number of LoadLockedReq MSHR miss cycles 748system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5689319500 # number of StoreCondReq MSHR miss cycles 749system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5689319500 # number of StoreCondReq MSHR miss cycles 750system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6788500 # number of StoreCondFailReq MSHR miss cycles 751system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6788500 # number of StoreCondFailReq MSHR miss cycles 752system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95216250500 # number of demand (read+write) MSHR miss cycles 753system.cpu0.dcache.demand_mshr_miss_latency::total 95216250500 # number of demand (read+write) MSHR miss cycles 754system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115424645500 # number of overall MSHR miss cycles 755system.cpu0.dcache.overall_mshr_miss_latency::total 115424645500 # number of overall MSHR miss cycles 756system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2640339000 # number of ReadReq MSHR uncacheable cycles 757system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2640339000 # number of ReadReq MSHR uncacheable cycles 758system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2747173500 # number of WriteReq MSHR uncacheable cycles 759system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2747173500 # number of WriteReq MSHR uncacheable cycles 760system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5387512500 # number of overall MSHR uncacheable cycles 761system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5387512500 # number of overall MSHR uncacheable cycles 762system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036493 # mshr miss rate for ReadReq accesses 763system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses 764system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019065 # mshr miss rate for WriteReq accesses 765system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019065 # mshr miss rate for WriteReq accesses 766system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.734050 # mshr miss rate for SoftPFReq accesses 767system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.734050 # mshr miss rate for SoftPFReq accesses 768system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858161 # mshr miss rate for WriteLineReq accesses 769system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858161 # mshr miss rate for WriteLineReq accesses 770system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063505 # mshr miss rate for LoadLockedReq accesses 771system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063505 # mshr miss rate for LoadLockedReq accesses 772system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097275 # mshr miss rate for StoreCondReq accesses 773system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097275 # mshr miss rate for StoreCondReq accesses 774system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028271 # mshr miss rate for demand accesses 775system.cpu0.dcache.demand_mshr_miss_rate::total 0.028271 # mshr miss rate for demand accesses 776system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032432 # mshr miss rate for overall accesses 777system.cpu0.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses 778system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16949.253530 # average ReadReq mshr miss latency 779system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16949.253530 # average ReadReq mshr miss latency 780system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25410.207701 # average WriteReq mshr miss latency 781system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25410.207701 # average WriteReq mshr miss latency 782system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27069.479384 # average SoftPFReq mshr miss latency 783system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27069.479384 # average SoftPFReq mshr miss latency 784system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58921.065746 # average WriteLineReq mshr miss latency 785system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58921.065746 # average WriteLineReq mshr miss latency 786system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14943.468026 # average LoadLockedReq mshr miss latency 787system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14943.468026 # average LoadLockedReq mshr miss latency 788system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27172.479917 # average StoreCondReq mshr miss latency 789system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27172.479917 # average StoreCondReq mshr miss latency 790system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 791system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 792system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19641.178645 # average overall mshr miss latency 793system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19641.178645 # average overall mshr miss latency 794system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20632.452619 # average overall mshr miss latency 795system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20632.452619 # average overall mshr miss latency 796system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175019.156834 # average ReadReq mshr uncacheable latency 797system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175019.156834 # average ReadReq mshr uncacheable latency 798system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171956.278167 # average WriteReq mshr uncacheable latency 799system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171956.278167 # average WriteReq mshr uncacheable latency 800system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173443.838130 # average overall mshr uncacheable latency 801system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173443.838130 # average overall mshr uncacheable latency 802system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 803system.cpu0.icache.tags.replacements 9845680 # number of replacements 804system.cpu0.icache.tags.tagsinuse 511.897003 # Cycle average of tags in use 805system.cpu0.icache.tags.total_refs 254505668 # Total number of references to valid blocks. 806system.cpu0.icache.tags.sampled_refs 9846192 # Sample count of references to valid blocks. 807system.cpu0.icache.tags.avg_refs 25.848132 # Average number of references to valid blocks. 808system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit. 809system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897003 # Average occupied blocks per requestor 810system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy 811system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy 812system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 813system.cpu0.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 814system.cpu0.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 815system.cpu0.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id 816system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 817system.cpu0.icache.tags.tag_accesses 538549912 # Number of tag accesses 818system.cpu0.icache.tags.data_accesses 538549912 # Number of data accesses 819system.cpu0.icache.ReadReq_hits::cpu0.inst 254505668 # number of ReadReq hits 820system.cpu0.icache.ReadReq_hits::total 254505668 # number of ReadReq hits 821system.cpu0.icache.demand_hits::cpu0.inst 254505668 # number of demand (read+write) hits 822system.cpu0.icache.demand_hits::total 254505668 # number of demand (read+write) hits 823system.cpu0.icache.overall_hits::cpu0.inst 254505668 # number of overall hits 824system.cpu0.icache.overall_hits::total 254505668 # number of overall hits 825system.cpu0.icache.ReadReq_misses::cpu0.inst 9846192 # number of ReadReq misses 826system.cpu0.icache.ReadReq_misses::total 9846192 # number of ReadReq misses 827system.cpu0.icache.demand_misses::cpu0.inst 9846192 # number of demand (read+write) misses 828system.cpu0.icache.demand_misses::total 9846192 # number of demand (read+write) misses 829system.cpu0.icache.overall_misses::cpu0.inst 9846192 # number of overall misses 830system.cpu0.icache.overall_misses::total 9846192 # number of overall misses 831system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104168962000 # number of ReadReq miss cycles 832system.cpu0.icache.ReadReq_miss_latency::total 104168962000 # number of ReadReq miss cycles 833system.cpu0.icache.demand_miss_latency::cpu0.inst 104168962000 # number of demand (read+write) miss cycles 834system.cpu0.icache.demand_miss_latency::total 104168962000 # number of demand (read+write) miss cycles 835system.cpu0.icache.overall_miss_latency::cpu0.inst 104168962000 # number of overall miss cycles 836system.cpu0.icache.overall_miss_latency::total 104168962000 # number of overall miss cycles 837system.cpu0.icache.ReadReq_accesses::cpu0.inst 264351860 # number of ReadReq accesses(hits+misses) 838system.cpu0.icache.ReadReq_accesses::total 264351860 # number of ReadReq accesses(hits+misses) 839system.cpu0.icache.demand_accesses::cpu0.inst 264351860 # number of demand (read+write) accesses 840system.cpu0.icache.demand_accesses::total 264351860 # number of demand (read+write) accesses 841system.cpu0.icache.overall_accesses::cpu0.inst 264351860 # number of overall (read+write) accesses 842system.cpu0.icache.overall_accesses::total 264351860 # number of overall (read+write) accesses 843system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037247 # miss rate for ReadReq accesses 844system.cpu0.icache.ReadReq_miss_rate::total 0.037247 # miss rate for ReadReq accesses 845system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037247 # miss rate for demand accesses 846system.cpu0.icache.demand_miss_rate::total 0.037247 # miss rate for demand accesses 847system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037247 # miss rate for overall accesses 848system.cpu0.icache.overall_miss_rate::total 0.037247 # miss rate for overall accesses 849system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10579.619207 # average ReadReq miss latency 850system.cpu0.icache.ReadReq_avg_miss_latency::total 10579.619207 # average ReadReq miss latency 851system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency 852system.cpu0.icache.demand_avg_miss_latency::total 10579.619207 # average overall miss latency 853system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10579.619207 # average overall miss latency 854system.cpu0.icache.overall_avg_miss_latency::total 10579.619207 # average overall miss latency 855system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 856system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 857system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 858system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 859system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 860system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 861system.cpu0.icache.fast_writes 0 # number of fast writes performed 862system.cpu0.icache.cache_copies 0 # number of cache copies performed 863system.cpu0.icache.writebacks::writebacks 9845680 # number of writebacks 864system.cpu0.icache.writebacks::total 9845680 # number of writebacks 865system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9846192 # number of ReadReq MSHR misses 866system.cpu0.icache.ReadReq_mshr_misses::total 9846192 # number of ReadReq MSHR misses 867system.cpu0.icache.demand_mshr_misses::cpu0.inst 9846192 # number of demand (read+write) MSHR misses 868system.cpu0.icache.demand_mshr_misses::total 9846192 # number of demand (read+write) MSHR misses 869system.cpu0.icache.overall_mshr_misses::cpu0.inst 9846192 # number of overall MSHR misses 870system.cpu0.icache.overall_mshr_misses::total 9846192 # number of overall MSHR misses 871system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 872system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 873system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 874system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 875system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99245866000 # number of ReadReq MSHR miss cycles 876system.cpu0.icache.ReadReq_mshr_miss_latency::total 99245866000 # number of ReadReq MSHR miss cycles 877system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99245866000 # number of demand (read+write) MSHR miss cycles 878system.cpu0.icache.demand_mshr_miss_latency::total 99245866000 # number of demand (read+write) MSHR miss cycles 879system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99245866000 # number of overall MSHR miss cycles 880system.cpu0.icache.overall_mshr_miss_latency::total 99245866000 # number of overall MSHR miss cycles 881system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 882system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 883system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 884system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 885system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for ReadReq accesses 886system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037247 # mshr miss rate for ReadReq accesses 887system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for demand accesses 888system.cpu0.icache.demand_mshr_miss_rate::total 0.037247 # mshr miss rate for demand accesses 889system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037247 # mshr miss rate for overall accesses 890system.cpu0.icache.overall_mshr_miss_rate::total 0.037247 # mshr miss rate for overall accesses 891system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average ReadReq mshr miss latency 892system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10079.619207 # average ReadReq mshr miss latency 893system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency 894system.cpu0.icache.demand_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency 895system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10079.619207 # average overall mshr miss latency 896system.cpu0.icache.overall_avg_mshr_miss_latency::total 10079.619207 # average overall mshr miss latency 897system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 898system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 899system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 900system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 901system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 902system.cpu0.l2cache.prefetcher.num_hwpf_issued 8550248 # number of hwpf issued 903system.cpu0.l2cache.prefetcher.pfIdentified 8550537 # number of prefetch candidates identified 904system.cpu0.l2cache.prefetcher.pfBufferHit 256 # number of redundant prefetches already in prefetch queue 905system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 906system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 907system.cpu0.l2cache.prefetcher.pfSpanPage 1111887 # number of prefetches not generated due to page crossing 908system.cpu0.l2cache.tags.replacements 3055162 # number of replacements 909system.cpu0.l2cache.tags.tagsinuse 16188.315469 # Cycle average of tags in use 910system.cpu0.l2cache.tags.total_refs 24712613 # Total number of references to valid blocks. 911system.cpu0.l2cache.tags.sampled_refs 3070855 # Sample count of references to valid blocks. 912system.cpu0.l2cache.tags.avg_refs 8.047470 # Average number of references to valid blocks. 913system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. 914system.cpu0.l2cache.tags.occ_blocks::writebacks 15276.749771 # Average occupied blocks per requestor 915system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.374129 # Average occupied blocks per requestor 916system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.193370 # Average occupied blocks per requestor 917system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 786.998198 # Average occupied blocks per requestor 918system.cpu0.l2cache.tags.occ_percent::writebacks 0.932419 # Average percentage of cache occupancy 919system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003868 # Average percentage of cache occupancy 920system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003735 # Average percentage of cache occupancy 921system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048035 # Average percentage of cache occupancy 922system.cpu0.l2cache.tags.occ_percent::total 0.988056 # Average percentage of cache occupancy 923system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1100 # Occupied blocks per task id 924system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id 925system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14511 # Occupied blocks per task id 926system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id 927system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id 928system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 849 # Occupied blocks per task id 929system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id 930system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5451 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id 938system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067139 # Percentage of cache occupancy per task id 939system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id 940system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885681 # Percentage of cache occupancy per task id 941system.cpu0.l2cache.tags.tag_accesses 539634613 # Number of tag accesses 942system.cpu0.l2cache.tags.data_accesses 539634613 # Number of data accesses 943system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 571667 # number of ReadReq hits 944system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 182910 # number of ReadReq hits 945system.cpu0.l2cache.ReadReq_hits::total 754577 # number of ReadReq hits 946system.cpu0.l2cache.WritebackDirty_hits::writebacks 4024953 # number of WritebackDirty hits 947system.cpu0.l2cache.WritebackDirty_hits::total 4024953 # number of WritebackDirty hits 948system.cpu0.l2cache.WritebackClean_hits::writebacks 11958375 # number of WritebackClean hits 949system.cpu0.l2cache.WritebackClean_hits::total 11958375 # number of WritebackClean hits 950system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 880 # number of UpgradeReq hits 951system.cpu0.l2cache.UpgradeReq_hits::total 880 # number of UpgradeReq hits 952system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits 953system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 954system.cpu0.l2cache.ReadExReq_hits::cpu0.data 964239 # number of ReadExReq hits 955system.cpu0.l2cache.ReadExReq_hits::total 964239 # number of ReadExReq hits 956system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9075218 # number of ReadCleanReq hits 957system.cpu0.l2cache.ReadCleanReq_hits::total 9075218 # number of ReadCleanReq hits 958system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3054625 # number of ReadSharedReq hits 959system.cpu0.l2cache.ReadSharedReq_hits::total 3054625 # number of ReadSharedReq hits 960system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 195729 # number of InvalidateReq hits 961system.cpu0.l2cache.InvalidateReq_hits::total 195729 # number of InvalidateReq hits 962system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 571667 # number of demand (read+write) hits 963system.cpu0.l2cache.demand_hits::cpu0.itb.walker 182910 # number of demand (read+write) hits 964system.cpu0.l2cache.demand_hits::cpu0.inst 9075218 # number of demand (read+write) hits 965system.cpu0.l2cache.demand_hits::cpu0.data 4018864 # number of demand (read+write) hits 966system.cpu0.l2cache.demand_hits::total 13848659 # number of demand (read+write) hits 967system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 571667 # number of overall hits 968system.cpu0.l2cache.overall_hits::cpu0.itb.walker 182910 # number of overall hits 969system.cpu0.l2cache.overall_hits::cpu0.inst 9075218 # number of overall hits 970system.cpu0.l2cache.overall_hits::cpu0.data 4018864 # number of overall hits 971system.cpu0.l2cache.overall_hits::total 13848659 # number of overall hits 972system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14134 # number of ReadReq misses 973system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10093 # number of ReadReq misses 974system.cpu0.l2cache.ReadReq_misses::total 24227 # number of ReadReq misses 975system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 976system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 977system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 274802 # number of UpgradeReq misses 978system.cpu0.l2cache.UpgradeReq_misses::total 274802 # number of UpgradeReq misses 979system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 209364 # number of SCUpgradeReq misses 980system.cpu0.l2cache.SCUpgradeReq_misses::total 209364 # number of SCUpgradeReq misses 981system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses 982system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 983system.cpu0.l2cache.ReadExReq_misses::cpu0.data 311346 # number of ReadExReq misses 984system.cpu0.l2cache.ReadExReq_misses::total 311346 # number of ReadExReq misses 985system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 770973 # number of ReadCleanReq misses 986system.cpu0.l2cache.ReadCleanReq_misses::total 770973 # number of ReadCleanReq misses 987system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1133829 # number of ReadSharedReq misses 988system.cpu0.l2cache.ReadSharedReq_misses::total 1133829 # number of ReadSharedReq misses 989system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 576566 # number of InvalidateReq misses 990system.cpu0.l2cache.InvalidateReq_misses::total 576566 # number of InvalidateReq misses 991system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14134 # number of demand (read+write) misses 992system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10093 # number of demand (read+write) misses 993system.cpu0.l2cache.demand_misses::cpu0.inst 770973 # number of demand (read+write) misses 994system.cpu0.l2cache.demand_misses::cpu0.data 1445175 # number of demand (read+write) misses 995system.cpu0.l2cache.demand_misses::total 2240375 # number of demand (read+write) misses 996system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14134 # number of overall misses 997system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10093 # number of overall misses 998system.cpu0.l2cache.overall_misses::cpu0.inst 770973 # number of overall misses 999system.cpu0.l2cache.overall_misses::cpu0.data 1445175 # number of overall misses 1000system.cpu0.l2cache.overall_misses::total 2240375 # number of overall misses 1001system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 807748500 # number of ReadReq miss cycles 1002system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 660476500 # number of ReadReq miss cycles 1003system.cpu0.l2cache.ReadReq_miss_latency::total 1468225000 # number of ReadReq miss cycles 1004system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3585176500 # number of UpgradeReq miss cycles 1005system.cpu0.l2cache.UpgradeReq_miss_latency::total 3585176500 # number of UpgradeReq miss cycles 1006system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2077487000 # number of SCUpgradeReq miss cycles 1007system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2077487000 # number of SCUpgradeReq miss cycles 1008system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6654497 # number of SCUpgradeFailReq miss cycles 1009system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6654497 # number of SCUpgradeFailReq miss cycles 1010system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 20598931500 # number of ReadExReq miss cycles 1011system.cpu0.l2cache.ReadExReq_miss_latency::total 20598931500 # number of ReadExReq miss cycles 1012system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29674847500 # number of ReadCleanReq miss cycles 1013system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29674847500 # number of ReadCleanReq miss cycles 1014system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 51821822989 # number of ReadSharedReq miss cycles 1015system.cpu0.l2cache.ReadSharedReq_miss_latency::total 51821822989 # number of ReadSharedReq miss cycles 1016system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 441045000 # number of InvalidateReq miss cycles 1017system.cpu0.l2cache.InvalidateReq_miss_latency::total 441045000 # number of InvalidateReq miss cycles 1018system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 807748500 # number of demand (read+write) miss cycles 1019system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 660476500 # number of demand (read+write) miss cycles 1020system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29674847500 # number of demand (read+write) miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.data 72420754489 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::total 103563826989 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 807748500 # number of overall miss cycles 1024system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 660476500 # number of overall miss cycles 1025system.cpu0.l2cache.overall_miss_latency::cpu0.inst 29674847500 # number of overall miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.data 72420754489 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::total 103563826989 # number of overall miss cycles 1028system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 585801 # number of ReadReq accesses(hits+misses) 1029system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 193003 # number of ReadReq accesses(hits+misses) 1030system.cpu0.l2cache.ReadReq_accesses::total 778804 # number of ReadReq accesses(hits+misses) 1031system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4024954 # number of WritebackDirty accesses(hits+misses) 1032system.cpu0.l2cache.WritebackDirty_accesses::total 4024954 # number of WritebackDirty accesses(hits+misses) 1033system.cpu0.l2cache.WritebackClean_accesses::writebacks 11958375 # number of WritebackClean accesses(hits+misses) 1034system.cpu0.l2cache.WritebackClean_accesses::total 11958375 # number of WritebackClean accesses(hits+misses) 1035system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 275682 # number of UpgradeReq accesses(hits+misses) 1036system.cpu0.l2cache.UpgradeReq_accesses::total 275682 # number of UpgradeReq accesses(hits+misses) 1037system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 209367 # number of SCUpgradeReq accesses(hits+misses) 1038system.cpu0.l2cache.SCUpgradeReq_accesses::total 209367 # number of SCUpgradeReq accesses(hits+misses) 1039system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 1040system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 1041system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1275585 # number of ReadExReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadExReq_accesses::total 1275585 # number of ReadExReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9846191 # number of ReadCleanReq accesses(hits+misses) 1044system.cpu0.l2cache.ReadCleanReq_accesses::total 9846191 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4188454 # number of ReadSharedReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadSharedReq_accesses::total 4188454 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 772295 # number of InvalidateReq accesses(hits+misses) 1048system.cpu0.l2cache.InvalidateReq_accesses::total 772295 # number of InvalidateReq accesses(hits+misses) 1049system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 585801 # number of demand (read+write) accesses 1050system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 193003 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::cpu0.inst 9846191 # number of demand (read+write) accesses 1052system.cpu0.l2cache.demand_accesses::cpu0.data 5464039 # number of demand (read+write) accesses 1053system.cpu0.l2cache.demand_accesses::total 16089034 # number of demand (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 585801 # number of overall (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 193003 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::cpu0.inst 9846191 # number of overall (read+write) accesses 1057system.cpu0.l2cache.overall_accesses::cpu0.data 5464039 # number of overall (read+write) accesses 1058system.cpu0.l2cache.overall_accesses::total 16089034 # number of overall (read+write) accesses 1059system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for ReadReq accesses 1060system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052295 # miss rate for ReadReq accesses 1061system.cpu0.l2cache.ReadReq_miss_rate::total 0.031108 # miss rate for ReadReq accesses 1062system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 1063system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 1064system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996808 # miss rate for UpgradeReq accesses 1065system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996808 # miss rate for UpgradeReq accesses 1066system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999986 # miss rate for SCUpgradeReq accesses 1067system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999986 # miss rate for SCUpgradeReq accesses 1068system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1069system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1070system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.244081 # miss rate for ReadExReq accesses 1071system.cpu0.l2cache.ReadExReq_miss_rate::total 0.244081 # miss rate for ReadExReq accesses 1072system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.078302 # miss rate for ReadCleanReq accesses 1073system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.078302 # miss rate for ReadCleanReq accesses 1074system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270703 # miss rate for ReadSharedReq accesses 1075system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270703 # miss rate for ReadSharedReq accesses 1076system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.746562 # miss rate for InvalidateReq accesses 1077system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.746562 # miss rate for InvalidateReq accesses 1078system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for demand accesses 1079system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052295 # miss rate for demand accesses 1080system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078302 # miss rate for demand accesses 1081system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264488 # miss rate for demand accesses 1082system.cpu0.l2cache.demand_miss_rate::total 0.139249 # miss rate for demand accesses 1083system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024128 # miss rate for overall accesses 1084system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052295 # miss rate for overall accesses 1085system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078302 # miss rate for overall accesses 1086system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264488 # miss rate for overall accesses 1087system.cpu0.l2cache.overall_miss_rate::total 0.139249 # miss rate for overall accesses 1088system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average ReadReq miss latency 1089system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 65439.066680 # average ReadReq miss latency 1090system.cpu0.l2cache.ReadReq_avg_miss_latency::total 60602.839807 # average ReadReq miss latency 1091system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13046.398862 # average UpgradeReq miss latency 1092system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13046.398862 # average UpgradeReq miss latency 1093system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9922.847290 # average SCUpgradeReq miss latency 1094system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9922.847290 # average SCUpgradeReq miss latency 1095system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 604954.272727 # average SCUpgradeFailReq miss latency 1096system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 604954.272727 # average SCUpgradeFailReq miss latency 1097system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66160.899771 # average ReadExReq miss latency 1098system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66160.899771 # average ReadExReq miss latency 1099system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38490.125465 # average ReadCleanReq miss latency 1100system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38490.125465 # average ReadCleanReq miss latency 1101system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45705.148650 # average ReadSharedReq miss latency 1102system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45705.148650 # average ReadSharedReq miss latency 1103system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 764.951454 # average InvalidateReq miss latency 1104system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 764.951454 # average InvalidateReq miss latency 1105system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average overall miss latency 1106system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 65439.066680 # average overall miss latency 1107system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38490.125465 # average overall miss latency 1108system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50112.100257 # average overall miss latency 1109system.cpu0.l2cache.demand_avg_miss_latency::total 46226.112588 # average overall miss latency 1110system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 57149.320787 # average overall miss latency 1111system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 65439.066680 # average overall miss latency 1112system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38490.125465 # average overall miss latency 1113system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50112.100257 # average overall miss latency 1114system.cpu0.l2cache.overall_avg_miss_latency::total 46226.112588 # average overall miss latency 1115system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1116system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1117system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1118system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1119system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1120system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1121system.cpu0.l2cache.fast_writes 0 # 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number of demand (read+write) MSHR hits 1134system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 1135system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11075 # number of demand (read+write) MSHR hits 1136system.cpu0.l2cache.demand_mshr_hits::total 11087 # number of demand (read+write) MSHR hits 1137system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 1138system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 1139system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11075 # number of overall MSHR hits 1140system.cpu0.l2cache.overall_mshr_hits::total 11087 # number of overall MSHR hits 1141system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 14134 # number of ReadReq MSHR misses 1142system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10090 # number of ReadReq MSHR misses 1143system.cpu0.l2cache.ReadReq_mshr_misses::total 24224 # number of ReadReq MSHR misses 1144system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # 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number of demand (read+write) MSHR misses 1165system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1434100 # number of demand (read+write) MSHR misses 1166system.cpu0.l2cache.demand_mshr_misses::total 2229288 # number of demand (read+write) MSHR misses 1167system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 14134 # number of overall MSHR misses 1168system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10090 # number of overall MSHR misses 1169system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 770964 # number of overall MSHR misses 1170system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1434100 # number of overall MSHR misses 1171system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 890747 # number of overall MSHR misses 1172system.cpu0.l2cache.overall_mshr_misses::total 3120035 # number of overall MSHR misses 1173system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 1174system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15086 # 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number of HardPFReq MSHR miss cycles 1185system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 54995868600 # number of HardPFReq MSHR miss cycles 1186system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 8223573999 # number of UpgradeReq MSHR miss cycles 1187system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 8223573999 # number of UpgradeReq MSHR miss cycles 1188system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4114812496 # number of SCUpgradeReq MSHR miss cycles 1189system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4114812496 # number of SCUpgradeReq MSHR miss cycles 1190system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6132497 # number of SCUpgradeFailReq MSHR miss cycles 1191system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6132497 # number of SCUpgradeFailReq MSHR miss cycles 1192system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17351951000 # number of ReadExReq MSHR miss cycles 1193system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17351951000 # number of ReadExReq MSHR miss cycles 1194system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25048433000 # number of ReadCleanReq MSHR miss cycles 1195system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25048433000 # number of ReadCleanReq MSHR miss cycles 1196system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 44909041489 # number of ReadSharedReq MSHR miss cycles 1197system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 44909041489 # number of ReadSharedReq MSHR miss cycles 1198system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39596476000 # number of InvalidateReq MSHR miss cycles 1199system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39596476000 # number of InvalidateReq MSHR miss cycles 1200system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of demand (read+write) MSHR miss cycles 1201system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 599881000 # number of demand (read+write) MSHR miss cycles 1202system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25048433000 # number of demand (read+write) MSHR miss cycles 1203system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 62260992489 # number of demand (read+write) MSHR miss cycles 1204system.cpu0.l2cache.demand_mshr_miss_latency::total 88632250989 # number of demand (read+write) MSHR miss cycles 1205system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 722944500 # number of overall MSHR miss cycles 1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 599881000 # number of overall MSHR miss cycles 1207system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25048433000 # number of overall MSHR miss cycles 1208system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 62260992489 # number of overall MSHR miss cycles 1209system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 54995868600 # number of overall MSHR miss cycles 1210system.cpu0.l2cache.overall_mshr_miss_latency::total 143628119589 # number of overall MSHR miss cycles 1211system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 1212system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2519460500 # number of ReadReq MSHR uncacheable cycles 1213system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9515615500 # number of ReadReq MSHR uncacheable cycles 1214system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2627296000 # number of WriteReq MSHR uncacheable cycles 1215system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2627296000 # number of WriteReq MSHR uncacheable cycles 1216system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 1217system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5146756500 # number of overall MSHR uncacheable cycles 1218system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12142911500 # number of overall MSHR uncacheable cycles 1219system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for ReadReq accesses 1220system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for ReadReq accesses 1221system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031104 # mshr miss rate for ReadReq accesses 1222system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 1223system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 1224system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1225system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1226system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996808 # mshr miss rate for UpgradeReq accesses 1227system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996808 # mshr miss rate for UpgradeReq accesses 1228system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999986 # mshr miss rate for SCUpgradeReq accesses 1229system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999986 # mshr miss rate for SCUpgradeReq accesses 1230system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1231system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1232system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236376 # mshr miss rate for ReadExReq accesses 1233system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236376 # mshr miss rate for ReadExReq accesses 1234system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for ReadCleanReq accesses 1235system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078301 # mshr miss rate for ReadCleanReq accesses 1236system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270406 # mshr miss rate for ReadSharedReq accesses 1237system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270406 # mshr miss rate for ReadSharedReq accesses 1238system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.746562 # mshr miss rate for InvalidateReq accesses 1239system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.746562 # mshr miss rate for InvalidateReq accesses 1240system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for demand accesses 1241system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for demand accesses 1242system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for demand accesses 1243system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for demand accesses 1244system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138559 # mshr miss rate for demand accesses 1245system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for overall accesses 1246system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for overall accesses 1247system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for overall accesses 1248system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for overall accesses 1249system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1250system.cpu0.l2cache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses 1251system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average ReadReq mshr miss latency 1252system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average ReadReq mshr miss latency 1253system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996 # average ReadReq mshr miss latency 1254system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average HardPFReq mshr miss latency 1255system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726 # average HardPFReq mshr miss latency 1256system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776 # average UpgradeReq mshr miss latency 1257system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776 # average UpgradeReq mshr miss latency 1258system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363 # average SCUpgradeReq mshr miss latency 1259system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363 # average SCUpgradeReq mshr miss latency 1260system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273 # average SCUpgradeFailReq mshr miss latency 1261system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273 # average SCUpgradeFailReq mshr miss latency 1262system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546 # average ReadExReq mshr miss latency 1263system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546 # average ReadExReq mshr miss latency 1264system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average ReadCleanReq mshr miss latency 1265system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980 # average ReadCleanReq mshr miss latency 1266system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728 # average ReadSharedReq mshr miss latency 1267system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728 # average ReadSharedReq mshr miss latency 1268system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845 # average InvalidateReq mshr miss latency 1269system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845 # average InvalidateReq mshr miss latency 1270system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency 1271system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency 1272system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency 1273system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency 1274system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096 # average overall mshr miss latency 1275system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency 1276system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency 1277system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency 1278system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency 1279system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average overall mshr miss latency 1280system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306 # average overall mshr miss latency 1281system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 1282system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232 # average ReadReq mshr uncacheable latency 1283system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035 # average ReadReq mshr uncacheable latency 1284system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019 # average WriteReq mshr uncacheable latency 1285system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019 # average WriteReq mshr uncacheable latency 1286system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 1287system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191 # average overall mshr uncacheable latency 1288system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605 # average overall mshr uncacheable latency 1289system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1290system.cpu0.toL2Bus.snoop_filter.tot_requests 32897508 # Total number of requests made to the snoop filter. 1291system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16815136 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1292system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1293system.cpu0.toL2Bus.snoop_filter.tot_snoops 2403341 # Total number of snoops made to the snoop filter. 1294system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2402836 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1295system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 505 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1296system.cpu0.toL2Bus.trans_dist::ReadReq 933618 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::ReadResp 15066373 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::WriteReq 15977 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::WriteResp 15976 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::WritebackDirty 5804347 # Transaction distribution 1301system.cpu0.toL2Bus.trans_dist::WritebackClean 11960956 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::CleanEvict 3276888 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::HardPFReq 1153411 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::UpgradeReq 478642 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 376774 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::UpgradeResp 550943 # Transaction distribution 1308system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution 1309system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution 1310system.cpu0.toL2Bus.trans_dist::ReadExReq 1307095 # Transaction distribution 1311system.cpu0.toL2Bus.trans_dist::ReadExResp 1283776 # Transaction distribution 1312system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9846192 # Transaction distribution 1313system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5335526 # Transaction distribution 1314system.cpu0.toL2Bus.trans_dist::InvalidateReq 825564 # Transaction distribution 1315system.cpu0.toL2Bus.trans_dist::InvalidateResp 772295 # Transaction distribution 1316system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29642681 # Packet count per connected master and slave (bytes) 1317system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19817496 # Packet count per connected master and slave (bytes) 1318system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 405752 # Packet count per connected master and slave (bytes) 1319system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1239273 # Packet count per connected master and slave (bytes) 1320system.cpu0.toL2Bus.pkt_count::total 51105202 # Packet count per connected master and slave (bytes) 1321system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1263627520 # Cumulative packet size per connected master and slave (bytes) 1322system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 749575419 # Cumulative packet size per connected master and slave (bytes) 1323system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1544024 # Cumulative packet size per connected master and slave (bytes) 1324system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4686408 # Cumulative packet size per connected master and slave (bytes) 1325system.cpu0.toL2Bus.pkt_size::total 2019433371 # Cumulative packet size per connected master and slave (bytes) 1326system.cpu0.toL2Bus.snoops 8071764 # Total snoops (count) 1327system.cpu0.toL2Bus.snoop_fanout::samples 25329170 # Request fanout histogram 1328system.cpu0.toL2Bus.snoop_fanout::mean 0.108588 # Request fanout histogram 1329system.cpu0.toL2Bus.snoop_fanout::stdev 0.311185 # Request fanout histogram 1330system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1331system.cpu0.toL2Bus.snoop_fanout::0 22579237 89.14% 89.14% # Request fanout histogram 1332system.cpu0.toL2Bus.snoop_fanout::1 2749428 10.85% 100.00% # Request fanout histogram 1333system.cpu0.toL2Bus.snoop_fanout::2 505 0.00% 100.00% # Request fanout histogram 1334system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1335system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1336system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1337system.cpu0.toL2Bus.snoop_fanout::total 25329170 # Request fanout histogram 1338system.cpu0.toL2Bus.reqLayer0.occupancy 32745453976 # Layer occupancy (ticks) 1339system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1340system.cpu0.toL2Bus.snoopLayer0.occupancy 192728655 # Layer occupancy (ticks) 1341system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1342system.cpu0.toL2Bus.respLayer0.occupancy 14851397186 # Layer occupancy (ticks) 1343system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1344system.cpu0.toL2Bus.respLayer1.occupancy 8851946898 # Layer occupancy (ticks) 1345system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1346system.cpu0.toL2Bus.respLayer2.occupancy 212824349 # Layer occupancy (ticks) 1347system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1348system.cpu0.toL2Bus.respLayer3.occupancy 653582276 # Layer occupancy (ticks) 1349system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1350system.cpu1.branchPred.lookups 143060728 # Number of BP lookups 1351system.cpu1.branchPred.condPredicted 103431257 # Number of conditional branches predicted 1352system.cpu1.branchPred.condIncorrect 6108949 # Number of conditional branches incorrect 1353system.cpu1.branchPred.BTBLookups 108043566 # Number of BTB lookups 1354system.cpu1.branchPred.BTBHits 80039888 # Number of BTB hits 1355system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1356system.cpu1.branchPred.BTBHitPct 74.081124 # BTB Hit Percentage 1357system.cpu1.branchPred.usedRAS 15973583 # Number of times the RAS was used to get a target. 1358system.cpu1.branchPred.RASInCorrect 1078136 # Number of incorrect RAS predictions. 1359system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1360system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1361system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1362system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1363system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1364system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1365system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1366system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1367system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1368system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1369system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1370system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1371system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1372system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1373system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1374system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1375system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1376system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1377system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1378system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1379system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1380system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1381system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1382system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1383system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1384system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1385system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1386system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1387system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1388system.cpu1.dtb.walker.walks 316205 # Table walker walks requested 1389system.cpu1.dtb.walker.walksLong 316205 # Table walker walks initiated with long descriptors 1390system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13111 # Level at which table walker walks with long descriptors terminate 1391system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 102055 # Level at which table walker walks with long descriptors terminate 1392system.cpu1.dtb.walker.walkWaitTime::samples 316205 # Table walker wait (enqueue to first request) latency 1393system.cpu1.dtb.walker.walkWaitTime::0 316205 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1394system.cpu1.dtb.walker.walkWaitTime::total 316205 # Table walker wait (enqueue to first request) latency 1395system.cpu1.dtb.walker.walkCompletionTime::samples 115166 # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470 # Table walker service (enqueue to completion) latency 1397system.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420 # Table walker service (enqueue to completion) latency 1398system.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140 # Table walker service (enqueue to completion) latency 1399system.cpu1.dtb.walker.walkCompletionTime::0-65535 114056 99.04% 99.04% # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walkCompletionTime::65536-131071 145 0.13% 99.16% # Table walker service (enqueue to completion) latency 1401system.cpu1.dtb.walker.walkCompletionTime::131072-196607 815 0.71% 99.87% # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.90% # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.03% 99.94% # Table walker service (enqueue to completion) latency 1404system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency 1405system.cpu1.dtb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency 1406system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 1407system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 1408system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1409system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1410system.cpu1.dtb.walker.walkCompletionTime::total 115166 # Table walker service (enqueue to completion) latency 1411system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution 1412system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution 1413system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution 1414system.cpu1.dtb.walker.walkPageSizes::4K 102056 88.62% 88.62% # Table walker page sizes translated 1415system.cpu1.dtb.walker.walkPageSizes::2M 13111 11.38% 100.00% # Table walker page sizes translated 1416system.cpu1.dtb.walker.walkPageSizes::total 115167 # Table walker page sizes translated 1417system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 316205 # Table walker requests started/completed, data/inst 1418system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1419system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 316205 # Table walker requests started/completed, data/inst 1420system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115167 # Table walker requests started/completed, data/inst 1421system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1422system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115167 # Table walker requests started/completed, data/inst 1423system.cpu1.dtb.walker.walkRequestOrigin::total 431372 # Table walker requests started/completed, data/inst 1424system.cpu1.dtb.inst_hits 0 # ITB inst hits 1425system.cpu1.dtb.inst_misses 0 # ITB inst misses 1426system.cpu1.dtb.read_hits 90416501 # DTB read hits 1427system.cpu1.dtb.read_misses 263668 # DTB read misses 1428system.cpu1.dtb.write_hits 78865175 # DTB write hits 1429system.cpu1.dtb.write_misses 52537 # DTB write misses 1430system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 1431system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1432system.cpu1.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 1433system.cpu1.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 1434system.cpu1.dtb.flush_entries 39779 # Number of entries that have been flushed from TLB 1435system.cpu1.dtb.align_faults 1900 # Number of TLB faults due to alignment restrictions 1436system.cpu1.dtb.prefetch_faults 9673 # Number of TLB faults due to prefetch 1437system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1438system.cpu1.dtb.perms_faults 11862 # Number of TLB faults due to permissions restrictions 1439system.cpu1.dtb.read_accesses 90680169 # DTB read accesses 1440system.cpu1.dtb.write_accesses 78917712 # DTB write accesses 1441system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1442system.cpu1.dtb.hits 169281676 # DTB hits 1443system.cpu1.dtb.misses 316205 # DTB misses 1444system.cpu1.dtb.accesses 169597881 # DTB accesses 1445system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1446system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1447system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1448system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1449system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1450system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1451system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1452system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1453system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1454system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1455system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1456system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1457system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1458system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1459system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1460system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1461system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1462system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1463system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1464system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1465system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1466system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1467system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1468system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1469system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1470system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1471system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1472system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1473system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1474system.cpu1.itb.walker.walks 61623 # Table walker walks requested 1475system.cpu1.itb.walker.walksLong 61623 # Table walker walks initiated with long descriptors 1476system.cpu1.itb.walker.walksLongTerminationLevel::Level2 682 # Level at which table walker walks with long descriptors terminate 1477system.cpu1.itb.walker.walksLongTerminationLevel::Level3 51951 # Level at which table walker walks with long descriptors terminate 1478system.cpu1.itb.walker.walkWaitTime::samples 61623 # Table walker wait (enqueue to first request) latency 1479system.cpu1.itb.walker.walkWaitTime::0 61623 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1480system.cpu1.itb.walker.walkWaitTime::total 61623 # Table walker wait (enqueue to first request) latency 1481system.cpu1.itb.walker.walkCompletionTime::samples 52633 # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::mean 26809.463644 # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548 # Table walker service (enqueue to completion) latency 1484system.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644 # Table walker service (enqueue to completion) latency 1485system.cpu1.itb.walker.walkCompletionTime::0-65535 51446 97.74% 97.74% # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.76% # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::131072-196607 1035 1.97% 99.73% # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.83% # Table walker service (enqueue to completion) latency 1489system.cpu1.itb.walker.walkCompletionTime::262144-327679 44 0.08% 99.91% # Table walker service (enqueue to completion) latency 1490system.cpu1.itb.walker.walkCompletionTime::327680-393215 33 0.06% 99.98% # Table walker service (enqueue to completion) latency 1491system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.99% # Table walker service (enqueue to completion) latency 1492system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1493system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1494system.cpu1.itb.walker.walkCompletionTime::total 52633 # Table walker service (enqueue to completion) latency 1495system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution 1496system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution 1497system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution 1498system.cpu1.itb.walker.walkPageSizes::4K 51951 98.70% 98.70% # Table walker page sizes translated 1499system.cpu1.itb.walker.walkPageSizes::2M 682 1.30% 100.00% # Table walker page sizes translated 1500system.cpu1.itb.walker.walkPageSizes::total 52633 # Table walker page sizes translated 1501system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1502system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61623 # Table walker requests started/completed, data/inst 1503system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61623 # Table walker requests started/completed, data/inst 1504system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1505system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52633 # Table walker requests started/completed, data/inst 1506system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52633 # Table walker requests started/completed, data/inst 1507system.cpu1.itb.walker.walkRequestOrigin::total 114256 # Table walker requests started/completed, data/inst 1508system.cpu1.itb.inst_hits 255703249 # ITB inst hits 1509system.cpu1.itb.inst_misses 61623 # ITB inst misses 1510system.cpu1.itb.read_hits 0 # DTB read hits 1511system.cpu1.itb.read_misses 0 # DTB read misses 1512system.cpu1.itb.write_hits 0 # DTB write hits 1513system.cpu1.itb.write_misses 0 # DTB write misses 1514system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 1515system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1516system.cpu1.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID 1517system.cpu1.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID 1518system.cpu1.itb.flush_entries 28254 # Number of entries that have been flushed from TLB 1519system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1520system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1521system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1522system.cpu1.itb.perms_faults 225386 # Number of TLB faults due to permissions restrictions 1523system.cpu1.itb.read_accesses 0 # DTB read accesses 1524system.cpu1.itb.write_accesses 0 # DTB write accesses 1525system.cpu1.itb.inst_accesses 255764872 # ITB inst accesses 1526system.cpu1.itb.hits 255703249 # DTB hits 1527system.cpu1.itb.misses 61623 # DTB misses 1528system.cpu1.itb.accesses 255764872 # DTB accesses 1529system.cpu1.numCycles 1013399126 # number of cpu cycles simulated 1530system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1531system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1532system.cpu1.committedInsts 463476016 # Number of instructions committed 1533system.cpu1.committedOps 544549672 # Number of ops (including micro ops) committed 1534system.cpu1.discardedOps 51973590 # Number of ops (including micro ops) which were discarded before commit 1535system.cpu1.numFetchSuspends 4681 # Number of times Execute suspended instruction fetching 1536system.cpu1.quiesceCycles 93896343891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1537system.cpu1.cpi 2.186519 # CPI: cycles per instruction 1538system.cpu1.ipc 0.457348 # IPC: instructions per cycle 1539system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1540system.cpu1.kern.inst.quiesce 13591 # number of quiesce instructions executed 1541system.cpu1.tickCycles 759435347 # Number of cycles that the object actually ticked 1542system.cpu1.idleCycles 253963779 # Total number of cycles that the object has spent stopped 1543system.cpu1.dcache.tags.replacements 5640902 # number of replacements 1544system.cpu1.dcache.tags.tagsinuse 433.747661 # Cycle average of tags in use 1545system.cpu1.dcache.tags.total_refs 160682361 # Total number of references to valid blocks. 1546system.cpu1.dcache.tags.sampled_refs 5641413 # Sample count of references to valid blocks. 1547system.cpu1.dcache.tags.avg_refs 28.482645 # Average number of references to valid blocks. 1548system.cpu1.dcache.tags.warmup_cycle 8381463375500 # Cycle when the warmup percentage was hit. 1549system.cpu1.dcache.tags.occ_blocks::cpu1.data 433.747661 # Average occupied blocks per requestor 1550system.cpu1.dcache.tags.occ_percent::cpu1.data 0.847163 # Average percentage of cache occupancy 1551system.cpu1.dcache.tags.occ_percent::total 0.847163 # Average percentage of cache occupancy 1552system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1553system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 1554system.cpu1.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id 1555system.cpu1.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 1556system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1557system.cpu1.dcache.tags.tag_accesses 341448433 # Number of tag accesses 1558system.cpu1.dcache.tags.data_accesses 341448433 # Number of data accesses 1559system.cpu1.dcache.ReadReq_hits::cpu1.data 82699161 # number of ReadReq hits 1560system.cpu1.dcache.ReadReq_hits::total 82699161 # number of ReadReq hits 1561system.cpu1.dcache.WriteReq_hits::cpu1.data 73240702 # number of WriteReq hits 1562system.cpu1.dcache.WriteReq_hits::total 73240702 # number of WriteReq hits 1563system.cpu1.dcache.SoftPFReq_hits::cpu1.data 257576 # number of SoftPFReq hits 1564system.cpu1.dcache.SoftPFReq_hits::total 257576 # number of SoftPFReq hits 1565system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197387 # number of WriteLineReq hits 1566system.cpu1.dcache.WriteLineReq_hits::total 197387 # number of WriteLineReq hits 1567system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1901357 # number of LoadLockedReq hits 1568system.cpu1.dcache.LoadLockedReq_hits::total 1901357 # number of LoadLockedReq hits 1569system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1855769 # number of StoreCondReq hits 1570system.cpu1.dcache.StoreCondReq_hits::total 1855769 # number of StoreCondReq hits 1571system.cpu1.dcache.demand_hits::cpu1.data 155939863 # number of demand (read+write) hits 1572system.cpu1.dcache.demand_hits::total 155939863 # number of demand (read+write) hits 1573system.cpu1.dcache.overall_hits::cpu1.data 156197439 # number of overall hits 1574system.cpu1.dcache.overall_hits::total 156197439 # number of overall hits 1575system.cpu1.dcache.ReadReq_misses::cpu1.data 3585243 # number of ReadReq misses 1576system.cpu1.dcache.ReadReq_misses::total 3585243 # number of ReadReq misses 1577system.cpu1.dcache.WriteReq_misses::cpu1.data 2523734 # number of WriteReq misses 1578system.cpu1.dcache.WriteReq_misses::total 2523734 # number of WriteReq misses 1579system.cpu1.dcache.SoftPFReq_misses::cpu1.data 738365 # number of SoftPFReq misses 1580system.cpu1.dcache.SoftPFReq_misses::total 738365 # number of SoftPFReq misses 1581system.cpu1.dcache.WriteLineReq_misses::cpu1.data 486988 # number of WriteLineReq misses 1582system.cpu1.dcache.WriteLineReq_misses::total 486988 # number of WriteLineReq misses 1583system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162310 # number of LoadLockedReq misses 1584system.cpu1.dcache.LoadLockedReq_misses::total 162310 # number of LoadLockedReq misses 1585system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206438 # number of StoreCondReq misses 1586system.cpu1.dcache.StoreCondReq_misses::total 206438 # number of StoreCondReq misses 1587system.cpu1.dcache.demand_misses::cpu1.data 6108977 # number of demand (read+write) misses 1588system.cpu1.dcache.demand_misses::total 6108977 # number of demand (read+write) misses 1589system.cpu1.dcache.overall_misses::cpu1.data 6847342 # number of overall misses 1590system.cpu1.dcache.overall_misses::total 6847342 # number of overall misses 1591system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60530715500 # number of ReadReq miss cycles 1592system.cpu1.dcache.ReadReq_miss_latency::total 60530715500 # number of ReadReq miss cycles 1593system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 58663605500 # number of WriteReq miss cycles 1594system.cpu1.dcache.WriteReq_miss_latency::total 58663605500 # number of WriteReq miss cycles 1595system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22007902000 # number of WriteLineReq miss cycles 1596system.cpu1.dcache.WriteLineReq_miss_latency::total 22007902000 # number of WriteLineReq miss cycles 1597system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2738446000 # number of LoadLockedReq miss cycles 1598system.cpu1.dcache.LoadLockedReq_miss_latency::total 2738446000 # number of LoadLockedReq miss cycles 1599system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5741911000 # number of StoreCondReq miss cycles 1600system.cpu1.dcache.StoreCondReq_miss_latency::total 5741911000 # number of StoreCondReq miss cycles 1601system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7112000 # number of StoreCondFailReq miss cycles 1602system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7112000 # number of StoreCondFailReq miss cycles 1603system.cpu1.dcache.demand_miss_latency::cpu1.data 119194321000 # number of demand (read+write) miss cycles 1604system.cpu1.dcache.demand_miss_latency::total 119194321000 # number of demand (read+write) miss cycles 1605system.cpu1.dcache.overall_miss_latency::cpu1.data 119194321000 # number of overall miss cycles 1606system.cpu1.dcache.overall_miss_latency::total 119194321000 # number of overall miss cycles 1607system.cpu1.dcache.ReadReq_accesses::cpu1.data 86284404 # number of ReadReq accesses(hits+misses) 1608system.cpu1.dcache.ReadReq_accesses::total 86284404 # number of ReadReq accesses(hits+misses) 1609system.cpu1.dcache.WriteReq_accesses::cpu1.data 75764436 # number of WriteReq accesses(hits+misses) 1610system.cpu1.dcache.WriteReq_accesses::total 75764436 # number of WriteReq accesses(hits+misses) 1611system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 995941 # number of SoftPFReq accesses(hits+misses) 1612system.cpu1.dcache.SoftPFReq_accesses::total 995941 # number of SoftPFReq accesses(hits+misses) 1613system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 684375 # number of WriteLineReq accesses(hits+misses) 1614system.cpu1.dcache.WriteLineReq_accesses::total 684375 # number of WriteLineReq accesses(hits+misses) 1615system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2063667 # number of LoadLockedReq accesses(hits+misses) 1616system.cpu1.dcache.LoadLockedReq_accesses::total 2063667 # number of LoadLockedReq accesses(hits+misses) 1617system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2062207 # number of StoreCondReq accesses(hits+misses) 1618system.cpu1.dcache.StoreCondReq_accesses::total 2062207 # number of StoreCondReq accesses(hits+misses) 1619system.cpu1.dcache.demand_accesses::cpu1.data 162048840 # number of demand (read+write) accesses 1620system.cpu1.dcache.demand_accesses::total 162048840 # number of demand (read+write) accesses 1621system.cpu1.dcache.overall_accesses::cpu1.data 163044781 # number of overall (read+write) accesses 1622system.cpu1.dcache.overall_accesses::total 163044781 # number of overall (read+write) accesses 1623system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041551 # miss rate for ReadReq accesses 1624system.cpu1.dcache.ReadReq_miss_rate::total 0.041551 # miss rate for ReadReq accesses 1625system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033310 # miss rate for WriteReq accesses 1626system.cpu1.dcache.WriteReq_miss_rate::total 0.033310 # miss rate for WriteReq accesses 1627system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.741374 # miss rate for SoftPFReq accesses 1628system.cpu1.dcache.SoftPFReq_miss_rate::total 0.741374 # miss rate for SoftPFReq accesses 1629system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.711581 # miss rate for WriteLineReq accesses 1630system.cpu1.dcache.WriteLineReq_miss_rate::total 0.711581 # miss rate for WriteLineReq accesses 1631system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078651 # miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078651 # miss rate for LoadLockedReq accesses 1633system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100105 # miss rate for StoreCondReq accesses 1634system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100105 # miss rate for StoreCondReq accesses 1635system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037698 # miss rate for demand accesses 1636system.cpu1.dcache.demand_miss_rate::total 0.037698 # miss rate for demand accesses 1637system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041997 # miss rate for overall accesses 1638system.cpu1.dcache.overall_miss_rate::total 0.041997 # miss rate for overall accesses 1639system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16883.295079 # average ReadReq miss latency 1640system.cpu1.dcache.ReadReq_avg_miss_latency::total 16883.295079 # average ReadReq miss latency 1641system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23244.765692 # average WriteReq miss latency 1642system.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692 # average WriteReq miss latency 1643system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418 # average WriteLineReq miss latency 1644system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45191.877418 # average WriteLineReq miss latency 1645system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16871.702298 # average LoadLockedReq miss latency 1646system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16871.702298 # average LoadLockedReq miss latency 1647system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27814.215406 # average StoreCondReq miss latency 1648system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27814.215406 # average StoreCondReq miss latency 1649system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1650system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1651system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19511.338969 # average overall miss latency 1652system.cpu1.dcache.demand_avg_miss_latency::total 19511.338969 # average overall miss latency 1653system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17407.385377 # average overall miss latency 1654system.cpu1.dcache.overall_avg_miss_latency::total 17407.385377 # average overall miss latency 1655system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1656system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1657system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1658system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1659system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1660system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1661system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1662system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1663system.cpu1.dcache.writebacks::writebacks 5640935 # number of writebacks 1664system.cpu1.dcache.writebacks::total 5640935 # number of writebacks 1665system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 429416 # number of ReadReq MSHR hits 1666system.cpu1.dcache.ReadReq_mshr_hits::total 429416 # number of ReadReq MSHR hits 1667system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1043359 # number of WriteReq MSHR hits 1668system.cpu1.dcache.WriteReq_mshr_hits::total 1043359 # number of WriteReq MSHR hits 1669system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits 1670system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits 1671system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42170 # number of LoadLockedReq MSHR hits 1672system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42170 # number of LoadLockedReq MSHR hits 1673system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 72 # number of StoreCondReq MSHR hits 1674system.cpu1.dcache.StoreCondReq_mshr_hits::total 72 # number of StoreCondReq MSHR hits 1675system.cpu1.dcache.demand_mshr_hits::cpu1.data 1472775 # number of demand (read+write) MSHR hits 1676system.cpu1.dcache.demand_mshr_hits::total 1472775 # number of demand (read+write) MSHR hits 1677system.cpu1.dcache.overall_mshr_hits::cpu1.data 1472775 # number of overall MSHR hits 1678system.cpu1.dcache.overall_mshr_hits::total 1472775 # number of overall MSHR hits 1679system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3155827 # number of ReadReq MSHR misses 1680system.cpu1.dcache.ReadReq_mshr_misses::total 3155827 # number of ReadReq MSHR misses 1681system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1480375 # number of WriteReq MSHR misses 1682system.cpu1.dcache.WriteReq_mshr_misses::total 1480375 # number of WriteReq MSHR misses 1683system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 738082 # number of SoftPFReq MSHR misses 1684system.cpu1.dcache.SoftPFReq_mshr_misses::total 738082 # number of SoftPFReq MSHR misses 1685system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 486914 # number of WriteLineReq MSHR misses 1686system.cpu1.dcache.WriteLineReq_mshr_misses::total 486914 # number of WriteLineReq MSHR misses 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120140 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120140 # number of LoadLockedReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206366 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.StoreCondReq_mshr_misses::total 206366 # number of StoreCondReq MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::cpu1.data 4636202 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.demand_mshr_misses::total 4636202 # number of demand (read+write) MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::cpu1.data 5374284 # number of overall MSHR misses 1694system.cpu1.dcache.overall_mshr_misses::total 5374284 # number of overall MSHR misses 1695system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable 1696system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23242 # number of ReadReq MSHR uncacheable 1697system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable 1698system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable 1699system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses 1700system.cpu1.dcache.overall_mshr_uncacheable_misses::total 45478 # number of overall MSHR uncacheable misses 1701system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 47412877500 # number of ReadReq MSHR miss cycles 1702system.cpu1.dcache.ReadReq_mshr_miss_latency::total 47412877500 # number of ReadReq MSHR miss cycles 1703system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34746994000 # number of WriteReq MSHR miss cycles 1704system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34746994000 # number of WriteReq MSHR miss cycles 1705system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 19660408500 # number of SoftPFReq MSHR miss cycles 1706system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 19660408500 # number of SoftPFReq MSHR miss cycles 1707system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 21514132500 # number of WriteLineReq MSHR miss cycles 1708system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 21514132500 # number of WriteLineReq MSHR miss cycles 1709system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1774236500 # number of LoadLockedReq MSHR miss cycles 1710system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1774236500 # number of LoadLockedReq MSHR miss cycles 1711system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5529988500 # number of StoreCondReq MSHR miss cycles 1712system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5529988500 # number of StoreCondReq MSHR miss cycles 1713system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6729000 # number of StoreCondFailReq MSHR miss cycles 1714system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6729000 # number of StoreCondFailReq MSHR miss cycles 1715system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82159871500 # number of demand (read+write) MSHR miss cycles 1716system.cpu1.dcache.demand_mshr_miss_latency::total 82159871500 # number of demand (read+write) MSHR miss cycles 1717system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101820280000 # number of overall MSHR miss cycles 1718system.cpu1.dcache.overall_mshr_miss_latency::total 101820280000 # number of overall MSHR miss cycles 1719system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4292810500 # number of ReadReq MSHR uncacheable cycles 1720system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4292810500 # number of ReadReq MSHR uncacheable cycles 1721system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4172773000 # number of WriteReq MSHR uncacheable cycles 1722system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4172773000 # number of WriteReq MSHR uncacheable cycles 1723system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8465583500 # number of overall MSHR uncacheable cycles 1724system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8465583500 # number of overall MSHR uncacheable cycles 1725system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036575 # mshr miss rate for ReadReq accesses 1726system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036575 # mshr miss rate for ReadReq accesses 1727system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019539 # mshr miss rate for WriteReq accesses 1728system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019539 # mshr miss rate for WriteReq accesses 1729system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741090 # mshr miss rate for SoftPFReq accesses 1730system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.741090 # mshr miss rate for SoftPFReq accesses 1731system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.711473 # mshr miss rate for WriteLineReq accesses 1732system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.711473 # mshr miss rate for WriteLineReq accesses 1733system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058217 # mshr miss rate for LoadLockedReq accesses 1734system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058217 # mshr miss rate for LoadLockedReq accesses 1735system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100070 # mshr miss rate for StoreCondReq accesses 1736system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100070 # mshr miss rate for StoreCondReq accesses 1737system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028610 # mshr miss rate for demand accesses 1738system.cpu1.dcache.demand_mshr_miss_rate::total 0.028610 # mshr miss rate for demand accesses 1739system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032962 # mshr miss rate for overall accesses 1740system.cpu1.dcache.overall_mshr_miss_rate::total 0.032962 # mshr miss rate for overall accesses 1741system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284 # average ReadReq mshr miss latency 1742system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284 # average ReadReq mshr miss latency 1743system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414 # average WriteReq mshr miss latency 1744system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414 # average WriteReq mshr miss latency 1745system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234 # average SoftPFReq mshr miss latency 1746system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234 # average SoftPFReq mshr miss latency 1747system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081 # average WriteLineReq mshr miss latency 1748system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081 # average WriteLineReq mshr miss latency 1749system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746 # average LoadLockedReq mshr miss latency 1750system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746 # average LoadLockedReq mshr miss latency 1751system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175 # average StoreCondReq mshr miss latency 1752system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175 # average StoreCondReq mshr miss latency 1753system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1754system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1755system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17721.374414 # average overall mshr miss latency 1756system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17721.374414 # average overall mshr miss latency 1757system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18945.831668 # average overall mshr miss latency 1758system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18945.831668 # average overall mshr miss latency 1759system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184700.563635 # average ReadReq mshr uncacheable latency 1760system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184700.563635 # average ReadReq mshr uncacheable latency 1761system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187658.436769 # average WriteReq mshr uncacheable latency 1762system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187658.436769 # average WriteReq mshr uncacheable latency 1763system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186146.785259 # average overall mshr uncacheable latency 1764system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186146.785259 # average overall mshr uncacheable latency 1765system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1766system.cpu1.icache.tags.replacements 9253909 # number of replacements 1767system.cpu1.icache.tags.tagsinuse 506.772073 # Cycle average of tags in use 1768system.cpu1.icache.tags.total_refs 246217857 # Total number of references to valid blocks. 1769system.cpu1.icache.tags.sampled_refs 9254421 # Sample count of references to valid blocks. 1770system.cpu1.icache.tags.avg_refs 26.605431 # Average number of references to valid blocks. 1771system.cpu1.icache.tags.warmup_cycle 8381293063000 # Cycle when the warmup percentage was hit. 1772system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.772073 # Average occupied blocks per requestor 1773system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989789 # Average percentage of cache occupancy 1774system.cpu1.icache.tags.occ_percent::total 0.989789 # Average percentage of cache occupancy 1775system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1776system.cpu1.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 1777system.cpu1.icache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 1778system.cpu1.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 1779system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1780system.cpu1.icache.tags.tag_accesses 520199009 # Number of tag accesses 1781system.cpu1.icache.tags.data_accesses 520199009 # Number of data accesses 1782system.cpu1.icache.ReadReq_hits::cpu1.inst 246217857 # number of ReadReq hits 1783system.cpu1.icache.ReadReq_hits::total 246217857 # number of ReadReq hits 1784system.cpu1.icache.demand_hits::cpu1.inst 246217857 # number of demand (read+write) hits 1785system.cpu1.icache.demand_hits::total 246217857 # number of demand (read+write) hits 1786system.cpu1.icache.overall_hits::cpu1.inst 246217857 # number of overall hits 1787system.cpu1.icache.overall_hits::total 246217857 # number of overall hits 1788system.cpu1.icache.ReadReq_misses::cpu1.inst 9254432 # number of ReadReq misses 1789system.cpu1.icache.ReadReq_misses::total 9254432 # number of ReadReq misses 1790system.cpu1.icache.demand_misses::cpu1.inst 9254432 # number of demand (read+write) misses 1791system.cpu1.icache.demand_misses::total 9254432 # number of demand (read+write) misses 1792system.cpu1.icache.overall_misses::cpu1.inst 9254432 # number of overall misses 1793system.cpu1.icache.overall_misses::total 9254432 # number of overall misses 1794system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 97819295000 # number of ReadReq miss cycles 1795system.cpu1.icache.ReadReq_miss_latency::total 97819295000 # number of ReadReq miss cycles 1796system.cpu1.icache.demand_miss_latency::cpu1.inst 97819295000 # number of demand (read+write) miss cycles 1797system.cpu1.icache.demand_miss_latency::total 97819295000 # number of demand (read+write) miss cycles 1798system.cpu1.icache.overall_miss_latency::cpu1.inst 97819295000 # number of overall miss cycles 1799system.cpu1.icache.overall_miss_latency::total 97819295000 # number of overall miss cycles 1800system.cpu1.icache.ReadReq_accesses::cpu1.inst 255472289 # number of ReadReq accesses(hits+misses) 1801system.cpu1.icache.ReadReq_accesses::total 255472289 # number of ReadReq accesses(hits+misses) 1802system.cpu1.icache.demand_accesses::cpu1.inst 255472289 # number of demand (read+write) accesses 1803system.cpu1.icache.demand_accesses::total 255472289 # number of demand (read+write) accesses 1804system.cpu1.icache.overall_accesses::cpu1.inst 255472289 # number of overall (read+write) accesses 1805system.cpu1.icache.overall_accesses::total 255472289 # number of overall (read+write) accesses 1806system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036225 # miss rate for ReadReq accesses 1807system.cpu1.icache.ReadReq_miss_rate::total 0.036225 # miss rate for ReadReq accesses 1808system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036225 # miss rate for demand accesses 1809system.cpu1.icache.demand_miss_rate::total 0.036225 # miss rate for demand accesses 1810system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036225 # miss rate for overall accesses 1811system.cpu1.icache.overall_miss_rate::total 0.036225 # miss rate for overall accesses 1812system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10569.994463 # average ReadReq miss latency 1813system.cpu1.icache.ReadReq_avg_miss_latency::total 10569.994463 # average ReadReq miss latency 1814system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency 1815system.cpu1.icache.demand_avg_miss_latency::total 10569.994463 # average overall miss latency 1816system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency 1817system.cpu1.icache.overall_avg_miss_latency::total 10569.994463 # average overall miss latency 1818system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1819system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1820system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1821system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1822system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1823system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1824system.cpu1.icache.fast_writes 0 # number of fast writes performed 1825system.cpu1.icache.cache_copies 0 # number of cache copies performed 1826system.cpu1.icache.writebacks::writebacks 9253909 # number of writebacks 1827system.cpu1.icache.writebacks::total 9253909 # number of writebacks 1828system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9254432 # number of ReadReq MSHR misses 1829system.cpu1.icache.ReadReq_mshr_misses::total 9254432 # number of ReadReq MSHR misses 1830system.cpu1.icache.demand_mshr_misses::cpu1.inst 9254432 # number of demand (read+write) MSHR misses 1831system.cpu1.icache.demand_mshr_misses::total 9254432 # number of demand (read+write) MSHR misses 1832system.cpu1.icache.overall_mshr_misses::cpu1.inst 9254432 # number of overall MSHR misses 1833system.cpu1.icache.overall_mshr_misses::total 9254432 # number of overall MSHR misses 1834system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 1835system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 1836system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 1837system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses 1838system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 93192079500 # number of ReadReq MSHR miss cycles 1839system.cpu1.icache.ReadReq_mshr_miss_latency::total 93192079500 # number of ReadReq MSHR miss cycles 1840system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 93192079500 # number of demand (read+write) MSHR miss cycles 1841system.cpu1.icache.demand_mshr_miss_latency::total 93192079500 # number of demand (read+write) MSHR miss cycles 1842system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 93192079500 # number of overall MSHR miss cycles 1843system.cpu1.icache.overall_mshr_miss_latency::total 93192079500 # number of overall MSHR miss cycles 1844system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13081000 # number of ReadReq MSHR uncacheable cycles 1845system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13081000 # number of ReadReq MSHR uncacheable cycles 1846system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles 1847system.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles 1848system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for ReadReq accesses 1849system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036225 # mshr miss rate for ReadReq accesses 1850system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for demand accesses 1851system.cpu1.icache.demand_mshr_miss_rate::total 0.036225 # mshr miss rate for demand accesses 1852system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for overall accesses 1853system.cpu1.icache.overall_mshr_miss_rate::total 0.036225 # mshr miss rate for overall accesses 1854system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average ReadReq mshr miss latency 1855system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10069.994517 # average ReadReq mshr miss latency 1856system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency 1857system.cpu1.icache.demand_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency 1858system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency 1859system.cpu1.icache.overall_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency 1860system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency 1861system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency 1862system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency 1863system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency 1864system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1865system.cpu1.l2cache.prefetcher.num_hwpf_issued 7972481 # number of hwpf issued 1866system.cpu1.l2cache.prefetcher.pfIdentified 7973767 # number of prefetch candidates identified 1867system.cpu1.l2cache.prefetcher.pfBufferHit 1132 # number of redundant prefetches already in prefetch queue 1868system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1869system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1870system.cpu1.l2cache.prefetcher.pfSpanPage 946401 # number of prefetches not generated due to page crossing 1871system.cpu1.l2cache.tags.replacements 2682833 # number of replacements 1872system.cpu1.l2cache.tags.tagsinuse 13443.137658 # Cycle average of tags in use 1873system.cpu1.l2cache.tags.total_refs 23351564 # Total number of references to valid blocks. 1874system.cpu1.l2cache.tags.sampled_refs 2698948 # Sample count of references to valid blocks. 1875system.cpu1.l2cache.tags.avg_refs 8.652099 # Average number of references to valid blocks. 1876system.cpu1.l2cache.tags.warmup_cycle 10051011039000 # Cycle when the warmup percentage was hit. 1877system.cpu1.l2cache.tags.occ_blocks::writebacks 12664.163497 # Average occupied blocks per requestor 1878system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 64.427658 # Average occupied blocks per requestor 1879system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 52.788670 # Average occupied blocks per requestor 1880system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 661.757834 # Average occupied blocks per requestor 1881system.cpu1.l2cache.tags.occ_percent::writebacks 0.772959 # Average percentage of cache occupancy 1882system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003932 # Average percentage of cache occupancy 1883system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003222 # Average percentage of cache occupancy 1884system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040390 # Average percentage of cache occupancy 1885system.cpu1.l2cache.tags.occ_percent::total 0.820504 # Average percentage of cache occupancy 1886system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1261 # Occupied blocks per task id 1887system.cpu1.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 338 # Occupied blocks per task id 1891system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 798 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1053 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5404 # Occupied blocks per task id 1899system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7290 # Occupied blocks per task id 1900system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 973 # Occupied blocks per task id 1901system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076965 # Percentage of cache occupancy per task id 1902system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id 1903system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id 1904system.cpu1.l2cache.tags.tag_accesses 504035480 # Number of tag accesses 1905system.cpu1.l2cache.tags.data_accesses 504035480 # Number of data accesses 1906system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 619167 # number of ReadReq hits 1907system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 157082 # number of ReadReq hits 1908system.cpu1.l2cache.ReadReq_hits::total 776249 # number of ReadReq hits 1909system.cpu1.l2cache.WritebackDirty_hits::writebacks 3580112 # number of WritebackDirty hits 1910system.cpu1.l2cache.WritebackDirty_hits::total 3580112 # number of WritebackDirty hits 1911system.cpu1.l2cache.WritebackClean_hits::writebacks 11312106 # number of WritebackClean hits 1912system.cpu1.l2cache.WritebackClean_hits::total 11312106 # number of WritebackClean hits 1913system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 786 # number of UpgradeReq hits 1914system.cpu1.l2cache.UpgradeReq_hits::total 786 # number of UpgradeReq hits 1915system.cpu1.l2cache.ReadExReq_hits::cpu1.data 968681 # number of ReadExReq hits 1916system.cpu1.l2cache.ReadExReq_hits::total 968681 # number of ReadExReq hits 1917system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8504758 # number of ReadCleanReq hits 1918system.cpu1.l2cache.ReadCleanReq_hits::total 8504758 # number of ReadCleanReq hits 1919system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2930307 # number of ReadSharedReq hits 1920system.cpu1.l2cache.ReadSharedReq_hits::total 2930307 # number of ReadSharedReq hits 1921system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 167226 # number of InvalidateReq hits 1922system.cpu1.l2cache.InvalidateReq_hits::total 167226 # number of InvalidateReq hits 1923system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 619167 # number of demand (read+write) hits 1924system.cpu1.l2cache.demand_hits::cpu1.itb.walker 157082 # number of demand (read+write) hits 1925system.cpu1.l2cache.demand_hits::cpu1.inst 8504758 # number of demand (read+write) hits 1926system.cpu1.l2cache.demand_hits::cpu1.data 3898988 # number of demand (read+write) hits 1927system.cpu1.l2cache.demand_hits::total 13179995 # number of demand (read+write) hits 1928system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 619167 # number of overall hits 1929system.cpu1.l2cache.overall_hits::cpu1.itb.walker 157082 # number of overall hits 1930system.cpu1.l2cache.overall_hits::cpu1.inst 8504758 # number of overall hits 1931system.cpu1.l2cache.overall_hits::cpu1.data 3898988 # number of overall hits 1932system.cpu1.l2cache.overall_hits::total 13179995 # number of overall hits 1933system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13008 # number of ReadReq misses 1934system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8398 # number of ReadReq misses 1935system.cpu1.l2cache.ReadReq_misses::total 21406 # number of ReadReq misses 1936system.cpu1.l2cache.WritebackDirty_misses::writebacks 3 # number of WritebackDirty misses 1937system.cpu1.l2cache.WritebackDirty_misses::total 3 # number of WritebackDirty misses 1938system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 242430 # number of UpgradeReq misses 1939system.cpu1.l2cache.UpgradeReq_misses::total 242430 # number of UpgradeReq misses 1940system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 206357 # number of SCUpgradeReq misses 1941system.cpu1.l2cache.SCUpgradeReq_misses::total 206357 # number of SCUpgradeReq misses 1942system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 1943system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 1944system.cpu1.l2cache.ReadExReq_misses::cpu1.data 271269 # number of ReadExReq misses 1945system.cpu1.l2cache.ReadExReq_misses::total 271269 # number of ReadExReq misses 1946system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 749674 # number of ReadCleanReq misses 1947system.cpu1.l2cache.ReadCleanReq_misses::total 749674 # number of ReadCleanReq misses 1948system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1083420 # number of ReadSharedReq misses 1949system.cpu1.l2cache.ReadSharedReq_misses::total 1083420 # number of ReadSharedReq misses 1950system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 317410 # number of InvalidateReq misses 1951system.cpu1.l2cache.InvalidateReq_misses::total 317410 # number of InvalidateReq misses 1952system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13008 # number of demand (read+write) misses 1953system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8398 # number of demand (read+write) misses 1954system.cpu1.l2cache.demand_misses::cpu1.inst 749674 # number of demand (read+write) misses 1955system.cpu1.l2cache.demand_misses::cpu1.data 1354689 # number of demand (read+write) misses 1956system.cpu1.l2cache.demand_misses::total 2125769 # number of demand (read+write) misses 1957system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13008 # number of overall misses 1958system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8398 # number of overall misses 1959system.cpu1.l2cache.overall_misses::cpu1.inst 749674 # number of overall misses 1960system.cpu1.l2cache.overall_misses::cpu1.data 1354689 # number of overall misses 1961system.cpu1.l2cache.overall_misses::total 2125769 # number of overall misses 1962system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 644553000 # number of ReadReq miss cycles 1963system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 465440500 # number of ReadReq miss cycles 1964system.cpu1.l2cache.ReadReq_miss_latency::total 1109993500 # number of ReadReq miss cycles 1965system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3394976000 # number of UpgradeReq miss cycles 1966system.cpu1.l2cache.UpgradeReq_miss_latency::total 3394976000 # number of UpgradeReq miss cycles 1967system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2059365000 # number of SCUpgradeReq miss cycles 1968system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2059365000 # number of SCUpgradeReq miss cycles 1969system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6608499 # number of SCUpgradeFailReq miss cycles 1970system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6608499 # number of SCUpgradeFailReq miss cycles 1971system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 17354243497 # number of ReadExReq miss cycles 1972system.cpu1.l2cache.ReadExReq_miss_latency::total 17354243497 # number of ReadExReq miss cycles 1973system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 27964377000 # number of ReadCleanReq miss cycles 1974system.cpu1.l2cache.ReadCleanReq_miss_latency::total 27964377000 # number of ReadCleanReq miss cycles 1975system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 43468216991 # number of ReadSharedReq miss cycles 1976system.cpu1.l2cache.ReadSharedReq_miss_latency::total 43468216991 # number of ReadSharedReq miss cycles 1977system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 430263500 # number of InvalidateReq miss cycles 1978system.cpu1.l2cache.InvalidateReq_miss_latency::total 430263500 # number of InvalidateReq miss cycles 1979system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 644553000 # number of demand (read+write) miss cycles 1980system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 465440500 # number of demand (read+write) miss cycles 1981system.cpu1.l2cache.demand_miss_latency::cpu1.inst 27964377000 # number of demand (read+write) miss cycles 1982system.cpu1.l2cache.demand_miss_latency::cpu1.data 60822460488 # number of demand (read+write) miss cycles 1983system.cpu1.l2cache.demand_miss_latency::total 89896830988 # number of demand (read+write) miss cycles 1984system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 644553000 # number of overall miss cycles 1985system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 465440500 # number of overall miss cycles 1986system.cpu1.l2cache.overall_miss_latency::cpu1.inst 27964377000 # number of overall miss cycles 1987system.cpu1.l2cache.overall_miss_latency::cpu1.data 60822460488 # number of overall miss cycles 1988system.cpu1.l2cache.overall_miss_latency::total 89896830988 # number of overall miss cycles 1989system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 632175 # number of ReadReq accesses(hits+misses) 1990system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165480 # number of ReadReq accesses(hits+misses) 1991system.cpu1.l2cache.ReadReq_accesses::total 797655 # number of ReadReq accesses(hits+misses) 1992system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3580115 # number of WritebackDirty accesses(hits+misses) 1993system.cpu1.l2cache.WritebackDirty_accesses::total 3580115 # number of WritebackDirty accesses(hits+misses) 1994system.cpu1.l2cache.WritebackClean_accesses::writebacks 11312106 # number of WritebackClean accesses(hits+misses) 1995system.cpu1.l2cache.WritebackClean_accesses::total 11312106 # number of WritebackClean accesses(hits+misses) 1996system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 243216 # number of UpgradeReq accesses(hits+misses) 1997system.cpu1.l2cache.UpgradeReq_accesses::total 243216 # number of UpgradeReq accesses(hits+misses) 1998system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 206357 # number of SCUpgradeReq accesses(hits+misses) 1999system.cpu1.l2cache.SCUpgradeReq_accesses::total 206357 # number of SCUpgradeReq accesses(hits+misses) 2000system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 2001system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 2002system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1239950 # number of ReadExReq accesses(hits+misses) 2003system.cpu1.l2cache.ReadExReq_accesses::total 1239950 # number of ReadExReq accesses(hits+misses) 2004system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9254432 # number of ReadCleanReq accesses(hits+misses) 2005system.cpu1.l2cache.ReadCleanReq_accesses::total 9254432 # number of ReadCleanReq accesses(hits+misses) 2006system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4013727 # number of ReadSharedReq accesses(hits+misses) 2007system.cpu1.l2cache.ReadSharedReq_accesses::total 4013727 # number of ReadSharedReq accesses(hits+misses) 2008system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 484636 # number of InvalidateReq accesses(hits+misses) 2009system.cpu1.l2cache.InvalidateReq_accesses::total 484636 # number of InvalidateReq accesses(hits+misses) 2010system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 632175 # number of demand (read+write) accesses 2011system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165480 # number of demand (read+write) accesses 2012system.cpu1.l2cache.demand_accesses::cpu1.inst 9254432 # number of demand (read+write) accesses 2013system.cpu1.l2cache.demand_accesses::cpu1.data 5253677 # number of demand (read+write) accesses 2014system.cpu1.l2cache.demand_accesses::total 15305764 # number of demand (read+write) accesses 2015system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 632175 # number of overall (read+write) accesses 2016system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165480 # number of overall (read+write) accesses 2017system.cpu1.l2cache.overall_accesses::cpu1.inst 9254432 # number of overall (read+write) accesses 2018system.cpu1.l2cache.overall_accesses::cpu1.data 5253677 # number of overall (read+write) accesses 2019system.cpu1.l2cache.overall_accesses::total 15305764 # number of overall (read+write) accesses 2020system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for ReadReq accesses 2021system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050749 # miss rate for ReadReq accesses 2022system.cpu1.l2cache.ReadReq_miss_rate::total 0.026836 # miss rate for ReadReq accesses 2023system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 2024system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 2025system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996768 # miss rate for UpgradeReq accesses 2026system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996768 # miss rate for UpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2028system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2029system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2030system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2031system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.218774 # miss rate for ReadExReq accesses 2032system.cpu1.l2cache.ReadExReq_miss_rate::total 0.218774 # miss rate for ReadExReq accesses 2033system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081007 # miss rate for ReadCleanReq accesses 2034system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081007 # miss rate for ReadCleanReq accesses 2035system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.269929 # miss rate for ReadSharedReq accesses 2036system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.269929 # miss rate for ReadSharedReq accesses 2037system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.654945 # miss rate for InvalidateReq accesses 2038system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.654945 # miss rate for InvalidateReq accesses 2039system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for demand accesses 2040system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050749 # miss rate for demand accesses 2041system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081007 # miss rate for demand accesses 2042system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.257855 # miss rate for demand accesses 2043system.cpu1.l2cache.demand_miss_rate::total 0.138887 # miss rate for demand accesses 2044system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020577 # miss rate for overall accesses 2045system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050749 # miss rate for overall accesses 2046system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081007 # miss rate for overall accesses 2047system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.257855 # miss rate for overall accesses 2048system.cpu1.l2cache.overall_miss_rate::total 0.138887 # miss rate for overall accesses 2049system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average ReadReq miss latency 2050system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 55422.779233 # average ReadReq miss latency 2051system.cpu1.l2cache.ReadReq_avg_miss_latency::total 51854.316547 # average ReadReq miss latency 2052system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14003.943406 # average UpgradeReq miss latency 2053system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14003.943406 # average UpgradeReq miss latency 2054system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9979.622693 # average SCUpgradeReq miss latency 2055system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9979.622693 # average SCUpgradeReq miss latency 2056system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 734277.666667 # average SCUpgradeFailReq miss latency 2057system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 734277.666667 # average SCUpgradeFailReq miss latency 2058system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 63974.296720 # average ReadExReq miss latency 2059system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 63974.296720 # average ReadExReq miss latency 2060system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37302.049958 # average ReadCleanReq miss latency 2061system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37302.049958 # average ReadCleanReq miss latency 2062system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40121.298288 # average ReadSharedReq miss latency 2063system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40121.298288 # average ReadSharedReq miss latency 2064system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1355.544879 # average InvalidateReq miss latency 2065system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1355.544879 # average InvalidateReq miss latency 2066system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average overall miss latency 2067system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 55422.779233 # average overall miss latency 2068system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37302.049958 # average overall miss latency 2069system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44897.729655 # average overall miss latency 2070system.cpu1.l2cache.demand_avg_miss_latency::total 42289.087379 # average overall miss latency 2071system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 49550.507380 # average overall miss latency 2072system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 55422.779233 # average overall miss latency 2073system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37302.049958 # average overall miss latency 2074system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44897.729655 # average overall miss latency 2075system.cpu1.l2cache.overall_avg_miss_latency::total 42289.087379 # average overall miss latency 2076system.cpu1.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked 2077system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2078system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 2079system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2080system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 2081system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2082system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2083system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2084system.cpu1.l2cache.writebacks::writebacks 1388382 # number of writebacks 2085system.cpu1.l2cache.writebacks::total 1388382 # number of writebacks 2086system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2087system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2088system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 13745 # number of ReadExReq MSHR hits 2089system.cpu1.l2cache.ReadExReq_mshr_hits::total 13745 # number of ReadExReq MSHR hits 2090system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 8 # number of ReadCleanReq MSHR hits 2091system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits 2092system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1083 # number of ReadSharedReq MSHR hits 2093system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1083 # number of ReadSharedReq MSHR hits 2094system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits 2095system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 2096system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 2097system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 2098system.cpu1.l2cache.demand_mshr_hits::cpu1.data 14828 # number of demand (read+write) MSHR hits 2099system.cpu1.l2cache.demand_mshr_hits::total 14837 # number of demand (read+write) MSHR hits 2100system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 2101system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 2102system.cpu1.l2cache.overall_mshr_hits::cpu1.data 14828 # number of overall MSHR hits 2103system.cpu1.l2cache.overall_mshr_hits::total 14837 # number of overall MSHR hits 2104system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13008 # number of ReadReq MSHR misses 2105system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8397 # number of ReadReq MSHR misses 2106system.cpu1.l2cache.ReadReq_mshr_misses::total 21405 # number of ReadReq MSHR misses 2107system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 3 # number of WritebackDirty MSHR misses 2108system.cpu1.l2cache.WritebackDirty_mshr_misses::total 3 # number of WritebackDirty MSHR misses 2109system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 882624 # number of HardPFReq MSHR misses 2110system.cpu1.l2cache.HardPFReq_mshr_misses::total 882624 # number of HardPFReq MSHR misses 2111system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 242430 # number of UpgradeReq MSHR misses 2112system.cpu1.l2cache.UpgradeReq_mshr_misses::total 242430 # number of UpgradeReq MSHR misses 2113system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 206357 # number of SCUpgradeReq MSHR misses 2114system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 206357 # number of SCUpgradeReq MSHR misses 2115system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 2116system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 2117system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257524 # number of ReadExReq MSHR misses 2118system.cpu1.l2cache.ReadExReq_mshr_misses::total 257524 # number of ReadExReq MSHR misses 2119system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 749666 # number of ReadCleanReq MSHR misses 2120system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 749666 # number of ReadCleanReq MSHR misses 2121system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1082337 # number of ReadSharedReq MSHR misses 2122system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1082337 # number of ReadSharedReq MSHR misses 2123system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 317406 # number of InvalidateReq MSHR misses 2124system.cpu1.l2cache.InvalidateReq_mshr_misses::total 317406 # number of InvalidateReq MSHR misses 2125system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13008 # number of demand (read+write) MSHR misses 2126system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8397 # number of demand (read+write) MSHR misses 2127system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 749666 # number of demand (read+write) MSHR misses 2128system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1339861 # number of demand (read+write) MSHR misses 2129system.cpu1.l2cache.demand_mshr_misses::total 2110932 # number of demand (read+write) MSHR misses 2130system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13008 # number of overall MSHR misses 2131system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8397 # number of overall MSHR misses 2132system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 749666 # number of overall MSHR misses 2133system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1339861 # number of overall MSHR misses 2134system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 882624 # number of overall MSHR misses 2135system.cpu1.l2cache.overall_mshr_misses::total 2993556 # number of overall MSHR misses 2136system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2137system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable 2138system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23335 # number of ReadReq MSHR uncacheable 2139system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable 2140system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable 2141system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2142system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses 2143system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 45571 # number of overall MSHR uncacheable misses 2144system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of ReadReq MSHR miss cycles 2145system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 415038000 # number of ReadReq MSHR miss cycles 2146system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 981543000 # number of ReadReq MSHR miss cycles 2147system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 64551953809 # number of HardPFReq MSHR miss cycles 2148system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 64551953809 # number of HardPFReq MSHR miss cycles 2149system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7440388995 # number of UpgradeReq MSHR miss cycles 2150system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7440388995 # number of UpgradeReq MSHR miss cycles 2151system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3978239996 # number of SCUpgradeReq MSHR miss cycles 2152system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3978239996 # number of SCUpgradeReq MSHR miss cycles 2153system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6134499 # number of SCUpgradeFailReq MSHR miss cycles 2154system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6134499 # number of SCUpgradeFailReq MSHR miss cycles 2155system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 13620219997 # number of ReadExReq MSHR miss cycles 2156system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 13620219997 # number of ReadExReq MSHR miss cycles 2157system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 23466170000 # number of ReadCleanReq MSHR miss cycles 2158system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 23466170000 # number of ReadCleanReq MSHR miss cycles 2159system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 36889013991 # number of ReadSharedReq MSHR miss cycles 2160system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 36889013991 # number of ReadSharedReq MSHR miss cycles 2161system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17653665500 # number of InvalidateReq MSHR miss cycles 2162system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17653665500 # number of InvalidateReq MSHR miss cycles 2163system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of demand (read+write) MSHR miss cycles 2164system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 415038000 # number of demand (read+write) MSHR miss cycles 2165system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 23466170000 # number of demand (read+write) MSHR miss cycles 2166system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 50509233988 # number of demand (read+write) MSHR miss cycles 2167system.cpu1.l2cache.demand_mshr_miss_latency::total 74956946988 # number of demand (read+write) MSHR miss cycles 2168system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 566505000 # number of overall MSHR miss cycles 2169system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 415038000 # number of overall MSHR miss cycles 2170system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 23466170000 # number of overall MSHR miss cycles 2171system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 50509233988 # number of overall MSHR miss cycles 2172system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 64551953809 # number of overall MSHR miss cycles 2173system.cpu1.l2cache.overall_mshr_miss_latency::total 139508900797 # number of overall MSHR miss cycles 2174system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12337000 # number of ReadReq MSHR uncacheable cycles 2175system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4106803500 # number of ReadReq MSHR uncacheable cycles 2176system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4119140500 # number of ReadReq MSHR uncacheable cycles 2177system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 4005950500 # number of WriteReq MSHR uncacheable cycles 2178system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 4005950500 # number of WriteReq MSHR uncacheable cycles 2179system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12337000 # number of overall MSHR uncacheable cycles 2180system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8112754000 # number of overall MSHR uncacheable cycles 2181system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8125091000 # number of overall MSHR uncacheable cycles 2182system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for ReadReq accesses 2183system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for ReadReq accesses 2184system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026835 # mshr miss rate for ReadReq accesses 2185system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 2186system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 2187system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2188system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2189system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996768 # mshr miss rate for UpgradeReq accesses 2190system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996768 # mshr miss rate for UpgradeReq accesses 2191system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2192system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2193system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2194system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2195system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207689 # mshr miss rate for ReadExReq accesses 2196system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207689 # mshr miss rate for ReadExReq accesses 2197system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for ReadCleanReq accesses 2198system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081006 # mshr miss rate for ReadCleanReq accesses 2199system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.269659 # mshr miss rate for ReadSharedReq accesses 2200system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.269659 # mshr miss rate for ReadSharedReq accesses 2201system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.654937 # mshr miss rate for InvalidateReq accesses 2202system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.654937 # mshr miss rate for InvalidateReq accesses 2203system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for demand accesses 2204system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for demand accesses 2205system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for demand accesses 2206system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for demand accesses 2207system.cpu1.l2cache.demand_mshr_miss_rate::total 0.137917 # mshr miss rate for demand accesses 2208system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020577 # mshr miss rate for overall accesses 2209system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050743 # mshr miss rate for overall accesses 2210system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081006 # mshr miss rate for overall accesses 2211system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255033 # mshr miss rate for overall accesses 2212system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2213system.cpu1.l2cache.overall_mshr_miss_rate::total 0.195584 # mshr miss rate for overall accesses 2214system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average ReadReq mshr miss latency 2215system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average ReadReq mshr miss latency 2216system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45855.781359 # average ReadReq mshr miss latency 2217system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average HardPFReq mshr miss latency 2218system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 73136.413477 # average HardPFReq mshr miss latency 2219system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30690.875696 # average UpgradeReq mshr miss latency 2220system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30690.875696 # average UpgradeReq mshr miss latency 2221system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19278.434926 # average SCUpgradeReq mshr miss latency 2222system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19278.434926 # average SCUpgradeReq mshr miss latency 2223system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 681611 # average SCUpgradeFailReq mshr miss latency 2224system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 681611 # average SCUpgradeFailReq mshr miss latency 2225system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52889.128769 # average ReadExReq mshr miss latency 2226system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52889.128769 # average ReadExReq mshr miss latency 2227system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average ReadCleanReq mshr miss latency 2228system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31302.166565 # average ReadCleanReq mshr miss latency 2229system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34082.743167 # average ReadSharedReq mshr miss latency 2230system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34082.743167 # average ReadSharedReq mshr miss latency 2231system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55618.562661 # average InvalidateReq mshr miss latency 2232system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55618.562661 # average InvalidateReq mshr miss latency 2233system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency 2234system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency 2235system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency 2236system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency 2237system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35508.934910 # average overall mshr miss latency 2238system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency 2239system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency 2240system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency 2241system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency 2242system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average overall mshr miss latency 2243system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 46603.070327 # average overall mshr miss latency 2244system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency 2245system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176697.508820 # average ReadReq mshr uncacheable latency 2246system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176521.984144 # average ReadReq mshr uncacheable latency 2247system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180156.075733 # average WriteReq mshr uncacheable latency 2248system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180156.075733 # average WriteReq mshr uncacheable latency 2249system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency 2250system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178388.539514 # average overall mshr uncacheable latency 2251system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673 # average overall mshr uncacheable latency 2252system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2253system.cpu1.toL2Bus.snoop_filter.tot_requests 30687781 # Total number of requests made to the snoop filter. 2254system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15695228 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2255system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2256system.cpu1.toL2Bus.snoop_filter.tot_snoops 2305562 # Total number of snoops made to the snoop filter. 2257system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2305078 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2258system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 484 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2259system.cpu1.toL2Bus.trans_dist::ReadReq 905031 # Transaction distribution 2260system.cpu1.toL2Bus.trans_dist::ReadResp 14265709 # Transaction distribution 2261system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 2262system.cpu1.toL2Bus.trans_dist::WriteReq 22236 # Transaction distribution 2263system.cpu1.toL2Bus.trans_dist::WriteResp 22236 # Transaction distribution 2264system.cpu1.toL2Bus.trans_dist::WritebackDirty 4974934 # Transaction distribution 2265system.cpu1.toL2Bus.trans_dist::WritebackClean 11314728 # Transaction distribution 2266system.cpu1.toL2Bus.trans_dist::CleanEvict 3212624 # Transaction distribution 2267system.cpu1.toL2Bus.trans_dist::HardPFReq 1143576 # Transaction distribution 2268system.cpu1.toL2Bus.trans_dist::UpgradeReq 456570 # Transaction distribution 2269system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 371810 # Transaction distribution 2270system.cpu1.toL2Bus.trans_dist::UpgradeResp 515155 # Transaction distribution 2271system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution 2272system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution 2273system.cpu1.toL2Bus.trans_dist::ReadExReq 1270102 # Transaction distribution 2274system.cpu1.toL2Bus.trans_dist::ReadExResp 1247161 # Transaction distribution 2275system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9254432 # Transaction distribution 2276system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5086529 # Transaction distribution 2277system.cpu1.toL2Bus.trans_dist::InvalidateReq 540215 # Transaction distribution 2278system.cpu1.toL2Bus.trans_dist::InvalidateResp 484636 # Transaction distribution 2279system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27762958 # Packet count per connected master and slave (bytes) 2280system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18273152 # Packet count per connected master and slave (bytes) 2281system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 349398 # Packet count per connected master and slave (bytes) 2282system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1329953 # Packet count per connected master and slave (bytes) 2283system.cpu1.toL2Bus.pkt_count::total 47715461 # Packet count per connected master and slave (bytes) 2284system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1184539712 # Cumulative packet size per connected master and slave (bytes) 2285system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703787179 # Cumulative packet size per connected master and slave (bytes) 2286system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1323840 # Cumulative packet size per connected master and slave (bytes) 2287system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5057400 # Cumulative packet size per connected master and slave (bytes) 2288system.cpu1.toL2Bus.pkt_size::total 1894708131 # Cumulative packet size per connected master and slave (bytes) 2289system.cpu1.toL2Bus.snoops 7537959 # Total snoops (count) 2290system.cpu1.toL2Bus.snoop_fanout::samples 23658040 # Request fanout histogram 2291system.cpu1.toL2Bus.snoop_fanout::mean 0.112405 # Request fanout histogram 2292system.cpu1.toL2Bus.snoop_fanout::stdev 0.315929 # Request fanout histogram 2293system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2294system.cpu1.toL2Bus.snoop_fanout::0 20999234 88.76% 88.76% # Request fanout histogram 2295system.cpu1.toL2Bus.snoop_fanout::1 2658322 11.24% 100.00% # Request fanout histogram 2296system.cpu1.toL2Bus.snoop_fanout::2 484 0.00% 100.00% # Request fanout histogram 2297system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2298system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2299system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2300system.cpu1.toL2Bus.snoop_fanout::total 23658040 # Request fanout histogram 2301system.cpu1.toL2Bus.reqLayer0.occupancy 30538190977 # Layer occupancy (ticks) 2302system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2303system.cpu1.toL2Bus.snoopLayer0.occupancy 182787124 # Layer occupancy (ticks) 2304system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2305system.cpu1.toL2Bus.respLayer0.occupancy 13885672200 # Layer occupancy (ticks) 2306system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2307system.cpu1.toL2Bus.respLayer1.occupancy 8385983653 # Layer occupancy (ticks) 2308system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2309system.cpu1.toL2Bus.respLayer2.occupancy 183975884 # Layer occupancy (ticks) 2310system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2311system.cpu1.toL2Bus.respLayer3.occupancy 697921212 # Layer occupancy (ticks) 2312system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2313system.iobus.trans_dist::ReadReq 40434 # Transaction distribution 2314system.iobus.trans_dist::ReadResp 40434 # Transaction distribution 2315system.iobus.trans_dist::WriteReq 136979 # Transaction distribution 2316system.iobus.trans_dist::WriteResp 136979 # Transaction distribution 2317system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47874 # Packet count per connected master and slave (bytes) 2318system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2319system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2320system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2321system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2322system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2323system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2324system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2325system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2326system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2327system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2328system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) 2329system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2330system.iobus.pkt_count_system.bridge.master::total 122964 # Packet count per connected master and slave (bytes) 2331system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes) 2332system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes) 2333system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2334system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2335system.iobus.pkt_count::total 354826 # Packet count per connected master and slave (bytes) 2336system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47894 # Cumulative packet size per connected master and slave (bytes) 2337system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2338system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2339system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2340system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2341system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2342system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2343system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2346system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2347system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) 2348system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2349system.iobus.pkt_size_system.bridge.master::total 156002 # Cumulative packet size per connected master and slave (bytes) 2350system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes) 2351system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes) 2352system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2353system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2354system.iobus.pkt_size::total 7513568 # Cumulative packet size per connected master and slave (bytes) 2355system.iobus.reqLayer0.occupancy 47273505 # Layer occupancy (ticks) 2356system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2357system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 2358system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2359system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 2360system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2361system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) 2362system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2363system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 2364system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2365system.iobus.reqLayer10.occupancy 8500 # Layer occupancy (ticks) 2366system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2367system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 2368system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2369system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 2370system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2371system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 2372system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2373system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) 2374system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2375system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 2376system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2377system.iobus.reqLayer23.occupancy 26273501 # Layer occupancy (ticks) 2378system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2379system.iobus.reqLayer24.occupancy 36398000 # Layer occupancy (ticks) 2380system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2381system.iobus.reqLayer25.occupancy 568842992 # Layer occupancy (ticks) 2382system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2383system.iobus.respLayer0.occupancy 92972000 # Layer occupancy (ticks) 2384system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2385system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks) 2386system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2387system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2388system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2389system.iocache.tags.replacements 115872 # number of replacements 2390system.iocache.tags.tagsinuse 11.252872 # Cycle average of tags in use 2391system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2392system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. 2393system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2394system.iocache.tags.warmup_cycle 9138217056000 # Cycle when the warmup percentage was hit. 2395system.iocache.tags.occ_blocks::realview.ethernet 3.833219 # Average occupied blocks per requestor 2396system.iocache.tags.occ_blocks::realview.ide 7.419652 # Average occupied blocks per requestor 2397system.iocache.tags.occ_percent::realview.ethernet 0.239576 # Average percentage of cache occupancy 2398system.iocache.tags.occ_percent::realview.ide 0.463728 # Average percentage of cache occupancy 2399system.iocache.tags.occ_percent::total 0.703304 # Average percentage of cache occupancy 2400system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2401system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2402system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2403system.iocache.tags.tag_accesses 1043376 # Number of tag accesses 2404system.iocache.tags.data_accesses 1043376 # Number of data accesses 2405system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2406system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses 2407system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses 2408system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2409system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2410system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2411system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2412system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2413system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses 2414system.iocache.demand_misses::total 8947 # number of demand (read+write) misses 2415system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2416system.iocache.overall_misses::realview.ide 8907 # number of overall misses 2417system.iocache.overall_misses::total 8947 # number of overall misses 2418system.iocache.ReadReq_miss_latency::realview.ethernet 5277000 # number of ReadReq miss cycles 2419system.iocache.ReadReq_miss_latency::realview.ide 1705079977 # number of ReadReq miss cycles 2420system.iocache.ReadReq_miss_latency::total 1710356977 # number of ReadReq miss cycles 2421system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2422system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2423system.iocache.WriteLineReq_miss_latency::realview.ide 13558851015 # number of WriteLineReq miss cycles 2424system.iocache.WriteLineReq_miss_latency::total 13558851015 # number of WriteLineReq miss cycles 2425system.iocache.demand_miss_latency::realview.ethernet 5646000 # number of demand (read+write) miss cycles 2426system.iocache.demand_miss_latency::realview.ide 1705079977 # number of demand (read+write) miss cycles 2427system.iocache.demand_miss_latency::total 1710725977 # number of demand (read+write) miss cycles 2428system.iocache.overall_miss_latency::realview.ethernet 5646000 # number of overall miss cycles 2429system.iocache.overall_miss_latency::realview.ide 1705079977 # number of overall miss cycles 2430system.iocache.overall_miss_latency::total 1710725977 # number of overall miss cycles 2431system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2432system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses) 2433system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses) 2434system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2435system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2436system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2437system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2438system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2439system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses 2440system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses 2441system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2442system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses 2443system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses 2444system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2445system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2446system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2447system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2448system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2449system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2450system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2451system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2452system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2453system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2454system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2455system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2456system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2457system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142621.621622 # average ReadReq miss latency 2458system.iocache.ReadReq_avg_miss_latency::realview.ide 191431.455821 # average ReadReq miss latency 2459system.iocache.ReadReq_avg_miss_latency::total 191229.536784 # average ReadReq miss latency 2460system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2461system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2462system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126737.185140 # average WriteLineReq miss latency 2463system.iocache.WriteLineReq_avg_miss_latency::total 126737.185140 # average WriteLineReq miss latency 2464system.iocache.demand_avg_miss_latency::realview.ethernet 141150 # average overall miss latency 2465system.iocache.demand_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency 2466system.iocache.demand_avg_miss_latency::total 191206.658880 # average overall miss latency 2467system.iocache.overall_avg_miss_latency::realview.ethernet 141150 # average overall miss latency 2468system.iocache.overall_avg_miss_latency::realview.ide 191431.455821 # average overall miss latency 2469system.iocache.overall_avg_miss_latency::total 191206.658880 # average overall miss latency 2470system.iocache.blocked_cycles::no_mshrs 35119 # number of cycles access was blocked 2471system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2472system.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked 2473system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2474system.iocache.avg_blocked_cycles::no_mshrs 10.011117 # average number of cycles each access was blocked 2475system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2476system.iocache.fast_writes 0 # number of fast writes performed 2477system.iocache.cache_copies 0 # number of cache copies performed 2478system.iocache.writebacks::writebacks 106950 # number of writebacks 2479system.iocache.writebacks::total 106950 # number of writebacks 2480system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2481system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses 2482system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses 2483system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2484system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2485system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2486system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2487system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2488system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses 2489system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses 2490system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2491system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses 2492system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses 2493system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3427000 # number of ReadReq MSHR miss cycles 2494system.iocache.ReadReq_mshr_miss_latency::realview.ide 1259729977 # number of ReadReq MSHR miss cycles 2495system.iocache.ReadReq_mshr_miss_latency::total 1263156977 # number of ReadReq MSHR miss cycles 2496system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2497system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2498system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203408528 # number of WriteLineReq MSHR miss cycles 2499system.iocache.WriteLineReq_mshr_miss_latency::total 8203408528 # number of WriteLineReq MSHR miss cycles 2500system.iocache.demand_mshr_miss_latency::realview.ethernet 3646000 # number of demand (read+write) MSHR miss cycles 2501system.iocache.demand_mshr_miss_latency::realview.ide 1259729977 # number of demand (read+write) MSHR miss cycles 2502system.iocache.demand_mshr_miss_latency::total 1263375977 # number of demand (read+write) MSHR miss cycles 2503system.iocache.overall_mshr_miss_latency::realview.ethernet 3646000 # number of overall MSHR miss cycles 2504system.iocache.overall_mshr_miss_latency::realview.ide 1259729977 # number of overall MSHR miss cycles 2505system.iocache.overall_mshr_miss_latency::total 1263375977 # number of overall MSHR miss cycles 2506system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2507system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2508system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2509system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2510system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2511system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2512system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2513system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2514system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2515system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2516system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2517system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2518system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2519system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92621.621622 # average ReadReq mshr miss latency 2520system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141431.455821 # average ReadReq mshr miss latency 2521system.iocache.ReadReq_avg_mshr_miss_latency::total 141229.536784 # average ReadReq mshr miss latency 2522system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2523system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2524system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76678.835415 # average WriteLineReq mshr miss latency 2525system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76678.835415 # average WriteLineReq mshr miss latency 2526system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency 2527system.iocache.demand_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency 2528system.iocache.demand_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency 2529system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91150 # average overall mshr miss latency 2530system.iocache.overall_avg_mshr_miss_latency::realview.ide 141431.455821 # average overall mshr miss latency 2531system.iocache.overall_avg_mshr_miss_latency::total 141206.658880 # average overall mshr miss latency 2532system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2533system.l2c.tags.replacements 1736304 # number of replacements 2534system.l2c.tags.tagsinuse 63595.107970 # Cycle average of tags in use 2535system.l2c.tags.total_refs 7296515 # Total number of references to valid blocks. 2536system.l2c.tags.sampled_refs 1796625 # Sample count of references to valid blocks. 2537system.l2c.tags.avg_refs 4.061234 # Average number of references to valid blocks. 2538system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. 2539system.l2c.tags.occ_blocks::writebacks 21438.357602 # Average occupied blocks per requestor 2540system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.623523 # Average occupied blocks per requestor 2541system.l2c.tags.occ_blocks::cpu0.itb.walker 216.352807 # Average occupied blocks per requestor 2542system.l2c.tags.occ_blocks::cpu0.inst 5273.180907 # Average occupied blocks per requestor 2543system.l2c.tags.occ_blocks::cpu0.data 7402.273131 # Average occupied blocks per requestor 2544system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10592.541457 # Average occupied blocks per requestor 2545system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.822853 # Average occupied blocks per requestor 2546system.l2c.tags.occ_blocks::cpu1.itb.walker 191.052659 # Average occupied blocks per requestor 2547system.l2c.tags.occ_blocks::cpu1.inst 3264.316466 # Average occupied blocks per requestor 2548system.l2c.tags.occ_blocks::cpu1.data 6229.486316 # Average occupied blocks per requestor 2549system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8664.100250 # Average occupied blocks per requestor 2550system.l2c.tags.occ_percent::writebacks 0.327123 # Average percentage of cache occupancy 2551system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy 2552system.l2c.tags.occ_percent::cpu0.itb.walker 0.003301 # Average percentage of cache occupancy 2553system.l2c.tags.occ_percent::cpu0.inst 0.080462 # Average percentage of cache occupancy 2554system.l2c.tags.occ_percent::cpu0.data 0.112950 # Average percentage of cache occupancy 2555system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.161629 # Average percentage of cache occupancy 2556system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002286 # Average percentage of cache occupancy 2557system.l2c.tags.occ_percent::cpu1.itb.walker 0.002915 # Average percentage of cache occupancy 2558system.l2c.tags.occ_percent::cpu1.inst 0.049810 # Average percentage of cache occupancy 2559system.l2c.tags.occ_percent::cpu1.data 0.095054 # Average percentage of cache occupancy 2560system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132204 # Average percentage of cache occupancy 2561system.l2c.tags.occ_percent::total 0.970384 # Average percentage of cache occupancy 2562system.l2c.tags.occ_task_id_blocks::1022 8701 # Occupied blocks per task id 2563system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id 2564system.l2c.tags.occ_task_id_blocks::1024 51426 # Occupied blocks per task id 2565system.l2c.tags.age_task_id_blocks_1022::0 62 # Occupied blocks per task id 2566system.l2c.tags.age_task_id_blocks_1022::1 67 # Occupied blocks per task id 2567system.l2c.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id 2568system.l2c.tags.age_task_id_blocks_1022::3 1394 # Occupied blocks per task id 2569system.l2c.tags.age_task_id_blocks_1022::4 6925 # Occupied blocks per task id 2570system.l2c.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 2571system.l2c.tags.age_task_id_blocks_1023::4 186 # Occupied blocks per task id 2572system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 2573system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id 2574system.l2c.tags.age_task_id_blocks_1024::2 2651 # Occupied blocks per task id 2575system.l2c.tags.age_task_id_blocks_1024::3 12885 # Occupied blocks per task id 2576system.l2c.tags.age_task_id_blocks_1024::4 35470 # Occupied blocks per task id 2577system.l2c.tags.occ_task_id_percent::1022 0.132767 # Percentage of cache occupancy per task id 2578system.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id 2579system.l2c.tags.occ_task_id_percent::1024 0.784698 # Percentage of cache occupancy per task id 2580system.l2c.tags.tag_accesses 90467673 # Number of tag accesses 2581system.l2c.tags.data_accesses 90467673 # Number of data accesses 2582system.l2c.WritebackDirty_hits::writebacks 3161640 # number of WritebackDirty hits 2583system.l2c.WritebackDirty_hits::total 3161640 # number of WritebackDirty hits 2584system.l2c.UpgradeReq_hits::cpu0.data 190042 # number of UpgradeReq hits 2585system.l2c.UpgradeReq_hits::cpu1.data 150318 # number of UpgradeReq hits 2586system.l2c.UpgradeReq_hits::total 340360 # number of UpgradeReq hits 2587system.l2c.SCUpgradeReq_hits::cpu0.data 46175 # number of SCUpgradeReq hits 2588system.l2c.SCUpgradeReq_hits::cpu1.data 40691 # number of SCUpgradeReq hits 2589system.l2c.SCUpgradeReq_hits::total 86866 # number of SCUpgradeReq hits 2590system.l2c.ReadExReq_hits::cpu0.data 66080 # number of ReadExReq hits 2591system.l2c.ReadExReq_hits::cpu1.data 54849 # number of ReadExReq hits 2592system.l2c.ReadExReq_hits::total 120929 # number of ReadExReq hits 2593system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7647 # number of ReadSharedReq hits 2594system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4987 # number of ReadSharedReq hits 2595system.l2c.ReadSharedReq_hits::cpu0.inst 699090 # number of ReadSharedReq hits 2596system.l2c.ReadSharedReq_hits::cpu0.data 694199 # number of ReadSharedReq hits 2597system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 343045 # number of ReadSharedReq hits 2598system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6831 # number of ReadSharedReq hits 2599system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3980 # number of ReadSharedReq hits 2600system.l2c.ReadSharedReq_hits::cpu1.inst 688497 # number of ReadSharedReq hits 2601system.l2c.ReadSharedReq_hits::cpu1.data 675339 # number of ReadSharedReq hits 2602system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 302251 # number of ReadSharedReq hits 2603system.l2c.ReadSharedReq_hits::total 3425866 # number of ReadSharedReq hits 2604system.l2c.InvalidateReq_hits::cpu0.data 143577 # number of InvalidateReq hits 2605system.l2c.InvalidateReq_hits::cpu1.data 133038 # number of InvalidateReq hits 2606system.l2c.InvalidateReq_hits::total 276615 # number of InvalidateReq hits 2607system.l2c.demand_hits::cpu0.dtb.walker 7647 # number of demand (read+write) hits 2608system.l2c.demand_hits::cpu0.itb.walker 4987 # number of demand (read+write) hits 2609system.l2c.demand_hits::cpu0.inst 699090 # number of demand (read+write) hits 2610system.l2c.demand_hits::cpu0.data 760279 # number of demand (read+write) hits 2611system.l2c.demand_hits::cpu0.l2cache.prefetcher 343045 # number of demand (read+write) hits 2612system.l2c.demand_hits::cpu1.dtb.walker 6831 # number of demand (read+write) hits 2613system.l2c.demand_hits::cpu1.itb.walker 3980 # number of demand (read+write) hits 2614system.l2c.demand_hits::cpu1.inst 688497 # number of demand (read+write) hits 2615system.l2c.demand_hits::cpu1.data 730188 # number of demand (read+write) hits 2616system.l2c.demand_hits::cpu1.l2cache.prefetcher 302251 # number of demand (read+write) hits 2617system.l2c.demand_hits::total 3546795 # number of demand (read+write) hits 2618system.l2c.overall_hits::cpu0.dtb.walker 7647 # number of overall hits 2619system.l2c.overall_hits::cpu0.itb.walker 4987 # number of overall hits 2620system.l2c.overall_hits::cpu0.inst 699090 # number of overall hits 2621system.l2c.overall_hits::cpu0.data 760279 # number of overall hits 2622system.l2c.overall_hits::cpu0.l2cache.prefetcher 343045 # number of overall hits 2623system.l2c.overall_hits::cpu1.dtb.walker 6831 # number of overall hits 2624system.l2c.overall_hits::cpu1.itb.walker 3980 # number of overall hits 2625system.l2c.overall_hits::cpu1.inst 688497 # number of overall hits 2626system.l2c.overall_hits::cpu1.data 730188 # number of overall hits 2627system.l2c.overall_hits::cpu1.l2cache.prefetcher 302251 # number of overall hits 2628system.l2c.overall_hits::total 3546795 # number of overall hits 2629system.l2c.UpgradeReq_misses::cpu0.data 66937 # number of UpgradeReq misses 2630system.l2c.UpgradeReq_misses::cpu1.data 62230 # number of UpgradeReq misses 2631system.l2c.UpgradeReq_misses::total 129167 # number of UpgradeReq misses 2632system.l2c.SCUpgradeReq_misses::cpu0.data 13492 # number of SCUpgradeReq misses 2633system.l2c.SCUpgradeReq_misses::cpu1.data 12585 # number of SCUpgradeReq misses 2634system.l2c.SCUpgradeReq_misses::total 26077 # number of SCUpgradeReq misses 2635system.l2c.ReadExReq_misses::cpu0.data 88765 # number of ReadExReq misses 2636system.l2c.ReadExReq_misses::cpu1.data 66782 # number of ReadExReq misses 2637system.l2c.ReadExReq_misses::total 155547 # number of ReadExReq misses 2638system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3643 # number of ReadSharedReq misses 2639system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3291 # number of ReadSharedReq misses 2640system.l2c.ReadSharedReq_misses::cpu0.inst 71874 # number of ReadSharedReq misses 2641system.l2c.ReadSharedReq_misses::cpu0.data 188609 # number of ReadSharedReq misses 2642system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 283713 # number of ReadSharedReq misses 2643system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2600 # number of ReadSharedReq misses 2644system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2065 # number of ReadSharedReq misses 2645system.l2c.ReadSharedReq_misses::cpu1.inst 61168 # number of ReadSharedReq misses 2646system.l2c.ReadSharedReq_misses::cpu1.data 131288 # number of ReadSharedReq misses 2647system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 331034 # number of ReadSharedReq misses 2648system.l2c.ReadSharedReq_misses::total 1079285 # number of ReadSharedReq misses 2649system.l2c.InvalidateReq_misses::cpu0.data 420248 # number of InvalidateReq misses 2650system.l2c.InvalidateReq_misses::cpu1.data 172062 # number of InvalidateReq misses 2651system.l2c.InvalidateReq_misses::total 592310 # number of InvalidateReq misses 2652system.l2c.demand_misses::cpu0.dtb.walker 3643 # number of demand (read+write) misses 2653system.l2c.demand_misses::cpu0.itb.walker 3291 # number of demand (read+write) misses 2654system.l2c.demand_misses::cpu0.inst 71874 # number of demand (read+write) misses 2655system.l2c.demand_misses::cpu0.data 277374 # number of demand (read+write) misses 2656system.l2c.demand_misses::cpu0.l2cache.prefetcher 283713 # number of demand (read+write) misses 2657system.l2c.demand_misses::cpu1.dtb.walker 2600 # number of demand (read+write) misses 2658system.l2c.demand_misses::cpu1.itb.walker 2065 # number of demand (read+write) misses 2659system.l2c.demand_misses::cpu1.inst 61168 # number of demand (read+write) misses 2660system.l2c.demand_misses::cpu1.data 198070 # number of demand (read+write) misses 2661system.l2c.demand_misses::cpu1.l2cache.prefetcher 331034 # number of demand (read+write) misses 2662system.l2c.demand_misses::total 1234832 # number of demand (read+write) misses 2663system.l2c.overall_misses::cpu0.dtb.walker 3643 # number of overall misses 2664system.l2c.overall_misses::cpu0.itb.walker 3291 # number of overall misses 2665system.l2c.overall_misses::cpu0.inst 71874 # number of overall misses 2666system.l2c.overall_misses::cpu0.data 277374 # number of overall misses 2667system.l2c.overall_misses::cpu0.l2cache.prefetcher 283713 # number of overall misses 2668system.l2c.overall_misses::cpu1.dtb.walker 2600 # number of overall misses 2669system.l2c.overall_misses::cpu1.itb.walker 2065 # number of overall misses 2670system.l2c.overall_misses::cpu1.inst 61168 # number of overall misses 2671system.l2c.overall_misses::cpu1.data 198070 # number of overall misses 2672system.l2c.overall_misses::cpu1.l2cache.prefetcher 331034 # number of overall misses 2673system.l2c.overall_misses::total 1234832 # number of overall misses 2674system.l2c.UpgradeReq_miss_latency::cpu0.data 1172514500 # number of UpgradeReq miss cycles 2675system.l2c.UpgradeReq_miss_latency::cpu1.data 1079518500 # number of UpgradeReq miss cycles 2676system.l2c.UpgradeReq_miss_latency::total 2252033000 # number of UpgradeReq miss cycles 2677system.l2c.SCUpgradeReq_miss_latency::cpu0.data 202156500 # number of SCUpgradeReq miss cycles 2678system.l2c.SCUpgradeReq_miss_latency::cpu1.data 215769000 # number of SCUpgradeReq miss cycles 2679system.l2c.SCUpgradeReq_miss_latency::total 417925500 # number of SCUpgradeReq miss cycles 2680system.l2c.ReadExReq_miss_latency::cpu0.data 12242204500 # number of ReadExReq miss cycles 2681system.l2c.ReadExReq_miss_latency::cpu1.data 9216523500 # number of ReadExReq miss cycles 2682system.l2c.ReadExReq_miss_latency::total 21458728000 # number of ReadExReq miss cycles 2683system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 512308500 # number of ReadSharedReq miss cycles 2684system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 464071000 # number of ReadSharedReq miss cycles 2685system.l2c.ReadSharedReq_miss_latency::cpu0.inst 9761528500 # number of ReadSharedReq miss cycles 2686system.l2c.ReadSharedReq_miss_latency::cpu0.data 26674163500 # number of ReadSharedReq miss cycles 2687system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of ReadSharedReq miss cycles 2688system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 367906000 # number of ReadSharedReq miss cycles 2689system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 298172500 # number of ReadSharedReq miss cycles 2690system.l2c.ReadSharedReq_miss_latency::cpu1.inst 8283610000 # number of ReadSharedReq miss cycles 2691system.l2c.ReadSharedReq_miss_latency::cpu1.data 18924327000 # number of ReadSharedReq miss cycles 2692system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of ReadSharedReq miss cycles 2693system.l2c.ReadSharedReq_miss_latency::total 172936434536 # number of ReadSharedReq miss cycles 2694system.l2c.InvalidateReq_miss_latency::cpu0.data 151369500 # number of InvalidateReq miss cycles 2695system.l2c.InvalidateReq_miss_latency::cpu1.data 160513500 # number of InvalidateReq miss cycles 2696system.l2c.InvalidateReq_miss_latency::total 311883000 # number of InvalidateReq miss cycles 2697system.l2c.demand_miss_latency::cpu0.dtb.walker 512308500 # number of demand (read+write) miss cycles 2698system.l2c.demand_miss_latency::cpu0.itb.walker 464071000 # number of demand (read+write) miss cycles 2699system.l2c.demand_miss_latency::cpu0.inst 9761528500 # number of demand (read+write) miss cycles 2700system.l2c.demand_miss_latency::cpu0.data 38916368000 # number of demand (read+write) miss cycles 2701system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of demand (read+write) miss cycles 2702system.l2c.demand_miss_latency::cpu1.dtb.walker 367906000 # number of demand (read+write) miss cycles 2703system.l2c.demand_miss_latency::cpu1.itb.walker 298172500 # number of demand (read+write) miss cycles 2704system.l2c.demand_miss_latency::cpu1.inst 8283610000 # number of demand (read+write) miss cycles 2705system.l2c.demand_miss_latency::cpu1.data 28140850500 # number of demand (read+write) miss cycles 2706system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of demand (read+write) miss cycles 2707system.l2c.demand_miss_latency::total 194395162536 # number of demand (read+write) miss cycles 2708system.l2c.overall_miss_latency::cpu0.dtb.walker 512308500 # number of overall miss cycles 2709system.l2c.overall_miss_latency::cpu0.itb.walker 464071000 # number of overall miss cycles 2710system.l2c.overall_miss_latency::cpu0.inst 9761528500 # number of overall miss cycles 2711system.l2c.overall_miss_latency::cpu0.data 38916368000 # number of overall miss cycles 2712system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 48831200595 # number of overall miss cycles 2713system.l2c.overall_miss_latency::cpu1.dtb.walker 367906000 # number of overall miss cycles 2714system.l2c.overall_miss_latency::cpu1.itb.walker 298172500 # number of overall miss cycles 2715system.l2c.overall_miss_latency::cpu1.inst 8283610000 # number of overall miss cycles 2716system.l2c.overall_miss_latency::cpu1.data 28140850500 # number of overall miss cycles 2717system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 58819146941 # number of overall miss cycles 2718system.l2c.overall_miss_latency::total 194395162536 # number of overall miss cycles 2719system.l2c.WritebackDirty_accesses::writebacks 3161640 # number of WritebackDirty accesses(hits+misses) 2720system.l2c.WritebackDirty_accesses::total 3161640 # number of WritebackDirty accesses(hits+misses) 2721system.l2c.UpgradeReq_accesses::cpu0.data 256979 # number of UpgradeReq accesses(hits+misses) 2722system.l2c.UpgradeReq_accesses::cpu1.data 212548 # number of UpgradeReq accesses(hits+misses) 2723system.l2c.UpgradeReq_accesses::total 469527 # number of UpgradeReq accesses(hits+misses) 2724system.l2c.SCUpgradeReq_accesses::cpu0.data 59667 # number of SCUpgradeReq accesses(hits+misses) 2725system.l2c.SCUpgradeReq_accesses::cpu1.data 53276 # number of SCUpgradeReq accesses(hits+misses) 2726system.l2c.SCUpgradeReq_accesses::total 112943 # number of SCUpgradeReq accesses(hits+misses) 2727system.l2c.ReadExReq_accesses::cpu0.data 154845 # number of ReadExReq accesses(hits+misses) 2728system.l2c.ReadExReq_accesses::cpu1.data 121631 # number of ReadExReq accesses(hits+misses) 2729system.l2c.ReadExReq_accesses::total 276476 # number of ReadExReq accesses(hits+misses) 2730system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 11290 # number of ReadSharedReq accesses(hits+misses) 2731system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8278 # number of ReadSharedReq accesses(hits+misses) 2732system.l2c.ReadSharedReq_accesses::cpu0.inst 770964 # number of ReadSharedReq accesses(hits+misses) 2733system.l2c.ReadSharedReq_accesses::cpu0.data 882808 # number of ReadSharedReq accesses(hits+misses) 2734system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 626758 # number of ReadSharedReq accesses(hits+misses) 2735system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9431 # number of ReadSharedReq accesses(hits+misses) 2736system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6045 # number of ReadSharedReq accesses(hits+misses) 2737system.l2c.ReadSharedReq_accesses::cpu1.inst 749665 # number of ReadSharedReq accesses(hits+misses) 2738system.l2c.ReadSharedReq_accesses::cpu1.data 806627 # number of ReadSharedReq accesses(hits+misses) 2739system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 633285 # number of ReadSharedReq accesses(hits+misses) 2740system.l2c.ReadSharedReq_accesses::total 4505151 # number of ReadSharedReq accesses(hits+misses) 2741system.l2c.InvalidateReq_accesses::cpu0.data 563825 # number of InvalidateReq accesses(hits+misses) 2742system.l2c.InvalidateReq_accesses::cpu1.data 305100 # number of InvalidateReq accesses(hits+misses) 2743system.l2c.InvalidateReq_accesses::total 868925 # number of InvalidateReq accesses(hits+misses) 2744system.l2c.demand_accesses::cpu0.dtb.walker 11290 # number of demand (read+write) accesses 2745system.l2c.demand_accesses::cpu0.itb.walker 8278 # number of demand (read+write) accesses 2746system.l2c.demand_accesses::cpu0.inst 770964 # number of demand (read+write) accesses 2747system.l2c.demand_accesses::cpu0.data 1037653 # number of demand (read+write) accesses 2748system.l2c.demand_accesses::cpu0.l2cache.prefetcher 626758 # number of demand (read+write) accesses 2749system.l2c.demand_accesses::cpu1.dtb.walker 9431 # number of demand (read+write) accesses 2750system.l2c.demand_accesses::cpu1.itb.walker 6045 # number of demand (read+write) accesses 2751system.l2c.demand_accesses::cpu1.inst 749665 # number of demand (read+write) accesses 2752system.l2c.demand_accesses::cpu1.data 928258 # number of demand (read+write) accesses 2753system.l2c.demand_accesses::cpu1.l2cache.prefetcher 633285 # number of demand (read+write) accesses 2754system.l2c.demand_accesses::total 4781627 # number of demand (read+write) accesses 2755system.l2c.overall_accesses::cpu0.dtb.walker 11290 # number of overall (read+write) accesses 2756system.l2c.overall_accesses::cpu0.itb.walker 8278 # number of overall (read+write) accesses 2757system.l2c.overall_accesses::cpu0.inst 770964 # number of overall (read+write) accesses 2758system.l2c.overall_accesses::cpu0.data 1037653 # number of overall (read+write) accesses 2759system.l2c.overall_accesses::cpu0.l2cache.prefetcher 626758 # number of overall (read+write) accesses 2760system.l2c.overall_accesses::cpu1.dtb.walker 9431 # number of overall (read+write) accesses 2761system.l2c.overall_accesses::cpu1.itb.walker 6045 # number of overall (read+write) accesses 2762system.l2c.overall_accesses::cpu1.inst 749665 # number of overall (read+write) accesses 2763system.l2c.overall_accesses::cpu1.data 928258 # number of overall (read+write) accesses 2764system.l2c.overall_accesses::cpu1.l2cache.prefetcher 633285 # number of overall (read+write) accesses 2765system.l2c.overall_accesses::total 4781627 # number of overall (read+write) accesses 2766system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260477 # miss rate for UpgradeReq accesses 2767system.l2c.UpgradeReq_miss_rate::cpu1.data 0.292781 # miss rate for UpgradeReq accesses 2768system.l2c.UpgradeReq_miss_rate::total 0.275100 # miss rate for UpgradeReq accesses 2769system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.226122 # miss rate for SCUpgradeReq accesses 2770system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.236223 # miss rate for SCUpgradeReq accesses 2771system.l2c.SCUpgradeReq_miss_rate::total 0.230886 # miss rate for SCUpgradeReq accesses 2772system.l2c.ReadExReq_miss_rate::cpu0.data 0.573251 # miss rate for ReadExReq accesses 2773system.l2c.ReadExReq_miss_rate::cpu1.data 0.549054 # miss rate for ReadExReq accesses 2774system.l2c.ReadExReq_miss_rate::total 0.562606 # miss rate for ReadExReq accesses 2775system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for ReadSharedReq accesses 2776system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.397560 # miss rate for ReadSharedReq accesses 2777system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.093226 # miss rate for ReadSharedReq accesses 2778system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213647 # miss rate for ReadSharedReq accesses 2779system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for ReadSharedReq accesses 2780system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for ReadSharedReq accesses 2781system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.341605 # miss rate for ReadSharedReq accesses 2782system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.081594 # miss rate for ReadSharedReq accesses 2783system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.162762 # miss rate for ReadSharedReq accesses 2784system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for ReadSharedReq accesses 2785system.l2c.ReadSharedReq_miss_rate::total 0.239567 # miss rate for ReadSharedReq accesses 2786system.l2c.InvalidateReq_miss_rate::cpu0.data 0.745352 # miss rate for InvalidateReq accesses 2787system.l2c.InvalidateReq_miss_rate::cpu1.data 0.563953 # miss rate for InvalidateReq accesses 2788system.l2c.InvalidateReq_miss_rate::total 0.681658 # miss rate for InvalidateReq accesses 2789system.l2c.demand_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for demand accesses 2790system.l2c.demand_miss_rate::cpu0.itb.walker 0.397560 # miss rate for demand accesses 2791system.l2c.demand_miss_rate::cpu0.inst 0.093226 # miss rate for demand accesses 2792system.l2c.demand_miss_rate::cpu0.data 0.267309 # miss rate for demand accesses 2793system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for demand accesses 2794system.l2c.demand_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for demand accesses 2795system.l2c.demand_miss_rate::cpu1.itb.walker 0.341605 # miss rate for demand accesses 2796system.l2c.demand_miss_rate::cpu1.inst 0.081594 # miss rate for demand accesses 2797system.l2c.demand_miss_rate::cpu1.data 0.213378 # miss rate for demand accesses 2798system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for demand accesses 2799system.l2c.demand_miss_rate::total 0.258245 # miss rate for demand accesses 2800system.l2c.overall_miss_rate::cpu0.dtb.walker 0.322675 # miss rate for overall accesses 2801system.l2c.overall_miss_rate::cpu0.itb.walker 0.397560 # miss rate for overall accesses 2802system.l2c.overall_miss_rate::cpu0.inst 0.093226 # miss rate for overall accesses 2803system.l2c.overall_miss_rate::cpu0.data 0.267309 # miss rate for overall accesses 2804system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.452668 # miss rate for overall accesses 2805system.l2c.overall_miss_rate::cpu1.dtb.walker 0.275687 # miss rate for overall accesses 2806system.l2c.overall_miss_rate::cpu1.itb.walker 0.341605 # miss rate for overall accesses 2807system.l2c.overall_miss_rate::cpu1.inst 0.081594 # miss rate for overall accesses 2808system.l2c.overall_miss_rate::cpu1.data 0.213378 # miss rate for overall accesses 2809system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.522725 # miss rate for overall accesses 2810system.l2c.overall_miss_rate::total 0.258245 # miss rate for overall accesses 2811system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17516.687333 # average UpgradeReq miss latency 2812system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17347.236060 # average UpgradeReq miss latency 2813system.l2c.UpgradeReq_avg_miss_latency::total 17435.049200 # average UpgradeReq miss latency 2814system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14983.434628 # average SCUpgradeReq miss latency 2815system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17144.934446 # average SCUpgradeReq miss latency 2816system.l2c.SCUpgradeReq_avg_miss_latency::total 16026.594317 # average SCUpgradeReq miss latency 2817system.l2c.ReadExReq_avg_miss_latency::cpu0.data 137917.022475 # average ReadExReq miss latency 2818system.l2c.ReadExReq_avg_miss_latency::cpu1.data 138009.096763 # average ReadExReq miss latency 2819system.l2c.ReadExReq_avg_miss_latency::total 137956.553325 # average ReadExReq miss latency 2820system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average ReadSharedReq miss latency 2821system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141012.154360 # average ReadSharedReq miss latency 2822system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135814.460027 # average ReadSharedReq miss latency 2823system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141425.719345 # average ReadSharedReq miss latency 2824system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average ReadSharedReq miss latency 2825system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average ReadSharedReq miss latency 2826system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144393.462470 # average ReadSharedReq miss latency 2827system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135423.914465 # average ReadSharedReq miss latency 2828system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144143.615563 # average ReadSharedReq miss latency 2829system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average ReadSharedReq miss latency 2830system.l2c.ReadSharedReq_avg_miss_latency::total 160232.408063 # average ReadSharedReq miss latency 2831system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 360.190887 # average InvalidateReq miss latency 2832system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 932.881752 # average InvalidateReq miss latency 2833system.l2c.InvalidateReq_avg_miss_latency::total 526.553663 # average InvalidateReq miss latency 2834system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average overall miss latency 2835system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141012.154360 # average overall miss latency 2836system.l2c.demand_avg_miss_latency::cpu0.inst 135814.460027 # average overall miss latency 2837system.l2c.demand_avg_miss_latency::cpu0.data 140302.869050 # average overall miss latency 2838system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average overall miss latency 2839system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average overall miss latency 2840system.l2c.demand_avg_miss_latency::cpu1.itb.walker 144393.462470 # average overall miss latency 2841system.l2c.demand_avg_miss_latency::cpu1.inst 135423.914465 # average overall miss latency 2842system.l2c.demand_avg_miss_latency::cpu1.data 142075.278942 # average overall miss latency 2843system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average overall miss latency 2844system.l2c.demand_avg_miss_latency::total 157426.404998 # average overall miss latency 2845system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140628.191051 # average overall miss latency 2846system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141012.154360 # average overall miss latency 2847system.l2c.overall_avg_miss_latency::cpu0.inst 135814.460027 # average overall miss latency 2848system.l2c.overall_avg_miss_latency::cpu0.data 140302.869050 # average overall miss latency 2849system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059 # average overall miss latency 2850system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141502.307692 # average overall miss latency 2851system.l2c.overall_avg_miss_latency::cpu1.itb.walker 144393.462470 # average overall miss latency 2852system.l2c.overall_avg_miss_latency::cpu1.inst 135423.914465 # average overall miss latency 2853system.l2c.overall_avg_miss_latency::cpu1.data 142075.278942 # average overall miss latency 2854system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839 # average overall miss latency 2855system.l2c.overall_avg_miss_latency::total 157426.404998 # average overall miss latency 2856system.l2c.blocked_cycles::no_mshrs 1204 # number of cycles access was blocked 2857system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2858system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked 2859system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2860system.l2c.avg_blocked_cycles::no_mshrs 240.800000 # average number of cycles each access was blocked 2861system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2862system.l2c.fast_writes 0 # number of fast writes performed 2863system.l2c.cache_copies 0 # number of cache copies performed 2864system.l2c.writebacks::writebacks 1344961 # number of writebacks 2865system.l2c.writebacks::total 1344961 # number of writebacks 2866system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits 2867system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 474 # number of ReadSharedReq MSHR hits 2868system.l2c.ReadSharedReq_mshr_hits::cpu0.data 106 # number of ReadSharedReq MSHR hits 2869system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 35 # number of ReadSharedReq MSHR hits 2870system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 389 # number of ReadSharedReq MSHR hits 2871system.l2c.ReadSharedReq_mshr_hits::cpu1.data 102 # number of ReadSharedReq MSHR hits 2872system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadSharedReq MSHR hits 2873system.l2c.ReadSharedReq_mshr_hits::total 1122 # number of ReadSharedReq MSHR hits 2874system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 2875system.l2c.demand_mshr_hits::cpu0.inst 474 # number of demand (read+write) MSHR hits 2876system.l2c.demand_mshr_hits::cpu0.data 106 # number of demand (read+write) MSHR hits 2877system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 35 # number of demand (read+write) MSHR hits 2878system.l2c.demand_mshr_hits::cpu1.inst 389 # number of demand (read+write) MSHR hits 2879system.l2c.demand_mshr_hits::cpu1.data 102 # number of demand (read+write) MSHR hits 2880system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits 2881system.l2c.demand_mshr_hits::total 1122 # number of demand (read+write) MSHR hits 2882system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 2883system.l2c.overall_mshr_hits::cpu0.inst 474 # number of overall MSHR hits 2884system.l2c.overall_mshr_hits::cpu0.data 106 # number of overall MSHR hits 2885system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 35 # number of overall MSHR hits 2886system.l2c.overall_mshr_hits::cpu1.inst 389 # number of overall MSHR hits 2887system.l2c.overall_mshr_hits::cpu1.data 102 # number of overall MSHR hits 2888system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits 2889system.l2c.overall_mshr_hits::total 1122 # number of overall MSHR hits 2890system.l2c.CleanEvict_mshr_misses::writebacks 71582 # number of CleanEvict MSHR misses 2891system.l2c.CleanEvict_mshr_misses::total 71582 # number of CleanEvict MSHR misses 2892system.l2c.UpgradeReq_mshr_misses::cpu0.data 66937 # number of UpgradeReq MSHR misses 2893system.l2c.UpgradeReq_mshr_misses::cpu1.data 62230 # number of UpgradeReq MSHR misses 2894system.l2c.UpgradeReq_mshr_misses::total 129167 # number of UpgradeReq MSHR misses 2895system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13492 # number of SCUpgradeReq MSHR misses 2896system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12585 # number of SCUpgradeReq MSHR misses 2897system.l2c.SCUpgradeReq_mshr_misses::total 26077 # number of SCUpgradeReq MSHR misses 2898system.l2c.ReadExReq_mshr_misses::cpu0.data 88765 # number of ReadExReq MSHR misses 2899system.l2c.ReadExReq_mshr_misses::cpu1.data 66782 # number of ReadExReq MSHR misses 2900system.l2c.ReadExReq_mshr_misses::total 155547 # number of ReadExReq MSHR misses 2901system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3642 # number of ReadSharedReq MSHR misses 2902system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3291 # number of ReadSharedReq MSHR misses 2903system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 71400 # number of ReadSharedReq MSHR misses 2904system.l2c.ReadSharedReq_mshr_misses::cpu0.data 188503 # number of ReadSharedReq MSHR misses 2905system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 283678 # number of ReadSharedReq MSHR misses 2906system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2600 # number of ReadSharedReq MSHR misses 2907system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2065 # number of ReadSharedReq MSHR misses 2908system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 60779 # number of ReadSharedReq MSHR misses 2909system.l2c.ReadSharedReq_mshr_misses::cpu1.data 131186 # number of ReadSharedReq MSHR misses 2910system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 331019 # number of ReadSharedReq MSHR misses 2911system.l2c.ReadSharedReq_mshr_misses::total 1078163 # number of ReadSharedReq MSHR misses 2912system.l2c.InvalidateReq_mshr_misses::cpu0.data 420248 # number of InvalidateReq MSHR misses 2913system.l2c.InvalidateReq_mshr_misses::cpu1.data 172062 # number of InvalidateReq MSHR misses 2914system.l2c.InvalidateReq_mshr_misses::total 592310 # number of InvalidateReq MSHR misses 2915system.l2c.demand_mshr_misses::cpu0.dtb.walker 3642 # number of demand (read+write) MSHR misses 2916system.l2c.demand_mshr_misses::cpu0.itb.walker 3291 # number of demand (read+write) MSHR misses 2917system.l2c.demand_mshr_misses::cpu0.inst 71400 # number of demand (read+write) MSHR misses 2918system.l2c.demand_mshr_misses::cpu0.data 277268 # number of demand (read+write) MSHR misses 2919system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 283678 # number of demand (read+write) MSHR misses 2920system.l2c.demand_mshr_misses::cpu1.dtb.walker 2600 # number of demand (read+write) MSHR misses 2921system.l2c.demand_mshr_misses::cpu1.itb.walker 2065 # number of demand (read+write) MSHR misses 2922system.l2c.demand_mshr_misses::cpu1.inst 60779 # number of demand (read+write) MSHR misses 2923system.l2c.demand_mshr_misses::cpu1.data 197968 # number of demand (read+write) MSHR misses 2924system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 331019 # number of demand (read+write) MSHR misses 2925system.l2c.demand_mshr_misses::total 1233710 # number of demand (read+write) MSHR misses 2926system.l2c.overall_mshr_misses::cpu0.dtb.walker 3642 # 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number of ReadReq MSHR uncacheable 2939system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 2940system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23240 # number of ReadReq MSHR uncacheable 2941system.l2c.ReadReq_mshr_uncacheable::total 90728 # number of ReadReq MSHR uncacheable 2942system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15976 # number of WriteReq MSHR uncacheable 2943system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable 2944system.l2c.WriteReq_mshr_uncacheable::total 38212 # number of WriteReq MSHR uncacheable 2945system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 2946system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31062 # number of overall MSHR uncacheable misses 2947system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 2948system.l2c.overall_mshr_uncacheable_misses::cpu1.data 45476 # number of overall MSHR uncacheable misses 2949system.l2c.overall_mshr_uncacheable_misses::total 128940 # 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number of ReadSharedReq MSHR miss cycles 2960system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 431144036 # number of ReadSharedReq MSHR miss cycles 2961system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8990432141 # number of ReadSharedReq MSHR miss cycles 2962system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 24773636898 # number of ReadSharedReq MSHR miss cycles 2963system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 45987586011 # number of ReadSharedReq MSHR miss cycles 2964system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 341894523 # number of ReadSharedReq MSHR miss cycles 2965system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 277514518 # number of ReadSharedReq MSHR miss cycles 2966system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 7629341915 # number of ReadSharedReq MSHR miss cycles 2967system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17597986348 # number of ReadSharedReq MSHR miss cycles 2968system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 55505284382 # number of ReadSharedReq MSHR miss cycles 2969system.l2c.ReadSharedReq_mshr_miss_latency::total 162010566311 # number of ReadSharedReq MSHR miss cycles 2970system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 29454261500 # number of InvalidateReq MSHR miss cycles 2971system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 11918839498 # number of InvalidateReq MSHR miss cycles 2972system.l2c.InvalidateReq_mshr_miss_latency::total 41373100998 # number of InvalidateReq MSHR miss cycles 2973system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 475745539 # number of demand (read+write) MSHR miss cycles 2974system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 431144036 # number of demand (read+write) MSHR miss cycles 2975system.l2c.demand_mshr_miss_latency::cpu0.inst 8990432141 # number of demand (read+write) MSHR miss cycles 2976system.l2c.demand_mshr_miss_latency::cpu0.data 36127781624 # number of demand (read+write) MSHR miss cycles 2977system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 45987586011 # number of demand (read+write) MSHR miss cycles 2978system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 341894523 # number of demand (read+write) MSHR miss cycles 2979system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 277514518 # number of demand (read+write) MSHR miss cycles 2980system.l2c.demand_mshr_miss_latency::cpu1.inst 7629341915 # number of demand (read+write) MSHR miss cycles 2981system.l2c.demand_mshr_miss_latency::cpu1.data 26146389369 # number of demand (read+write) MSHR miss cycles 2982system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 55505284382 # number of demand (read+write) MSHR miss cycles 2983system.l2c.demand_mshr_miss_latency::total 181913114058 # number of demand (read+write) MSHR miss cycles 2984system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 475745539 # number of overall MSHR miss cycles 2985system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 431144036 # number of overall MSHR miss cycles 2986system.l2c.overall_mshr_miss_latency::cpu0.inst 8990432141 # number of overall MSHR miss cycles 2987system.l2c.overall_mshr_miss_latency::cpu0.data 36127781624 # number of overall MSHR miss cycles 2988system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 45987586011 # number of overall MSHR miss cycles 2989system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 341894523 # number of overall MSHR miss cycles 2990system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 277514518 # number of overall MSHR miss cycles 2991system.l2c.overall_mshr_miss_latency::cpu1.inst 7629341915 # number of overall MSHR miss cycles 2992system.l2c.overall_mshr_miss_latency::cpu1.data 26146389369 # number of overall MSHR miss cycles 2993system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 55505284382 # number of overall MSHR miss cycles 2994system.l2c.overall_mshr_miss_latency::total 181913114058 # number of overall MSHR miss cycles 2995system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles 2996system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2247697035 # number of ReadReq MSHR uncacheable cycles 2997system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10383500 # number of ReadReq MSHR uncacheable cycles 2998system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3688367522 # number of ReadReq MSHR uncacheable cycles 2999system.l2c.ReadReq_mshr_uncacheable_latency::total 11844114057 # number of ReadReq MSHR uncacheable cycles 3000system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2355491526 # number of WriteReq MSHR uncacheable cycles 3001system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3627802114 # number of WriteReq MSHR uncacheable cycles 3002system.l2c.WriteReq_mshr_uncacheable_latency::total 5983293640 # number of WriteReq MSHR uncacheable cycles 3003system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles 3004system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4603188561 # number of overall MSHR uncacheable cycles 3005system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10383500 # number of overall MSHR uncacheable cycles 3006system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7316169636 # number of overall MSHR uncacheable cycles 3007system.l2c.overall_mshr_uncacheable_latency::total 17827407697 # number of overall MSHR uncacheable cycles 3008system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3009system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3010system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.260477 # mshr miss rate for UpgradeReq accesses 3011system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.292781 # mshr miss rate for UpgradeReq accesses 3012system.l2c.UpgradeReq_mshr_miss_rate::total 0.275100 # mshr miss rate for UpgradeReq accesses 3013system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.226122 # mshr miss rate for SCUpgradeReq accesses 3014system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.236223 # mshr miss rate for SCUpgradeReq accesses 3015system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230886 # mshr miss rate for SCUpgradeReq accesses 3016system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573251 # mshr miss rate for ReadExReq accesses 3017system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.549054 # mshr miss rate for ReadExReq accesses 3018system.l2c.ReadExReq_mshr_miss_rate::total 0.562606 # mshr miss rate for ReadExReq accesses 3019system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for ReadSharedReq accesses 3020system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for ReadSharedReq accesses 3021system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for ReadSharedReq accesses 3022system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.213527 # mshr miss rate for ReadSharedReq accesses 3023system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for ReadSharedReq accesses 3024system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for ReadSharedReq accesses 3025system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for ReadSharedReq accesses 3026system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for ReadSharedReq accesses 3027system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162635 # mshr miss rate for ReadSharedReq accesses 3028system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for ReadSharedReq accesses 3029system.l2c.ReadSharedReq_mshr_miss_rate::total 0.239318 # mshr miss rate for ReadSharedReq accesses 3030system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.745352 # mshr miss rate for InvalidateReq accesses 3031system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.563953 # mshr miss rate for InvalidateReq accesses 3032system.l2c.InvalidateReq_mshr_miss_rate::total 0.681658 # mshr miss rate for InvalidateReq accesses 3033system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for demand accesses 3034system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for demand accesses 3035system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for demand accesses 3036system.l2c.demand_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for demand accesses 3037system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for demand accesses 3038system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for demand accesses 3039system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for demand accesses 3040system.l2c.demand_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for demand accesses 3041system.l2c.demand_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for demand accesses 3042system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for demand accesses 3043system.l2c.demand_mshr_miss_rate::total 0.258011 # mshr miss rate for demand accesses 3044system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for overall accesses 3045system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for overall accesses 3046system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for overall accesses 3047system.l2c.overall_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for overall accesses 3048system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for overall accesses 3049system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for overall accesses 3050system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for overall accesses 3051system.l2c.overall_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for overall accesses 3052system.l2c.overall_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for overall accesses 3053system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for overall accesses 3054system.l2c.overall_mshr_miss_rate::total 0.258011 # mshr miss rate for overall accesses 3055system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.339917 # average UpgradeReq mshr miss latency 3056system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70359.930821 # average UpgradeReq mshr miss latency 3057system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70566.394621 # average UpgradeReq mshr miss latency 3058system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73641.009191 # average SCUpgradeReq mshr miss latency 3059system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73548.748351 # average SCUpgradeReq mshr miss latency 3060system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.483261 # average SCUpgradeReq mshr miss latency 3061system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127912.406083 # average ReadExReq mshr miss latency 3062system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128004.597362 # average ReadExReq mshr miss latency 3063system.l2c.ReadExReq_avg_mshr_miss_latency::total 127951.987161 # average ReadExReq mshr miss latency 3064system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average ReadSharedReq mshr miss latency 3065system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average ReadSharedReq mshr miss latency 3066system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average ReadSharedReq mshr miss latency 3067system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131423.037819 # average ReadSharedReq mshr miss latency 3068system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average ReadSharedReq mshr miss latency 3069system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average ReadSharedReq mshr miss latency 3070system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average ReadSharedReq mshr miss latency 3071system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average ReadSharedReq mshr miss latency 3072system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134145.307792 # average ReadSharedReq mshr miss latency 3073system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average ReadSharedReq mshr miss latency 3074system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 150265.373892 # average ReadSharedReq mshr miss latency 3075system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70087.808865 # average InvalidateReq mshr miss latency 3076system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69270.608839 # average InvalidateReq mshr miss latency 3077system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69850.417852 # average InvalidateReq mshr miss latency 3078system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency 3079system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency 3080system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency 3081system.l2c.demand_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency 3082system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency 3083system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency 3084system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency 3085system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency 3086system.l2c.demand_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency 3087system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency 3088system.l2c.demand_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency 3089system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency 3090system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency 3091system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency 3092system.l2c.overall_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency 3093system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency 3094system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency 3095system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency 3096system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency 3097system.l2c.overall_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency 3098system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency 3099system.l2c.overall_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency 3100system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 3101system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 148992.246785 # average ReadReq mshr uncacheable latency 3102system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency 3103system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158707.724699 # average ReadReq mshr uncacheable latency 3104system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130545.300866 # average ReadReq mshr uncacheable latency 3105system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147439.379444 # average WriteReq mshr uncacheable latency 3106system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163149.942166 # average WriteReq mshr uncacheable latency 3107system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156581.535643 # average WriteReq mshr uncacheable latency 3108system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 3109system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148193.566448 # average overall mshr uncacheable latency 3110system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency 3111system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160879.796728 # average overall mshr uncacheable latency 3112system.l2c.overall_avg_mshr_uncacheable_latency::total 138261.266457 # average overall mshr uncacheable latency 3113system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3114system.membus.trans_dist::ReadReq 90728 # Transaction distribution 3115system.membus.trans_dist::ReadResp 1177835 # Transaction distribution 3116system.membus.trans_dist::WriteReq 38212 # Transaction distribution 3117system.membus.trans_dist::WriteResp 38212 # Transaction distribution 3118system.membus.trans_dist::WritebackDirty 1451911 # Transaction distribution 3119system.membus.trans_dist::CleanEvict 312799 # Transaction distribution 3120system.membus.trans_dist::UpgradeReq 438732 # Transaction distribution 3121system.membus.trans_dist::SCUpgradeReq 328709 # Transaction distribution 3122system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3123system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 3124system.membus.trans_dist::ReadExReq 166722 # Transaction distribution 3125system.membus.trans_dist::ReadExResp 150087 # Transaction distribution 3126system.membus.trans_dist::ReadSharedReq 1087107 # Transaction distribution 3127system.membus.trans_dist::InvalidateReq 695373 # Transaction distribution 3128system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122964 # Packet count per connected master and slave (bytes) 3129system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3130system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24892 # Packet count per connected master and slave (bytes) 3131system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5587054 # Packet count per connected master and slave (bytes) 3132system.membus.pkt_count_system.l2c.mem_side::total 5734962 # Packet count per connected master and slave (bytes) 3133system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238554 # Packet count per connected master and slave (bytes) 3134system.membus.pkt_count_system.iocache.mem_side::total 238554 # Packet count per connected master and slave (bytes) 3135system.membus.pkt_count::total 5973516 # Packet count per connected master and slave (bytes) 3136system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156002 # Cumulative packet size per connected master and slave (bytes) 3137system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3138system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49784 # Cumulative packet size per connected master and slave (bytes) 3139system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168012608 # Cumulative packet size per connected master and slave (bytes) 3140system.membus.pkt_size_system.l2c.mem_side::total 168219718 # Cumulative packet size per connected master and slave (bytes) 3141system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276864 # Cumulative packet size per connected master and slave (bytes) 3142system.membus.pkt_size_system.iocache.mem_side::total 7276864 # Cumulative packet size per connected master and slave (bytes) 3143system.membus.pkt_size::total 175496582 # Cumulative packet size per connected master and slave (bytes) 3144system.membus.snoops 622390 # Total snoops (count) 3145system.membus.snoop_fanout::samples 4610336 # Request fanout histogram 3146system.membus.snoop_fanout::mean 1 # Request fanout histogram 3147system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3148system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3149system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3150system.membus.snoop_fanout::1 4610336 100.00% 100.00% # Request fanout histogram 3151system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3152system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3153system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3154system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3155system.membus.snoop_fanout::total 4610336 # Request fanout histogram 3156system.membus.reqLayer0.occupancy 110366494 # Layer occupancy (ticks) 3157system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3158system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3159system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3160system.membus.reqLayer2.occupancy 20951999 # Layer occupancy (ticks) 3161system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3162system.membus.reqLayer5.occupancy 10147074149 # Layer occupancy (ticks) 3163system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3164system.membus.respLayer2.occupancy 6858565377 # Layer occupancy (ticks) 3165system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3166system.membus.respLayer3.occupancy 45617493 # Layer occupancy (ticks) 3167system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3168system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3169system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3170system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3171system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3172system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3173system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3174system.realview.ethernet.txBytes 966 # Bytes Transmitted 3175system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3176system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3177system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3178system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3179system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3180system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3181system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3182system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3183system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3184system.realview.ethernet.totPackets 3 # Total Packets 3185system.realview.ethernet.totBytes 966 # Total Bytes 3186system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3187system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3188system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3189system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3190system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3191system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3192system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3193system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3194system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3195system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3196system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3197system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3198system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3199system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3200system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3201system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3202system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3203system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3204system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3205system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3206system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3207system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3208system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3209system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3210system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3211system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3212system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3213system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3214system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3215system.realview.ethernet.droppedPackets 0 # number of packets dropped 3216system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3217system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3218system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3219system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3220system.toL2Bus.snoop_filter.tot_requests 13817515 # Total number of requests made to the snoop filter. 3221system.toL2Bus.snoop_filter.hit_single_requests 7477037 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3222system.toL2Bus.snoop_filter.hit_multi_requests 2215935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3223system.toL2Bus.snoop_filter.tot_snoops 187202 # Total number of snoops made to the snoop filter. 3224system.toL2Bus.snoop_filter.hit_single_snoops 169247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3225system.toL2Bus.snoop_filter.hit_multi_snoops 17955 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3226system.toL2Bus.trans_dist::ReadReq 90730 # Transaction distribution 3227system.toL2Bus.trans_dist::ReadResp 5393978 # Transaction distribution 3228system.toL2Bus.trans_dist::WriteReq 38212 # Transaction distribution 3229system.toL2Bus.trans_dist::WriteResp 38212 # Transaction distribution 3230system.toL2Bus.trans_dist::WritebackDirty 4613586 # Transaction distribution 3231system.toL2Bus.trans_dist::CleanEvict 3368394 # Transaction distribution 3232system.toL2Bus.trans_dist::UpgradeReq 769711 # Transaction distribution 3233system.toL2Bus.trans_dist::SCUpgradeReq 415575 # Transaction distribution 3234system.toL2Bus.trans_dist::UpgradeResp 1185286 # Transaction distribution 3235system.toL2Bus.trans_dist::SCUpgradeFailReq 166 # Transaction distribution 3236system.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution 3237system.toL2Bus.trans_dist::ReadExReq 331620 # Transaction distribution 3238system.toL2Bus.trans_dist::ReadExResp 331620 # Transaction distribution 3239system.toL2Bus.trans_dist::ReadSharedReq 5310492 # Transaction distribution 3240system.toL2Bus.trans_dist::InvalidateReq 975909 # Transaction distribution 3241system.toL2Bus.trans_dist::InvalidateResp 868925 # Transaction distribution 3242system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10817825 # Packet count per connected master and slave (bytes) 3243system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9492092 # Packet count per connected master and slave (bytes) 3244system.toL2Bus.pkt_count::total 20309917 # Packet count per connected master and slave (bytes) 3245system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 274107435 # Cumulative packet size per connected master and slave (bytes) 3246system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 237950875 # Cumulative packet size per connected master and slave (bytes) 3247system.toL2Bus.pkt_size::total 512058310 # Cumulative packet size per connected master and slave (bytes) 3248system.toL2Bus.snoops 3424368 # Total snoops (count) 3249system.toL2Bus.snoop_fanout::samples 9784683 # Request fanout histogram 3250system.toL2Bus.snoop_fanout::mean 0.340448 # Request fanout histogram 3251system.toL2Bus.snoop_fanout::stdev 0.477717 # Request fanout histogram 3252system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3253system.toL2Bus.snoop_fanout::0 6471464 66.14% 66.14% # Request fanout histogram 3254system.toL2Bus.snoop_fanout::1 3295264 33.68% 99.82% # Request fanout histogram 3255system.toL2Bus.snoop_fanout::2 17955 0.18% 100.00% # Request fanout histogram 3256system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3257system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3258system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3259system.toL2Bus.snoop_fanout::total 9784683 # Request fanout histogram 3260system.toL2Bus.reqLayer0.occupancy 10614903907 # Layer occupancy (ticks) 3261system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3262system.toL2Bus.snoopLayer0.occupancy 2624417 # Layer occupancy (ticks) 3263system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3264system.toL2Bus.respLayer0.occupancy 5004390482 # Layer occupancy (ticks) 3265system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3266system.toL2Bus.respLayer1.occupancy 4630478453 # Layer occupancy (ticks) 3267system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3268 3269---------- End Simulation Statistics ---------- 3270