stats.txt revision 11239:3be64e1f80ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.381663 # Number of seconds simulated 4sim_ticks 47381662864000 # Number of ticks simulated 5final_tick 47381662864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 132815 # Simulator instruction rate (inst/s) 8host_op_rate 156205 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7502885455 # Simulator tick rate (ticks/s) 10host_mem_usage 760860 # Number of bytes of host memory used 11host_seconds 6315.13 # Real time elapsed on the host 12sim_insts 838745469 # Number of instructions simulated 13sim_ops 986455629 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 42368 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 41792 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 6976384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 35367624 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 9096640 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 59520 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 61888 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3056960 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 12429456 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 7583744 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 432640 # Number of bytes read from this memory 27system.physmem.bytes_read::total 75149016 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 6976384 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3056960 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 10033344 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 59523200 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 59543784 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 662 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 653 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 109006 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 552632 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 142135 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 930 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 967 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 47765 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 194223 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 118496 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6760 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1174229 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 930050 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 932624 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 894 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 882 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 147238 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 746441 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 191987 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1256 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1306 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 64518 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 262326 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 160057 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9131 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1586036 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 147238 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 64518 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 211756 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1256250 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1256684 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1256250 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 894 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 882 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 147238 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 746876 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 191987 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1256 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1306 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 64518 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 262326 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 160057 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9131 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2842720 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1174229 # Number of read requests accepted 84system.physmem.writeReqs 932624 # Number of write requests accepted 85system.physmem.readBursts 1174229 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 932624 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 75113152 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 37504 # Total number of bytes read from write queue 89system.physmem.bytesWritten 59543040 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 75149016 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 59543784 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 586 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 448232 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 71067 # Per bank write bursts 96system.physmem.perBankRdBursts::1 73380 # Per bank write bursts 97system.physmem.perBankRdBursts::2 69314 # Per bank write bursts 98system.physmem.perBankRdBursts::3 74537 # Per bank write bursts 99system.physmem.perBankRdBursts::4 66547 # Per bank write bursts 100system.physmem.perBankRdBursts::5 79030 # Per bank write bursts 101system.physmem.perBankRdBursts::6 66275 # Per bank write bursts 102system.physmem.perBankRdBursts::7 68082 # Per bank write bursts 103system.physmem.perBankRdBursts::8 68948 # Per bank write bursts 104system.physmem.perBankRdBursts::9 127738 # Per bank write bursts 105system.physmem.perBankRdBursts::10 63222 # Per bank write bursts 106system.physmem.perBankRdBursts::11 73993 # Per bank write bursts 107system.physmem.perBankRdBursts::12 67075 # Per bank write bursts 108system.physmem.perBankRdBursts::13 69321 # Per bank write bursts 109system.physmem.perBankRdBursts::14 63089 # Per bank write bursts 110system.physmem.perBankRdBursts::15 72025 # Per bank write bursts 111system.physmem.perBankWrBursts::0 57427 # Per bank write bursts 112system.physmem.perBankWrBursts::1 61393 # Per bank write bursts 113system.physmem.perBankWrBursts::2 59144 # Per bank write bursts 114system.physmem.perBankWrBursts::3 61303 # Per bank write bursts 115system.physmem.perBankWrBursts::4 56823 # Per bank write bursts 116system.physmem.perBankWrBursts::5 63517 # Per bank write bursts 117system.physmem.perBankWrBursts::6 54876 # Per bank write bursts 118system.physmem.perBankWrBursts::7 56576 # Per bank write bursts 119system.physmem.perBankWrBursts::8 56101 # Per bank write bursts 120system.physmem.perBankWrBursts::9 62480 # Per bank write bursts 121system.physmem.perBankWrBursts::10 54750 # Per bank write bursts 122system.physmem.perBankWrBursts::11 61148 # Per bank write bursts 123system.physmem.perBankWrBursts::12 54574 # Per bank write bursts 124system.physmem.perBankWrBursts::13 57375 # Per bank write bursts 125system.physmem.perBankWrBursts::14 53605 # Per bank write bursts 126system.physmem.perBankWrBursts::15 59268 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 30 # Number of times write queue was full causing retry 129system.physmem.totGap 47381660751500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1174199 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 930050 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 756841 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 295232 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 26539 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 19834 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 17154 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 15837 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 14079 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 12670 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 10425 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1820 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 647 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 492 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 324 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 175 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 157 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 142 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 119 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 16213 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 18671 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 35561 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 45390 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 50223 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 52287 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 55018 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 55938 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 58169 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 58483 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 59754 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 64501 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 60072 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 59690 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 64110 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 58190 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 54561 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 52990 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1468 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 888 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 738 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 611 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 522 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 526 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 421 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 349 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 397 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 295 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 327 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 308 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 322 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 256 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 224 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 174 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 120 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 43 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 709891 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 189.684557 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 114.673344 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 252.164844 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 431942 60.85% 60.85% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 132623 18.68% 79.53% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 44376 6.25% 85.78% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 24102 3.40% 89.17% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 15088 2.13% 91.30% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 9957 1.40% 92.70% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 7669 1.08% 93.78% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 7642 1.08% 94.86% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 36492 5.14% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 709891 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 51534 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 22.773974 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 380.344580 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 51531 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 51534 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 51534 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 18.053324 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.386136 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.764507 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 48029 93.20% 93.20% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 1359 2.64% 95.84% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 210 0.41% 96.24% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 316 0.61% 96.86% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 77 0.15% 97.01% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 304 0.59% 97.60% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 196 0.38% 97.98% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 89 0.17% 98.15% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 103 0.20% 98.35% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 90 0.17% 98.52% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 42 0.08% 98.60% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 57 0.11% 98.72% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 406 0.79% 99.50% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 44 0.09% 99.59% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 34 0.07% 99.65% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 103 0.20% 99.85% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 21 0.04% 99.90% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 3 0.01% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 3 0.01% 99.91% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::120-123 3 0.01% 99.93% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 20 0.04% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 51534 # Writes before turning the bus around for reads 300system.physmem.totQLat 26583019130 # Total ticks spent queuing 301system.physmem.totMemAccLat 48588825380 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 5868215000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 22650.00 # Average queueing delay per DRAM burst 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 305system.physmem.avgMemAccLat 41400.00 # Average memory access latency per DRAM burst 306system.physmem.avgRdBW 1.59 # Average DRAM read bandwidth in MiByte/s 307system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s 308system.physmem.avgRdBWSys 1.59 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 1.26 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.02 # Data bus utilization in percentage 312system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 313system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 314system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 21.83 # Average write queue length when enqueuing 316system.physmem.readRowHits 952385 # Number of row buffer hits during reads 317system.physmem.writeRowHits 441721 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 81.15 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 47.48 # Row buffer hit rate for writes 320system.physmem.avgGap 22489305.50 # Average gap between requests 321system.physmem.pageHitRate 66.26 # Row buffer hit rate, read and write combined 322system.physmem_0.actEnergy 2710380960 # Energy for activate commands per rank (pJ) 323system.physmem_0.preEnergy 1478878500 # Energy for precharge commands per rank (pJ) 324system.physmem_0.readEnergy 4432209600 # Energy for read commands per rank (pJ) 325system.physmem_0.writeEnergy 3052442880 # Energy for write commands per rank (pJ) 326system.physmem_0.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) 327system.physmem_0.actBackEnergy 1177500235590 # Energy for active background per rank (pJ) 328system.physmem_0.preBackEnergy 27396100823250 # Energy for precharge background per rank (pJ) 329system.physmem_0.totalEnergy 31680014630220 # Total energy per rank (pJ) 330system.physmem_0.averagePower 668.613444 # Core power per rank (mW) 331system.physmem_0.memoryStateTime::IDLE 45575607610794 # Time in different power states 332system.physmem_0.memoryStateTime::REF 1582177740000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 223874273456 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.physmem_1.actEnergy 2656364760 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 1449405375 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 4722003000 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 2976166800 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 1182079758375 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 27392083725750 # Energy for precharge background per rank (pJ) 343system.physmem_1.totalEnergy 31680707083500 # Total energy per rank (pJ) 344system.physmem_1.averagePower 668.628058 # Core power per rank (mW) 345system.physmem_1.memoryStateTime::IDLE 45568857815114 # Time in different power states 346system.physmem_1.memoryStateTime::REF 1582177740000 # Time in different power states 347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 348system.physmem_1.memoryStateTime::ACT 230624127636 # Time in different power states 349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 350system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 357system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 358system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 363system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 376system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 377system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 378system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 379system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 380system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 381system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 382system.cpu0.branchPred.lookups 125258409 # Number of BP lookups 383system.cpu0.branchPred.condPredicted 88001025 # Number of conditional branches predicted 384system.cpu0.branchPred.condIncorrect 5802079 # Number of conditional branches incorrect 385system.cpu0.branchPred.BTBLookups 93100413 # Number of BTB lookups 386system.cpu0.branchPred.BTBHits 67841086 # Number of BTB hits 387system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 388system.cpu0.branchPred.BTBHitPct 72.868727 # BTB Hit Percentage 389system.cpu0.branchPred.usedRAS 15085862 # Number of times the RAS was used to get a target. 390system.cpu0.branchPred.RASInCorrect 1028654 # Number of incorrect RAS predictions. 391system.cpu_clk_domain.clock 500 # Clock period in ticks 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 401system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 402system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 403system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 404system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 405system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 410system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 411system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 412system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 413system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 416system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 417system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 418system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 419system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 420system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 421system.cpu0.dtb.walker.walks 252652 # Table walker walks requested 422system.cpu0.dtb.walker.walksLong 252652 # Table walker walks initiated with long descriptors 423system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7537 # Level at which table walker walks with long descriptors terminate 424system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 66702 # Level at which table walker walks with long descriptors terminate 425system.cpu0.dtb.walker.walkWaitTime::samples 252652 # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::0 252652 100.00% 100.00% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::total 252652 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkCompletionTime::samples 74239 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::mean 22181.016716 # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::gmean 20809.120487 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::stdev 13879.929548 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::0-65535 73678 99.24% 99.24% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::65536-131071 179 0.24% 99.49% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::131072-196607 332 0.45% 99.93% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.95% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::total 74239 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 445system.cpu0.dtb.walker.walkPageSizes::4K 66702 89.85% 89.85% # Table walker page sizes translated 446system.cpu0.dtb.walker.walkPageSizes::2M 7537 10.15% 100.00% # Table walker page sizes translated 447system.cpu0.dtb.walker.walkPageSizes::total 74239 # Table walker page sizes translated 448system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 252652 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 252652 # Table walker requests started/completed, data/inst 451system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 74239 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 74239 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin::total 326891 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.inst_hits 0 # ITB inst hits 456system.cpu0.dtb.inst_misses 0 # ITB inst misses 457system.cpu0.dtb.read_hits 81678885 # DTB read hits 458system.cpu0.dtb.read_misses 209727 # DTB read misses 459system.cpu0.dtb.write_hits 70936828 # DTB write hits 460system.cpu0.dtb.write_misses 42925 # DTB write misses 461system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 462system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 463system.cpu0.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 464system.cpu0.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 465system.cpu0.dtb.flush_entries 33720 # Number of entries that have been flushed from TLB 466system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions 467system.cpu0.dtb.prefetch_faults 8048 # Number of TLB faults due to prefetch 468system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu0.dtb.perms_faults 9709 # Number of TLB faults due to permissions restrictions 470system.cpu0.dtb.read_accesses 81888612 # DTB read accesses 471system.cpu0.dtb.write_accesses 70979753 # DTB write accesses 472system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 473system.cpu0.dtb.hits 152615713 # DTB hits 474system.cpu0.dtb.misses 252652 # DTB misses 475system.cpu0.dtb.accesses 152868365 # DTB accesses 476system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 485system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 486system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 487system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 488system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 489system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 491system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 492system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 493system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 494system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 495system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 496system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 497system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 498system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 499system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 500system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 501system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 502system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 503system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 504system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 505system.cpu0.itb.walker.walks 57977 # Table walker walks requested 506system.cpu0.itb.walker.walksLong 57977 # Table walker walks initiated with long descriptors 507system.cpu0.itb.walker.walksLongTerminationLevel::Level2 503 # Level at which table walker walks with long descriptors terminate 508system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46742 # Level at which table walker walks with long descriptors terminate 509system.cpu0.itb.walker.walkWaitTime::samples 57977 # Table walker wait (enqueue to first request) latency 510system.cpu0.itb.walker.walkWaitTime::0 57977 100.00% 100.00% # Table walker wait (enqueue to first request) latency 511system.cpu0.itb.walker.walkWaitTime::total 57977 # Table walker wait (enqueue to first request) latency 512system.cpu0.itb.walker.walkCompletionTime::samples 47245 # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::mean 24873.087099 # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::gmean 23068.832563 # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::stdev 17067.215870 # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::0-32767 43882 92.88% 92.88% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::32768-65535 2853 6.04% 98.92% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::65536-98303 11 0.02% 98.94% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::131072-163839 288 0.61% 99.55% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::163840-196607 169 0.36% 99.91% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::196608-229375 7 0.01% 99.93% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.95% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.03% 99.97% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::total 47245 # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 531system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 532system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 533system.cpu0.itb.walker.walkPageSizes::4K 46742 98.94% 98.94% # Table walker page sizes translated 534system.cpu0.itb.walker.walkPageSizes::2M 503 1.06% 100.00% # Table walker page sizes translated 535system.cpu0.itb.walker.walkPageSizes::total 47245 # Table walker page sizes translated 536system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 537system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57977 # Table walker requests started/completed, data/inst 538system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57977 # Table walker requests started/completed, data/inst 539system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 540system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47245 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47245 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin::total 105222 # Table walker requests started/completed, data/inst 543system.cpu0.itb.inst_hits 224840362 # ITB inst hits 544system.cpu0.itb.inst_misses 57977 # ITB inst misses 545system.cpu0.itb.read_hits 0 # DTB read hits 546system.cpu0.itb.read_misses 0 # DTB read misses 547system.cpu0.itb.write_hits 0 # DTB write hits 548system.cpu0.itb.write_misses 0 # DTB write misses 549system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 550system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 551system.cpu0.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 552system.cpu0.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 553system.cpu0.itb.flush_entries 24328 # Number of entries that have been flushed from TLB 554system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 555system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 556system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 557system.cpu0.itb.perms_faults 193753 # Number of TLB faults due to permissions restrictions 558system.cpu0.itb.read_accesses 0 # DTB read accesses 559system.cpu0.itb.write_accesses 0 # DTB write accesses 560system.cpu0.itb.inst_accesses 224898339 # ITB inst accesses 561system.cpu0.itb.hits 224840362 # DTB hits 562system.cpu0.itb.misses 57977 # DTB misses 563system.cpu0.itb.accesses 224898339 # DTB accesses 564system.cpu0.numCycles 954325944 # number of cpu cycles simulated 565system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 566system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 567system.cpu0.committedInsts 417810947 # Number of instructions committed 568system.cpu0.committedOps 490605107 # Number of ops (including micro ops) committed 569system.cpu0.discardedOps 41344261 # Number of ops (including micro ops) which were discarded before commit 570system.cpu0.numFetchSuspends 4694 # Number of times Execute suspended instruction fetching 571system.cpu0.quiesceCycles 93809718025 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 572system.cpu0.cpi 2.284109 # CPI: cycles per instruction 573system.cpu0.ipc 0.437807 # IPC: instructions per cycle 574system.cpu0.kern.inst.arm 0 # number of arm instructions executed 575system.cpu0.kern.inst.quiesce 4756 # number of quiesce instructions executed 576system.cpu0.tickCycles 674001287 # Number of cycles that the object actually ticked 577system.cpu0.idleCycles 280324657 # Total number of cycles that the object has spent stopped 578system.cpu0.dcache.tags.replacements 5190067 # number of replacements 579system.cpu0.dcache.tags.tagsinuse 482.757722 # Cycle average of tags in use 580system.cpu0.dcache.tags.total_refs 144829115 # Total number of references to valid blocks. 581system.cpu0.dcache.tags.sampled_refs 5190578 # Sample count of references to valid blocks. 582system.cpu0.dcache.tags.avg_refs 27.902310 # Average number of references to valid blocks. 583system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 584system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.757722 # Average occupied blocks per requestor 585system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942886 # Average percentage of cache occupancy 586system.cpu0.dcache.tags.occ_percent::total 0.942886 # Average percentage of cache occupancy 587system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 588system.cpu0.dcache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 589system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 590system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 591system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 592system.cpu0.dcache.tags.tag_accesses 307937411 # Number of tag accesses 593system.cpu0.dcache.tags.data_accesses 307937411 # Number of data accesses 594system.cpu0.dcache.ReadReq_hits::cpu0.data 74836049 # number of ReadReq hits 595system.cpu0.dcache.ReadReq_hits::total 74836049 # number of ReadReq hits 596system.cpu0.dcache.WriteReq_hits::cpu0.data 65744025 # number of WriteReq hits 597system.cpu0.dcache.WriteReq_hits::total 65744025 # number of WriteReq hits 598system.cpu0.dcache.SoftPFReq_hits::cpu0.data 248898 # number of SoftPFReq hits 599system.cpu0.dcache.SoftPFReq_hits::total 248898 # number of SoftPFReq hits 600system.cpu0.dcache.WriteLineReq_hits::cpu0.data 135683 # number of WriteLineReq hits 601system.cpu0.dcache.WriteLineReq_hits::total 135683 # number of WriteLineReq hits 602system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1688860 # number of LoadLockedReq hits 603system.cpu0.dcache.LoadLockedReq_hits::total 1688860 # number of LoadLockedReq hits 604system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1659238 # number of StoreCondReq hits 605system.cpu0.dcache.StoreCondReq_hits::total 1659238 # number of StoreCondReq hits 606system.cpu0.dcache.demand_hits::cpu0.data 140580074 # number of demand (read+write) hits 607system.cpu0.dcache.demand_hits::total 140580074 # number of demand (read+write) hits 608system.cpu0.dcache.overall_hits::cpu0.data 140828972 # number of overall hits 609system.cpu0.dcache.overall_hits::total 140828972 # number of overall hits 610system.cpu0.dcache.ReadReq_misses::cpu0.data 3204136 # number of ReadReq misses 611system.cpu0.dcache.ReadReq_misses::total 3204136 # number of ReadReq misses 612system.cpu0.dcache.WriteReq_misses::cpu0.data 2171939 # number of WriteReq misses 613system.cpu0.dcache.WriteReq_misses::total 2171939 # number of WriteReq misses 614system.cpu0.dcache.SoftPFReq_misses::cpu0.data 583430 # number of SoftPFReq misses 615system.cpu0.dcache.SoftPFReq_misses::total 583430 # number of SoftPFReq misses 616system.cpu0.dcache.WriteLineReq_misses::cpu0.data 728874 # number of WriteLineReq misses 617system.cpu0.dcache.WriteLineReq_misses::total 728874 # number of WriteLineReq misses 618system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 150550 # number of LoadLockedReq misses 619system.cpu0.dcache.LoadLockedReq_misses::total 150550 # number of LoadLockedReq misses 620system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178568 # number of StoreCondReq misses 621system.cpu0.dcache.StoreCondReq_misses::total 178568 # number of StoreCondReq misses 622system.cpu0.dcache.demand_misses::cpu0.data 5376075 # number of demand (read+write) misses 623system.cpu0.dcache.demand_misses::total 5376075 # number of demand (read+write) misses 624system.cpu0.dcache.overall_misses::cpu0.data 5959505 # number of overall misses 625system.cpu0.dcache.overall_misses::total 5959505 # number of overall misses 626system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51043675000 # number of ReadReq miss cycles 627system.cpu0.dcache.ReadReq_miss_latency::total 51043675000 # number of ReadReq miss cycles 628system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55065851500 # number of WriteReq miss cycles 629system.cpu0.dcache.WriteReq_miss_latency::total 55065851500 # number of WriteReq miss cycles 630system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 67163849000 # number of WriteLineReq miss cycles 631system.cpu0.dcache.WriteLineReq_miss_latency::total 67163849000 # number of WriteLineReq miss cycles 632system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2254990500 # number of LoadLockedReq miss cycles 633system.cpu0.dcache.LoadLockedReq_miss_latency::total 2254990500 # number of LoadLockedReq miss cycles 634system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5008928500 # number of StoreCondReq miss cycles 635system.cpu0.dcache.StoreCondReq_miss_latency::total 5008928500 # number of StoreCondReq miss cycles 636system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5076500 # number of StoreCondFailReq miss cycles 637system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5076500 # number of StoreCondFailReq miss cycles 638system.cpu0.dcache.demand_miss_latency::cpu0.data 106109526500 # number of demand (read+write) miss cycles 639system.cpu0.dcache.demand_miss_latency::total 106109526500 # number of demand (read+write) miss cycles 640system.cpu0.dcache.overall_miss_latency::cpu0.data 106109526500 # number of overall miss cycles 641system.cpu0.dcache.overall_miss_latency::total 106109526500 # number of overall miss cycles 642system.cpu0.dcache.ReadReq_accesses::cpu0.data 78040185 # number of ReadReq accesses(hits+misses) 643system.cpu0.dcache.ReadReq_accesses::total 78040185 # number of ReadReq accesses(hits+misses) 644system.cpu0.dcache.WriteReq_accesses::cpu0.data 67915964 # number of WriteReq accesses(hits+misses) 645system.cpu0.dcache.WriteReq_accesses::total 67915964 # number of WriteReq accesses(hits+misses) 646system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 832328 # number of SoftPFReq accesses(hits+misses) 647system.cpu0.dcache.SoftPFReq_accesses::total 832328 # number of SoftPFReq accesses(hits+misses) 648system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 864557 # number of WriteLineReq accesses(hits+misses) 649system.cpu0.dcache.WriteLineReq_accesses::total 864557 # number of WriteLineReq accesses(hits+misses) 650system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1839410 # number of LoadLockedReq accesses(hits+misses) 651system.cpu0.dcache.LoadLockedReq_accesses::total 1839410 # number of LoadLockedReq accesses(hits+misses) 652system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1837806 # number of StoreCondReq accesses(hits+misses) 653system.cpu0.dcache.StoreCondReq_accesses::total 1837806 # number of StoreCondReq accesses(hits+misses) 654system.cpu0.dcache.demand_accesses::cpu0.data 145956149 # number of demand (read+write) accesses 655system.cpu0.dcache.demand_accesses::total 145956149 # number of demand (read+write) accesses 656system.cpu0.dcache.overall_accesses::cpu0.data 146788477 # number of overall (read+write) accesses 657system.cpu0.dcache.overall_accesses::total 146788477 # number of overall (read+write) accesses 658system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041058 # miss rate for ReadReq accesses 659system.cpu0.dcache.ReadReq_miss_rate::total 0.041058 # miss rate for ReadReq accesses 660system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031980 # miss rate for WriteReq accesses 661system.cpu0.dcache.WriteReq_miss_rate::total 0.031980 # miss rate for WriteReq accesses 662system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.700962 # miss rate for SoftPFReq accesses 663system.cpu0.dcache.SoftPFReq_miss_rate::total 0.700962 # miss rate for SoftPFReq accesses 664system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843061 # miss rate for WriteLineReq accesses 665system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843061 # miss rate for WriteLineReq accesses 666system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081847 # miss rate for LoadLockedReq accesses 667system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081847 # miss rate for LoadLockedReq accesses 668system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097164 # miss rate for StoreCondReq accesses 669system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097164 # miss rate for StoreCondReq accesses 670system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036833 # miss rate for demand accesses 671system.cpu0.dcache.demand_miss_rate::total 0.036833 # miss rate for demand accesses 672system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040599 # miss rate for overall accesses 673system.cpu0.dcache.overall_miss_rate::total 0.040599 # miss rate for overall accesses 674system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15930.558191 # average ReadReq miss latency 675system.cpu0.dcache.ReadReq_avg_miss_latency::total 15930.558191 # average ReadReq miss latency 676system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25353.314020 # average WriteReq miss latency 677system.cpu0.dcache.WriteReq_avg_miss_latency::total 25353.314020 # average WriteReq miss latency 678system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92147.406822 # average WriteLineReq miss latency 679system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92147.406822 # average WriteLineReq miss latency 680system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14978.349386 # average LoadLockedReq miss latency 681system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14978.349386 # average LoadLockedReq miss latency 682system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28050.538170 # average StoreCondReq miss latency 683system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28050.538170 # average StoreCondReq miss latency 684system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 685system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 686system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19737.359784 # average overall miss latency 687system.cpu0.dcache.demand_avg_miss_latency::total 19737.359784 # average overall miss latency 688system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17805.090607 # average overall miss latency 689system.cpu0.dcache.overall_avg_miss_latency::total 17805.090607 # average overall miss latency 690system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 691system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 693system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 695system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu0.dcache.fast_writes 0 # number of fast writes performed 697system.cpu0.dcache.cache_copies 0 # number of cache copies performed 698system.cpu0.dcache.writebacks::writebacks 5190079 # number of writebacks 699system.cpu0.dcache.writebacks::total 5190079 # number of writebacks 700system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 389569 # number of ReadReq MSHR hits 701system.cpu0.dcache.ReadReq_mshr_hits::total 389569 # number of ReadReq MSHR hits 702system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 893829 # number of WriteReq MSHR hits 703system.cpu0.dcache.WriteReq_mshr_hits::total 893829 # number of WriteReq MSHR hits 704system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 64 # number of WriteLineReq MSHR hits 705system.cpu0.dcache.WriteLineReq_mshr_hits::total 64 # number of WriteLineReq MSHR hits 706system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40085 # number of LoadLockedReq MSHR hits 707system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40085 # number of LoadLockedReq MSHR hits 708system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 63 # number of StoreCondReq MSHR hits 709system.cpu0.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits 710system.cpu0.dcache.demand_mshr_hits::cpu0.data 1283398 # number of demand (read+write) MSHR hits 711system.cpu0.dcache.demand_mshr_hits::total 1283398 # number of demand (read+write) MSHR hits 712system.cpu0.dcache.overall_mshr_hits::cpu0.data 1283398 # number of overall MSHR hits 713system.cpu0.dcache.overall_mshr_hits::total 1283398 # number of overall MSHR hits 714system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2814567 # number of ReadReq MSHR misses 715system.cpu0.dcache.ReadReq_mshr_misses::total 2814567 # number of ReadReq MSHR misses 716system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1278110 # number of WriteReq MSHR misses 717system.cpu0.dcache.WriteReq_mshr_misses::total 1278110 # number of WriteReq MSHR misses 718system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 581694 # number of SoftPFReq MSHR misses 719system.cpu0.dcache.SoftPFReq_mshr_misses::total 581694 # number of SoftPFReq MSHR misses 720system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 728810 # number of WriteLineReq MSHR misses 721system.cpu0.dcache.WriteLineReq_mshr_misses::total 728810 # number of WriteLineReq MSHR misses 722system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110465 # number of LoadLockedReq MSHR misses 723system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110465 # number of LoadLockedReq MSHR misses 724system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178505 # number of StoreCondReq MSHR misses 725system.cpu0.dcache.StoreCondReq_mshr_misses::total 178505 # number of StoreCondReq MSHR misses 726system.cpu0.dcache.demand_mshr_misses::cpu0.data 4092677 # number of demand (read+write) MSHR misses 727system.cpu0.dcache.demand_mshr_misses::total 4092677 # number of demand (read+write) MSHR misses 728system.cpu0.dcache.overall_mshr_misses::cpu0.data 4674371 # number of overall MSHR misses 729system.cpu0.dcache.overall_mshr_misses::total 4674371 # number of overall MSHR misses 730system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable 731system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16748 # number of ReadReq MSHR uncacheable 732system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable 733system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18251 # number of WriteReq MSHR uncacheable 734system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses 735system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34999 # number of overall MSHR uncacheable misses 736system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40095557000 # number of ReadReq MSHR miss cycles 737system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40095557000 # number of ReadReq MSHR miss cycles 738system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32063318500 # number of WriteReq MSHR miss cycles 739system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32063318500 # number of WriteReq MSHR miss cycles 740system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14032843000 # number of SoftPFReq MSHR miss cycles 741system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14032843000 # number of SoftPFReq MSHR miss cycles 742system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 66427837000 # number of WriteLineReq MSHR miss cycles 743system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 66427837000 # number of WriteLineReq MSHR miss cycles 744system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1488538500 # number of LoadLockedReq MSHR miss cycles 745system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1488538500 # number of LoadLockedReq MSHR miss cycles 746system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4826102000 # number of StoreCondReq MSHR miss cycles 747system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4826102000 # number of StoreCondReq MSHR miss cycles 748system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4518500 # number of StoreCondFailReq MSHR miss cycles 749system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4518500 # number of StoreCondFailReq MSHR miss cycles 750system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 72158875500 # number of demand (read+write) MSHR miss cycles 751system.cpu0.dcache.demand_mshr_miss_latency::total 72158875500 # number of demand (read+write) MSHR miss cycles 752system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 86191718500 # number of overall MSHR miss cycles 753system.cpu0.dcache.overall_mshr_miss_latency::total 86191718500 # number of overall MSHR miss cycles 754system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3021431000 # number of ReadReq MSHR uncacheable cycles 755system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3021431000 # number of ReadReq MSHR uncacheable cycles 756system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3257996500 # number of WriteReq MSHR uncacheable cycles 757system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3257996500 # number of WriteReq MSHR uncacheable cycles 758system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6279427500 # number of overall MSHR uncacheable cycles 759system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6279427500 # number of overall MSHR uncacheable cycles 760system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036066 # mshr miss rate for ReadReq accesses 761system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036066 # mshr miss rate for ReadReq accesses 762system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018819 # mshr miss rate for WriteReq accesses 763system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018819 # mshr miss rate for WriteReq accesses 764system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.698876 # mshr miss rate for SoftPFReq accesses 765system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.698876 # mshr miss rate for SoftPFReq accesses 766system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842987 # mshr miss rate for WriteLineReq accesses 767system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842987 # mshr miss rate for WriteLineReq accesses 768system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060055 # mshr miss rate for LoadLockedReq accesses 769system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060055 # mshr miss rate for LoadLockedReq accesses 770system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097129 # mshr miss rate for StoreCondReq accesses 771system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097129 # mshr miss rate for StoreCondReq accesses 772system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028040 # mshr miss rate for demand accesses 773system.cpu0.dcache.demand_mshr_miss_rate::total 0.028040 # mshr miss rate for demand accesses 774system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031844 # mshr miss rate for overall accesses 775system.cpu0.dcache.overall_mshr_miss_rate::total 0.031844 # mshr miss rate for overall accesses 776system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.728384 # average ReadReq mshr miss latency 777system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14245.728384 # average ReadReq mshr miss latency 778system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25086.509377 # average WriteReq mshr miss latency 779system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25086.509377 # average WriteReq mshr miss latency 780system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24124.097893 # average SoftPFReq mshr miss latency 781system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.097893 # average SoftPFReq mshr miss latency 782system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91145.616827 # average WriteLineReq mshr miss latency 783system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91145.616827 # average WriteLineReq mshr miss latency 784system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13475.204816 # average LoadLockedReq mshr miss latency 785system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13475.204816 # average LoadLockedReq mshr miss latency 786system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27036.228677 # average StoreCondReq mshr miss latency 787system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27036.228677 # average StoreCondReq mshr miss latency 788system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 789system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 790system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17631.216805 # average overall mshr miss latency 791system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17631.216805 # average overall mshr miss latency 792system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18439.212142 # average overall mshr miss latency 793system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18439.212142 # average overall mshr miss latency 794system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180405.481251 # average ReadReq mshr uncacheable latency 795system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180405.481251 # average ReadReq mshr uncacheable latency 796system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178510.574763 # average WriteReq mshr uncacheable latency 797system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 178510.574763 # average WriteReq mshr uncacheable latency 798system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179417.340495 # average overall mshr uncacheable latency 799system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179417.340495 # average overall mshr uncacheable latency 800system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 801system.cpu0.icache.tags.replacements 8911456 # number of replacements 802system.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use 803system.cpu0.icache.tags.total_refs 215729294 # Total number of references to valid blocks. 804system.cpu0.icache.tags.sampled_refs 8911968 # Sample count of references to valid blocks. 805system.cpu0.icache.tags.avg_refs 24.206695 # Average number of references to valid blocks. 806system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. 807system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor 808system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy 809system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy 810system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 811system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 812system.cpu0.icache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id 813system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 814system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 815system.cpu0.icache.tags.tag_accesses 458194521 # Number of tag accesses 816system.cpu0.icache.tags.data_accesses 458194521 # Number of data accesses 817system.cpu0.icache.ReadReq_hits::cpu0.inst 215729294 # number of ReadReq hits 818system.cpu0.icache.ReadReq_hits::total 215729294 # number of ReadReq hits 819system.cpu0.icache.demand_hits::cpu0.inst 215729294 # number of demand (read+write) hits 820system.cpu0.icache.demand_hits::total 215729294 # number of demand (read+write) hits 821system.cpu0.icache.overall_hits::cpu0.inst 215729294 # number of overall hits 822system.cpu0.icache.overall_hits::total 215729294 # number of overall hits 823system.cpu0.icache.ReadReq_misses::cpu0.inst 8911978 # number of ReadReq misses 824system.cpu0.icache.ReadReq_misses::total 8911978 # number of ReadReq misses 825system.cpu0.icache.demand_misses::cpu0.inst 8911978 # number of demand (read+write) misses 826system.cpu0.icache.demand_misses::total 8911978 # number of demand (read+write) misses 827system.cpu0.icache.overall_misses::cpu0.inst 8911978 # number of overall misses 828system.cpu0.icache.overall_misses::total 8911978 # number of overall misses 829system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92482342000 # number of ReadReq miss cycles 830system.cpu0.icache.ReadReq_miss_latency::total 92482342000 # number of ReadReq miss cycles 831system.cpu0.icache.demand_miss_latency::cpu0.inst 92482342000 # number of demand (read+write) miss cycles 832system.cpu0.icache.demand_miss_latency::total 92482342000 # number of demand (read+write) miss cycles 833system.cpu0.icache.overall_miss_latency::cpu0.inst 92482342000 # number of overall miss cycles 834system.cpu0.icache.overall_miss_latency::total 92482342000 # number of overall miss cycles 835system.cpu0.icache.ReadReq_accesses::cpu0.inst 224641272 # number of ReadReq accesses(hits+misses) 836system.cpu0.icache.ReadReq_accesses::total 224641272 # number of ReadReq accesses(hits+misses) 837system.cpu0.icache.demand_accesses::cpu0.inst 224641272 # number of demand (read+write) accesses 838system.cpu0.icache.demand_accesses::total 224641272 # number of demand (read+write) accesses 839system.cpu0.icache.overall_accesses::cpu0.inst 224641272 # number of overall (read+write) accesses 840system.cpu0.icache.overall_accesses::total 224641272 # number of overall (read+write) accesses 841system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039672 # miss rate for ReadReq accesses 842system.cpu0.icache.ReadReq_miss_rate::total 0.039672 # miss rate for ReadReq accesses 843system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039672 # miss rate for demand accesses 844system.cpu0.icache.demand_miss_rate::total 0.039672 # miss rate for demand accesses 845system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039672 # miss rate for overall accesses 846system.cpu0.icache.overall_miss_rate::total 0.039672 # miss rate for overall accesses 847system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10377.308158 # average ReadReq miss latency 848system.cpu0.icache.ReadReq_avg_miss_latency::total 10377.308158 # average ReadReq miss latency 849system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10377.308158 # average overall miss latency 850system.cpu0.icache.demand_avg_miss_latency::total 10377.308158 # average overall miss latency 851system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10377.308158 # average overall miss latency 852system.cpu0.icache.overall_avg_miss_latency::total 10377.308158 # average overall miss latency 853system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 854system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 855system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 856system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 857system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 858system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 859system.cpu0.icache.fast_writes 0 # number of fast writes performed 860system.cpu0.icache.cache_copies 0 # number of cache copies performed 861system.cpu0.icache.writebacks::writebacks 8911456 # number of writebacks 862system.cpu0.icache.writebacks::total 8911456 # number of writebacks 863system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8911978 # number of ReadReq MSHR misses 864system.cpu0.icache.ReadReq_mshr_misses::total 8911978 # number of ReadReq MSHR misses 865system.cpu0.icache.demand_mshr_misses::cpu0.inst 8911978 # number of demand (read+write) MSHR misses 866system.cpu0.icache.demand_mshr_misses::total 8911978 # number of demand (read+write) MSHR misses 867system.cpu0.icache.overall_mshr_misses::cpu0.inst 8911978 # number of overall MSHR misses 868system.cpu0.icache.overall_mshr_misses::total 8911978 # number of overall MSHR misses 869system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 870system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 871system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 872system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 873system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88026353500 # number of ReadReq MSHR miss cycles 874system.cpu0.icache.ReadReq_mshr_miss_latency::total 88026353500 # number of ReadReq MSHR miss cycles 875system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88026353500 # number of demand (read+write) MSHR miss cycles 876system.cpu0.icache.demand_mshr_miss_latency::total 88026353500 # number of demand (read+write) MSHR miss cycles 877system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88026353500 # number of overall MSHR miss cycles 878system.cpu0.icache.overall_mshr_miss_latency::total 88026353500 # number of overall MSHR miss cycles 879system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 880system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 881system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 882system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 883system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for ReadReq accesses 884system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039672 # mshr miss rate for ReadReq accesses 885system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for demand accesses 886system.cpu0.icache.demand_mshr_miss_rate::total 0.039672 # mshr miss rate for demand accesses 887system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for overall accesses 888system.cpu0.icache.overall_mshr_miss_rate::total 0.039672 # mshr miss rate for overall accesses 889system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average ReadReq mshr miss latency 890system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9877.308214 # average ReadReq mshr miss latency 891system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency 892system.cpu0.icache.demand_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency 893system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency 894system.cpu0.icache.overall_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency 895system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 896system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 897system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 898system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 899system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 900system.cpu0.l2cache.prefetcher.num_hwpf_issued 7009428 # number of hwpf issued 901system.cpu0.l2cache.prefetcher.pfIdentified 7009488 # number of prefetch candidates identified 902system.cpu0.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue 903system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 904system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 905system.cpu0.l2cache.prefetcher.pfSpanPage 921168 # number of prefetches not generated due to page crossing 906system.cpu0.l2cache.tags.replacements 2475518 # number of replacements 907system.cpu0.l2cache.tags.tagsinuse 16200.233462 # Cycle average of tags in use 908system.cpu0.l2cache.tags.total_refs 22065601 # Total number of references to valid blocks. 909system.cpu0.l2cache.tags.sampled_refs 2491662 # Sample count of references to valid blocks. 910system.cpu0.l2cache.tags.avg_refs 8.855776 # Average number of references to valid blocks. 911system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. 912system.cpu0.l2cache.tags.occ_blocks::writebacks 15248.600129 # Average occupied blocks per requestor 913system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 44.173698 # Average occupied blocks per requestor 914system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 44.219033 # Average occupied blocks per requestor 915system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 863.240603 # Average occupied blocks per requestor 916system.cpu0.l2cache.tags.occ_percent::writebacks 0.930701 # Average percentage of cache occupancy 917system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002696 # Average percentage of cache occupancy 918system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002699 # Average percentage of cache occupancy 919system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052688 # Average percentage of cache occupancy 920system.cpu0.l2cache.tags.occ_percent::total 0.988784 # Average percentage of cache occupancy 921system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1264 # Occupied blocks per task id 922system.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id 923system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14832 # Occupied blocks per task id 924system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 925system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 796 # Occupied blocks per task id 926system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 176 # Occupied blocks per task id 927system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id 928system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 929system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id 930system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1045 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5479 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6042 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2161 # Occupied blocks per task id 936system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.077148 # Percentage of cache occupancy per task id 937system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002930 # Percentage of cache occupancy per task id 938system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id 939system.cpu0.l2cache.tags.tag_accesses 474836128 # Number of tag accesses 940system.cpu0.l2cache.tags.data_accesses 474836128 # Number of data accesses 941system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 472021 # number of ReadReq hits 942system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147981 # number of ReadReq hits 943system.cpu0.l2cache.ReadReq_hits::total 620002 # number of ReadReq hits 944system.cpu0.l2cache.WritebackDirty_hits::writebacks 3408595 # number of WritebackDirty hits 945system.cpu0.l2cache.WritebackDirty_hits::total 3408595 # number of WritebackDirty hits 946system.cpu0.l2cache.WritebackClean_hits::writebacks 10690717 # number of WritebackClean hits 947system.cpu0.l2cache.WritebackClean_hits::total 10690717 # number of WritebackClean hits 948system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits 949system.cpu0.l2cache.UpgradeReq_hits::total 115 # number of UpgradeReq hits 950system.cpu0.l2cache.ReadExReq_hits::cpu0.data 789207 # number of ReadExReq hits 951system.cpu0.l2cache.ReadExReq_hits::total 789207 # number of ReadExReq hits 952system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8250320 # number of ReadCleanReq hits 953system.cpu0.l2cache.ReadCleanReq_hits::total 8250320 # number of ReadCleanReq hits 954system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2605662 # number of ReadSharedReq hits 955system.cpu0.l2cache.ReadSharedReq_hits::total 2605662 # number of ReadSharedReq hits 956system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 165539 # number of InvalidateReq hits 957system.cpu0.l2cache.InvalidateReq_hits::total 165539 # number of InvalidateReq hits 958system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 472021 # number of demand (read+write) hits 959system.cpu0.l2cache.demand_hits::cpu0.itb.walker 147981 # number of demand (read+write) hits 960system.cpu0.l2cache.demand_hits::cpu0.inst 8250320 # number of demand (read+write) hits 961system.cpu0.l2cache.demand_hits::cpu0.data 3394869 # number of demand (read+write) hits 962system.cpu0.l2cache.demand_hits::total 12265191 # number of demand (read+write) hits 963system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 472021 # number of overall hits 964system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147981 # number of overall hits 965system.cpu0.l2cache.overall_hits::cpu0.inst 8250320 # number of overall hits 966system.cpu0.l2cache.overall_hits::cpu0.data 3394869 # number of overall hits 967system.cpu0.l2cache.overall_hits::total 12265191 # number of overall hits 968system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10450 # number of ReadReq misses 969system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7208 # number of ReadReq misses 970system.cpu0.l2cache.ReadReq_misses::total 17658 # number of ReadReq misses 971system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 972system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 973system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242851 # number of UpgradeReq misses 974system.cpu0.l2cache.UpgradeReq_misses::total 242851 # number of UpgradeReq misses 975system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 178501 # number of SCUpgradeReq misses 976system.cpu0.l2cache.SCUpgradeReq_misses::total 178501 # number of SCUpgradeReq misses 977system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 978system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 979system.cpu0.l2cache.ReadExReq_misses::cpu0.data 254335 # number of ReadExReq misses 980system.cpu0.l2cache.ReadExReq_misses::total 254335 # number of ReadExReq misses 981system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 661657 # number of ReadCleanReq misses 982system.cpu0.l2cache.ReadCleanReq_misses::total 661657 # number of ReadCleanReq misses 983system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 900762 # number of ReadSharedReq misses 984system.cpu0.l2cache.ReadSharedReq_misses::total 900762 # number of ReadSharedReq misses 985system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 561341 # number of InvalidateReq misses 986system.cpu0.l2cache.InvalidateReq_misses::total 561341 # number of InvalidateReq misses 987system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10450 # number of demand (read+write) misses 988system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7208 # number of demand (read+write) misses 989system.cpu0.l2cache.demand_misses::cpu0.inst 661657 # number of demand (read+write) misses 990system.cpu0.l2cache.demand_misses::cpu0.data 1155097 # number of demand (read+write) misses 991system.cpu0.l2cache.demand_misses::total 1834412 # number of demand (read+write) misses 992system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10450 # number of overall misses 993system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7208 # number of overall misses 994system.cpu0.l2cache.overall_misses::cpu0.inst 661657 # number of overall misses 995system.cpu0.l2cache.overall_misses::cpu0.data 1155097 # number of overall misses 996system.cpu0.l2cache.overall_misses::total 1834412 # number of overall misses 997system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 323189500 # number of ReadReq miss cycles 998system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 243712500 # number of ReadReq miss cycles 999system.cpu0.l2cache.ReadReq_miss_latency::total 566902000 # number of ReadReq miss cycles 1000system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3278340000 # number of UpgradeReq miss cycles 1001system.cpu0.l2cache.UpgradeReq_miss_latency::total 3278340000 # number of UpgradeReq miss cycles 1002system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1776981500 # number of SCUpgradeReq miss cycles 1003system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1776981500 # number of SCUpgradeReq miss cycles 1004system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4439499 # number of SCUpgradeFailReq miss cycles 1005system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4439499 # number of SCUpgradeFailReq miss cycles 1006system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15942119997 # number of ReadExReq miss cycles 1007system.cpu0.l2cache.ReadExReq_miss_latency::total 15942119997 # number of ReadExReq miss cycles 1008system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24805875000 # number of ReadCleanReq miss cycles 1009system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24805875000 # number of ReadCleanReq miss cycles 1010system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33147375490 # number of ReadSharedReq miss cycles 1011system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33147375490 # number of ReadSharedReq miss cycles 1012system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 64101878000 # number of InvalidateReq miss cycles 1013system.cpu0.l2cache.InvalidateReq_miss_latency::total 64101878000 # number of InvalidateReq miss cycles 1014system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 323189500 # number of demand (read+write) miss cycles 1015system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 243712500 # number of demand (read+write) miss cycles 1016system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24805875000 # number of demand (read+write) miss cycles 1017system.cpu0.l2cache.demand_miss_latency::cpu0.data 49089495487 # number of demand (read+write) miss cycles 1018system.cpu0.l2cache.demand_miss_latency::total 74462272487 # number of demand (read+write) miss cycles 1019system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 323189500 # number of overall miss cycles 1020system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 243712500 # number of overall miss cycles 1021system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24805875000 # number of overall miss cycles 1022system.cpu0.l2cache.overall_miss_latency::cpu0.data 49089495487 # number of overall miss cycles 1023system.cpu0.l2cache.overall_miss_latency::total 74462272487 # number of overall miss cycles 1024system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 482471 # number of ReadReq accesses(hits+misses) 1025system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155189 # number of ReadReq accesses(hits+misses) 1026system.cpu0.l2cache.ReadReq_accesses::total 637660 # number of ReadReq accesses(hits+misses) 1027system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3408595 # number of WritebackDirty accesses(hits+misses) 1028system.cpu0.l2cache.WritebackDirty_accesses::total 3408595 # number of WritebackDirty accesses(hits+misses) 1029system.cpu0.l2cache.WritebackClean_accesses::writebacks 10690718 # number of WritebackClean accesses(hits+misses) 1030system.cpu0.l2cache.WritebackClean_accesses::total 10690718 # number of WritebackClean accesses(hits+misses) 1031system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242966 # number of UpgradeReq accesses(hits+misses) 1032system.cpu0.l2cache.UpgradeReq_accesses::total 242966 # number of UpgradeReq accesses(hits+misses) 1033system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 178501 # number of SCUpgradeReq accesses(hits+misses) 1034system.cpu0.l2cache.SCUpgradeReq_accesses::total 178501 # number of SCUpgradeReq accesses(hits+misses) 1035system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1036system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1037system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1043542 # number of ReadExReq accesses(hits+misses) 1038system.cpu0.l2cache.ReadExReq_accesses::total 1043542 # number of ReadExReq accesses(hits+misses) 1039system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 8911977 # number of ReadCleanReq accesses(hits+misses) 1040system.cpu0.l2cache.ReadCleanReq_accesses::total 8911977 # number of ReadCleanReq accesses(hits+misses) 1041system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3506424 # number of ReadSharedReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadSharedReq_accesses::total 3506424 # number of ReadSharedReq accesses(hits+misses) 1043system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 726880 # number of InvalidateReq accesses(hits+misses) 1044system.cpu0.l2cache.InvalidateReq_accesses::total 726880 # number of InvalidateReq accesses(hits+misses) 1045system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 482471 # number of demand (read+write) accesses 1046system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155189 # number of demand (read+write) accesses 1047system.cpu0.l2cache.demand_accesses::cpu0.inst 8911977 # number of demand (read+write) accesses 1048system.cpu0.l2cache.demand_accesses::cpu0.data 4549966 # number of demand (read+write) accesses 1049system.cpu0.l2cache.demand_accesses::total 14099603 # number of demand (read+write) accesses 1050system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 482471 # number of overall (read+write) accesses 1051system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155189 # number of overall (read+write) accesses 1052system.cpu0.l2cache.overall_accesses::cpu0.inst 8911977 # number of overall (read+write) accesses 1053system.cpu0.l2cache.overall_accesses::cpu0.data 4549966 # number of overall (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::total 14099603 # number of overall (read+write) accesses 1055system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021659 # miss rate for ReadReq accesses 1056system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046447 # miss rate for ReadReq accesses 1057system.cpu0.l2cache.ReadReq_miss_rate::total 0.027692 # miss rate for ReadReq accesses 1058system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1059system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1060system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999527 # miss rate for UpgradeReq accesses 1061system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999527 # miss rate for UpgradeReq accesses 1062system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1063system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1064system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1065system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1066system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.243723 # miss rate for ReadExReq accesses 1067system.cpu0.l2cache.ReadExReq_miss_rate::total 0.243723 # miss rate for ReadExReq accesses 1068system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.074244 # miss rate for ReadCleanReq accesses 1069system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.074244 # miss rate for ReadCleanReq accesses 1070system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.256889 # miss rate for ReadSharedReq accesses 1071system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.256889 # miss rate for ReadSharedReq accesses 1072system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.772261 # miss rate for InvalidateReq accesses 1073system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.772261 # miss rate for InvalidateReq accesses 1074system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021659 # miss rate for demand accesses 1075system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046447 # miss rate for demand accesses 1076system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.074244 # miss rate for demand accesses 1077system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253869 # miss rate for demand accesses 1078system.cpu0.l2cache.demand_miss_rate::total 0.130104 # miss rate for demand accesses 1079system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021659 # miss rate for overall accesses 1080system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046447 # miss rate for overall accesses 1081system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.074244 # miss rate for overall accesses 1082system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253869 # miss rate for overall accesses 1083system.cpu0.l2cache.overall_miss_rate::total 0.130104 # miss rate for overall accesses 1084system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30927.224880 # average ReadReq miss latency 1085system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33811.390122 # average ReadReq miss latency 1086system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32104.541851 # average ReadReq miss latency 1087system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13499.388514 # average UpgradeReq miss latency 1088system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13499.388514 # average UpgradeReq miss latency 1089system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9955.022661 # average SCUpgradeReq miss latency 1090system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9955.022661 # average SCUpgradeReq miss latency 1091system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1109874.750000 # average SCUpgradeFailReq miss latency 1092system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1109874.750000 # average SCUpgradeFailReq miss latency 1093system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62681.581367 # average ReadExReq miss latency 1094system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62681.581367 # average ReadExReq miss latency 1095system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37490.535126 # average ReadCleanReq miss latency 1096system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37490.535126 # average ReadCleanReq miss latency 1097system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36799.260504 # average ReadSharedReq miss latency 1098system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36799.260504 # average ReadSharedReq miss latency 1099system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114194.184996 # average InvalidateReq miss latency 1100system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114194.184996 # average InvalidateReq miss latency 1101system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30927.224880 # average overall miss latency 1102system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33811.390122 # average overall miss latency 1103system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37490.535126 # average overall miss latency 1104system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42498.158585 # average overall miss latency 1105system.cpu0.l2cache.demand_avg_miss_latency::total 40591.902194 # average overall miss latency 1106system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30927.224880 # average overall miss latency 1107system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33811.390122 # average overall miss latency 1108system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37490.535126 # average overall miss latency 1109system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42498.158585 # average overall miss latency 1110system.cpu0.l2cache.overall_avg_miss_latency::total 40591.902194 # average overall miss latency 1111system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1112system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1113system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1114system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1115system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1116system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1117system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1118system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1119system.cpu0.l2cache.writebacks::writebacks 1435569 # number of writebacks 1120system.cpu0.l2cache.writebacks::total 1435569 # number of writebacks 1121system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 1122system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1123system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4123 # number of ReadExReq MSHR hits 1124system.cpu0.l2cache.ReadExReq_mshr_hits::total 4123 # number of ReadExReq MSHR hits 1125system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits 1126system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 1127system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 932 # number of ReadSharedReq MSHR hits 1128system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 932 # number of ReadSharedReq MSHR hits 1129system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits 1130system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 1131system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5055 # number of demand (read+write) MSHR hits 1132system.cpu0.l2cache.demand_mshr_hits::total 5064 # number of demand (read+write) MSHR hits 1133system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits 1134system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 1135system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5055 # number of overall MSHR hits 1136system.cpu0.l2cache.overall_mshr_hits::total 5064 # number of overall MSHR hits 1137system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10450 # number of ReadReq MSHR misses 1138system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7206 # number of ReadReq MSHR misses 1139system.cpu0.l2cache.ReadReq_mshr_misses::total 17656 # number of ReadReq MSHR misses 1140system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 1141system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 1142system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 688849 # number of HardPFReq MSHR misses 1143system.cpu0.l2cache.HardPFReq_mshr_misses::total 688849 # number of HardPFReq MSHR misses 1144system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 242851 # number of UpgradeReq MSHR misses 1145system.cpu0.l2cache.UpgradeReq_mshr_misses::total 242851 # number of UpgradeReq MSHR misses 1146system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 178501 # number of SCUpgradeReq MSHR misses 1147system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 178501 # number of SCUpgradeReq MSHR misses 1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1150system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 250212 # number of ReadExReq MSHR misses 1151system.cpu0.l2cache.ReadExReq_mshr_misses::total 250212 # number of ReadExReq MSHR misses 1152system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 661650 # number of ReadCleanReq MSHR misses 1153system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 661650 # number of ReadCleanReq MSHR misses 1154system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 899830 # number of ReadSharedReq MSHR misses 1155system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 899830 # number of ReadSharedReq MSHR misses 1156system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 561341 # number of InvalidateReq MSHR misses 1157system.cpu0.l2cache.InvalidateReq_mshr_misses::total 561341 # number of InvalidateReq MSHR misses 1158system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10450 # number of demand (read+write) MSHR misses 1159system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7206 # number of demand (read+write) MSHR misses 1160system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 661650 # number of demand (read+write) MSHR misses 1161system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1150042 # number of demand (read+write) MSHR misses 1162system.cpu0.l2cache.demand_mshr_misses::total 1829348 # number of demand (read+write) MSHR misses 1163system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10450 # number of overall MSHR misses 1164system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7206 # number of overall MSHR misses 1165system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 661650 # number of overall MSHR misses 1166system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1150042 # number of overall MSHR misses 1167system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 688849 # number of overall MSHR misses 1168system.cpu0.l2cache.overall_mshr_misses::total 2518197 # number of overall MSHR misses 1169system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 1170system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable 1171system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 69057 # number of ReadReq MSHR uncacheable 1172system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable 1173system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18251 # number of WriteReq MSHR uncacheable 1174system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 1175system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses 1176system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87308 # number of overall MSHR uncacheable misses 1177system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 260489500 # number of ReadReq MSHR miss cycles 1178system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 200447500 # number of ReadReq MSHR miss cycles 1179system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 460937000 # number of ReadReq MSHR miss cycles 1180system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28313104052 # number of HardPFReq MSHR miss cycles 1181system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 28313104052 # number of HardPFReq MSHR miss cycles 1182system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7480349995 # number of UpgradeReq MSHR miss cycles 1183system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7480349995 # number of UpgradeReq MSHR miss cycles 1184system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3483043000 # number of SCUpgradeReq MSHR miss cycles 1185system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3483043000 # number of SCUpgradeReq MSHR miss cycles 1186system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4127499 # number of SCUpgradeFailReq MSHR miss cycles 1187system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4127499 # number of SCUpgradeFailReq MSHR miss cycles 1188system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13883735997 # number of ReadExReq MSHR miss cycles 1189system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13883735997 # number of ReadExReq MSHR miss cycles 1190system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20835719500 # number of ReadCleanReq MSHR miss cycles 1191system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20835719500 # number of ReadCleanReq MSHR miss cycles 1192system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27673983990 # number of ReadSharedReq MSHR miss cycles 1193system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27673983990 # number of ReadSharedReq MSHR miss cycles 1194system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 60733832000 # number of InvalidateReq MSHR miss cycles 1195system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 60733832000 # number of InvalidateReq MSHR miss cycles 1196system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 260489500 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 200447500 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20835719500 # number of demand (read+write) MSHR miss cycles 1199system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41557719987 # number of demand (read+write) MSHR miss cycles 1200system.cpu0.l2cache.demand_mshr_miss_latency::total 62854376487 # number of demand (read+write) MSHR miss cycles 1201system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 260489500 # number of overall MSHR miss cycles 1202system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 200447500 # number of overall MSHR miss cycles 1203system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20835719500 # number of overall MSHR miss cycles 1204system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41557719987 # number of overall MSHR miss cycles 1205system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28313104052 # number of overall MSHR miss cycles 1206system.cpu0.l2cache.overall_mshr_miss_latency::total 91167480539 # number of overall MSHR miss cycles 1207system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 1208system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2887260500 # number of ReadReq MSHR uncacheable cycles 1209system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9883415500 # number of ReadReq MSHR uncacheable cycles 1210system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3121073500 # number of WriteReq MSHR uncacheable cycles 1211system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3121073500 # number of WriteReq MSHR uncacheable cycles 1212system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 1213system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6008334000 # number of overall MSHR uncacheable cycles 1214system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 13004489000 # number of overall MSHR uncacheable cycles 1215system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for ReadReq accesses 1216system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for ReadReq accesses 1217system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027689 # mshr miss rate for ReadReq accesses 1218system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1219system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1220system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1221system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1222system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999527 # mshr miss rate for UpgradeReq accesses 1223system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999527 # mshr miss rate for UpgradeReq accesses 1224system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1225system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1226system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1227system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1228system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239772 # mshr miss rate for ReadExReq accesses 1229system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239772 # mshr miss rate for ReadExReq accesses 1230system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for ReadCleanReq accesses 1231system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074243 # mshr miss rate for ReadCleanReq accesses 1232system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.256623 # mshr miss rate for ReadSharedReq accesses 1233system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.256623 # mshr miss rate for ReadSharedReq accesses 1234system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772261 # mshr miss rate for InvalidateReq accesses 1235system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772261 # mshr miss rate for InvalidateReq accesses 1236system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for demand accesses 1237system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for demand accesses 1238system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for demand accesses 1239system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for demand accesses 1240system.cpu0.l2cache.demand_mshr_miss_rate::total 0.129745 # mshr miss rate for demand accesses 1241system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for overall accesses 1242system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for overall accesses 1243system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for overall accesses 1244system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for overall accesses 1245system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1246system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178601 # mshr miss rate for overall accesses 1247system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average ReadReq mshr miss latency 1248system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average ReadReq mshr miss latency 1249system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26106.536022 # average ReadReq mshr miss latency 1250system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average HardPFReq mshr miss latency 1251system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41102.047113 # average HardPFReq mshr miss latency 1252system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30802.220271 # average UpgradeReq mshr miss latency 1253system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30802.220271 # average UpgradeReq mshr miss latency 1254system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19512.736623 # average SCUpgradeReq mshr miss latency 1255system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19512.736623 # average SCUpgradeReq mshr miss latency 1256system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1031874.750000 # average SCUpgradeFailReq mshr miss latency 1257system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031874.750000 # average SCUpgradeFailReq mshr miss latency 1258system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55487.890257 # average ReadExReq mshr miss latency 1259system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.890257 # average ReadExReq mshr miss latency 1260system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average ReadCleanReq mshr miss latency 1261system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31490.545606 # average ReadCleanReq mshr miss latency 1262system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30754.680317 # average ReadSharedReq mshr miss latency 1263system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30754.680317 # average ReadSharedReq mshr miss latency 1264system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108194.184996 # average InvalidateReq mshr miss latency 1265system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108194.184996 # average InvalidateReq mshr miss latency 1266system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency 1267system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency 1268system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency 1269system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency 1270system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34358.895348 # average overall mshr miss latency 1271system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency 1272system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency 1273system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency 1274system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency 1275system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average overall mshr miss latency 1276system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36203.474366 # average overall mshr miss latency 1277system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 1278system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172394.345594 # average ReadReq mshr uncacheable latency 1279system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143119.676499 # average ReadReq mshr uncacheable latency 1280system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171008.355707 # average WriteReq mshr uncacheable latency 1281system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171008.355707 # average WriteReq mshr uncacheable latency 1282system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 1283system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171671.590617 # average overall mshr uncacheable latency 1284system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 148949.569341 # average overall mshr uncacheable latency 1285system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1286system.cpu0.toL2Bus.snoop_filter.tot_requests 29004574 # Total number of requests made to the snoop filter. 1287system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14815953 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1288system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1289system.cpu0.toL2Bus.snoop_filter.tot_snoops 1990994 # Total number of snoops made to the snoop filter. 1290system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1990568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1291system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1292system.cpu0.toL2Bus.trans_dist::ReadReq 781840 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::ReadResp 13286786 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::WriteReq 18251 # Transaction distribution 1295system.cpu0.toL2Bus.trans_dist::WriteResp 18251 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::WritebackDirty 4847792 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::WritebackClean 10690718 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::CleanEvict 2645908 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::HardPFReq 891756 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::UpgradeReq 444613 # Transaction distribution 1301system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 320296 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::UpgradeResp 480335 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::ReadExReq 1119465 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::ReadExResp 1052013 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8911978 # Transaction distribution 1308system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4503059 # Transaction distribution 1309system.cpu0.toL2Bus.trans_dist::InvalidateReq 735449 # Transaction distribution 1310system.cpu0.toL2Bus.trans_dist::InvalidateResp 726880 # Transaction distribution 1311system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26838850 # Packet count per connected master and slave (bytes) 1312system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16809682 # Packet count per connected master and slave (bytes) 1313system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 328338 # Packet count per connected master and slave (bytes) 1314system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1022103 # Packet count per connected master and slave (bytes) 1315system.cpu0.toL2Bus.pkt_count::total 44998973 # Packet count per connected master and slave (bytes) 1316system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1143972032 # Cumulative packet size per connected master and slave (bytes) 1317system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629474552 # Cumulative packet size per connected master and slave (bytes) 1318system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241512 # Cumulative packet size per connected master and slave (bytes) 1319system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3859768 # Cumulative packet size per connected master and slave (bytes) 1320system.cpu0.toL2Bus.pkt_size::total 1778547864 # Cumulative packet size per connected master and slave (bytes) 1321system.cpu0.toL2Bus.snoops 6630650 # Total snoops (count) 1322system.cpu0.toL2Bus.snoop_fanout::samples 21811897 # Request fanout histogram 1323system.cpu0.toL2Bus.snoop_fanout::mean 0.104823 # Request fanout histogram 1324system.cpu0.toL2Bus.snoop_fanout::stdev 0.306390 # Request fanout histogram 1325system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1326system.cpu0.toL2Bus.snoop_fanout::0 19525925 89.52% 89.52% # Request fanout histogram 1327system.cpu0.toL2Bus.snoop_fanout::1 2285546 10.48% 100.00% # Request fanout histogram 1328system.cpu0.toL2Bus.snoop_fanout::2 426 0.00% 100.00% # Request fanout histogram 1329system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1330system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1331system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1332system.cpu0.toL2Bus.snoop_fanout::total 21811897 # Request fanout histogram 1333system.cpu0.toL2Bus.reqLayer0.occupancy 28866629481 # Layer occupancy (ticks) 1334system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1335system.cpu0.toL2Bus.snoopLayer0.occupancy 172367004 # Layer occupancy (ticks) 1336system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1337system.cpu0.toL2Bus.respLayer0.occupancy 13449935466 # Layer occupancy (ticks) 1338system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1339system.cpu0.toL2Bus.respLayer1.occupancy 7428549534 # Layer occupancy (ticks) 1340system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1341system.cpu0.toL2Bus.respLayer2.occupancy 173196405 # Layer occupancy (ticks) 1342system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1343system.cpu0.toL2Bus.respLayer3.occupancy 539756748 # Layer occupancy (ticks) 1344system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1345system.cpu1.branchPred.lookups 127068265 # Number of BP lookups 1346system.cpu1.branchPred.condPredicted 89752795 # Number of conditional branches predicted 1347system.cpu1.branchPred.condIncorrect 6099791 # Number of conditional branches incorrect 1348system.cpu1.branchPred.BTBLookups 94409743 # Number of BTB lookups 1349system.cpu1.branchPred.BTBHits 68319168 # Number of BTB hits 1350system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1351system.cpu1.branchPred.BTBHitPct 72.364531 # BTB Hit Percentage 1352system.cpu1.branchPred.usedRAS 15069899 # Number of times the RAS was used to get a target. 1353system.cpu1.branchPred.RASInCorrect 999135 # Number of incorrect RAS predictions. 1354system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1355system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1356system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1357system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1358system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1359system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1360system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1361system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1362system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1363system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1364system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1365system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1366system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1367system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1368system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1369system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1370system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1371system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1372system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1373system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1374system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1375system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1376system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1377system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1378system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1379system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1380system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1381system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1382system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1383system.cpu1.dtb.walker.walks 271482 # Table walker walks requested 1384system.cpu1.dtb.walker.walksLong 271482 # Table walker walks initiated with long descriptors 1385system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7964 # Level at which table walker walks with long descriptors terminate 1386system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78105 # Level at which table walker walks with long descriptors terminate 1387system.cpu1.dtb.walker.walkWaitTime::samples 271482 # Table walker wait (enqueue to first request) latency 1388system.cpu1.dtb.walker.walkWaitTime::0 271482 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1389system.cpu1.dtb.walker.walkWaitTime::total 271482 # Table walker wait (enqueue to first request) latency 1390system.cpu1.dtb.walker.walkCompletionTime::samples 86069 # Table walker service (enqueue to completion) latency 1391system.cpu1.dtb.walker.walkCompletionTime::mean 22755.010515 # Table walker service (enqueue to completion) latency 1392system.cpu1.dtb.walker.walkCompletionTime::gmean 21243.396519 # Table walker service (enqueue to completion) latency 1393system.cpu1.dtb.walker.walkCompletionTime::stdev 15660.005020 # Table walker service (enqueue to completion) latency 1394system.cpu1.dtb.walker.walkCompletionTime::0-65535 85331 99.14% 99.14% # Table walker service (enqueue to completion) latency 1395system.cpu1.dtb.walker.walkCompletionTime::65536-131071 168 0.20% 99.34% # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walkCompletionTime::131072-196607 495 0.58% 99.91% # Table walker service (enqueue to completion) latency 1397system.cpu1.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.93% # Table walker service (enqueue to completion) latency 1398system.cpu1.dtb.walker.walkCompletionTime::262144-327679 20 0.02% 99.95% # Table walker service (enqueue to completion) latency 1399system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walkCompletionTime::393216-458751 22 0.03% 100.00% # Table walker service (enqueue to completion) latency 1401system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1404system.cpu1.dtb.walker.walkCompletionTime::total 86069 # Table walker service (enqueue to completion) latency 1405system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution 1406system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution 1407system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution 1408system.cpu1.dtb.walker.walkPageSizes::4K 78105 90.75% 90.75% # Table walker page sizes translated 1409system.cpu1.dtb.walker.walkPageSizes::2M 7964 9.25% 100.00% # Table walker page sizes translated 1410system.cpu1.dtb.walker.walkPageSizes::total 86069 # Table walker page sizes translated 1411system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271482 # Table walker requests started/completed, data/inst 1412system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1413system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271482 # Table walker requests started/completed, data/inst 1414system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86069 # Table walker requests started/completed, data/inst 1415system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1416system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86069 # Table walker requests started/completed, data/inst 1417system.cpu1.dtb.walker.walkRequestOrigin::total 357551 # Table walker requests started/completed, data/inst 1418system.cpu1.dtb.inst_hits 0 # ITB inst hits 1419system.cpu1.dtb.inst_misses 0 # ITB inst misses 1420system.cpu1.dtb.read_hits 82675138 # DTB read hits 1421system.cpu1.dtb.read_misses 225741 # DTB read misses 1422system.cpu1.dtb.write_hits 73180273 # DTB write hits 1423system.cpu1.dtb.write_misses 45741 # DTB write misses 1424system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1425system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1426system.cpu1.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 1427system.cpu1.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 1428system.cpu1.dtb.flush_entries 37272 # Number of entries that have been flushed from TLB 1429system.cpu1.dtb.align_faults 1666 # Number of TLB faults due to alignment restrictions 1430system.cpu1.dtb.prefetch_faults 8268 # Number of TLB faults due to prefetch 1431system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1432system.cpu1.dtb.perms_faults 11369 # Number of TLB faults due to permissions restrictions 1433system.cpu1.dtb.read_accesses 82900879 # DTB read accesses 1434system.cpu1.dtb.write_accesses 73226014 # DTB write accesses 1435system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1436system.cpu1.dtb.hits 155855411 # DTB hits 1437system.cpu1.dtb.misses 271482 # DTB misses 1438system.cpu1.dtb.accesses 156126893 # DTB accesses 1439system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1440system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1441system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1442system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1443system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1444system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1445system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1446system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1447system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1448system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1449system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1450system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1451system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1452system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1453system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1454system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1455system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1456system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1457system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1458system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1459system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1460system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1461system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1462system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1463system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1464system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1465system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1466system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1467system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1468system.cpu1.itb.walker.walks 69604 # Table walker walks requested 1469system.cpu1.itb.walker.walksLong 69604 # Table walker walks initiated with long descriptors 1470system.cpu1.itb.walker.walksLongTerminationLevel::Level2 666 # Level at which table walker walks with long descriptors terminate 1471system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61994 # Level at which table walker walks with long descriptors terminate 1472system.cpu1.itb.walker.walkWaitTime::samples 69604 # Table walker wait (enqueue to first request) latency 1473system.cpu1.itb.walker.walkWaitTime::0 69604 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1474system.cpu1.itb.walker.walkWaitTime::total 69604 # Table walker wait (enqueue to first request) latency 1475system.cpu1.itb.walker.walkCompletionTime::samples 62660 # Table walker service (enqueue to completion) latency 1476system.cpu1.itb.walker.walkCompletionTime::mean 25321.249601 # Table walker service (enqueue to completion) latency 1477system.cpu1.itb.walker.walkCompletionTime::gmean 23483.555874 # Table walker service (enqueue to completion) latency 1478system.cpu1.itb.walker.walkCompletionTime::stdev 17582.582178 # Table walker service (enqueue to completion) latency 1479system.cpu1.itb.walker.walkCompletionTime::0-65535 61881 98.76% 98.76% # Table walker service (enqueue to completion) latency 1480system.cpu1.itb.walker.walkCompletionTime::65536-131071 12 0.02% 98.78% # Table walker service (enqueue to completion) latency 1481system.cpu1.itb.walker.walkCompletionTime::131072-196607 712 1.14% 99.91% # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.98% # Table walker service (enqueue to completion) latency 1484system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1485system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::total 62660 # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution 1489system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution 1490system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution 1491system.cpu1.itb.walker.walkPageSizes::4K 61994 98.94% 98.94% # Table walker page sizes translated 1492system.cpu1.itb.walker.walkPageSizes::2M 666 1.06% 100.00% # Table walker page sizes translated 1493system.cpu1.itb.walker.walkPageSizes::total 62660 # Table walker page sizes translated 1494system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1495system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69604 # Table walker requests started/completed, data/inst 1496system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69604 # Table walker requests started/completed, data/inst 1497system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1498system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62660 # Table walker requests started/completed, data/inst 1499system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62660 # Table walker requests started/completed, data/inst 1500system.cpu1.itb.walker.walkRequestOrigin::total 132264 # Table walker requests started/completed, data/inst 1501system.cpu1.itb.inst_hits 226404999 # ITB inst hits 1502system.cpu1.itb.inst_misses 69604 # ITB inst misses 1503system.cpu1.itb.read_hits 0 # DTB read hits 1504system.cpu1.itb.read_misses 0 # DTB read misses 1505system.cpu1.itb.write_hits 0 # DTB write hits 1506system.cpu1.itb.write_misses 0 # DTB write misses 1507system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1508system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1509system.cpu1.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID 1510system.cpu1.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID 1511system.cpu1.itb.flush_entries 26762 # Number of entries that have been flushed from TLB 1512system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1513system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1514system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1515system.cpu1.itb.perms_faults 203402 # Number of TLB faults due to permissions restrictions 1516system.cpu1.itb.read_accesses 0 # DTB read accesses 1517system.cpu1.itb.write_accesses 0 # DTB write accesses 1518system.cpu1.itb.inst_accesses 226474603 # ITB inst accesses 1519system.cpu1.itb.hits 226404999 # DTB hits 1520system.cpu1.itb.misses 69604 # DTB misses 1521system.cpu1.itb.accesses 226474603 # DTB accesses 1522system.cpu1.numCycles 896249910 # number of cpu cycles simulated 1523system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1524system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1525system.cpu1.committedInsts 420934522 # Number of instructions committed 1526system.cpu1.committedOps 495850522 # Number of ops (including micro ops) committed 1527system.cpu1.discardedOps 42911431 # Number of ops (including micro ops) which were discarded before commit 1528system.cpu1.numFetchSuspends 4588 # Number of times Execute suspended instruction fetching 1529system.cpu1.quiesceCycles 93867828238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1530system.cpu1.cpi 2.129191 # CPI: cycles per instruction 1531system.cpu1.ipc 0.469662 # IPC: instructions per cycle 1532system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1533system.cpu1.kern.inst.quiesce 13511 # number of quiesce instructions executed 1534system.cpu1.tickCycles 680922299 # Number of cycles that the object actually ticked 1535system.cpu1.idleCycles 215327611 # Total number of cycles that the object has spent stopped 1536system.cpu1.dcache.tags.replacements 4921419 # number of replacements 1537system.cpu1.dcache.tags.tagsinuse 458.899025 # Cycle average of tags in use 1538system.cpu1.dcache.tags.total_refs 148299852 # Total number of references to valid blocks. 1539system.cpu1.dcache.tags.sampled_refs 4921931 # Sample count of references to valid blocks. 1540system.cpu1.dcache.tags.avg_refs 30.130421 # Average number of references to valid blocks. 1541system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit. 1542system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.899025 # Average occupied blocks per requestor 1543system.cpu1.dcache.tags.occ_percent::cpu1.data 0.896287 # Average percentage of cache occupancy 1544system.cpu1.dcache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy 1545system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1546system.cpu1.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 1547system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 1548system.cpu1.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 1549system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1550system.cpu1.dcache.tags.tag_accesses 313981831 # Number of tag accesses 1551system.cpu1.dcache.tags.data_accesses 313981831 # Number of data accesses 1552system.cpu1.dcache.ReadReq_hits::cpu1.data 76035057 # number of ReadReq hits 1553system.cpu1.dcache.ReadReq_hits::total 76035057 # number of ReadReq hits 1554system.cpu1.dcache.WriteReq_hits::cpu1.data 68321160 # number of WriteReq hits 1555system.cpu1.dcache.WriteReq_hits::total 68321160 # number of WriteReq hits 1556system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232478 # number of SoftPFReq hits 1557system.cpu1.dcache.SoftPFReq_hits::total 232478 # number of SoftPFReq hits 1558system.cpu1.dcache.WriteLineReq_hits::cpu1.data 184182 # number of WriteLineReq hits 1559system.cpu1.dcache.WriteLineReq_hits::total 184182 # number of WriteLineReq hits 1560system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1549703 # number of LoadLockedReq hits 1561system.cpu1.dcache.LoadLockedReq_hits::total 1549703 # number of LoadLockedReq hits 1562system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1524262 # number of StoreCondReq hits 1563system.cpu1.dcache.StoreCondReq_hits::total 1524262 # number of StoreCondReq hits 1564system.cpu1.dcache.demand_hits::cpu1.data 144356217 # number of demand (read+write) hits 1565system.cpu1.dcache.demand_hits::total 144356217 # number of demand (read+write) hits 1566system.cpu1.dcache.overall_hits::cpu1.data 144588695 # number of overall hits 1567system.cpu1.dcache.overall_hits::total 144588695 # number of overall hits 1568system.cpu1.dcache.ReadReq_misses::cpu1.data 3124160 # number of ReadReq misses 1569system.cpu1.dcache.ReadReq_misses::total 3124160 # number of ReadReq misses 1570system.cpu1.dcache.WriteReq_misses::cpu1.data 2104338 # number of WriteReq misses 1571system.cpu1.dcache.WriteReq_misses::total 2104338 # number of WriteReq misses 1572system.cpu1.dcache.SoftPFReq_misses::cpu1.data 561771 # number of SoftPFReq misses 1573system.cpu1.dcache.SoftPFReq_misses::total 561771 # number of SoftPFReq misses 1574system.cpu1.dcache.WriteLineReq_misses::cpu1.data 510720 # number of WriteLineReq misses 1575system.cpu1.dcache.WriteLineReq_misses::total 510720 # number of WriteLineReq misses 1576system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156544 # number of LoadLockedReq misses 1577system.cpu1.dcache.LoadLockedReq_misses::total 156544 # number of LoadLockedReq misses 1578system.cpu1.dcache.StoreCondReq_misses::cpu1.data 180437 # number of StoreCondReq misses 1579system.cpu1.dcache.StoreCondReq_misses::total 180437 # number of StoreCondReq misses 1580system.cpu1.dcache.demand_misses::cpu1.data 5228498 # number of demand (read+write) misses 1581system.cpu1.dcache.demand_misses::total 5228498 # number of demand (read+write) misses 1582system.cpu1.dcache.overall_misses::cpu1.data 5790269 # number of overall misses 1583system.cpu1.dcache.overall_misses::total 5790269 # number of overall misses 1584system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 48221817000 # number of ReadReq miss cycles 1585system.cpu1.dcache.ReadReq_miss_latency::total 48221817000 # number of ReadReq miss cycles 1586system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 44559226500 # number of WriteReq miss cycles 1587system.cpu1.dcache.WriteReq_miss_latency::total 44559226500 # number of WriteReq miss cycles 1588system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19302885000 # number of WriteLineReq miss cycles 1589system.cpu1.dcache.WriteLineReq_miss_latency::total 19302885000 # number of WriteLineReq miss cycles 1590system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2427765500 # number of LoadLockedReq miss cycles 1591system.cpu1.dcache.LoadLockedReq_miss_latency::total 2427765500 # number of LoadLockedReq miss cycles 1592system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5104015500 # number of StoreCondReq miss cycles 1593system.cpu1.dcache.StoreCondReq_miss_latency::total 5104015500 # number of StoreCondReq miss cycles 1594system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7589000 # number of StoreCondFailReq miss cycles 1595system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7589000 # number of StoreCondFailReq miss cycles 1596system.cpu1.dcache.demand_miss_latency::cpu1.data 92781043500 # number of demand (read+write) miss cycles 1597system.cpu1.dcache.demand_miss_latency::total 92781043500 # number of demand (read+write) miss cycles 1598system.cpu1.dcache.overall_miss_latency::cpu1.data 92781043500 # number of overall miss cycles 1599system.cpu1.dcache.overall_miss_latency::total 92781043500 # number of overall miss cycles 1600system.cpu1.dcache.ReadReq_accesses::cpu1.data 79159217 # number of ReadReq accesses(hits+misses) 1601system.cpu1.dcache.ReadReq_accesses::total 79159217 # number of ReadReq accesses(hits+misses) 1602system.cpu1.dcache.WriteReq_accesses::cpu1.data 70425498 # number of WriteReq accesses(hits+misses) 1603system.cpu1.dcache.WriteReq_accesses::total 70425498 # number of WriteReq accesses(hits+misses) 1604system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 794249 # number of SoftPFReq accesses(hits+misses) 1605system.cpu1.dcache.SoftPFReq_accesses::total 794249 # number of SoftPFReq accesses(hits+misses) 1606system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 694902 # number of WriteLineReq accesses(hits+misses) 1607system.cpu1.dcache.WriteLineReq_accesses::total 694902 # number of WriteLineReq accesses(hits+misses) 1608system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1706247 # number of LoadLockedReq accesses(hits+misses) 1609system.cpu1.dcache.LoadLockedReq_accesses::total 1706247 # number of LoadLockedReq accesses(hits+misses) 1610system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1704699 # number of StoreCondReq accesses(hits+misses) 1611system.cpu1.dcache.StoreCondReq_accesses::total 1704699 # number of StoreCondReq accesses(hits+misses) 1612system.cpu1.dcache.demand_accesses::cpu1.data 149584715 # number of demand (read+write) accesses 1613system.cpu1.dcache.demand_accesses::total 149584715 # number of demand (read+write) accesses 1614system.cpu1.dcache.overall_accesses::cpu1.data 150378964 # number of overall (read+write) accesses 1615system.cpu1.dcache.overall_accesses::total 150378964 # number of overall (read+write) accesses 1616system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039467 # miss rate for ReadReq accesses 1617system.cpu1.dcache.ReadReq_miss_rate::total 0.039467 # miss rate for ReadReq accesses 1618system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029880 # miss rate for WriteReq accesses 1619system.cpu1.dcache.WriteReq_miss_rate::total 0.029880 # miss rate for WriteReq accesses 1620system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707298 # miss rate for SoftPFReq accesses 1621system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707298 # miss rate for SoftPFReq accesses 1622system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734953 # miss rate for WriteLineReq accesses 1623system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734953 # miss rate for WriteLineReq accesses 1624system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091748 # miss rate for LoadLockedReq accesses 1625system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091748 # miss rate for LoadLockedReq accesses 1626system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105847 # miss rate for StoreCondReq accesses 1627system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105847 # miss rate for StoreCondReq accesses 1628system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034953 # miss rate for demand accesses 1629system.cpu1.dcache.demand_miss_rate::total 0.034953 # miss rate for demand accesses 1630system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038505 # miss rate for overall accesses 1631system.cpu1.dcache.overall_miss_rate::total 0.038505 # miss rate for overall accesses 1632system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15435.130403 # average ReadReq miss latency 1633system.cpu1.dcache.ReadReq_avg_miss_latency::total 15435.130403 # average ReadReq miss latency 1634system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21174.937914 # average WriteReq miss latency 1635system.cpu1.dcache.WriteReq_avg_miss_latency::total 21174.937914 # average WriteReq miss latency 1636system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37795.435855 # average WriteLineReq miss latency 1637system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37795.435855 # average WriteLineReq miss latency 1638system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15508.518372 # average LoadLockedReq miss latency 1639system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15508.518372 # average LoadLockedReq miss latency 1640system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28286.967196 # average StoreCondReq miss latency 1641system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28286.967196 # average StoreCondReq miss latency 1642system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1643system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1644system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17745.257529 # average overall miss latency 1645system.cpu1.dcache.demand_avg_miss_latency::total 17745.257529 # average overall miss latency 1646system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16023.615397 # average overall miss latency 1647system.cpu1.dcache.overall_avg_miss_latency::total 16023.615397 # average overall miss latency 1648system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1649system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1650system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1651system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1652system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1653system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1654system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1655system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1656system.cpu1.dcache.writebacks::writebacks 4921438 # number of writebacks 1657system.cpu1.dcache.writebacks::total 4921438 # number of writebacks 1658system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 336855 # number of ReadReq MSHR hits 1659system.cpu1.dcache.ReadReq_mshr_hits::total 336855 # number of ReadReq MSHR hits 1660system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 865157 # number of WriteReq MSHR hits 1661system.cpu1.dcache.WriteReq_mshr_hits::total 865157 # number of WriteReq MSHR hits 1662system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 99 # number of WriteLineReq MSHR hits 1663system.cpu1.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits 1664system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39963 # number of LoadLockedReq MSHR hits 1665system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39963 # number of LoadLockedReq MSHR hits 1666system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 44 # number of StoreCondReq MSHR hits 1667system.cpu1.dcache.StoreCondReq_mshr_hits::total 44 # number of StoreCondReq MSHR hits 1668system.cpu1.dcache.demand_mshr_hits::cpu1.data 1202012 # number of demand (read+write) MSHR hits 1669system.cpu1.dcache.demand_mshr_hits::total 1202012 # number of demand (read+write) MSHR hits 1670system.cpu1.dcache.overall_mshr_hits::cpu1.data 1202012 # number of overall MSHR hits 1671system.cpu1.dcache.overall_mshr_hits::total 1202012 # number of overall MSHR hits 1672system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2787305 # number of ReadReq MSHR misses 1673system.cpu1.dcache.ReadReq_mshr_misses::total 2787305 # number of ReadReq MSHR misses 1674system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1239181 # number of WriteReq MSHR misses 1675system.cpu1.dcache.WriteReq_mshr_misses::total 1239181 # number of WriteReq MSHR misses 1676system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 561309 # number of SoftPFReq MSHR misses 1677system.cpu1.dcache.SoftPFReq_mshr_misses::total 561309 # number of SoftPFReq MSHR misses 1678system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 510621 # number of WriteLineReq MSHR misses 1679system.cpu1.dcache.WriteLineReq_mshr_misses::total 510621 # number of WriteLineReq MSHR misses 1680system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116581 # number of LoadLockedReq MSHR misses 1681system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116581 # number of LoadLockedReq MSHR misses 1682system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 180393 # number of StoreCondReq MSHR misses 1683system.cpu1.dcache.StoreCondReq_mshr_misses::total 180393 # number of StoreCondReq MSHR misses 1684system.cpu1.dcache.demand_mshr_misses::cpu1.data 4026486 # number of demand (read+write) MSHR misses 1685system.cpu1.dcache.demand_mshr_misses::total 4026486 # number of demand (read+write) MSHR misses 1686system.cpu1.dcache.overall_mshr_misses::cpu1.data 4587795 # number of overall MSHR misses 1687system.cpu1.dcache.overall_mshr_misses::total 4587795 # number of overall MSHR misses 1688system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20902 # number of ReadReq MSHR uncacheable 1689system.cpu1.dcache.ReadReq_mshr_uncacheable::total 20902 # number of ReadReq MSHR uncacheable 1690system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19312 # number of WriteReq MSHR uncacheable 1691system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19312 # number of WriteReq MSHR uncacheable 1692system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40214 # number of overall MSHR uncacheable misses 1693system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40214 # number of overall MSHR uncacheable misses 1694system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38841507500 # number of ReadReq MSHR miss cycles 1695system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38841507500 # number of ReadReq MSHR miss cycles 1696system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26434060500 # number of WriteReq MSHR miss cycles 1697system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26434060500 # number of WriteReq MSHR miss cycles 1698system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12644921000 # number of SoftPFReq MSHR miss cycles 1699system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12644921000 # number of SoftPFReq MSHR miss cycles 1700system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 18783135000 # number of WriteLineReq MSHR miss cycles 1701system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 18783135000 # number of WriteLineReq MSHR miss cycles 1702system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1568875000 # number of LoadLockedReq MSHR miss cycles 1703system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1568875000 # number of LoadLockedReq MSHR miss cycles 1704system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4920605000 # number of StoreCondReq MSHR miss cycles 1705system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4920605000 # number of StoreCondReq MSHR miss cycles 1706system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 7128000 # number of StoreCondFailReq MSHR miss cycles 1707system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 7128000 # number of StoreCondFailReq MSHR miss cycles 1708system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 65275568000 # number of demand (read+write) MSHR miss cycles 1709system.cpu1.dcache.demand_mshr_miss_latency::total 65275568000 # number of demand (read+write) MSHR miss cycles 1710system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 77920489000 # number of overall MSHR miss cycles 1711system.cpu1.dcache.overall_mshr_miss_latency::total 77920489000 # number of overall MSHR miss cycles 1712system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3868216000 # number of ReadReq MSHR uncacheable cycles 1713system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3868216000 # number of ReadReq MSHR uncacheable cycles 1714system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3618681000 # number of WriteReq MSHR uncacheable cycles 1715system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3618681000 # number of WriteReq MSHR uncacheable cycles 1716system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7486897000 # number of overall MSHR uncacheable cycles 1717system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7486897000 # number of overall MSHR uncacheable cycles 1718system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035211 # mshr miss rate for ReadReq accesses 1719system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035211 # mshr miss rate for ReadReq accesses 1720system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017596 # mshr miss rate for WriteReq accesses 1721system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017596 # mshr miss rate for WriteReq accesses 1722system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706717 # mshr miss rate for SoftPFReq accesses 1723system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706717 # mshr miss rate for SoftPFReq accesses 1724system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734810 # mshr miss rate for WriteLineReq accesses 1725system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734810 # mshr miss rate for WriteLineReq accesses 1726system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068326 # mshr miss rate for LoadLockedReq accesses 1727system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068326 # mshr miss rate for LoadLockedReq accesses 1728system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105821 # mshr miss rate for StoreCondReq accesses 1729system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105821 # mshr miss rate for StoreCondReq accesses 1730system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026918 # mshr miss rate for demand accesses 1731system.cpu1.dcache.demand_mshr_miss_rate::total 0.026918 # mshr miss rate for demand accesses 1732system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030508 # mshr miss rate for overall accesses 1733system.cpu1.dcache.overall_mshr_miss_rate::total 0.030508 # mshr miss rate for overall accesses 1734system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13935.147930 # average ReadReq mshr miss latency 1735system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13935.147930 # average ReadReq mshr miss latency 1736system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21331.880089 # average WriteReq mshr miss latency 1737system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21331.880089 # average WriteReq mshr miss latency 1738system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22527.557905 # average SoftPFReq mshr miss latency 1739system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22527.557905 # average SoftPFReq mshr miss latency 1740system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36784.885463 # average WriteLineReq mshr miss latency 1741system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36784.885463 # average WriteLineReq mshr miss latency 1742system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13457.381563 # average LoadLockedReq mshr miss latency 1743system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13457.381563 # average LoadLockedReq mshr miss latency 1744system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27277.139357 # average StoreCondReq mshr miss latency 1745system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27277.139357 # average StoreCondReq mshr miss latency 1746system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1747system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1748system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16211.547240 # average overall mshr miss latency 1749system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16211.547240 # average overall mshr miss latency 1750system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16984.300519 # average overall mshr miss latency 1751system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16984.300519 # average overall mshr miss latency 1752system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185064.395752 # average ReadReq mshr uncacheable latency 1753system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185064.395752 # average ReadReq mshr uncacheable latency 1754system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187379.919221 # average WriteReq mshr uncacheable latency 1755system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187379.919221 # average WriteReq mshr uncacheable latency 1756system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186176.381360 # average overall mshr uncacheable latency 1757system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186176.381360 # average overall mshr uncacheable latency 1758system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1759system.cpu1.icache.tags.replacements 9409188 # number of replacements 1760system.cpu1.icache.tags.tagsinuse 506.684863 # Cycle average of tags in use 1761system.cpu1.icache.tags.total_refs 216784534 # Total number of references to valid blocks. 1762system.cpu1.icache.tags.sampled_refs 9409700 # Sample count of references to valid blocks. 1763system.cpu1.icache.tags.avg_refs 23.038411 # Average number of references to valid blocks. 1764system.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit. 1765system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684863 # Average occupied blocks per requestor 1766system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy 1767system.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy 1768system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1769system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 1770system.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 1771system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id 1772system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1773system.cpu1.icache.tags.tag_accesses 461798168 # Number of tag accesses 1774system.cpu1.icache.tags.data_accesses 461798168 # Number of data accesses 1775system.cpu1.icache.ReadReq_hits::cpu1.inst 216784534 # number of ReadReq hits 1776system.cpu1.icache.ReadReq_hits::total 216784534 # number of ReadReq hits 1777system.cpu1.icache.demand_hits::cpu1.inst 216784534 # number of demand (read+write) hits 1778system.cpu1.icache.demand_hits::total 216784534 # number of demand (read+write) hits 1779system.cpu1.icache.overall_hits::cpu1.inst 216784534 # number of overall hits 1780system.cpu1.icache.overall_hits::total 216784534 # number of overall hits 1781system.cpu1.icache.ReadReq_misses::cpu1.inst 9409700 # number of ReadReq misses 1782system.cpu1.icache.ReadReq_misses::total 9409700 # number of ReadReq misses 1783system.cpu1.icache.demand_misses::cpu1.inst 9409700 # number of demand (read+write) misses 1784system.cpu1.icache.demand_misses::total 9409700 # number of demand (read+write) misses 1785system.cpu1.icache.overall_misses::cpu1.inst 9409700 # number of overall misses 1786system.cpu1.icache.overall_misses::total 9409700 # number of overall misses 1787system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 95979801000 # number of ReadReq miss cycles 1788system.cpu1.icache.ReadReq_miss_latency::total 95979801000 # number of ReadReq miss cycles 1789system.cpu1.icache.demand_miss_latency::cpu1.inst 95979801000 # number of demand (read+write) miss cycles 1790system.cpu1.icache.demand_miss_latency::total 95979801000 # number of demand (read+write) miss cycles 1791system.cpu1.icache.overall_miss_latency::cpu1.inst 95979801000 # number of overall miss cycles 1792system.cpu1.icache.overall_miss_latency::total 95979801000 # number of overall miss cycles 1793system.cpu1.icache.ReadReq_accesses::cpu1.inst 226194234 # number of ReadReq accesses(hits+misses) 1794system.cpu1.icache.ReadReq_accesses::total 226194234 # number of ReadReq accesses(hits+misses) 1795system.cpu1.icache.demand_accesses::cpu1.inst 226194234 # number of demand (read+write) accesses 1796system.cpu1.icache.demand_accesses::total 226194234 # number of demand (read+write) accesses 1797system.cpu1.icache.overall_accesses::cpu1.inst 226194234 # number of overall (read+write) accesses 1798system.cpu1.icache.overall_accesses::total 226194234 # number of overall (read+write) accesses 1799system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041600 # miss rate for ReadReq accesses 1800system.cpu1.icache.ReadReq_miss_rate::total 0.041600 # miss rate for ReadReq accesses 1801system.cpu1.icache.demand_miss_rate::cpu1.inst 0.041600 # miss rate for demand accesses 1802system.cpu1.icache.demand_miss_rate::total 0.041600 # miss rate for demand accesses 1803system.cpu1.icache.overall_miss_rate::cpu1.inst 0.041600 # miss rate for overall accesses 1804system.cpu1.icache.overall_miss_rate::total 0.041600 # miss rate for overall accesses 1805system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10200.091501 # average ReadReq miss latency 1806system.cpu1.icache.ReadReq_avg_miss_latency::total 10200.091501 # average ReadReq miss latency 1807system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency 1808system.cpu1.icache.demand_avg_miss_latency::total 10200.091501 # average overall miss latency 1809system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency 1810system.cpu1.icache.overall_avg_miss_latency::total 10200.091501 # average overall miss latency 1811system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1812system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1813system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1814system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1815system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1816system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1817system.cpu1.icache.fast_writes 0 # number of fast writes performed 1818system.cpu1.icache.cache_copies 0 # number of cache copies performed 1819system.cpu1.icache.writebacks::writebacks 9409188 # number of writebacks 1820system.cpu1.icache.writebacks::total 9409188 # number of writebacks 1821system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9409700 # number of ReadReq MSHR misses 1822system.cpu1.icache.ReadReq_mshr_misses::total 9409700 # number of ReadReq MSHR misses 1823system.cpu1.icache.demand_mshr_misses::cpu1.inst 9409700 # number of demand (read+write) MSHR misses 1824system.cpu1.icache.demand_mshr_misses::total 9409700 # number of demand (read+write) MSHR misses 1825system.cpu1.icache.overall_mshr_misses::cpu1.inst 9409700 # number of overall MSHR misses 1826system.cpu1.icache.overall_mshr_misses::total 9409700 # number of overall MSHR misses 1827system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 1828system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable 1829system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 1830system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses 1831system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91274951000 # number of ReadReq MSHR miss cycles 1832system.cpu1.icache.ReadReq_mshr_miss_latency::total 91274951000 # number of ReadReq MSHR miss cycles 1833system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91274951000 # number of demand (read+write) MSHR miss cycles 1834system.cpu1.icache.demand_mshr_miss_latency::total 91274951000 # number of demand (read+write) MSHR miss cycles 1835system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91274951000 # number of overall MSHR miss cycles 1836system.cpu1.icache.overall_mshr_miss_latency::total 91274951000 # number of overall MSHR miss cycles 1837system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles 1838system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles 1839system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles 1840system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles 1841system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for ReadReq accesses 1842system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041600 # mshr miss rate for ReadReq accesses 1843system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for demand accesses 1844system.cpu1.icache.demand_mshr_miss_rate::total 0.041600 # mshr miss rate for demand accesses 1845system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for overall accesses 1846system.cpu1.icache.overall_mshr_miss_rate::total 0.041600 # mshr miss rate for overall accesses 1847system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average ReadReq mshr miss latency 1848system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9700.091501 # average ReadReq mshr miss latency 1849system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency 1850system.cpu1.icache.demand_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency 1851system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency 1852system.cpu1.icache.overall_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency 1853system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency 1854system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency 1855system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency 1856system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency 1857system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1858system.cpu1.l2cache.prefetcher.num_hwpf_issued 6599308 # number of hwpf issued 1859system.cpu1.l2cache.prefetcher.pfIdentified 6600409 # number of prefetch candidates identified 1860system.cpu1.l2cache.prefetcher.pfBufferHit 970 # number of redundant prefetches already in prefetch queue 1861system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1862system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1863system.cpu1.l2cache.prefetcher.pfSpanPage 793623 # number of prefetches not generated due to page crossing 1864system.cpu1.l2cache.tags.replacements 2151198 # number of replacements 1865system.cpu1.l2cache.tags.tagsinuse 13377.061252 # Cycle average of tags in use 1866system.cpu1.l2cache.tags.total_refs 23203065 # Total number of references to valid blocks. 1867system.cpu1.l2cache.tags.sampled_refs 2166951 # Sample count of references to valid blocks. 1868system.cpu1.l2cache.tags.avg_refs 10.707702 # Average number of references to valid blocks. 1869system.cpu1.l2cache.tags.warmup_cycle 9986150274500 # Cycle when the warmup percentage was hit. 1870system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.259690 # Average occupied blocks per requestor 1871system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.377906 # Average occupied blocks per requestor 1872system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 74.184237 # Average occupied blocks per requestor 1873system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 713.239419 # Average occupied blocks per requestor 1874system.cpu1.l2cache.tags.occ_percent::writebacks 0.764359 # Average percentage of cache occupancy 1875system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004051 # Average percentage of cache occupancy 1876system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004528 # Average percentage of cache occupancy 1877system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043533 # Average percentage of cache occupancy 1878system.cpu1.l2cache.tags.occ_percent::total 0.816471 # Average percentage of cache occupancy 1879system.cpu1.l2cache.tags.occ_task_id_blocks::1022 985 # Occupied blocks per task id 1880system.cpu1.l2cache.tags.occ_task_id_blocks::1023 109 # Occupied blocks per task id 1881system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14659 # Occupied blocks per task id 1882system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 1883system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 1884system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id 1885system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 750 # Occupied blocks per task id 1886system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id 1887system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 46 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1891system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1249 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4750 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8044 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060120 # Percentage of cache occupancy per task id 1897system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006653 # Percentage of cache occupancy per task id 1898system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.894714 # Percentage of cache occupancy per task id 1899system.cpu1.l2cache.tags.tag_accesses 482635734 # Number of tag accesses 1900system.cpu1.l2cache.tags.data_accesses 482635734 # Number of data accesses 1901system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 517404 # number of ReadReq hits 1902system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 182303 # number of ReadReq hits 1903system.cpu1.l2cache.ReadReq_hits::total 699707 # number of ReadReq hits 1904system.cpu1.l2cache.WritebackDirty_hits::writebacks 3095740 # number of WritebackDirty hits 1905system.cpu1.l2cache.WritebackDirty_hits::total 3095740 # number of WritebackDirty hits 1906system.cpu1.l2cache.WritebackClean_hits::writebacks 11232116 # number of WritebackClean hits 1907system.cpu1.l2cache.WritebackClean_hits::total 11232116 # number of WritebackClean hits 1908system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 197 # number of UpgradeReq hits 1909system.cpu1.l2cache.UpgradeReq_hits::total 197 # number of UpgradeReq hits 1910system.cpu1.l2cache.ReadExReq_hits::cpu1.data 799662 # number of ReadExReq hits 1911system.cpu1.l2cache.ReadExReq_hits::total 799662 # number of ReadExReq hits 1912system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8718417 # number of ReadCleanReq hits 1913system.cpu1.l2cache.ReadCleanReq_hits::total 8718417 # number of ReadCleanReq hits 1914system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2602566 # number of ReadSharedReq hits 1915system.cpu1.l2cache.ReadSharedReq_hits::total 2602566 # number of ReadSharedReq hits 1916system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 242267 # number of InvalidateReq hits 1917system.cpu1.l2cache.InvalidateReq_hits::total 242267 # number of InvalidateReq hits 1918system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 517404 # number of demand (read+write) hits 1919system.cpu1.l2cache.demand_hits::cpu1.itb.walker 182303 # number of demand (read+write) hits 1920system.cpu1.l2cache.demand_hits::cpu1.inst 8718417 # number of demand (read+write) hits 1921system.cpu1.l2cache.demand_hits::cpu1.data 3402228 # number of demand (read+write) hits 1922system.cpu1.l2cache.demand_hits::total 12820352 # number of demand (read+write) hits 1923system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 517404 # number of overall hits 1924system.cpu1.l2cache.overall_hits::cpu1.itb.walker 182303 # number of overall hits 1925system.cpu1.l2cache.overall_hits::cpu1.inst 8718417 # number of overall hits 1926system.cpu1.l2cache.overall_hits::cpu1.data 3402228 # number of overall hits 1927system.cpu1.l2cache.overall_hits::total 12820352 # number of overall hits 1928system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10447 # number of ReadReq misses 1929system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7725 # number of ReadReq misses 1930system.cpu1.l2cache.ReadReq_misses::total 18172 # number of ReadReq misses 1931system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 203082 # number of UpgradeReq misses 1932system.cpu1.l2cache.UpgradeReq_misses::total 203082 # number of UpgradeReq misses 1933system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 180388 # number of SCUpgradeReq misses 1934system.cpu1.l2cache.SCUpgradeReq_misses::total 180388 # number of SCUpgradeReq misses 1935system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 1936system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1937system.cpu1.l2cache.ReadExReq_misses::cpu1.data 239405 # number of ReadExReq misses 1938system.cpu1.l2cache.ReadExReq_misses::total 239405 # number of ReadExReq misses 1939system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 691283 # number of ReadCleanReq misses 1940system.cpu1.l2cache.ReadCleanReq_misses::total 691283 # number of ReadCleanReq misses 1941system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 862205 # number of ReadSharedReq misses 1942system.cpu1.l2cache.ReadSharedReq_misses::total 862205 # number of ReadSharedReq misses 1943system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266022 # number of InvalidateReq misses 1944system.cpu1.l2cache.InvalidateReq_misses::total 266022 # number of InvalidateReq misses 1945system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10447 # number of demand (read+write) misses 1946system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7725 # number of demand (read+write) misses 1947system.cpu1.l2cache.demand_misses::cpu1.inst 691283 # number of demand (read+write) misses 1948system.cpu1.l2cache.demand_misses::cpu1.data 1101610 # number of demand (read+write) misses 1949system.cpu1.l2cache.demand_misses::total 1811065 # number of demand (read+write) misses 1950system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10447 # number of overall misses 1951system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7725 # number of overall misses 1952system.cpu1.l2cache.overall_misses::cpu1.inst 691283 # number of overall misses 1953system.cpu1.l2cache.overall_misses::cpu1.data 1101610 # number of overall misses 1954system.cpu1.l2cache.overall_misses::total 1811065 # number of overall misses 1955system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 361003500 # number of ReadReq miss cycles 1956system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 296858500 # number of ReadReq miss cycles 1957system.cpu1.l2cache.ReadReq_miss_latency::total 657862000 # number of ReadReq miss cycles 1958system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3343793000 # number of UpgradeReq miss cycles 1959system.cpu1.l2cache.UpgradeReq_miss_latency::total 3343793000 # number of UpgradeReq miss cycles 1960system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1815465000 # number of SCUpgradeReq miss cycles 1961system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1815465000 # number of SCUpgradeReq miss cycles 1962system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 7003999 # number of SCUpgradeFailReq miss cycles 1963system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 7003999 # number of SCUpgradeFailReq miss cycles 1964system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11577465998 # number of ReadExReq miss cycles 1965system.cpu1.l2cache.ReadExReq_miss_latency::total 11577465998 # number of ReadExReq miss cycles 1966system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24488845500 # number of ReadCleanReq miss cycles 1967system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24488845500 # number of ReadCleanReq miss cycles 1968system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30668978480 # number of ReadSharedReq miss cycles 1969system.cpu1.l2cache.ReadSharedReq_miss_latency::total 30668978480 # number of ReadSharedReq miss cycles 1970system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 16284255500 # number of InvalidateReq miss cycles 1971system.cpu1.l2cache.InvalidateReq_miss_latency::total 16284255500 # number of InvalidateReq miss cycles 1972system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 361003500 # number of demand (read+write) miss cycles 1973system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 296858500 # number of demand (read+write) miss cycles 1974system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24488845500 # number of demand (read+write) miss cycles 1975system.cpu1.l2cache.demand_miss_latency::cpu1.data 42246444478 # number of demand (read+write) miss cycles 1976system.cpu1.l2cache.demand_miss_latency::total 67393151978 # number of demand (read+write) miss cycles 1977system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 361003500 # number of overall miss cycles 1978system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 296858500 # number of overall miss cycles 1979system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24488845500 # number of overall miss cycles 1980system.cpu1.l2cache.overall_miss_latency::cpu1.data 42246444478 # number of overall miss cycles 1981system.cpu1.l2cache.overall_miss_latency::total 67393151978 # number of overall miss cycles 1982system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 527851 # number of ReadReq accesses(hits+misses) 1983system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 190028 # number of ReadReq accesses(hits+misses) 1984system.cpu1.l2cache.ReadReq_accesses::total 717879 # number of ReadReq accesses(hits+misses) 1985system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3095740 # number of WritebackDirty accesses(hits+misses) 1986system.cpu1.l2cache.WritebackDirty_accesses::total 3095740 # number of WritebackDirty accesses(hits+misses) 1987system.cpu1.l2cache.WritebackClean_accesses::writebacks 11232116 # number of WritebackClean accesses(hits+misses) 1988system.cpu1.l2cache.WritebackClean_accesses::total 11232116 # number of WritebackClean accesses(hits+misses) 1989system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 203279 # number of UpgradeReq accesses(hits+misses) 1990system.cpu1.l2cache.UpgradeReq_accesses::total 203279 # number of UpgradeReq accesses(hits+misses) 1991system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 180388 # number of SCUpgradeReq accesses(hits+misses) 1992system.cpu1.l2cache.SCUpgradeReq_accesses::total 180388 # number of SCUpgradeReq accesses(hits+misses) 1993system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1994system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1995system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1039067 # number of ReadExReq accesses(hits+misses) 1996system.cpu1.l2cache.ReadExReq_accesses::total 1039067 # number of ReadExReq accesses(hits+misses) 1997system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9409700 # number of ReadCleanReq accesses(hits+misses) 1998system.cpu1.l2cache.ReadCleanReq_accesses::total 9409700 # number of ReadCleanReq accesses(hits+misses) 1999system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3464771 # number of ReadSharedReq accesses(hits+misses) 2000system.cpu1.l2cache.ReadSharedReq_accesses::total 3464771 # number of ReadSharedReq accesses(hits+misses) 2001system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 508289 # number of InvalidateReq accesses(hits+misses) 2002system.cpu1.l2cache.InvalidateReq_accesses::total 508289 # number of InvalidateReq accesses(hits+misses) 2003system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 527851 # number of demand (read+write) accesses 2004system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 190028 # number of demand (read+write) accesses 2005system.cpu1.l2cache.demand_accesses::cpu1.inst 9409700 # number of demand (read+write) accesses 2006system.cpu1.l2cache.demand_accesses::cpu1.data 4503838 # number of demand (read+write) accesses 2007system.cpu1.l2cache.demand_accesses::total 14631417 # number of demand (read+write) accesses 2008system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 527851 # number of overall (read+write) accesses 2009system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 190028 # number of overall (read+write) accesses 2010system.cpu1.l2cache.overall_accesses::cpu1.inst 9409700 # number of overall (read+write) accesses 2011system.cpu1.l2cache.overall_accesses::cpu1.data 4503838 # number of overall (read+write) accesses 2012system.cpu1.l2cache.overall_accesses::total 14631417 # number of overall (read+write) accesses 2013system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.019792 # miss rate for ReadReq accesses 2014system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.040652 # miss rate for ReadReq accesses 2015system.cpu1.l2cache.ReadReq_miss_rate::total 0.025313 # miss rate for ReadReq accesses 2016system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999031 # miss rate for UpgradeReq accesses 2017system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999031 # miss rate for UpgradeReq accesses 2018system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2019system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2020system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2021system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2022system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230404 # miss rate for ReadExReq accesses 2023system.cpu1.l2cache.ReadExReq_miss_rate::total 0.230404 # miss rate for ReadExReq accesses 2024system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.073465 # miss rate for ReadCleanReq accesses 2025system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.073465 # miss rate for ReadCleanReq accesses 2026system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248849 # miss rate for ReadSharedReq accesses 2027system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248849 # miss rate for ReadSharedReq accesses 2028system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.523368 # miss rate for InvalidateReq accesses 2029system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.523368 # miss rate for InvalidateReq accesses 2030system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.019792 # miss rate for demand accesses 2031system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.040652 # miss rate for demand accesses 2032system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.073465 # miss rate for demand accesses 2033system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244594 # miss rate for demand accesses 2034system.cpu1.l2cache.demand_miss_rate::total 0.123779 # miss rate for demand accesses 2035system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.019792 # miss rate for overall accesses 2036system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.040652 # miss rate for overall accesses 2037system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.073465 # miss rate for overall accesses 2038system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244594 # miss rate for overall accesses 2039system.cpu1.l2cache.overall_miss_rate::total 0.123779 # miss rate for overall accesses 2040system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34555.709773 # average ReadReq miss latency 2041system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38428.284790 # average ReadReq miss latency 2042system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36201.959058 # average ReadReq miss latency 2043system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16465.235718 # average UpgradeReq miss latency 2044system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16465.235718 # average UpgradeReq miss latency 2045system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10064.222676 # average SCUpgradeReq miss latency 2046system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10064.222676 # average SCUpgradeReq miss latency 2047system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1400799.800000 # average SCUpgradeFailReq miss latency 2048system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1400799.800000 # average SCUpgradeFailReq miss latency 2049system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48359.332503 # average ReadExReq miss latency 2050system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48359.332503 # average ReadExReq miss latency 2051system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35425.210080 # average ReadCleanReq miss latency 2052system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35425.210080 # average ReadCleanReq miss latency 2053system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35570.402027 # average ReadSharedReq miss latency 2054system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35570.402027 # average ReadSharedReq miss latency 2055system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 61213.942832 # average InvalidateReq miss latency 2056system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 61213.942832 # average InvalidateReq miss latency 2057system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34555.709773 # average overall miss latency 2058system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38428.284790 # average overall miss latency 2059system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35425.210080 # average overall miss latency 2060system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38349.728559 # average overall miss latency 2061system.cpu1.l2cache.demand_avg_miss_latency::total 37211.890229 # average overall miss latency 2062system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34555.709773 # average overall miss latency 2063system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38428.284790 # average overall miss latency 2064system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35425.210080 # average overall miss latency 2065system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38349.728559 # average overall miss latency 2066system.cpu1.l2cache.overall_avg_miss_latency::total 37211.890229 # average overall miss latency 2067system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2068system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2069system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2070system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2071system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2072system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2073system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2074system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2075system.cpu1.l2cache.writebacks::writebacks 1042577 # number of writebacks 2076system.cpu1.l2cache.writebacks::total 1042577 # number of writebacks 2077system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2078system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2079system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4272 # number of ReadExReq MSHR hits 2080system.cpu1.l2cache.ReadExReq_mshr_hits::total 4272 # number of ReadExReq MSHR hits 2081system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits 2082system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 2083system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1142 # number of ReadSharedReq MSHR hits 2084system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1142 # number of ReadSharedReq MSHR hits 2085system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 2086system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 2087system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5414 # number of demand (read+write) MSHR hits 2088system.cpu1.l2cache.demand_mshr_hits::total 5422 # number of demand (read+write) MSHR hits 2089system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 2090system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 2091system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5414 # number of overall MSHR hits 2092system.cpu1.l2cache.overall_mshr_hits::total 5422 # number of overall MSHR hits 2093system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10447 # number of ReadReq MSHR misses 2094system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7724 # number of ReadReq MSHR misses 2095system.cpu1.l2cache.ReadReq_mshr_misses::total 18171 # number of ReadReq MSHR misses 2096system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 679285 # number of HardPFReq MSHR misses 2097system.cpu1.l2cache.HardPFReq_mshr_misses::total 679285 # number of HardPFReq MSHR misses 2098system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 203082 # number of UpgradeReq MSHR misses 2099system.cpu1.l2cache.UpgradeReq_mshr_misses::total 203082 # number of UpgradeReq MSHR misses 2100system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 180388 # number of SCUpgradeReq MSHR misses 2101system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 180388 # number of SCUpgradeReq MSHR misses 2102system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2103system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2104system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235133 # number of ReadExReq MSHR misses 2105system.cpu1.l2cache.ReadExReq_mshr_misses::total 235133 # number of ReadExReq MSHR misses 2106system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 691276 # number of ReadCleanReq MSHR misses 2107system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 691276 # number of ReadCleanReq MSHR misses 2108system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 861063 # number of ReadSharedReq MSHR misses 2109system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 861063 # number of ReadSharedReq MSHR misses 2110system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266022 # number of InvalidateReq MSHR misses 2111system.cpu1.l2cache.InvalidateReq_mshr_misses::total 266022 # number of InvalidateReq MSHR misses 2112system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10447 # number of demand (read+write) MSHR misses 2113system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7724 # number of demand (read+write) MSHR misses 2114system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 691276 # number of demand (read+write) MSHR misses 2115system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1096196 # number of demand (read+write) MSHR misses 2116system.cpu1.l2cache.demand_mshr_misses::total 1805643 # number of demand (read+write) MSHR misses 2117system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10447 # number of overall MSHR misses 2118system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7724 # number of overall MSHR misses 2119system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 691276 # number of overall MSHR misses 2120system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1096196 # number of overall MSHR misses 2121system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 679285 # number of overall MSHR misses 2122system.cpu1.l2cache.overall_mshr_misses::total 2484928 # number of overall MSHR misses 2123system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2124system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 20902 # number of ReadReq MSHR uncacheable 2125system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 20994 # number of ReadReq MSHR uncacheable 2126system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19312 # number of WriteReq MSHR uncacheable 2127system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19312 # number of WriteReq MSHR uncacheable 2128system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2129system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40214 # number of overall MSHR uncacheable misses 2130system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40306 # number of overall MSHR uncacheable misses 2131system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 298321500 # number of ReadReq MSHR miss cycles 2132system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 250498000 # number of ReadReq MSHR miss cycles 2133system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 548819500 # number of ReadReq MSHR miss cycles 2134system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 24534893187 # number of HardPFReq MSHR miss cycles 2135system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 24534893187 # number of HardPFReq MSHR miss cycles 2136system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6599396497 # number of UpgradeReq MSHR miss cycles 2137system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6599396497 # number of UpgradeReq MSHR miss cycles 2138system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3563733500 # number of SCUpgradeReq MSHR miss cycles 2139system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3563733500 # number of SCUpgradeReq MSHR miss cycles 2140system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6517999 # number of SCUpgradeFailReq MSHR miss cycles 2141system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6517999 # number of SCUpgradeFailReq MSHR miss cycles 2142system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9585687998 # number of ReadExReq MSHR miss cycles 2143system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9585687998 # number of ReadExReq MSHR miss cycles 2144system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20341013500 # number of ReadCleanReq MSHR miss cycles 2145system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20341013500 # number of ReadCleanReq MSHR miss cycles 2146system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25423220980 # number of ReadSharedReq MSHR miss cycles 2147system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25423220980 # number of ReadSharedReq MSHR miss cycles 2148system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 14688123500 # number of InvalidateReq MSHR miss cycles 2149system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 14688123500 # number of InvalidateReq MSHR miss cycles 2150system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 298321500 # number of demand (read+write) MSHR miss cycles 2151system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 250498000 # number of demand (read+write) MSHR miss cycles 2152system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20341013500 # number of demand (read+write) MSHR miss cycles 2153system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35008908978 # number of demand (read+write) MSHR miss cycles 2154system.cpu1.l2cache.demand_mshr_miss_latency::total 55898741978 # number of demand (read+write) MSHR miss cycles 2155system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 298321500 # number of overall MSHR miss cycles 2156system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 250498000 # number of overall MSHR miss cycles 2157system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20341013500 # number of overall MSHR miss cycles 2158system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35008908978 # number of overall MSHR miss cycles 2159system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 24534893187 # number of overall MSHR miss cycles 2160system.cpu1.l2cache.overall_mshr_miss_latency::total 80433635165 # number of overall MSHR miss cycles 2161system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles 2162system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3700892500 # number of ReadReq MSHR uncacheable cycles 2163system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3713107000 # number of ReadReq MSHR uncacheable cycles 2164system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3473788500 # number of WriteReq MSHR uncacheable cycles 2165system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3473788500 # number of WriteReq MSHR uncacheable cycles 2166system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles 2167system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7174681000 # number of overall MSHR uncacheable cycles 2168system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7186895500 # number of overall MSHR uncacheable cycles 2169system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for ReadReq accesses 2170system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for ReadReq accesses 2171system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025312 # mshr miss rate for ReadReq accesses 2172system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2173system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2174system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999031 # mshr miss rate for UpgradeReq accesses 2175system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999031 # mshr miss rate for UpgradeReq accesses 2176system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2177system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2178system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2179system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2180system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226292 # mshr miss rate for ReadExReq accesses 2181system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226292 # mshr miss rate for ReadExReq accesses 2182system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for ReadCleanReq accesses 2183system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073464 # mshr miss rate for ReadCleanReq accesses 2184system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248519 # mshr miss rate for ReadSharedReq accesses 2185system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248519 # mshr miss rate for ReadSharedReq accesses 2186system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.523368 # mshr miss rate for InvalidateReq accesses 2187system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.523368 # mshr miss rate for InvalidateReq accesses 2188system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for demand accesses 2189system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for demand accesses 2190system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for demand accesses 2191system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for demand accesses 2192system.cpu1.l2cache.demand_mshr_miss_rate::total 0.123409 # mshr miss rate for demand accesses 2193system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for overall accesses 2194system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for overall accesses 2195system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for overall accesses 2196system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for overall accesses 2197system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2198system.cpu1.l2cache.overall_mshr_miss_rate::total 0.169835 # mshr miss rate for overall accesses 2199system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average ReadReq mshr miss latency 2200system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average ReadReq mshr miss latency 2201system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30203.043311 # average ReadReq mshr miss latency 2202system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average HardPFReq mshr miss latency 2203system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36118.703029 # average HardPFReq mshr miss latency 2204system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32496.215800 # average UpgradeReq mshr miss latency 2205system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32496.215800 # average UpgradeReq mshr miss latency 2206system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19755.934430 # average SCUpgradeReq mshr miss latency 2207system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19755.934430 # average SCUpgradeReq mshr miss latency 2208system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1303599.800000 # average SCUpgradeFailReq mshr miss latency 2209system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1303599.800000 # average SCUpgradeFailReq mshr miss latency 2210system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 40767.089256 # average ReadExReq mshr miss latency 2211system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 40767.089256 # average ReadExReq mshr miss latency 2212system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average ReadCleanReq mshr miss latency 2213system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29425.314202 # average ReadCleanReq mshr miss latency 2214system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29525.390105 # average ReadSharedReq mshr miss latency 2215system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29525.390105 # average ReadSharedReq mshr miss latency 2216system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55213.942832 # average InvalidateReq mshr miss latency 2217system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55213.942832 # average InvalidateReq mshr miss latency 2218system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency 2219system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency 2220system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency 2221system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency 2222system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30957.803939 # average overall mshr miss latency 2223system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency 2224system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency 2225system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency 2226system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency 2227system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average overall mshr miss latency 2228system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32368.597869 # average overall mshr miss latency 2229system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency 2230system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177059.252703 # average ReadReq mshr uncacheable latency 2231system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176865.151948 # average ReadReq mshr uncacheable latency 2232system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179877.200704 # average WriteReq mshr uncacheable latency 2233system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179877.200704 # average WriteReq mshr uncacheable latency 2234system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency 2235system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178412.518029 # average overall mshr uncacheable latency 2236system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178308.328785 # average overall mshr uncacheable latency 2237system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2238system.cpu1.toL2Bus.snoop_filter.tot_requests 29428527 # Total number of requests made to the snoop filter. 2239system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15006964 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2240system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2768 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2241system.cpu1.toL2Bus.snoop_filter.tot_snoops 1972954 # Total number of snoops made to the snoop filter. 2242system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1972589 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2243system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 365 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2244system.cpu1.toL2Bus.trans_dist::ReadReq 814249 # Transaction distribution 2245system.cpu1.toL2Bus.trans_dist::ReadResp 13775310 # Transaction distribution 2246system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2247system.cpu1.toL2Bus.trans_dist::WriteReq 19312 # Transaction distribution 2248system.cpu1.toL2Bus.trans_dist::WriteResp 19312 # Transaction distribution 2249system.cpu1.toL2Bus.trans_dist::WritebackDirty 4142105 # Transaction distribution 2250system.cpu1.toL2Bus.trans_dist::WritebackClean 11232116 # Transaction distribution 2251system.cpu1.toL2Bus.trans_dist::CleanEvict 2703238 # Transaction distribution 2252system.cpu1.toL2Bus.trans_dist::HardPFReq 874176 # Transaction distribution 2253system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2254system.cpu1.toL2Bus.trans_dist::UpgradeReq 401941 # Transaction distribution 2255system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 322763 # Transaction distribution 2256system.cpu1.toL2Bus.trans_dist::UpgradeResp 444037 # Transaction distribution 2257system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 2258system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 2259system.cpu1.toL2Bus.trans_dist::ReadExReq 1114947 # Transaction distribution 2260system.cpu1.toL2Bus.trans_dist::ReadExResp 1047219 # Transaction distribution 2261system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9409700 # Transaction distribution 2262system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4456605 # Transaction distribution 2263system.cpu1.toL2Bus.trans_dist::InvalidateReq 514166 # Transaction distribution 2264system.cpu1.toL2Bus.trans_dist::InvalidateResp 508289 # Transaction distribution 2265system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28226960 # Packet count per connected master and slave (bytes) 2266system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15947748 # Packet count per connected master and slave (bytes) 2267system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 397923 # Packet count per connected master and slave (bytes) 2268system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1113211 # Packet count per connected master and slave (bytes) 2269system.cpu1.toL2Bus.pkt_count::total 45685842 # Packet count per connected master and slave (bytes) 2270system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1204298752 # Cumulative packet size per connected master and slave (bytes) 2271system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609360975 # Cumulative packet size per connected master and slave (bytes) 2272system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1520224 # Cumulative packet size per connected master and slave (bytes) 2273system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4222808 # Cumulative packet size per connected master and slave (bytes) 2274system.cpu1.toL2Bus.pkt_size::total 1819402759 # Cumulative packet size per connected master and slave (bytes) 2275system.cpu1.toL2Bus.snoops 6269077 # Total snoops (count) 2276system.cpu1.toL2Bus.snoop_fanout::samples 21677519 # Request fanout histogram 2277system.cpu1.toL2Bus.snoop_fanout::mean 0.104647 # Request fanout histogram 2278system.cpu1.toL2Bus.snoop_fanout::stdev 0.306153 # Request fanout histogram 2279system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2280system.cpu1.toL2Bus.snoop_fanout::0 19409393 89.54% 89.54% # Request fanout histogram 2281system.cpu1.toL2Bus.snoop_fanout::1 2267761 10.46% 100.00% # Request fanout histogram 2282system.cpu1.toL2Bus.snoop_fanout::2 365 0.00% 100.00% # Request fanout histogram 2283system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2284system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2285system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2286system.cpu1.toL2Bus.snoop_fanout::total 21677519 # Request fanout histogram 2287system.cpu1.toL2Bus.reqLayer0.occupancy 29325134974 # Layer occupancy (ticks) 2288system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2289system.cpu1.toL2Bus.snoopLayer0.occupancy 172530424 # Layer occupancy (ticks) 2290system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2291system.cpu1.toL2Bus.respLayer0.occupancy 14118247362 # Layer occupancy (ticks) 2292system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2293system.cpu1.toL2Bus.respLayer1.occupancy 7236066136 # Layer occupancy (ticks) 2294system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2295system.cpu1.toL2Bus.respLayer2.occupancy 207955878 # Layer occupancy (ticks) 2296system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2297system.cpu1.toL2Bus.respLayer3.occupancy 585496227 # Layer occupancy (ticks) 2298system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2299system.iobus.trans_dist::ReadReq 40404 # Transaction distribution 2300system.iobus.trans_dist::ReadResp 40404 # Transaction distribution 2301system.iobus.trans_dist::WriteReq 136972 # Transaction distribution 2302system.iobus.trans_dist::WriteResp 136972 # Transaction distribution 2303system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47770 # Packet count per connected master and slave (bytes) 2304system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2305system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2306system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2307system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2308system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2309system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2310system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2311system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2312system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2313system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 2314system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2315system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2316system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2317system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2318system.iobus.pkt_count_system.bridge.master::total 122912 # Packet count per connected master and slave (bytes) 2319system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231760 # Packet count per connected master and slave (bytes) 2320system.iobus.pkt_count_system.realview.ide.dma::total 231760 # Packet count per connected master and slave (bytes) 2321system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2322system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2323system.iobus.pkt_count::total 354752 # Packet count per connected master and slave (bytes) 2324system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47790 # Cumulative packet size per connected master and slave (bytes) 2325system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2326system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2327system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2328system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2329system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2330system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2331system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2332system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2333system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2334system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 2335system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2336system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2337system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2338system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2339system.iobus.pkt_size_system.bridge.master::total 155927 # Cumulative packet size per connected master and slave (bytes) 2340system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355392 # Cumulative packet size per connected master and slave (bytes) 2341system.iobus.pkt_size_system.realview.ide.dma::total 7355392 # Cumulative packet size per connected master and slave (bytes) 2342system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2343system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size::total 7513405 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.reqLayer0.occupancy 47202500 # Layer occupancy (ticks) 2346system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2347system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 2348system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2349system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 2350system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2351system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 2352system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2353system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) 2354system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2355system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 2356system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2357system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 2358system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2359system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2360system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2361system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 2362system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2363system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 2364system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2365system.iobus.reqLayer23.occupancy 25874502 # Layer occupancy (ticks) 2366system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2367system.iobus.reqLayer24.occupancy 168500 # Layer occupancy (ticks) 2368system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2369system.iobus.reqLayer25.occupancy 36406501 # Layer occupancy (ticks) 2370system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2371system.iobus.reqLayer26.occupancy 123500 # Layer occupancy (ticks) 2372system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2373system.iobus.reqLayer27.occupancy 566812397 # Layer occupancy (ticks) 2374system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2375system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) 2376system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2377system.iobus.respLayer0.occupancy 92927000 # Layer occupancy (ticks) 2378system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2379system.iobus.respLayer3.occupancy 148200000 # Layer occupancy (ticks) 2380system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2381system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2382system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2383system.iocache.tags.replacements 115872 # number of replacements 2384system.iocache.tags.tagsinuse 11.264501 # Cycle average of tags in use 2385system.iocache.tags.total_refs 6 # Total number of references to valid blocks. 2386system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. 2387system.iocache.tags.avg_refs 0.000052 # Average number of references to valid blocks. 2388system.iocache.tags.warmup_cycle 9145998133000 # Cycle when the warmup percentage was hit. 2389system.iocache.tags.occ_blocks::realview.ethernet 7.414921 # Average occupied blocks per requestor 2390system.iocache.tags.occ_blocks::realview.ide 3.849581 # Average occupied blocks per requestor 2391system.iocache.tags.occ_percent::realview.ethernet 0.463433 # Average percentage of cache occupancy 2392system.iocache.tags.occ_percent::realview.ide 0.240599 # Average percentage of cache occupancy 2393system.iocache.tags.occ_percent::total 0.704031 # Average percentage of cache occupancy 2394system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2395system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2396system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2397system.iocache.tags.tag_accesses 1043272 # Number of tag accesses 2398system.iocache.tags.data_accesses 1043272 # Number of data accesses 2399system.iocache.WriteLineReq_hits::realview.ide 2 # number of WriteLineReq hits 2400system.iocache.WriteLineReq_hits::total 2 # number of WriteLineReq hits 2401system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2402system.iocache.ReadReq_misses::realview.ide 8896 # number of ReadReq misses 2403system.iocache.ReadReq_misses::total 8933 # number of ReadReq misses 2404system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2405system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2406system.iocache.WriteLineReq_misses::realview.ide 106982 # number of WriteLineReq misses 2407system.iocache.WriteLineReq_misses::total 106982 # number of WriteLineReq misses 2408system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2409system.iocache.demand_misses::realview.ide 8896 # number of demand (read+write) misses 2410system.iocache.demand_misses::total 8936 # number of demand (read+write) misses 2411system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2412system.iocache.overall_misses::realview.ide 8896 # number of overall misses 2413system.iocache.overall_misses::total 8936 # number of overall misses 2414system.iocache.ReadReq_miss_latency::realview.ethernet 5261000 # number of ReadReq miss cycles 2415system.iocache.ReadReq_miss_latency::realview.ide 1700094991 # number of ReadReq miss cycles 2416system.iocache.ReadReq_miss_latency::total 1705355991 # number of ReadReq miss cycles 2417system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2418system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2419system.iocache.WriteLineReq_miss_latency::realview.ide 14013428406 # number of WriteLineReq miss cycles 2420system.iocache.WriteLineReq_miss_latency::total 14013428406 # number of WriteLineReq miss cycles 2421system.iocache.demand_miss_latency::realview.ethernet 5630000 # number of demand (read+write) miss cycles 2422system.iocache.demand_miss_latency::realview.ide 1700094991 # number of demand (read+write) miss cycles 2423system.iocache.demand_miss_latency::total 1705724991 # number of demand (read+write) miss cycles 2424system.iocache.overall_miss_latency::realview.ethernet 5630000 # number of overall miss cycles 2425system.iocache.overall_miss_latency::realview.ide 1700094991 # number of overall miss cycles 2426system.iocache.overall_miss_latency::total 1705724991 # number of overall miss cycles 2427system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2428system.iocache.ReadReq_accesses::realview.ide 8896 # number of ReadReq accesses(hits+misses) 2429system.iocache.ReadReq_accesses::total 8933 # number of ReadReq accesses(hits+misses) 2430system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2431system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2432system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2433system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2434system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2435system.iocache.demand_accesses::realview.ide 8896 # number of demand (read+write) accesses 2436system.iocache.demand_accesses::total 8936 # number of demand (read+write) accesses 2437system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2438system.iocache.overall_accesses::realview.ide 8896 # number of overall (read+write) accesses 2439system.iocache.overall_accesses::total 8936 # number of overall (read+write) accesses 2440system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2441system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2442system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2443system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2444system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2445system.iocache.WriteLineReq_miss_rate::realview.ide 0.999981 # miss rate for WriteLineReq accesses 2446system.iocache.WriteLineReq_miss_rate::total 0.999981 # miss rate for WriteLineReq accesses 2447system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2448system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2449system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2450system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2451system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2452system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2453system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142189.189189 # average ReadReq miss latency 2454system.iocache.ReadReq_avg_miss_latency::realview.ide 191107.800247 # average ReadReq miss latency 2455system.iocache.ReadReq_avg_miss_latency::total 190905.182022 # average ReadReq miss latency 2456system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2457system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2458system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130988.656092 # average WriteLineReq miss latency 2459system.iocache.WriteLineReq_avg_miss_latency::total 130988.656092 # average WriteLineReq miss latency 2460system.iocache.demand_avg_miss_latency::realview.ethernet 140750 # average overall miss latency 2461system.iocache.demand_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency 2462system.iocache.demand_avg_miss_latency::total 190882.384848 # average overall miss latency 2463system.iocache.overall_avg_miss_latency::realview.ethernet 140750 # average overall miss latency 2464system.iocache.overall_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency 2465system.iocache.overall_avg_miss_latency::total 190882.384848 # average overall miss latency 2466system.iocache.blocked_cycles::no_mshrs 36149 # number of cycles access was blocked 2467system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2468system.iocache.blocked::no_mshrs 3721 # number of cycles access was blocked 2469system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2470system.iocache.avg_blocked_cycles::no_mshrs 9.714862 # average number of cycles each access was blocked 2471system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2472system.iocache.fast_writes 0 # number of fast writes performed 2473system.iocache.cache_copies 0 # number of cache copies performed 2474system.iocache.writebacks::writebacks 106948 # number of writebacks 2475system.iocache.writebacks::total 106948 # number of writebacks 2476system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2477system.iocache.ReadReq_mshr_misses::realview.ide 8896 # number of ReadReq MSHR misses 2478system.iocache.ReadReq_mshr_misses::total 8933 # number of ReadReq MSHR misses 2479system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2480system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2481system.iocache.WriteLineReq_mshr_misses::realview.ide 106982 # number of WriteLineReq MSHR misses 2482system.iocache.WriteLineReq_mshr_misses::total 106982 # number of WriteLineReq MSHR misses 2483system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2484system.iocache.demand_mshr_misses::realview.ide 8896 # number of demand (read+write) MSHR misses 2485system.iocache.demand_mshr_misses::total 8936 # number of demand (read+write) MSHR misses 2486system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2487system.iocache.overall_mshr_misses::realview.ide 8896 # number of overall MSHR misses 2488system.iocache.overall_mshr_misses::total 8936 # number of overall MSHR misses 2489system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3411000 # number of ReadReq MSHR miss cycles 2490system.iocache.ReadReq_mshr_miss_latency::realview.ide 1255294991 # number of ReadReq MSHR miss cycles 2491system.iocache.ReadReq_mshr_miss_latency::total 1258705991 # number of ReadReq MSHR miss cycles 2492system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2493system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2494system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8664328406 # number of WriteLineReq MSHR miss cycles 2495system.iocache.WriteLineReq_mshr_miss_latency::total 8664328406 # number of WriteLineReq MSHR miss cycles 2496system.iocache.demand_mshr_miss_latency::realview.ethernet 3630000 # number of demand (read+write) MSHR miss cycles 2497system.iocache.demand_mshr_miss_latency::realview.ide 1255294991 # number of demand (read+write) MSHR miss cycles 2498system.iocache.demand_mshr_miss_latency::total 1258924991 # number of demand (read+write) MSHR miss cycles 2499system.iocache.overall_mshr_miss_latency::realview.ethernet 3630000 # number of overall MSHR miss cycles 2500system.iocache.overall_mshr_miss_latency::realview.ide 1255294991 # number of overall MSHR miss cycles 2501system.iocache.overall_mshr_miss_latency::total 1258924991 # number of overall MSHR miss cycles 2502system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2503system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2504system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2505system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2506system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2507system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999981 # mshr miss rate for WriteLineReq accesses 2508system.iocache.WriteLineReq_mshr_miss_rate::total 0.999981 # mshr miss rate for WriteLineReq accesses 2509system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2510system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2511system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2512system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2513system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2514system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2515system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92189.189189 # average ReadReq mshr miss latency 2516system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141107.800247 # average ReadReq mshr miss latency 2517system.iocache.ReadReq_avg_mshr_miss_latency::total 140905.182022 # average ReadReq mshr miss latency 2518system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2519system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2520system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80988.656092 # average WriteLineReq mshr miss latency 2521system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80988.656092 # average WriteLineReq mshr miss latency 2522system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency 2523system.iocache.demand_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency 2524system.iocache.demand_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency 2525system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90750 # average overall mshr miss latency 2526system.iocache.overall_avg_mshr_miss_latency::realview.ide 141107.800247 # average overall mshr miss latency 2527system.iocache.overall_avg_mshr_miss_latency::total 140882.384848 # average overall mshr miss latency 2528system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2529system.l2c.tags.replacements 1047057 # number of replacements 2530system.l2c.tags.tagsinuse 63052.180525 # Cycle average of tags in use 2531system.l2c.tags.total_refs 6067910 # Total number of references to valid blocks. 2532system.l2c.tags.sampled_refs 1106756 # Sample count of references to valid blocks. 2533system.l2c.tags.avg_refs 5.482609 # Average number of references to valid blocks. 2534system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2535system.l2c.tags.occ_blocks::writebacks 25661.598067 # Average occupied blocks per requestor 2536system.l2c.tags.occ_blocks::cpu0.dtb.walker 59.549817 # Average occupied blocks per requestor 2537system.l2c.tags.occ_blocks::cpu0.itb.walker 63.820457 # Average occupied blocks per requestor 2538system.l2c.tags.occ_blocks::cpu0.inst 6721.957431 # Average occupied blocks per requestor 2539system.l2c.tags.occ_blocks::cpu0.data 5596.771487 # Average occupied blocks per requestor 2540system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5304.396230 # Average occupied blocks per requestor 2541system.l2c.tags.occ_blocks::cpu1.dtb.walker 138.527549 # Average occupied blocks per requestor 2542system.l2c.tags.occ_blocks::cpu1.itb.walker 206.635310 # Average occupied blocks per requestor 2543system.l2c.tags.occ_blocks::cpu1.inst 5419.027786 # Average occupied blocks per requestor 2544system.l2c.tags.occ_blocks::cpu1.data 6651.679849 # Average occupied blocks per requestor 2545system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7228.216543 # Average occupied blocks per requestor 2546system.l2c.tags.occ_percent::writebacks 0.391565 # Average percentage of cache occupancy 2547system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000909 # Average percentage of cache occupancy 2548system.l2c.tags.occ_percent::cpu0.itb.walker 0.000974 # Average percentage of cache occupancy 2549system.l2c.tags.occ_percent::cpu0.inst 0.102569 # Average percentage of cache occupancy 2550system.l2c.tags.occ_percent::cpu0.data 0.085400 # Average percentage of cache occupancy 2551system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.080939 # Average percentage of cache occupancy 2552system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002114 # Average percentage of cache occupancy 2553system.l2c.tags.occ_percent::cpu1.itb.walker 0.003153 # Average percentage of cache occupancy 2554system.l2c.tags.occ_percent::cpu1.inst 0.082688 # Average percentage of cache occupancy 2555system.l2c.tags.occ_percent::cpu1.data 0.101497 # Average percentage of cache occupancy 2556system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.110294 # Average percentage of cache occupancy 2557system.l2c.tags.occ_percent::total 0.962100 # Average percentage of cache occupancy 2558system.l2c.tags.occ_task_id_blocks::1022 9310 # Occupied blocks per task id 2559system.l2c.tags.occ_task_id_blocks::1023 176 # Occupied blocks per task id 2560system.l2c.tags.occ_task_id_blocks::1024 50213 # Occupied blocks per task id 2561system.l2c.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id 2562system.l2c.tags.age_task_id_blocks_1022::1 427 # Occupied blocks per task id 2563system.l2c.tags.age_task_id_blocks_1022::2 684 # Occupied blocks per task id 2564system.l2c.tags.age_task_id_blocks_1022::3 1579 # Occupied blocks per task id 2565system.l2c.tags.age_task_id_blocks_1022::4 6559 # Occupied blocks per task id 2566system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 2567system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 2568system.l2c.tags.age_task_id_blocks_1023::4 158 # Occupied blocks per task id 2569system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 2570system.l2c.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 2571system.l2c.tags.age_task_id_blocks_1024::2 2614 # Occupied blocks per task id 2572system.l2c.tags.age_task_id_blocks_1024::3 11152 # Occupied blocks per task id 2573system.l2c.tags.age_task_id_blocks_1024::4 36045 # Occupied blocks per task id 2574system.l2c.tags.occ_task_id_percent::1022 0.142059 # Percentage of cache occupancy per task id 2575system.l2c.tags.occ_task_id_percent::1023 0.002686 # Percentage of cache occupancy per task id 2576system.l2c.tags.occ_task_id_percent::1024 0.766190 # Percentage of cache occupancy per task id 2577system.l2c.tags.tag_accesses 72230268 # Number of tag accesses 2578system.l2c.tags.data_accesses 72230268 # Number of data accesses 2579system.l2c.WritebackDirty_hits::writebacks 2478146 # number of WritebackDirty hits 2580system.l2c.WritebackDirty_hits::total 2478146 # number of WritebackDirty hits 2581system.l2c.UpgradeReq_hits::cpu0.data 154381 # number of UpgradeReq hits 2582system.l2c.UpgradeReq_hits::cpu1.data 128604 # number of UpgradeReq hits 2583system.l2c.UpgradeReq_hits::total 282985 # number of UpgradeReq hits 2584system.l2c.SCUpgradeReq_hits::cpu0.data 37860 # number of SCUpgradeReq hits 2585system.l2c.SCUpgradeReq_hits::cpu1.data 40612 # number of SCUpgradeReq hits 2586system.l2c.SCUpgradeReq_hits::total 78472 # number of SCUpgradeReq hits 2587system.l2c.ReadExReq_hits::cpu0.data 167086 # number of ReadExReq hits 2588system.l2c.ReadExReq_hits::cpu1.data 187378 # number of ReadExReq hits 2589system.l2c.ReadExReq_hits::total 354464 # number of ReadExReq hits 2590system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5729 # number of ReadSharedReq hits 2591system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3917 # number of ReadSharedReq hits 2592system.l2c.ReadSharedReq_hits::cpu0.inst 604815 # number of ReadSharedReq hits 2593system.l2c.ReadSharedReq_hits::cpu0.data 555526 # number of ReadSharedReq hits 2594system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 312245 # number of ReadSharedReq hits 2595system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6550 # number of ReadSharedReq hits 2596system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4876 # number of ReadSharedReq hits 2597system.l2c.ReadSharedReq_hits::cpu1.inst 643471 # number of ReadSharedReq hits 2598system.l2c.ReadSharedReq_hits::cpu1.data 544206 # number of ReadSharedReq hits 2599system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 332267 # number of ReadSharedReq hits 2600system.l2c.ReadSharedReq_hits::total 3013602 # number of ReadSharedReq hits 2601system.l2c.demand_hits::cpu0.dtb.walker 5729 # number of demand (read+write) hits 2602system.l2c.demand_hits::cpu0.itb.walker 3917 # number of demand (read+write) hits 2603system.l2c.demand_hits::cpu0.inst 604815 # number of demand (read+write) hits 2604system.l2c.demand_hits::cpu0.data 722612 # number of demand (read+write) hits 2605system.l2c.demand_hits::cpu0.l2cache.prefetcher 312245 # number of demand (read+write) hits 2606system.l2c.demand_hits::cpu1.dtb.walker 6550 # number of demand (read+write) hits 2607system.l2c.demand_hits::cpu1.itb.walker 4876 # number of demand (read+write) hits 2608system.l2c.demand_hits::cpu1.inst 643471 # number of demand (read+write) hits 2609system.l2c.demand_hits::cpu1.data 731584 # number of demand (read+write) hits 2610system.l2c.demand_hits::cpu1.l2cache.prefetcher 332267 # number of demand (read+write) hits 2611system.l2c.demand_hits::total 3368066 # number of demand (read+write) hits 2612system.l2c.overall_hits::cpu0.dtb.walker 5729 # number of overall hits 2613system.l2c.overall_hits::cpu0.itb.walker 3917 # number of overall hits 2614system.l2c.overall_hits::cpu0.inst 604815 # number of overall hits 2615system.l2c.overall_hits::cpu0.data 722612 # number of overall hits 2616system.l2c.overall_hits::cpu0.l2cache.prefetcher 312245 # number of overall hits 2617system.l2c.overall_hits::cpu1.dtb.walker 6550 # number of overall hits 2618system.l2c.overall_hits::cpu1.itb.walker 4876 # number of overall hits 2619system.l2c.overall_hits::cpu1.inst 643471 # number of overall hits 2620system.l2c.overall_hits::cpu1.data 731584 # number of overall hits 2621system.l2c.overall_hits::cpu1.l2cache.prefetcher 332267 # number of overall hits 2622system.l2c.overall_hits::total 3368066 # number of overall hits 2623system.l2c.UpgradeReq_misses::cpu0.data 61102 # number of UpgradeReq misses 2624system.l2c.UpgradeReq_misses::cpu1.data 58240 # number of UpgradeReq misses 2625system.l2c.UpgradeReq_misses::total 119342 # number of UpgradeReq misses 2626system.l2c.SCUpgradeReq_misses::cpu0.data 10859 # number of SCUpgradeReq misses 2627system.l2c.SCUpgradeReq_misses::cpu1.data 11400 # number of SCUpgradeReq misses 2628system.l2c.SCUpgradeReq_misses::total 22259 # number of SCUpgradeReq misses 2629system.l2c.ReadExReq_misses::cpu0.data 464077 # number of ReadExReq misses 2630system.l2c.ReadExReq_misses::cpu1.data 119615 # number of ReadExReq misses 2631system.l2c.ReadExReq_misses::total 583692 # number of ReadExReq misses 2632system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 662 # number of ReadSharedReq misses 2633system.l2c.ReadSharedReq_misses::cpu0.itb.walker 653 # number of ReadSharedReq misses 2634system.l2c.ReadSharedReq_misses::cpu0.inst 56835 # number of ReadSharedReq misses 2635system.l2c.ReadSharedReq_misses::cpu0.data 93190 # number of ReadSharedReq misses 2636system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 142344 # number of ReadSharedReq misses 2637system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 930 # number of ReadSharedReq misses 2638system.l2c.ReadSharedReq_misses::cpu1.itb.walker 967 # number of ReadSharedReq misses 2639system.l2c.ReadSharedReq_misses::cpu1.inst 47805 # number of ReadSharedReq misses 2640system.l2c.ReadSharedReq_misses::cpu1.data 79816 # number of ReadSharedReq misses 2641system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 118522 # number of ReadSharedReq misses 2642system.l2c.ReadSharedReq_misses::total 541724 # number of ReadSharedReq misses 2643system.l2c.demand_misses::cpu0.dtb.walker 662 # number of demand (read+write) misses 2644system.l2c.demand_misses::cpu0.itb.walker 653 # number of demand (read+write) misses 2645system.l2c.demand_misses::cpu0.inst 56835 # number of demand (read+write) misses 2646system.l2c.demand_misses::cpu0.data 557267 # number of demand (read+write) misses 2647system.l2c.demand_misses::cpu0.l2cache.prefetcher 142344 # number of demand (read+write) misses 2648system.l2c.demand_misses::cpu1.dtb.walker 930 # number of demand (read+write) misses 2649system.l2c.demand_misses::cpu1.itb.walker 967 # number of demand (read+write) misses 2650system.l2c.demand_misses::cpu1.inst 47805 # number of demand (read+write) misses 2651system.l2c.demand_misses::cpu1.data 199431 # number of demand (read+write) misses 2652system.l2c.demand_misses::cpu1.l2cache.prefetcher 118522 # number of demand (read+write) misses 2653system.l2c.demand_misses::total 1125416 # number of demand (read+write) misses 2654system.l2c.overall_misses::cpu0.dtb.walker 662 # number of overall misses 2655system.l2c.overall_misses::cpu0.itb.walker 653 # number of overall misses 2656system.l2c.overall_misses::cpu0.inst 56835 # number of overall misses 2657system.l2c.overall_misses::cpu0.data 557267 # number of overall misses 2658system.l2c.overall_misses::cpu0.l2cache.prefetcher 142344 # number of overall misses 2659system.l2c.overall_misses::cpu1.dtb.walker 930 # number of overall misses 2660system.l2c.overall_misses::cpu1.itb.walker 967 # number of overall misses 2661system.l2c.overall_misses::cpu1.inst 47805 # number of overall misses 2662system.l2c.overall_misses::cpu1.data 199431 # number of overall misses 2663system.l2c.overall_misses::cpu1.l2cache.prefetcher 118522 # number of overall misses 2664system.l2c.overall_misses::total 1125416 # number of overall misses 2665system.l2c.UpgradeReq_miss_latency::cpu0.data 1103543500 # number of UpgradeReq miss cycles 2666system.l2c.UpgradeReq_miss_latency::cpu1.data 1130362500 # number of UpgradeReq miss cycles 2667system.l2c.UpgradeReq_miss_latency::total 2233906000 # number of UpgradeReq miss cycles 2668system.l2c.SCUpgradeReq_miss_latency::cpu0.data 187676500 # number of SCUpgradeReq miss cycles 2669system.l2c.SCUpgradeReq_miss_latency::cpu1.data 195172500 # number of SCUpgradeReq miss cycles 2670system.l2c.SCUpgradeReq_miss_latency::total 382849000 # number of SCUpgradeReq miss cycles 2671system.l2c.ReadExReq_miss_latency::cpu0.data 64543141999 # number of ReadExReq miss cycles 2672system.l2c.ReadExReq_miss_latency::cpu1.data 16037903000 # number of ReadExReq miss cycles 2673system.l2c.ReadExReq_miss_latency::total 80581044999 # number of ReadExReq miss cycles 2674system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 90596000 # number of ReadSharedReq miss cycles 2675system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90566500 # number of ReadSharedReq miss cycles 2676system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7555639500 # number of ReadSharedReq miss cycles 2677system.l2c.ReadSharedReq_miss_latency::cpu0.data 12682874000 # number of ReadSharedReq miss cycles 2678system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 22835971280 # number of ReadSharedReq miss cycles 2679system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 127343000 # number of ReadSharedReq miss cycles 2680system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132126000 # number of ReadSharedReq miss cycles 2681system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6369869500 # number of ReadSharedReq miss cycles 2682system.l2c.ReadSharedReq_miss_latency::cpu1.data 10891833000 # number of ReadSharedReq miss cycles 2683system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 18778961423 # number of ReadSharedReq miss cycles 2684system.l2c.ReadSharedReq_miss_latency::total 79555780203 # number of ReadSharedReq miss cycles 2685system.l2c.demand_miss_latency::cpu0.dtb.walker 90596000 # number of demand (read+write) miss cycles 2686system.l2c.demand_miss_latency::cpu0.itb.walker 90566500 # number of demand (read+write) miss cycles 2687system.l2c.demand_miss_latency::cpu0.inst 7555639500 # number of demand (read+write) miss cycles 2688system.l2c.demand_miss_latency::cpu0.data 77226015999 # number of demand (read+write) miss cycles 2689system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 22835971280 # number of demand (read+write) miss cycles 2690system.l2c.demand_miss_latency::cpu1.dtb.walker 127343000 # number of demand (read+write) miss cycles 2691system.l2c.demand_miss_latency::cpu1.itb.walker 132126000 # number of demand (read+write) miss cycles 2692system.l2c.demand_miss_latency::cpu1.inst 6369869500 # number of demand (read+write) miss cycles 2693system.l2c.demand_miss_latency::cpu1.data 26929736000 # number of demand (read+write) miss cycles 2694system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 18778961423 # number of demand (read+write) miss cycles 2695system.l2c.demand_miss_latency::total 160136825202 # number of demand (read+write) miss cycles 2696system.l2c.overall_miss_latency::cpu0.dtb.walker 90596000 # number of overall miss cycles 2697system.l2c.overall_miss_latency::cpu0.itb.walker 90566500 # number of overall miss cycles 2698system.l2c.overall_miss_latency::cpu0.inst 7555639500 # number of overall miss cycles 2699system.l2c.overall_miss_latency::cpu0.data 77226015999 # number of overall miss cycles 2700system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 22835971280 # number of overall miss cycles 2701system.l2c.overall_miss_latency::cpu1.dtb.walker 127343000 # number of overall miss cycles 2702system.l2c.overall_miss_latency::cpu1.itb.walker 132126000 # number of overall miss cycles 2703system.l2c.overall_miss_latency::cpu1.inst 6369869500 # number of overall miss cycles 2704system.l2c.overall_miss_latency::cpu1.data 26929736000 # number of overall miss cycles 2705system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 18778961423 # number of overall miss cycles 2706system.l2c.overall_miss_latency::total 160136825202 # number of overall miss cycles 2707system.l2c.WritebackDirty_accesses::writebacks 2478146 # number of WritebackDirty accesses(hits+misses) 2708system.l2c.WritebackDirty_accesses::total 2478146 # number of WritebackDirty accesses(hits+misses) 2709system.l2c.UpgradeReq_accesses::cpu0.data 215483 # number of UpgradeReq accesses(hits+misses) 2710system.l2c.UpgradeReq_accesses::cpu1.data 186844 # number of UpgradeReq accesses(hits+misses) 2711system.l2c.UpgradeReq_accesses::total 402327 # number of UpgradeReq accesses(hits+misses) 2712system.l2c.SCUpgradeReq_accesses::cpu0.data 48719 # number of SCUpgradeReq accesses(hits+misses) 2713system.l2c.SCUpgradeReq_accesses::cpu1.data 52012 # number of SCUpgradeReq accesses(hits+misses) 2714system.l2c.SCUpgradeReq_accesses::total 100731 # number of SCUpgradeReq accesses(hits+misses) 2715system.l2c.ReadExReq_accesses::cpu0.data 631163 # number of ReadExReq accesses(hits+misses) 2716system.l2c.ReadExReq_accesses::cpu1.data 306993 # number of ReadExReq accesses(hits+misses) 2717system.l2c.ReadExReq_accesses::total 938156 # number of ReadExReq accesses(hits+misses) 2718system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6391 # number of ReadSharedReq accesses(hits+misses) 2719system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4570 # number of ReadSharedReq accesses(hits+misses) 2720system.l2c.ReadSharedReq_accesses::cpu0.inst 661650 # number of ReadSharedReq accesses(hits+misses) 2721system.l2c.ReadSharedReq_accesses::cpu0.data 648716 # number of ReadSharedReq accesses(hits+misses) 2722system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 454589 # number of ReadSharedReq accesses(hits+misses) 2723system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7480 # number of ReadSharedReq accesses(hits+misses) 2724system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5843 # number of ReadSharedReq accesses(hits+misses) 2725system.l2c.ReadSharedReq_accesses::cpu1.inst 691276 # number of ReadSharedReq accesses(hits+misses) 2726system.l2c.ReadSharedReq_accesses::cpu1.data 624022 # number of ReadSharedReq accesses(hits+misses) 2727system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 450789 # number of ReadSharedReq accesses(hits+misses) 2728system.l2c.ReadSharedReq_accesses::total 3555326 # number of ReadSharedReq accesses(hits+misses) 2729system.l2c.demand_accesses::cpu0.dtb.walker 6391 # number of demand (read+write) accesses 2730system.l2c.demand_accesses::cpu0.itb.walker 4570 # number of demand (read+write) accesses 2731system.l2c.demand_accesses::cpu0.inst 661650 # number of demand (read+write) accesses 2732system.l2c.demand_accesses::cpu0.data 1279879 # number of demand (read+write) accesses 2733system.l2c.demand_accesses::cpu0.l2cache.prefetcher 454589 # number of demand (read+write) accesses 2734system.l2c.demand_accesses::cpu1.dtb.walker 7480 # number of demand (read+write) accesses 2735system.l2c.demand_accesses::cpu1.itb.walker 5843 # number of demand (read+write) accesses 2736system.l2c.demand_accesses::cpu1.inst 691276 # number of demand (read+write) accesses 2737system.l2c.demand_accesses::cpu1.data 931015 # number of demand (read+write) accesses 2738system.l2c.demand_accesses::cpu1.l2cache.prefetcher 450789 # number of demand (read+write) accesses 2739system.l2c.demand_accesses::total 4493482 # number of demand (read+write) accesses 2740system.l2c.overall_accesses::cpu0.dtb.walker 6391 # number of overall (read+write) accesses 2741system.l2c.overall_accesses::cpu0.itb.walker 4570 # number of overall (read+write) accesses 2742system.l2c.overall_accesses::cpu0.inst 661650 # number of overall (read+write) accesses 2743system.l2c.overall_accesses::cpu0.data 1279879 # number of overall (read+write) accesses 2744system.l2c.overall_accesses::cpu0.l2cache.prefetcher 454589 # number of overall (read+write) accesses 2745system.l2c.overall_accesses::cpu1.dtb.walker 7480 # number of overall (read+write) accesses 2746system.l2c.overall_accesses::cpu1.itb.walker 5843 # number of overall (read+write) accesses 2747system.l2c.overall_accesses::cpu1.inst 691276 # number of overall (read+write) accesses 2748system.l2c.overall_accesses::cpu1.data 931015 # number of overall (read+write) accesses 2749system.l2c.overall_accesses::cpu1.l2cache.prefetcher 450789 # number of overall (read+write) accesses 2750system.l2c.overall_accesses::total 4493482 # number of overall (read+write) accesses 2751system.l2c.UpgradeReq_miss_rate::cpu0.data 0.283558 # miss rate for UpgradeReq accesses 2752system.l2c.UpgradeReq_miss_rate::cpu1.data 0.311704 # miss rate for UpgradeReq accesses 2753system.l2c.UpgradeReq_miss_rate::total 0.296629 # miss rate for UpgradeReq accesses 2754system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.222890 # miss rate for SCUpgradeReq accesses 2755system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.219180 # miss rate for SCUpgradeReq accesses 2756system.l2c.SCUpgradeReq_miss_rate::total 0.220975 # miss rate for SCUpgradeReq accesses 2757system.l2c.ReadExReq_miss_rate::cpu0.data 0.735273 # miss rate for ReadExReq accesses 2758system.l2c.ReadExReq_miss_rate::cpu1.data 0.389634 # miss rate for ReadExReq accesses 2759system.l2c.ReadExReq_miss_rate::total 0.622169 # miss rate for ReadExReq accesses 2760system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.103583 # miss rate for ReadSharedReq accesses 2761system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.142888 # miss rate for ReadSharedReq accesses 2762system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.085899 # miss rate for ReadSharedReq accesses 2763system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.143653 # miss rate for ReadSharedReq accesses 2764system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.313127 # miss rate for ReadSharedReq accesses 2765system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.124332 # miss rate for ReadSharedReq accesses 2766system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.165497 # miss rate for ReadSharedReq accesses 2767system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.069155 # miss rate for ReadSharedReq accesses 2768system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.127906 # miss rate for ReadSharedReq accesses 2769system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.262921 # miss rate for ReadSharedReq accesses 2770system.l2c.ReadSharedReq_miss_rate::total 0.152370 # miss rate for ReadSharedReq accesses 2771system.l2c.demand_miss_rate::cpu0.dtb.walker 0.103583 # miss rate for demand accesses 2772system.l2c.demand_miss_rate::cpu0.itb.walker 0.142888 # miss rate for demand accesses 2773system.l2c.demand_miss_rate::cpu0.inst 0.085899 # miss rate for demand accesses 2774system.l2c.demand_miss_rate::cpu0.data 0.435406 # miss rate for demand accesses 2775system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.313127 # miss rate for demand accesses 2776system.l2c.demand_miss_rate::cpu1.dtb.walker 0.124332 # miss rate for demand accesses 2777system.l2c.demand_miss_rate::cpu1.itb.walker 0.165497 # miss rate for demand accesses 2778system.l2c.demand_miss_rate::cpu1.inst 0.069155 # miss rate for demand accesses 2779system.l2c.demand_miss_rate::cpu1.data 0.214208 # miss rate for demand accesses 2780system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.262921 # miss rate for demand accesses 2781system.l2c.demand_miss_rate::total 0.250455 # miss rate for demand accesses 2782system.l2c.overall_miss_rate::cpu0.dtb.walker 0.103583 # miss rate for overall accesses 2783system.l2c.overall_miss_rate::cpu0.itb.walker 0.142888 # miss rate for overall accesses 2784system.l2c.overall_miss_rate::cpu0.inst 0.085899 # miss rate for overall accesses 2785system.l2c.overall_miss_rate::cpu0.data 0.435406 # miss rate for overall accesses 2786system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.313127 # miss rate for overall accesses 2787system.l2c.overall_miss_rate::cpu1.dtb.walker 0.124332 # miss rate for overall accesses 2788system.l2c.overall_miss_rate::cpu1.itb.walker 0.165497 # miss rate for overall accesses 2789system.l2c.overall_miss_rate::cpu1.inst 0.069155 # miss rate for overall accesses 2790system.l2c.overall_miss_rate::cpu1.data 0.214208 # miss rate for overall accesses 2791system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.262921 # miss rate for overall accesses 2792system.l2c.overall_miss_rate::total 0.250455 # miss rate for overall accesses 2793system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18060.677228 # average UpgradeReq miss latency 2794system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19408.696772 # average UpgradeReq miss latency 2795system.l2c.UpgradeReq_avg_miss_latency::total 18718.523236 # average UpgradeReq miss latency 2796system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17283.037112 # average SCUpgradeReq miss latency 2797system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17120.394737 # average SCUpgradeReq miss latency 2798system.l2c.SCUpgradeReq_avg_miss_latency::total 17199.739431 # average SCUpgradeReq miss latency 2799system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139078.519295 # average ReadExReq miss latency 2800system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134079.362956 # average ReadExReq miss latency 2801system.l2c.ReadExReq_avg_miss_latency::total 138054.050765 # average ReadExReq miss latency 2802system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136851.963746 # average ReadSharedReq miss latency 2803system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138692.955590 # average ReadSharedReq miss latency 2804system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132939.904988 # average ReadSharedReq miss latency 2805system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136096.941732 # average ReadSharedReq miss latency 2806system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539 # average ReadSharedReq miss latency 2807system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136927.956989 # average ReadSharedReq miss latency 2808system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 136634.953464 # average ReadSharedReq miss latency 2809system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133246.930237 # average ReadSharedReq miss latency 2810system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 136461.774582 # average ReadSharedReq miss latency 2811system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748 # average ReadSharedReq miss latency 2812system.l2c.ReadSharedReq_avg_miss_latency::total 146856.665392 # average ReadSharedReq miss latency 2813system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136851.963746 # average overall miss latency 2814system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138692.955590 # average overall miss latency 2815system.l2c.demand_avg_miss_latency::cpu0.inst 132939.904988 # average overall miss latency 2816system.l2c.demand_avg_miss_latency::cpu0.data 138579.919498 # average overall miss latency 2817system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539 # average overall miss latency 2818system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136927.956989 # average overall miss latency 2819system.l2c.demand_avg_miss_latency::cpu1.itb.walker 136634.953464 # average overall miss latency 2820system.l2c.demand_avg_miss_latency::cpu1.inst 133246.930237 # average overall miss latency 2821system.l2c.demand_avg_miss_latency::cpu1.data 135032.848454 # average overall miss latency 2822system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748 # average overall miss latency 2823system.l2c.demand_avg_miss_latency::total 142291.228490 # average overall miss latency 2824system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136851.963746 # average overall miss latency 2825system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138692.955590 # average overall miss latency 2826system.l2c.overall_avg_miss_latency::cpu0.inst 132939.904988 # average overall miss latency 2827system.l2c.overall_avg_miss_latency::cpu0.data 138579.919498 # average overall miss latency 2828system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539 # average overall miss latency 2829system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136927.956989 # average overall miss latency 2830system.l2c.overall_avg_miss_latency::cpu1.itb.walker 136634.953464 # average overall miss latency 2831system.l2c.overall_avg_miss_latency::cpu1.inst 133246.930237 # average overall miss latency 2832system.l2c.overall_avg_miss_latency::cpu1.data 135032.848454 # average overall miss latency 2833system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748 # average overall miss latency 2834system.l2c.overall_avg_miss_latency::total 142291.228490 # average overall miss latency 2835system.l2c.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked 2836system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2837system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 2838system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2839system.l2c.avg_blocked_cycles::no_mshrs 129.500000 # average number of cycles each access was blocked 2840system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2841system.l2c.fast_writes 0 # number of fast writes performed 2842system.l2c.cache_copies 0 # number of cache copies performed 2843system.l2c.writebacks::writebacks 823102 # number of writebacks 2844system.l2c.writebacks::total 823102 # number of writebacks 2845system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 112 # number of ReadSharedReq MSHR hits 2846system.l2c.ReadSharedReq_mshr_hits::cpu0.data 15 # number of ReadSharedReq MSHR hits 2847system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 123 # number of ReadSharedReq MSHR hits 2848system.l2c.ReadSharedReq_mshr_hits::cpu1.data 13 # number of ReadSharedReq MSHR hits 2849system.l2c.ReadSharedReq_mshr_hits::total 263 # number of ReadSharedReq MSHR hits 2850system.l2c.demand_mshr_hits::cpu0.inst 112 # number of demand (read+write) MSHR hits 2851system.l2c.demand_mshr_hits::cpu0.data 15 # number of demand (read+write) MSHR hits 2852system.l2c.demand_mshr_hits::cpu1.inst 123 # number of demand (read+write) MSHR hits 2853system.l2c.demand_mshr_hits::cpu1.data 13 # number of demand (read+write) MSHR hits 2854system.l2c.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits 2855system.l2c.overall_mshr_hits::cpu0.inst 112 # number of overall MSHR hits 2856system.l2c.overall_mshr_hits::cpu0.data 15 # number of overall MSHR hits 2857system.l2c.overall_mshr_hits::cpu1.inst 123 # number of overall MSHR hits 2858system.l2c.overall_mshr_hits::cpu1.data 13 # number of overall MSHR hits 2859system.l2c.overall_mshr_hits::total 263 # number of overall MSHR hits 2860system.l2c.CleanEvict_mshr_misses::writebacks 35269 # number of CleanEvict MSHR misses 2861system.l2c.CleanEvict_mshr_misses::total 35269 # number of CleanEvict MSHR misses 2862system.l2c.UpgradeReq_mshr_misses::cpu0.data 61102 # number of UpgradeReq MSHR misses 2863system.l2c.UpgradeReq_mshr_misses::cpu1.data 58240 # number of UpgradeReq MSHR misses 2864system.l2c.UpgradeReq_mshr_misses::total 119342 # number of UpgradeReq MSHR misses 2865system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10859 # number of SCUpgradeReq MSHR misses 2866system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11400 # number of SCUpgradeReq MSHR misses 2867system.l2c.SCUpgradeReq_mshr_misses::total 22259 # number of SCUpgradeReq MSHR misses 2868system.l2c.ReadExReq_mshr_misses::cpu0.data 464077 # number of ReadExReq MSHR misses 2869system.l2c.ReadExReq_mshr_misses::cpu1.data 119615 # number of ReadExReq MSHR misses 2870system.l2c.ReadExReq_mshr_misses::total 583692 # number of ReadExReq MSHR misses 2871system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 662 # number of ReadSharedReq MSHR misses 2872system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 653 # number of ReadSharedReq MSHR misses 2873system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 56723 # number of ReadSharedReq MSHR misses 2874system.l2c.ReadSharedReq_mshr_misses::cpu0.data 93175 # number of ReadSharedReq MSHR misses 2875system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 142344 # number of ReadSharedReq MSHR misses 2876system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 930 # number of ReadSharedReq MSHR misses 2877system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 967 # number of ReadSharedReq MSHR misses 2878system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 47682 # number of ReadSharedReq MSHR misses 2879system.l2c.ReadSharedReq_mshr_misses::cpu1.data 79803 # number of ReadSharedReq MSHR misses 2880system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 118522 # number of ReadSharedReq MSHR misses 2881system.l2c.ReadSharedReq_mshr_misses::total 541461 # number of ReadSharedReq MSHR misses 2882system.l2c.demand_mshr_misses::cpu0.dtb.walker 662 # number of demand (read+write) MSHR misses 2883system.l2c.demand_mshr_misses::cpu0.itb.walker 653 # number of demand (read+write) MSHR misses 2884system.l2c.demand_mshr_misses::cpu0.inst 56723 # number of demand (read+write) MSHR misses 2885system.l2c.demand_mshr_misses::cpu0.data 557252 # number of demand (read+write) MSHR misses 2886system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 142344 # number of demand (read+write) MSHR misses 2887system.l2c.demand_mshr_misses::cpu1.dtb.walker 930 # number of demand (read+write) MSHR misses 2888system.l2c.demand_mshr_misses::cpu1.itb.walker 967 # number of demand (read+write) MSHR misses 2889system.l2c.demand_mshr_misses::cpu1.inst 47682 # number of demand (read+write) MSHR misses 2890system.l2c.demand_mshr_misses::cpu1.data 199418 # number of demand (read+write) MSHR misses 2891system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 118522 # number of demand (read+write) MSHR misses 2892system.l2c.demand_mshr_misses::total 1125153 # number of demand (read+write) MSHR misses 2893system.l2c.overall_mshr_misses::cpu0.dtb.walker 662 # number of overall MSHR misses 2894system.l2c.overall_mshr_misses::cpu0.itb.walker 653 # number of overall MSHR misses 2895system.l2c.overall_mshr_misses::cpu0.inst 56723 # number of overall MSHR misses 2896system.l2c.overall_mshr_misses::cpu0.data 557252 # number of overall MSHR misses 2897system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 142344 # number of overall MSHR misses 2898system.l2c.overall_mshr_misses::cpu1.dtb.walker 930 # number of overall MSHR misses 2899system.l2c.overall_mshr_misses::cpu1.itb.walker 967 # number of overall MSHR misses 2900system.l2c.overall_mshr_misses::cpu1.inst 47682 # number of overall MSHR misses 2901system.l2c.overall_mshr_misses::cpu1.data 199418 # number of overall MSHR misses 2902system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 118522 # number of overall MSHR misses 2903system.l2c.overall_mshr_misses::total 1125153 # number of overall MSHR misses 2904system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 2905system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable 2906system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2907system.l2c.ReadReq_mshr_uncacheable::cpu1.data 20900 # number of ReadReq MSHR uncacheable 2908system.l2c.ReadReq_mshr_uncacheable::total 90049 # number of ReadReq MSHR uncacheable 2909system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable 2910system.l2c.WriteReq_mshr_uncacheable::cpu1.data 19312 # number of WriteReq MSHR uncacheable 2911system.l2c.WriteReq_mshr_uncacheable::total 37563 # number of WriteReq MSHR uncacheable 2912system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 2913system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses 2914system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2915system.l2c.overall_mshr_uncacheable_misses::cpu1.data 40212 # number of overall MSHR uncacheable misses 2916system.l2c.overall_mshr_uncacheable_misses::total 127612 # number of overall MSHR uncacheable misses 2917system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4485198505 # number of UpgradeReq MSHR miss cycles 2918system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4277577003 # number of UpgradeReq MSHR miss cycles 2919system.l2c.UpgradeReq_mshr_miss_latency::total 8762775508 # number of UpgradeReq MSHR miss cycles 2920system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 830961500 # number of SCUpgradeReq MSHR miss cycles 2921system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 871854000 # number of SCUpgradeReq MSHR miss cycles 2922system.l2c.SCUpgradeReq_mshr_miss_latency::total 1702815500 # number of SCUpgradeReq MSHR miss cycles 2923system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 59902371999 # number of ReadExReq MSHR miss cycles 2924system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 14841753000 # number of ReadExReq MSHR miss cycles 2925system.l2c.ReadExReq_mshr_miss_latency::total 74744124999 # number of ReadExReq MSHR miss cycles 2926system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 83976000 # number of ReadSharedReq MSHR miss cycles 2927system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 84036500 # number of ReadSharedReq MSHR miss cycles 2928system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6976120000 # number of ReadSharedReq MSHR miss cycles 2929system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11749122500 # number of ReadSharedReq MSHR miss cycles 2930system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21412531280 # number of ReadSharedReq MSHR miss cycles 2931system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 118043000 # number of ReadSharedReq MSHR miss cycles 2932system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 122456000 # number of ReadSharedReq MSHR miss cycles 2933system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5880117000 # number of ReadSharedReq MSHR miss cycles 2934system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10092485500 # number of ReadSharedReq MSHR miss cycles 2935system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17593741423 # number of ReadSharedReq MSHR miss cycles 2936system.l2c.ReadSharedReq_mshr_miss_latency::total 74112629203 # number of ReadSharedReq MSHR miss cycles 2937system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 83976000 # number of demand (read+write) MSHR miss cycles 2938system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 84036500 # number of demand (read+write) MSHR miss cycles 2939system.l2c.demand_mshr_miss_latency::cpu0.inst 6976120000 # number of demand (read+write) MSHR miss cycles 2940system.l2c.demand_mshr_miss_latency::cpu0.data 71651494499 # number of demand (read+write) MSHR miss cycles 2941system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 21412531280 # number of demand (read+write) MSHR miss cycles 2942system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 118043000 # number of demand (read+write) MSHR miss cycles 2943system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 122456000 # number of demand (read+write) MSHR miss cycles 2944system.l2c.demand_mshr_miss_latency::cpu1.inst 5880117000 # number of demand (read+write) MSHR miss cycles 2945system.l2c.demand_mshr_miss_latency::cpu1.data 24934238500 # number of demand (read+write) MSHR miss cycles 2946system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 17593741423 # number of demand (read+write) MSHR miss cycles 2947system.l2c.demand_mshr_miss_latency::total 148856754202 # number of demand (read+write) MSHR miss cycles 2948system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 83976000 # number of overall MSHR miss cycles 2949system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 84036500 # number of overall MSHR miss cycles 2950system.l2c.overall_mshr_miss_latency::cpu0.inst 6976120000 # number of overall MSHR miss cycles 2951system.l2c.overall_mshr_miss_latency::cpu0.data 71651494499 # number of overall MSHR miss cycles 2952system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21412531280 # number of overall MSHR miss cycles 2953system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 118043000 # number of overall MSHR miss cycles 2954system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 122456000 # number of overall MSHR miss cycles 2955system.l2c.overall_mshr_miss_latency::cpu1.inst 5880117000 # number of overall MSHR miss cycles 2956system.l2c.overall_mshr_miss_latency::cpu1.data 24934238500 # number of overall MSHR miss cycles 2957system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17593741423 # number of overall MSHR miss cycles 2958system.l2c.overall_mshr_miss_latency::total 148856754202 # number of overall MSHR miss cycles 2959system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles 2960system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2585611500 # number of ReadReq MSHR uncacheable cycles 2961system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10279000 # number of ReadReq MSHR uncacheable cycles 2962system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3324582500 # number of ReadReq MSHR uncacheable cycles 2963system.l2c.ReadReq_mshr_uncacheable_latency::total 11818139000 # number of ReadReq MSHR uncacheable cycles 2964system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2810539000 # number of WriteReq MSHR uncacheable cycles 2965system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3145380500 # number of WriteReq MSHR uncacheable cycles 2966system.l2c.WriteReq_mshr_uncacheable_latency::total 5955919500 # number of WriteReq MSHR uncacheable cycles 2967system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles 2968system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5396150500 # number of overall MSHR uncacheable cycles 2969system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10279000 # number of overall MSHR uncacheable cycles 2970system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6469963000 # number of overall MSHR uncacheable cycles 2971system.l2c.overall_mshr_uncacheable_latency::total 17774058500 # number of overall MSHR uncacheable cycles 2972system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2973system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2974system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.283558 # mshr miss rate for UpgradeReq accesses 2975system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.311704 # mshr miss rate for UpgradeReq accesses 2976system.l2c.UpgradeReq_mshr_miss_rate::total 0.296629 # mshr miss rate for UpgradeReq accesses 2977system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.222890 # mshr miss rate for SCUpgradeReq accesses 2978system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.219180 # mshr miss rate for SCUpgradeReq accesses 2979system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.220975 # mshr miss rate for SCUpgradeReq accesses 2980system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.735273 # mshr miss rate for ReadExReq accesses 2981system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.389634 # mshr miss rate for ReadExReq accesses 2982system.l2c.ReadExReq_mshr_miss_rate::total 0.622169 # mshr miss rate for ReadExReq accesses 2983system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for ReadSharedReq accesses 2984system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for ReadSharedReq accesses 2985system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for ReadSharedReq accesses 2986system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.143630 # mshr miss rate for ReadSharedReq accesses 2987system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for ReadSharedReq accesses 2988system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for ReadSharedReq accesses 2989system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for ReadSharedReq accesses 2990system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for ReadSharedReq accesses 2991system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.127885 # mshr miss rate for ReadSharedReq accesses 2992system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for ReadSharedReq accesses 2993system.l2c.ReadSharedReq_mshr_miss_rate::total 0.152296 # mshr miss rate for ReadSharedReq accesses 2994system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for demand accesses 2995system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for demand accesses 2996system.l2c.demand_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for demand accesses 2997system.l2c.demand_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for demand accesses 2998system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for demand accesses 2999system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for demand accesses 3000system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for demand accesses 3001system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for demand accesses 3002system.l2c.demand_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for demand accesses 3003system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for demand accesses 3004system.l2c.demand_mshr_miss_rate::total 0.250397 # mshr miss rate for demand accesses 3005system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for overall accesses 3006system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for overall accesses 3007system.l2c.overall_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for overall accesses 3008system.l2c.overall_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for overall accesses 3009system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for overall accesses 3010system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for overall accesses 3011system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for overall accesses 3012system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for overall accesses 3013system.l2c.overall_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for overall accesses 3014system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for overall accesses 3015system.l2c.overall_mshr_miss_rate::total 0.250397 # mshr miss rate for overall accesses 3016system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73405.101388 # average UpgradeReq mshr miss latency 3017system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73447.407332 # average UpgradeReq mshr miss latency 3018system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73425.747080 # average UpgradeReq mshr miss latency 3019system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76522.838199 # average SCUpgradeReq mshr miss latency 3020system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.421053 # average SCUpgradeReq mshr miss latency 3021system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76500.089851 # average SCUpgradeReq mshr miss latency 3022system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129078.519295 # average ReadExReq mshr miss latency 3023system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124079.362956 # average ReadExReq mshr miss latency 3024system.l2c.ReadExReq_avg_mshr_miss_latency::total 128054.050765 # average ReadExReq mshr miss latency 3025system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average ReadSharedReq mshr miss latency 3026system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average ReadSharedReq mshr miss latency 3027system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average ReadSharedReq mshr miss latency 3028system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126097.370539 # average ReadSharedReq mshr miss latency 3029system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average ReadSharedReq mshr miss latency 3030system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average ReadSharedReq mshr miss latency 3031system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average ReadSharedReq mshr miss latency 3032system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average ReadSharedReq mshr miss latency 3033system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 126467.494956 # average ReadSharedReq mshr miss latency 3034system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average ReadSharedReq mshr miss latency 3035system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 136875.285945 # average ReadSharedReq mshr miss latency 3036system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency 3037system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency 3038system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency 3039system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency 3040system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency 3041system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency 3042system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency 3043system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency 3044system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency 3045system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency 3046system.l2c.demand_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency 3047system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency 3048system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency 3049system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency 3050system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency 3051system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency 3052system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency 3053system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency 3054system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency 3055system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency 3056system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency 3057system.l2c.overall_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency 3058system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 3059system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154383.299498 # average ReadReq mshr uncacheable latency 3060system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency 3061system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159070.933014 # average ReadReq mshr uncacheable latency 3062system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131241.202012 # average ReadReq mshr uncacheable latency 3063system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153993.698975 # average WriteReq mshr uncacheable latency 3064system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162871.815452 # average WriteReq mshr uncacheable latency 3065system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158558.142321 # average WriteReq mshr uncacheable latency 3066system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 3067system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154180.133718 # average overall mshr uncacheable latency 3068system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency 3069system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160896.324480 # average overall mshr uncacheable latency 3070system.l2c.overall_avg_mshr_uncacheable_latency::total 139282.030687 # average overall mshr uncacheable latency 3071system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3072system.membus.trans_dist::ReadReq 90049 # Transaction distribution 3073system.membus.trans_dist::ReadResp 640443 # Transaction distribution 3074system.membus.trans_dist::WriteReq 37563 # Transaction distribution 3075system.membus.trans_dist::WriteResp 37563 # Transaction distribution 3076system.membus.trans_dist::WritebackDirty 930050 # Transaction distribution 3077system.membus.trans_dist::CleanEvict 190296 # Transaction distribution 3078system.membus.trans_dist::UpgradeReq 413026 # Transaction distribution 3079system.membus.trans_dist::SCUpgradeReq 280293 # Transaction distribution 3080system.membus.trans_dist::UpgradeResp 150977 # Transaction distribution 3081system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3082system.membus.trans_dist::ReadExReq 593740 # Transaction distribution 3083system.membus.trans_dist::ReadExResp 574320 # Transaction distribution 3084system.membus.trans_dist::ReadSharedReq 550394 # Transaction distribution 3085system.membus.trans_dist::InvalidateReq 106981 # Transaction distribution 3086system.membus.trans_dist::InvalidateResp 106981 # Transaction distribution 3087system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122912 # Packet count per connected master and slave (bytes) 3088system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3089system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22290 # Packet count per connected master and slave (bytes) 3090system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4211327 # Packet count per connected master and slave (bytes) 3091system.membus.pkt_count_system.l2c.mem_side::total 4356581 # Packet count per connected master and slave (bytes) 3092system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343179 # Packet count per connected master and slave (bytes) 3093system.membus.pkt_count_system.iocache.mem_side::total 343179 # Packet count per connected master and slave (bytes) 3094system.membus.pkt_count::total 4699760 # Packet count per connected master and slave (bytes) 3095system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155927 # Cumulative packet size per connected master and slave (bytes) 3096system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3097system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 44580 # Cumulative packet size per connected master and slave (bytes) 3098system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 127415488 # Cumulative packet size per connected master and slave (bytes) 3099system.membus.pkt_size_system.l2c.mem_side::total 127617319 # Cumulative packet size per connected master and slave (bytes) 3100system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7277312 # Cumulative packet size per connected master and slave (bytes) 3101system.membus.pkt_size_system.iocache.mem_side::total 7277312 # Cumulative packet size per connected master and slave (bytes) 3102system.membus.pkt_size::total 134894631 # Cumulative packet size per connected master and slave (bytes) 3103system.membus.snoops 564682 # Total snoops (count) 3104system.membus.snoop_fanout::samples 3194785 # Request fanout histogram 3105system.membus.snoop_fanout::mean 1 # Request fanout histogram 3106system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3107system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3108system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3109system.membus.snoop_fanout::1 3194785 100.00% 100.00% # Request fanout histogram 3110system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3111system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3112system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3113system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3114system.membus.snoop_fanout::total 3194785 # Request fanout histogram 3115system.membus.reqLayer0.occupancy 109901497 # Layer occupancy (ticks) 3116system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3117system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3118system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3119system.membus.reqLayer2.occupancy 18632000 # Layer occupancy (ticks) 3120system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3121system.membus.reqLayer5.occupancy 6680198838 # Layer occupancy (ticks) 3122system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3123system.membus.respLayer2.occupancy 6549107858 # Layer occupancy (ticks) 3124system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3125system.membus.respLayer3.occupancy 229362666 # Layer occupancy (ticks) 3126system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3127system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3128system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3129system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3130system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3131system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3132system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3133system.realview.ethernet.txBytes 966 # Bytes Transmitted 3134system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3135system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3136system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3137system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3138system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3139system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3140system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3141system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3142system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3143system.realview.ethernet.totPackets 3 # Total Packets 3144system.realview.ethernet.totBytes 966 # Total Bytes 3145system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3146system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3147system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3148system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3149system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3150system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3151system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3152system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3153system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3154system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3155system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3156system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3157system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3158system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3159system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3160system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3161system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3162system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3163system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3164system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3165system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3166system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3167system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3168system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3169system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3170system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3171system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3172system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3173system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3174system.realview.ethernet.droppedPackets 0 # number of packets dropped 3175system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3176system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3177system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3178system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3179system.toL2Bus.snoop_filter.tot_requests 11369480 # Total number of requests made to the snoop filter. 3180system.toL2Bus.snoop_filter.hit_single_requests 6166084 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3181system.toL2Bus.snoop_filter.hit_multi_requests 1983565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3182system.toL2Bus.snoop_filter.tot_snoops 99756 # Total number of snoops made to the snoop filter. 3183system.toL2Bus.snoop_filter.hit_single_snoops 89163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3184system.toL2Bus.snoop_filter.hit_multi_snoops 10593 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3185system.toL2Bus.trans_dist::ReadReq 90051 # Transaction distribution 3186system.toL2Bus.trans_dist::ReadResp 4379282 # Transaction distribution 3187system.toL2Bus.trans_dist::WriteReq 37563 # Transaction distribution 3188system.toL2Bus.trans_dist::WriteResp 37563 # Transaction distribution 3189system.toL2Bus.trans_dist::WritebackDirty 3408225 # Transaction distribution 3190system.toL2Bus.trans_dist::CleanEvict 1479469 # Transaction distribution 3191system.toL2Bus.trans_dist::UpgradeReq 686639 # Transaction distribution 3192system.toL2Bus.trans_dist::SCUpgradeReq 358765 # Transaction distribution 3193system.toL2Bus.trans_dist::UpgradeResp 1045403 # Transaction distribution 3194system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution 3195system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 3196system.toL2Bus.trans_dist::ReadExReq 1072017 # Transaction distribution 3197system.toL2Bus.trans_dist::ReadExResp 1072017 # Transaction distribution 3198system.toL2Bus.trans_dist::ReadSharedReq 4296486 # Transaction distribution 3199system.toL2Bus.trans_dist::InvalidateReq 106981 # Transaction distribution 3200system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8273345 # Packet count per connected master and slave (bytes) 3201system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7109938 # Packet count per connected master and slave (bytes) 3202system.toL2Bus.pkt_count::total 15383283 # Packet count per connected master and slave (bytes) 3203system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 249443752 # Cumulative packet size per connected master and slave (bytes) 3204system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200422911 # Cumulative packet size per connected master and slave (bytes) 3205system.toL2Bus.pkt_size::total 449866663 # Cumulative packet size per connected master and slave (bytes) 3206system.toL2Bus.snoops 2689125 # Total snoops (count) 3207system.toL2Bus.snoop_fanout::samples 7811601 # Request fanout histogram 3208system.toL2Bus.snoop_fanout::mean 0.375584 # Request fanout histogram 3209system.toL2Bus.snoop_fanout::stdev 0.487066 # Request fanout histogram 3210system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3211system.toL2Bus.snoop_fanout::0 4888281 62.58% 62.58% # Request fanout histogram 3212system.toL2Bus.snoop_fanout::1 2912727 37.29% 99.86% # Request fanout histogram 3213system.toL2Bus.snoop_fanout::2 10593 0.14% 100.00% # Request fanout histogram 3214system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3215system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3216system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3217system.toL2Bus.snoop_fanout::total 7811601 # Request fanout histogram 3218system.toL2Bus.reqLayer0.occupancy 8585712934 # Layer occupancy (ticks) 3219system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3220system.toL2Bus.snoopLayer0.occupancy 2584443 # Layer occupancy (ticks) 3221system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3222system.toL2Bus.respLayer0.occupancy 4648327252 # Layer occupancy (ticks) 3223system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3224system.toL2Bus.respLayer1.occupancy 4065319209 # Layer occupancy (ticks) 3225system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3226 3227---------- End Simulation Statistics ---------- 3228