stats.txt revision 11138:a611a23c8cc2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.464182 # Number of seconds simulated 4sim_ticks 47464181819000 # Number of ticks simulated 5final_tick 47464181819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 165089 # Simulator instruction rate (inst/s) 8host_op_rate 194182 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9130718670 # Simulator tick rate (ticks/s) 10host_mem_usage 773696 # Number of bytes of host memory used 11host_seconds 5198.30 # Real time elapsed on the host 12sim_insts 858179266 # Number of instructions simulated 13sim_ops 1009414094 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 76544 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 6880896 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 37557256 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10768960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 75264 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 68480 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3528576 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 13557136 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 8552832 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory 27system.physmem.bytes_read::total 81587544 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 6880896 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3528576 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 10409472 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 64065088 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 64085672 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1196 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 107514 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 586845 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 168265 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1176 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1070 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 55134 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 211843 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 133638 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1274831 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1001017 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1003591 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1803 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1613 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 144970 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 791276 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 226886 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1586 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1443 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 74342 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 285629 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 180196 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9187 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1718929 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 144970 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 74342 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 219312 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1349757 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1350190 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1349757 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1803 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1613 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 144970 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 791709 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 226886 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1586 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1443 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 74342 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 285629 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 180196 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9187 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3069119 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1274831 # Number of read requests accepted 84system.physmem.writeReqs 1003591 # Number of write requests accepted 85system.physmem.readBursts 1274831 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1003591 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 81546816 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue 89system.physmem.bytesWritten 64084800 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 81587544 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 64085672 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 221043 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 69298 # Per bank write bursts 96system.physmem.perBankRdBursts::1 80196 # Per bank write bursts 97system.physmem.perBankRdBursts::2 71590 # Per bank write bursts 98system.physmem.perBankRdBursts::3 80518 # Per bank write bursts 99system.physmem.perBankRdBursts::4 76240 # Per bank write bursts 100system.physmem.perBankRdBursts::5 80771 # Per bank write bursts 101system.physmem.perBankRdBursts::6 77164 # Per bank write bursts 102system.physmem.perBankRdBursts::7 81418 # Per bank write bursts 103system.physmem.perBankRdBursts::8 74880 # Per bank write bursts 104system.physmem.perBankRdBursts::9 125815 # Per bank write bursts 105system.physmem.perBankRdBursts::10 65333 # Per bank write bursts 106system.physmem.perBankRdBursts::11 79047 # Per bank write bursts 107system.physmem.perBankRdBursts::12 75605 # Per bank write bursts 108system.physmem.perBankRdBursts::13 79656 # Per bank write bursts 109system.physmem.perBankRdBursts::14 77605 # Per bank write bursts 110system.physmem.perBankRdBursts::15 79033 # Per bank write bursts 111system.physmem.perBankWrBursts::0 58028 # Per bank write bursts 112system.physmem.perBankWrBursts::1 64393 # Per bank write bursts 113system.physmem.perBankWrBursts::2 59641 # Per bank write bursts 114system.physmem.perBankWrBursts::3 64677 # Per bank write bursts 115system.physmem.perBankWrBursts::4 61513 # Per bank write bursts 116system.physmem.perBankWrBursts::5 65147 # Per bank write bursts 117system.physmem.perBankWrBursts::6 63058 # Per bank write bursts 118system.physmem.perBankWrBursts::7 64825 # Per bank write bursts 119system.physmem.perBankWrBursts::8 60547 # Per bank write bursts 120system.physmem.perBankWrBursts::9 63081 # Per bank write bursts 121system.physmem.perBankWrBursts::10 56749 # Per bank write bursts 122system.physmem.perBankWrBursts::11 64053 # Per bank write bursts 123system.physmem.perBankWrBursts::12 61964 # Per bank write bursts 124system.physmem.perBankWrBursts::13 65797 # Per bank write bursts 125system.physmem.perBankWrBursts::14 62586 # Per bank write bursts 126system.physmem.perBankWrBursts::15 65266 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 59 # Number of times write queue was full causing retry 129system.physmem.totGap 47464179840500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1274801 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1001017 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 816238 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 315854 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 31830 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 23000 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 19787 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 18192 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 16305 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 14624 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 12016 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 2281 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1222 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 783 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 615 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 252 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 209 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 201 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 148 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 15348 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 17874 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 37266 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 47521 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 53574 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 55971 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 59005 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 60181 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 62652 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 62838 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 63556 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 68208 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 65188 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 65181 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 70319 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 65705 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 61499 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 58334 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1919 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1152 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 800 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 620 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 493 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 457 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 321 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 358 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 237 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 344 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 339 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 227 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 143 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 122 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 102 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 193 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 760858 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 191.403705 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 116.807820 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 249.999790 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 448904 59.00% 59.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 151841 19.96% 78.96% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 50675 6.66% 85.62% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 27026 3.55% 89.17% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 17061 2.24% 91.41% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11068 1.45% 92.87% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8074 1.06% 93.93% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 8214 1.08% 95.01% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 37995 4.99% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 760858 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 56148 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 22.692705 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 368.089974 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 56145 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 56148 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 56148 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.833672 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.227387 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.381246 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 52715 93.89% 93.89% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 1304 2.32% 96.21% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 213 0.38% 96.59% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 294 0.52% 97.11% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 73 0.13% 97.24% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 309 0.55% 97.79% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 189 0.34% 98.13% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 132 0.24% 98.36% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 76 0.14% 98.50% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 103 0.18% 98.68% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 49 0.09% 98.77% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 61 0.11% 98.88% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 401 0.71% 99.59% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 39 0.07% 99.66% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 42 0.07% 99.74% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 82 0.15% 99.88% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 1 0.00% 99.91% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::total 56148 # Writes before turning the bus around for reads 302system.physmem.totQLat 34002300770 # Total ticks spent queuing 303system.physmem.totMemAccLat 57892969520 # Total ticks spent from burst creation until serviced by the DRAM 304system.physmem.totBusLat 6370845000 # Total ticks spent in databus transfers 305system.physmem.avgQLat 26685.86 # Average queueing delay per DRAM burst 306system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 307system.physmem.avgMemAccLat 45435.86 # Average memory access latency per DRAM burst 308system.physmem.avgRdBW 1.72 # Average DRAM read bandwidth in MiByte/s 309system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s 310system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s 311system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s 312system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 313system.physmem.busUtil 0.02 # Data bus utilization in percentage 314system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 315system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 316system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 317system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing 318system.physmem.readRowHits 1026298 # Number of row buffer hits during reads 319system.physmem.writeRowHits 488335 # Number of row buffer hits during writes 320system.physmem.readRowHitRate 80.55 # Row buffer hit rate for reads 321system.physmem.writeRowHitRate 48.77 # Row buffer hit rate for writes 322system.physmem.avgGap 20832040.70 # Average gap between requests 323system.physmem.pageHitRate 66.56 # Row buffer hit rate, read and write combined 324system.physmem_0.actEnergy 2867901120 # Energy for activate commands per rank (pJ) 325system.physmem_0.preEnergy 1564827000 # Energy for precharge commands per rank (pJ) 326system.physmem_0.readEnergy 4814050800 # Energy for read commands per rank (pJ) 327system.physmem_0.writeEnergy 3248307360 # Energy for write commands per rank (pJ) 328system.physmem_0.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ) 329system.physmem_0.actBackEnergy 1185321114675 # Energy for active background per rank (pJ) 330system.physmem_0.preBackEnergy 27438751602000 # Energy for precharge background per rank (pJ) 331system.physmem_0.totalEnergy 31736697181275 # Total energy per rank (pJ) 332system.physmem_0.averagePower 668.645246 # Core power per rank (mW) 333system.physmem_0.memoryStateTime::IDLE 45646225461150 # Time in different power states 334system.physmem_0.memoryStateTime::REF 1584933220000 # Time in different power states 335system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 336system.physmem_0.memoryStateTime::ACT 233019608850 # Time in different power states 337system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 338system.physmem_1.actEnergy 2884185360 # Energy for activate commands per rank (pJ) 339system.physmem_1.preEnergy 1573712250 # Energy for precharge commands per rank (pJ) 340system.physmem_1.readEnergy 5124397200 # Energy for read commands per rank (pJ) 341system.physmem_1.writeEnergy 3240278640 # Energy for write commands per rank (pJ) 342system.physmem_1.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ) 343system.physmem_1.actBackEnergy 1191686941080 # Energy for active background per rank (pJ) 344system.physmem_1.preBackEnergy 27433167543750 # Energy for precharge background per rank (pJ) 345system.physmem_1.totalEnergy 31737806436600 # Total energy per rank (pJ) 346system.physmem_1.averagePower 668.668617 # Core power per rank (mW) 347system.physmem_1.memoryStateTime::IDLE 45636858751692 # Time in different power states 348system.physmem_1.memoryStateTime::REF 1584933220000 # Time in different power states 349system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 350system.physmem_1.memoryStateTime::ACT 242386318308 # Time in different power states 351system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 352system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 357system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 358system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 359system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 360system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 363system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 365system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 378system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 379system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 380system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 381system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 382system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 383system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 384system.cpu0.branchPred.lookups 135703894 # Number of BP lookups 385system.cpu0.branchPred.condPredicted 95425291 # Number of conditional branches predicted 386system.cpu0.branchPred.condIncorrect 6312333 # Number of conditional branches incorrect 387system.cpu0.branchPred.BTBLookups 100672877 # Number of BTB lookups 388system.cpu0.branchPred.BTBHits 73270894 # Number of BTB hits 389system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 390system.cpu0.branchPred.BTBHitPct 72.781166 # BTB Hit Percentage 391system.cpu0.branchPred.usedRAS 16275299 # Number of times the RAS was used to get a target. 392system.cpu0.branchPred.RASInCorrect 1070570 # Number of incorrect RAS predictions. 393system.cpu_clk_domain.clock 500 # Clock period in ticks 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 403system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 404system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 405system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 406system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 407system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 410system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 411system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 412system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 413system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 415system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 418system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 419system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 420system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 421system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 422system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 423system.cpu0.dtb.walker.walks 277006 # Table walker walks requested 424system.cpu0.dtb.walker.walksLong 277006 # Table walker walks initiated with long descriptors 425system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8797 # Level at which table walker walks with long descriptors terminate 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76685 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walkWaitTime::samples 277006 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::0 277006 100.00% 100.00% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::total 277006 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkCompletionTime::samples 85482 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::mean 21392.901430 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::gmean 19388.852647 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::stdev 17614.753194 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::0-65535 84631 99.00% 99.00% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::65536-131071 172 0.20% 99.21% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::131072-196607 584 0.68% 99.89% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::196608-262143 16 0.02% 99.91% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.95% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.96% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::393216-458751 27 0.03% 99.99% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::total 85482 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution 448system.cpu0.dtb.walker.walkPageSizes::4K 76685 89.71% 89.71% # Table walker page sizes translated 449system.cpu0.dtb.walker.walkPageSizes::2M 8797 10.29% 100.00% # Table walker page sizes translated 450system.cpu0.dtb.walker.walkPageSizes::total 85482 # Table walker page sizes translated 451system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 277006 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 277006 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85482 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85482 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin::total 362488 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.inst_hits 0 # ITB inst hits 459system.cpu0.dtb.inst_misses 0 # ITB inst misses 460system.cpu0.dtb.read_hits 88941283 # DTB read hits 461system.cpu0.dtb.read_misses 229899 # DTB read misses 462system.cpu0.dtb.write_hits 77314134 # DTB write hits 463system.cpu0.dtb.write_misses 47107 # DTB write misses 464system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 465system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 466system.cpu0.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID 467system.cpu0.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID 468system.cpu0.dtb.flush_entries 37002 # Number of entries that have been flushed from TLB 469system.cpu0.dtb.align_faults 982 # Number of TLB faults due to alignment restrictions 470system.cpu0.dtb.prefetch_faults 8335 # Number of TLB faults due to prefetch 471system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 472system.cpu0.dtb.perms_faults 10385 # Number of TLB faults due to permissions restrictions 473system.cpu0.dtb.read_accesses 89171182 # DTB read accesses 474system.cpu0.dtb.write_accesses 77361241 # DTB write accesses 475system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 476system.cpu0.dtb.hits 166255417 # DTB hits 477system.cpu0.dtb.misses 277006 # DTB misses 478system.cpu0.dtb.accesses 166532423 # DTB accesses 479system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 488system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 489system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 490system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 491system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 492system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 493system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 494system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 495system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 496system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 497system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 498system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 499system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 500system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 501system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 502system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 503system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 504system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 505system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 506system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 507system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 508system.cpu0.itb.walker.walks 67964 # Table walker walks requested 509system.cpu0.itb.walker.walksLong 67964 # Table walker walks initiated with long descriptors 510system.cpu0.itb.walker.walksLongTerminationLevel::Level2 522 # Level at which table walker walks with long descriptors terminate 511system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55569 # Level at which table walker walks with long descriptors terminate 512system.cpu0.itb.walker.walkWaitTime::samples 67964 # Table walker wait (enqueue to first request) latency 513system.cpu0.itb.walker.walkWaitTime::0 67964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 514system.cpu0.itb.walker.walkWaitTime::total 67964 # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkCompletionTime::samples 56091 # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::mean 23783.423366 # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::gmean 21371.413212 # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::stdev 19530.956784 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::0-32767 52347 93.33% 93.33% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::32768-65535 2944 5.25% 98.57% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::65536-98303 5 0.01% 98.58% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.58% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::131072-163839 475 0.85% 99.43% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::163840-196607 248 0.44% 99.87% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::196608-229375 15 0.03% 99.90% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.92% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.93% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.98% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::393216-425983 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::total 56091 # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution 535system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution 536system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution 537system.cpu0.itb.walker.walkPageSizes::4K 55569 99.07% 99.07% # Table walker page sizes translated 538system.cpu0.itb.walker.walkPageSizes::2M 522 0.93% 100.00% # Table walker page sizes translated 539system.cpu0.itb.walker.walkPageSizes::total 56091 # Table walker page sizes translated 540system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67964 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67964 # Table walker requests started/completed, data/inst 543system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 544system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56091 # Table walker requests started/completed, data/inst 545system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56091 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin::total 124055 # Table walker requests started/completed, data/inst 547system.cpu0.itb.inst_hits 243132835 # ITB inst hits 548system.cpu0.itb.inst_misses 67964 # ITB inst misses 549system.cpu0.itb.read_hits 0 # DTB read hits 550system.cpu0.itb.read_misses 0 # DTB read misses 551system.cpu0.itb.write_hits 0 # DTB write hits 552system.cpu0.itb.write_misses 0 # DTB write misses 553system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 554system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 555system.cpu0.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID 556system.cpu0.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID 557system.cpu0.itb.flush_entries 26811 # Number of entries that have been flushed from TLB 558system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 559system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 560system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 561system.cpu0.itb.perms_faults 210881 # Number of TLB faults due to permissions restrictions 562system.cpu0.itb.read_accesses 0 # DTB read accesses 563system.cpu0.itb.write_accesses 0 # DTB write accesses 564system.cpu0.itb.inst_accesses 243200799 # ITB inst accesses 565system.cpu0.itb.hits 243132835 # DTB hits 566system.cpu0.itb.misses 67964 # DTB misses 567system.cpu0.itb.accesses 243200799 # DTB accesses 568system.cpu0.numCycles 1024570142 # number of cpu cycles simulated 569system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 570system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 571system.cpu0.committedInsts 453671847 # Number of instructions committed 572system.cpu0.committedOps 532972040 # Number of ops (including micro ops) committed 573system.cpu0.discardedOps 44332709 # Number of ops (including micro ops) which were discarded before commit 574system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching 575system.cpu0.quiesceCycles 93904749601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 576system.cpu0.cpi 2.258395 # CPI: cycles per instruction 577system.cpu0.ipc 0.442792 # IPC: instructions per cycle 578system.cpu0.kern.inst.arm 0 # number of arm instructions executed 579system.cpu0.kern.inst.quiesce 6224 # number of quiesce instructions executed 580system.cpu0.tickCycles 727182617 # Number of cycles that the object actually ticked 581system.cpu0.idleCycles 297387525 # Total number of cycles that the object has spent stopped 582system.cpu0.dcache.tags.replacements 5606815 # number of replacements 583system.cpu0.dcache.tags.tagsinuse 475.898466 # Cycle average of tags in use 584system.cpu0.dcache.tags.total_refs 157812679 # Total number of references to valid blocks. 585system.cpu0.dcache.tags.sampled_refs 5607327 # Sample count of references to valid blocks. 586system.cpu0.dcache.tags.avg_refs 28.144012 # Average number of references to valid blocks. 587system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit. 588system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.898466 # Average occupied blocks per requestor 589system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929489 # Average percentage of cache occupancy 590system.cpu0.dcache.tags.occ_percent::total 0.929489 # Average percentage of cache occupancy 591system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 592system.cpu0.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 593system.cpu0.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id 594system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id 595system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 596system.cpu0.dcache.tags.tag_accesses 335393662 # Number of tag accesses 597system.cpu0.dcache.tags.data_accesses 335393662 # Number of data accesses 598system.cpu0.dcache.ReadReq_hits::cpu0.data 81544003 # number of ReadReq hits 599system.cpu0.dcache.ReadReq_hits::total 81544003 # number of ReadReq hits 600system.cpu0.dcache.WriteReq_hits::cpu0.data 71771704 # number of WriteReq hits 601system.cpu0.dcache.WriteReq_hits::total 71771704 # number of WriteReq hits 602system.cpu0.dcache.SoftPFReq_hits::cpu0.data 253031 # number of SoftPFReq hits 603system.cpu0.dcache.SoftPFReq_hits::total 253031 # number of SoftPFReq hits 604system.cpu0.dcache.WriteLineReq_hits::cpu0.data 130003 # number of WriteLineReq hits 605system.cpu0.dcache.WriteLineReq_hits::total 130003 # number of WriteLineReq hits 606system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1818235 # number of LoadLockedReq hits 607system.cpu0.dcache.LoadLockedReq_hits::total 1818235 # number of LoadLockedReq hits 608system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1799115 # number of StoreCondReq hits 609system.cpu0.dcache.StoreCondReq_hits::total 1799115 # number of StoreCondReq hits 610system.cpu0.dcache.demand_hits::cpu0.data 153315707 # number of demand (read+write) hits 611system.cpu0.dcache.demand_hits::total 153315707 # number of demand (read+write) hits 612system.cpu0.dcache.overall_hits::cpu0.data 153568738 # number of overall hits 613system.cpu0.dcache.overall_hits::total 153568738 # number of overall hits 614system.cpu0.dcache.ReadReq_misses::cpu0.data 3470214 # number of ReadReq misses 615system.cpu0.dcache.ReadReq_misses::total 3470214 # number of ReadReq misses 616system.cpu0.dcache.WriteReq_misses::cpu0.data 2296821 # number of WriteReq misses 617system.cpu0.dcache.WriteReq_misses::total 2296821 # number of WriteReq misses 618system.cpu0.dcache.SoftPFReq_misses::cpu0.data 622517 # number of SoftPFReq misses 619system.cpu0.dcache.SoftPFReq_misses::total 622517 # number of SoftPFReq misses 620system.cpu0.dcache.WriteLineReq_misses::cpu0.data 787681 # number of WriteLineReq misses 621system.cpu0.dcache.WriteLineReq_misses::total 787681 # number of WriteLineReq misses 622system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168627 # number of LoadLockedReq misses 623system.cpu0.dcache.LoadLockedReq_misses::total 168627 # number of LoadLockedReq misses 624system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185724 # number of StoreCondReq misses 625system.cpu0.dcache.StoreCondReq_misses::total 185724 # number of StoreCondReq misses 626system.cpu0.dcache.demand_misses::cpu0.data 5767035 # number of demand (read+write) misses 627system.cpu0.dcache.demand_misses::total 5767035 # number of demand (read+write) misses 628system.cpu0.dcache.overall_misses::cpu0.data 6389552 # number of overall misses 629system.cpu0.dcache.overall_misses::total 6389552 # number of overall misses 630system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57404903000 # number of ReadReq miss cycles 631system.cpu0.dcache.ReadReq_miss_latency::total 57404903000 # number of ReadReq miss cycles 632system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 53218814500 # number of WriteReq miss cycles 633system.cpu0.dcache.WriteReq_miss_latency::total 53218814500 # number of WriteReq miss cycles 634system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 70624877500 # number of WriteLineReq miss cycles 635system.cpu0.dcache.WriteLineReq_miss_latency::total 70624877500 # number of WriteLineReq miss cycles 636system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2615349000 # number of LoadLockedReq miss cycles 637system.cpu0.dcache.LoadLockedReq_miss_latency::total 2615349000 # number of LoadLockedReq miss cycles 638system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4471340500 # number of StoreCondReq miss cycles 639system.cpu0.dcache.StoreCondReq_miss_latency::total 4471340500 # number of StoreCondReq miss cycles 640system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4645500 # number of StoreCondFailReq miss cycles 641system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4645500 # number of StoreCondFailReq miss cycles 642system.cpu0.dcache.demand_miss_latency::cpu0.data 110623717500 # number of demand (read+write) miss cycles 643system.cpu0.dcache.demand_miss_latency::total 110623717500 # number of demand (read+write) miss cycles 644system.cpu0.dcache.overall_miss_latency::cpu0.data 110623717500 # number of overall miss cycles 645system.cpu0.dcache.overall_miss_latency::total 110623717500 # number of overall miss cycles 646system.cpu0.dcache.ReadReq_accesses::cpu0.data 85014217 # number of ReadReq accesses(hits+misses) 647system.cpu0.dcache.ReadReq_accesses::total 85014217 # number of ReadReq accesses(hits+misses) 648system.cpu0.dcache.WriteReq_accesses::cpu0.data 74068525 # number of WriteReq accesses(hits+misses) 649system.cpu0.dcache.WriteReq_accesses::total 74068525 # number of WriteReq accesses(hits+misses) 650system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 875548 # number of SoftPFReq accesses(hits+misses) 651system.cpu0.dcache.SoftPFReq_accesses::total 875548 # number of SoftPFReq accesses(hits+misses) 652system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 917684 # number of WriteLineReq accesses(hits+misses) 653system.cpu0.dcache.WriteLineReq_accesses::total 917684 # number of WriteLineReq accesses(hits+misses) 654system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986862 # number of LoadLockedReq accesses(hits+misses) 655system.cpu0.dcache.LoadLockedReq_accesses::total 1986862 # number of LoadLockedReq accesses(hits+misses) 656system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1984839 # number of StoreCondReq accesses(hits+misses) 657system.cpu0.dcache.StoreCondReq_accesses::total 1984839 # number of StoreCondReq accesses(hits+misses) 658system.cpu0.dcache.demand_accesses::cpu0.data 159082742 # number of demand (read+write) accesses 659system.cpu0.dcache.demand_accesses::total 159082742 # number of demand (read+write) accesses 660system.cpu0.dcache.overall_accesses::cpu0.data 159958290 # number of overall (read+write) accesses 661system.cpu0.dcache.overall_accesses::total 159958290 # number of overall (read+write) accesses 662system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040819 # miss rate for ReadReq accesses 663system.cpu0.dcache.ReadReq_miss_rate::total 0.040819 # miss rate for ReadReq accesses 664system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031009 # miss rate for WriteReq accesses 665system.cpu0.dcache.WriteReq_miss_rate::total 0.031009 # miss rate for WriteReq accesses 666system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.711003 # miss rate for SoftPFReq accesses 667system.cpu0.dcache.SoftPFReq_miss_rate::total 0.711003 # miss rate for SoftPFReq accesses 668system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858336 # miss rate for WriteLineReq accesses 669system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858336 # miss rate for WriteLineReq accesses 670system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084871 # miss rate for LoadLockedReq accesses 671system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084871 # miss rate for LoadLockedReq accesses 672system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093571 # miss rate for StoreCondReq accesses 673system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093571 # miss rate for StoreCondReq accesses 674system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036252 # miss rate for demand accesses 675system.cpu0.dcache.demand_miss_rate::total 0.036252 # miss rate for demand accesses 676system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039945 # miss rate for overall accesses 677system.cpu0.dcache.overall_miss_rate::total 0.039945 # miss rate for overall accesses 678system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16542.179531 # average ReadReq miss latency 679system.cpu0.dcache.ReadReq_avg_miss_latency::total 16542.179531 # average ReadReq miss latency 680system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23170.640855 # average WriteReq miss latency 681system.cpu0.dcache.WriteReq_avg_miss_latency::total 23170.640855 # average WriteReq miss latency 682system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 89661.776150 # average WriteLineReq miss latency 683system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 89661.776150 # average WriteLineReq miss latency 684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15509.669270 # average LoadLockedReq miss latency 685system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15509.669270 # average LoadLockedReq miss latency 686system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24075.189529 # average StoreCondReq miss latency 687system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24075.189529 # average StoreCondReq miss latency 688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 689system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 690system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19182.078399 # average overall miss latency 691system.cpu0.dcache.demand_avg_miss_latency::total 19182.078399 # average overall miss latency 692system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17313.219691 # average overall miss latency 693system.cpu0.dcache.overall_avg_miss_latency::total 17313.219691 # average overall miss latency 694system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 695system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 696system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 697system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 698system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 699system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 700system.cpu0.dcache.fast_writes 0 # number of fast writes performed 701system.cpu0.dcache.cache_copies 0 # number of cache copies performed 702system.cpu0.dcache.writebacks::writebacks 3758761 # number of writebacks 703system.cpu0.dcache.writebacks::total 3758761 # number of writebacks 704system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423304 # number of ReadReq MSHR hits 705system.cpu0.dcache.ReadReq_mshr_hits::total 423304 # number of ReadReq MSHR hits 706system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 954060 # number of WriteReq MSHR hits 707system.cpu0.dcache.WriteReq_mshr_hits::total 954060 # number of WriteReq MSHR hits 708system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 67 # number of WriteLineReq MSHR hits 709system.cpu0.dcache.WriteLineReq_mshr_hits::total 67 # number of WriteLineReq MSHR hits 710system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43006 # number of LoadLockedReq MSHR hits 711system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43006 # number of LoadLockedReq MSHR hits 712system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 59 # number of StoreCondReq MSHR hits 713system.cpu0.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits 714system.cpu0.dcache.demand_mshr_hits::cpu0.data 1377364 # number of demand (read+write) MSHR hits 715system.cpu0.dcache.demand_mshr_hits::total 1377364 # number of demand (read+write) MSHR hits 716system.cpu0.dcache.overall_mshr_hits::cpu0.data 1377364 # number of overall MSHR hits 717system.cpu0.dcache.overall_mshr_hits::total 1377364 # number of overall MSHR hits 718system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3046910 # number of ReadReq MSHR misses 719system.cpu0.dcache.ReadReq_mshr_misses::total 3046910 # number of ReadReq MSHR misses 720system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342761 # number of WriteReq MSHR misses 721system.cpu0.dcache.WriteReq_mshr_misses::total 1342761 # number of WriteReq MSHR misses 722system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 616851 # number of SoftPFReq MSHR misses 723system.cpu0.dcache.SoftPFReq_mshr_misses::total 616851 # number of SoftPFReq MSHR misses 724system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 787614 # number of WriteLineReq MSHR misses 725system.cpu0.dcache.WriteLineReq_mshr_misses::total 787614 # number of WriteLineReq MSHR misses 726system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125621 # number of LoadLockedReq MSHR misses 727system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125621 # number of LoadLockedReq MSHR misses 728system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185665 # number of StoreCondReq MSHR misses 729system.cpu0.dcache.StoreCondReq_mshr_misses::total 185665 # number of StoreCondReq MSHR misses 730system.cpu0.dcache.demand_mshr_misses::cpu0.data 4389671 # number of demand (read+write) MSHR misses 731system.cpu0.dcache.demand_mshr_misses::total 4389671 # number of demand (read+write) MSHR misses 732system.cpu0.dcache.overall_mshr_misses::cpu0.data 5006522 # number of overall MSHR misses 733system.cpu0.dcache.overall_mshr_misses::total 5006522 # number of overall MSHR misses 734system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable 735system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14625 # number of ReadReq MSHR uncacheable 736system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable 737system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable 738system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses 739system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30107 # number of overall MSHR uncacheable misses 740system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45015119500 # number of ReadReq MSHR miss cycles 741system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45015119500 # number of ReadReq MSHR miss cycles 742system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30226463500 # number of WriteReq MSHR miss cycles 743system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30226463500 # number of WriteReq MSHR miss cycles 744system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15766385500 # number of SoftPFReq MSHR miss cycles 745system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15766385500 # number of SoftPFReq MSHR miss cycles 746system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 69831148500 # number of WriteLineReq MSHR miss cycles 747system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 69831148500 # number of WriteLineReq MSHR miss cycles 748system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1724289500 # number of LoadLockedReq MSHR miss cycles 749system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1724289500 # number of LoadLockedReq MSHR miss cycles 750system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4281874000 # number of StoreCondReq MSHR miss cycles 751system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4281874000 # number of StoreCondReq MSHR miss cycles 752system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4478500 # number of StoreCondFailReq MSHR miss cycles 753system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4478500 # number of StoreCondFailReq MSHR miss cycles 754system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75241583000 # number of demand (read+write) MSHR miss cycles 755system.cpu0.dcache.demand_mshr_miss_latency::total 75241583000 # number of demand (read+write) MSHR miss cycles 756system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91007968500 # number of overall MSHR miss cycles 757system.cpu0.dcache.overall_mshr_miss_latency::total 91007968500 # number of overall MSHR miss cycles 758system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2444404000 # number of ReadReq MSHR uncacheable cycles 759system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2444404000 # number of ReadReq MSHR uncacheable cycles 760system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2533371000 # number of WriteReq MSHR uncacheable cycles 761system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2533371000 # number of WriteReq MSHR uncacheable cycles 762system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4977775000 # number of overall MSHR uncacheable cycles 763system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4977775000 # number of overall MSHR uncacheable cycles 764system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035840 # mshr miss rate for ReadReq accesses 765system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035840 # mshr miss rate for ReadReq accesses 766system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018129 # mshr miss rate for WriteReq accesses 767system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018129 # mshr miss rate for WriteReq accesses 768system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.704531 # mshr miss rate for SoftPFReq accesses 769system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.704531 # mshr miss rate for SoftPFReq accesses 770system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858263 # mshr miss rate for WriteLineReq accesses 771system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858263 # mshr miss rate for WriteLineReq accesses 772system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063226 # mshr miss rate for LoadLockedReq accesses 773system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063226 # mshr miss rate for LoadLockedReq accesses 774system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093542 # mshr miss rate for StoreCondReq accesses 775system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093542 # mshr miss rate for StoreCondReq accesses 776system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027594 # mshr miss rate for demand accesses 777system.cpu0.dcache.demand_mshr_miss_rate::total 0.027594 # mshr miss rate for demand accesses 778system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031299 # mshr miss rate for overall accesses 779system.cpu0.dcache.overall_mshr_miss_rate::total 0.031299 # mshr miss rate for overall accesses 780system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14774.023355 # average ReadReq mshr miss latency 781system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14774.023355 # average ReadReq mshr miss latency 782system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22510.680233 # average WriteReq mshr miss latency 783system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22510.680233 # average WriteReq mshr miss latency 784system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25559.471412 # average SoftPFReq mshr miss latency 785system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25559.471412 # average SoftPFReq mshr miss latency 786system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 88661.639458 # average WriteLineReq mshr miss latency 787system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 88661.639458 # average WriteLineReq mshr miss latency 788system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13726.124613 # average LoadLockedReq mshr miss latency 789system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.124613 # average LoadLockedReq mshr miss latency 790system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23062.365012 # average StoreCondReq mshr miss latency 791system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23062.365012 # average StoreCondReq mshr miss latency 792system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 793system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 794system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17140.597325 # average overall mshr miss latency 795system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17140.597325 # average overall mshr miss latency 796system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18177.882470 # average overall mshr miss latency 797system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18177.882470 # average overall mshr miss latency 798system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167138.735043 # average ReadReq mshr uncacheable latency 799system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167138.735043 # average ReadReq mshr uncacheable latency 800system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163633.316109 # average WriteReq mshr uncacheable latency 801system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163633.316109 # average WriteReq mshr uncacheable latency 802system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165336.134454 # average overall mshr uncacheable latency 803system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165336.134454 # average overall mshr uncacheable latency 804system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu0.icache.tags.replacements 9688574 # number of replacements 806system.cpu0.icache.tags.tagsinuse 511.890007 # Cycle average of tags in use 807system.cpu0.icache.tags.total_refs 233226662 # Total number of references to valid blocks. 808system.cpu0.icache.tags.sampled_refs 9689086 # Sample count of references to valid blocks. 809system.cpu0.icache.tags.avg_refs 24.071069 # Average number of references to valid blocks. 810system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit. 811system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890007 # Average occupied blocks per requestor 812system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999785 # Average percentage of cache occupancy 813system.cpu0.icache.tags.occ_percent::total 0.999785 # Average percentage of cache occupancy 814system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 815system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 816system.cpu0.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id 817system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 818system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 819system.cpu0.icache.tags.tag_accesses 495520584 # Number of tag accesses 820system.cpu0.icache.tags.data_accesses 495520584 # Number of data accesses 821system.cpu0.icache.ReadReq_hits::cpu0.inst 233226662 # number of ReadReq hits 822system.cpu0.icache.ReadReq_hits::total 233226662 # number of ReadReq hits 823system.cpu0.icache.demand_hits::cpu0.inst 233226662 # number of demand (read+write) hits 824system.cpu0.icache.demand_hits::total 233226662 # number of demand (read+write) hits 825system.cpu0.icache.overall_hits::cpu0.inst 233226662 # number of overall hits 826system.cpu0.icache.overall_hits::total 233226662 # number of overall hits 827system.cpu0.icache.ReadReq_misses::cpu0.inst 9689087 # number of ReadReq misses 828system.cpu0.icache.ReadReq_misses::total 9689087 # number of ReadReq misses 829system.cpu0.icache.demand_misses::cpu0.inst 9689087 # number of demand (read+write) misses 830system.cpu0.icache.demand_misses::total 9689087 # number of demand (read+write) misses 831system.cpu0.icache.overall_misses::cpu0.inst 9689087 # number of overall misses 832system.cpu0.icache.overall_misses::total 9689087 # number of overall misses 833system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100299166000 # number of ReadReq miss cycles 834system.cpu0.icache.ReadReq_miss_latency::total 100299166000 # number of ReadReq miss cycles 835system.cpu0.icache.demand_miss_latency::cpu0.inst 100299166000 # number of demand (read+write) miss cycles 836system.cpu0.icache.demand_miss_latency::total 100299166000 # number of demand (read+write) miss cycles 837system.cpu0.icache.overall_miss_latency::cpu0.inst 100299166000 # number of overall miss cycles 838system.cpu0.icache.overall_miss_latency::total 100299166000 # number of overall miss cycles 839system.cpu0.icache.ReadReq_accesses::cpu0.inst 242915749 # number of ReadReq accesses(hits+misses) 840system.cpu0.icache.ReadReq_accesses::total 242915749 # number of ReadReq accesses(hits+misses) 841system.cpu0.icache.demand_accesses::cpu0.inst 242915749 # number of demand (read+write) accesses 842system.cpu0.icache.demand_accesses::total 242915749 # number of demand (read+write) accesses 843system.cpu0.icache.overall_accesses::cpu0.inst 242915749 # number of overall (read+write) accesses 844system.cpu0.icache.overall_accesses::total 242915749 # number of overall (read+write) accesses 845system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039887 # miss rate for ReadReq accesses 846system.cpu0.icache.ReadReq_miss_rate::total 0.039887 # miss rate for ReadReq accesses 847system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039887 # miss rate for demand accesses 848system.cpu0.icache.demand_miss_rate::total 0.039887 # miss rate for demand accesses 849system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039887 # miss rate for overall accesses 850system.cpu0.icache.overall_miss_rate::total 0.039887 # miss rate for overall accesses 851system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.766477 # average ReadReq miss latency 852system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.766477 # average ReadReq miss latency 853system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency 854system.cpu0.icache.demand_avg_miss_latency::total 10351.766477 # average overall miss latency 855system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency 856system.cpu0.icache.overall_avg_miss_latency::total 10351.766477 # average overall miss latency 857system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 858system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 859system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 860system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 861system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 862system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 863system.cpu0.icache.fast_writes 0 # number of fast writes performed 864system.cpu0.icache.cache_copies 0 # number of cache copies performed 865system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9689087 # number of ReadReq MSHR misses 866system.cpu0.icache.ReadReq_mshr_misses::total 9689087 # number of ReadReq MSHR misses 867system.cpu0.icache.demand_mshr_misses::cpu0.inst 9689087 # number of demand (read+write) MSHR misses 868system.cpu0.icache.demand_mshr_misses::total 9689087 # number of demand (read+write) MSHR misses 869system.cpu0.icache.overall_mshr_misses::cpu0.inst 9689087 # number of overall MSHR misses 870system.cpu0.icache.overall_mshr_misses::total 9689087 # number of overall MSHR misses 871system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 872system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 873system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 874system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 875system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95454623000 # number of ReadReq MSHR miss cycles 876system.cpu0.icache.ReadReq_mshr_miss_latency::total 95454623000 # number of ReadReq MSHR miss cycles 877system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95454623000 # number of demand (read+write) MSHR miss cycles 878system.cpu0.icache.demand_mshr_miss_latency::total 95454623000 # number of demand (read+write) MSHR miss cycles 879system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95454623000 # number of overall MSHR miss cycles 880system.cpu0.icache.overall_mshr_miss_latency::total 95454623000 # number of overall MSHR miss cycles 881system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of ReadReq MSHR uncacheable cycles 882system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7413401000 # number of ReadReq MSHR uncacheable cycles 883system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of overall MSHR uncacheable cycles 884system.cpu0.icache.overall_mshr_uncacheable_latency::total 7413401000 # number of overall MSHR uncacheable cycles 885system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for ReadReq accesses 886system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039887 # mshr miss rate for ReadReq accesses 887system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for demand accesses 888system.cpu0.icache.demand_mshr_miss_rate::total 0.039887 # mshr miss rate for demand accesses 889system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for overall accesses 890system.cpu0.icache.overall_mshr_miss_rate::total 0.039887 # mshr miss rate for overall accesses 891system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average ReadReq mshr miss latency 892system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.766529 # average ReadReq mshr miss latency 893system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency 894system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency 895system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency 896system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency 897system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency 898system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency 899system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency 900system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency 901system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 902system.cpu0.l2cache.prefetcher.num_hwpf_issued 7463777 # number of hwpf issued 903system.cpu0.l2cache.prefetcher.pfIdentified 7463951 # number of prefetch candidates identified 904system.cpu0.l2cache.prefetcher.pfBufferHit 154 # number of redundant prefetches already in prefetch queue 905system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 906system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 907system.cpu0.l2cache.prefetcher.pfSpanPage 1020305 # number of prefetches not generated due to page crossing 908system.cpu0.l2cache.tags.replacements 2664787 # number of replacements 909system.cpu0.l2cache.tags.tagsinuse 15957.113648 # Cycle average of tags in use 910system.cpu0.l2cache.tags.total_refs 26864509 # Total number of references to valid blocks. 911system.cpu0.l2cache.tags.sampled_refs 2680682 # Sample count of references to valid blocks. 912system.cpu0.l2cache.tags.avg_refs 10.021520 # Average number of references to valid blocks. 913system.cpu0.l2cache.tags.warmup_cycle 38485430000 # Cycle when the warmup percentage was hit. 914system.cpu0.l2cache.tags.occ_blocks::writebacks 6872.215886 # Average occupied blocks per requestor 915system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 83.268968 # Average occupied blocks per requestor 916system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 86.677569 # Average occupied blocks per requestor 917system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4373.710312 # Average occupied blocks per requestor 918system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3617.876682 # Average occupied blocks per requestor 919system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 923.364231 # Average occupied blocks per requestor 920system.cpu0.l2cache.tags.occ_percent::writebacks 0.419447 # Average percentage of cache occupancy 921system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005082 # Average percentage of cache occupancy 922system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005290 # Average percentage of cache occupancy 923system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.266950 # Average percentage of cache occupancy 924system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.220818 # Average percentage of cache occupancy 925system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056358 # Average percentage of cache occupancy 926system.cpu0.l2cache.tags.occ_percent::total 0.973945 # Average percentage of cache occupancy 927system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1328 # Occupied blocks per task id 928system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id 929system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14509 # Occupied blocks per task id 930system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 565 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 693 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 52 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4763 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8150 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 382 # Occupied blocks per task id 942system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081055 # Percentage of cache occupancy per task id 943system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id 944system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885559 # Percentage of cache occupancy per task id 945system.cpu0.l2cache.tags.tag_accesses 513598249 # Number of tag accesses 946system.cpu0.l2cache.tags.data_accesses 513598249 # Number of data accesses 947system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 486721 # number of ReadReq hits 948system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 161483 # number of ReadReq hits 949system.cpu0.l2cache.ReadReq_hits::total 648204 # number of ReadReq hits 950system.cpu0.l2cache.Writeback_hits::writebacks 3758761 # number of Writeback hits 951system.cpu0.l2cache.Writeback_hits::total 3758761 # number of Writeback hits 952system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 96787 # number of UpgradeReq hits 953system.cpu0.l2cache.UpgradeReq_hits::total 96787 # number of UpgradeReq hits 954system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 34850 # number of SCUpgradeReq hits 955system.cpu0.l2cache.SCUpgradeReq_hits::total 34850 # number of SCUpgradeReq hits 956system.cpu0.l2cache.ReadExReq_hits::cpu0.data 870093 # number of ReadExReq hits 957system.cpu0.l2cache.ReadExReq_hits::total 870093 # number of ReadExReq hits 958system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8916496 # number of ReadCleanReq hits 959system.cpu0.l2cache.ReadCleanReq_hits::total 8916496 # number of ReadCleanReq hits 960system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2811099 # number of ReadSharedReq hits 961system.cpu0.l2cache.ReadSharedReq_hits::total 2811099 # number of ReadSharedReq hits 962system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 212338 # number of InvalidateReq hits 963system.cpu0.l2cache.InvalidateReq_hits::total 212338 # number of InvalidateReq hits 964system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 486721 # number of demand (read+write) hits 965system.cpu0.l2cache.demand_hits::cpu0.itb.walker 161483 # number of demand (read+write) hits 966system.cpu0.l2cache.demand_hits::cpu0.inst 8916496 # number of demand (read+write) hits 967system.cpu0.l2cache.demand_hits::cpu0.data 3681192 # number of demand (read+write) hits 968system.cpu0.l2cache.demand_hits::total 13245892 # number of demand (read+write) hits 969system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 486721 # number of overall hits 970system.cpu0.l2cache.overall_hits::cpu0.itb.walker 161483 # number of overall hits 971system.cpu0.l2cache.overall_hits::cpu0.inst 8916496 # number of overall hits 972system.cpu0.l2cache.overall_hits::cpu0.data 3681192 # number of overall hits 973system.cpu0.l2cache.overall_hits::total 13245892 # number of overall hits 974system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11149 # number of ReadReq misses 975system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7679 # number of ReadReq misses 976system.cpu0.l2cache.ReadReq_misses::total 18828 # number of ReadReq misses 977system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134429 # number of UpgradeReq misses 978system.cpu0.l2cache.UpgradeReq_misses::total 134429 # number of UpgradeReq misses 979system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 150813 # number of SCUpgradeReq misses 980system.cpu0.l2cache.SCUpgradeReq_misses::total 150813 # number of SCUpgradeReq misses 981system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 982system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 983system.cpu0.l2cache.ReadExReq_misses::cpu0.data 252885 # number of ReadExReq misses 984system.cpu0.l2cache.ReadExReq_misses::total 252885 # number of ReadExReq misses 985system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 772590 # number of ReadCleanReq misses 986system.cpu0.l2cache.ReadCleanReq_misses::total 772590 # number of ReadCleanReq misses 987system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 977962 # number of ReadSharedReq misses 988system.cpu0.l2cache.ReadSharedReq_misses::total 977962 # number of ReadSharedReq misses 989system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 573862 # number of InvalidateReq misses 990system.cpu0.l2cache.InvalidateReq_misses::total 573862 # number of InvalidateReq misses 991system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11149 # number of demand (read+write) misses 992system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7679 # number of demand (read+write) misses 993system.cpu0.l2cache.demand_misses::cpu0.inst 772590 # number of demand (read+write) misses 994system.cpu0.l2cache.demand_misses::cpu0.data 1230847 # number of demand (read+write) misses 995system.cpu0.l2cache.demand_misses::total 2022265 # number of demand (read+write) misses 996system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11149 # number of overall misses 997system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7679 # number of overall misses 998system.cpu0.l2cache.overall_misses::cpu0.inst 772590 # number of overall misses 999system.cpu0.l2cache.overall_misses::cpu0.data 1230847 # number of overall misses 1000system.cpu0.l2cache.overall_misses::total 2022265 # number of overall misses 1001system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 426258000 # number of ReadReq miss cycles 1002system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 324009000 # number of ReadReq miss cycles 1003system.cpu0.l2cache.ReadReq_miss_latency::total 750267000 # number of ReadReq miss cycles 1004system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 4100217500 # number of UpgradeReq miss cycles 1005system.cpu0.l2cache.UpgradeReq_miss_latency::total 4100217500 # number of UpgradeReq miss cycles 1006system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3583690499 # number of SCUpgradeReq miss cycles 1007system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3583690499 # number of SCUpgradeReq miss cycles 1008system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4385000 # number of SCUpgradeFailReq miss cycles 1009system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4385000 # number of SCUpgradeFailReq miss cycles 1010system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16205618499 # number of ReadExReq miss cycles 1011system.cpu0.l2cache.ReadExReq_miss_latency::total 16205618499 # number of ReadExReq miss cycles 1012system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27749596500 # number of ReadCleanReq miss cycles 1013system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27749596500 # number of ReadCleanReq miss cycles 1014system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 38364944997 # number of ReadSharedReq miss cycles 1015system.cpu0.l2cache.ReadSharedReq_miss_latency::total 38364944997 # number of ReadSharedReq miss cycles 1016system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67134826000 # number of InvalidateReq miss cycles 1017system.cpu0.l2cache.InvalidateReq_miss_latency::total 67134826000 # number of InvalidateReq miss cycles 1018system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 426258000 # number of demand (read+write) miss cycles 1019system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 324009000 # number of demand (read+write) miss cycles 1020system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27749596500 # number of demand (read+write) miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.data 54570563496 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::total 83070426996 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 426258000 # number of overall miss cycles 1024system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 324009000 # number of overall miss cycles 1025system.cpu0.l2cache.overall_miss_latency::cpu0.inst 27749596500 # number of overall miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.data 54570563496 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::total 83070426996 # number of overall miss cycles 1028system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 497870 # number of ReadReq accesses(hits+misses) 1029system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 169162 # number of ReadReq accesses(hits+misses) 1030system.cpu0.l2cache.ReadReq_accesses::total 667032 # number of ReadReq accesses(hits+misses) 1031system.cpu0.l2cache.Writeback_accesses::writebacks 3758761 # number of Writeback accesses(hits+misses) 1032system.cpu0.l2cache.Writeback_accesses::total 3758761 # number of Writeback accesses(hits+misses) 1033system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231216 # number of UpgradeReq accesses(hits+misses) 1034system.cpu0.l2cache.UpgradeReq_accesses::total 231216 # number of UpgradeReq accesses(hits+misses) 1035system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 185663 # number of SCUpgradeReq accesses(hits+misses) 1036system.cpu0.l2cache.SCUpgradeReq_accesses::total 185663 # number of SCUpgradeReq accesses(hits+misses) 1037system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1038system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1039system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1122978 # number of ReadExReq accesses(hits+misses) 1040system.cpu0.l2cache.ReadExReq_accesses::total 1122978 # number of ReadExReq accesses(hits+misses) 1041system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9689086 # number of ReadCleanReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadCleanReq_accesses::total 9689086 # number of ReadCleanReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3789061 # number of ReadSharedReq accesses(hits+misses) 1044system.cpu0.l2cache.ReadSharedReq_accesses::total 3789061 # number of ReadSharedReq accesses(hits+misses) 1045system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 786200 # number of InvalidateReq accesses(hits+misses) 1046system.cpu0.l2cache.InvalidateReq_accesses::total 786200 # number of InvalidateReq accesses(hits+misses) 1047system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 497870 # number of demand (read+write) accesses 1048system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 169162 # number of demand (read+write) accesses 1049system.cpu0.l2cache.demand_accesses::cpu0.inst 9689086 # number of demand (read+write) accesses 1050system.cpu0.l2cache.demand_accesses::cpu0.data 4912039 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::total 15268157 # number of demand (read+write) accesses 1052system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 497870 # number of overall (read+write) accesses 1053system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 169162 # number of overall (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::cpu0.inst 9689086 # number of overall (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.data 4912039 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::total 15268157 # number of overall (read+write) accesses 1057system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for ReadReq accesses 1058system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045394 # miss rate for ReadReq accesses 1059system.cpu0.l2cache.ReadReq_miss_rate::total 0.028227 # miss rate for ReadReq accesses 1060system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.581400 # miss rate for UpgradeReq accesses 1061system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.581400 # miss rate for UpgradeReq accesses 1062system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.812294 # miss rate for SCUpgradeReq accesses 1063system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.812294 # miss rate for SCUpgradeReq accesses 1064system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1065system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1066system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.225191 # miss rate for ReadExReq accesses 1067system.cpu0.l2cache.ReadExReq_miss_rate::total 0.225191 # miss rate for ReadExReq accesses 1068system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.079738 # miss rate for ReadCleanReq accesses 1069system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079738 # miss rate for ReadCleanReq accesses 1070system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.258101 # miss rate for ReadSharedReq accesses 1071system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.258101 # miss rate for ReadSharedReq accesses 1072system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729919 # miss rate for InvalidateReq accesses 1073system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729919 # miss rate for InvalidateReq accesses 1074system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for demand accesses 1075system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045394 # miss rate for demand accesses 1076system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079738 # miss rate for demand accesses 1077system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250578 # miss rate for demand accesses 1078system.cpu0.l2cache.demand_miss_rate::total 0.132450 # miss rate for demand accesses 1079system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for overall accesses 1080system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045394 # miss rate for overall accesses 1081system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079738 # miss rate for overall accesses 1082system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250578 # miss rate for overall accesses 1083system.cpu0.l2cache.overall_miss_rate::total 0.132450 # miss rate for overall accesses 1084system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average ReadReq miss latency 1085system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42194.165907 # average ReadReq miss latency 1086system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39848.470363 # average ReadReq miss latency 1087system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 30500.989370 # average UpgradeReq miss latency 1088system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 30500.989370 # average UpgradeReq miss latency 1089system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23762.477366 # average SCUpgradeReq miss latency 1090system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23762.477366 # average SCUpgradeReq miss latency 1091system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2192500 # average SCUpgradeFailReq miss latency 1092system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2192500 # average SCUpgradeFailReq miss latency 1093system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64082.956676 # average ReadExReq miss latency 1094system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64082.956676 # average ReadExReq miss latency 1095system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35917.623190 # average ReadCleanReq miss latency 1096system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35917.623190 # average ReadCleanReq miss latency 1097system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39229.484374 # average ReadSharedReq miss latency 1098system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39229.484374 # average ReadSharedReq miss latency 1099system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 116987.753153 # average InvalidateReq miss latency 1100system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 116987.753153 # average InvalidateReq miss latency 1101system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average overall miss latency 1102system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42194.165907 # average overall miss latency 1103system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35917.623190 # average overall miss latency 1104system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44335.781373 # average overall miss latency 1105system.cpu0.l2cache.demand_avg_miss_latency::total 41077.913625 # average overall miss latency 1106system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average overall miss latency 1107system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42194.165907 # average overall miss latency 1108system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35917.623190 # average overall miss latency 1109system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44335.781373 # average overall miss latency 1110system.cpu0.l2cache.overall_avg_miss_latency::total 41077.913625 # average overall miss latency 1111system.cpu0.l2cache.blocked_cycles::no_mshrs 189 # number of cycles access was blocked 1112system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1113system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1114system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1115system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 189 # average number of cycles each access was blocked 1116system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1117system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1118system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1119system.cpu0.l2cache.writebacks::writebacks 1318085 # number of writebacks 1120system.cpu0.l2cache.writebacks::total 1318085 # number of writebacks 1121system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1122system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 1123system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 1124system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5018 # number of ReadExReq MSHR hits 1125system.cpu0.l2cache.ReadExReq_mshr_hits::total 5018 # number of ReadExReq MSHR hits 1126system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits 1127system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 1128system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1141 # number of ReadSharedReq MSHR hits 1129system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1141 # number of ReadSharedReq MSHR hits 1130system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits 1131system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 1132system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1133system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 1134system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 1135system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6159 # number of demand (read+write) MSHR hits 1136system.cpu0.l2cache.demand_mshr_hits::total 6170 # number of demand (read+write) MSHR hits 1137system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1138system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 1139system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 1140system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6159 # number of overall MSHR hits 1141system.cpu0.l2cache.overall_mshr_hits::total 6170 # number of overall MSHR hits 1142system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11148 # number of ReadReq MSHR misses 1143system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7676 # number of ReadReq MSHR misses 1144system.cpu0.l2cache.ReadReq_mshr_misses::total 18824 # number of ReadReq MSHR misses 1145system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 109829 # number of CleanEvict MSHR misses 1146system.cpu0.l2cache.CleanEvict_mshr_misses::total 109829 # number of CleanEvict MSHR misses 1147system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 670532 # number of HardPFReq MSHR misses 1148system.cpu0.l2cache.HardPFReq_mshr_misses::total 670532 # number of HardPFReq MSHR misses 1149system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 134429 # number of UpgradeReq MSHR misses 1150system.cpu0.l2cache.UpgradeReq_mshr_misses::total 134429 # number of UpgradeReq MSHR misses 1151system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 150813 # number of SCUpgradeReq MSHR misses 1152system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 150813 # number of SCUpgradeReq MSHR misses 1153system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1154system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1155system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247867 # number of ReadExReq MSHR misses 1156system.cpu0.l2cache.ReadExReq_mshr_misses::total 247867 # number of ReadExReq MSHR misses 1157system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 772583 # number of ReadCleanReq MSHR misses 1158system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 772583 # number of ReadCleanReq MSHR misses 1159system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 976821 # number of ReadSharedReq MSHR misses 1160system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 976821 # number of ReadSharedReq MSHR misses 1161system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 573859 # number of InvalidateReq MSHR misses 1162system.cpu0.l2cache.InvalidateReq_mshr_misses::total 573859 # number of InvalidateReq MSHR misses 1163system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11148 # number of demand (read+write) MSHR misses 1164system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7676 # number of demand (read+write) MSHR misses 1165system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 772583 # number of demand (read+write) MSHR misses 1166system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1224688 # number of demand (read+write) MSHR misses 1167system.cpu0.l2cache.demand_mshr_misses::total 2016095 # number of demand (read+write) MSHR misses 1168system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11148 # number of overall MSHR misses 1169system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7676 # number of overall MSHR misses 1170system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 772583 # number of overall MSHR misses 1171system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1224688 # number of overall MSHR misses 1172system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 670532 # number of overall MSHR misses 1173system.cpu0.l2cache.overall_mshr_misses::total 2686627 # number of overall MSHR misses 1174system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 1175system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable 1176system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 66934 # number of ReadReq MSHR uncacheable 1177system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable 1178system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable 1179system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 1180system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses 1181system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 82416 # number of overall MSHR uncacheable misses 1182system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of ReadReq MSHR miss cycles 1183system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 277905000 # number of ReadReq MSHR miss cycles 1184system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 637268000 # number of ReadReq MSHR miss cycles 1185system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33195033631 # number of HardPFReq MSHR miss cycles 1186system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33195033631 # number of HardPFReq MSHR miss cycles 1187system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4709210494 # number of UpgradeReq MSHR miss cycles 1188system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4709210494 # number of UpgradeReq MSHR miss cycles 1189system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2870671499 # number of SCUpgradeReq MSHR miss cycles 1190system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2870671499 # number of SCUpgradeReq MSHR miss cycles 1191system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4013000 # number of SCUpgradeFailReq MSHR miss cycles 1192system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4013000 # number of SCUpgradeFailReq MSHR miss cycles 1193system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13996811499 # number of ReadExReq MSHR miss cycles 1194system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13996811499 # number of ReadExReq MSHR miss cycles 1195system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23113725500 # number of ReadCleanReq MSHR miss cycles 1196system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23113725500 # number of ReadCleanReq MSHR miss cycles 1197system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32421419997 # number of ReadSharedReq MSHR miss cycles 1198system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32421419997 # number of ReadSharedReq MSHR miss cycles 1199system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 63691409500 # number of InvalidateReq MSHR miss cycles 1200system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 63691409500 # number of InvalidateReq MSHR miss cycles 1201system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of demand (read+write) MSHR miss cycles 1202system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 277905000 # number of demand (read+write) MSHR miss cycles 1203system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23113725500 # number of demand (read+write) MSHR miss cycles 1204system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46418231496 # number of demand (read+write) MSHR miss cycles 1205system.cpu0.l2cache.demand_mshr_miss_latency::total 70169224996 # number of demand (read+write) MSHR miss cycles 1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of overall MSHR miss cycles 1207system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 277905000 # number of overall MSHR miss cycles 1208system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23113725500 # number of overall MSHR miss cycles 1209system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46418231496 # number of overall MSHR miss cycles 1210system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33195033631 # number of overall MSHR miss cycles 1211system.cpu0.l2cache.overall_mshr_miss_latency::total 103364258627 # number of overall MSHR miss cycles 1212system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of ReadReq MSHR uncacheable cycles 1213system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2327318500 # number of ReadReq MSHR uncacheable cycles 1214system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9322247500 # number of ReadReq MSHR uncacheable cycles 1215system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2417234500 # number of WriteReq MSHR uncacheable cycles 1216system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2417234500 # number of WriteReq MSHR uncacheable cycles 1217system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of overall MSHR uncacheable cycles 1218system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4744553000 # number of overall MSHR uncacheable cycles 1219system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11739482000 # number of overall MSHR uncacheable cycles 1220system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for ReadReq accesses 1221system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for ReadReq accesses 1222system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028221 # mshr miss rate for ReadReq accesses 1223system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1224system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1225system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1226system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1227system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.581400 # mshr miss rate for UpgradeReq accesses 1228system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.581400 # mshr miss rate for UpgradeReq accesses 1229system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.812294 # mshr miss rate for SCUpgradeReq accesses 1230system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.812294 # mshr miss rate for SCUpgradeReq accesses 1231system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1232system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1233system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220723 # mshr miss rate for ReadExReq accesses 1234system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220723 # mshr miss rate for ReadExReq accesses 1235system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for ReadCleanReq accesses 1236system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079737 # mshr miss rate for ReadCleanReq accesses 1237system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257800 # mshr miss rate for ReadSharedReq accesses 1238system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257800 # mshr miss rate for ReadSharedReq accesses 1239system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729915 # mshr miss rate for InvalidateReq accesses 1240system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729915 # mshr miss rate for InvalidateReq accesses 1241system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for demand accesses 1242system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for demand accesses 1243system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for demand accesses 1244system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for demand accesses 1245system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132046 # mshr miss rate for demand accesses 1246system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for overall accesses 1247system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for overall accesses 1248system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for overall accesses 1249system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for overall accesses 1250system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1251system.cpu0.l2cache.overall_mshr_miss_rate::total 0.175963 # mshr miss rate for overall accesses 1252system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average ReadReq mshr miss latency 1253system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average ReadReq mshr miss latency 1254system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33854.016150 # average ReadReq mshr miss latency 1255system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average HardPFReq mshr miss latency 1256system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49505.517456 # average HardPFReq mshr miss latency 1257system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35031.209739 # average UpgradeReq mshr miss latency 1258system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35031.209739 # average UpgradeReq mshr miss latency 1259system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19034.642232 # average SCUpgradeReq mshr miss latency 1260system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19034.642232 # average SCUpgradeReq mshr miss latency 1261system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 2006500 # average SCUpgradeFailReq mshr miss latency 1262system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2006500 # average SCUpgradeFailReq mshr miss latency 1263system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56469.039844 # average ReadExReq mshr miss latency 1264system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56469.039844 # average ReadExReq mshr miss latency 1265system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average ReadCleanReq mshr miss latency 1266system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29917.465826 # average ReadCleanReq mshr miss latency 1267system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33190.748353 # average ReadSharedReq mshr miss latency 1268system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.748353 # average ReadSharedReq mshr miss latency 1269system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 110987.907308 # average InvalidateReq mshr miss latency 1270system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 110987.907308 # average InvalidateReq mshr miss latency 1271system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency 1272system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency 1273system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency 1274system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency 1275system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34804.523098 # average overall mshr miss latency 1276system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency 1277system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency 1278system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency 1279system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency 1280system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average overall mshr miss latency 1281system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38473.617152 # average overall mshr miss latency 1282system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency 1283system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159132.888889 # average ReadReq mshr uncacheable latency 1284system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139275.218872 # average ReadReq mshr uncacheable latency 1285system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156131.927400 # average WriteReq mshr uncacheable latency 1286system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 156131.927400 # average WriteReq mshr uncacheable latency 1287system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency 1288system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157589.696748 # average overall mshr uncacheable latency 1289system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142441.783149 # average overall mshr uncacheable latency 1290system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1291system.cpu0.toL2Bus.snoop_filter.tot_requests 31422927 # Total number of requests made to the snoop filter. 1292system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16035788 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1293system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1294system.cpu0.toL2Bus.snoop_filter.tot_snoops 525852 # Total number of snoops made to the snoop filter. 1295system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 525836 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1296system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 16 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1297system.cpu0.toL2Bus.trans_dist::ReadReq 867706 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::ReadResp 14437095 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::WriteReq 15482 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::WriteResp 15482 # Transaction distribution 1301system.cpu0.toL2Bus.trans_dist::Writeback 5117037 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::CleanEvict 13614128 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::HardPFReq 885080 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::UpgradeReq 435794 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332763 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::UpgradeResp 479351 # Transaction distribution 1308system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution 1309system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 1310system.cpu0.toL2Bus.trans_dist::ReadExReq 1199260 # Transaction distribution 1311system.cpu0.toL2Bus.trans_dist::ReadExResp 1131949 # Transaction distribution 1312system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9689087 # Transaction distribution 1313system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4838943 # Transaction distribution 1314system.cpu0.toL2Bus.trans_dist::InvalidateReq 791881 # Transaction distribution 1315system.cpu0.toL2Bus.trans_dist::InvalidateResp 786200 # Transaction distribution 1316system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29170184 # Packet count per connected master and slave (bytes) 1317system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18058991 # Packet count per connected master and slave (bytes) 1318system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 372221 # Packet count per connected master and slave (bytes) 1319system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1095581 # Packet count per connected master and slave (bytes) 1320system.cpu0.toL2Bus.pkt_count::total 48696977 # Packet count per connected master and slave (bytes) 1321system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623449216 # Cumulative packet size per connected master and slave (bytes) 1322system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561436611 # Cumulative packet size per connected master and slave (bytes) 1323system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1353296 # Cumulative packet size per connected master and slave (bytes) 1324system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3982960 # Cumulative packet size per connected master and slave (bytes) 1325system.cpu0.toL2Bus.pkt_size::total 1190222083 # Cumulative packet size per connected master and slave (bytes) 1326system.cpu0.toL2Bus.snoops 6103291 # Total snoops (count) 1327system.cpu0.toL2Bus.snoop_fanout::samples 37789516 # Request fanout histogram 1328system.cpu0.toL2Bus.snoop_fanout::mean 0.022593 # Request fanout histogram 1329system.cpu0.toL2Bus.snoop_fanout::stdev 0.148604 # Request fanout histogram 1330system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1331system.cpu0.toL2Bus.snoop_fanout::0 36935768 97.74% 97.74% # Request fanout histogram 1332system.cpu0.toL2Bus.snoop_fanout::1 853732 2.26% 100.00% # Request fanout histogram 1333system.cpu0.toL2Bus.snoop_fanout::2 16 0.00% 100.00% # Request fanout histogram 1334system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1335system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1336system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1337system.cpu0.toL2Bus.snoop_fanout::total 37789516 # Request fanout histogram 1338system.cpu0.toL2Bus.reqLayer0.occupancy 19757899995 # Layer occupancy (ticks) 1339system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1340system.cpu0.toL2Bus.snoopLayer0.occupancy 181829197 # Layer occupancy (ticks) 1341system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1342system.cpu0.toL2Bus.respLayer0.occupancy 14614802569 # Layer occupancy (ticks) 1343system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1344system.cpu0.toL2Bus.respLayer1.occupancy 7994552968 # Layer occupancy (ticks) 1345system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1346system.cpu0.toL2Bus.respLayer2.occupancy 203085447 # Layer occupancy (ticks) 1347system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1348system.cpu0.toL2Bus.respLayer3.occupancy 597764892 # Layer occupancy (ticks) 1349system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1350system.cpu1.branchPred.lookups 123013748 # Number of BP lookups 1351system.cpu1.branchPred.condPredicted 87245709 # Number of conditional branches predicted 1352system.cpu1.branchPred.condIncorrect 5806283 # Number of conditional branches incorrect 1353system.cpu1.branchPred.BTBLookups 91467062 # Number of BTB lookups 1354system.cpu1.branchPred.BTBHits 66791634 # Number of BTB hits 1355system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1356system.cpu1.branchPred.BTBHitPct 73.022608 # BTB Hit Percentage 1357system.cpu1.branchPred.usedRAS 14491018 # Number of times the RAS was used to get a target. 1358system.cpu1.branchPred.RASInCorrect 994593 # Number of incorrect RAS predictions. 1359system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1360system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1361system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1362system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1363system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1364system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1365system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1366system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1367system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1368system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1369system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1370system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1371system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1372system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1373system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1374system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1375system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1376system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1377system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1378system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1379system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1380system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1381system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1382system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1383system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1384system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1385system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1386system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1387system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1388system.cpu1.dtb.walker.walks 261280 # Table walker walks requested 1389system.cpu1.dtb.walker.walksLong 261280 # Table walker walks initiated with long descriptors 1390system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8108 # Level at which table walker walks with long descriptors terminate 1391system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 72332 # Level at which table walker walks with long descriptors terminate 1392system.cpu1.dtb.walker.walkWaitTime::samples 261280 # Table walker wait (enqueue to first request) latency 1393system.cpu1.dtb.walker.walkWaitTime::0 261280 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1394system.cpu1.dtb.walker.walkWaitTime::total 261280 # Table walker wait (enqueue to first request) latency 1395system.cpu1.dtb.walker.walkCompletionTime::samples 80440 # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walkCompletionTime::mean 21205.221283 # Table walker service (enqueue to completion) latency 1397system.cpu1.dtb.walker.walkCompletionTime::gmean 19053.776737 # Table walker service (enqueue to completion) latency 1398system.cpu1.dtb.walker.walkCompletionTime::stdev 17699.176778 # Table walker service (enqueue to completion) latency 1399system.cpu1.dtb.walker.walkCompletionTime::0-65535 79639 99.00% 99.00% # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walkCompletionTime::65536-131071 177 0.22% 99.22% # Table walker service (enqueue to completion) latency 1401system.cpu1.dtb.walker.walkCompletionTime::131072-196607 525 0.65% 99.88% # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.90% # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walkCompletionTime::262144-327679 29 0.04% 99.94% # Table walker service (enqueue to completion) latency 1404system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.96% # Table walker service (enqueue to completion) latency 1405system.cpu1.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency 1406system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1407system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1408system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1409system.cpu1.dtb.walker.walkCompletionTime::total 80440 # Table walker service (enqueue to completion) latency 1410system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution 1411system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution 1412system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution 1413system.cpu1.dtb.walker.walkPageSizes::4K 72332 89.92% 89.92% # Table walker page sizes translated 1414system.cpu1.dtb.walker.walkPageSizes::2M 8108 10.08% 100.00% # Table walker page sizes translated 1415system.cpu1.dtb.walker.walkPageSizes::total 80440 # Table walker page sizes translated 1416system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261280 # Table walker requests started/completed, data/inst 1417system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1418system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261280 # Table walker requests started/completed, data/inst 1419system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 80440 # Table walker requests started/completed, data/inst 1420system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1421system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 80440 # Table walker requests started/completed, data/inst 1422system.cpu1.dtb.walker.walkRequestOrigin::total 341720 # Table walker requests started/completed, data/inst 1423system.cpu1.dtb.inst_hits 0 # ITB inst hits 1424system.cpu1.dtb.inst_misses 0 # ITB inst misses 1425system.cpu1.dtb.read_hits 79147380 # DTB read hits 1426system.cpu1.dtb.read_misses 216729 # DTB read misses 1427system.cpu1.dtb.write_hits 70165250 # DTB write hits 1428system.cpu1.dtb.write_misses 44551 # DTB write misses 1429system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1430system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1431system.cpu1.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID 1432system.cpu1.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID 1433system.cpu1.dtb.flush_entries 35978 # Number of entries that have been flushed from TLB 1434system.cpu1.dtb.align_faults 1622 # Number of TLB faults due to alignment restrictions 1435system.cpu1.dtb.prefetch_faults 8536 # Number of TLB faults due to prefetch 1436system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1437system.cpu1.dtb.perms_faults 11275 # Number of TLB faults due to permissions restrictions 1438system.cpu1.dtb.read_accesses 79364109 # DTB read accesses 1439system.cpu1.dtb.write_accesses 70209801 # DTB write accesses 1440system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1441system.cpu1.dtb.hits 149312630 # DTB hits 1442system.cpu1.dtb.misses 261280 # DTB misses 1443system.cpu1.dtb.accesses 149573910 # DTB accesses 1444system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1445system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1446system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1447system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1448system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1449system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1450system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1451system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1452system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1453system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1454system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1455system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1456system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1457system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1458system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1459system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1460system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1461system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1462system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1463system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1464system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1465system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1466system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1467system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1468system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1469system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1470system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1471system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1472system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1473system.cpu1.itb.walker.walks 64423 # Table walker walks requested 1474system.cpu1.itb.walker.walksLong 64423 # Table walker walks initiated with long descriptors 1475system.cpu1.itb.walker.walksLongTerminationLevel::Level2 649 # Level at which table walker walks with long descriptors terminate 1476system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55396 # Level at which table walker walks with long descriptors terminate 1477system.cpu1.itb.walker.walkWaitTime::samples 64423 # Table walker wait (enqueue to first request) latency 1478system.cpu1.itb.walker.walkWaitTime::0 64423 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1479system.cpu1.itb.walker.walkWaitTime::total 64423 # Table walker wait (enqueue to first request) latency 1480system.cpu1.itb.walker.walkCompletionTime::samples 56045 # Table walker service (enqueue to completion) latency 1481system.cpu1.itb.walker.walkCompletionTime::mean 23900.053528 # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::gmean 21358.293391 # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walkCompletionTime::stdev 20280.389435 # Table walker service (enqueue to completion) latency 1484system.cpu1.itb.walker.walkCompletionTime::0-65535 55251 98.58% 98.58% # Table walker service (enqueue to completion) latency 1485system.cpu1.itb.walker.walkCompletionTime::65536-131071 6 0.01% 98.59% # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::131072-196607 707 1.26% 99.86% # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::196608-262143 21 0.04% 99.89% # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walkCompletionTime::262144-327679 35 0.06% 99.96% # Table walker service (enqueue to completion) latency 1489system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency 1490system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 1491system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1492system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1493system.cpu1.itb.walker.walkCompletionTime::total 56045 # Table walker service (enqueue to completion) latency 1494system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution 1495system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution 1496system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution 1497system.cpu1.itb.walker.walkPageSizes::4K 55396 98.84% 98.84% # Table walker page sizes translated 1498system.cpu1.itb.walker.walkPageSizes::2M 649 1.16% 100.00% # Table walker page sizes translated 1499system.cpu1.itb.walker.walkPageSizes::total 56045 # Table walker page sizes translated 1500system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1501system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64423 # Table walker requests started/completed, data/inst 1502system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64423 # Table walker requests started/completed, data/inst 1503system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1504system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56045 # Table walker requests started/completed, data/inst 1505system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56045 # Table walker requests started/completed, data/inst 1506system.cpu1.itb.walker.walkRequestOrigin::total 120468 # Table walker requests started/completed, data/inst 1507system.cpu1.itb.inst_hits 219650463 # ITB inst hits 1508system.cpu1.itb.inst_misses 64423 # ITB inst misses 1509system.cpu1.itb.read_hits 0 # DTB read hits 1510system.cpu1.itb.read_misses 0 # DTB read misses 1511system.cpu1.itb.write_hits 0 # DTB write hits 1512system.cpu1.itb.write_misses 0 # DTB write misses 1513system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1514system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1515system.cpu1.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID 1516system.cpu1.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID 1517system.cpu1.itb.flush_entries 25468 # Number of entries that have been flushed from TLB 1518system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1519system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1520system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1521system.cpu1.itb.perms_faults 193837 # Number of TLB faults due to permissions restrictions 1522system.cpu1.itb.read_accesses 0 # DTB read accesses 1523system.cpu1.itb.write_accesses 0 # DTB write accesses 1524system.cpu1.itb.inst_accesses 219714886 # ITB inst accesses 1525system.cpu1.itb.hits 219650463 # DTB hits 1526system.cpu1.itb.misses 64423 # DTB misses 1527system.cpu1.itb.accesses 219714886 # DTB accesses 1528system.cpu1.numCycles 870330668 # number of cpu cycles simulated 1529system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1530system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1531system.cpu1.committedInsts 404507419 # Number of instructions committed 1532system.cpu1.committedOps 476442054 # Number of ops (including micro ops) committed 1533system.cpu1.discardedOps 42651509 # Number of ops (including micro ops) which were discarded before commit 1534system.cpu1.numFetchSuspends 4585 # Number of times Execute suspended instruction fetching 1535system.cpu1.quiesceCycles 94059012808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1536system.cpu1.cpi 2.151581 # CPI: cycles per instruction 1537system.cpu1.ipc 0.464774 # IPC: instructions per cycle 1538system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1539system.cpu1.kern.inst.quiesce 15419 # number of quiesce instructions executed 1540system.cpu1.tickCycles 657243105 # Number of cycles that the object actually ticked 1541system.cpu1.idleCycles 213087563 # Total number of cycles that the object has spent stopped 1542system.cpu1.dcache.tags.replacements 4754677 # number of replacements 1543system.cpu1.dcache.tags.tagsinuse 457.418304 # Cycle average of tags in use 1544system.cpu1.dcache.tags.total_refs 141978837 # Total number of references to valid blocks. 1545system.cpu1.dcache.tags.sampled_refs 4755187 # Sample count of references to valid blocks. 1546system.cpu1.dcache.tags.avg_refs 29.857677 # Average number of references to valid blocks. 1547system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit. 1548system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.418304 # Average occupied blocks per requestor 1549system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893395 # Average percentage of cache occupancy 1550system.cpu1.dcache.tags.occ_percent::total 0.893395 # Average percentage of cache occupancy 1551system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 1552system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 1553system.cpu1.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 1554system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 1555system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 1556system.cpu1.dcache.tags.tag_accesses 300818421 # Number of tag accesses 1557system.cpu1.dcache.tags.data_accesses 300818421 # Number of data accesses 1558system.cpu1.dcache.ReadReq_hits::cpu1.data 72673299 # number of ReadReq hits 1559system.cpu1.dcache.ReadReq_hits::total 72673299 # number of ReadReq hits 1560system.cpu1.dcache.WriteReq_hits::cpu1.data 65442912 # number of WriteReq hits 1561system.cpu1.dcache.WriteReq_hits::total 65442912 # number of WriteReq hits 1562system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235828 # number of SoftPFReq hits 1563system.cpu1.dcache.SoftPFReq_hits::total 235828 # number of SoftPFReq hits 1564system.cpu1.dcache.WriteLineReq_hits::cpu1.data 186972 # number of WriteLineReq hits 1565system.cpu1.dcache.WriteLineReq_hits::total 186972 # number of WriteLineReq hits 1566system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1517500 # number of LoadLockedReq hits 1567system.cpu1.dcache.LoadLockedReq_hits::total 1517500 # number of LoadLockedReq hits 1568system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1485570 # number of StoreCondReq hits 1569system.cpu1.dcache.StoreCondReq_hits::total 1485570 # number of StoreCondReq hits 1570system.cpu1.dcache.demand_hits::cpu1.data 138116211 # number of demand (read+write) hits 1571system.cpu1.dcache.demand_hits::total 138116211 # number of demand (read+write) hits 1572system.cpu1.dcache.overall_hits::cpu1.data 138352039 # number of overall hits 1573system.cpu1.dcache.overall_hits::total 138352039 # number of overall hits 1574system.cpu1.dcache.ReadReq_misses::cpu1.data 3009807 # number of ReadReq misses 1575system.cpu1.dcache.ReadReq_misses::total 3009807 # number of ReadReq misses 1576system.cpu1.dcache.WriteReq_misses::cpu1.data 2062772 # number of WriteReq misses 1577system.cpu1.dcache.WriteReq_misses::total 2062772 # number of WriteReq misses 1578system.cpu1.dcache.SoftPFReq_misses::cpu1.data 570106 # number of SoftPFReq misses 1579system.cpu1.dcache.SoftPFReq_misses::total 570106 # number of SoftPFReq misses 1580system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466745 # number of WriteLineReq misses 1581system.cpu1.dcache.WriteLineReq_misses::total 466745 # number of WriteLineReq misses 1582system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151961 # number of LoadLockedReq misses 1583system.cpu1.dcache.LoadLockedReq_misses::total 151961 # number of LoadLockedReq misses 1584system.cpu1.dcache.StoreCondReq_misses::cpu1.data 182125 # number of StoreCondReq misses 1585system.cpu1.dcache.StoreCondReq_misses::total 182125 # number of StoreCondReq misses 1586system.cpu1.dcache.demand_misses::cpu1.data 5072579 # number of demand (read+write) misses 1587system.cpu1.dcache.demand_misses::total 5072579 # number of demand (read+write) misses 1588system.cpu1.dcache.overall_misses::cpu1.data 5642685 # number of overall misses 1589system.cpu1.dcache.overall_misses::total 5642685 # number of overall misses 1590system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47626322500 # number of ReadReq miss cycles 1591system.cpu1.dcache.ReadReq_miss_latency::total 47626322500 # number of ReadReq miss cycles 1592system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41378134500 # number of WriteReq miss cycles 1593system.cpu1.dcache.WriteReq_miss_latency::total 41378134500 # number of WriteReq miss cycles 1594system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19926390000 # number of WriteLineReq miss cycles 1595system.cpu1.dcache.WriteLineReq_miss_latency::total 19926390000 # number of WriteLineReq miss cycles 1596system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2395499000 # number of LoadLockedReq miss cycles 1597system.cpu1.dcache.LoadLockedReq_miss_latency::total 2395499000 # number of LoadLockedReq miss cycles 1598system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4359715500 # number of StoreCondReq miss cycles 1599system.cpu1.dcache.StoreCondReq_miss_latency::total 4359715500 # number of StoreCondReq miss cycles 1600system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5890500 # number of StoreCondFailReq miss cycles 1601system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5890500 # number of StoreCondFailReq miss cycles 1602system.cpu1.dcache.demand_miss_latency::cpu1.data 89004457000 # number of demand (read+write) miss cycles 1603system.cpu1.dcache.demand_miss_latency::total 89004457000 # number of demand (read+write) miss cycles 1604system.cpu1.dcache.overall_miss_latency::cpu1.data 89004457000 # number of overall miss cycles 1605system.cpu1.dcache.overall_miss_latency::total 89004457000 # number of overall miss cycles 1606system.cpu1.dcache.ReadReq_accesses::cpu1.data 75683106 # number of ReadReq accesses(hits+misses) 1607system.cpu1.dcache.ReadReq_accesses::total 75683106 # number of ReadReq accesses(hits+misses) 1608system.cpu1.dcache.WriteReq_accesses::cpu1.data 67505684 # number of WriteReq accesses(hits+misses) 1609system.cpu1.dcache.WriteReq_accesses::total 67505684 # number of WriteReq accesses(hits+misses) 1610system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 805934 # number of SoftPFReq accesses(hits+misses) 1611system.cpu1.dcache.SoftPFReq_accesses::total 805934 # number of SoftPFReq accesses(hits+misses) 1612system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653717 # number of WriteLineReq accesses(hits+misses) 1613system.cpu1.dcache.WriteLineReq_accesses::total 653717 # number of WriteLineReq accesses(hits+misses) 1614system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1669461 # number of LoadLockedReq accesses(hits+misses) 1615system.cpu1.dcache.LoadLockedReq_accesses::total 1669461 # number of LoadLockedReq accesses(hits+misses) 1616system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1667695 # number of StoreCondReq accesses(hits+misses) 1617system.cpu1.dcache.StoreCondReq_accesses::total 1667695 # number of StoreCondReq accesses(hits+misses) 1618system.cpu1.dcache.demand_accesses::cpu1.data 143188790 # number of demand (read+write) accesses 1619system.cpu1.dcache.demand_accesses::total 143188790 # number of demand (read+write) accesses 1620system.cpu1.dcache.overall_accesses::cpu1.data 143994724 # number of overall (read+write) accesses 1621system.cpu1.dcache.overall_accesses::total 143994724 # number of overall (read+write) accesses 1622system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039769 # miss rate for ReadReq accesses 1623system.cpu1.dcache.ReadReq_miss_rate::total 0.039769 # miss rate for ReadReq accesses 1624system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030557 # miss rate for WriteReq accesses 1625system.cpu1.dcache.WriteReq_miss_rate::total 0.030557 # miss rate for WriteReq accesses 1626system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707385 # miss rate for SoftPFReq accesses 1627system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707385 # miss rate for SoftPFReq accesses 1628system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.713986 # miss rate for WriteLineReq accesses 1629system.cpu1.dcache.WriteLineReq_miss_rate::total 0.713986 # miss rate for WriteLineReq accesses 1630system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091024 # miss rate for LoadLockedReq accesses 1631system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091024 # miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109208 # miss rate for StoreCondReq accesses 1633system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109208 # miss rate for StoreCondReq accesses 1634system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035426 # miss rate for demand accesses 1635system.cpu1.dcache.demand_miss_rate::total 0.035426 # miss rate for demand accesses 1636system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039187 # miss rate for overall accesses 1637system.cpu1.dcache.overall_miss_rate::total 0.039187 # miss rate for overall accesses 1638system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15823.713115 # average ReadReq miss latency 1639system.cpu1.dcache.ReadReq_avg_miss_latency::total 15823.713115 # average ReadReq miss latency 1640system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20059.480398 # average WriteReq miss latency 1641system.cpu1.dcache.WriteReq_avg_miss_latency::total 20059.480398 # average WriteReq miss latency 1642system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42692.240945 # average WriteLineReq miss latency 1643system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42692.240945 # average WriteLineReq miss latency 1644system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15763.906529 # average LoadLockedReq miss latency 1645system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15763.906529 # average LoadLockedReq miss latency 1646system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23938.039808 # average StoreCondReq miss latency 1647system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23938.039808 # average StoreCondReq miss latency 1648system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1649system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1650system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17546.194352 # average overall miss latency 1651system.cpu1.dcache.demand_avg_miss_latency::total 17546.194352 # average overall miss latency 1652system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15773.422936 # average overall miss latency 1653system.cpu1.dcache.overall_avg_miss_latency::total 15773.422936 # average overall miss latency 1654system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1655system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1656system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1657system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1658system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1659system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1660system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1661system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1662system.cpu1.dcache.writebacks::writebacks 3093987 # number of writebacks 1663system.cpu1.dcache.writebacks::total 3093987 # number of writebacks 1664system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 330751 # number of ReadReq MSHR hits 1665system.cpu1.dcache.ReadReq_mshr_hits::total 330751 # number of ReadReq MSHR hits 1666system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 852033 # number of WriteReq MSHR hits 1667system.cpu1.dcache.WriteReq_mshr_hits::total 852033 # number of WriteReq MSHR hits 1668system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 101 # number of WriteLineReq MSHR hits 1669system.cpu1.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits 1670system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39295 # number of LoadLockedReq MSHR hits 1671system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39295 # number of LoadLockedReq MSHR hits 1672system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits 1673system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits 1674system.cpu1.dcache.demand_mshr_hits::cpu1.data 1182784 # number of demand (read+write) MSHR hits 1675system.cpu1.dcache.demand_mshr_hits::total 1182784 # number of demand (read+write) MSHR hits 1676system.cpu1.dcache.overall_mshr_hits::cpu1.data 1182784 # number of overall MSHR hits 1677system.cpu1.dcache.overall_mshr_hits::total 1182784 # number of overall MSHR hits 1678system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2679056 # number of ReadReq MSHR misses 1679system.cpu1.dcache.ReadReq_mshr_misses::total 2679056 # number of ReadReq MSHR misses 1680system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1210739 # number of WriteReq MSHR misses 1681system.cpu1.dcache.WriteReq_mshr_misses::total 1210739 # number of WriteReq MSHR misses 1682system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 569730 # number of SoftPFReq MSHR misses 1683system.cpu1.dcache.SoftPFReq_mshr_misses::total 569730 # number of SoftPFReq MSHR misses 1684system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466644 # number of WriteLineReq MSHR misses 1685system.cpu1.dcache.WriteLineReq_mshr_misses::total 466644 # number of WriteLineReq MSHR misses 1686system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 112666 # number of LoadLockedReq MSHR misses 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::total 112666 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 182078 # number of StoreCondReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::total 182078 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.demand_mshr_misses::cpu1.data 3889795 # number of demand (read+write) MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::total 3889795 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.overall_mshr_misses::cpu1.data 4459525 # number of overall MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::total 4459525 # number of overall MSHR misses 1694system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable 1695system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23510 # number of ReadReq MSHR uncacheable 1696system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable 1697system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable 1698system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses 1699system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46082 # number of overall MSHR uncacheable misses 1700system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38219808000 # number of ReadReq MSHR miss cycles 1701system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38219808000 # number of ReadReq MSHR miss cycles 1702system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24026284000 # number of WriteReq MSHR miss cycles 1703system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24026284000 # number of WriteReq MSHR miss cycles 1704system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13466616000 # number of SoftPFReq MSHR miss cycles 1705system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13466616000 # number of SoftPFReq MSHR miss cycles 1706system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19450050500 # number of WriteLineReq MSHR miss cycles 1707system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19450050500 # number of WriteLineReq MSHR miss cycles 1708system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1560972500 # number of LoadLockedReq MSHR miss cycles 1709system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1560972500 # number of LoadLockedReq MSHR miss cycles 1710system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174804000 # number of StoreCondReq MSHR miss cycles 1711system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174804000 # number of StoreCondReq MSHR miss cycles 1712system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5498500 # number of StoreCondFailReq MSHR miss cycles 1713system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5498500 # number of StoreCondFailReq MSHR miss cycles 1714system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62246092000 # number of demand (read+write) MSHR miss cycles 1715system.cpu1.dcache.demand_mshr_miss_latency::total 62246092000 # number of demand (read+write) MSHR miss cycles 1716system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75712708000 # number of overall MSHR miss cycles 1717system.cpu1.dcache.overall_mshr_miss_latency::total 75712708000 # number of overall MSHR miss cycles 1718system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4058237000 # number of ReadReq MSHR uncacheable cycles 1719system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4058237000 # number of ReadReq MSHR uncacheable cycles 1720system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3938068000 # number of WriteReq MSHR uncacheable cycles 1721system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3938068000 # number of WriteReq MSHR uncacheable cycles 1722system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7996305000 # number of overall MSHR uncacheable cycles 1723system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7996305000 # number of overall MSHR uncacheable cycles 1724system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035398 # mshr miss rate for ReadReq accesses 1725system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses 1726system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017935 # mshr miss rate for WriteReq accesses 1727system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017935 # mshr miss rate for WriteReq accesses 1728system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706919 # mshr miss rate for SoftPFReq accesses 1729system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706919 # mshr miss rate for SoftPFReq accesses 1730system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.713832 # mshr miss rate for WriteLineReq accesses 1731system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.713832 # mshr miss rate for WriteLineReq accesses 1732system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067486 # mshr miss rate for LoadLockedReq accesses 1733system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067486 # mshr miss rate for LoadLockedReq accesses 1734system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109179 # mshr miss rate for StoreCondReq accesses 1735system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109179 # mshr miss rate for StoreCondReq accesses 1736system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027165 # mshr miss rate for demand accesses 1737system.cpu1.dcache.demand_mshr_miss_rate::total 0.027165 # mshr miss rate for demand accesses 1738system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030970 # mshr miss rate for overall accesses 1739system.cpu1.dcache.overall_mshr_miss_rate::total 0.030970 # mshr miss rate for overall accesses 1740system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14266.147479 # average ReadReq mshr miss latency 1741system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14266.147479 # average ReadReq mshr miss latency 1742system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19844.313267 # average WriteReq mshr miss latency 1743system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19844.313267 # average WriteReq mshr miss latency 1744system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23636.838502 # average SoftPFReq mshr miss latency 1745system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23636.838502 # average SoftPFReq mshr miss latency 1746system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41680.704134 # average WriteLineReq mshr miss latency 1747system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41680.704134 # average WriteLineReq mshr miss latency 1748system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13854.867484 # average LoadLockedReq mshr miss latency 1749system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13854.867484 # average LoadLockedReq mshr miss latency 1750system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22928.656949 # average StoreCondReq mshr miss latency 1751system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22928.656949 # average StoreCondReq mshr miss latency 1752system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1753system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1754system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16002.409381 # average overall mshr miss latency 1755system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16002.409381 # average overall mshr miss latency 1756system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16977.751666 # average overall mshr miss latency 1757system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16977.751666 # average overall mshr miss latency 1758system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172617.481923 # average ReadReq mshr uncacheable latency 1759system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172617.481923 # average ReadReq mshr uncacheable latency 1760system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174466.950204 # average WriteReq mshr uncacheable latency 1761system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174466.950204 # average WriteReq mshr uncacheable latency 1762system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173523.393082 # average overall mshr uncacheable latency 1763system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173523.393082 # average overall mshr uncacheable latency 1764system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1765system.cpu1.icache.tags.replacements 8864427 # number of replacements 1766system.cpu1.icache.tags.tagsinuse 506.853262 # Cycle average of tags in use 1767system.cpu1.icache.tags.total_refs 210585390 # Total number of references to valid blocks. 1768system.cpu1.icache.tags.sampled_refs 8864939 # Sample count of references to valid blocks. 1769system.cpu1.icache.tags.avg_refs 23.754861 # Average number of references to valid blocks. 1770system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit. 1771system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.853262 # Average occupied blocks per requestor 1772system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989948 # Average percentage of cache occupancy 1773system.cpu1.icache.tags.occ_percent::total 0.989948 # Average percentage of cache occupancy 1774system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1775system.cpu1.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 1776system.cpu1.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id 1777system.cpu1.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id 1778system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1779system.cpu1.icache.tags.tag_accesses 447765626 # Number of tag accesses 1780system.cpu1.icache.tags.data_accesses 447765626 # Number of data accesses 1781system.cpu1.icache.ReadReq_hits::cpu1.inst 210585390 # number of ReadReq hits 1782system.cpu1.icache.ReadReq_hits::total 210585390 # number of ReadReq hits 1783system.cpu1.icache.demand_hits::cpu1.inst 210585390 # number of demand (read+write) hits 1784system.cpu1.icache.demand_hits::total 210585390 # number of demand (read+write) hits 1785system.cpu1.icache.overall_hits::cpu1.inst 210585390 # number of overall hits 1786system.cpu1.icache.overall_hits::total 210585390 # number of overall hits 1787system.cpu1.icache.ReadReq_misses::cpu1.inst 8864949 # number of ReadReq misses 1788system.cpu1.icache.ReadReq_misses::total 8864949 # number of ReadReq misses 1789system.cpu1.icache.demand_misses::cpu1.inst 8864949 # number of demand (read+write) misses 1790system.cpu1.icache.demand_misses::total 8864949 # number of demand (read+write) misses 1791system.cpu1.icache.overall_misses::cpu1.inst 8864949 # number of overall misses 1792system.cpu1.icache.overall_misses::total 8864949 # number of overall misses 1793system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93186086500 # number of ReadReq miss cycles 1794system.cpu1.icache.ReadReq_miss_latency::total 93186086500 # number of ReadReq miss cycles 1795system.cpu1.icache.demand_miss_latency::cpu1.inst 93186086500 # number of demand (read+write) miss cycles 1796system.cpu1.icache.demand_miss_latency::total 93186086500 # number of demand (read+write) miss cycles 1797system.cpu1.icache.overall_miss_latency::cpu1.inst 93186086500 # number of overall miss cycles 1798system.cpu1.icache.overall_miss_latency::total 93186086500 # number of overall miss cycles 1799system.cpu1.icache.ReadReq_accesses::cpu1.inst 219450339 # number of ReadReq accesses(hits+misses) 1800system.cpu1.icache.ReadReq_accesses::total 219450339 # number of ReadReq accesses(hits+misses) 1801system.cpu1.icache.demand_accesses::cpu1.inst 219450339 # number of demand (read+write) accesses 1802system.cpu1.icache.demand_accesses::total 219450339 # number of demand (read+write) accesses 1803system.cpu1.icache.overall_accesses::cpu1.inst 219450339 # number of overall (read+write) accesses 1804system.cpu1.icache.overall_accesses::total 219450339 # number of overall (read+write) accesses 1805system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.040396 # miss rate for ReadReq accesses 1806system.cpu1.icache.ReadReq_miss_rate::total 0.040396 # miss rate for ReadReq accesses 1807system.cpu1.icache.demand_miss_rate::cpu1.inst 0.040396 # miss rate for demand accesses 1808system.cpu1.icache.demand_miss_rate::total 0.040396 # miss rate for demand accesses 1809system.cpu1.icache.overall_miss_rate::cpu1.inst 0.040396 # miss rate for overall accesses 1810system.cpu1.icache.overall_miss_rate::total 0.040396 # miss rate for overall accesses 1811system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10511.745358 # average ReadReq miss latency 1812system.cpu1.icache.ReadReq_avg_miss_latency::total 10511.745358 # average ReadReq miss latency 1813system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency 1814system.cpu1.icache.demand_avg_miss_latency::total 10511.745358 # average overall miss latency 1815system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency 1816system.cpu1.icache.overall_avg_miss_latency::total 10511.745358 # average overall miss latency 1817system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1818system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1819system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1820system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1821system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1822system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1823system.cpu1.icache.fast_writes 0 # number of fast writes performed 1824system.cpu1.icache.cache_copies 0 # number of cache copies performed 1825system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8864949 # number of ReadReq MSHR misses 1826system.cpu1.icache.ReadReq_mshr_misses::total 8864949 # number of ReadReq MSHR misses 1827system.cpu1.icache.demand_mshr_misses::cpu1.inst 8864949 # number of demand (read+write) MSHR misses 1828system.cpu1.icache.demand_mshr_misses::total 8864949 # number of demand (read+write) MSHR misses 1829system.cpu1.icache.overall_mshr_misses::cpu1.inst 8864949 # number of overall MSHR misses 1830system.cpu1.icache.overall_mshr_misses::total 8864949 # number of overall MSHR misses 1831system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 1832system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable 1833system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 1834system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses 1835system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88753612500 # number of ReadReq MSHR miss cycles 1836system.cpu1.icache.ReadReq_mshr_miss_latency::total 88753612500 # number of ReadReq MSHR miss cycles 1837system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88753612500 # number of demand (read+write) MSHR miss cycles 1838system.cpu1.icache.demand_mshr_miss_latency::total 88753612500 # number of demand (read+write) MSHR miss cycles 1839system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88753612500 # number of overall MSHR miss cycles 1840system.cpu1.icache.overall_mshr_miss_latency::total 88753612500 # number of overall MSHR miss cycles 1841system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12520000 # number of ReadReq MSHR uncacheable cycles 1842system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12520000 # number of ReadReq MSHR uncacheable cycles 1843system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12520000 # number of overall MSHR uncacheable cycles 1844system.cpu1.icache.overall_mshr_uncacheable_latency::total 12520000 # number of overall MSHR uncacheable cycles 1845system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for ReadReq accesses 1846system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.040396 # mshr miss rate for ReadReq accesses 1847system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for demand accesses 1848system.cpu1.icache.demand_mshr_miss_rate::total 0.040396 # mshr miss rate for demand accesses 1849system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for overall accesses 1850system.cpu1.icache.overall_mshr_miss_rate::total 0.040396 # mshr miss rate for overall accesses 1851system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average ReadReq mshr miss latency 1852system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10011.745414 # average ReadReq mshr miss latency 1853system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency 1854system.cpu1.icache.demand_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency 1855system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency 1856system.cpu1.icache.overall_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency 1857system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency 1858system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency 1859system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency 1860system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency 1861system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1862system.cpu1.l2cache.prefetcher.num_hwpf_issued 6449392 # number of hwpf issued 1863system.cpu1.l2cache.prefetcher.pfIdentified 6450426 # number of prefetch candidates identified 1864system.cpu1.l2cache.prefetcher.pfBufferHit 905 # number of redundant prefetches already in prefetch queue 1865system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1866system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1867system.cpu1.l2cache.prefetcher.pfSpanPage 802102 # number of prefetches not generated due to page crossing 1868system.cpu1.l2cache.tags.replacements 2183837 # number of replacements 1869system.cpu1.l2cache.tags.tagsinuse 13560.981052 # Cycle average of tags in use 1870system.cpu1.l2cache.tags.total_refs 24336260 # Total number of references to valid blocks. 1871system.cpu1.l2cache.tags.sampled_refs 2199514 # Sample count of references to valid blocks. 1872system.cpu1.l2cache.tags.avg_refs 11.064381 # Average number of references to valid blocks. 1873system.cpu1.l2cache.tags.warmup_cycle 9986977778000 # Cycle when the warmup percentage was hit. 1874system.cpu1.l2cache.tags.occ_blocks::writebacks 3995.301083 # Average occupied blocks per requestor 1875system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.705175 # Average occupied blocks per requestor 1876system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.813454 # Average occupied blocks per requestor 1877system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5399.423450 # Average occupied blocks per requestor 1878system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3183.311357 # Average occupied blocks per requestor 1879system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 849.426534 # Average occupied blocks per requestor 1880system.cpu1.l2cache.tags.occ_percent::writebacks 0.243854 # Average percentage of cache occupancy 1881system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004132 # Average percentage of cache occupancy 1882system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004017 # Average percentage of cache occupancy 1883system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.329555 # Average percentage of cache occupancy 1884system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194294 # Average percentage of cache occupancy 1885system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051845 # Average percentage of cache occupancy 1886system.cpu1.l2cache.tags.occ_percent::total 0.827697 # Average percentage of cache occupancy 1887system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1064 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14535 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id 1891system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 92 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 248 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 600 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 111 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 33 # Occupied blocks per task id 1899system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 1900system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 1901system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 692 # Occupied blocks per task id 1902system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4987 # Occupied blocks per task id 1903system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7639 # Occupied blocks per task id 1904system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1109 # Occupied blocks per task id 1905system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064941 # Percentage of cache occupancy per task id 1906system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id 1907system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.887146 # Percentage of cache occupancy per task id 1908system.cpu1.l2cache.tags.tag_accesses 457590280 # Number of tag accesses 1909system.cpu1.l2cache.tags.data_accesses 457590280 # Number of data accesses 1910system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 449487 # number of ReadReq hits 1911system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151613 # number of ReadReq hits 1912system.cpu1.l2cache.ReadReq_hits::total 601100 # number of ReadReq hits 1913system.cpu1.l2cache.Writeback_hits::writebacks 3093985 # number of Writeback hits 1914system.cpu1.l2cache.Writeback_hits::total 3093985 # number of Writeback hits 1915system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 65506 # number of UpgradeReq hits 1916system.cpu1.l2cache.UpgradeReq_hits::total 65506 # number of UpgradeReq hits 1917system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33165 # number of SCUpgradeReq hits 1918system.cpu1.l2cache.SCUpgradeReq_hits::total 33165 # number of SCUpgradeReq hits 1919system.cpu1.l2cache.ReadExReq_hits::cpu1.data 791344 # number of ReadExReq hits 1920system.cpu1.l2cache.ReadExReq_hits::total 791344 # number of ReadExReq hits 1921system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8112196 # number of ReadCleanReq hits 1922system.cpu1.l2cache.ReadCleanReq_hits::total 8112196 # number of ReadCleanReq hits 1923system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2464747 # number of ReadSharedReq hits 1924system.cpu1.l2cache.ReadSharedReq_hits::total 2464747 # number of ReadSharedReq hits 1925system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 204016 # number of InvalidateReq hits 1926system.cpu1.l2cache.InvalidateReq_hits::total 204016 # number of InvalidateReq hits 1927system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 449487 # number of demand (read+write) hits 1928system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151613 # number of demand (read+write) hits 1929system.cpu1.l2cache.demand_hits::cpu1.inst 8112196 # number of demand (read+write) hits 1930system.cpu1.l2cache.demand_hits::cpu1.data 3256091 # number of demand (read+write) hits 1931system.cpu1.l2cache.demand_hits::total 11969387 # number of demand (read+write) hits 1932system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 449487 # number of overall hits 1933system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151613 # number of overall hits 1934system.cpu1.l2cache.overall_hits::cpu1.inst 8112196 # number of overall hits 1935system.cpu1.l2cache.overall_hits::cpu1.data 3256091 # number of overall hits 1936system.cpu1.l2cache.overall_hits::total 11969387 # number of overall hits 1937system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10587 # number of ReadReq misses 1938system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7678 # number of ReadReq misses 1939system.cpu1.l2cache.ReadReq_misses::total 18265 # number of ReadReq misses 1940system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 126676 # number of UpgradeReq misses 1941system.cpu1.l2cache.UpgradeReq_misses::total 126676 # number of UpgradeReq misses 1942system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 148906 # number of SCUpgradeReq misses 1943system.cpu1.l2cache.SCUpgradeReq_misses::total 148906 # number of SCUpgradeReq misses 1944system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 1945system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1946system.cpu1.l2cache.ReadExReq_misses::cpu1.data 229716 # number of ReadExReq misses 1947system.cpu1.l2cache.ReadExReq_misses::total 229716 # number of ReadExReq misses 1948system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 752753 # number of ReadCleanReq misses 1949system.cpu1.l2cache.ReadCleanReq_misses::total 752753 # number of ReadCleanReq misses 1950system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 896376 # number of ReadSharedReq misses 1951system.cpu1.l2cache.ReadSharedReq_misses::total 896376 # number of ReadSharedReq misses 1952system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 260955 # number of InvalidateReq misses 1953system.cpu1.l2cache.InvalidateReq_misses::total 260955 # number of InvalidateReq misses 1954system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10587 # number of demand (read+write) misses 1955system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7678 # number of demand (read+write) misses 1956system.cpu1.l2cache.demand_misses::cpu1.inst 752753 # number of demand (read+write) misses 1957system.cpu1.l2cache.demand_misses::cpu1.data 1126092 # number of demand (read+write) misses 1958system.cpu1.l2cache.demand_misses::total 1897110 # number of demand (read+write) misses 1959system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10587 # number of overall misses 1960system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7678 # number of overall misses 1961system.cpu1.l2cache.overall_misses::cpu1.inst 752753 # number of overall misses 1962system.cpu1.l2cache.overall_misses::cpu1.data 1126092 # number of overall misses 1963system.cpu1.l2cache.overall_misses::total 1897110 # number of overall misses 1964system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 399086500 # number of ReadReq miss cycles 1965system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 314156000 # number of ReadReq miss cycles 1966system.cpu1.l2cache.ReadReq_miss_latency::total 713242500 # number of ReadReq miss cycles 1967system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3920313500 # number of UpgradeReq miss cycles 1968system.cpu1.l2cache.UpgradeReq_miss_latency::total 3920313500 # number of UpgradeReq miss cycles 1969system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3517664000 # number of SCUpgradeReq miss cycles 1970system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3517664000 # number of SCUpgradeReq miss cycles 1971system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5390999 # number of SCUpgradeFailReq miss cycles 1972system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5390999 # number of SCUpgradeFailReq miss cycles 1973system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11586003000 # number of ReadExReq miss cycles 1974system.cpu1.l2cache.ReadExReq_miss_latency::total 11586003000 # number of ReadExReq miss cycles 1975system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 27103959000 # number of ReadCleanReq miss cycles 1976system.cpu1.l2cache.ReadCleanReq_miss_latency::total 27103959000 # number of ReadCleanReq miss cycles 1977system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32012190991 # number of ReadSharedReq miss cycles 1978system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32012190991 # number of ReadSharedReq miss cycles 1979system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17327350500 # number of InvalidateReq miss cycles 1980system.cpu1.l2cache.InvalidateReq_miss_latency::total 17327350500 # number of InvalidateReq miss cycles 1981system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 399086500 # number of demand (read+write) miss cycles 1982system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 314156000 # number of demand (read+write) miss cycles 1983system.cpu1.l2cache.demand_miss_latency::cpu1.inst 27103959000 # number of demand (read+write) miss cycles 1984system.cpu1.l2cache.demand_miss_latency::cpu1.data 43598193991 # number of demand (read+write) miss cycles 1985system.cpu1.l2cache.demand_miss_latency::total 71415395491 # number of demand (read+write) miss cycles 1986system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 399086500 # number of overall miss cycles 1987system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 314156000 # number of overall miss cycles 1988system.cpu1.l2cache.overall_miss_latency::cpu1.inst 27103959000 # number of overall miss cycles 1989system.cpu1.l2cache.overall_miss_latency::cpu1.data 43598193991 # number of overall miss cycles 1990system.cpu1.l2cache.overall_miss_latency::total 71415395491 # number of overall miss cycles 1991system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 460074 # number of ReadReq accesses(hits+misses) 1992system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159291 # number of ReadReq accesses(hits+misses) 1993system.cpu1.l2cache.ReadReq_accesses::total 619365 # number of ReadReq accesses(hits+misses) 1994system.cpu1.l2cache.Writeback_accesses::writebacks 3093985 # number of Writeback accesses(hits+misses) 1995system.cpu1.l2cache.Writeback_accesses::total 3093985 # number of Writeback accesses(hits+misses) 1996system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 192182 # number of UpgradeReq accesses(hits+misses) 1997system.cpu1.l2cache.UpgradeReq_accesses::total 192182 # number of UpgradeReq accesses(hits+misses) 1998system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 182071 # number of SCUpgradeReq accesses(hits+misses) 1999system.cpu1.l2cache.SCUpgradeReq_accesses::total 182071 # number of SCUpgradeReq accesses(hits+misses) 2000system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 2001system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 2002system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1021060 # number of ReadExReq accesses(hits+misses) 2003system.cpu1.l2cache.ReadExReq_accesses::total 1021060 # number of ReadExReq accesses(hits+misses) 2004system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8864949 # number of ReadCleanReq accesses(hits+misses) 2005system.cpu1.l2cache.ReadCleanReq_accesses::total 8864949 # number of ReadCleanReq accesses(hits+misses) 2006system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3361123 # number of ReadSharedReq accesses(hits+misses) 2007system.cpu1.l2cache.ReadSharedReq_accesses::total 3361123 # number of ReadSharedReq accesses(hits+misses) 2008system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 464971 # number of InvalidateReq accesses(hits+misses) 2009system.cpu1.l2cache.InvalidateReq_accesses::total 464971 # number of InvalidateReq accesses(hits+misses) 2010system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 460074 # number of demand (read+write) accesses 2011system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159291 # number of demand (read+write) accesses 2012system.cpu1.l2cache.demand_accesses::cpu1.inst 8864949 # number of demand (read+write) accesses 2013system.cpu1.l2cache.demand_accesses::cpu1.data 4382183 # number of demand (read+write) accesses 2014system.cpu1.l2cache.demand_accesses::total 13866497 # number of demand (read+write) accesses 2015system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 460074 # number of overall (read+write) accesses 2016system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159291 # number of overall (read+write) accesses 2017system.cpu1.l2cache.overall_accesses::cpu1.inst 8864949 # number of overall (read+write) accesses 2018system.cpu1.l2cache.overall_accesses::cpu1.data 4382183 # number of overall (read+write) accesses 2019system.cpu1.l2cache.overall_accesses::total 13866497 # number of overall (read+write) accesses 2020system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for ReadReq accesses 2021system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048201 # miss rate for ReadReq accesses 2022system.cpu1.l2cache.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses 2023system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.659146 # miss rate for UpgradeReq accesses 2024system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.659146 # miss rate for UpgradeReq accesses 2025system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.817846 # miss rate for SCUpgradeReq accesses 2026system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.817846 # miss rate for SCUpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2028system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2029system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224978 # miss rate for ReadExReq accesses 2030system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224978 # miss rate for ReadExReq accesses 2031system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.084913 # miss rate for ReadCleanReq accesses 2032system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.084913 # miss rate for ReadCleanReq accesses 2033system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.266689 # miss rate for ReadSharedReq accesses 2034system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.266689 # miss rate for ReadSharedReq accesses 2035system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.561229 # miss rate for InvalidateReq accesses 2036system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.561229 # miss rate for InvalidateReq accesses 2037system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for demand accesses 2038system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048201 # miss rate for demand accesses 2039system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.084913 # miss rate for demand accesses 2040system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256971 # miss rate for demand accesses 2041system.cpu1.l2cache.demand_miss_rate::total 0.136812 # miss rate for demand accesses 2042system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for overall accesses 2043system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048201 # miss rate for overall accesses 2044system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.084913 # miss rate for overall accesses 2045system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256971 # miss rate for overall accesses 2046system.cpu1.l2cache.overall_miss_rate::total 0.136812 # miss rate for overall accesses 2047system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average ReadReq miss latency 2048system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40916.384475 # average ReadReq miss latency 2049system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39049.685190 # average ReadReq miss latency 2050system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30947.563074 # average UpgradeReq miss latency 2051system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30947.563074 # average UpgradeReq miss latency 2052system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23623.386566 # average SCUpgradeReq miss latency 2053system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23623.386566 # average SCUpgradeReq miss latency 2054system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 770142.714286 # average SCUpgradeFailReq miss latency 2055system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 770142.714286 # average SCUpgradeFailReq miss latency 2056system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50436.203834 # average ReadExReq miss latency 2057system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50436.203834 # average ReadExReq miss latency 2058system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36006.444345 # average ReadCleanReq miss latency 2059system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36006.444345 # average ReadCleanReq miss latency 2060system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35712.905066 # average ReadSharedReq miss latency 2061system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35712.905066 # average ReadSharedReq miss latency 2062system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 66399.764327 # average InvalidateReq miss latency 2063system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 66399.764327 # average InvalidateReq miss latency 2064system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average overall miss latency 2065system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40916.384475 # average overall miss latency 2066system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36006.444345 # average overall miss latency 2067system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38716.369525 # average overall miss latency 2068system.cpu1.l2cache.demand_avg_miss_latency::total 37644.309234 # average overall miss latency 2069system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average overall miss latency 2070system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40916.384475 # average overall miss latency 2071system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36006.444345 # average overall miss latency 2072system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38716.369525 # average overall miss latency 2073system.cpu1.l2cache.overall_avg_miss_latency::total 37644.309234 # average overall miss latency 2074system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2075system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2076system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2077system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2078system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2079system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2080system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2081system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2082system.cpu1.l2cache.writebacks::writebacks 895073 # number of writebacks 2083system.cpu1.l2cache.writebacks::total 895073 # number of writebacks 2084system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits 2085system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2086system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4757 # number of ReadExReq MSHR hits 2087system.cpu1.l2cache.ReadExReq_mshr_hits::total 4757 # number of ReadExReq MSHR hits 2088system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits 2089system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 2090system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1267 # number of ReadSharedReq MSHR hits 2091system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1267 # number of ReadSharedReq MSHR hits 2092system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits 2093system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 2094system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits 2095system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits 2096system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6024 # number of demand (read+write) MSHR hits 2097system.cpu1.l2cache.demand_mshr_hits::total 6030 # number of demand (read+write) MSHR hits 2098system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits 2099system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits 2100system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6024 # number of overall MSHR hits 2101system.cpu1.l2cache.overall_mshr_hits::total 6030 # number of overall MSHR hits 2102system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10587 # number of ReadReq MSHR misses 2103system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7677 # number of ReadReq MSHR misses 2104system.cpu1.l2cache.ReadReq_mshr_misses::total 18264 # number of ReadReq MSHR misses 2105system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104448 # number of CleanEvict MSHR misses 2106system.cpu1.l2cache.CleanEvict_mshr_misses::total 104448 # number of CleanEvict MSHR misses 2107system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 626506 # number of HardPFReq MSHR misses 2108system.cpu1.l2cache.HardPFReq_mshr_misses::total 626506 # number of HardPFReq MSHR misses 2109system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 126676 # number of UpgradeReq MSHR misses 2110system.cpu1.l2cache.UpgradeReq_mshr_misses::total 126676 # number of UpgradeReq MSHR misses 2111system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 148906 # number of SCUpgradeReq MSHR misses 2112system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 148906 # number of SCUpgradeReq MSHR misses 2113system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses 2114system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 2115system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 224959 # number of ReadExReq MSHR misses 2116system.cpu1.l2cache.ReadExReq_mshr_misses::total 224959 # number of ReadExReq MSHR misses 2117system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 752748 # number of ReadCleanReq MSHR misses 2118system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 752748 # number of ReadCleanReq MSHR misses 2119system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 895109 # number of ReadSharedReq MSHR misses 2120system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 895109 # number of ReadSharedReq MSHR misses 2121system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 260951 # number of InvalidateReq MSHR misses 2122system.cpu1.l2cache.InvalidateReq_mshr_misses::total 260951 # number of InvalidateReq MSHR misses 2123system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10587 # number of demand (read+write) MSHR misses 2124system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7677 # number of demand (read+write) MSHR misses 2125system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 752748 # number of demand (read+write) MSHR misses 2126system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1120068 # number of demand (read+write) MSHR misses 2127system.cpu1.l2cache.demand_mshr_misses::total 1891080 # number of demand (read+write) MSHR misses 2128system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10587 # number of overall MSHR misses 2129system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7677 # number of overall MSHR misses 2130system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 752748 # number of overall MSHR misses 2131system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1120068 # number of overall MSHR misses 2132system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 626506 # number of overall MSHR misses 2133system.cpu1.l2cache.overall_mshr_misses::total 2517586 # number of overall MSHR misses 2134system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2135system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable 2136system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23602 # number of ReadReq MSHR uncacheable 2137system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable 2138system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable 2139system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2140system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses 2141system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 46174 # number of overall MSHR uncacheable misses 2142system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of ReadReq MSHR miss cycles 2143system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 268081000 # number of ReadReq MSHR miss cycles 2144system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 603645500 # number of ReadReq MSHR miss cycles 2145system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27110588000 # number of HardPFReq MSHR miss cycles 2146system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27110588000 # number of HardPFReq MSHR miss cycles 2147system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4296542495 # number of UpgradeReq MSHR miss cycles 2148system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4296542495 # number of UpgradeReq MSHR miss cycles 2149system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2791394499 # number of SCUpgradeReq MSHR miss cycles 2150system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2791394499 # number of SCUpgradeReq MSHR miss cycles 2151system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4964999 # number of SCUpgradeFailReq MSHR miss cycles 2152system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4964999 # number of SCUpgradeFailReq MSHR miss cycles 2153system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9564152000 # number of ReadExReq MSHR miss cycles 2154system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9564152000 # number of ReadExReq MSHR miss cycles 2155system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 22587351000 # number of ReadCleanReq MSHR miss cycles 2156system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 22587351000 # number of ReadCleanReq MSHR miss cycles 2157system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26554233491 # number of ReadSharedReq MSHR miss cycles 2158system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26554233491 # number of ReadSharedReq MSHR miss cycles 2159system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15760443000 # number of InvalidateReq MSHR miss cycles 2160system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15760443000 # number of InvalidateReq MSHR miss cycles 2161system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of demand (read+write) MSHR miss cycles 2162system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 268081000 # number of demand (read+write) MSHR miss cycles 2163system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 22587351000 # number of demand (read+write) MSHR miss cycles 2164system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36118385491 # number of demand (read+write) MSHR miss cycles 2165system.cpu1.l2cache.demand_mshr_miss_latency::total 59309381991 # number of demand (read+write) MSHR miss cycles 2166system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of overall MSHR miss cycles 2167system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 268081000 # number of overall MSHR miss cycles 2168system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 22587351000 # number of overall MSHR miss cycles 2169system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36118385491 # number of overall MSHR miss cycles 2170system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27110588000 # number of overall MSHR miss cycles 2171system.cpu1.l2cache.overall_mshr_miss_latency::total 86419969991 # number of overall MSHR miss cycles 2172system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11784000 # number of ReadReq MSHR uncacheable cycles 2173system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3870100000 # number of ReadReq MSHR uncacheable cycles 2174system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3881884000 # number of ReadReq MSHR uncacheable cycles 2175system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3768766500 # number of WriteReq MSHR uncacheable cycles 2176system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3768766500 # number of WriteReq MSHR uncacheable cycles 2177system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 11784000 # number of overall MSHR uncacheable cycles 2178system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7638866500 # number of overall MSHR uncacheable cycles 2179system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7650650500 # number of overall MSHR uncacheable cycles 2180system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for ReadReq accesses 2181system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for ReadReq accesses 2182system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029488 # mshr miss rate for ReadReq accesses 2183system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2184system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2185system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2186system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2187system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.659146 # mshr miss rate for UpgradeReq accesses 2188system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.659146 # mshr miss rate for UpgradeReq accesses 2189system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.817846 # mshr miss rate for SCUpgradeReq accesses 2190system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817846 # mshr miss rate for SCUpgradeReq accesses 2191system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2192system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2193system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220319 # mshr miss rate for ReadExReq accesses 2194system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220319 # mshr miss rate for ReadExReq accesses 2195system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for ReadCleanReq accesses 2196system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084913 # mshr miss rate for ReadCleanReq accesses 2197system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.266312 # mshr miss rate for ReadSharedReq accesses 2198system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266312 # mshr miss rate for ReadSharedReq accesses 2199system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.561220 # mshr miss rate for InvalidateReq accesses 2200system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.561220 # mshr miss rate for InvalidateReq accesses 2201system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for demand accesses 2202system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for demand accesses 2203system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for demand accesses 2204system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255596 # mshr miss rate for demand accesses 2205system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136378 # mshr miss rate for demand accesses 2206system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for overall accesses 2207system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for overall accesses 2208system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for overall accesses 2209system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255596 # mshr miss rate for overall accesses 2210system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2211system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181559 # mshr miss rate for overall accesses 2212system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average ReadReq mshr miss latency 2213system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average ReadReq mshr miss latency 2214system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33051.111476 # average ReadReq mshr miss latency 2215system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average HardPFReq mshr miss latency 2216system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43272.670972 # average HardPFReq mshr miss latency 2217system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33917.573139 # average UpgradeReq mshr miss latency 2218system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33917.573139 # average UpgradeReq mshr miss latency 2219system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18746.017615 # average SCUpgradeReq mshr miss latency 2220system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18746.017615 # average SCUpgradeReq mshr miss latency 2221system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 709285.571429 # average SCUpgradeFailReq mshr miss latency 2222system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 709285.571429 # average SCUpgradeFailReq mshr miss latency 2223system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 42515.089416 # average ReadExReq mshr miss latency 2224system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 42515.089416 # average ReadExReq mshr miss latency 2225system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average ReadCleanReq mshr miss latency 2226system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30006.524096 # average ReadCleanReq mshr miss latency 2227system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29665.921682 # average ReadSharedReq mshr miss latency 2228system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29665.921682 # average ReadSharedReq mshr miss latency 2229system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60396.177826 # average InvalidateReq mshr miss latency 2230system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60396.177826 # average InvalidateReq mshr miss latency 2231system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency 2232system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency 2233system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency 2234system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency 2235system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31362.703847 # average overall mshr miss latency 2236system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency 2237system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency 2238system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency 2239system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency 2240system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average overall mshr miss latency 2241system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34326.521513 # average overall mshr miss latency 2242system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency 2243system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164615.057422 # average ReadReq mshr uncacheable latency 2244system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164472.671807 # average ReadReq mshr uncacheable latency 2245system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166966.440723 # average WriteReq mshr uncacheable latency 2246system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166966.440723 # average WriteReq mshr uncacheable latency 2247system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency 2248system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165766.817846 # average overall mshr uncacheable latency 2249system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165691.742106 # average overall mshr uncacheable latency 2250system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2251system.cpu1.toL2Bus.snoop_filter.tot_requests 27994147 # Total number of requests made to the snoop filter. 2252system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14282234 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2253system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2462 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2254system.cpu1.toL2Bus.snoop_filter.tot_snoops 511124 # Total number of snoops made to the snoop filter. 2255system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 511112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2256system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2257system.cpu1.toL2Bus.trans_dist::ReadReq 774549 # Transaction distribution 2258system.cpu1.toL2Bus.trans_dist::ReadResp 13093104 # Transaction distribution 2259system.cpu1.toL2Bus.trans_dist::WriteReq 22572 # Transaction distribution 2260system.cpu1.toL2Bus.trans_dist::WriteResp 22572 # Transaction distribution 2261system.cpu1.toL2Bus.trans_dist::Writeback 4024053 # Transaction distribution 2262system.cpu1.toL2Bus.trans_dist::CleanEvict 12566811 # Transaction distribution 2263system.cpu1.toL2Bus.trans_dist::HardPFReq 824857 # Transaction distribution 2264system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2265system.cpu1.toL2Bus.trans_dist::UpgradeReq 394282 # Transaction distribution 2266system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330789 # Transaction distribution 2267system.cpu1.toL2Bus.trans_dist::UpgradeResp 437890 # Transaction distribution 2268system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution 2269system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 2270system.cpu1.toL2Bus.trans_dist::ReadExReq 1101707 # Transaction distribution 2271system.cpu1.toL2Bus.trans_dist::ReadExResp 1029116 # Transaction distribution 2272system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8864949 # Transaction distribution 2273system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4459910 # Transaction distribution 2274system.cpu1.toL2Bus.trans_dist::InvalidateReq 472941 # Transaction distribution 2275system.cpu1.toL2Bus.trans_dist::InvalidateResp 464971 # Transaction distribution 2276system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26592839 # Packet count per connected master and slave (bytes) 2277system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15453192 # Packet count per connected master and slave (bytes) 2278system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 351687 # Packet count per connected master and slave (bytes) 2279system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1018625 # Packet count per connected master and slave (bytes) 2280system.cpu1.toL2Bus.pkt_count::total 43416343 # Packet count per connected master and slave (bytes) 2281system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 567362560 # Cumulative packet size per connected master and slave (bytes) 2282system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 485060327 # Cumulative packet size per connected master and slave (bytes) 2283system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1274328 # Cumulative packet size per connected master and slave (bytes) 2284system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3680592 # Cumulative packet size per connected master and slave (bytes) 2285system.cpu1.toL2Bus.pkt_size::total 1057377807 # Cumulative packet size per connected master and slave (bytes) 2286system.cpu1.toL2Bus.snoops 5633237 # Total snoops (count) 2287system.cpu1.toL2Bus.snoop_fanout::samples 33839951 # Request fanout histogram 2288system.cpu1.toL2Bus.snoop_fanout::mean 0.023781 # Request fanout histogram 2289system.cpu1.toL2Bus.snoop_fanout::stdev 0.152368 # Request fanout histogram 2290system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2291system.cpu1.toL2Bus.snoop_fanout::0 33035226 97.62% 97.62% # Request fanout histogram 2292system.cpu1.toL2Bus.snoop_fanout::1 804713 2.38% 100.00% # Request fanout histogram 2293system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram 2294system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2295system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2296system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2297system.cpu1.toL2Bus.snoop_fanout::total 33839951 # Request fanout histogram 2298system.cpu1.toL2Bus.reqLayer0.occupancy 17356578996 # Layer occupancy (ticks) 2299system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2300system.cpu1.toL2Bus.snoopLayer0.occupancy 182990836 # Layer occupancy (ticks) 2301system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2302system.cpu1.toL2Bus.respLayer0.occupancy 13300024061 # Layer occupancy (ticks) 2303system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2304system.cpu1.toL2Bus.respLayer1.occupancy 7030302930 # Layer occupancy (ticks) 2305system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2306system.cpu1.toL2Bus.respLayer2.occupancy 192411968 # Layer occupancy (ticks) 2307system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2308system.cpu1.toL2Bus.respLayer3.occupancy 558633834 # Layer occupancy (ticks) 2309system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2310system.iobus.trans_dist::ReadReq 40378 # Transaction distribution 2311system.iobus.trans_dist::ReadResp 40378 # Transaction distribution 2312system.iobus.trans_dist::WriteReq 136939 # Transaction distribution 2313system.iobus.trans_dist::WriteResp 136939 # Transaction distribution 2314system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) 2315system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2316system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2317system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2318system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2319system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2320system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2321system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2322system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2323system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2324system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) 2325system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2326system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2327system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2328system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2329system.iobus.pkt_count_system.bridge.master::total 122772 # Packet count per connected master and slave (bytes) 2330system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes) 2331system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes) 2332system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2333system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2334system.iobus.pkt_count::total 354634 # Packet count per connected master and slave (bytes) 2335system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) 2336system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2337system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2338system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2339system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2340system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2341system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2342system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2343system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) 2346system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2347system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2348system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2349system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2350system.iobus.pkt_size_system.bridge.master::total 155810 # Cumulative packet size per connected master and slave (bytes) 2351system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes) 2352system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes) 2353system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2354system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2355system.iobus.pkt_size::total 7513376 # Cumulative packet size per connected master and slave (bytes) 2356system.iobus.reqLayer0.occupancy 36227000 # Layer occupancy (ticks) 2357system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2359system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2361system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2362system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2363system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2365system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2367system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2368system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2369system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2370system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2371system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2372system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2373system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2374system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2375system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2376system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) 2377system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2378system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2379system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2380system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2381system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2382system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2383system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2384system.iobus.reqLayer27.occupancy 567439447 # Layer occupancy (ticks) 2385system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2386system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2387system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2388system.iobus.respLayer0.occupancy 92820000 # Layer occupancy (ticks) 2389system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2390system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks) 2391system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2392system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2393system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2394system.iocache.tags.replacements 115886 # number of replacements 2395system.iocache.tags.tagsinuse 11.252205 # Cycle average of tags in use 2396system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2397system.iocache.tags.sampled_refs 115902 # Sample count of references to valid blocks. 2398system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2399system.iocache.tags.warmup_cycle 9146784544000 # Cycle when the warmup percentage was hit. 2400system.iocache.tags.occ_blocks::realview.ethernet 7.402122 # Average occupied blocks per requestor 2401system.iocache.tags.occ_blocks::realview.ide 3.850083 # Average occupied blocks per requestor 2402system.iocache.tags.occ_percent::realview.ethernet 0.462633 # Average percentage of cache occupancy 2403system.iocache.tags.occ_percent::realview.ide 0.240630 # Average percentage of cache occupancy 2404system.iocache.tags.occ_percent::total 0.703263 # Average percentage of cache occupancy 2405system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2406system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2407system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2408system.iocache.tags.tag_accesses 1043376 # Number of tag accesses 2409system.iocache.tags.data_accesses 1043376 # Number of data accesses 2410system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2411system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses 2412system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses 2413system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2414system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2415system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2416system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2417system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2418system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses 2419system.iocache.demand_misses::total 8947 # number of demand (read+write) misses 2420system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2421system.iocache.overall_misses::realview.ide 8907 # number of overall misses 2422system.iocache.overall_misses::total 8947 # number of overall misses 2423system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 2424system.iocache.ReadReq_miss_latency::realview.ide 1688317981 # number of ReadReq miss cycles 2425system.iocache.ReadReq_miss_latency::total 1693512981 # number of ReadReq miss cycles 2426system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2427system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2428system.iocache.WriteLineReq_miss_latency::realview.ide 13959998466 # number of WriteLineReq miss cycles 2429system.iocache.WriteLineReq_miss_latency::total 13959998466 # number of WriteLineReq miss cycles 2430system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 2431system.iocache.demand_miss_latency::realview.ide 1688317981 # number of demand (read+write) miss cycles 2432system.iocache.demand_miss_latency::total 1693881981 # number of demand (read+write) miss cycles 2433system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 2434system.iocache.overall_miss_latency::realview.ide 1688317981 # number of overall miss cycles 2435system.iocache.overall_miss_latency::total 1693881981 # number of overall miss cycles 2436system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2437system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses) 2438system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses) 2439system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2440system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2441system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2442system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2443system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2444system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses 2445system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses 2446system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2447system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses 2448system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses 2449system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2450system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2451system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2452system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2453system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2454system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2455system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2456system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2457system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2458system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2459system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2460system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2461system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2462system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 2463system.iocache.ReadReq_avg_miss_latency::realview.ide 189549.565623 # average ReadReq miss latency 2464system.iocache.ReadReq_avg_miss_latency::total 189346.263529 # average ReadReq miss latency 2465system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2466system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2467system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130486.787426 # average WriteLineReq miss latency 2468system.iocache.WriteLineReq_avg_miss_latency::total 130486.787426 # average WriteLineReq miss latency 2469system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2470system.iocache.demand_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency 2471system.iocache.demand_avg_miss_latency::total 189324.017101 # average overall miss latency 2472system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2473system.iocache.overall_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency 2474system.iocache.overall_avg_miss_latency::total 189324.017101 # average overall miss latency 2475system.iocache.blocked_cycles::no_mshrs 34260 # number of cycles access was blocked 2476system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2477system.iocache.blocked::no_mshrs 3572 # number of cycles access was blocked 2478system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2479system.iocache.avg_blocked_cycles::no_mshrs 9.591265 # average number of cycles each access was blocked 2480system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2481system.iocache.fast_writes 0 # number of fast writes performed 2482system.iocache.cache_copies 0 # number of cache copies performed 2483system.iocache.writebacks::writebacks 106949 # number of writebacks 2484system.iocache.writebacks::total 106949 # number of writebacks 2485system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2486system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses 2487system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses 2488system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2489system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2490system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2491system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2492system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2493system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses 2494system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses 2495system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2496system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses 2497system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses 2498system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 2499system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242967981 # number of ReadReq MSHR miss cycles 2500system.iocache.ReadReq_mshr_miss_latency::total 1246312981 # number of ReadReq MSHR miss cycles 2501system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2502system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2503system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8610798466 # number of WriteLineReq MSHR miss cycles 2504system.iocache.WriteLineReq_mshr_miss_latency::total 8610798466 # number of WriteLineReq MSHR miss cycles 2505system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 2506system.iocache.demand_mshr_miss_latency::realview.ide 1242967981 # number of demand (read+write) MSHR miss cycles 2507system.iocache.demand_mshr_miss_latency::total 1246531981 # number of demand (read+write) MSHR miss cycles 2508system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 2509system.iocache.overall_mshr_miss_latency::realview.ide 1242967981 # number of overall MSHR miss cycles 2510system.iocache.overall_mshr_miss_latency::total 1246531981 # number of overall MSHR miss cycles 2511system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2512system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2513system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2514system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2515system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2516system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2517system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2518system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2519system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2520system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2521system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2522system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2523system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2524system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 2525system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139549.565623 # average ReadReq mshr miss latency 2526system.iocache.ReadReq_avg_mshr_miss_latency::total 139346.263529 # average ReadReq mshr miss latency 2527system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2528system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2529system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80486.787426 # average WriteLineReq mshr miss latency 2530system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80486.787426 # average WriteLineReq mshr miss latency 2531system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2532system.iocache.demand_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency 2533system.iocache.demand_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency 2534system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2535system.iocache.overall_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency 2536system.iocache.overall_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency 2537system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2538system.l2c.tags.replacements 1172651 # number of replacements 2539system.l2c.tags.tagsinuse 63896.612844 # Cycle average of tags in use 2540system.l2c.tags.total_refs 5899189 # Total number of references to valid blocks. 2541system.l2c.tags.sampled_refs 1234288 # Sample count of references to valid blocks. 2542system.l2c.tags.avg_refs 4.779427 # Average number of references to valid blocks. 2543system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2544system.l2c.tags.occ_blocks::writebacks 19626.342189 # Average occupied blocks per requestor 2545system.l2c.tags.occ_blocks::cpu0.dtb.walker 209.741305 # Average occupied blocks per requestor 2546system.l2c.tags.occ_blocks::cpu0.itb.walker 250.506537 # Average occupied blocks per requestor 2547system.l2c.tags.occ_blocks::cpu0.inst 6148.160419 # Average occupied blocks per requestor 2548system.l2c.tags.occ_blocks::cpu0.data 12486.088901 # Average occupied blocks per requestor 2549system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 12942.693356 # Average occupied blocks per requestor 2550system.l2c.tags.occ_blocks::cpu1.dtb.walker 77.886538 # Average occupied blocks per requestor 2551system.l2c.tags.occ_blocks::cpu1.itb.walker 86.786571 # Average occupied blocks per requestor 2552system.l2c.tags.occ_blocks::cpu1.inst 4894.205028 # Average occupied blocks per requestor 2553system.l2c.tags.occ_blocks::cpu1.data 3546.886464 # Average occupied blocks per requestor 2554system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3627.315534 # Average occupied blocks per requestor 2555system.l2c.tags.occ_percent::writebacks 0.299474 # Average percentage of cache occupancy 2556system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003200 # Average percentage of cache occupancy 2557system.l2c.tags.occ_percent::cpu0.itb.walker 0.003822 # Average percentage of cache occupancy 2558system.l2c.tags.occ_percent::cpu0.inst 0.093813 # Average percentage of cache occupancy 2559system.l2c.tags.occ_percent::cpu0.data 0.190523 # Average percentage of cache occupancy 2560system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.197490 # Average percentage of cache occupancy 2561system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001188 # Average percentage of cache occupancy 2562system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy 2563system.l2c.tags.occ_percent::cpu1.inst 0.074680 # Average percentage of cache occupancy 2564system.l2c.tags.occ_percent::cpu1.data 0.054121 # Average percentage of cache occupancy 2565system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055348 # Average percentage of cache occupancy 2566system.l2c.tags.occ_percent::total 0.974985 # Average percentage of cache occupancy 2567system.l2c.tags.occ_task_id_blocks::1022 12177 # Occupied blocks per task id 2568system.l2c.tags.occ_task_id_blocks::1023 211 # Occupied blocks per task id 2569system.l2c.tags.occ_task_id_blocks::1024 49249 # Occupied blocks per task id 2570system.l2c.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id 2571system.l2c.tags.age_task_id_blocks_1022::1 56 # Occupied blocks per task id 2572system.l2c.tags.age_task_id_blocks_1022::2 1468 # Occupied blocks per task id 2573system.l2c.tags.age_task_id_blocks_1022::3 3502 # Occupied blocks per task id 2574system.l2c.tags.age_task_id_blocks_1022::4 7139 # Occupied blocks per task id 2575system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 2576system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 2577system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id 2578system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 2579system.l2c.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 2580system.l2c.tags.age_task_id_blocks_1024::2 1696 # Occupied blocks per task id 2581system.l2c.tags.age_task_id_blocks_1024::3 11834 # Occupied blocks per task id 2582system.l2c.tags.age_task_id_blocks_1024::4 35465 # Occupied blocks per task id 2583system.l2c.tags.occ_task_id_percent::1022 0.185806 # Percentage of cache occupancy per task id 2584system.l2c.tags.occ_task_id_percent::1023 0.003220 # Percentage of cache occupancy per task id 2585system.l2c.tags.occ_task_id_percent::1024 0.751480 # Percentage of cache occupancy per task id 2586system.l2c.tags.tag_accesses 69068672 # Number of tag accesses 2587system.l2c.tags.data_accesses 69068672 # Number of data accesses 2588system.l2c.Writeback_hits::writebacks 2213157 # number of Writeback hits 2589system.l2c.Writeback_hits::total 2213157 # number of Writeback hits 2590system.l2c.UpgradeReq_hits::cpu0.data 26227 # number of UpgradeReq hits 2591system.l2c.UpgradeReq_hits::cpu1.data 30963 # number of UpgradeReq hits 2592system.l2c.UpgradeReq_hits::total 57190 # number of UpgradeReq hits 2593system.l2c.SCUpgradeReq_hits::cpu0.data 5791 # number of SCUpgradeReq hits 2594system.l2c.SCUpgradeReq_hits::cpu1.data 6000 # number of SCUpgradeReq hits 2595system.l2c.SCUpgradeReq_hits::total 11791 # number of SCUpgradeReq hits 2596system.l2c.ReadExReq_hits::cpu0.data 170699 # number of ReadExReq hits 2597system.l2c.ReadExReq_hits::cpu1.data 173368 # number of ReadExReq hits 2598system.l2c.ReadExReq_hits::total 344067 # number of ReadExReq hits 2599system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6059 # number of ReadSharedReq hits 2600system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4018 # number of ReadSharedReq hits 2601system.l2c.ReadSharedReq_hits::cpu0.inst 717194 # number of ReadSharedReq hits 2602system.l2c.ReadSharedReq_hits::cpu0.data 567434 # number of ReadSharedReq hits 2603system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 309455 # number of ReadSharedReq hits 2604system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6450 # number of ReadSharedReq hits 2605system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4624 # number of ReadSharedReq hits 2606system.l2c.ReadSharedReq_hits::cpu1.inst 697524 # number of ReadSharedReq hits 2607system.l2c.ReadSharedReq_hits::cpu1.data 530409 # number of ReadSharedReq hits 2608system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 314319 # number of ReadSharedReq hits 2609system.l2c.ReadSharedReq_hits::total 3157486 # number of ReadSharedReq hits 2610system.l2c.demand_hits::cpu0.dtb.walker 6059 # number of demand (read+write) hits 2611system.l2c.demand_hits::cpu0.itb.walker 4018 # number of demand (read+write) hits 2612system.l2c.demand_hits::cpu0.inst 717194 # number of demand (read+write) hits 2613system.l2c.demand_hits::cpu0.data 738133 # number of demand (read+write) hits 2614system.l2c.demand_hits::cpu0.l2cache.prefetcher 309455 # number of demand (read+write) hits 2615system.l2c.demand_hits::cpu1.dtb.walker 6450 # number of demand (read+write) hits 2616system.l2c.demand_hits::cpu1.itb.walker 4624 # number of demand (read+write) hits 2617system.l2c.demand_hits::cpu1.inst 697524 # number of demand (read+write) hits 2618system.l2c.demand_hits::cpu1.data 703777 # number of demand (read+write) hits 2619system.l2c.demand_hits::cpu1.l2cache.prefetcher 314319 # number of demand (read+write) hits 2620system.l2c.demand_hits::total 3501553 # number of demand (read+write) hits 2621system.l2c.overall_hits::cpu0.dtb.walker 6059 # number of overall hits 2622system.l2c.overall_hits::cpu0.itb.walker 4018 # number of overall hits 2623system.l2c.overall_hits::cpu0.inst 717194 # number of overall hits 2624system.l2c.overall_hits::cpu0.data 738133 # number of overall hits 2625system.l2c.overall_hits::cpu0.l2cache.prefetcher 309455 # number of overall hits 2626system.l2c.overall_hits::cpu1.dtb.walker 6450 # number of overall hits 2627system.l2c.overall_hits::cpu1.itb.walker 4624 # number of overall hits 2628system.l2c.overall_hits::cpu1.inst 697524 # number of overall hits 2629system.l2c.overall_hits::cpu1.data 703777 # number of overall hits 2630system.l2c.overall_hits::cpu1.l2cache.prefetcher 314319 # number of overall hits 2631system.l2c.overall_hits::total 3501553 # number of overall hits 2632system.l2c.UpgradeReq_misses::cpu0.data 46094 # number of UpgradeReq misses 2633system.l2c.UpgradeReq_misses::cpu1.data 42278 # number of UpgradeReq misses 2634system.l2c.UpgradeReq_misses::total 88372 # number of UpgradeReq misses 2635system.l2c.SCUpgradeReq_misses::cpu0.data 9356 # number of SCUpgradeReq misses 2636system.l2c.SCUpgradeReq_misses::cpu1.data 8640 # number of SCUpgradeReq misses 2637system.l2c.SCUpgradeReq_misses::total 17996 # number of SCUpgradeReq misses 2638system.l2c.ReadExReq_misses::cpu0.data 470394 # number of ReadExReq misses 2639system.l2c.ReadExReq_misses::cpu1.data 130669 # number of ReadExReq misses 2640system.l2c.ReadExReq_misses::total 601063 # number of ReadExReq misses 2641system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1338 # number of ReadSharedReq misses 2642system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1196 # number of ReadSharedReq misses 2643system.l2c.ReadSharedReq_misses::cpu0.inst 55388 # number of ReadSharedReq misses 2644system.l2c.ReadSharedReq_misses::cpu0.data 120389 # number of ReadSharedReq misses 2645system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 168332 # number of ReadSharedReq misses 2646system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1176 # number of ReadSharedReq misses 2647system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1070 # number of ReadSharedReq misses 2648system.l2c.ReadSharedReq_misses::cpu1.inst 55224 # number of ReadSharedReq misses 2649system.l2c.ReadSharedReq_misses::cpu1.data 85443 # number of ReadSharedReq misses 2650system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 133806 # number of ReadSharedReq misses 2651system.l2c.ReadSharedReq_misses::total 623362 # number of ReadSharedReq misses 2652system.l2c.demand_misses::cpu0.dtb.walker 1338 # number of demand (read+write) misses 2653system.l2c.demand_misses::cpu0.itb.walker 1196 # number of demand (read+write) misses 2654system.l2c.demand_misses::cpu0.inst 55388 # number of demand (read+write) misses 2655system.l2c.demand_misses::cpu0.data 590783 # number of demand (read+write) misses 2656system.l2c.demand_misses::cpu0.l2cache.prefetcher 168332 # number of demand (read+write) misses 2657system.l2c.demand_misses::cpu1.dtb.walker 1176 # number of demand (read+write) misses 2658system.l2c.demand_misses::cpu1.itb.walker 1070 # number of demand (read+write) misses 2659system.l2c.demand_misses::cpu1.inst 55224 # number of demand (read+write) misses 2660system.l2c.demand_misses::cpu1.data 216112 # number of demand (read+write) misses 2661system.l2c.demand_misses::cpu1.l2cache.prefetcher 133806 # number of demand (read+write) misses 2662system.l2c.demand_misses::total 1224425 # number of demand (read+write) misses 2663system.l2c.overall_misses::cpu0.dtb.walker 1338 # number of overall misses 2664system.l2c.overall_misses::cpu0.itb.walker 1196 # number of overall misses 2665system.l2c.overall_misses::cpu0.inst 55388 # number of overall misses 2666system.l2c.overall_misses::cpu0.data 590783 # number of overall misses 2667system.l2c.overall_misses::cpu0.l2cache.prefetcher 168332 # number of overall misses 2668system.l2c.overall_misses::cpu1.dtb.walker 1176 # number of overall misses 2669system.l2c.overall_misses::cpu1.itb.walker 1070 # number of overall misses 2670system.l2c.overall_misses::cpu1.inst 55224 # number of overall misses 2671system.l2c.overall_misses::cpu1.data 216112 # number of overall misses 2672system.l2c.overall_misses::cpu1.l2cache.prefetcher 133806 # number of overall misses 2673system.l2c.overall_misses::total 1224425 # number of overall misses 2674system.l2c.UpgradeReq_miss_latency::cpu0.data 737888500 # number of UpgradeReq miss cycles 2675system.l2c.UpgradeReq_miss_latency::cpu1.data 668601000 # number of UpgradeReq miss cycles 2676system.l2c.UpgradeReq_miss_latency::total 1406489500 # number of UpgradeReq miss cycles 2677system.l2c.SCUpgradeReq_miss_latency::cpu0.data 133423500 # number of SCUpgradeReq miss cycles 2678system.l2c.SCUpgradeReq_miss_latency::cpu1.data 126121000 # number of SCUpgradeReq miss cycles 2679system.l2c.SCUpgradeReq_miss_latency::total 259544500 # number of SCUpgradeReq miss cycles 2680system.l2c.ReadExReq_miss_latency::cpu0.data 68021517000 # number of ReadExReq miss cycles 2681system.l2c.ReadExReq_miss_latency::cpu1.data 17893316000 # number of ReadExReq miss cycles 2682system.l2c.ReadExReq_miss_latency::total 85914833000 # number of ReadExReq miss cycles 2683system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 182621000 # number of ReadSharedReq miss cycles 2684system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 165049500 # number of ReadSharedReq miss cycles 2685system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7432164500 # number of ReadSharedReq miss cycles 2686system.l2c.ReadSharedReq_miss_latency::cpu0.data 16649727500 # number of ReadSharedReq miss cycles 2687system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of ReadSharedReq miss cycles 2688system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 164644500 # number of ReadSharedReq miss cycles 2689system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 152256000 # number of ReadSharedReq miss cycles 2690system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7382488500 # number of ReadSharedReq miss cycles 2691system.l2c.ReadSharedReq_miss_latency::cpu1.data 11836491000 # number of ReadSharedReq miss cycles 2692system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of ReadSharedReq miss cycles 2693system.l2c.ReadSharedReq_miss_latency::total 93356372957 # number of ReadSharedReq miss cycles 2694system.l2c.demand_miss_latency::cpu0.dtb.walker 182621000 # number of demand (read+write) miss cycles 2695system.l2c.demand_miss_latency::cpu0.itb.walker 165049500 # number of demand (read+write) miss cycles 2696system.l2c.demand_miss_latency::cpu0.inst 7432164500 # number of demand (read+write) miss cycles 2697system.l2c.demand_miss_latency::cpu0.data 84671244500 # number of demand (read+write) miss cycles 2698system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of demand (read+write) miss cycles 2699system.l2c.demand_miss_latency::cpu1.dtb.walker 164644500 # number of demand (read+write) miss cycles 2700system.l2c.demand_miss_latency::cpu1.itb.walker 152256000 # number of demand (read+write) miss cycles 2701system.l2c.demand_miss_latency::cpu1.inst 7382488500 # number of demand (read+write) miss cycles 2702system.l2c.demand_miss_latency::cpu1.data 29729807000 # number of demand (read+write) miss cycles 2703system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of demand (read+write) miss cycles 2704system.l2c.demand_miss_latency::total 179271205957 # number of demand (read+write) miss cycles 2705system.l2c.overall_miss_latency::cpu0.dtb.walker 182621000 # number of overall miss cycles 2706system.l2c.overall_miss_latency::cpu0.itb.walker 165049500 # number of overall miss cycles 2707system.l2c.overall_miss_latency::cpu0.inst 7432164500 # number of overall miss cycles 2708system.l2c.overall_miss_latency::cpu0.data 84671244500 # number of overall miss cycles 2709system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of overall miss cycles 2710system.l2c.overall_miss_latency::cpu1.dtb.walker 164644500 # number of overall miss cycles 2711system.l2c.overall_miss_latency::cpu1.itb.walker 152256000 # number of overall miss cycles 2712system.l2c.overall_miss_latency::cpu1.inst 7382488500 # number of overall miss cycles 2713system.l2c.overall_miss_latency::cpu1.data 29729807000 # number of overall miss cycles 2714system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of overall miss cycles 2715system.l2c.overall_miss_latency::total 179271205957 # number of overall miss cycles 2716system.l2c.Writeback_accesses::writebacks 2213157 # number of Writeback accesses(hits+misses) 2717system.l2c.Writeback_accesses::total 2213157 # number of Writeback accesses(hits+misses) 2718system.l2c.UpgradeReq_accesses::cpu0.data 72321 # number of UpgradeReq accesses(hits+misses) 2719system.l2c.UpgradeReq_accesses::cpu1.data 73241 # number of UpgradeReq accesses(hits+misses) 2720system.l2c.UpgradeReq_accesses::total 145562 # number of UpgradeReq accesses(hits+misses) 2721system.l2c.SCUpgradeReq_accesses::cpu0.data 15147 # number of SCUpgradeReq accesses(hits+misses) 2722system.l2c.SCUpgradeReq_accesses::cpu1.data 14640 # number of SCUpgradeReq accesses(hits+misses) 2723system.l2c.SCUpgradeReq_accesses::total 29787 # number of SCUpgradeReq accesses(hits+misses) 2724system.l2c.ReadExReq_accesses::cpu0.data 641093 # number of ReadExReq accesses(hits+misses) 2725system.l2c.ReadExReq_accesses::cpu1.data 304037 # number of ReadExReq accesses(hits+misses) 2726system.l2c.ReadExReq_accesses::total 945130 # number of ReadExReq accesses(hits+misses) 2727system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7397 # number of ReadSharedReq accesses(hits+misses) 2728system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5214 # number of ReadSharedReq accesses(hits+misses) 2729system.l2c.ReadSharedReq_accesses::cpu0.inst 772582 # number of ReadSharedReq accesses(hits+misses) 2730system.l2c.ReadSharedReq_accesses::cpu0.data 687823 # number of ReadSharedReq accesses(hits+misses) 2731system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 477787 # number of ReadSharedReq accesses(hits+misses) 2732system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7626 # number of ReadSharedReq accesses(hits+misses) 2733system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5694 # number of ReadSharedReq accesses(hits+misses) 2734system.l2c.ReadSharedReq_accesses::cpu1.inst 752748 # number of ReadSharedReq accesses(hits+misses) 2735system.l2c.ReadSharedReq_accesses::cpu1.data 615852 # number of ReadSharedReq accesses(hits+misses) 2736system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 448125 # number of ReadSharedReq accesses(hits+misses) 2737system.l2c.ReadSharedReq_accesses::total 3780848 # number of ReadSharedReq accesses(hits+misses) 2738system.l2c.demand_accesses::cpu0.dtb.walker 7397 # number of demand (read+write) accesses 2739system.l2c.demand_accesses::cpu0.itb.walker 5214 # number of demand (read+write) accesses 2740system.l2c.demand_accesses::cpu0.inst 772582 # number of demand (read+write) accesses 2741system.l2c.demand_accesses::cpu0.data 1328916 # number of demand (read+write) accesses 2742system.l2c.demand_accesses::cpu0.l2cache.prefetcher 477787 # number of demand (read+write) accesses 2743system.l2c.demand_accesses::cpu1.dtb.walker 7626 # number of demand (read+write) accesses 2744system.l2c.demand_accesses::cpu1.itb.walker 5694 # number of demand (read+write) accesses 2745system.l2c.demand_accesses::cpu1.inst 752748 # number of demand (read+write) accesses 2746system.l2c.demand_accesses::cpu1.data 919889 # number of demand (read+write) accesses 2747system.l2c.demand_accesses::cpu1.l2cache.prefetcher 448125 # number of demand (read+write) accesses 2748system.l2c.demand_accesses::total 4725978 # number of demand (read+write) accesses 2749system.l2c.overall_accesses::cpu0.dtb.walker 7397 # number of overall (read+write) accesses 2750system.l2c.overall_accesses::cpu0.itb.walker 5214 # number of overall (read+write) accesses 2751system.l2c.overall_accesses::cpu0.inst 772582 # number of overall (read+write) accesses 2752system.l2c.overall_accesses::cpu0.data 1328916 # number of overall (read+write) accesses 2753system.l2c.overall_accesses::cpu0.l2cache.prefetcher 477787 # number of overall (read+write) accesses 2754system.l2c.overall_accesses::cpu1.dtb.walker 7626 # number of overall (read+write) accesses 2755system.l2c.overall_accesses::cpu1.itb.walker 5694 # number of overall (read+write) accesses 2756system.l2c.overall_accesses::cpu1.inst 752748 # number of overall (read+write) accesses 2757system.l2c.overall_accesses::cpu1.data 919889 # number of overall (read+write) accesses 2758system.l2c.overall_accesses::cpu1.l2cache.prefetcher 448125 # number of overall (read+write) accesses 2759system.l2c.overall_accesses::total 4725978 # number of overall (read+write) accesses 2760system.l2c.UpgradeReq_miss_rate::cpu0.data 0.637353 # miss rate for UpgradeReq accesses 2761system.l2c.UpgradeReq_miss_rate::cpu1.data 0.577245 # miss rate for UpgradeReq accesses 2762system.l2c.UpgradeReq_miss_rate::total 0.607109 # miss rate for UpgradeReq accesses 2763system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.617680 # miss rate for SCUpgradeReq accesses 2764system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590164 # miss rate for SCUpgradeReq accesses 2765system.l2c.SCUpgradeReq_miss_rate::total 0.604156 # miss rate for SCUpgradeReq accesses 2766system.l2c.ReadExReq_miss_rate::cpu0.data 0.733738 # miss rate for ReadExReq accesses 2767system.l2c.ReadExReq_miss_rate::cpu1.data 0.429780 # miss rate for ReadExReq accesses 2768system.l2c.ReadExReq_miss_rate::total 0.635958 # miss rate for ReadExReq accesses 2769system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for ReadSharedReq accesses 2770system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.229382 # miss rate for ReadSharedReq accesses 2771system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.071692 # miss rate for ReadSharedReq accesses 2772system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.175029 # miss rate for ReadSharedReq accesses 2773system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for ReadSharedReq accesses 2774system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for ReadSharedReq accesses 2775system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.187917 # miss rate for ReadSharedReq accesses 2776system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.073363 # miss rate for ReadSharedReq accesses 2777system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.138740 # miss rate for ReadSharedReq accesses 2778system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for ReadSharedReq accesses 2779system.l2c.ReadSharedReq_miss_rate::total 0.164874 # miss rate for ReadSharedReq accesses 2780system.l2c.demand_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for demand accesses 2781system.l2c.demand_miss_rate::cpu0.itb.walker 0.229382 # miss rate for demand accesses 2782system.l2c.demand_miss_rate::cpu0.inst 0.071692 # miss rate for demand accesses 2783system.l2c.demand_miss_rate::cpu0.data 0.444560 # miss rate for demand accesses 2784system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for demand accesses 2785system.l2c.demand_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for demand accesses 2786system.l2c.demand_miss_rate::cpu1.itb.walker 0.187917 # miss rate for demand accesses 2787system.l2c.demand_miss_rate::cpu1.inst 0.073363 # miss rate for demand accesses 2788system.l2c.demand_miss_rate::cpu1.data 0.234933 # miss rate for demand accesses 2789system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for demand accesses 2790system.l2c.demand_miss_rate::total 0.259084 # miss rate for demand accesses 2791system.l2c.overall_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for overall accesses 2792system.l2c.overall_miss_rate::cpu0.itb.walker 0.229382 # miss rate for overall accesses 2793system.l2c.overall_miss_rate::cpu0.inst 0.071692 # miss rate for overall accesses 2794system.l2c.overall_miss_rate::cpu0.data 0.444560 # miss rate for overall accesses 2795system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for overall accesses 2796system.l2c.overall_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for overall accesses 2797system.l2c.overall_miss_rate::cpu1.itb.walker 0.187917 # miss rate for overall accesses 2798system.l2c.overall_miss_rate::cpu1.inst 0.073363 # miss rate for overall accesses 2799system.l2c.overall_miss_rate::cpu1.data 0.234933 # miss rate for overall accesses 2800system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for overall accesses 2801system.l2c.overall_miss_rate::total 0.259084 # miss rate for overall accesses 2802system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16008.341650 # average UpgradeReq miss latency 2803system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15814.395194 # average UpgradeReq miss latency 2804system.l2c.UpgradeReq_avg_miss_latency::total 15915.555832 # average UpgradeReq miss latency 2805system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14260.741770 # average SCUpgradeReq miss latency 2806system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14597.337963 # average SCUpgradeReq miss latency 2807system.l2c.SCUpgradeReq_avg_miss_latency::total 14422.343854 # average SCUpgradeReq miss latency 2808system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144605.409508 # average ReadExReq miss latency 2809system.l2c.ReadExReq_avg_miss_latency::cpu1.data 136936.197568 # average ReadExReq miss latency 2810system.l2c.ReadExReq_avg_miss_latency::total 142938.149578 # average ReadExReq miss latency 2811system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average ReadSharedReq miss latency 2812system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138001.254181 # average ReadSharedReq miss latency 2813system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134183.658915 # average ReadSharedReq miss latency 2814system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138299.408584 # average ReadSharedReq miss latency 2815system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average ReadSharedReq miss latency 2816system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average ReadSharedReq miss latency 2817system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142295.327103 # average ReadSharedReq miss latency 2818system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133682.610821 # average ReadSharedReq miss latency 2819system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138530.845125 # average ReadSharedReq miss latency 2820system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average ReadSharedReq miss latency 2821system.l2c.ReadSharedReq_avg_miss_latency::total 149762.694802 # average ReadSharedReq miss latency 2822system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average overall miss latency 2823system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138001.254181 # average overall miss latency 2824system.l2c.demand_avg_miss_latency::cpu0.inst 134183.658915 # average overall miss latency 2825system.l2c.demand_avg_miss_latency::cpu0.data 143320.380749 # average overall miss latency 2826system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average overall miss latency 2827system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average overall miss latency 2828system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142295.327103 # average overall miss latency 2829system.l2c.demand_avg_miss_latency::cpu1.inst 133682.610821 # average overall miss latency 2830system.l2c.demand_avg_miss_latency::cpu1.data 137566.664507 # average overall miss latency 2831system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average overall miss latency 2832system.l2c.demand_avg_miss_latency::total 146412.565863 # average overall miss latency 2833system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average overall miss latency 2834system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138001.254181 # average overall miss latency 2835system.l2c.overall_avg_miss_latency::cpu0.inst 134183.658915 # average overall miss latency 2836system.l2c.overall_avg_miss_latency::cpu0.data 143320.380749 # average overall miss latency 2837system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average overall miss latency 2838system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average overall miss latency 2839system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142295.327103 # average overall miss latency 2840system.l2c.overall_avg_miss_latency::cpu1.inst 133682.610821 # average overall miss latency 2841system.l2c.overall_avg_miss_latency::cpu1.data 137566.664507 # average overall miss latency 2842system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average overall miss latency 2843system.l2c.overall_avg_miss_latency::total 146412.565863 # average overall miss latency 2844system.l2c.blocked_cycles::no_mshrs 2168 # number of cycles access was blocked 2845system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2846system.l2c.blocked::no_mshrs 31 # number of cycles access was blocked 2847system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2848system.l2c.avg_blocked_cycles::no_mshrs 69.935484 # average number of cycles each access was blocked 2849system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2850system.l2c.fast_writes 0 # number of fast writes performed 2851system.l2c.cache_copies 0 # number of cache copies performed 2852system.l2c.writebacks::writebacks 894068 # number of writebacks 2853system.l2c.writebacks::total 894068 # number of writebacks 2854system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits 2855system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 157 # number of ReadSharedReq MSHR hits 2856system.l2c.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits 2857system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 173 # number of ReadSharedReq MSHR hits 2858system.l2c.ReadSharedReq_mshr_hits::cpu1.data 21 # number of ReadSharedReq MSHR hits 2859system.l2c.ReadSharedReq_mshr_hits::total 381 # number of ReadSharedReq MSHR hits 2860system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 2861system.l2c.demand_mshr_hits::cpu0.inst 157 # number of demand (read+write) MSHR hits 2862system.l2c.demand_mshr_hits::cpu0.data 29 # number of demand (read+write) MSHR hits 2863system.l2c.demand_mshr_hits::cpu1.inst 173 # number of demand (read+write) MSHR hits 2864system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits 2865system.l2c.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits 2866system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 2867system.l2c.overall_mshr_hits::cpu0.inst 157 # number of overall MSHR hits 2868system.l2c.overall_mshr_hits::cpu0.data 29 # number of overall MSHR hits 2869system.l2c.overall_mshr_hits::cpu1.inst 173 # number of overall MSHR hits 2870system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits 2871system.l2c.overall_mshr_hits::total 381 # number of overall MSHR hits 2872system.l2c.CleanEvict_mshr_misses::writebacks 39667 # number of CleanEvict MSHR misses 2873system.l2c.CleanEvict_mshr_misses::total 39667 # number of CleanEvict MSHR misses 2874system.l2c.UpgradeReq_mshr_misses::cpu0.data 46094 # number of UpgradeReq MSHR misses 2875system.l2c.UpgradeReq_mshr_misses::cpu1.data 42278 # number of UpgradeReq MSHR misses 2876system.l2c.UpgradeReq_mshr_misses::total 88372 # number of UpgradeReq MSHR misses 2877system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9356 # number of SCUpgradeReq MSHR misses 2878system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8640 # number of SCUpgradeReq MSHR misses 2879system.l2c.SCUpgradeReq_mshr_misses::total 17996 # number of SCUpgradeReq MSHR misses 2880system.l2c.ReadExReq_mshr_misses::cpu0.data 470394 # number of ReadExReq MSHR misses 2881system.l2c.ReadExReq_mshr_misses::cpu1.data 130669 # number of ReadExReq MSHR misses 2882system.l2c.ReadExReq_mshr_misses::total 601063 # number of ReadExReq MSHR misses 2883system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1337 # number of ReadSharedReq MSHR misses 2884system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1196 # number of ReadSharedReq MSHR misses 2885system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 55231 # number of ReadSharedReq MSHR misses 2886system.l2c.ReadSharedReq_mshr_misses::cpu0.data 120360 # number of ReadSharedReq MSHR misses 2887system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of ReadSharedReq MSHR misses 2888system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1176 # number of ReadSharedReq MSHR misses 2889system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1070 # number of ReadSharedReq MSHR misses 2890system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 55051 # number of ReadSharedReq MSHR misses 2891system.l2c.ReadSharedReq_mshr_misses::cpu1.data 85422 # number of ReadSharedReq MSHR misses 2892system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of ReadSharedReq MSHR misses 2893system.l2c.ReadSharedReq_mshr_misses::total 622981 # number of ReadSharedReq MSHR misses 2894system.l2c.demand_mshr_misses::cpu0.dtb.walker 1337 # number of demand (read+write) MSHR misses 2895system.l2c.demand_mshr_misses::cpu0.itb.walker 1196 # number of demand (read+write) MSHR misses 2896system.l2c.demand_mshr_misses::cpu0.inst 55231 # number of demand (read+write) MSHR misses 2897system.l2c.demand_mshr_misses::cpu0.data 590754 # number of demand (read+write) MSHR misses 2898system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of demand (read+write) MSHR misses 2899system.l2c.demand_mshr_misses::cpu1.dtb.walker 1176 # number of demand (read+write) MSHR misses 2900system.l2c.demand_mshr_misses::cpu1.itb.walker 1070 # number of demand (read+write) MSHR misses 2901system.l2c.demand_mshr_misses::cpu1.inst 55051 # number of demand (read+write) MSHR misses 2902system.l2c.demand_mshr_misses::cpu1.data 216091 # number of demand (read+write) MSHR misses 2903system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of demand (read+write) MSHR misses 2904system.l2c.demand_mshr_misses::total 1224044 # number of demand (read+write) MSHR misses 2905system.l2c.overall_mshr_misses::cpu0.dtb.walker 1337 # number of overall MSHR misses 2906system.l2c.overall_mshr_misses::cpu0.itb.walker 1196 # number of overall MSHR misses 2907system.l2c.overall_mshr_misses::cpu0.inst 55231 # number of overall MSHR misses 2908system.l2c.overall_mshr_misses::cpu0.data 590754 # number of overall MSHR misses 2909system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of overall MSHR misses 2910system.l2c.overall_mshr_misses::cpu1.dtb.walker 1176 # number of overall MSHR misses 2911system.l2c.overall_mshr_misses::cpu1.itb.walker 1070 # number of overall MSHR misses 2912system.l2c.overall_mshr_misses::cpu1.inst 55051 # number of overall MSHR misses 2913system.l2c.overall_mshr_misses::cpu1.data 216091 # number of overall MSHR misses 2914system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of overall MSHR misses 2915system.l2c.overall_mshr_misses::total 1224044 # number of overall MSHR misses 2916system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 2917system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable 2918system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2919system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23508 # number of ReadReq MSHR uncacheable 2920system.l2c.ReadReq_mshr_uncacheable::total 90534 # number of ReadReq MSHR uncacheable 2921system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable 2922system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable 2923system.l2c.WriteReq_mshr_uncacheable::total 38054 # number of WriteReq MSHR uncacheable 2924system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 2925system.l2c.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses 2926system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2927system.l2c.overall_mshr_uncacheable_misses::cpu1.data 46080 # number of overall MSHR uncacheable misses 2928system.l2c.overall_mshr_uncacheable_misses::total 128588 # number of overall MSHR uncacheable misses 2929system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3387465005 # number of UpgradeReq MSHR miss cycles 2930system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3115331505 # number of UpgradeReq MSHR miss cycles 2931system.l2c.UpgradeReq_mshr_miss_latency::total 6502796510 # number of UpgradeReq MSHR miss cycles 2932system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 715527500 # number of SCUpgradeReq MSHR miss cycles 2933system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 661381001 # number of SCUpgradeReq MSHR miss cycles 2934system.l2c.SCUpgradeReq_mshr_miss_latency::total 1376908501 # number of SCUpgradeReq MSHR miss cycles 2935system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 63317577000 # number of ReadExReq MSHR miss cycles 2936system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16586626000 # number of ReadExReq MSHR miss cycles 2937system.l2c.ReadExReq_mshr_miss_latency::total 79904203000 # number of ReadExReq MSHR miss cycles 2938system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of ReadSharedReq MSHR miss cycles 2939system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 153089500 # number of ReadSharedReq MSHR miss cycles 2940system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6862441500 # number of ReadSharedReq MSHR miss cycles 2941system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 15441020000 # number of ReadSharedReq MSHR miss cycles 2942system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of ReadSharedReq MSHR miss cycles 2943system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of ReadSharedReq MSHR miss cycles 2944system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141556000 # number of ReadSharedReq MSHR miss cycles 2945system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6812739500 # number of ReadSharedReq MSHR miss cycles 2946system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10979665500 # number of ReadSharedReq MSHR miss cycles 2947system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of ReadSharedReq MSHR miss cycles 2948system.l2c.ReadSharedReq_mshr_miss_latency::total 87082118457 # number of ReadSharedReq MSHR miss cycles 2949system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of demand (read+write) MSHR miss cycles 2950system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 153089500 # number of demand (read+write) MSHR miss cycles 2951system.l2c.demand_mshr_miss_latency::cpu0.inst 6862441500 # number of demand (read+write) MSHR miss cycles 2952system.l2c.demand_mshr_miss_latency::cpu0.data 78758597000 # number of demand (read+write) MSHR miss cycles 2953system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of demand (read+write) MSHR miss cycles 2954system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of demand (read+write) MSHR miss cycles 2955system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141556000 # number of demand (read+write) MSHR miss cycles 2956system.l2c.demand_mshr_miss_latency::cpu1.inst 6812739500 # number of demand (read+write) MSHR miss cycles 2957system.l2c.demand_mshr_miss_latency::cpu1.data 27566291500 # number of demand (read+write) MSHR miss cycles 2958system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of demand (read+write) MSHR miss cycles 2959system.l2c.demand_mshr_miss_latency::total 166986321457 # number of demand (read+write) MSHR miss cycles 2960system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of overall MSHR miss cycles 2961system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 153089500 # number of overall MSHR miss cycles 2962system.l2c.overall_mshr_miss_latency::cpu0.inst 6862441500 # number of overall MSHR miss cycles 2963system.l2c.overall_mshr_miss_latency::cpu0.data 78758597000 # number of overall MSHR miss cycles 2964system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of overall MSHR miss cycles 2965system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of overall MSHR miss cycles 2966system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141556000 # number of overall MSHR miss cycles 2967system.l2c.overall_mshr_miss_latency::cpu1.inst 6812739500 # number of overall MSHR miss cycles 2968system.l2c.overall_mshr_miss_latency::cpu1.data 27566291500 # number of overall MSHR miss cycles 2969system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of overall MSHR miss cycles 2970system.l2c.overall_mshr_miss_latency::total 166986321457 # number of overall MSHR miss cycles 2971system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of ReadReq MSHR uncacheable cycles 2972system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2064046000 # number of ReadReq MSHR uncacheable cycles 2973system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9850500 # number of ReadReq MSHR uncacheable cycles 2974system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3446902500 # number of ReadReq MSHR uncacheable cycles 2975system.l2c.ReadReq_mshr_uncacheable_latency::total 11417239000 # number of ReadReq MSHR uncacheable cycles 2976system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154023500 # number of WriteReq MSHR uncacheable cycles 2977system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3385027500 # number of WriteReq MSHR uncacheable cycles 2978system.l2c.WriteReq_mshr_uncacheable_latency::total 5539051000 # number of WriteReq MSHR uncacheable cycles 2979system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of overall MSHR uncacheable cycles 2980system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4218069500 # number of overall MSHR uncacheable cycles 2981system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9850500 # number of overall MSHR uncacheable cycles 2982system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6831930000 # number of overall MSHR uncacheable cycles 2983system.l2c.overall_mshr_uncacheable_latency::total 16956290000 # number of overall MSHR uncacheable cycles 2984system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2985system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2986system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.637353 # mshr miss rate for UpgradeReq accesses 2987system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.577245 # mshr miss rate for UpgradeReq accesses 2988system.l2c.UpgradeReq_mshr_miss_rate::total 0.607109 # mshr miss rate for UpgradeReq accesses 2989system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.617680 # mshr miss rate for SCUpgradeReq accesses 2990system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590164 # mshr miss rate for SCUpgradeReq accesses 2991system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.604156 # mshr miss rate for SCUpgradeReq accesses 2992system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733738 # mshr miss rate for ReadExReq accesses 2993system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.429780 # mshr miss rate for ReadExReq accesses 2994system.l2c.ReadExReq_mshr_miss_rate::total 0.635958 # mshr miss rate for ReadExReq accesses 2995system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for ReadSharedReq accesses 2996system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for ReadSharedReq accesses 2997system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for ReadSharedReq accesses 2998system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174987 # mshr miss rate for ReadSharedReq accesses 2999system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for ReadSharedReq accesses 3000system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for ReadSharedReq accesses 3001system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for ReadSharedReq accesses 3002system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for ReadSharedReq accesses 3003system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.138705 # mshr miss rate for ReadSharedReq accesses 3004system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for ReadSharedReq accesses 3005system.l2c.ReadSharedReq_mshr_miss_rate::total 0.164773 # mshr miss rate for ReadSharedReq accesses 3006system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for demand accesses 3007system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for demand accesses 3008system.l2c.demand_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for demand accesses 3009system.l2c.demand_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for demand accesses 3010system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for demand accesses 3011system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for demand accesses 3012system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for demand accesses 3013system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for demand accesses 3014system.l2c.demand_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for demand accesses 3015system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for demand accesses 3016system.l2c.demand_mshr_miss_rate::total 0.259003 # mshr miss rate for demand accesses 3017system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for overall accesses 3018system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for overall accesses 3019system.l2c.overall_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for overall accesses 3020system.l2c.overall_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for overall accesses 3021system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for overall accesses 3022system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for overall accesses 3023system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for overall accesses 3024system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for overall accesses 3025system.l2c.overall_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for overall accesses 3026system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for overall accesses 3027system.l2c.overall_mshr_miss_rate::total 0.259003 # mshr miss rate for overall accesses 3028system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73490.367618 # average UpgradeReq mshr miss latency 3029system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73686.823052 # average UpgradeReq mshr miss latency 3030system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73584.353755 # average UpgradeReq mshr miss latency 3031system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76477.928602 # average SCUpgradeReq mshr miss latency 3032system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76548.726968 # average SCUpgradeReq mshr miss latency 3033system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76511.919371 # average SCUpgradeReq mshr miss latency 3034system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134605.409508 # average ReadExReq mshr miss latency 3035system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126936.197568 # average ReadExReq mshr miss latency 3036system.l2c.ReadExReq_avg_mshr_miss_latency::total 132938.149578 # average ReadExReq mshr miss latency 3037system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average ReadSharedReq mshr miss latency 3038system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average ReadSharedReq mshr miss latency 3039system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average ReadSharedReq mshr miss latency 3040system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128290.295779 # average ReadSharedReq mshr miss latency 3041system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average ReadSharedReq mshr miss latency 3042system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average ReadSharedReq mshr miss latency 3043system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average ReadSharedReq mshr miss latency 3044system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average ReadSharedReq mshr miss latency 3045system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128534.399803 # average ReadSharedReq mshr miss latency 3046system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average ReadSharedReq mshr miss latency 3047system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 139782.944355 # average ReadSharedReq mshr miss latency 3048system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency 3049system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency 3050system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency 3051system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency 3052system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency 3053system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency 3054system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency 3055system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency 3056system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency 3057system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency 3058system.l2c.demand_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency 3059system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency 3060system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency 3061system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency 3062system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency 3063system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency 3064system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency 3065system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency 3066system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency 3067system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency 3068system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency 3069system.l2c.overall_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency 3070system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency 3071system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 141131.350427 # average ReadReq mshr uncacheable latency 3072system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency 3073system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146626.786626 # average ReadReq mshr uncacheable latency 3074system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126109.958690 # average ReadReq mshr uncacheable latency 3075system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 139130.829350 # average WriteReq mshr uncacheable latency 3076system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149965.776183 # average WriteReq mshr uncacheable latency 3077system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145557.654911 # average WriteReq mshr uncacheable latency 3078system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency 3079system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 140102.617332 # average overall mshr uncacheable latency 3080system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency 3081system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148262.369792 # average overall mshr uncacheable latency 3082system.l2c.overall_avg_mshr_uncacheable_latency::total 131865.259589 # average overall mshr uncacheable latency 3083system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3084system.membus.trans_dist::ReadReq 90534 # Transaction distribution 3085system.membus.trans_dist::ReadResp 722459 # Transaction distribution 3086system.membus.trans_dist::WriteReq 38054 # Transaction distribution 3087system.membus.trans_dist::WriteResp 38054 # Transaction distribution 3088system.membus.trans_dist::Writeback 1001017 # Transaction distribution 3089system.membus.trans_dist::CleanEvict 217536 # Transaction distribution 3090system.membus.trans_dist::UpgradeReq 423474 # Transaction distribution 3091system.membus.trans_dist::SCUpgradeReq 287804 # Transaction distribution 3092system.membus.trans_dist::UpgradeResp 114083 # Transaction distribution 3093system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3094system.membus.trans_dist::ReadExReq 614073 # Transaction distribution 3095system.membus.trans_dist::ReadExResp 593351 # Transaction distribution 3096system.membus.trans_dist::ReadSharedReq 631925 # Transaction distribution 3097system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution 3098system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution 3099system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122772 # Packet count per connected master and slave (bytes) 3100system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3101system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24382 # Packet count per connected master and slave (bytes) 3102system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492959 # Packet count per connected master and slave (bytes) 3103system.membus.pkt_count_system.l2c.mem_side::total 4640165 # Packet count per connected master and slave (bytes) 3104system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343288 # Packet count per connected master and slave (bytes) 3105system.membus.pkt_count_system.iocache.mem_side::total 343288 # Packet count per connected master and slave (bytes) 3106system.membus.pkt_count::total 4983453 # Packet count per connected master and slave (bytes) 3107system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155810 # Cumulative packet size per connected master and slave (bytes) 3108system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3109system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48764 # Cumulative packet size per connected master and slave (bytes) 3110system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 138392448 # Cumulative packet size per connected master and slave (bytes) 3111system.membus.pkt_size_system.l2c.mem_side::total 138598346 # Cumulative packet size per connected master and slave (bytes) 3112system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280768 # Cumulative packet size per connected master and slave (bytes) 3113system.membus.pkt_size_system.iocache.mem_side::total 7280768 # Cumulative packet size per connected master and slave (bytes) 3114system.membus.pkt_size::total 145879114 # Cumulative packet size per connected master and slave (bytes) 3115system.membus.snoops 620798 # Total snoops (count) 3116system.membus.snoop_fanout::samples 3413791 # Request fanout histogram 3117system.membus.snoop_fanout::mean 1 # Request fanout histogram 3118system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3119system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3120system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3121system.membus.snoop_fanout::1 3413791 100.00% 100.00% # Request fanout histogram 3122system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3123system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3124system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3125system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3126system.membus.snoop_fanout::total 3413791 # Request fanout histogram 3127system.membus.reqLayer0.occupancy 110035999 # Layer occupancy (ticks) 3128system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3129system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3130system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3131system.membus.reqLayer2.occupancy 20235499 # Layer occupancy (ticks) 3132system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3133system.membus.reqLayer5.occupancy 7135371847 # Layer occupancy (ticks) 3134system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3135system.membus.respLayer2.occupancy 7009823140 # Layer occupancy (ticks) 3136system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3137system.membus.respLayer3.occupancy 230763823 # Layer occupancy (ticks) 3138system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3139system.realview.ethernet.txBytes 966 # Bytes Transmitted 3140system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3141system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3142system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3143system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3144system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3145system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3146system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3147system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3148system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3149system.realview.ethernet.totPackets 3 # Total Packets 3150system.realview.ethernet.totBytes 966 # Total Bytes 3151system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3152system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3153system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3154system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3155system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3156system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3157system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3158system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3159system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3160system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3161system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3162system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3163system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3164system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3165system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3166system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3167system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3168system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3169system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3170system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3171system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3172system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3173system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3174system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3175system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3176system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3177system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3178system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3179system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3180system.realview.ethernet.droppedPackets 0 # number of packets dropped 3181system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 3182system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 3183system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 3184system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3185system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3186system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3187system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 3188system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3189system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3190system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 3191system.toL2Bus.snoop_filter.tot_requests 11297780 # Total number of requests made to the snoop filter. 3192system.toL2Bus.snoop_filter.hit_single_requests 5747695 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3193system.toL2Bus.snoop_filter.hit_multi_requests 2144395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3194system.toL2Bus.snoop_filter.tot_snoops 127398 # Total number of snoops made to the snoop filter. 3195system.toL2Bus.snoop_filter.hit_single_snoops 116260 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3196system.toL2Bus.snoop_filter.hit_multi_snoops 11138 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3197system.toL2Bus.trans_dist::ReadReq 90536 # Transaction distribution 3198system.toL2Bus.trans_dist::ReadResp 4706613 # Transaction distribution 3199system.toL2Bus.trans_dist::WriteReq 38054 # Transaction distribution 3200system.toL2Bus.trans_dist::WriteResp 38054 # Transaction distribution 3201system.toL2Bus.trans_dist::Writeback 3214229 # Transaction distribution 3202system.toL2Bus.trans_dist::CleanEvict 1520051 # Transaction distribution 3203system.toL2Bus.trans_dist::UpgradeReq 472952 # Transaction distribution 3204system.toL2Bus.trans_dist::SCUpgradeReq 299595 # Transaction distribution 3205system.toL2Bus.trans_dist::UpgradeResp 772547 # Transaction distribution 3206system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution 3207system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 3208system.toL2Bus.trans_dist::ReadExReq 1095800 # Transaction distribution 3209system.toL2Bus.trans_dist::ReadExResp 1095800 # Transaction distribution 3210system.toL2Bus.trans_dist::ReadSharedReq 4623306 # Transaction distribution 3211system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution 3212system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8277775 # Packet count per connected master and slave (bytes) 3213system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6810974 # Packet count per connected master and slave (bytes) 3214system.toL2Bus.pkt_count::total 15088749 # Packet count per connected master and slave (bytes) 3215system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 253701939 # Cumulative packet size per connected master and slave (bytes) 3216system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194091607 # Cumulative packet size per connected master and slave (bytes) 3217system.toL2Bus.pkt_size::total 447793546 # Cumulative packet size per connected master and slave (bytes) 3218system.toL2Bus.snoops 2987756 # Total snoops (count) 3219system.toL2Bus.snoop_fanout::samples 12830892 # Request fanout histogram 3220system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram 3221system.toL2Bus.snoop_fanout::stdev 0.481048 # Request fanout histogram 3222system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3223system.toL2Bus.snoop_fanout::0 8255998 64.34% 64.34% # Request fanout histogram 3224system.toL2Bus.snoop_fanout::1 4563756 35.57% 99.91% # Request fanout histogram 3225system.toL2Bus.snoop_fanout::2 11138 0.09% 100.00% # Request fanout histogram 3226system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3227system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3228system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3229system.toL2Bus.snoop_fanout::total 12830892 # Request fanout histogram 3230system.toL2Bus.reqLayer0.occupancy 8297238000 # Layer occupancy (ticks) 3231system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3232system.toL2Bus.snoopLayer0.occupancy 2658855 # Layer occupancy (ticks) 3233system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3234system.toL2Bus.respLayer0.occupancy 4939762812 # Layer occupancy (ticks) 3235system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3236system.toL2Bus.respLayer1.occupancy 4158976314 # Layer occupancy (ticks) 3237system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3238 3239---------- End Simulation Statistics ---------- 3240