110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 47.310816 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 47310816168000 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 279196 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 332505 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 15871048208 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 770320 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 2980.95 # Real time elapsed on the host 1211860Sandreas.hansson@arm.comsim_insts 832269934 # Number of instructions simulated 1311860Sandreas.hansson@arm.comsim_ops 991180133 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory 2411860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory 2611860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory 2711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory 2811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 69383704 # Number of bytes read from this memory 2911860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory 3011860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory 3111860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory 3211860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 84026920 # Number of bytes written to this memory 3611860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory 3711860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory 3811860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory 3911860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory 4011860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory 4111860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory 4211860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory 4311860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory 4411860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory 4511860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory 4611860Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory 4711860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory 4811860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory 5211860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) 5311860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s) 5411860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s) 5511860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s) 5611860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s) 5711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s) 5811860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s) 5911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s) 6011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s) 6111860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s) 6211860Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s) 6311860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s) 6411860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s) 6511860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s) 6611860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s) 6711860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s) 6811754Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6910636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s) 7111860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s) 7211860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) 7311860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s) 7411860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s) 7511860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s) 7611860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s) 7711860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s) 7811860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s) 7911860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s) 8011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s) 8111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s) 8211860Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s) 8311860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s) 8411860Sandreas.hansson@arm.comsystem.physmem.readReqs 1084146 # Number of read requests accepted 8511860Sandreas.hansson@arm.comsystem.physmem.writeReqs 1315173 # Number of write requests accepted 8611860Sandreas.hansson@arm.comsystem.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue 8711860Sandreas.hansson@arm.comsystem.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue 8811860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM 8911860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue 9011860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM 9111860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side 9211860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side 9311860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue 9411860Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 69238 # Per bank write bursts 9711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 72128 # Per bank write bursts 9811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 62859 # Per bank write bursts 9911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 64909 # Per bank write bursts 10011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 64833 # Per bank write bursts 10111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 74280 # Per bank write bursts 10211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 68552 # Per bank write bursts 10311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 74109 # Per bank write bursts 10411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 62269 # Per bank write bursts 10511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 70311 # Per bank write bursts 10611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 59842 # Per bank write bursts 10711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 70232 # Per bank write bursts 10811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 64744 # Per bank write bursts 10911860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 72876 # Per bank write bursts 11011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 66012 # Per bank write bursts 11111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 66520 # Per bank write bursts 11211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 83559 # Per bank write bursts 11311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 83793 # Per bank write bursts 11411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 79464 # Per bank write bursts 11511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 82775 # Per bank write bursts 11611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 80648 # Per bank write bursts 11711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 87124 # Per bank write bursts 11811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 80406 # Per bank write bursts 11911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 83854 # Per bank write bursts 12011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 77300 # Per bank write bursts 12111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 82321 # Per bank write bursts 12211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 78447 # Per bank write bursts 12311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 84798 # Per bank write bursts 12411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 79286 # Per bank write bursts 12511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 85569 # Per bank write bursts 12611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 81705 # Per bank write bursts 12711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 81847 # Per bank write bursts 12810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911860Sandreas.hansson@arm.comsystem.physmem.numWrRetry 404 # Number of times write queue was full causing retry 13011860Sandreas.hansson@arm.comsystem.physmem.totGap 47310814104000 # Total gap between requests 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1084116 # Read request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1312599 # Write request sizes (log2) 14511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 617903 # What read queue length does an incoming req see 14611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 194931 # What read queue length does an incoming req see 14711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 61099 # What read queue length does an incoming req see 14811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 46691 # What read queue length does an incoming req see 14911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 35439 # What read queue length does an incoming req see 15011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 32251 # What read queue length does an incoming req see 15111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 29577 # What read queue length does an incoming req see 15211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 26712 # What read queue length does an incoming req see 15311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 23659 # What read queue length does an incoming req see 15411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 6340 # What read queue length does an incoming req see 15511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 2474 # What read queue length does an incoming req see 15611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1816 # What read queue length does an incoming req see 15711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1451 # What read queue length does an incoming req see 15811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1051 # What read queue length does an incoming req see 15911860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 661 # What read queue length does an incoming req see 16011860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 562 # What read queue length does an incoming req see 16111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 469 # What read queue length does an incoming req see 16211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 366 # What read queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16711860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 25826 # What write queue length does an incoming req see 19311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 33833 # What write queue length does an incoming req see 19411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 51697 # What write queue length does an incoming req see 19511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 60223 # What write queue length does an incoming req see 19611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 67549 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 71954 # What write queue length does an incoming req see 19811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 74550 # What write queue length does an incoming req see 19911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 77056 # What write queue length does an incoming req see 20011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 80172 # What write queue length does an incoming req see 20111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 80848 # What write queue length does an incoming req see 20211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 83842 # What write queue length does an incoming req see 20311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 85747 # What write queue length does an incoming req see 20411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 82598 # What write queue length does an incoming req see 20511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 81110 # What write queue length does an incoming req see 20611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 82972 # What write queue length does an incoming req see 20711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 86524 # What write queue length does an incoming req see 20811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 78237 # What write queue length does an incoming req see 20911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 73594 # What write queue length does an incoming req see 21011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 5576 # What write queue length does an incoming req see 21111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 2994 # What write queue length does an incoming req see 21211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 2165 # What write queue length does an incoming req see 21311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1766 # What write queue length does an incoming req see 21411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 1465 # What write queue length does an incoming req see 21511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 1199 # What write queue length does an incoming req see 21611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 1020 # What write queue length does an incoming req see 21711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 972 # What write queue length does an incoming req see 21811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 852 # What write queue length does an incoming req see 21911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 863 # What write queue length does an incoming req see 22011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 845 # What write queue length does an incoming req see 22111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 859 # What write queue length does an incoming req see 22211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 720 # What write queue length does an incoming req see 22311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 777 # What write queue length does an incoming req see 22411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 704 # What write queue length does an incoming req see 22511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 661 # What write queue length does an incoming req see 22611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 705 # What write queue length does an incoming req see 22711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 720 # What write queue length does an incoming req see 22811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 686 # What write queue length does an incoming req see 22911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 655 # What write queue length does an incoming req see 23011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 659 # What write queue length does an incoming req see 23111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 618 # What write queue length does an incoming req see 23211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 582 # What write queue length does an incoming req see 23311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 844 # What write queue length does an incoming req see 23411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 711 # What write queue length does an incoming req see 23511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 546 # What write queue length does an incoming req see 23611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 766 # What write queue length does an incoming req see 23711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 1149 # What write queue length does an incoming req see 23811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 1102 # What write queue length does an incoming req see 23911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 478 # What write queue length does an incoming req see 24011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 917 # What write queue length does an incoming req see 24111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1043685 # Bytes accessed per row activation 24211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 146.962350 # Bytes accessed per row activation 24311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 99.815605 # Bytes accessed per row activation 24411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 191.425821 # Bytes accessed per row activation 24511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 685015 65.63% 65.63% # Bytes accessed per row activation 24611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 212974 20.41% 86.04% # Bytes accessed per row activation 24711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 53995 5.17% 91.21% # Bytes accessed per row activation 24811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 24749 2.37% 93.59% # Bytes accessed per row activation 24911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 18577 1.78% 95.36% # Bytes accessed per row activation 25011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 11845 1.13% 96.50% # Bytes accessed per row activation 25111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 7907 0.76% 97.26% # Bytes accessed per row activation 25211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 6706 0.64% 97.90% # Bytes accessed per row activation 25311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation 25411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation 25511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 65638 # Reads before turning the bus around for writes 25611860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes 25711860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 26.150337 # Reads before turning the bus around for writes 25811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-255 65626 99.98% 99.98% # Reads before turning the bus around for writes 25911860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes 26011860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 26111860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes 26211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes 26311860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes 26411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 65638 # Writes before turning the bus around for reads 26511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads 26611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads 26711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads 26811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 57560 87.69% 87.69% # Writes before turning the bus around for reads 26911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 2491 3.80% 91.49% # Writes before turning the bus around for reads 27011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads 27111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads 27211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads 27311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads 27411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads 27511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads 27611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads 27711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads 27811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads 27911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads 28011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads 28111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads 28211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads 28311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads 28411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads 28511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 63 0.10% 98.86% # Writes before turning the bus around for reads 28611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 64 0.10% 98.95% # Writes before turning the bus around for reads 28711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads 28811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads 28911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads 29011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 89 0.14% 99.46% # Writes before turning the bus around for reads 29111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 57 0.09% 99.54% # Writes before turning the bus around for reads 29211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 53 0.08% 99.63% # Writes before turning the bus around for reads 29311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads 29411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads 29511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads 29611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 43 0.07% 99.89% # Writes before turning the bus around for reads 29711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads 29811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads 29911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads 30011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads 30111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 2 0.00% 99.96% # Writes before turning the bus around for reads 30211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads 30311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 5 0.01% 99.97% # Writes before turning the bus around for reads 30411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads 30511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads 30611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads 30711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads 30811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads 30911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads 31011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads 31111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads 31211860Sandreas.hansson@arm.comsystem.physmem.totQLat 57570179828 # Total ticks spent queuing 31311860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM 31411860Sandreas.hansson@arm.comsystem.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers 31511860Sandreas.hansson@arm.comsystem.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst 31610515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31711860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst 31811860Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s 31911860Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s 32011860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s 32111860Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s 32210515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32311860Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 32411353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32511441Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32611860Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing 32711860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing 32811860Sandreas.hansson@arm.comsystem.physmem.readRowHits 798943 # Number of row buffer hits during reads 32911860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 553978 # Number of row buffer hits during writes 33011860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads 33111860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes 33211860Sandreas.hansson@arm.comsystem.physmem.avgGap 19718434.32 # Average gap between requests 33311860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined 33411860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ) 33511860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ) 33611860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ) 33711860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ) 33811860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ) 33911860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ) 34011860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ) 34111860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ) 34211860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ) 34311860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ) 34411860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ) 34511860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 242.939265 # Core power per rank (mW) 34611860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank 34711860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states 34811860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states 34911860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states 35011860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states 35111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states 35211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states 35311860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ) 35411860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ) 35511860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ) 35611860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ) 35711860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ) 35811860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ) 35911860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ) 36011860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ) 36111860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ) 36211860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ) 36311860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ) 36411860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 242.827762 # Core power per rank (mW) 36511860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank 36611860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states 36711860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states 36811860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states 36911860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states 37011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states 37111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states 37211860Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 37310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 37511570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 37610636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 37711570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 37810515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 37911570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 38011570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 38110636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 38210636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 38311570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 38410636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 38511570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 38610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 38710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 38811754Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) 38910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 39011570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 39110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 39211754Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) 39311570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 39410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 39510636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 39611754Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) 39710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 39811570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 39911860Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 40011860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 40111860Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 40210585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 40310585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 40410585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 40511606Sandreas.sandberg@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 40611606Sandreas.sandberg@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 40711606Sandreas.sandberg@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 40811860Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 116746639 # Number of BP lookups 40911860Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted 41011860Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect 41111860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups 41211860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits 41310585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 41411860Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage 41511860Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target. 41611860Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions. 41711860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups. 41811860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits. 41911860Sandreas.hansson@arm.comsystem.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses. 42011860Sandreas.hansson@arm.comsystem.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches. 42110515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 42211860Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 42310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 42410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 42710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 42810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 43110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 43410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 43510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 43610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 43710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 43810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 43910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 44010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 44110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 44210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 44310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 44410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 44510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 44610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 44710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 44810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 44910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 45010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 45110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 45211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 45311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 291933 # Table walker walks requested 45411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors 45511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate 45611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate 45711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency 45811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency 45911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency 46011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency 46111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency 46211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency 46311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency 46411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency 46511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency 46611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency 46711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency 46811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency 46911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency 47011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 47111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 47211860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 47311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 47411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency 47511860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution 47611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution 47711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution 47811860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated 47911860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated 48011860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated 48111860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst 48210628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48311860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst 48411860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48611860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst 48711860Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst 48810585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 48910585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 49011860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 91107490 # DTB read hits 49111860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 238663 # DTB read misses 49211860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 81148084 # DTB write hits 49311860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 53270 # DTB write misses 49411441Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 49510585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49611860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID 49711860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 49811860Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB 49911860Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions 50011860Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch 50110585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 50211860Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions 50311860Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 91346153 # DTB read accesses 50411860Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 81201354 # DTB write accesses 50510585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 50611860Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 172255574 # DTB hits 50711860Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 291933 # DTB misses 50811860Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 172547507 # DTB accesses 50911860Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 51010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 51110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 51210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 51310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 51410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 51510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 51610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 51710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 52110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 52410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 52510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 52710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 53110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 53210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 53310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 53410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 53510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 53610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 53710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 53810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 53911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 54011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 65131 # Table walker walks requested 54111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors 54211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate 54311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate 54411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency 54511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency 54611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency 54711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency 54811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency 54911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency 55011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency 55111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency 55211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency 55311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency 55411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency 55511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency 55611860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 55711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency 55811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency 55911860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency 56011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution 56111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution 56211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution 56311860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated 56411860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated 56511860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated 56610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 56711860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst 56811860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst 56910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 57011860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst 57111860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst 57211860Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst 57311860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 201165320 # ITB inst hits 57411860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 65131 # ITB inst misses 57510585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 57610585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 57710585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 57810585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 57911441Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 58010585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58111860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID 58211860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 58311860Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB 58410585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 58510585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58610585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58711860Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions 58810585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 58910585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 59011860Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 201230451 # ITB inst accesses 59111860Sandreas.hansson@arm.comsystem.cpu0.itb.hits 201165320 # DTB hits 59211860Sandreas.hansson@arm.comsystem.cpu0.itb.misses 65131 # DTB misses 59311860Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 201230451 # DTB accesses 59411860Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 27066 # Number of power state transitions 59511860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state 59611860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state 59711860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state 59811860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state 59911860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state 60011754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 60111754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 60211860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 60311754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 60411860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 60511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 60611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 60711860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 60811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 60911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 61011860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state 61111860Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state 61211860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states 61311860Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states 61411860Sandreas.hansson@arm.comsystem.cpu0.numCycles 923231946 # number of cpu cycles simulated 61510585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 61610585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 61711860Sandreas.hansson@arm.comsystem.cpu0.committedInsts 433947137 # Number of instructions committed 61811860Sandreas.hansson@arm.comsystem.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed 61911860Sandreas.hansson@arm.comsystem.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit 62011860Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching 62111860Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 62211860Sandreas.hansson@arm.comsystem.cpu0.cpi 2.127522 # CPI: cycles per instruction 62311860Sandreas.hansson@arm.comsystem.cpu0.ipc 0.470030 # IPC: instructions per cycle 62411860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 62511860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction 62611860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction 62711860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction 62811860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction 62911860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction 63011860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction 63111860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction 63211860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction 63311860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction 63411860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction 63511860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction 63611860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction 63711860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction 63811860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction 63911860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction 64011860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction 64111860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction 64211860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction 64311860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction 64411860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction 64511860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction 64611860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction 64711860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction 64811860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction 64911860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction 65011860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction 65111860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction 65211860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction 65311860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction 65411860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction 65511860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction 65611860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction 65711860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction 65811860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction 65911860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction 66011441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 66111441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 66211860Sandreas.hansson@arm.comsystem.cpu0.op_class_0::total 516803462 # Class of committed instruction 66310585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 66411860Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed 66511860Sandreas.hansson@arm.comsystem.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked 66611860Sandreas.hansson@arm.comsystem.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped 66711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 66811860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6005277 # number of replacements 66911860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use 67011860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks. 67111860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks. 67211860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks. 67311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit. 67411860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor 67511860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy 67611860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy 67711860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 67811860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 67911860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id 68011860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id 68111860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 68211860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses 68311860Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses 68411860Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 68511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits 68611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits 68711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 75142855 # number of WriteReq hits 68811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 75142855 # number of WriteReq hits 68911860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits 69011860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits 69111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits 69211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits 69311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits 69411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits 69511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1839620 # number of StoreCondReq hits 69611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits 69711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 158957916 # number of demand (read+write) hits 69811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 158957916 # number of demand (read+write) hits 69911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 159232945 # number of overall hits 70011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 159232945 # number of overall hits 70111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses 70211860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses 70311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses 70411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2596834 # number of WriteReq misses 70511860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses 70611860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses 70711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses 70811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses 70911860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses 71011860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 164864 # number of LoadLockedReq misses 71111860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 202355 # number of StoreCondReq misses 71211860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 202355 # number of StoreCondReq misses 71311860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 6797232 # number of demand (read+write) misses 71411860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 6797232 # number of demand (read+write) misses 71511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 7527165 # number of overall misses 71611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 7527165 # number of overall misses 71711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55240233000 # number of ReadReq miss cycles 71811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 55240233000 # number of ReadReq miss cycles 71911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55000663500 # number of WriteReq miss cycles 72011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 55000663500 # number of WriteReq miss cycles 72111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26000939500 # number of WriteLineReq miss cycles 72211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 26000939500 # number of WriteLineReq miss cycles 72311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2528136500 # number of LoadLockedReq miss cycles 72411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2528136500 # number of LoadLockedReq miss cycles 72511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4851897500 # number of StoreCondReq miss cycles 72611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4851897500 # number of StoreCondReq miss cycles 72711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2304500 # number of StoreCondFailReq miss cycles 72811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2304500 # number of StoreCondFailReq miss cycles 72911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 136241836000 # number of demand (read+write) miss cycles 73011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 136241836000 # number of demand (read+write) miss cycles 73111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 136241836000 # number of overall miss cycles 73211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 136241836000 # number of overall miss cycles 73311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 87029633 # number of ReadReq accesses(hits+misses) 73411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 87029633 # number of ReadReq accesses(hits+misses) 73511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 77739689 # number of WriteReq accesses(hits+misses) 73611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 77739689 # number of WriteReq accesses(hits+misses) 73711860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1004962 # number of SoftPFReq accesses(hits+misses) 73811860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 1004962 # number of SoftPFReq accesses(hits+misses) 73911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 985826 # number of WriteLineReq accesses(hits+misses) 74011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 985826 # number of WriteLineReq accesses(hits+misses) 74111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2043167 # number of LoadLockedReq accesses(hits+misses) 74211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2043167 # number of LoadLockedReq accesses(hits+misses) 74311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041975 # number of StoreCondReq accesses(hits+misses) 74411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2041975 # number of StoreCondReq accesses(hits+misses) 74511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 165755148 # number of demand (read+write) accesses 74611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 165755148 # number of demand (read+write) accesses 74711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 166760110 # number of overall (read+write) accesses 74811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 166760110 # number of overall (read+write) accesses 74911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038983 # miss rate for ReadReq accesses 75011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.038983 # miss rate for ReadReq accesses 75111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033404 # miss rate for WriteReq accesses 75211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.033404 # miss rate for WriteReq accesses 75311860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.726329 # miss rate for SoftPFReq accesses 75411860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.726329 # miss rate for SoftPFReq accesses 75511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.819328 # miss rate for WriteLineReq accesses 75611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.819328 # miss rate for WriteLineReq accesses 75711860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080690 # miss rate for LoadLockedReq accesses 75811860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080690 # miss rate for LoadLockedReq accesses 75911860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099098 # miss rate for StoreCondReq accesses 76011860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.099098 # miss rate for StoreCondReq accesses 76111860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.041008 # miss rate for demand accesses 76211860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.041008 # miss rate for demand accesses 76311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.045138 # miss rate for overall accesses 76411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.045138 # miss rate for overall accesses 76511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency 76611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 16282.167535 # average ReadReq miss latency 76711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21179.891938 # average WriteReq miss latency 76811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency 76911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency 77011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency 77111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15334.678887 # average LoadLockedReq miss latency 77211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15334.678887 # average LoadLockedReq miss latency 77311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23977.156482 # average StoreCondReq miss latency 77411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency 77510636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 77610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 77711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20043.723092 # average overall miss latency 77811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 20043.723092 # average overall miss latency 77911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18100.019861 # average overall miss latency 78011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 18100.019861 # average overall miss latency 78110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 78210585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78310585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78410585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 78510585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78610585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78711860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 6005280 # number of writebacks 78811860Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 6005280 # number of writebacks 78911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 217816 # number of ReadReq MSHR hits 79011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 217816 # number of ReadReq MSHR hits 79111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1084214 # number of WriteReq MSHR hits 79211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1084214 # number of WriteReq MSHR hits 79311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 111 # number of WriteLineReq MSHR hits 79411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 111 # number of WriteLineReq MSHR hits 79511860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44378 # number of LoadLockedReq MSHR hits 79611860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 44378 # number of LoadLockedReq MSHR hits 79711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 58 # number of StoreCondReq MSHR hits 79811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits 79911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1302141 # number of demand (read+write) MSHR hits 80011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1302141 # number of demand (read+write) MSHR hits 80111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1302141 # number of overall MSHR hits 80211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1302141 # number of overall MSHR hits 80311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3174867 # number of ReadReq MSHR misses 80411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3174867 # number of ReadReq MSHR misses 80511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1512620 # number of WriteReq MSHR misses 80611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1512620 # number of WriteReq MSHR misses 80711860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 727670 # number of SoftPFReq MSHR misses 80811860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 727670 # number of SoftPFReq MSHR misses 80911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 807604 # number of WriteLineReq MSHR misses 81011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 807604 # number of WriteLineReq MSHR misses 81111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120486 # number of LoadLockedReq MSHR misses 81211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 120486 # number of LoadLockedReq MSHR misses 81311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202297 # number of StoreCondReq MSHR misses 81411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 202297 # number of StoreCondReq MSHR misses 81511860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5495091 # number of demand (read+write) MSHR misses 81611860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5495091 # number of demand (read+write) MSHR misses 81711860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 6222761 # number of overall MSHR misses 81811860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 6222761 # number of overall MSHR misses 81911860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable 82011860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 32770 # number of ReadReq MSHR uncacheable 82111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable 82211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable 82311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses 82411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 65503 # number of overall MSHR uncacheable misses 82511860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46331358000 # number of ReadReq MSHR miss cycles 82611860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 46331358000 # number of ReadReq MSHR miss cycles 82711860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30906822000 # number of WriteReq MSHR miss cycles 82811860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 30906822000 # number of WriteReq MSHR miss cycles 82911860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18329110000 # number of SoftPFReq MSHR miss cycles 83011860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18329110000 # number of SoftPFReq MSHR miss cycles 83111860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25186211500 # number of WriteLineReq MSHR miss cycles 83211860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25186211500 # number of WriteLineReq MSHR miss cycles 83311860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1650103500 # number of LoadLockedReq MSHR miss cycles 83411860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1650103500 # number of LoadLockedReq MSHR miss cycles 83511860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4648318000 # number of StoreCondReq MSHR miss cycles 83611860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4648318000 # number of StoreCondReq MSHR miss cycles 83711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1886000 # number of StoreCondFailReq MSHR miss cycles 83811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1886000 # number of StoreCondFailReq MSHR miss cycles 83911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102424391500 # number of demand (read+write) MSHR miss cycles 84011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 102424391500 # number of demand (read+write) MSHR miss cycles 84111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 120753501500 # number of overall MSHR miss cycles 84211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 120753501500 # number of overall MSHR miss cycles 84311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6287102500 # number of ReadReq MSHR uncacheable cycles 84411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6287102500 # number of ReadReq MSHR uncacheable cycles 84511860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6287102500 # number of overall MSHR uncacheable cycles 84611860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 6287102500 # number of overall MSHR uncacheable cycles 84711860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036480 # mshr miss rate for ReadReq accesses 84811860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036480 # mshr miss rate for ReadReq accesses 84911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019458 # mshr miss rate for WriteReq accesses 85011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019458 # mshr miss rate for WriteReq accesses 85111860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.724077 # mshr miss rate for SoftPFReq accesses 85211860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.724077 # mshr miss rate for SoftPFReq accesses 85311860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.819216 # mshr miss rate for WriteLineReq accesses 85411860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.819216 # mshr miss rate for WriteLineReq accesses 85511860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058970 # mshr miss rate for LoadLockedReq accesses 85611860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058970 # mshr miss rate for LoadLockedReq accesses 85711860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099069 # mshr miss rate for StoreCondReq accesses 85811860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099069 # mshr miss rate for StoreCondReq accesses 85911860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033152 # mshr miss rate for demand accesses 86011860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.033152 # mshr miss rate for demand accesses 86111860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037316 # mshr miss rate for overall accesses 86211860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.037316 # mshr miss rate for overall accesses 86311860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14593.165005 # average ReadReq mshr miss latency 86411860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14593.165005 # average ReadReq mshr miss latency 86511860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20432.641377 # average WriteReq mshr miss latency 86611860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20432.641377 # average WriteReq mshr miss latency 86711860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25188.766886 # average SoftPFReq mshr miss latency 86811860Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency 86911860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31186.338230 # average WriteLineReq mshr miss latency 87011860Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency 87111860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13695.396146 # average LoadLockedReq mshr miss latency 87211860Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency 87311860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22977.691216 # average StoreCondReq mshr miss latency 87411860Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency 87510636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 87610585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 87711860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18639.253017 # average overall mshr miss latency 87811860Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18639.253017 # average overall mshr miss latency 87911860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19405.132465 # average overall mshr miss latency 88011860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19405.132465 # average overall mshr miss latency 88111860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191855.431797 # average ReadReq mshr uncacheable latency 88211860Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191855.431797 # average ReadReq mshr uncacheable latency 88311860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95981.901592 # average overall mshr uncacheable latency 88411860Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95981.901592 # average overall mshr uncacheable latency 88511860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 88611860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 9998472 # number of replacements 88711860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.981180 # Cycle average of tags in use 88811860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 190986664 # Total number of references to valid blocks. 88911860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 9998984 # Sample count of references to valid blocks. 89011860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 19.100607 # Average number of references to valid blocks. 89111860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 18008070000 # Cycle when the warmup percentage was hit. 89211860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.981180 # Average occupied blocks per requestor 89311860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999963 # Average percentage of cache occupancy 89411860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy 89510585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 89611860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id 89711860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id 89811860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 89910585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 90011860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses 90111860Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses 90211860Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 90311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 190986664 # number of ReadReq hits 90411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 190986664 # number of ReadReq hits 90511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 190986664 # number of demand (read+write) hits 90611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 190986664 # number of demand (read+write) hits 90711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 190986664 # number of overall hits 90811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 190986664 # number of overall hits 90911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9998995 # number of ReadReq misses 91011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 9998995 # number of ReadReq misses 91111860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9998995 # number of demand (read+write) misses 91211860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 9998995 # number of demand (read+write) misses 91311860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9998995 # number of overall misses 91411860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 9998995 # number of overall misses 91511860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104315202000 # number of ReadReq miss cycles 91611860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles 91711860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 104315202000 # number of demand (read+write) miss cycles 91811860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 104315202000 # number of demand (read+write) miss cycles 91911860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 104315202000 # number of overall miss cycles 92011860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles 92111860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses) 92211860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 200985659 # number of ReadReq accesses(hits+misses) 92311860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 200985659 # number of demand (read+write) accesses 92411860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 200985659 # number of demand (read+write) accesses 92511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 200985659 # number of overall (read+write) accesses 92611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 200985659 # number of overall (read+write) accesses 92711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049750 # miss rate for ReadReq accesses 92811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.049750 # miss rate for ReadReq accesses 92911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.049750 # miss rate for demand accesses 93011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.049750 # miss rate for demand accesses 93111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.049750 # miss rate for overall accesses 93211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.049750 # miss rate for overall accesses 93311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.568673 # average ReadReq miss latency 93411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency 93511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency 93611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency 93711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency 93811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # average overall miss latency 93910585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 94010585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 94110585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 94210585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 94310585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 94410585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 94511860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 9998472 # number of writebacks 94611860Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 9998472 # number of writebacks 94711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9998995 # number of ReadReq MSHR misses 94811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9998995 # number of ReadReq MSHR misses 94911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9998995 # number of demand (read+write) MSHR misses 95011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9998995 # number of demand (read+write) MSHR misses 95111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9998995 # number of overall MSHR misses 95211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9998995 # number of overall MSHR misses 95311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable 95411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 4283 # number of ReadReq MSHR uncacheable 95511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses 95611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 4283 # number of overall MSHR uncacheable misses 95711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99315705000 # number of ReadReq MSHR miss cycles 95811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 99315705000 # number of ReadReq MSHR miss cycles 95911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99315705000 # number of demand (read+write) MSHR miss cycles 96011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 99315705000 # number of demand (read+write) MSHR miss cycles 96111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99315705000 # number of overall MSHR miss cycles 96211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 99315705000 # number of overall MSHR miss cycles 96311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 427814500 # number of ReadReq MSHR uncacheable cycles 96411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 427814500 # number of ReadReq MSHR uncacheable cycles 96511860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 427814500 # number of overall MSHR uncacheable cycles 96611860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 427814500 # number of overall MSHR uncacheable cycles 96711860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for ReadReq accesses 96811860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.049750 # mshr miss rate for ReadReq accesses 96911860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for demand accesses 97011860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.049750 # mshr miss rate for demand accesses 97111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for overall accesses 97211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.049750 # mshr miss rate for overall accesses 97311860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average ReadReq mshr miss latency 97411860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.568723 # average ReadReq mshr miss latency 97511860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency 97611860Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency 97711860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency 97811860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency 97911860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average ReadReq mshr uncacheable latency 98011860Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 99886.644875 # average ReadReq mshr uncacheable latency 98111860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average overall mshr uncacheable latency 98211860Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 99886.644875 # average overall mshr uncacheable latency 98311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 98411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 8169933 # number of hwpf issued 98511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 8171403 # number of prefetch candidates identified 98611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1304 # number of redundant prefetches already in prefetch queue 98710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1047741 # number of prefetches not generated due to page crossing 99011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 99111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2932551 # number of replacements 99211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15705.924224 # Cycle average of tags in use 99311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 14272950 # Total number of references to valid blocks. 99411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2948325 # Sample count of references to valid blocks. 99511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 4.841037 # Average number of references to valid blocks. 99611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1130072000 # Cycle when the warmup percentage was hit. 99711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15376.526197 # Average occupied blocks per requestor 99811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 37.361518 # Average occupied blocks per requestor 99911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 20.248621 # Average occupied blocks per requestor 100011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 271.787888 # Average occupied blocks per requestor 100111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.938509 # Average percentage of cache occupancy 100211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002280 # Average percentage of cache occupancy 100311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001236 # Average percentage of cache occupancy 100411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016589 # Average percentage of cache occupancy 100511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.958614 # Average percentage of cache occupancy 100611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 362 # Occupied blocks per task id 100711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id 100811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id 100911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 101011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 176 # Occupied blocks per task id 101111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id 101211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id 101311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id 101411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 101511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 101611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id 101711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2130 # Occupied blocks per task id 101811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6262 # Occupied blocks per task id 101911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5229 # Occupied blocks per task id 102011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id 102111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022095 # Percentage of cache occupancy per task id 102211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id 102311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id 102411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 549297414 # Number of tag accesses 102511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 549297414 # Number of data accesses 102611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 102711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539317 # number of ReadReq hits 102811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 165054 # number of ReadReq hits 102911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 704371 # number of ReadReq hits 103011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3976191 # number of WritebackDirty hits 103111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3976191 # number of WritebackDirty hits 103211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 12024318 # number of WritebackClean hits 103311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 12024318 # number of WritebackClean hits 103411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 971762 # number of ReadExReq hits 103511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 971762 # number of ReadExReq hits 103611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9224160 # number of ReadCleanReq hits 103711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 9224160 # number of ReadCleanReq hits 103811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2947596 # number of ReadSharedReq hits 103911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2947596 # number of ReadSharedReq hits 104011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 209682 # number of InvalidateReq hits 104111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 209682 # number of InvalidateReq hits 104211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539317 # number of demand (read+write) hits 104311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 165054 # number of demand (read+write) hits 104411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 9224160 # number of demand (read+write) hits 104511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3919358 # number of demand (read+write) hits 104611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 13847889 # number of demand (read+write) hits 104711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539317 # number of overall hits 104811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 165054 # number of overall hits 104911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 9224160 # number of overall hits 105011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3919358 # number of overall hits 105111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 13847889 # number of overall hits 105211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21966 # number of ReadReq misses 105311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10468 # number of ReadReq misses 105411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 32434 # number of ReadReq misses 105511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 105611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 105711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257791 # number of UpgradeReq misses 105811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 257791 # number of UpgradeReq misses 105911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202293 # number of SCUpgradeReq misses 106011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 202293 # number of SCUpgradeReq misses 106111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 106211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 106311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 289245 # number of ReadExReq misses 106411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 289245 # number of ReadExReq misses 106511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 774834 # number of ReadCleanReq misses 106611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 774834 # number of ReadCleanReq misses 106711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1075153 # number of ReadSharedReq misses 106811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1075153 # number of ReadSharedReq misses 106911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597922 # number of InvalidateReq misses 107011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 597922 # number of InvalidateReq misses 107111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21966 # number of demand (read+write) misses 107211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 10468 # number of demand (read+write) misses 107311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 774834 # number of demand (read+write) misses 107411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1364398 # number of demand (read+write) misses 107511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2171666 # number of demand (read+write) misses 107611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21966 # number of overall misses 107711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 10468 # number of overall misses 107811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 774834 # number of overall misses 107911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1364398 # number of overall misses 108011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2171666 # number of overall misses 108111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 715984000 # number of ReadReq miss cycles 108211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 391759500 # number of ReadReq miss cycles 108311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 1107743500 # number of ReadReq miss cycles 108411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 860565000 # number of UpgradeReq miss cycles 108511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 860565000 # number of UpgradeReq miss cycles 108611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 334549500 # number of SCUpgradeReq miss cycles 108711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 334549500 # number of SCUpgradeReq miss cycles 108811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1814999 # number of SCUpgradeFailReq miss cycles 108911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1814999 # number of SCUpgradeFailReq miss cycles 109011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15808379497 # number of ReadExReq miss cycles 109111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 15808379497 # number of ReadExReq miss cycles 109211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 28621690500 # number of ReadCleanReq miss cycles 109311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 28621690500 # number of ReadCleanReq miss cycles 109411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40818686990 # number of ReadSharedReq miss cycles 109511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 40818686990 # number of ReadSharedReq miss cycles 109611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles 109711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles 109811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 715984000 # number of demand (read+write) miss cycles 109911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 391759500 # number of demand (read+write) miss cycles 110011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 28621690500 # number of demand (read+write) miss cycles 110111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 56627066487 # number of demand (read+write) miss cycles 110211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 86356500487 # number of demand (read+write) miss cycles 110311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 715984000 # number of overall miss cycles 110411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 391759500 # number of overall miss cycles 110511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 28621690500 # number of overall miss cycles 110611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 56627066487 # number of overall miss cycles 110711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 86356500487 # number of overall miss cycles 110811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 561283 # number of ReadReq accesses(hits+misses) 110911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175522 # number of ReadReq accesses(hits+misses) 111011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 736805 # number of ReadReq accesses(hits+misses) 111111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3976191 # number of WritebackDirty accesses(hits+misses) 111211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3976191 # number of WritebackDirty accesses(hits+misses) 111311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 12024319 # number of WritebackClean accesses(hits+misses) 111411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 12024319 # number of WritebackClean accesses(hits+misses) 111511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257791 # number of UpgradeReq accesses(hits+misses) 111611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 257791 # number of UpgradeReq accesses(hits+misses) 111711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202293 # number of SCUpgradeReq accesses(hits+misses) 111811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 202293 # number of SCUpgradeReq accesses(hits+misses) 111911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 112011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 112111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1261007 # number of ReadExReq accesses(hits+misses) 112211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1261007 # number of ReadExReq accesses(hits+misses) 112311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9998994 # number of ReadCleanReq accesses(hits+misses) 112411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9998994 # number of ReadCleanReq accesses(hits+misses) 112511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4022749 # number of ReadSharedReq accesses(hits+misses) 112611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4022749 # number of ReadSharedReq accesses(hits+misses) 112711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 807604 # number of InvalidateReq accesses(hits+misses) 112811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 807604 # number of InvalidateReq accesses(hits+misses) 112911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 561283 # number of demand (read+write) accesses 113011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175522 # number of demand (read+write) accesses 113111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9998994 # number of demand (read+write) accesses 113211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5283756 # number of demand (read+write) accesses 113311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 16019555 # number of demand (read+write) accesses 113411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 561283 # number of overall (read+write) accesses 113511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175522 # number of overall (read+write) accesses 113611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9998994 # number of overall (read+write) accesses 113711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5283756 # number of overall (read+write) accesses 113811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 16019555 # number of overall (read+write) accesses 113911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for ReadReq accesses 114011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059639 # miss rate for ReadReq accesses 114111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.044020 # miss rate for ReadReq accesses 114211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 114311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 114411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 114511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 114611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 114711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 114810636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 114910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 115011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.229376 # miss rate for ReadExReq accesses 115111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.229376 # miss rate for ReadExReq accesses 115211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.077491 # miss rate for ReadCleanReq accesses 115311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.077491 # miss rate for ReadCleanReq accesses 115411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267268 # miss rate for ReadSharedReq accesses 115511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267268 # miss rate for ReadSharedReq accesses 115611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.740365 # miss rate for InvalidateReq accesses 115711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.740365 # miss rate for InvalidateReq accesses 115811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for demand accesses 115911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059639 # miss rate for demand accesses 116011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.077491 # miss rate for demand accesses 116111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258225 # miss rate for demand accesses 116211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.135563 # miss rate for demand accesses 116311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for overall accesses 116411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059639 # miss rate for overall accesses 116511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.077491 # miss rate for overall accesses 116611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258225 # miss rate for overall accesses 116711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.135563 # miss rate for overall accesses 116811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average ReadReq miss latency 116911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37424.484142 # average ReadReq miss latency 117011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 34153.773818 # average ReadReq miss latency 117111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3338.227479 # average UpgradeReq miss latency 117211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3338.227479 # average UpgradeReq miss latency 117311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1653.786834 # average SCUpgradeReq miss latency 117411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1653.786834 # average SCUpgradeReq miss latency 117511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 453749.750000 # average SCUpgradeFailReq miss latency 117611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 453749.750000 # average SCUpgradeFailReq miss latency 117711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54653.942149 # average ReadExReq miss latency 117811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54653.942149 # average ReadExReq miss latency 117911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 36939.125671 # average ReadCleanReq miss latency 118011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 36939.125671 # average ReadCleanReq miss latency 118111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37965.468161 # average ReadSharedReq miss latency 118211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37965.468161 # average ReadSharedReq miss latency 118311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.173936 # average InvalidateReq miss latency 118411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.173936 # average InvalidateReq miss latency 118511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency 118611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency 118711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency 118811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency 118911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 39765.093015 # average overall miss latency 119011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency 119111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency 119211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency 119311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency 119411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 39765.093015 # average overall miss latency 119511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked 119610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 119810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 119911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 92 # average number of cycles each access was blocked 120010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 120111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.unused_prefetches 48917 # number of HardPF blocks evicted w/o reference 120211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1795601 # number of writebacks 120311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1795601 # number of writebacks 120411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits 120511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 90 # number of ReadReq MSHR hits 120611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 120711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10129 # number of ReadExReq MSHR hits 120811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 10129 # number of ReadExReq MSHR hits 120911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits 121011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 121111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 992 # number of ReadSharedReq MSHR hits 121211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 992 # number of ReadSharedReq MSHR hits 121311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits 121411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 121511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits 121611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 90 # number of demand (read+write) MSHR hits 121711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits 121811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 11121 # number of demand (read+write) MSHR hits 121911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits 122011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits 122111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 90 # number of overall MSHR hits 122211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits 122311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 11121 # number of overall MSHR hits 122411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 11245 # number of overall MSHR hits 122511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21943 # number of ReadReq MSHR misses 122611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10378 # number of ReadReq MSHR misses 122711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 32321 # number of ReadReq MSHR misses 122811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 122911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 123011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of HardPFReq MSHR misses 123111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 836449 # number of HardPFReq MSHR misses 123211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257791 # number of UpgradeReq MSHR misses 123311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 257791 # number of UpgradeReq MSHR misses 123411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202293 # number of SCUpgradeReq MSHR misses 123511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202293 # number of SCUpgradeReq MSHR misses 123611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 123711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 123811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 279116 # number of ReadExReq MSHR misses 123911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 279116 # number of ReadExReq MSHR misses 124011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 774823 # number of ReadCleanReq MSHR misses 124111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 774823 # number of ReadCleanReq MSHR misses 124211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074161 # number of ReadSharedReq MSHR misses 124311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074161 # number of ReadSharedReq MSHR misses 124411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 597920 # number of InvalidateReq MSHR misses 124511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 597920 # number of InvalidateReq MSHR misses 124611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21943 # number of demand (read+write) MSHR misses 124711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10378 # number of demand (read+write) MSHR misses 124811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 774823 # number of demand (read+write) MSHR misses 124911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353277 # number of demand (read+write) MSHR misses 125011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 2160421 # number of demand (read+write) MSHR misses 125111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21943 # number of overall MSHR misses 125211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10378 # number of overall MSHR misses 125311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 774823 # number of overall MSHR misses 125411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353277 # number of overall MSHR misses 125511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of overall MSHR misses 125611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2996870 # number of overall MSHR misses 125711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable 125811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable 125911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37053 # number of ReadReq MSHR uncacheable 126011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable 126111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable 126211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses 126311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses 126411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69786 # number of overall MSHR uncacheable misses 126511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of ReadReq MSHR miss cycles 126611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 328079000 # number of ReadReq MSHR miss cycles 126711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 911857500 # number of ReadReq MSHR miss cycles 126811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of HardPFReq MSHR miss cycles 126911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44903675775 # number of HardPFReq MSHR miss cycles 127011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4788332493 # number of UpgradeReq MSHR miss cycles 127111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4788332493 # number of UpgradeReq MSHR miss cycles 127211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3126512997 # number of SCUpgradeReq MSHR miss cycles 127311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3126512997 # number of SCUpgradeReq MSHR miss cycles 127411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1538999 # number of SCUpgradeFailReq MSHR miss cycles 127511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1538999 # number of SCUpgradeFailReq MSHR miss cycles 127611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12740129497 # number of ReadExReq MSHR miss cycles 127711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12740129497 # number of ReadExReq MSHR miss cycles 127811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23972456500 # number of ReadCleanReq MSHR miss cycles 127911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles 128011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles 128111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles 128211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles 128311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles 128411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles 128511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles 128611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles 128711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles 128811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles 128911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles 129011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles 129111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles 129211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles 129311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles 129411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles 129511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles 129611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles 129711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles 129811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles 129911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles 130011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles 130111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses 130211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses 130311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses 130411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 130511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 130610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 130710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 130811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 130911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 131011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 131111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 131210636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 131310585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 131411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses 131511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses 131611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses 131711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses 131811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses 131911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses 132011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses 132111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses 132211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses 132311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses 132411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses 132511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses 132611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses 132711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses 132811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses 132911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses 133011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses 133110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 133211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses 133311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency 133411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency 133511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency 133611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency 133711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency 133811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency 133911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency 134011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency 134111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency 134211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency 134311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency 134411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency 134511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency 134611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency 134711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency 134811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency 134911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency 135011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency 135111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency 135211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency 135311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency 135411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency 135511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency 135611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency 135711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency 135811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency 135911860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency 136011860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency 136111860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency 136211860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency 136311860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency 136411860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency 136511860Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency 136611860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency 136711860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency 136811860Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency 136911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter. 137011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data. 137111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 137211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter. 137311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 137411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 137511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 137611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution 137711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution 137811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 137911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution 138011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution 138111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution 138211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution 138311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution 138411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution 138511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 138611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution 138711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution 138811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution 138911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution 139011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution 139111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution 139211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution 139311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution 139411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution 139511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution 139611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution 139711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes) 139811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes) 139911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes) 140011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes) 140111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes) 140211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes) 140311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes) 140411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes) 140511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes) 140611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes) 140711860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 6115163 # Total snoops (count) 140811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes) 140911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram 141011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram 141111860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram 141210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 141311860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram 141411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram 141511860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram 141610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 141711138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 141810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 141911860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram 142011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks) 142111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 142211860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks) 142310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 142411860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks) 142510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 142611860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks) 142710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 142811860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks) 142910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 143011860Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks) 143110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 143211860Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 106657949 # Number of BP lookups 143311860Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted 143411860Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect 143511860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups 143611860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits 143710585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 143811860Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage 143911860Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target. 144011860Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions. 144111860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups. 144211860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits. 144311860Sandreas.hansson@arm.comsystem.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses. 144411860Sandreas.hansson@arm.comsystem.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches. 144511860Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 144610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 144710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 144810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 145110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 145210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 145310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 145410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 145510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 145610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 145710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 145810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 145910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 146010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 146110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 146210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 146310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 146410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 146510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 146610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 146710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 146810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 146910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 147010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 147110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 147210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 147310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 147410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 147511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 147611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 277975 # Table walker walks requested 147711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors 147811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate 147911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate 148011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency 148111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency 148211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency 148311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency 148411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency 148511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency 148611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency 148711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency 148811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency 148911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency 149011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency 149111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency 149211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency 149311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 149411860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 149511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency 149611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency 149711860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution 149811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution 149911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution 150011860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated 150111860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated 150211860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated 150311860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst 150410628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 150511860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst 150611860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst 150710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 150811860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst 150911860Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst 151010585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 151110585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 151211860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 85144665 # DTB read hits 151311860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 232605 # DTB read misses 151411860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 73861979 # DTB write hits 151511860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 45370 # DTB write misses 151611441Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 151710585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 151811860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID 151911860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 152011860Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB 152111860Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions 152211860Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch 152310585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 152411860Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions 152511860Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 85377270 # DTB read accesses 152611860Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 73907349 # DTB write accesses 152710585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 152811860Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 159006644 # DTB hits 152911860Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 277975 # DTB misses 153011860Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 159284619 # DTB accesses 153111860Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 153210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 153310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 153410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 153510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 153610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 153710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 153810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 153910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 154010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 154110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 154210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 154310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 154410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 154510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 154610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 154710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 154810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 154910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 155010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 155110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 155210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 155310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 155410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 155610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 155710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 155810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 155910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 156010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 156111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 156211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 63204 # Table walker walks requested 156311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors 156411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate 156511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate 156611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency 156711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency 156811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency 156911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency 157011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency 157111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency 157211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency 157311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency 157411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency 157511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency 157611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency 157711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency 157811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency 157911860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 158011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 158111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 158211860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency 158311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution 158411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution 158511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution 158611860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated 158711860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated 158811860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated 158910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 159011860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst 159111860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst 159210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 159311860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst 159411860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst 159511860Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst 159611860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 184175570 # ITB inst hits 159711860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 63204 # ITB inst misses 159810585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 159910585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 160010585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 160110585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 160211441Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 160310585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 160411860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID 160511860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 160611860Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB 160710585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 160810585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 160910585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 161011860Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions 161110585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 161210585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 161311860Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 184238774 # ITB inst accesses 161411860Sandreas.hansson@arm.comsystem.cpu1.itb.hits 184175570 # DTB hits 161511860Sandreas.hansson@arm.comsystem.cpu1.itb.misses 63204 # DTB misses 161611860Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 184238774 # DTB accesses 161711860Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 10058 # Number of power state transitions 161811860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state 161911860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state 162011860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state 162111860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state 162211860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state 162311860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state 162411860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state 162511860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state 162611860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state 162711860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state 162811860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state 162911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 163011860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state 163111860Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state 163211860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states 163311860Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states 163411860Sandreas.hansson@arm.comsystem.cpu1.numCycles 798693745 # number of cpu cycles simulated 163510585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 163610585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 163711860Sandreas.hansson@arm.comsystem.cpu1.committedInsts 398322797 # Number of instructions committed 163811860Sandreas.hansson@arm.comsystem.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed 163911860Sandreas.hansson@arm.comsystem.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit 164011860Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching 164111860Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 164211860Sandreas.hansson@arm.comsystem.cpu1.cpi 2.005142 # CPI: cycles per instruction 164311860Sandreas.hansson@arm.comsystem.cpu1.ipc 0.498718 # IPC: instructions per cycle 164411860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 164511860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction 164611860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction 164711860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction 164811860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction 164911860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction 165011860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction 165111860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction 165211860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction 165311860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction 165411860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction 165511860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction 165611860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction 165711860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction 165811860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction 165911860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction 166011860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction 166111860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction 166211860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction 166311860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction 166411860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction 166511860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction 166611860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction 166711860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction 166811860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction 166911860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction 167011860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction 167111860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction 167211860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction 167311860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction 167411860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction 167511860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction 167611860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction 167711860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction 167811860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction 167911860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction 168011441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 168111441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 168211860Sandreas.hansson@arm.comsystem.cpu1.op_class_0::total 474376671 # Class of committed instruction 168310585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 168411860Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed 168511860Sandreas.hansson@arm.comsystem.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked 168611860Sandreas.hansson@arm.comsystem.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped 168711860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 168811860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5132038 # number of replacements 168911860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use 169011860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks. 169111860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks. 169211860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks. 169311860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit. 169411860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor 169511860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy 169611860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy 169711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 169811860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 169911860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id 170011860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id 170111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 170211860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses 170311860Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses 170411860Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 170511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 78335043 # number of ReadReq hits 170611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 78335043 # number of ReadReq hits 170711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 68878259 # number of WriteReq hits 170811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 68878259 # number of WriteReq hits 170911860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 235022 # number of SoftPFReq hits 171011860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 235022 # number of SoftPFReq hits 171111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 144067 # number of WriteLineReq hits 171211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 144067 # number of WriteLineReq hits 171311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753147 # number of LoadLockedReq hits 171411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1753147 # number of LoadLockedReq hits 171511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1717747 # number of StoreCondReq hits 171611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1717747 # number of StoreCondReq hits 171711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 147357369 # number of demand (read+write) hits 171811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 147357369 # number of demand (read+write) hits 171911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 147592391 # number of overall hits 172011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 147592391 # number of overall hits 172111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3132424 # number of ReadReq misses 172211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3132424 # number of ReadReq misses 172311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2174513 # number of WriteReq misses 172411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2174513 # number of WriteReq misses 172511860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 607658 # number of SoftPFReq misses 172611860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 607658 # number of SoftPFReq misses 172711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 439275 # number of WriteLineReq misses 172811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 439275 # number of WriteLineReq misses 172911860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165234 # number of LoadLockedReq misses 173011860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 165234 # number of LoadLockedReq misses 173111860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 199402 # number of StoreCondReq misses 173211860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 199402 # number of StoreCondReq misses 173311860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5746212 # number of demand (read+write) misses 173411860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 5746212 # number of demand (read+write) misses 173511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6353870 # number of overall misses 173611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6353870 # number of overall misses 173711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50822417500 # number of ReadReq miss cycles 173811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 50822417500 # number of ReadReq miss cycles 173911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41404734500 # number of WriteReq miss cycles 174011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 41404734500 # number of WriteReq miss cycles 174111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10557419500 # number of WriteLineReq miss cycles 174211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 10557419500 # number of WriteLineReq miss cycles 174311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2612130500 # number of LoadLockedReq miss cycles 174411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2612130500 # number of LoadLockedReq miss cycles 174511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4773809500 # number of StoreCondReq miss cycles 174611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4773809500 # number of StoreCondReq miss cycles 174711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2292000 # number of StoreCondFailReq miss cycles 174811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2292000 # number of StoreCondFailReq miss cycles 174911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 102784571500 # number of demand (read+write) miss cycles 175011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 102784571500 # number of demand (read+write) miss cycles 175111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 102784571500 # number of overall miss cycles 175211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 102784571500 # number of overall miss cycles 175311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 81467467 # number of ReadReq accesses(hits+misses) 175411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 81467467 # number of ReadReq accesses(hits+misses) 175511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 71052772 # number of WriteReq accesses(hits+misses) 175611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 71052772 # number of WriteReq accesses(hits+misses) 175711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842680 # number of SoftPFReq accesses(hits+misses) 175811860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses) 175911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 583342 # number of WriteLineReq accesses(hits+misses) 176011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 583342 # number of WriteLineReq accesses(hits+misses) 176111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1918381 # number of LoadLockedReq accesses(hits+misses) 176211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1918381 # number of LoadLockedReq accesses(hits+misses) 176311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1917149 # number of StoreCondReq accesses(hits+misses) 176411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1917149 # number of StoreCondReq accesses(hits+misses) 176511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 153103581 # number of demand (read+write) accesses 176611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 153103581 # number of demand (read+write) accesses 176711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 153946261 # number of overall (read+write) accesses 176811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 153946261 # number of overall (read+write) accesses 176911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038450 # miss rate for ReadReq accesses 177011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038450 # miss rate for ReadReq accesses 177111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030604 # miss rate for WriteReq accesses 177211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.030604 # miss rate for WriteReq accesses 177311860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.721102 # miss rate for SoftPFReq accesses 177411860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.721102 # miss rate for SoftPFReq accesses 177511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.753032 # miss rate for WriteLineReq accesses 177611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.753032 # miss rate for WriteLineReq accesses 177711860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086132 # miss rate for LoadLockedReq accesses 177811860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086132 # miss rate for LoadLockedReq accesses 177911860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104010 # miss rate for StoreCondReq accesses 178011860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.104010 # miss rate for StoreCondReq accesses 178111860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.037532 # miss rate for demand accesses 178211860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.037532 # miss rate for demand accesses 178311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.041273 # miss rate for overall accesses 178411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.041273 # miss rate for overall accesses 178511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency 178611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency 178711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency 178811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency 178911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency 179011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency 179111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15808.674365 # average LoadLockedReq miss latency 179211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency 179311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23940.629984 # average StoreCondReq miss latency 179411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency 179510636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 179610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 179711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17887.361535 # average overall miss latency 179811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency 179911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency 180011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency 180110585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 180210585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 180310585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 180410585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 180510585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180610585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180711860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks 180811860Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5132050 # number of writebacks 180911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 160382 # number of ReadReq MSHR hits 181011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 160382 # number of ReadReq MSHR hits 181111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 885255 # number of WriteReq MSHR hits 181211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 885255 # number of WriteReq MSHR hits 181311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 52 # number of WriteLineReq MSHR hits 181411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 52 # number of WriteLineReq MSHR hits 181511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41570 # number of LoadLockedReq MSHR hits 181611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 41570 # number of LoadLockedReq MSHR hits 181711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits 181811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits 181911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1045689 # number of demand (read+write) MSHR hits 182011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1045689 # number of demand (read+write) MSHR hits 182111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1045689 # number of overall MSHR hits 182211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1045689 # number of overall MSHR hits 182311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2972042 # number of ReadReq MSHR misses 182411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2972042 # number of ReadReq MSHR misses 182511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1289258 # number of WriteReq MSHR misses 182611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1289258 # number of WriteReq MSHR misses 182711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607473 # number of SoftPFReq MSHR misses 182811860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 607473 # number of SoftPFReq MSHR misses 182911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 439223 # number of WriteLineReq MSHR misses 183011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 439223 # number of WriteLineReq MSHR misses 183111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123664 # number of LoadLockedReq MSHR misses 183211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 123664 # number of LoadLockedReq MSHR misses 183311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199344 # number of StoreCondReq MSHR misses 183411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 199344 # number of StoreCondReq MSHR misses 183511860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4700523 # number of demand (read+write) MSHR misses 183611860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4700523 # number of demand (read+write) MSHR misses 183711860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5307996 # number of overall MSHR misses 183811860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5307996 # number of overall MSHR misses 183911860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable 184011860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 5330 # number of ReadReq MSHR uncacheable 184111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable 184211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable 184311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses 184411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 10596 # number of overall MSHR uncacheable misses 184511860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43920578500 # number of ReadReq MSHR miss cycles 184611860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 43920578500 # number of ReadReq MSHR miss cycles 184711860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24016685500 # number of WriteReq MSHR miss cycles 184811860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 24016685500 # number of WriteReq MSHR miss cycles 184911860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14415408000 # number of SoftPFReq MSHR miss cycles 185011860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14415408000 # number of SoftPFReq MSHR miss cycles 185111860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10114952000 # number of WriteLineReq MSHR miss cycles 185211860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10114952000 # number of WriteLineReq MSHR miss cycles 185311860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1723729000 # number of LoadLockedReq MSHR miss cycles 185411860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1723729000 # number of LoadLockedReq MSHR miss cycles 185511860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4572940000 # number of StoreCondReq MSHR miss cycles 185611860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4572940000 # number of StoreCondReq MSHR miss cycles 185711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2004000 # number of StoreCondFailReq MSHR miss cycles 185811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2004000 # number of StoreCondFailReq MSHR miss cycles 185911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78052216000 # number of demand (read+write) MSHR miss cycles 186011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 78052216000 # number of demand (read+write) MSHR miss cycles 186111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 92467624000 # number of overall MSHR miss cycles 186211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 92467624000 # number of overall MSHR miss cycles 186311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 634565500 # number of ReadReq MSHR uncacheable cycles 186411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 634565500 # number of ReadReq MSHR uncacheable cycles 186511860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 634565500 # number of overall MSHR uncacheable cycles 186611860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 634565500 # number of overall MSHR uncacheable cycles 186711860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036481 # mshr miss rate for ReadReq accesses 186811860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses 186911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018145 # mshr miss rate for WriteReq accesses 187011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018145 # mshr miss rate for WriteReq accesses 187111860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.720882 # mshr miss rate for SoftPFReq accesses 187211860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.720882 # mshr miss rate for SoftPFReq accesses 187311860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.752943 # mshr miss rate for WriteLineReq accesses 187411860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.752943 # mshr miss rate for WriteLineReq accesses 187511860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064463 # mshr miss rate for LoadLockedReq accesses 187611860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064463 # mshr miss rate for LoadLockedReq accesses 187711860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103979 # mshr miss rate for StoreCondReq accesses 187811860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103979 # mshr miss rate for StoreCondReq accesses 187911860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030702 # mshr miss rate for demand accesses 188011860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030702 # mshr miss rate for demand accesses 188111860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034480 # mshr miss rate for overall accesses 188211860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034480 # mshr miss rate for overall accesses 188311860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14777.913132 # average ReadReq mshr miss latency 188411860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14777.913132 # average ReadReq mshr miss latency 188511860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18628.300542 # average WriteReq mshr miss latency 188611860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18628.300542 # average WriteReq mshr miss latency 188711860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23730.121339 # average SoftPFReq mshr miss latency 188811860Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency 188911860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23029.194737 # average WriteLineReq mshr miss latency 189011860Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23029.194737 # average WriteLineReq mshr miss latency 189111860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13938.810001 # average LoadLockedReq mshr miss latency 189211860Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency 189311860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22939.943013 # average StoreCondReq mshr miss latency 189411860Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22939.943013 # average StoreCondReq mshr miss latency 189510636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 189610585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 189711860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16605.006719 # average overall mshr miss latency 189811860Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16605.006719 # average overall mshr miss latency 189911860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17420.439654 # average overall mshr miss latency 190011860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 17420.439654 # average overall mshr miss latency 190111860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119055.440901 # average ReadReq mshr uncacheable latency 190211860Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 119055.440901 # average ReadReq mshr uncacheable latency 190311860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59887.268781 # average overall mshr uncacheable latency 190411860Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59887.268781 # average overall mshr uncacheable latency 190511860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 190611860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 8722673 # number of replacements 190711860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 507.263120 # Cycle average of tags in use 190811860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 175283400 # Total number of references to valid blocks. 190911860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 8723185 # Sample count of references to valid blocks. 191011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 20.093968 # Average number of references to valid blocks. 191111860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8363988306000 # Cycle when the warmup percentage was hit. 191211860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.263120 # Average occupied blocks per requestor 191311860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990748 # Average percentage of cache occupancy 191411860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990748 # Average percentage of cache occupancy 191510585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 191611860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 191711860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id 191811860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 191910585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 192011860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 376736355 # Number of tag accesses 192111860Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses 192211860Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 192311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 175283400 # number of ReadReq hits 192411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 175283400 # number of ReadReq hits 192511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 175283400 # number of demand (read+write) hits 192611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 175283400 # number of demand (read+write) hits 192711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 175283400 # number of overall hits 192811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 175283400 # number of overall hits 192911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 8723185 # number of ReadReq misses 193011860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 8723185 # number of ReadReq misses 193111860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 8723185 # number of demand (read+write) misses 193211860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 8723185 # number of demand (read+write) misses 193311860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 8723185 # number of overall misses 193411860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 8723185 # number of overall misses 193511860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 89772651500 # number of ReadReq miss cycles 193611860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 89772651500 # number of ReadReq miss cycles 193711860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 89772651500 # number of demand (read+write) miss cycles 193811860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 89772651500 # number of demand (read+write) miss cycles 193911860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 89772651500 # number of overall miss cycles 194011860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles 194111860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 184006585 # number of ReadReq accesses(hits+misses) 194211860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 184006585 # number of ReadReq accesses(hits+misses) 194311860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 184006585 # number of demand (read+write) accesses 194411860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 184006585 # number of demand (read+write) accesses 194511860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 184006585 # number of overall (read+write) accesses 194611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 184006585 # number of overall (read+write) accesses 194711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.047407 # miss rate for ReadReq accesses 194811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.047407 # miss rate for ReadReq accesses 194911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.047407 # miss rate for demand accesses 195011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.047407 # miss rate for demand accesses 195111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.047407 # miss rate for overall accesses 195211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.047407 # miss rate for overall accesses 195311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10291.269932 # average ReadReq miss latency 195411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10291.269932 # average ReadReq miss latency 195511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency 195611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10291.269932 # average overall miss latency 195711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency 195811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10291.269932 # average overall miss latency 195910585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 196010585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 196110585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 196210585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 196310585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 196410585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 196511860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 8722673 # number of writebacks 196611860Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 8722673 # number of writebacks 196711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8723185 # number of ReadReq MSHR misses 196811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 8723185 # number of ReadReq MSHR misses 196911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 8723185 # number of demand (read+write) MSHR misses 197011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 8723185 # number of demand (read+write) MSHR misses 197111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 8723185 # number of overall MSHR misses 197211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 8723185 # number of overall MSHR misses 197311570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 197411570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 197511570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 197611570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 197711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85411059000 # number of ReadReq MSHR miss cycles 197811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 85411059000 # number of ReadReq MSHR miss cycles 197911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85411059000 # number of demand (read+write) MSHR miss cycles 198011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 85411059000 # number of demand (read+write) MSHR miss cycles 198111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85411059000 # number of overall MSHR miss cycles 198211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 85411059000 # number of overall MSHR miss cycles 198311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9620500 # number of ReadReq MSHR uncacheable cycles 198411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9620500 # number of ReadReq MSHR uncacheable cycles 198511860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9620500 # number of overall MSHR uncacheable cycles 198611860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 9620500 # number of overall MSHR uncacheable cycles 198711860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for ReadReq accesses 198811860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.047407 # mshr miss rate for ReadReq accesses 198911860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for demand accesses 199011860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.047407 # mshr miss rate for demand accesses 199111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for overall accesses 199211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.047407 # mshr miss rate for overall accesses 199311860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average ReadReq mshr miss latency 199411860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9791.269932 # average ReadReq mshr miss latency 199511860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency 199611860Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency 199711860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency 199811860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency 199911860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average ReadReq mshr uncacheable latency 200011860Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101268.421053 # average ReadReq mshr uncacheable latency 200111860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average overall mshr uncacheable latency 200211860Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101268.421053 # average overall mshr uncacheable latency 200311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 200411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7056390 # number of hwpf issued 200511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7056554 # number of prefetch candidates identified 200611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 145 # number of redundant prefetches already in prefetch queue 200710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 200810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 200911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 902638 # number of prefetches not generated due to page crossing 201011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 201111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2217652 # number of replacements 201211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13067.579403 # Cycle average of tags in use 201311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 12709221 # Total number of references to valid blocks. 201411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2233219 # Sample count of references to valid blocks. 201511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 5.690987 # Average number of references to valid blocks. 201611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 201711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12703.923602 # Average occupied blocks per requestor 201811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.973948 # Average occupied blocks per requestor 201911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.153172 # Average occupied blocks per requestor 202011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 317.528681 # Average occupied blocks per requestor 202111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.775386 # Average percentage of cache occupancy 202211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001890 # Average percentage of cache occupancy 202311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000925 # Average percentage of cache occupancy 202411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019380 # Average percentage of cache occupancy 202511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.797582 # Average percentage of cache occupancy 202611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 287 # Occupied blocks per task id 202711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id 202811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id 202911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 85 # Occupied blocks per task id 203011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 84 # Occupied blocks per task id 203111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id 203211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 203311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 203411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 27 # Occupied blocks per task id 203511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id 203611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id 203711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id 203811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1567 # Occupied blocks per task id 203911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id 204011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5612 # Occupied blocks per task id 204111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2311 # Occupied blocks per task id 204211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017517 # Percentage of cache occupancy per task id 204311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id 204411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id 204511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 477362276 # Number of tag accesses 204611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 477362276 # Number of data accesses 204711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 204811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532002 # number of ReadReq hits 204911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159372 # number of ReadReq hits 205011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 691374 # number of ReadReq hits 205111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3201676 # number of WritebackDirty hits 205211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3201676 # number of WritebackDirty hits 205311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 10651334 # number of WritebackClean hits 205411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 10651334 # number of WritebackClean hits 205511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 860878 # number of ReadExReq hits 205611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 860878 # number of ReadExReq hits 205711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8051210 # number of ReadCleanReq hits 205811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8051210 # number of ReadCleanReq hits 205911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2757056 # number of ReadSharedReq hits 206011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2757056 # number of ReadSharedReq hits 206111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173091 # number of InvalidateReq hits 206211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 173091 # number of InvalidateReq hits 206311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532002 # number of demand (read+write) hits 206411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 159372 # number of demand (read+write) hits 206511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8051210 # number of demand (read+write) hits 206611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3617934 # number of demand (read+write) hits 206711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 12360518 # number of demand (read+write) hits 206811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532002 # number of overall hits 206911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 159372 # number of overall hits 207011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8051210 # number of overall hits 207111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3617934 # number of overall hits 207211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 12360518 # number of overall hits 207311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21589 # number of ReadReq misses 207411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10425 # number of ReadReq misses 207511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 32014 # number of ReadReq misses 207611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206575 # number of UpgradeReq misses 207711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 206575 # number of UpgradeReq misses 207811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 199341 # number of SCUpgradeReq misses 207911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 199341 # number of SCUpgradeReq misses 208011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 208111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 208211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 222346 # number of ReadExReq misses 208311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 222346 # number of ReadExReq misses 208411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 671975 # number of ReadCleanReq misses 208511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 671975 # number of ReadCleanReq misses 208611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 945788 # number of ReadSharedReq misses 208711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 945788 # number of ReadSharedReq misses 208811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266132 # number of InvalidateReq misses 208911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 266132 # number of InvalidateReq misses 209011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21589 # number of demand (read+write) misses 209111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10425 # number of demand (read+write) misses 209211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 671975 # number of demand (read+write) misses 209311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1168134 # number of demand (read+write) misses 209411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1872123 # number of demand (read+write) misses 209511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21589 # number of overall misses 209611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10425 # number of overall misses 209711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 671975 # number of overall misses 209811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1168134 # number of overall misses 209911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1872123 # number of overall misses 210011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 733662000 # number of ReadReq miss cycles 210111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 446226000 # number of ReadReq miss cycles 210211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1179888000 # number of ReadReq miss cycles 210311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 870385500 # number of UpgradeReq miss cycles 210411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 870385500 # number of UpgradeReq miss cycles 210511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 311325000 # number of SCUpgradeReq miss cycles 210611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 311325000 # number of SCUpgradeReq miss cycles 210711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1930000 # number of SCUpgradeFailReq miss cycles 210811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1930000 # number of SCUpgradeFailReq miss cycles 210911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11310487497 # number of ReadExReq miss cycles 211011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 11310487497 # number of ReadExReq miss cycles 211111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 23715219500 # number of ReadCleanReq miss cycles 211211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 23715219500 # number of ReadCleanReq miss cycles 211311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36332241992 # number of ReadSharedReq miss cycles 211411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 36332241992 # number of ReadSharedReq miss cycles 211511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 733662000 # number of demand (read+write) miss cycles 211611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 446226000 # number of demand (read+write) miss cycles 211711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 23715219500 # number of demand (read+write) miss cycles 211811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 47642729489 # number of demand (read+write) miss cycles 211911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 72537836989 # number of demand (read+write) miss cycles 212011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 733662000 # number of overall miss cycles 212111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 446226000 # number of overall miss cycles 212211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 23715219500 # number of overall miss cycles 212311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 47642729489 # number of overall miss cycles 212411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 72537836989 # number of overall miss cycles 212511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 553591 # number of ReadReq accesses(hits+misses) 212611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169797 # number of ReadReq accesses(hits+misses) 212711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 723388 # number of ReadReq accesses(hits+misses) 212811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3201676 # number of WritebackDirty accesses(hits+misses) 212911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3201676 # number of WritebackDirty accesses(hits+misses) 213011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 10651334 # number of WritebackClean accesses(hits+misses) 213111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 10651334 # number of WritebackClean accesses(hits+misses) 213211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206575 # number of UpgradeReq accesses(hits+misses) 213311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 206575 # number of UpgradeReq accesses(hits+misses) 213411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199341 # number of SCUpgradeReq accesses(hits+misses) 213511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 199341 # number of SCUpgradeReq accesses(hits+misses) 213611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 213711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 213811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1083224 # number of ReadExReq accesses(hits+misses) 213911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1083224 # number of ReadExReq accesses(hits+misses) 214011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8723185 # number of ReadCleanReq accesses(hits+misses) 214111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 8723185 # number of ReadCleanReq accesses(hits+misses) 214211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3702844 # number of ReadSharedReq accesses(hits+misses) 214311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3702844 # number of ReadSharedReq accesses(hits+misses) 214411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 439223 # number of InvalidateReq accesses(hits+misses) 214511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 439223 # number of InvalidateReq accesses(hits+misses) 214611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 553591 # number of demand (read+write) accesses 214711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169797 # number of demand (read+write) accesses 214811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 8723185 # number of demand (read+write) accesses 214911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4786068 # number of demand (read+write) accesses 215011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 14232641 # number of demand (read+write) accesses 215111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 553591 # number of overall (read+write) accesses 215211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169797 # number of overall (read+write) accesses 215311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 8723185 # number of overall (read+write) accesses 215411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4786068 # number of overall (read+write) accesses 215511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 14232641 # number of overall (read+write) accesses 215611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for ReadReq accesses 215711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061397 # miss rate for ReadReq accesses 215811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.044256 # miss rate for ReadReq accesses 215911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 216011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 216111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 216211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 216310636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 216410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 216511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.205263 # miss rate for ReadExReq accesses 216611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.205263 # miss rate for ReadExReq accesses 216711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077033 # miss rate for ReadCleanReq accesses 216811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077033 # miss rate for ReadCleanReq accesses 216911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255422 # miss rate for ReadSharedReq accesses 217011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255422 # miss rate for ReadSharedReq accesses 217111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.605915 # miss rate for InvalidateReq accesses 217211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.605915 # miss rate for InvalidateReq accesses 217311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for demand accesses 217411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061397 # miss rate for demand accesses 217511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077033 # miss rate for demand accesses 217611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244070 # miss rate for demand accesses 217711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.131537 # miss rate for demand accesses 217811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for overall accesses 217911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061397 # miss rate for overall accesses 218011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077033 # miss rate for overall accesses 218111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244070 # miss rate for overall accesses 218211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.131537 # miss rate for overall accesses 218311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average ReadReq miss latency 218411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42803.453237 # average ReadReq miss latency 218511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 36855.375773 # average ReadReq miss latency 218611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4213.411594 # average UpgradeReq miss latency 218711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4213.411594 # average UpgradeReq miss latency 218811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1561.771036 # average SCUpgradeReq miss latency 218911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1561.771036 # average SCUpgradeReq miss latency 219011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 643333.333333 # average SCUpgradeFailReq miss latency 219111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 643333.333333 # average SCUpgradeFailReq miss latency 219211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50868.859782 # average ReadExReq miss latency 219311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50868.859782 # average ReadExReq miss latency 219411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35291.818148 # average ReadCleanReq miss latency 219511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35291.818148 # average ReadCleanReq miss latency 219611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38414.784277 # average ReadSharedReq miss latency 219711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38414.784277 # average ReadSharedReq miss latency 219811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency 219911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency 220011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency 220111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency 220211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 38746.298715 # average overall miss latency 220311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency 220411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency 220511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency 220611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency 220711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 38746.298715 # average overall miss latency 220811441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 220910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 221011441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 221110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 221211441Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 221411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.unused_prefetches 44670 # number of HardPF blocks evicted w/o reference 221511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1164875 # number of writebacks 221611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1164875 # number of writebacks 221711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 19 # number of ReadReq MSHR hits 221811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 106 # number of ReadReq MSHR hits 221911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits 222011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8703 # number of ReadExReq MSHR hits 222111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 8703 # number of ReadExReq MSHR hits 222211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits 222311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 222411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 710 # number of ReadSharedReq MSHR hits 222511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 710 # number of ReadSharedReq MSHR hits 222611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 19 # number of demand (read+write) MSHR hits 222711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 106 # number of demand (read+write) MSHR hits 222811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 222911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 9413 # number of demand (read+write) MSHR hits 223011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 9539 # number of demand (read+write) MSHR hits 223111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 19 # number of overall MSHR hits 223211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 106 # number of overall MSHR hits 223311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 223411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 9413 # number of overall MSHR hits 223511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 9539 # number of overall MSHR hits 223611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21570 # number of ReadReq MSHR misses 223711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10319 # number of ReadReq MSHR misses 223811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 31889 # number of ReadReq MSHR misses 223911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of HardPFReq MSHR misses 224011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 740053 # number of HardPFReq MSHR misses 224111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206575 # number of UpgradeReq MSHR misses 224211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 206575 # number of UpgradeReq MSHR misses 224311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199341 # number of SCUpgradeReq MSHR misses 224411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199341 # number of SCUpgradeReq MSHR misses 224511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 224611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 224711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 213643 # number of ReadExReq MSHR misses 224811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 213643 # number of ReadExReq MSHR misses 224911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 671974 # number of ReadCleanReq MSHR misses 225011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 671974 # number of ReadCleanReq MSHR misses 225111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 945078 # number of ReadSharedReq MSHR misses 225211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 945078 # number of ReadSharedReq MSHR misses 225311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266132 # number of InvalidateReq MSHR misses 225411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 266132 # number of InvalidateReq MSHR misses 225511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21570 # number of demand (read+write) MSHR misses 225611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10319 # number of demand (read+write) MSHR misses 225711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 671974 # number of demand (read+write) MSHR misses 225811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1158721 # number of demand (read+write) MSHR misses 225911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1862584 # number of demand (read+write) MSHR misses 226011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21570 # number of overall MSHR misses 226111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10319 # number of overall MSHR misses 226211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 671974 # number of overall MSHR misses 226311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1158721 # number of overall MSHR misses 226411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of overall MSHR misses 226511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2602637 # number of overall MSHR misses 226611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 226711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable 226811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5425 # number of ReadReq MSHR uncacheable 226911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable 227011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable 227111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 227211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses 227311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10691 # number of overall MSHR uncacheable misses 227411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of ReadReq MSHR miss cycles 227511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 382493500 # number of ReadReq MSHR miss cycles 227611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 986284000 # number of ReadReq MSHR miss cycles 227711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of HardPFReq MSHR miss cycles 227811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 37370954173 # number of HardPFReq MSHR miss cycles 227911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3898631994 # number of UpgradeReq MSHR miss cycles 228011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3898631994 # number of UpgradeReq MSHR miss cycles 228111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3073389997 # number of SCUpgradeReq MSHR miss cycles 228211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3073389997 # number of SCUpgradeReq MSHR miss cycles 228311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1642000 # number of SCUpgradeFailReq MSHR miss cycles 228411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1642000 # number of SCUpgradeFailReq MSHR miss cycles 228511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8857402997 # number of ReadExReq MSHR miss cycles 228611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8857402997 # number of ReadExReq MSHR miss cycles 228711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 19683346000 # number of ReadCleanReq MSHR miss cycles 228811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19683346000 # number of ReadCleanReq MSHR miss cycles 228911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30564768492 # number of ReadSharedReq MSHR miss cycles 229011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30564768492 # number of ReadSharedReq MSHR miss cycles 229111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6658115000 # number of InvalidateReq MSHR miss cycles 229211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6658115000 # number of InvalidateReq MSHR miss cycles 229311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of demand (read+write) MSHR miss cycles 229411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 382493500 # number of demand (read+write) MSHR miss cycles 229511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19683346000 # number of demand (read+write) MSHR miss cycles 229611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39422171489 # number of demand (read+write) MSHR miss cycles 229711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 60091801489 # number of demand (read+write) MSHR miss cycles 229811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of overall MSHR miss cycles 229911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 382493500 # number of overall MSHR miss cycles 230011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19683346000 # number of overall MSHR miss cycles 230111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39422171489 # number of overall MSHR miss cycles 230211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of overall MSHR miss cycles 230311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 97462755662 # number of overall MSHR miss cycles 230411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8860500 # number of ReadReq MSHR uncacheable cycles 230511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 591855500 # number of ReadReq MSHR uncacheable cycles 230611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 600716000 # number of ReadReq MSHR uncacheable cycles 230711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8860500 # number of overall MSHR uncacheable cycles 230811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 591855500 # number of overall MSHR uncacheable cycles 230911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 600716000 # number of overall MSHR uncacheable cycles 231011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for ReadReq accesses 231111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for ReadReq accesses 231211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044083 # mshr miss rate for ReadReq accesses 231310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 231410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 231511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 231611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 231711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 231811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 231910636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 232010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 232111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses 232211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses 232311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses 232411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses 232511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses 232611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses 232711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses 232811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses 232911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses 233011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses 233111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses 233211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses 233311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses 233411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses 233511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses 233611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses 233711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses 233810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 233911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses 234011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency 234111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency 234211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency 234311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency 234411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency 234511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency 234611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency 234711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency 234811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency 234911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency 235011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency 235111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency 235211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency 235311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency 235411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency 235511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency 235611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency 235711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency 235811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency 235911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency 236011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency 236111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency 236211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency 236311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency 236411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency 236511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency 236611860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency 236711860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency 236811860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency 236911860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency 237011860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency 237111860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency 237211860Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency 237311860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency 237411860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency 237511860Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency 237611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter. 237711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data. 237811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 237911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter. 238011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 238111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 238211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 238311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution 238411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution 238511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution 238611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution 238711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution 238811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution 238911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution 239011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution 239111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 239211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution 239311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution 239411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution 239511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 239611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution 239711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution 239811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution 239911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution 240011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution 240111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution 240211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution 240311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes) 240411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes) 240511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes) 240611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes) 240711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes) 240811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes) 240911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes) 241011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes) 241111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes) 241211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes) 241311860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5350505 # Total snoops (count) 241411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes) 241511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram 241611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram 241711860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram 241810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 241911860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram 242011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram 242111860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram 242210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 242311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 242410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 242511860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram 242611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks) 242711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 242811860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks) 242910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 243011860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks) 243110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 243211860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks) 243310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 243411860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks) 243510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 243611860Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks) 243710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 243811860Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 243911860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40225 # Transaction distribution 244011860Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40225 # Transaction distribution 244111860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136513 # Transaction distribution 244211860Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136513 # Transaction distribution 244311860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes) 244410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 244511245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 244610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 244710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 244810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 244910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 245010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 245110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 245210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 245310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 245411860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 245510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 245611860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes) 245711860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) 245811860Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) 245910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 246010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 246111860Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes) 246211860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47248 # Cumulative packet size per connected master and slave (bytes) 246310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 246411245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 246510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 246610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 246710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 246810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 246910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 247010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 247110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 247210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 247311860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 247410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 247511860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes) 247611860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) 247711860Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) 247810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 247910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 248011860Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes) 248111860Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 42338500 # Layer occupancy (ticks) 248210585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 248311860Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 248410585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 248511860Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) 248610585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 248711860Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 248810585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 248911860Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) 249011245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 249111860Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 249210585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 249311860Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 249410585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 249511754Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 249610585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 249711754Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 249810585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 249911860Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) 250010585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 250111860Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 250210585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 250311860Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks) 250410585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 250511860Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks) 250610585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 250711860Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks) 250810585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 250911860Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks) 251010585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 251111860Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks) 251210585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 251310892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 251410585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 251511860Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 251611860Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115597 # number of replacements 251711860Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use 251811336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 251911860Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. 252011336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 252111860Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit. 252211860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor 252311860Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor 252411860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy 252511860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy 252611860Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy 252710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 252810827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 252910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 253011860Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040910 # Number of tag accesses 253111860Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040910 # Number of data accesses 253211860Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 253310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 253411860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses 253511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8926 # number of ReadReq misses 253610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 253710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 253811606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 253911606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 254010585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 254111860Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115617 # number of demand (read+write) misses 254211860Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115657 # number of demand (read+write) misses 254310585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 254411860Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115617 # number of overall misses 254511860Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115657 # number of overall misses 254611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles 254711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles 254811860Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles 254910726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 255010726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 255111860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles 255211860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles 255311860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles 255411860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles 255511860Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles 255611860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles 255711860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles 255811860Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles 255910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 256011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) 256111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) 256210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 256310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 256411606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 256511606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 256610585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 256711860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115617 # number of demand (read+write) accesses 256811860Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses 256910585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 257011860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses 257111860Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses 257210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 257310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 257410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 257510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 257610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 257711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 257811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 257910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 258010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 258110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 258210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 258310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 258410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 258511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency 258611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency 258711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency 258810726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 258910726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 259011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 123589.242467 # average WriteLineReq miss latency 259111860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 123589.242467 # average WriteLineReq miss latency 259211860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency 259311860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency 259411860Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 131217.346127 # average overall miss latency 259511860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency 259611860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency 259711860Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 131217.346127 # average overall miss latency 259811860Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 49271 # number of cycles access was blocked 259910585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 260011860Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3583 # number of cycles access was blocked 260110585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 260211860Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 13.751326 # average number of cycles each access was blocked 260310585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 260411680SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106693 # number of writebacks 260511680SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106693 # number of writebacks 260610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 260711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses 260811860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses 260910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 261010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 261111606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 261211606Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 261310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 261411860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115617 # number of demand (read+write) MSHR misses 261511860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 115657 # number of demand (read+write) MSHR misses 261610585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 261711860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115617 # number of overall MSHR misses 261811860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 115657 # number of overall MSHR misses 261911860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles 262011860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1535756431 # number of ReadReq MSHR miss cycles 262111860Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1539102931 # number of ReadReq MSHR miss cycles 262210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 262310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 262411860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7847855187 # number of WriteLineReq MSHR miss cycles 262511860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7847855187 # number of WriteLineReq MSHR miss cycles 262611860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles 262711860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9383611618 # number of demand (read+write) MSHR miss cycles 262811860Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 9387177118 # number of demand (read+write) MSHR miss cycles 262911860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles 263011860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9383611618 # number of overall MSHR miss cycles 263111860Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles 263210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 263310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 263410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 263510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 263610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 263711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 263811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 263910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 264010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 264110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 264210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 264310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 264410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 264511860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency 264611860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172770.438857 # average ReadReq mshr miss latency 264711860Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 172429.187878 # average ReadReq mshr miss latency 264810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 264910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 265011860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73531.361845 # average WriteLineReq mshr miss latency 265111860Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 73531.361845 # average WriteLineReq mshr miss latency 265211860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency 265311860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency 265411860Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency 265511860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency 265611860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency 265711860Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency 265811860Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 265911860Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1609900 # number of replacements 266011860Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65157.020292 # Cycle average of tags in use 266111860Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 7484861 # Total number of references to valid blocks. 266211860Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1671770 # Sample count of references to valid blocks. 266311860Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.477207 # Average number of references to valid blocks. 266411860Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 3329231500 # Cycle when the warmup percentage was hit. 266511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 10396.250510 # Average occupied blocks per requestor 266611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 173.300313 # Average occupied blocks per requestor 266711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 163.171529 # Average occupied blocks per requestor 266811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4900.186700 # Average occupied blocks per requestor 266911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 12808.046984 # Average occupied blocks per requestor 267011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9631.875704 # Average occupied blocks per requestor 267111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 290.820455 # Average occupied blocks per requestor 267211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 308.484030 # Average occupied blocks per requestor 267311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3535.017429 # Average occupied blocks per requestor 267411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 11523.081214 # Average occupied blocks per requestor 267511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11426.785423 # Average occupied blocks per requestor 267611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.158634 # Average percentage of cache occupancy 267711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002644 # Average percentage of cache occupancy 267811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.002490 # Average percentage of cache occupancy 267911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.074771 # Average percentage of cache occupancy 268011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.195435 # Average percentage of cache occupancy 268111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146971 # Average percentage of cache occupancy 268211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004438 # Average percentage of cache occupancy 268311860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.004707 # Average percentage of cache occupancy 268411860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.053940 # Average percentage of cache occupancy 268511860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.175828 # Average percentage of cache occupancy 268611860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.174359 # Average percentage of cache occupancy 268711860Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.994217 # Average percentage of cache occupancy 268811860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10593 # Occupied blocks per task id 268911860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id 269011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 51026 # Occupied blocks per task id 269111860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id 269211860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 461 # Occupied blocks per task id 269311860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 10006 # Occupied blocks per task id 269411860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 251 # Occupied blocks per task id 269511860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 269611860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id 269711860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id 269811860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4614 # Occupied blocks per task id 269911860Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 44401 # Occupied blocks per task id 270011860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.161636 # Percentage of cache occupancy per task id 270111860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id 270211860Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.778595 # Percentage of cache occupancy per task id 270311860Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 82772579 # Number of tag accesses 270411860Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 82772579 # Number of data accesses 270511860Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 270611860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2960473 # number of WritebackDirty hits 270711860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2960473 # number of WritebackDirty hits 270811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 214775 # number of UpgradeReq hits 270911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 151269 # number of UpgradeReq hits 271011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 366044 # number of UpgradeReq hits 271111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 56896 # number of SCUpgradeReq hits 271211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 55474 # number of SCUpgradeReq hits 271311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 112370 # number of SCUpgradeReq hits 271411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 67148 # number of ReadExReq hits 271511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 51632 # number of ReadExReq hits 271611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 118780 # number of ReadExReq hits 271711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 14203 # number of ReadSharedReq hits 271811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 6226 # number of ReadSharedReq hits 271911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 695308 # number of ReadSharedReq hits 272011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 685955 # number of ReadSharedReq hits 272111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 328258 # number of ReadSharedReq hits 272211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12341 # number of ReadSharedReq hits 272311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4684 # number of ReadSharedReq hits 272411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 616265 # number of ReadSharedReq hits 272511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 560248 # number of ReadSharedReq hits 272611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 290505 # number of ReadSharedReq hits 272711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 3213993 # number of ReadSharedReq hits 272811860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 136732 # number of InvalidateReq hits 272911860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 122714 # number of InvalidateReq hits 273011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 259446 # number of InvalidateReq hits 273111860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 14203 # number of demand (read+write) hits 273211860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 6226 # number of demand (read+write) hits 273311860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 695308 # number of demand (read+write) hits 273411860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 753103 # number of demand (read+write) hits 273511860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 328258 # number of demand (read+write) hits 273611860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 12341 # number of demand (read+write) hits 273711860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4684 # number of demand (read+write) hits 273811860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 616265 # number of demand (read+write) hits 273911860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 611880 # number of demand (read+write) hits 274011860Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 290505 # number of demand (read+write) hits 274111860Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3332773 # number of demand (read+write) hits 274211860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 14203 # number of overall hits 274311860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 6226 # number of overall hits 274411860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 695308 # number of overall hits 274511860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 753103 # number of overall hits 274611860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 328258 # number of overall hits 274711860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 12341 # number of overall hits 274811860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4684 # number of overall hits 274911860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 616265 # number of overall hits 275011860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 611880 # number of overall hits 275111860Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 290505 # number of overall hits 275211860Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3332773 # number of overall hits 275311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 20148 # number of UpgradeReq misses 275411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 22532 # number of UpgradeReq misses 275511860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 42680 # number of UpgradeReq misses 275611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 632 # number of SCUpgradeReq misses 275711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses 275811860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1574 # number of SCUpgradeReq misses 275911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 82382 # number of ReadExReq misses 276011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 53449 # number of ReadExReq misses 276111860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 135831 # number of ReadExReq misses 276211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq misses 276311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1618 # number of ReadSharedReq misses 276411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 79514 # number of ReadSharedReq misses 276511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 147489 # number of ReadSharedReq misses 276611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq misses 276711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq misses 276811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2403 # number of ReadSharedReq misses 276911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 55709 # number of ReadSharedReq misses 277011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 138924 # number of ReadSharedReq misses 277111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq misses 277211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 938667 # number of ReadSharedReq misses 277311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 422083 # number of InvalidateReq misses 277411860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 110180 # number of InvalidateReq misses 277511860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 532263 # number of InvalidateReq misses 277611860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2080 # number of demand (read+write) misses 277711860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1618 # number of demand (read+write) misses 277811860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 79514 # number of demand (read+write) misses 277911860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 229871 # number of demand (read+write) misses 278011860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) misses 278111860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2595 # number of demand (read+write) misses 278211860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2403 # number of demand (read+write) misses 278311860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 55709 # number of demand (read+write) misses 278411860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 192373 # number of demand (read+write) misses 278511860Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) misses 278611860Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1074498 # number of demand (read+write) misses 278711860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2080 # number of overall misses 278811860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1618 # number of overall misses 278911860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 79514 # number of overall misses 279011860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 229871 # number of overall misses 279111860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 271925 # number of overall misses 279211860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2595 # number of overall misses 279311860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2403 # number of overall misses 279411860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 55709 # number of overall misses 279511860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 192373 # number of overall misses 279611860Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 236410 # number of overall misses 279711860Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1074498 # number of overall misses 279811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 146038500 # number of UpgradeReq miss cycles 279911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 131790500 # number of UpgradeReq miss cycles 280011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 277829000 # number of UpgradeReq miss cycles 280111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 10352000 # number of SCUpgradeReq miss cycles 280211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 8549500 # number of SCUpgradeReq miss cycles 280311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 18901500 # number of SCUpgradeReq miss cycles 280411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 8710976500 # number of ReadExReq miss cycles 280511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 5673543000 # number of ReadExReq miss cycles 280611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 14384519500 # number of ReadExReq miss cycles 280711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 219387000 # number of ReadSharedReq miss cycles 280811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 170599500 # number of ReadSharedReq miss cycles 280911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 8581562500 # number of ReadSharedReq miss cycles 281011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 16399499000 # number of ReadSharedReq miss cycles 281111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of ReadSharedReq miss cycles 281211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257094000 # number of ReadSharedReq miss cycles 281311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 237286000 # number of ReadSharedReq miss cycles 281411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6184697999 # number of ReadSharedReq miss cycles 281511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 15199077000 # number of ReadSharedReq miss cycles 281611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of ReadSharedReq miss cycles 281711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 118434367320 # number of ReadSharedReq miss cycles 281811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 219387000 # number of demand (read+write) miss cycles 281911860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 170599500 # number of demand (read+write) miss cycles 282011860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 8581562500 # number of demand (read+write) miss cycles 282111860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 25110475500 # number of demand (read+write) miss cycles 282211860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of demand (read+write) miss cycles 282311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 257094000 # number of demand (read+write) miss cycles 282411860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 237286000 # number of demand (read+write) miss cycles 282511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6184697999 # number of demand (read+write) miss cycles 282611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 20872620000 # number of demand (read+write) miss cycles 282711860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of demand (read+write) miss cycles 282811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 132818886820 # number of demand (read+write) miss cycles 282911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 219387000 # number of overall miss cycles 283011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 170599500 # number of overall miss cycles 283111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 8581562500 # number of overall miss cycles 283211860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 25110475500 # number of overall miss cycles 283311860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of overall miss cycles 283411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 257094000 # number of overall miss cycles 283511860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 237286000 # number of overall miss cycles 283611860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6184697999 # number of overall miss cycles 283711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 20872620000 # number of overall miss cycles 283811860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of overall miss cycles 283911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 132818886820 # number of overall miss cycles 284011860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2960473 # number of WritebackDirty accesses(hits+misses) 284111860Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2960473 # number of WritebackDirty accesses(hits+misses) 284211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 234923 # number of UpgradeReq accesses(hits+misses) 284311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 173801 # number of UpgradeReq accesses(hits+misses) 284411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 408724 # number of UpgradeReq accesses(hits+misses) 284511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 57528 # number of SCUpgradeReq accesses(hits+misses) 284611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 56416 # number of SCUpgradeReq accesses(hits+misses) 284711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 113944 # number of SCUpgradeReq accesses(hits+misses) 284811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 149530 # number of ReadExReq accesses(hits+misses) 284911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 105081 # number of ReadExReq accesses(hits+misses) 285011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 254611 # number of ReadExReq accesses(hits+misses) 285111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16283 # number of ReadSharedReq accesses(hits+misses) 285211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7844 # number of ReadSharedReq accesses(hits+misses) 285311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 774822 # number of ReadSharedReq accesses(hits+misses) 285411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 833444 # number of ReadSharedReq accesses(hits+misses) 285511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 600183 # number of ReadSharedReq accesses(hits+misses) 285611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14936 # number of ReadSharedReq accesses(hits+misses) 285711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7087 # number of ReadSharedReq accesses(hits+misses) 285811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 671974 # number of ReadSharedReq accesses(hits+misses) 285911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 699172 # number of ReadSharedReq accesses(hits+misses) 286011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 526915 # number of ReadSharedReq accesses(hits+misses) 286111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 4152660 # number of ReadSharedReq accesses(hits+misses) 286211860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 558815 # number of InvalidateReq accesses(hits+misses) 286311860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 232894 # number of InvalidateReq accesses(hits+misses) 286411860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 791709 # number of InvalidateReq accesses(hits+misses) 286511860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 16283 # number of demand (read+write) accesses 286611860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 7844 # number of demand (read+write) accesses 286711860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 774822 # number of demand (read+write) accesses 286811860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 982974 # number of demand (read+write) accesses 286911860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 600183 # number of demand (read+write) accesses 287011860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 14936 # number of demand (read+write) accesses 287111860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7087 # number of demand (read+write) accesses 287211860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 671974 # number of demand (read+write) accesses 287311860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 804253 # number of demand (read+write) accesses 287411860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 526915 # number of demand (read+write) accesses 287511860Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4407271 # number of demand (read+write) accesses 287611860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 16283 # number of overall (read+write) accesses 287711860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 7844 # number of overall (read+write) accesses 287811860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 774822 # number of overall (read+write) accesses 287911860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 982974 # number of overall (read+write) accesses 288011860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 600183 # number of overall (read+write) accesses 288111860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 14936 # number of overall (read+write) accesses 288211860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7087 # number of overall (read+write) accesses 288311860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 671974 # number of overall (read+write) accesses 288411860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 804253 # number of overall (read+write) accesses 288511860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 526915 # number of overall (read+write) accesses 288611860Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4407271 # number of overall (read+write) accesses 288711860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.085764 # miss rate for UpgradeReq accesses 288811860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.129643 # miss rate for UpgradeReq accesses 288911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.104423 # miss rate for UpgradeReq accesses 289011860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010986 # miss rate for SCUpgradeReq accesses 289111860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016697 # miss rate for SCUpgradeReq accesses 289211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.013814 # miss rate for SCUpgradeReq accesses 289311860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.550940 # miss rate for ReadExReq accesses 289411860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.508646 # miss rate for ReadExReq accesses 289511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.533484 # miss rate for ReadExReq accesses 289611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for ReadSharedReq accesses 289711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.206272 # miss rate for ReadSharedReq accesses 289811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102622 # miss rate for ReadSharedReq accesses 289911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.176963 # miss rate for ReadSharedReq accesses 290011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for ReadSharedReq accesses 290111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for ReadSharedReq accesses 290211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.339072 # miss rate for ReadSharedReq accesses 290311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.082904 # miss rate for ReadSharedReq accesses 290411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.198698 # miss rate for ReadSharedReq accesses 290511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for ReadSharedReq accesses 290611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.226040 # miss rate for ReadSharedReq accesses 290711860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.755318 # miss rate for InvalidateReq accesses 290811860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.473091 # miss rate for InvalidateReq accesses 290911860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.672296 # miss rate for InvalidateReq accesses 291011860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for demand accesses 291111860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.206272 # miss rate for demand accesses 291211860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.102622 # miss rate for demand accesses 291311860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.233853 # miss rate for demand accesses 291411860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for demand accesses 291511860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for demand accesses 291611860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.339072 # miss rate for demand accesses 291711860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.082904 # miss rate for demand accesses 291811860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.239195 # miss rate for demand accesses 291911860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for demand accesses 292011860Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.243801 # miss rate for demand accesses 292111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for overall accesses 292211860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.206272 # miss rate for overall accesses 292311860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.102622 # miss rate for overall accesses 292411860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.233853 # miss rate for overall accesses 292511860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for overall accesses 292611860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for overall accesses 292711860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.339072 # miss rate for overall accesses 292811860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.082904 # miss rate for overall accesses 292911860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.239195 # miss rate for overall accesses 293011860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for overall accesses 293111860Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.243801 # miss rate for overall accesses 293211860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7248.287671 # average UpgradeReq miss latency 293311860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5849.036925 # average UpgradeReq miss latency 293411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6509.582943 # average UpgradeReq miss latency 293511860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16379.746835 # average SCUpgradeReq miss latency 293611860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9075.902335 # average SCUpgradeReq miss latency 293711860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 12008.576874 # average SCUpgradeReq miss latency 293811860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 105738.832512 # average ReadExReq miss latency 293911860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 106148.721211 # average ReadExReq miss latency 294011860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 105900.122211 # average ReadExReq miss latency 294111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average ReadSharedReq miss latency 294211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105438.504326 # average ReadSharedReq miss latency 294311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107925.176698 # average ReadSharedReq miss latency 294411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111191.336303 # average ReadSharedReq miss latency 294511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average ReadSharedReq miss latency 294611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average ReadSharedReq miss latency 294711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 98745.734499 # average ReadSharedReq miss latency 294811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111017.932453 # average ReadSharedReq miss latency 294911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 109405.696640 # average ReadSharedReq miss latency 295011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average ReadSharedReq miss latency 295111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 126172.931743 # average ReadSharedReq miss latency 295211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency 295311860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency 295411860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency 295511860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency 295611860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency 295711860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency 295811860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency 295911860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency 296011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency 296111860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency 296211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 123610.175933 # average overall miss latency 296311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency 296411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency 296511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency 296611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency 296711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency 296811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency 296911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency 297011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency 297111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency 297211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency 297311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 123610.175933 # average overall miss latency 297411860Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 1362 # number of cycles access was blocked 297510515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 297611860Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 13 # number of cycles access was blocked 297710515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 297811860Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 104.769231 # average number of cycles each access was blocked 297910515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298011860Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1205906 # number of writebacks 298111860Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1205906 # number of writebacks 298211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 171 # number of ReadSharedReq MSHR hits 298311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 38 # number of ReadSharedReq MSHR hits 298411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 160 # number of ReadSharedReq MSHR hits 298511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits 298611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 380 # number of ReadSharedReq MSHR hits 298711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 171 # number of demand (read+write) MSHR hits 298811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits 298911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 160 # number of demand (read+write) MSHR hits 299011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits 299111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits 299211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 171 # number of overall MSHR hits 299311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits 299411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 160 # number of overall MSHR hits 299511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits 299611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 380 # number of overall MSHR hits 299711860Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 74973 # number of CleanEvict MSHR misses 299811860Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 74973 # number of CleanEvict MSHR misses 299911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 20148 # number of UpgradeReq MSHR misses 300011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 22532 # number of UpgradeReq MSHR misses 300111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 42680 # number of UpgradeReq MSHR misses 300211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 632 # number of SCUpgradeReq MSHR misses 300311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 942 # number of SCUpgradeReq MSHR misses 300411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1574 # number of SCUpgradeReq MSHR misses 300511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 82382 # number of ReadExReq MSHR misses 300611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 53449 # number of ReadExReq MSHR misses 300711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 135831 # number of ReadExReq MSHR misses 300811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq MSHR misses 300911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1618 # number of ReadSharedReq MSHR misses 301011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 79343 # 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number of ReadReq MSHR uncacheable cycles 310711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 303607000 # number of overall MSHR uncacheable cycles 310811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 5434541500 # number of overall MSHR uncacheable cycles 310911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6865000 # number of overall MSHR uncacheable cycles 311011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 495854501 # number of overall MSHR uncacheable cycles 311111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 6240868001 # number of overall MSHR uncacheable cycles 311210892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 311310892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 311411860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.085764 # 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mshr miss rate for ReadSharedReq accesses 313111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.198682 # mshr miss rate for ReadSharedReq accesses 313211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for ReadSharedReq accesses 313311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.225948 # mshr miss rate for ReadSharedReq accesses 313411860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.755318 # mshr miss rate for InvalidateReq accesses 313511860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.473091 # mshr miss rate for InvalidateReq accesses 313611860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.672296 # mshr miss rate for InvalidateReq accesses 313711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for demand accesses 313811860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for demand accesses 313911860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for demand accesses 314011860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for demand accesses 314111860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for demand accesses 314211860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for demand accesses 314311860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for demand accesses 314411860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for demand accesses 314511860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for demand accesses 314611860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for demand accesses 314711860Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.243715 # mshr miss rate for demand accesses 314811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses 314911860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for overall accesses 315011860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses 315111860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses 315211860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses 315311860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses 315411860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses 315511860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses 315611860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses 315711860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses 315811860Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses 315911860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency 316011860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency 316111860Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency 316211860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency 316311860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency 316411860Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency 316511860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency 316611860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency 316711860Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency 316811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency 316911860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency 317011860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency 317111860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency 317211860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency 317311860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency 317411860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency 317511860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency 317611860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency 317711860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency 317811860Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency 317911860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency 318011860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency 318111860Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency 318211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency 318311860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency 318411860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency 318511860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency 318611860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency 318711860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency 318811860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency 318911860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency 319011860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency 319111860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency 319211860Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency 319311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency 319411860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency 319511860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency 319611860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency 319711860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency 319811860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency 319911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency 320011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency 320111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency 320211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency 320311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency 320411860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency 320511860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency 320611860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency 320711860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency 320811860Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency 320911860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency 321011860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency 321111860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency 321211860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency 321311860Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency 321411860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter. 321511860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data. 321611860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 321711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 321811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 321911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 322011860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 322111860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 42476 # Transaction distribution 322211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 989688 # Transaction distribution 322311860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 37999 # Transaction distribution 322411860Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 37999 # Transaction distribution 322511860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution 322611860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 291937 # Transaction distribution 322711860Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 286456 # Transaction distribution 322811860Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution 322911680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 24 # Transaction distribution 323011860Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 323111860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 150791 # Transaction distribution 323211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 135122 # Transaction distribution 323311860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution 323411860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 648655 # Transaction distribution 323511860Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 27962 # Transaction distribution 323611860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes) 323711570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 323811860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes) 323911860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes) 324011860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes) 324111860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes) 324211860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes) 324311860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes) 324411860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes) 324511570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 324611860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes) 324711860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes) 324811860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes) 324911860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes) 325011860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes) 325111860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes) 325211860Sandreas.hansson@arm.comsystem.membus.snoops 586564 # Total snoops (count) 325311860Sandreas.hansson@arm.comsystem.membus.snoopTraffic 164864 # Total snoop traffic (bytes) 325411860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2402773 # Request fanout histogram 325511860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.012913 # Request fanout histogram 325611860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram 325710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 325811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram 325911860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram 326010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 326110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 326211502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 326310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 326411860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2402773 # Request fanout histogram 326511860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks) 326610585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 326711570SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 326810585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 326911860Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks) 327010585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 327111860Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks) 327210585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 327311860Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks) 327410585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 327511860Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks) 327610585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 327711860Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 327811860Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 327911860Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 328011860Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 328111860Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 328211860Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 328311860Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 328411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 328511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 328611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 328711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 328811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 328911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 329011860Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 329111860Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 329210515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 329310515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 329410515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 329510515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 329610515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 329710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 329810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 329910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 330010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 330111201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 330210515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 330310515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 330410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 330511201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 330610515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 330710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 330810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 330910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 331010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 331110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 331210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 331310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 331410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 331510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 331610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 331710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 331810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 331910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 332010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 332110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 332210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 332310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 332410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 332510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 332610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 332710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 332810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 332910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 333010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 333110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 333210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 333310515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 333411860Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 333511860Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 333611860Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 333711860Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 333811860Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 333911860Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 334011860Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 334111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 334211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 334311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 334411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 334511860Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 334611860Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 334711860Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 334811860Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 334911860Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335011860Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335111860Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335211860Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335311860Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335411860Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335511860Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335611860Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 335711860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter. 335811860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data. 335911860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 336011860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter. 336111860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 336211860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 336311860Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states 336411860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution 336511860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution 336611860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution 336711860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution 336811860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution 336911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 337011860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution 337111860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution 337211860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution 337311860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution 337411860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution 337511860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution 337611860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution 337711860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution 337811860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution 337911860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution 338011860Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution 338111860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes) 338211860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes) 338311860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes) 338411860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes) 338511860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes) 338611860Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes) 338711860Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3035429 # Total snoops (count) 338811860Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes) 338911860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram 339011860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram 339111860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram 339210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 339311860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram 339411860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram 339511860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram 339610515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 339711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 339810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 339911860Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram 340011860Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks) 340110515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 340211860Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks) 340310515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 340411860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks) 340510515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 340611860Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks) 340710515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 340810515SAli.Saidi@ARM.com 340910515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3410