stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.534332 # Number of seconds simulated 4sim_ticks 2534332336000 # Number of ticks simulated 5final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 60160 # Simulator instruction rate (inst/s) 8host_op_rate 77409 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2528112838 # Simulator tick rate (ticks/s) 10host_mem_usage 401532 # Number of bytes of host memory used 11host_seconds 1002.46 # Real time elapsed on the host 12sim_insts 60307773 # Number of instructions simulated 13sim_ops 77599321 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15101237 # Total number of read requests seen 53system.physmem.writeReqs 813162 # Total number of write requests seen 54system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 966479168 # Total number of bytes read from memory 56system.physmem.bytesWritten 52042368 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2534332242000 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 36 # Categorize read packet sizes 99system.physmem.readPktSize::3 14946576 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 154625 # Categorize read packet sizes 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 59144 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 142system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation 431system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays 432system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests 433system.physmem.totBusLat 75504790000 # Total cycles spent in databus access 434system.physmem.totBankLat 15713238750 # Total cycles spent in bank access 435system.physmem.avgQLat 23320.54 # Average queueing delay per request 436system.physmem.avgBankLat 1040.55 # Average bank access latency per request 437system.physmem.avgBusLat 5000.00 # Average bus latency per request 438system.physmem.avgMemAccLat 29361.08 # Average memory access latency 439system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s 440system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s 441system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s 442system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s 443system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 444system.physmem.busUtil 3.14 # Data bus utilization in percentage 445system.physmem.avgRdQLen 0.17 # Average read queue length over time 446system.physmem.avgWrQLen 10.77 # Average write queue length over time 447system.physmem.readRowHits 15074158 # Number of row buffer hits during reads 448system.physmem.writeRowHits 797610 # Number of row buffer hits during writes 449system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads 450system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes 451system.physmem.avgGap 159247.75 # Average gap between requests 452system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 453system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 454system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 455system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 456system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 457system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 458system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 459system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 460system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 461system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 462system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 463system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 464system.membus.throughput 54715776 # Throughput (bytes/s) 465system.membus.trans_dist::ReadReq 16153842 # Transaction distribution 466system.membus.trans_dist::ReadResp 16153842 # Transaction distribution 467system.membus.trans_dist::WriteReq 763336 # Transaction distribution 468system.membus.trans_dist::WriteResp 763336 # Transaction distribution 469system.membus.trans_dist::Writeback 59144 # Transaction distribution 470system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution 471system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 472system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution 473system.membus.trans_dist::ReadExReq 131438 # Transaction distribution 474system.membus.trans_dist::ReadExResp 131438 # Transaction distribution 475system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) 476system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 477system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) 478system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) 479system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 480system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) 481system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) 482system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) 483system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) 484system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 485system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) 486system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) 487system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 488system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) 489system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) 490system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 491system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) 492system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) 493system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 494system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) 495system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) 496system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) 497system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) 498system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 499system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) 500system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) 501system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 502system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) 503system.membus.data_through_bus 138667961 # Total data (bytes) 504system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 505system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) 506system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 507system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 508system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 509system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) 510system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) 511system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) 512system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 513system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) 514system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 515system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) 516system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 517system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) 518system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 519system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 520system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 521system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 522system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 523system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 524system.cf0.dma_write_txs 0 # Number of DMA write transactions. 525system.iobus.throughput 48124265 # Throughput (bytes/s) 526system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution 527system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution 528system.iobus.trans_dist::WriteReq 8158 # Transaction distribution 529system.iobus.trans_dist::WriteResp 8158 # Transaction distribution 530system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 531system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) 532system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) 533system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) 534system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 535system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 536system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 537system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 538system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 539system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 540system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 543system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 544system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 545system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 546system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 547system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 548system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 549system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 550system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 551system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 552system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 553system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) 554system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) 555system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) 556system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 557system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) 558system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) 559system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) 560system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 561system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 562system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 563system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 564system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 565system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 566system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 567system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 568system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 569system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 570system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 571system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 572system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 573system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 574system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 575system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 576system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 577system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 578system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 579system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) 580system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) 581system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 582system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) 583system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) 584system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) 585system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 586system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 587system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 588system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 589system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 590system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 591system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 592system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 593system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 594system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 595system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 596system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 597system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 598system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 599system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 600system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 601system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 602system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 603system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 604system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) 605system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) 606system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) 607system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.data_through_bus 121962881 # Total data (bytes) 633system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 634system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 635system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) 636system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 637system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) 638system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 639system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) 640system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 641system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 642system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 643system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 644system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 645system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 646system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 647system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 648system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 649system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 650system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 651system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 652system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 653system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 654system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 655system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 656system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 657system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 658system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 660system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 662system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 664system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 666system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 667system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 668system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 669system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 670system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 671system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 672system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 673system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 674system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 675system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 676system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 677system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 678system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 679system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) 680system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 681system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) 682system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 683system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) 684system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) 685system.cpu.branchPred.lookups 14663186 # Number of BP lookups 686system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted 687system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect 688system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups 689system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits 690system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 691system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage 692system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. 693system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. 694system.cpu.dtb.inst_hits 0 # ITB inst hits 695system.cpu.dtb.inst_misses 0 # ITB inst misses 696system.cpu.dtb.read_hits 51389107 # DTB read hits 697system.cpu.dtb.read_misses 64168 # DTB read misses 698system.cpu.dtb.write_hits 11699261 # DTB write hits 699system.cpu.dtb.write_misses 15977 # DTB write misses 700system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 701system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 702system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 703system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 704system.cpu.dtb.flush_entries 3558 # Number of entries that have been flushed from TLB 705system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions 706system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch 707system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 708system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions 709system.cpu.dtb.read_accesses 51453275 # DTB read accesses 710system.cpu.dtb.write_accesses 11715238 # DTB write accesses 711system.cpu.dtb.inst_accesses 0 # ITB inst accesses 712system.cpu.dtb.hits 63088368 # DTB hits 713system.cpu.dtb.misses 80145 # DTB misses 714system.cpu.dtb.accesses 63168513 # DTB accesses 715system.cpu.itb.inst_hits 12244686 # ITB inst hits 716system.cpu.itb.inst_misses 11272 # ITB inst misses 717system.cpu.itb.read_hits 0 # DTB read hits 718system.cpu.itb.read_misses 0 # DTB read misses 719system.cpu.itb.write_hits 0 # DTB write hits 720system.cpu.itb.write_misses 0 # DTB write misses 721system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 722system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 723system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 724system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 725system.cpu.itb.flush_entries 2481 # Number of entries that have been flushed from TLB 726system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 727system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 728system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 729system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions 730system.cpu.itb.read_accesses 0 # DTB read accesses 731system.cpu.itb.write_accesses 0 # DTB write accesses 732system.cpu.itb.inst_accesses 12255958 # ITB inst accesses 733system.cpu.itb.hits 12244686 # DTB hits 734system.cpu.itb.misses 11272 # DTB misses 735system.cpu.itb.accesses 12255958 # DTB accesses 736system.cpu.numCycles 475312551 # number of cpu cycles simulated 737system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 738system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 739system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss 740system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed 741system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered 742system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken 743system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked 744system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing 745system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb 746system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked 747system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 748system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps 749system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions 750system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR 751system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched 752system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed 753system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed 754system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) 755system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) 756system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) 757system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 758system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) 759system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) 760system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) 761system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) 762system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) 763system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) 764system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) 765system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) 766system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) 767system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 768system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 769system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 770system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) 771system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle 772system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle 773system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle 774system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked 775system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running 776system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking 777system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing 778system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch 779system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction 780system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode 781system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode 782system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing 783system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle 784system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking 785system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst 786system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running 787system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking 788system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename 789system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full 790system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full 791system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full 792system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers 793system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed 794system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made 795system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups 796system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups 797system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed 798system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing 799system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed 800system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed 801system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer 802system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. 803system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. 804system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. 805system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. 806system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) 807system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ 808system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued 809system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued 810system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling 811system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph 812system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed 813system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle 814system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle 815system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle 816system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 817system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle 818system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle 819system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle 820system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle 821system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle 822system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle 823system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle 824system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle 825system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle 826system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 827system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 828system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 829system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle 830system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 831system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available 832system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available 833system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available 834system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available 835system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available 836system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available 837system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available 838system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available 839system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available 840system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available 841system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available 842system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available 843system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available 844system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available 845system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available 846system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available 847system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available 848system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available 849system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available 850system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available 851system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available 852system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available 853system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available 854system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available 855system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available 856system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available 857system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available 858system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available 859system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available 860system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available 861system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available 862system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 863system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 864system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued 865system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued 866system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued 867system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued 868system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued 869system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued 870system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued 871system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued 872system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued 873system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued 874system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued 875system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued 876system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued 877system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued 878system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued 879system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued 880system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued 881system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued 882system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued 883system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued 884system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued 885system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued 886system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued 887system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued 888system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued 889system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued 890system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued 891system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued 892system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued 893system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued 894system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued 895system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued 896system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 897system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 898system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued 899system.cpu.iq.rate 0.261503 # Inst issue rate 900system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested 901system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) 902system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads 903system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes 904system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses 905system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads 906system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes 907system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses 908system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses 909system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses 910system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores 911system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 912system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed 913system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed 914system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations 915system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed 916system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 917system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 918system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled 919system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked 920system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 921system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing 922system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking 923system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking 924system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ 925system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch 926system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions 927system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions 928system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions 929system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall 930system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall 931system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations 932system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly 933system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly 934system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute 935system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions 936system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed 937system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute 938system.cpu.iew.exec_swp 0 # number of swp insts executed 939system.cpu.iew.exec_nop 222537 # number of nop insts executed 940system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed 941system.cpu.iew.exec_branches 11556571 # Number of branches executed 942system.cpu.iew.exec_stores 12211191 # Number of stores executed 943system.cpu.iew.exec_rate 0.255895 # Inst execution rate 944system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit 945system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back 946system.cpu.iew.wb_producers 47268516 # num instructions producing a value 947system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value 948system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 949system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle 950system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back 951system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 952system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit 953system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards 954system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted 955system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle 956system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle 957system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle 958system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 959system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle 960system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle 961system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle 962system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle 963system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle 964system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle 965system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle 966system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle 967system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle 968system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 969system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 970system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 971system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle 972system.cpu.commit.committedInsts 60458154 # Number of instructions committed 973system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed 974system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 975system.cpu.commit.refs 27386643 # Number of memory references committed 976system.cpu.commit.loads 15654562 # Number of loads committed 977system.cpu.commit.membars 403601 # Number of memory barriers committed 978system.cpu.commit.branches 9961356 # Number of branches committed 979system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 980system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. 981system.cpu.commit.function_calls 991265 # Number of function calls committed. 982system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached 983system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 984system.cpu.rob.rob_reads 243752783 # The number of ROB reads 985system.cpu.rob.rob_writes 201807644 # The number of ROB writes 986system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself 987system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling 988system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 989system.cpu.committedInsts 60307773 # Number of Instructions Simulated 990system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated 991system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated 992system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction 993system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads 994system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle 995system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads 996system.cpu.int_regfile_reads 550637144 # number of integer regfile reads 997system.cpu.int_regfile_writes 88566595 # number of integer regfile writes 998system.cpu.fp_regfile_reads 8370 # number of floating regfile reads 999system.cpu.fp_regfile_writes 2906 # number of floating regfile writes 1000system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads 1001system.cpu.misc_regfile_writes 831896 # number of misc regfile writes 1002system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) 1003system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution 1006system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution 1009system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution 1010system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution 1011system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution 1012system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution 1013system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) 1014system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) 1015system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) 1016system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) 1017system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) 1018system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) 1019system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) 1020system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) 1021system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) 1022system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) 1023system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) 1024system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) 1025system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) 1026system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1027system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) 1028system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1029system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) 1030system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1031system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) 1032system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1033system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) 1034system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1035system.cpu.icache.tags.replacements 980590 # number of replacements 1036system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use 1037system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. 1038system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. 1039system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. 1040system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. 1041system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor 1042system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy 1043system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy 1044system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits 1045system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits 1046system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits 1047system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits 1048system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits 1049system.cpu.icache.overall_hits::total 11180201 # number of overall hits 1050system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses 1051system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses 1052system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses 1053system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses 1054system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses 1055system.cpu.icache.overall_misses::total 1060929 # number of overall misses 1056system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles 1057system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles 1058system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles 1059system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles 1060system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles 1061system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles 1062system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) 1063system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) 1064system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses 1065system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses 1066system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses 1067system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses 1068system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses 1069system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses 1070system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses 1071system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses 1072system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses 1073system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses 1074system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency 1075system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency 1076system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency 1077system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency 1078system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency 1079system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency 1080system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked 1081system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1082system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked 1083system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1084system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked 1085system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1086system.cpu.icache.fast_writes 0 # number of fast writes performed 1087system.cpu.icache.cache_copies 0 # number of cache copies performed 1088system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79785 # number of ReadReq MSHR hits 1089system.cpu.icache.ReadReq_mshr_hits::total 79785 # number of ReadReq MSHR hits 1090system.cpu.icache.demand_mshr_hits::cpu.inst 79785 # number of demand (read+write) MSHR hits 1091system.cpu.icache.demand_mshr_hits::total 79785 # number of demand (read+write) MSHR hits 1092system.cpu.icache.overall_mshr_hits::cpu.inst 79785 # number of overall MSHR hits 1093system.cpu.icache.overall_mshr_hits::total 79785 # number of overall MSHR hits 1094system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981144 # number of ReadReq MSHR misses 1095system.cpu.icache.ReadReq_mshr_misses::total 981144 # number of ReadReq MSHR misses 1096system.cpu.icache.demand_mshr_misses::cpu.inst 981144 # number of demand (read+write) MSHR misses 1097system.cpu.icache.demand_mshr_misses::total 981144 # number of demand (read+write) MSHR misses 1098system.cpu.icache.overall_mshr_misses::cpu.inst 981144 # number of overall MSHR misses 1099system.cpu.icache.overall_mshr_misses::total 981144 # number of overall MSHR misses 1100system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11597968227 # number of ReadReq MSHR miss cycles 1101system.cpu.icache.ReadReq_mshr_miss_latency::total 11597968227 # number of ReadReq MSHR miss cycles 1102system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11597968227 # number of demand (read+write) MSHR miss cycles 1103system.cpu.icache.demand_mshr_miss_latency::total 11597968227 # number of demand (read+write) MSHR miss cycles 1104system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11597968227 # number of overall MSHR miss cycles 1105system.cpu.icache.overall_mshr_miss_latency::total 11597968227 # number of overall MSHR miss cycles 1106system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9563750 # number of ReadReq MSHR uncacheable cycles 1107system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9563750 # number of ReadReq MSHR uncacheable cycles 1108system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9563750 # number of overall MSHR uncacheable cycles 1109system.cpu.icache.overall_mshr_uncacheable_latency::total 9563750 # number of overall MSHR uncacheable cycles 1110system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for ReadReq accesses 1111system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080151 # mshr miss rate for ReadReq accesses 1112system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for demand accesses 1113system.cpu.icache.demand_mshr_miss_rate::total 0.080151 # mshr miss rate for demand accesses 1114system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for overall accesses 1115system.cpu.icache.overall_mshr_miss_rate::total 0.080151 # mshr miss rate for overall accesses 1116system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11820.862409 # average ReadReq mshr miss latency 1117system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11820.862409 # average ReadReq mshr miss latency 1118system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency 1119system.cpu.icache.demand_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency 1120system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency 1121system.cpu.icache.overall_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency 1122system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1123system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1124system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1125system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1126system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1127system.cpu.l2cache.tags.replacements 64396 # number of replacements 1128system.cpu.l2cache.tags.tagsinuse 51354.796312 # Cycle average of tags in use 1129system.cpu.l2cache.tags.total_refs 1885755 # Total number of references to valid blocks. 1130system.cpu.l2cache.tags.sampled_refs 129794 # Sample count of references to valid blocks. 1131system.cpu.l2cache.tags.avg_refs 14.528830 # Average number of references to valid blocks. 1132system.cpu.l2cache.tags.warmup_cycle 2499257274500 # Cycle when the warmup percentage was hit. 1133system.cpu.l2cache.tags.occ_blocks::writebacks 36876.248148 # Average occupied blocks per requestor 1134system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.469348 # Average occupied blocks per requestor 1135system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000368 # Average occupied blocks per requestor 1136system.cpu.l2cache.tags.occ_blocks::cpu.inst 8188.920307 # Average occupied blocks per requestor 1137system.cpu.l2cache.tags.occ_blocks::cpu.data 6258.158141 # Average occupied blocks per requestor 1138system.cpu.l2cache.tags.occ_percent::writebacks 0.562687 # Average percentage of cache occupancy 1139system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000480 # Average percentage of cache occupancy 1140system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 1141system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124953 # Average percentage of cache occupancy 1142system.cpu.l2cache.tags.occ_percent::cpu.data 0.095492 # Average percentage of cache occupancy 1143system.cpu.l2cache.tags.occ_percent::total 0.783612 # Average percentage of cache occupancy 1144system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52377 # number of ReadReq hits 1145system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10330 # number of ReadReq hits 1146system.cpu.l2cache.ReadReq_hits::cpu.inst 967621 # number of ReadReq hits 1147system.cpu.l2cache.ReadReq_hits::cpu.data 386975 # number of ReadReq hits 1148system.cpu.l2cache.ReadReq_hits::total 1417303 # number of ReadReq hits 1149system.cpu.l2cache.Writeback_hits::writebacks 607541 # number of Writeback hits 1150system.cpu.l2cache.Writeback_hits::total 607541 # number of Writeback hits 1151system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits 1152system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits 1153system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits 1154system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits 1155system.cpu.l2cache.ReadExReq_hits::cpu.data 112810 # number of ReadExReq hits 1156system.cpu.l2cache.ReadExReq_hits::total 112810 # number of ReadExReq hits 1157system.cpu.l2cache.demand_hits::cpu.dtb.walker 52377 # number of demand (read+write) hits 1158system.cpu.l2cache.demand_hits::cpu.itb.walker 10330 # number of demand (read+write) hits 1159system.cpu.l2cache.demand_hits::cpu.inst 967621 # number of demand (read+write) hits 1160system.cpu.l2cache.demand_hits::cpu.data 499785 # number of demand (read+write) hits 1161system.cpu.l2cache.demand_hits::total 1530113 # number of demand (read+write) hits 1162system.cpu.l2cache.overall_hits::cpu.dtb.walker 52377 # number of overall hits 1163system.cpu.l2cache.overall_hits::cpu.itb.walker 10330 # number of overall hits 1164system.cpu.l2cache.overall_hits::cpu.inst 967621 # number of overall hits 1165system.cpu.l2cache.overall_hits::cpu.data 499785 # number of overall hits 1166system.cpu.l2cache.overall_hits::total 1530113 # number of overall hits 1167system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses 1168system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1169system.cpu.l2cache.ReadReq_misses::cpu.inst 12364 # number of ReadReq misses 1170system.cpu.l2cache.ReadReq_misses::cpu.data 10739 # number of ReadReq misses 1171system.cpu.l2cache.ReadReq_misses::total 23149 # number of ReadReq misses 1172system.cpu.l2cache.UpgradeReq_misses::cpu.data 2922 # number of UpgradeReq misses 1173system.cpu.l2cache.UpgradeReq_misses::total 2922 # number of UpgradeReq misses 1174system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1175system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1176system.cpu.l2cache.ReadExReq_misses::cpu.data 133189 # number of ReadExReq misses 1177system.cpu.l2cache.ReadExReq_misses::total 133189 # number of ReadExReq misses 1178system.cpu.l2cache.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses 1179system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1180system.cpu.l2cache.demand_misses::cpu.inst 12364 # number of demand (read+write) misses 1181system.cpu.l2cache.demand_misses::cpu.data 143928 # number of demand (read+write) misses 1182system.cpu.l2cache.demand_misses::total 156338 # number of demand (read+write) misses 1183system.cpu.l2cache.overall_misses::cpu.dtb.walker 44 # number of overall misses 1184system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1185system.cpu.l2cache.overall_misses::cpu.inst 12364 # number of overall misses 1186system.cpu.l2cache.overall_misses::cpu.data 143928 # number of overall misses 1187system.cpu.l2cache.overall_misses::total 156338 # number of overall misses 1188system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4379500 # number of ReadReq miss cycles 1189system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles 1190system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 918927250 # number of ReadReq miss cycles 1191system.cpu.l2cache.ReadReq_miss_latency::cpu.data 809103750 # number of ReadReq miss cycles 1192system.cpu.l2cache.ReadReq_miss_latency::total 1732540750 # number of ReadReq miss cycles 1193system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 487979 # number of UpgradeReq miss cycles 1194system.cpu.l2cache.UpgradeReq_miss_latency::total 487979 # number of UpgradeReq miss cycles 1195system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9125635499 # number of ReadExReq miss cycles 1196system.cpu.l2cache.ReadExReq_miss_latency::total 9125635499 # number of ReadExReq miss cycles 1197system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4379500 # number of demand (read+write) miss cycles 1198system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles 1199system.cpu.l2cache.demand_miss_latency::cpu.inst 918927250 # number of demand (read+write) miss cycles 1200system.cpu.l2cache.demand_miss_latency::cpu.data 9934739249 # number of demand (read+write) miss cycles 1201system.cpu.l2cache.demand_miss_latency::total 10858176249 # number of demand (read+write) miss cycles 1202system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4379500 # number of overall miss cycles 1203system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles 1204system.cpu.l2cache.overall_miss_latency::cpu.inst 918927250 # number of overall miss cycles 1205system.cpu.l2cache.overall_miss_latency::cpu.data 9934739249 # number of overall miss cycles 1206system.cpu.l2cache.overall_miss_latency::total 10858176249 # number of overall miss cycles 1207system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52421 # number of ReadReq accesses(hits+misses) 1208system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10332 # number of ReadReq accesses(hits+misses) 1209system.cpu.l2cache.ReadReq_accesses::cpu.inst 979985 # number of ReadReq accesses(hits+misses) 1210system.cpu.l2cache.ReadReq_accesses::cpu.data 397714 # number of ReadReq accesses(hits+misses) 1211system.cpu.l2cache.ReadReq_accesses::total 1440452 # number of ReadReq accesses(hits+misses) 1212system.cpu.l2cache.Writeback_accesses::writebacks 607541 # number of Writeback accesses(hits+misses) 1213system.cpu.l2cache.Writeback_accesses::total 607541 # number of Writeback accesses(hits+misses) 1214system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) 1215system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) 1216system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) 1217system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) 1218system.cpu.l2cache.ReadExReq_accesses::cpu.data 245999 # number of ReadExReq accesses(hits+misses) 1219system.cpu.l2cache.ReadExReq_accesses::total 245999 # number of ReadExReq accesses(hits+misses) 1220system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52421 # number of demand (read+write) accesses 1221system.cpu.l2cache.demand_accesses::cpu.itb.walker 10332 # number of demand (read+write) accesses 1222system.cpu.l2cache.demand_accesses::cpu.inst 979985 # number of demand (read+write) accesses 1223system.cpu.l2cache.demand_accesses::cpu.data 643713 # number of demand (read+write) accesses 1224system.cpu.l2cache.demand_accesses::total 1686451 # number of demand (read+write) accesses 1225system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52421 # number of overall (read+write) accesses 1226system.cpu.l2cache.overall_accesses::cpu.itb.walker 10332 # number of overall (read+write) accesses 1227system.cpu.l2cache.overall_accesses::cpu.inst 979985 # number of overall (read+write) accesses 1228system.cpu.l2cache.overall_accesses::cpu.data 643713 # number of overall (read+write) accesses 1229system.cpu.l2cache.overall_accesses::total 1686451 # number of overall (read+write) accesses 1230system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000839 # miss rate for ReadReq accesses 1231system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000194 # miss rate for ReadReq accesses 1232system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012617 # miss rate for ReadReq accesses 1233system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027002 # miss rate for ReadReq accesses 1234system.cpu.l2cache.ReadReq_miss_rate::total 0.016071 # miss rate for ReadReq accesses 1235system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985165 # miss rate for UpgradeReq accesses 1236system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985165 # miss rate for UpgradeReq accesses 1237system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses 1238system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses 1239system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541421 # miss rate for ReadExReq accesses 1240system.cpu.l2cache.ReadExReq_miss_rate::total 0.541421 # miss rate for ReadExReq accesses 1241system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000839 # miss rate for demand accesses 1242system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000194 # miss rate for demand accesses 1243system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012617 # miss rate for demand accesses 1244system.cpu.l2cache.demand_miss_rate::cpu.data 0.223590 # miss rate for demand accesses 1245system.cpu.l2cache.demand_miss_rate::total 0.092702 # miss rate for demand accesses 1246system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000839 # miss rate for overall accesses 1247system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000194 # miss rate for overall accesses 1248system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012617 # miss rate for overall accesses 1249system.cpu.l2cache.overall_miss_rate::cpu.data 0.223590 # miss rate for overall accesses 1250system.cpu.l2cache.overall_miss_rate::total 0.092702 # miss rate for overall accesses 1251system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 99534.090909 # average ReadReq miss latency 1252system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency 1253system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74322.812197 # average ReadReq miss latency 1254system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75342.559829 # average ReadReq miss latency 1255system.cpu.l2cache.ReadReq_avg_miss_latency::total 74843.006177 # average ReadReq miss latency 1256system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 167.001711 # average UpgradeReq miss latency 1257system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 167.001711 # average UpgradeReq miss latency 1258system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68516.435284 # average ReadExReq miss latency 1259system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68516.435284 # average ReadExReq miss latency 1260system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 99534.090909 # average overall miss latency 1261system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency 1262system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74322.812197 # average overall miss latency 1263system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69025.757664 # average overall miss latency 1264system.cpu.l2cache.demand_avg_miss_latency::total 69453.211945 # average overall miss latency 1265system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 99534.090909 # average overall miss latency 1266system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency 1267system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74322.812197 # average overall miss latency 1268system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69025.757664 # average overall miss latency 1269system.cpu.l2cache.overall_avg_miss_latency::total 69453.211945 # average overall miss latency 1270system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1271system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1272system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1273system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1274system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1275system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1276system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1277system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1278system.cpu.l2cache.writebacks::writebacks 59144 # number of writebacks 1279system.cpu.l2cache.writebacks::total 59144 # number of writebacks 1280system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 1281system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 1282system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits 1283system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 1284system.cpu.l2cache.demand_mshr_hits::cpu.data 69 # number of demand (read+write) MSHR hits 1285system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits 1286system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits 1287system.cpu.l2cache.overall_mshr_hits::cpu.data 69 # number of overall MSHR hits 1288system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits 1289system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 44 # number of ReadReq MSHR misses 1290system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1291system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12352 # number of ReadReq MSHR misses 1292system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10670 # number of ReadReq MSHR misses 1293system.cpu.l2cache.ReadReq_mshr_misses::total 23068 # number of ReadReq MSHR misses 1294system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2922 # number of UpgradeReq MSHR misses 1295system.cpu.l2cache.UpgradeReq_mshr_misses::total 2922 # number of UpgradeReq MSHR misses 1296system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1297system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1298system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133189 # number of ReadExReq MSHR misses 1299system.cpu.l2cache.ReadExReq_mshr_misses::total 133189 # number of ReadExReq MSHR misses 1300system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 44 # number of demand (read+write) MSHR misses 1301system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1302system.cpu.l2cache.demand_mshr_misses::cpu.inst 12352 # number of demand (read+write) MSHR misses 1303system.cpu.l2cache.demand_mshr_misses::cpu.data 143859 # number of demand (read+write) MSHR misses 1304system.cpu.l2cache.demand_mshr_misses::total 156257 # number of demand (read+write) MSHR misses 1305system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 44 # number of overall MSHR misses 1306system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1307system.cpu.l2cache.overall_mshr_misses::cpu.inst 12352 # number of overall MSHR misses 1308system.cpu.l2cache.overall_mshr_misses::cpu.data 143859 # number of overall MSHR misses 1309system.cpu.l2cache.overall_mshr_misses::total 156257 # number of overall MSHR misses 1310system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3822500 # number of ReadReq MSHR miss cycles 1311system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles 1312system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 761684000 # number of ReadReq MSHR miss cycles 1313system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 670036500 # number of ReadReq MSHR miss cycles 1314system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1435648750 # number of ReadReq MSHR miss cycles 1315system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29223421 # number of UpgradeReq MSHR miss cycles 1316system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29223421 # number of UpgradeReq MSHR miss cycles 1317system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1318system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 1319system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7438270001 # number of ReadExReq MSHR miss cycles 1320system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7438270001 # number of ReadExReq MSHR miss cycles 1321system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3822500 # number of demand (read+write) MSHR miss cycles 1322system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles 1323system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 761684000 # number of demand (read+write) MSHR miss cycles 1324system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8108306501 # number of demand (read+write) MSHR miss cycles 1325system.cpu.l2cache.demand_mshr_miss_latency::total 8873918751 # number of demand (read+write) MSHR miss cycles 1326system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3822500 # number of overall MSHR miss cycles 1327system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles 1328system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 761684000 # number of overall MSHR miss cycles 1329system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8108306501 # number of overall MSHR miss cycles 1330system.cpu.l2cache.overall_mshr_miss_latency::total 8873918751 # number of overall MSHR miss cycles 1331system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 7076250 # number of ReadReq MSHR uncacheable cycles 1332system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166924302000 # number of ReadReq MSHR uncacheable cycles 1333system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166931378250 # number of ReadReq MSHR uncacheable cycles 1334system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26354291876 # number of WriteReq MSHR uncacheable cycles 1335system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26354291876 # number of WriteReq MSHR uncacheable cycles 1336system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7076250 # number of overall MSHR uncacheable cycles 1337system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193278593876 # number of overall MSHR uncacheable cycles 1338system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193285670126 # number of overall MSHR uncacheable cycles 1339system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses 1340system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for ReadReq accesses 1341system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for ReadReq accesses 1342system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses 1343system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016014 # mshr miss rate for ReadReq accesses 1344system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985165 # mshr miss rate for UpgradeReq accesses 1345system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985165 # mshr miss rate for UpgradeReq accesses 1346system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses 1347system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses 1348system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541421 # mshr miss rate for ReadExReq accesses 1349system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541421 # mshr miss rate for ReadExReq accesses 1350system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses 1351system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for demand accesses 1352system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for demand accesses 1353system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223483 # mshr miss rate for demand accesses 1354system.cpu.l2cache.demand_mshr_miss_rate::total 0.092654 # mshr miss rate for demand accesses 1355system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for overall accesses 1356system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for overall accesses 1357system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for overall accesses 1358system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223483 # mshr miss rate for overall accesses 1359system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses 1360system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average ReadReq mshr miss latency 1361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency 1362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61664.831606 # average ReadReq mshr miss latency 1363system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62796.298032 # average ReadReq mshr miss latency 1364system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62235.510231 # average ReadReq mshr miss latency 1365system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.170773 # average UpgradeReq mshr miss latency 1366system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.170773 # average UpgradeReq mshr miss latency 1367system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1368system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1369system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55847.479904 # average ReadExReq mshr miss latency 1370system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55847.479904 # average ReadExReq mshr miss latency 1371system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average overall mshr miss latency 1372system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1373system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61664.831606 # average overall mshr miss latency 1374system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency 1375system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency 1376system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average overall mshr miss latency 1377system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1378system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61664.831606 # average overall mshr miss latency 1379system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency 1380system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency 1381system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1382system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1383system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1384system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1385system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1386system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1387system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1388system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1389system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1390system.cpu.dcache.tags.replacements 643201 # number of replacements 1391system.cpu.dcache.tags.tagsinuse 511.992056 # Cycle average of tags in use 1392system.cpu.dcache.tags.total_refs 21499493 # Total number of references to valid blocks. 1393system.cpu.dcache.tags.sampled_refs 643713 # Sample count of references to valid blocks. 1394system.cpu.dcache.tags.avg_refs 33.399190 # Average number of references to valid blocks. 1395system.cpu.dcache.tags.warmup_cycle 48741250 # Cycle when the warmup percentage was hit. 1396system.cpu.dcache.tags.occ_blocks::cpu.data 511.992056 # Average occupied blocks per requestor 1397system.cpu.dcache.tags.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy 1398system.cpu.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy 1399system.cpu.dcache.ReadReq_hits::cpu.data 13746666 # number of ReadReq hits 1400system.cpu.dcache.ReadReq_hits::total 13746666 # number of ReadReq hits 1401system.cpu.dcache.WriteReq_hits::cpu.data 7259188 # number of WriteReq hits 1402system.cpu.dcache.WriteReq_hits::total 7259188 # number of WriteReq hits 1403system.cpu.dcache.LoadLockedReq_hits::cpu.data 242891 # number of LoadLockedReq hits 1404system.cpu.dcache.LoadLockedReq_hits::total 242891 # number of LoadLockedReq hits 1405system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits 1406system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits 1407system.cpu.dcache.demand_hits::cpu.data 21005854 # number of demand (read+write) hits 1408system.cpu.dcache.demand_hits::total 21005854 # number of demand (read+write) hits 1409system.cpu.dcache.overall_hits::cpu.data 21005854 # number of overall hits 1410system.cpu.dcache.overall_hits::total 21005854 # number of overall hits 1411system.cpu.dcache.ReadReq_misses::cpu.data 736262 # number of ReadReq misses 1412system.cpu.dcache.ReadReq_misses::total 736262 # number of ReadReq misses 1413system.cpu.dcache.WriteReq_misses::cpu.data 2963161 # number of WriteReq misses 1414system.cpu.dcache.WriteReq_misses::total 2963161 # number of WriteReq misses 1415system.cpu.dcache.LoadLockedReq_misses::cpu.data 13548 # number of LoadLockedReq misses 1416system.cpu.dcache.LoadLockedReq_misses::total 13548 # number of LoadLockedReq misses 1417system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses 1418system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses 1419system.cpu.dcache.demand_misses::cpu.data 3699423 # number of demand (read+write) misses 1420system.cpu.dcache.demand_misses::total 3699423 # number of demand (read+write) misses 1421system.cpu.dcache.overall_misses::cpu.data 3699423 # number of overall misses 1422system.cpu.dcache.overall_misses::total 3699423 # number of overall misses 1423system.cpu.dcache.ReadReq_miss_latency::cpu.data 10077942358 # number of ReadReq miss cycles 1424system.cpu.dcache.ReadReq_miss_latency::total 10077942358 # number of ReadReq miss cycles 1425system.cpu.dcache.WriteReq_miss_latency::cpu.data 134690017209 # number of WriteReq miss cycles 1426system.cpu.dcache.WriteReq_miss_latency::total 134690017209 # number of WriteReq miss cycles 1427system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184520250 # number of LoadLockedReq miss cycles 1428system.cpu.dcache.LoadLockedReq_miss_latency::total 184520250 # number of LoadLockedReq miss cycles 1429system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 258503 # number of StoreCondReq miss cycles 1430system.cpu.dcache.StoreCondReq_miss_latency::total 258503 # number of StoreCondReq miss cycles 1431system.cpu.dcache.demand_miss_latency::cpu.data 144767959567 # number of demand (read+write) miss cycles 1432system.cpu.dcache.demand_miss_latency::total 144767959567 # number of demand (read+write) miss cycles 1433system.cpu.dcache.overall_miss_latency::cpu.data 144767959567 # number of overall miss cycles 1434system.cpu.dcache.overall_miss_latency::total 144767959567 # number of overall miss cycles 1435system.cpu.dcache.ReadReq_accesses::cpu.data 14482928 # number of ReadReq accesses(hits+misses) 1436system.cpu.dcache.ReadReq_accesses::total 14482928 # number of ReadReq accesses(hits+misses) 1437system.cpu.dcache.WriteReq_accesses::cpu.data 10222349 # number of WriteReq accesses(hits+misses) 1438system.cpu.dcache.WriteReq_accesses::total 10222349 # number of WriteReq accesses(hits+misses) 1439system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256439 # number of LoadLockedReq accesses(hits+misses) 1440system.cpu.dcache.LoadLockedReq_accesses::total 256439 # number of LoadLockedReq accesses(hits+misses) 1441system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) 1442system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) 1443system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses 1444system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses 1445system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses 1446system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses 1447system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses 1448system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses 1449system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses 1450system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses 1451system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses 1452system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses 1453system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses 1454system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses 1455system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses 1456system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses 1457system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses 1458system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses 1459system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency 1460system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency 1461system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency 1462system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency 1463system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency 1464system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency 1465system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency 1466system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency 1467system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency 1468system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency 1469system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency 1470system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # average overall miss latency 1471system.cpu.dcache.blocked_cycles::no_mshrs 32140 # number of cycles access was blocked 1472system.cpu.dcache.blocked_cycles::no_targets 25391 # number of cycles access was blocked 1473system.cpu.dcache.blocked::no_mshrs 2640 # number of cycles access was blocked 1474system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked 1475system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.174242 # average number of cycles each access was blocked 1476system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked 1477system.cpu.dcache.fast_writes 0 # number of fast writes performed 1478system.cpu.dcache.cache_copies 0 # number of cache copies performed 1479system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks 1480system.cpu.dcache.writebacks::total 607541 # number of writebacks 1481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits 1482system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits 1483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits 1484system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits 1485system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits 1486system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits 1487system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits 1488system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits 1489system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits 1490system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits 1491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses 1492system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses 1493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses 1494system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses 1495system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses 1496system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses 1497system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses 1498system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses 1499system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses 1500system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses 1501system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses 1502system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses 1503system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles 1504system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles 1505system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles 1506system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles 1507system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles 1508system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles 1509system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles 1510system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles 1511system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles 1512system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles 1513system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles 1514system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles 1515system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles 1516system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles 1517system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles 1518system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles 1519system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles 1520system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles 1521system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses 1522system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses 1523system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses 1524system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses 1525system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses 1526system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses 1527system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses 1528system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses 1529system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses 1530system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses 1531system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses 1532system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses 1533system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency 1534system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency 1535system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency 1536system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency 1537system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency 1538system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency 1539system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency 1540system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency 1541system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency 1542system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency 1543system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency 1544system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency 1545system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1546system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1547system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1548system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1549system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1550system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1551system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1552system.iocache.tags.replacements 0 # number of replacements 1553system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1554system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1555system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1556system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1557system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1558system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1559system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1560system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1561system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1562system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1563system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1564system.iocache.fast_writes 0 # number of fast writes performed 1565system.iocache.cache_copies 0 # number of cache copies performed 1566system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles 1567system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles 1568system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles 1569system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles 1570system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1571system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1572system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1573system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1574system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1575system.cpu.kern.inst.arm 0 # number of arm instructions executed 1576system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed 1577 1578---------- End Simulation Statistics ---------- 1579