stats.txt revision 9661:18755c467503
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.533116 # Number of seconds simulated 4sim_ticks 2533115780500 # Number of ticks simulated 5final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 64757 # Simulator instruction rate (inst/s) 8host_op_rate 83325 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2720016614 # Simulator tick rate (ticks/s) 10host_mem_usage 398876 # Number of bytes of host memory used 11host_seconds 931.29 # Real time elapsed on the host 12sim_insts 60307726 # Number of instructions simulated 13sim_ops 77599286 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15096806 # Total number of read requests seen 53system.physmem.writeReqs 813108 # Total number of write requests seen 54system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 966195584 # Total number of bytes read from memory 56system.physmem.bytesWritten 52038912 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2533114676500 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 36 # Categorize read packet sizes 99system.physmem.readPktSize::3 14942208 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 154562 # Categorize read packet sizes 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 59090 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 142system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see 174system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests 176system.physmem.totBusLat 75482470000 # Total cycles spent in databus access 177system.physmem.totBankLat 16917518750 # Total cycles spent in bank access 178system.physmem.avgQLat 26047.39 # Average queueing delay per request 179system.physmem.avgBankLat 1120.63 # Average bank access latency per request 180system.physmem.avgBusLat 5000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 32168.02 # Average memory access latency 182system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 3.14 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.19 # Average read queue length over time 189system.physmem.avgWrQLen 11.11 # Average write queue length over time 190system.physmem.readRowHits 15020181 # Number of row buffer hits during reads 191system.physmem.writeRowHits 793022 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes 194system.physmem.avgGap 159216.11 # Average gap between requests 195system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 196system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 197system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 198system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 199system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 200system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 201system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 202system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 203system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 204system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 205system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 206system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 207system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 208system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 211system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 212system.cf0.dma_write_txs 0 # Number of DMA write transactions. 213system.cpu.branchPred.lookups 14672817 # Number of BP lookups 214system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted 215system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect 216system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups 217system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits 218system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 219system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage 220system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. 221system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. 222system.cpu.dtb.inst_hits 0 # ITB inst hits 223system.cpu.dtb.inst_misses 0 # ITB inst misses 224system.cpu.dtb.read_hits 51400888 # DTB read hits 225system.cpu.dtb.read_misses 64225 # DTB read misses 226system.cpu.dtb.write_hits 11700104 # DTB write hits 227system.cpu.dtb.write_misses 15848 # DTB write misses 228system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 229system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 230system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 231system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 232system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB 233system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions 234system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch 235system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 236system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions 237system.cpu.dtb.read_accesses 51465113 # DTB read accesses 238system.cpu.dtb.write_accesses 11715952 # DTB write accesses 239system.cpu.dtb.inst_accesses 0 # ITB inst accesses 240system.cpu.dtb.hits 63100992 # DTB hits 241system.cpu.dtb.misses 80073 # DTB misses 242system.cpu.dtb.accesses 63181065 # DTB accesses 243system.cpu.itb.inst_hits 12331220 # ITB inst hits 244system.cpu.itb.inst_misses 11422 # ITB inst misses 245system.cpu.itb.read_hits 0 # DTB read hits 246system.cpu.itb.read_misses 0 # DTB read misses 247system.cpu.itb.write_hits 0 # DTB write hits 248system.cpu.itb.write_misses 0 # DTB write misses 249system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 250system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 251system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 252system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 253system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB 254system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 255system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 256system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 257system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions 258system.cpu.itb.read_accesses 0 # DTB read accesses 259system.cpu.itb.write_accesses 0 # DTB write accesses 260system.cpu.itb.inst_accesses 12342642 # ITB inst accesses 261system.cpu.itb.hits 12331220 # DTB hits 262system.cpu.itb.misses 11422 # DTB misses 263system.cpu.itb.accesses 12342642 # DTB accesses 264system.cpu.numCycles 471822965 # number of cpu cycles simulated 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 267system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken 271system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked 272system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing 273system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb 274system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked 275system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps 277system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR 279system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed 282system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle 300system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle 301system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle 302system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked 303system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running 304system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking 305system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing 306system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch 307system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction 308system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode 309system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode 310system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing 311system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle 312system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking 313system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst 314system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running 315system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking 316system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename 317system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full 318system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full 319system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full 320system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers 321system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed 322system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made 323system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups 324system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups 325system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed 326system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing 327system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed 328system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed 329system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer 330system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. 331system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. 332system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. 333system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. 334system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) 335system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ 336system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued 337system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued 338system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling 339system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph 340system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed 341system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle 358system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 359system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available 360system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 388system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available 389system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available 390system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 391system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 392system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued 393system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued 394system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued 395system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued 422system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued 423system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued 424system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 426system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued 427system.cpu.iq.rate 0.263501 # Inst issue rate 428system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested 429system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) 430system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads 431system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes 432system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses 433system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads 434system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes 435system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses 436system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses 437system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses 438system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores 439system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 440system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed 441system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed 442system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations 443system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed 444system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 445system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 446system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled 447system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked 448system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 449system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing 450system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking 451system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking 452system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ 453system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch 454system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions 455system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions 456system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions 457system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall 458system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall 459system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations 460system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly 461system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly 462system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute 463system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions 464system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed 465system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute 466system.cpu.iew.exec_swp 0 # number of swp insts executed 467system.cpu.iew.exec_nop 221132 # number of nop insts executed 468system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed 469system.cpu.iew.exec_branches 11557425 # Number of branches executed 470system.cpu.iew.exec_stores 12211932 # Number of stores executed 471system.cpu.iew.exec_rate 0.257596 # Inst execution rate 472system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit 473system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back 474system.cpu.iew.wb_producers 47248258 # num instructions producing a value 475system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value 476system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 477system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle 478system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back 479system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 480system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit 481system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards 482system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted 483system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle 500system.cpu.commit.committedInsts 60458107 # Number of instructions committed 501system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed 502system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 503system.cpu.commit.refs 27386657 # Number of memory references committed 504system.cpu.commit.loads 15654563 # Number of loads committed 505system.cpu.commit.membars 403601 # Number of memory barriers committed 506system.cpu.commit.branches 9961339 # Number of branches committed 507system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 508system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. 509system.cpu.commit.function_calls 991261 # Number of function calls committed. 510system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached 511system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 512system.cpu.rob.rob_reads 242323943 # The number of ROB reads 513system.cpu.rob.rob_writes 202004834 # The number of ROB writes 514system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself 515system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling 516system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 517system.cpu.committedInsts 60307726 # Number of Instructions Simulated 518system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated 519system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated 520system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction 521system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads 522system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle 523system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads 524system.cpu.int_regfile_reads 550297300 # number of integer regfile reads 525system.cpu.int_regfile_writes 88455600 # number of integer regfile writes 526system.cpu.fp_regfile_reads 8347 # number of floating regfile reads 527system.cpu.fp_regfile_writes 2910 # number of floating regfile writes 528system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads 529system.cpu.misc_regfile_writes 831893 # number of misc regfile writes 530system.cpu.icache.replacements 979954 # number of replacements 531system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use 532system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. 533system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. 534system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. 535system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. 536system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor 537system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy 538system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy 539system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits 540system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits 541system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits 542system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits 543system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits 544system.cpu.icache.overall_hits::total 11267650 # number of overall hits 545system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses 546system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses 547system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses 548system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses 549system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses 550system.cpu.icache.overall_misses::total 1060047 # number of overall misses 551system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles 552system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles 553system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles 554system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles 555system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles 556system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles 557system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) 558system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) 559system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses 560system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses 561system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses 562system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses 563system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses 564system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses 565system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses 566system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses 567system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses 568system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses 569system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency 570system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency 571system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency 572system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency 573system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency 574system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency 575system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked 576system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked 577system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked 578system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 579system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked 580system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked 581system.cpu.icache.fast_writes 0 # number of fast writes performed 582system.cpu.icache.cache_copies 0 # number of cache copies performed 583system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79541 # number of ReadReq MSHR hits 584system.cpu.icache.ReadReq_mshr_hits::total 79541 # number of ReadReq MSHR hits 585system.cpu.icache.demand_mshr_hits::cpu.inst 79541 # number of demand (read+write) MSHR hits 586system.cpu.icache.demand_mshr_hits::total 79541 # number of demand (read+write) MSHR hits 587system.cpu.icache.overall_mshr_hits::cpu.inst 79541 # number of overall MSHR hits 588system.cpu.icache.overall_mshr_hits::total 79541 # number of overall MSHR hits 589system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980506 # number of ReadReq MSHR misses 590system.cpu.icache.ReadReq_mshr_misses::total 980506 # number of ReadReq MSHR misses 591system.cpu.icache.demand_mshr_misses::cpu.inst 980506 # number of demand (read+write) MSHR misses 592system.cpu.icache.demand_mshr_misses::total 980506 # number of demand (read+write) MSHR misses 593system.cpu.icache.overall_mshr_misses::cpu.inst 980506 # number of overall MSHR misses 594system.cpu.icache.overall_mshr_misses::total 980506 # number of overall MSHR misses 595system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11382269996 # number of ReadReq MSHR miss cycles 596system.cpu.icache.ReadReq_mshr_miss_latency::total 11382269996 # number of ReadReq MSHR miss cycles 597system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11382269996 # number of demand (read+write) MSHR miss cycles 598system.cpu.icache.demand_mshr_miss_latency::total 11382269996 # number of demand (read+write) MSHR miss cycles 599system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11382269996 # number of overall MSHR miss cycles 600system.cpu.icache.overall_mshr_miss_latency::total 11382269996 # number of overall MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles 602system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles 603system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles 604system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles 605system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for ReadReq accesses 606system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079537 # mshr miss rate for ReadReq accesses 607system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for demand accesses 608system.cpu.icache.demand_mshr_miss_rate::total 0.079537 # mshr miss rate for demand accesses 609system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for overall accesses 610system.cpu.icache.overall_mshr_miss_rate::total 0.079537 # mshr miss rate for overall accesses 611system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.567409 # average ReadReq mshr miss latency 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.567409 # average ReadReq mshr miss latency 613system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency 615system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency 617system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 618system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 619system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 620system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 621system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 622system.cpu.l2cache.replacements 64333 # number of replacements 623system.cpu.l2cache.tagsinuse 51339.387704 # Cycle average of tags in use 624system.cpu.l2cache.total_refs 1885585 # Total number of references to valid blocks. 625system.cpu.l2cache.sampled_refs 129729 # Sample count of references to valid blocks. 626system.cpu.l2cache.avg_refs 14.534799 # Average number of references to valid blocks. 627system.cpu.l2cache.warmup_cycle 2523139741500 # Cycle when the warmup percentage was hit. 628system.cpu.l2cache.occ_blocks::writebacks 36938.518996 # Average occupied blocks per requestor 629system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.781617 # Average occupied blocks per requestor 630system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor 631system.cpu.l2cache.occ_blocks::cpu.inst 8154.357820 # Average occupied blocks per requestor 632system.cpu.l2cache.occ_blocks::cpu.data 6219.728923 # Average occupied blocks per requestor 633system.cpu.l2cache.occ_percent::writebacks 0.563637 # Average percentage of cache occupancy 634system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000409 # Average percentage of cache occupancy 635system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 636system.cpu.l2cache.occ_percent::cpu.inst 0.124426 # Average percentage of cache occupancy 637system.cpu.l2cache.occ_percent::cpu.data 0.094906 # Average percentage of cache occupancy 638system.cpu.l2cache.occ_percent::total 0.783377 # Average percentage of cache occupancy 639system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52369 # number of ReadReq hits 640system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10535 # number of ReadReq hits 641system.cpu.l2cache.ReadReq_hits::cpu.inst 967038 # number of ReadReq hits 642system.cpu.l2cache.ReadReq_hits::cpu.data 387148 # number of ReadReq hits 643system.cpu.l2cache.ReadReq_hits::total 1417090 # number of ReadReq hits 644system.cpu.l2cache.Writeback_hits::writebacks 607758 # number of Writeback hits 645system.cpu.l2cache.Writeback_hits::total 607758 # number of Writeback hits 646system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits 647system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits 648system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits 649system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits 650system.cpu.l2cache.ReadExReq_hits::cpu.data 112914 # number of ReadExReq hits 651system.cpu.l2cache.ReadExReq_hits::total 112914 # number of ReadExReq hits 652system.cpu.l2cache.demand_hits::cpu.dtb.walker 52369 # number of demand (read+write) hits 653system.cpu.l2cache.demand_hits::cpu.itb.walker 10535 # number of demand (read+write) hits 654system.cpu.l2cache.demand_hits::cpu.inst 967038 # number of demand (read+write) hits 655system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits 656system.cpu.l2cache.demand_hits::total 1530004 # number of demand (read+write) hits 657system.cpu.l2cache.overall_hits::cpu.dtb.walker 52369 # number of overall hits 658system.cpu.l2cache.overall_hits::cpu.itb.walker 10535 # number of overall hits 659system.cpu.l2cache.overall_hits::cpu.inst 967038 # number of overall hits 660system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits 661system.cpu.l2cache.overall_hits::total 1530004 # number of overall hits 662system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses 663system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 664system.cpu.l2cache.ReadReq_misses::cpu.inst 12333 # number of ReadReq misses 665system.cpu.l2cache.ReadReq_misses::cpu.data 10696 # number of ReadReq misses 666system.cpu.l2cache.ReadReq_misses::total 23072 # number of ReadReq misses 667system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses 668system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses 669system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 670system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 671system.cpu.l2cache.ReadExReq_misses::cpu.data 133204 # number of ReadExReq misses 672system.cpu.l2cache.ReadExReq_misses::total 133204 # number of ReadExReq misses 673system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses 674system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 675system.cpu.l2cache.demand_misses::cpu.inst 12333 # number of demand (read+write) misses 676system.cpu.l2cache.demand_misses::cpu.data 143900 # number of demand (read+write) misses 677system.cpu.l2cache.demand_misses::total 156276 # number of demand (read+write) misses 678system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses 679system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 680system.cpu.l2cache.overall_misses::cpu.inst 12333 # number of overall misses 681system.cpu.l2cache.overall_misses::cpu.data 143900 # number of overall misses 682system.cpu.l2cache.overall_misses::total 156276 # number of overall misses 683system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2953500 # number of ReadReq miss cycles 684system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles 685system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695709500 # number of ReadReq miss cycles 686system.cpu.l2cache.ReadReq_miss_latency::cpu.data 628176999 # number of ReadReq miss cycles 687system.cpu.l2cache.ReadReq_miss_latency::total 1326957999 # number of ReadReq miss cycles 688system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478500 # number of UpgradeReq miss cycles 689system.cpu.l2cache.UpgradeReq_miss_latency::total 478500 # number of UpgradeReq miss cycles 690system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6755691500 # number of ReadExReq miss cycles 691system.cpu.l2cache.ReadExReq_miss_latency::total 6755691500 # number of ReadExReq miss cycles 692system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2953500 # number of demand (read+write) miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::cpu.inst 695709500 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::cpu.data 7383868499 # number of demand (read+write) miss cycles 696system.cpu.l2cache.demand_miss_latency::total 8082649499 # number of demand (read+write) miss cycles 697system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2953500 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles 699system.cpu.l2cache.overall_miss_latency::cpu.inst 695709500 # number of overall miss cycles 700system.cpu.l2cache.overall_miss_latency::cpu.data 7383868499 # number of overall miss cycles 701system.cpu.l2cache.overall_miss_latency::total 8082649499 # number of overall miss cycles 702system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52410 # number of ReadReq accesses(hits+misses) 703system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10537 # number of ReadReq accesses(hits+misses) 704system.cpu.l2cache.ReadReq_accesses::cpu.inst 979371 # number of ReadReq accesses(hits+misses) 705system.cpu.l2cache.ReadReq_accesses::cpu.data 397844 # number of ReadReq accesses(hits+misses) 706system.cpu.l2cache.ReadReq_accesses::total 1440162 # number of ReadReq accesses(hits+misses) 707system.cpu.l2cache.Writeback_accesses::writebacks 607758 # number of Writeback accesses(hits+misses) 708system.cpu.l2cache.Writeback_accesses::total 607758 # number of Writeback accesses(hits+misses) 709system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) 710system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) 711system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) 712system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::cpu.data 246118 # number of ReadExReq accesses(hits+misses) 714system.cpu.l2cache.ReadExReq_accesses::total 246118 # number of ReadExReq accesses(hits+misses) 715system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52410 # number of demand (read+write) accesses 716system.cpu.l2cache.demand_accesses::cpu.itb.walker 10537 # number of demand (read+write) accesses 717system.cpu.l2cache.demand_accesses::cpu.inst 979371 # number of demand (read+write) accesses 718system.cpu.l2cache.demand_accesses::cpu.data 643962 # number of demand (read+write) accesses 719system.cpu.l2cache.demand_accesses::total 1686280 # number of demand (read+write) accesses 720system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52410 # number of overall (read+write) accesses 721system.cpu.l2cache.overall_accesses::cpu.itb.walker 10537 # number of overall (read+write) accesses 722system.cpu.l2cache.overall_accesses::cpu.inst 979371 # number of overall (read+write) accesses 723system.cpu.l2cache.overall_accesses::cpu.data 643962 # number of overall (read+write) accesses 724system.cpu.l2cache.overall_accesses::total 1686280 # number of overall (read+write) accesses 725system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000782 # miss rate for ReadReq accesses 726system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses 727system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012593 # miss rate for ReadReq accesses 728system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026885 # miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_miss_rate::total 0.016020 # miss rate for ReadReq accesses 730system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986500 # miss rate for UpgradeReq accesses 731system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986500 # miss rate for UpgradeReq accesses 732system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses 733system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses 734system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541220 # miss rate for ReadExReq accesses 735system.cpu.l2cache.ReadExReq_miss_rate::total 0.541220 # miss rate for ReadExReq accesses 736system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000782 # miss rate for demand accesses 737system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses 738system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012593 # miss rate for demand accesses 739system.cpu.l2cache.demand_miss_rate::cpu.data 0.223460 # miss rate for demand accesses 740system.cpu.l2cache.demand_miss_rate::total 0.092675 # miss rate for demand accesses 741system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000782 # miss rate for overall accesses 742system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses 743system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012593 # miss rate for overall accesses 744system.cpu.l2cache.overall_miss_rate::cpu.data 0.223460 # miss rate for overall accesses 745system.cpu.l2cache.overall_miss_rate::total 0.092675 # miss rate for overall accesses 746system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72036.585366 # average ReadReq miss latency 747system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency 748system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56410.402984 # average ReadReq miss latency 749system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58730.085920 # average ReadReq miss latency 750system.cpu.l2cache.ReadReq_avg_miss_latency::total 57513.782897 # average ReadReq miss latency 751system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.701676 # average UpgradeReq miss latency 752system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.701676 # average UpgradeReq miss latency 753system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50716.881625 # average ReadExReq miss latency 754system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50716.881625 # average ReadExReq miss latency 755system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72036.585366 # average overall miss latency 756system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency 757system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56410.402984 # average overall miss latency 758system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51312.498256 # average overall miss latency 759system.cpu.l2cache.demand_avg_miss_latency::total 51720.350527 # average overall miss latency 760system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72036.585366 # average overall miss latency 761system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency 762system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56410.402984 # average overall miss latency 763system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51312.498256 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::total 51720.350527 # average overall miss latency 765system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 766system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 767system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 768system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 769system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 770system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 771system.cpu.l2cache.fast_writes 0 # number of fast writes performed 772system.cpu.l2cache.cache_copies 0 # number of cache copies performed 773system.cpu.l2cache.writebacks::writebacks 59090 # number of writebacks 774system.cpu.l2cache.writebacks::total 59090 # number of writebacks 775system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 776system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits 777system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 778system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 779system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits 780system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 781system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # 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number of overall MSHR misses 805system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2441041 # number of ReadReq MSHR miss cycles 806system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles 807system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541729027 # number of ReadReq MSHR miss cycles 808system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 493322234 # number of ReadReq MSHR miss cycles 809system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1037585553 # number of ReadReq MSHR miss cycles 810system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles 811system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles 812system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 813system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 814system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5095490217 # number of ReadExReq MSHR miss cycles 815system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5095490217 # number of ReadExReq MSHR miss cycles 816system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2441041 # number of demand (read+write) MSHR miss cycles 817system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles 818system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541729027 # number of demand (read+write) MSHR miss cycles 819system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5588812451 # number of demand (read+write) MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::total 6133075770 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2441041 # number of overall MSHR miss cycles 822system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles 823system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541729027 # number of overall MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5588812451 # number of overall MSHR miss cycles 825system.cpu.l2cache.overall_mshr_miss_latency::total 6133075770 # number of overall MSHR miss cycles 826system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles 827system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002521767 # number of ReadReq MSHR uncacheable cycles 828system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007602597 # number of ReadReq MSHR uncacheable cycles 829system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911564456 # number of WriteReq MSHR uncacheable cycles 830system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26911564456 # number of WriteReq MSHR uncacheable cycles 831system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles 832system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914086223 # number of overall MSHR uncacheable cycles 833system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919167053 # number of overall MSHR uncacheable cycles 834system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for ReadReq accesses 835system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses 836system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for ReadReq accesses 837system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026734 # mshr miss rate for ReadReq accesses 838system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015970 # mshr miss rate for ReadReq accesses 839system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986500 # mshr miss rate for UpgradeReq accesses 840system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986500 # mshr miss rate for UpgradeReq accesses 841system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses 842system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses 843system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541220 # mshr miss rate for ReadExReq accesses 844system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541220 # mshr miss rate for ReadExReq accesses 845system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for demand accesses 846system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses 847system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for demand accesses 848system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for demand accesses 849system.cpu.l2cache.demand_mshr_miss_rate::total 0.092632 # mshr miss rate for demand accesses 850system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for overall accesses 851system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses 852system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for overall accesses 853system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for overall accesses 854system.cpu.l2cache.overall_mshr_miss_rate::total 0.092632 # mshr miss rate for overall accesses 855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average ReadReq mshr miss latency 856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43967.943105 # average ReadReq mshr miss latency 858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46382.308575 # average ReadReq mshr miss latency 859system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45112.415348 # average ReadReq mshr miss latency 860system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 861system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 862system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 863system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 864system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38253.282311 # average ReadExReq mshr miss latency 865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38253.282311 # average ReadExReq mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency 868system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency 869system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency 870system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency 871system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency 872system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency 873system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency 874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency 875system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency 876system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 877system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 878system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 879system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 880system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 881system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 882system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 883system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 884system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 885system.cpu.dcache.replacements 643450 # number of replacements 886system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use 887system.cpu.dcache.total_refs 21511687 # Total number of references to valid blocks. 888system.cpu.dcache.sampled_refs 643962 # Sample count of references to valid blocks. 889system.cpu.dcache.avg_refs 33.405212 # Average number of references to valid blocks. 890system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. 891system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor 892system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 893system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy 894system.cpu.dcache.ReadReq_hits::cpu.data 13758946 # number of ReadReq hits 895system.cpu.dcache.ReadReq_hits::total 13758946 # number of ReadReq hits 896system.cpu.dcache.WriteReq_hits::cpu.data 7259114 # number of WriteReq hits 897system.cpu.dcache.WriteReq_hits::total 7259114 # number of WriteReq hits 898system.cpu.dcache.LoadLockedReq_hits::cpu.data 242919 # number of LoadLockedReq hits 899system.cpu.dcache.LoadLockedReq_hits::total 242919 # number of LoadLockedReq hits 900system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits 901system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits 902system.cpu.dcache.demand_hits::cpu.data 21018060 # number of demand (read+write) hits 903system.cpu.dcache.demand_hits::total 21018060 # number of demand (read+write) hits 904system.cpu.dcache.overall_hits::cpu.data 21018060 # number of overall hits 905system.cpu.dcache.overall_hits::total 21018060 # number of overall hits 906system.cpu.dcache.ReadReq_misses::cpu.data 736156 # number of ReadReq misses 907system.cpu.dcache.ReadReq_misses::total 736156 # number of ReadReq misses 908system.cpu.dcache.WriteReq_misses::cpu.data 2963249 # number of WriteReq misses 909system.cpu.dcache.WriteReq_misses::total 2963249 # number of WriteReq misses 910system.cpu.dcache.LoadLockedReq_misses::cpu.data 13539 # number of LoadLockedReq misses 911system.cpu.dcache.LoadLockedReq_misses::total 13539 # number of LoadLockedReq misses 912system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses 913system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses 914system.cpu.dcache.demand_misses::cpu.data 3699405 # number of demand (read+write) misses 915system.cpu.dcache.demand_misses::total 3699405 # number of demand (read+write) misses 916system.cpu.dcache.overall_misses::cpu.data 3699405 # number of overall misses 917system.cpu.dcache.overall_misses::total 3699405 # number of overall misses 918system.cpu.dcache.ReadReq_miss_latency::cpu.data 9739284500 # number of ReadReq miss cycles 919system.cpu.dcache.ReadReq_miss_latency::total 9739284500 # number of ReadReq miss cycles 920system.cpu.dcache.WriteReq_miss_latency::cpu.data 104713593229 # number of WriteReq miss cycles 921system.cpu.dcache.WriteReq_miss_latency::total 104713593229 # number of WriteReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181601500 # number of LoadLockedReq miss cycles 923system.cpu.dcache.LoadLockedReq_miss_latency::total 181601500 # number of LoadLockedReq miss cycles 924system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles 925system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles 926system.cpu.dcache.demand_miss_latency::cpu.data 114452877729 # number of demand (read+write) miss cycles 927system.cpu.dcache.demand_miss_latency::total 114452877729 # number of demand (read+write) miss cycles 928system.cpu.dcache.overall_miss_latency::cpu.data 114452877729 # number of overall miss cycles 929system.cpu.dcache.overall_miss_latency::total 114452877729 # number of overall miss cycles 930system.cpu.dcache.ReadReq_accesses::cpu.data 14495102 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.ReadReq_accesses::total 14495102 # number of ReadReq accesses(hits+misses) 932system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) 934system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) 935system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) 936system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) 937system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) 938system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses 939system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses 940system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses 941system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses 942system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses 943system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses 944system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses 945system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses 946system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses 947system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses 948system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses 949system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses 950system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses 951system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses 952system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses 953system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses 954system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency 955system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency 956system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency 957system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency 958system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency 959system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency 960system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency 961system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency 962system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency 963system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency 964system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency 965system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency 966system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked 967system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked 968system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked 969system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked 970system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked 971system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked 972system.cpu.dcache.fast_writes 0 # number of fast writes performed 973system.cpu.dcache.cache_copies 0 # number of cache copies performed 974system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks 975system.cpu.dcache.writebacks::total 607758 # number of writebacks 976system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits 977system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits 978system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits 979system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits 980system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits 981system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits 982system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits 983system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits 984system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits 985system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits 986system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses 987system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses 988system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses 989system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses 990system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses 991system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses 992system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses 993system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses 994system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses 995system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses 996system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses 997system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses 998system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles 1002system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles 1003system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles 1004system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles 1005system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles 1006system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles 1007system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles 1008system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles 1009system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles 1010system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles 1011system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles 1012system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles 1013system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles 1014system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles 1015system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles 1016system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses 1017system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses 1018system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses 1019system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses 1020system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses 1021system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses 1022system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses 1023system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses 1024system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses 1025system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses 1026system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses 1027system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses 1028system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency 1029system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency 1030system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency 1031system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency 1032system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency 1033system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency 1034system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency 1035system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency 1036system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency 1037system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency 1038system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency 1039system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency 1040system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1041system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1042system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1043system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1044system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1045system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1046system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1047system.iocache.replacements 0 # number of replacements 1048system.iocache.tagsinuse 0 # Cycle average of tags in use 1049system.iocache.total_refs 0 # Total number of references to valid blocks. 1050system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1051system.iocache.avg_refs nan # Average number of references to valid blocks. 1052system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1053system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1054system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1055system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1056system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1057system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1058system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1059system.iocache.fast_writes 0 # number of fast writes performed 1060system.iocache.cache_copies 0 # number of cache copies performed 1061system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles 1062system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles 1063system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles 1064system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles 1065system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1066system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1067system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1068system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1069system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1070system.cpu.kern.inst.arm 0 # number of arm instructions executed 1071system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed 1072 1073---------- End Simulation Statistics ---------- 1074