stats.txt revision 8911:4da2ea94319f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.501676 # Number of seconds simulated 4sim_ticks 2501676293500 # Number of ticks simulated 5final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93944 # Simulator instruction rate (inst/s) 8host_op_rate 121345 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3953091411 # Simulator tick rate (ticks/s) 10host_mem_usage 381372 # Number of bytes of host memory used 11host_seconds 632.84 # Real time elapsed on the host 12sim_insts 59451291 # Number of instructions simulated 13sim_ops 76792341 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory 15system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory 16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory 18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) 22system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) 23system.physmem.bytes_read 129652968 # Number of bytes read from this memory 24system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory 25system.physmem.bytes_written 9585096 # Number of bytes written to this memory 26system.physmem.num_reads 14979455 # Number of read requests responded to by this memory 27system.physmem.num_writes 856659 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s) 33system.l2c.replacements 119784 # number of replacements 34system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use 35system.l2c.total_refs 1826145 # Total number of references to valid blocks. 36system.l2c.sampled_refs 150763 # Sample count of references to valid blocks. 37system.l2c.avg_refs 12.112687 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 14272.421964 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor 41system.l2c.occ_blocks::cpu.itb.walker 0.932012 # Average occupied blocks per requestor 42system.l2c.occ_blocks::cpu.inst 6169.201034 # Average occupied blocks per requestor 43system.l2c.occ_blocks::cpu.data 5491.716201 # Average occupied blocks per requestor 44system.l2c.occ_percent::writebacks 0.217780 # Average percentage of cache occupancy 45system.l2c.occ_percent::cpu.dtb.walker 0.000997 # Average percentage of cache occupancy 46system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy 47system.l2c.occ_percent::cpu.inst 0.094135 # Average percentage of cache occupancy 48system.l2c.occ_percent::cpu.data 0.083797 # Average percentage of cache occupancy 49system.l2c.occ_percent::total 0.396723 # Average percentage of cache occupancy 50system.l2c.ReadReq_hits::cpu.dtb.walker 141919 # number of ReadReq hits 51system.l2c.ReadReq_hits::cpu.itb.walker 12116 # number of ReadReq hits 52system.l2c.ReadReq_hits::cpu.inst 995766 # number of ReadReq hits 53system.l2c.ReadReq_hits::cpu.data 377927 # number of ReadReq hits 54system.l2c.ReadReq_hits::total 1527728 # number of ReadReq hits 55system.l2c.Writeback_hits::writebacks 634955 # number of Writeback hits 56system.l2c.Writeback_hits::total 634955 # number of Writeback hits 57system.l2c.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits 58system.l2c.UpgradeReq_hits::total 46 # number of UpgradeReq hits 59system.l2c.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits 60system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits 61system.l2c.ReadExReq_hits::cpu.data 105770 # number of ReadExReq hits 62system.l2c.ReadExReq_hits::total 105770 # number of ReadExReq hits 63system.l2c.demand_hits::cpu.dtb.walker 141919 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.itb.walker 12116 # number of demand (read+write) hits 65system.l2c.demand_hits::cpu.inst 995766 # number of demand (read+write) hits 66system.l2c.demand_hits::cpu.data 483697 # number of demand (read+write) hits 67system.l2c.demand_hits::total 1633498 # number of demand (read+write) hits 68system.l2c.overall_hits::cpu.dtb.walker 141919 # number of overall hits 69system.l2c.overall_hits::cpu.itb.walker 12116 # number of overall hits 70system.l2c.overall_hits::cpu.inst 995766 # number of overall hits 71system.l2c.overall_hits::cpu.data 483697 # number of overall hits 72system.l2c.overall_hits::total 1633498 # number of overall hits 73system.l2c.ReadReq_misses::cpu.dtb.walker 157 # number of ReadReq misses 74system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses 75system.l2c.ReadReq_misses::cpu.inst 17392 # number of ReadReq misses 76system.l2c.ReadReq_misses::cpu.data 19166 # number of ReadReq misses 77system.l2c.ReadReq_misses::total 36728 # number of ReadReq misses 78system.l2c.UpgradeReq_misses::cpu.data 3302 # number of UpgradeReq misses 79system.l2c.UpgradeReq_misses::total 3302 # number of UpgradeReq misses 80system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 81system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 82system.l2c.ReadExReq_misses::cpu.data 140335 # number of ReadExReq misses 83system.l2c.ReadExReq_misses::total 140335 # number of ReadExReq misses 84system.l2c.demand_misses::cpu.dtb.walker 157 # number of demand (read+write) misses 85system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses 86system.l2c.demand_misses::cpu.inst 17392 # number of demand (read+write) misses 87system.l2c.demand_misses::cpu.data 159501 # number of demand (read+write) misses 88system.l2c.demand_misses::total 177063 # number of demand (read+write) misses 89system.l2c.overall_misses::cpu.dtb.walker 157 # number of overall misses 90system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses 91system.l2c.overall_misses::cpu.inst 17392 # number of overall misses 92system.l2c.overall_misses::cpu.data 159501 # number of overall misses 93system.l2c.overall_misses::total 177063 # number of overall misses 94system.l2c.ReadReq_miss_latency::cpu.dtb.walker 8196500 # number of ReadReq miss cycles 95system.l2c.ReadReq_miss_latency::cpu.itb.walker 677000 # number of ReadReq miss cycles 96system.l2c.ReadReq_miss_latency::cpu.inst 910933000 # number of ReadReq miss cycles 97system.l2c.ReadReq_miss_latency::cpu.data 1001503500 # number of ReadReq miss cycles 98system.l2c.ReadReq_miss_latency::total 1921310000 # number of ReadReq miss cycles 99system.l2c.UpgradeReq_miss_latency::cpu.data 1203000 # number of UpgradeReq miss cycles 100system.l2c.UpgradeReq_miss_latency::total 1203000 # number of UpgradeReq miss cycles 101system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles 102system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles 103system.l2c.ReadExReq_miss_latency::cpu.data 7367598500 # number of ReadExReq miss cycles 104system.l2c.ReadExReq_miss_latency::total 7367598500 # number of ReadExReq miss cycles 105system.l2c.demand_miss_latency::cpu.dtb.walker 8196500 # number of demand (read+write) miss cycles 106system.l2c.demand_miss_latency::cpu.itb.walker 677000 # number of demand (read+write) miss cycles 107system.l2c.demand_miss_latency::cpu.inst 910933000 # number of demand (read+write) miss cycles 108system.l2c.demand_miss_latency::cpu.data 8369102000 # number of demand (read+write) miss cycles 109system.l2c.demand_miss_latency::total 9288908500 # number of demand (read+write) miss cycles 110system.l2c.overall_miss_latency::cpu.dtb.walker 8196500 # number of overall miss cycles 111system.l2c.overall_miss_latency::cpu.itb.walker 677000 # number of overall miss cycles 112system.l2c.overall_miss_latency::cpu.inst 910933000 # number of overall miss cycles 113system.l2c.overall_miss_latency::cpu.data 8369102000 # number of overall miss cycles 114system.l2c.overall_miss_latency::total 9288908500 # number of overall miss cycles 115system.l2c.ReadReq_accesses::cpu.dtb.walker 142076 # number of ReadReq accesses(hits+misses) 116system.l2c.ReadReq_accesses::cpu.itb.walker 12129 # number of ReadReq accesses(hits+misses) 117system.l2c.ReadReq_accesses::cpu.inst 1013158 # number of ReadReq accesses(hits+misses) 118system.l2c.ReadReq_accesses::cpu.data 397093 # number of ReadReq accesses(hits+misses) 119system.l2c.ReadReq_accesses::total 1564456 # number of ReadReq accesses(hits+misses) 120system.l2c.Writeback_accesses::writebacks 634955 # number of Writeback accesses(hits+misses) 121system.l2c.Writeback_accesses::total 634955 # number of Writeback accesses(hits+misses) 122system.l2c.UpgradeReq_accesses::cpu.data 3348 # number of UpgradeReq accesses(hits+misses) 123system.l2c.UpgradeReq_accesses::total 3348 # number of UpgradeReq accesses(hits+misses) 124system.l2c.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses) 125system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) 126system.l2c.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses) 127system.l2c.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses) 128system.l2c.demand_accesses::cpu.dtb.walker 142076 # number of demand (read+write) accesses 129system.l2c.demand_accesses::cpu.itb.walker 12129 # number of demand (read+write) accesses 130system.l2c.demand_accesses::cpu.inst 1013158 # number of demand (read+write) accesses 131system.l2c.demand_accesses::cpu.data 643198 # number of demand (read+write) accesses 132system.l2c.demand_accesses::total 1810561 # number of demand (read+write) accesses 133system.l2c.overall_accesses::cpu.dtb.walker 142076 # number of overall (read+write) accesses 134system.l2c.overall_accesses::cpu.itb.walker 12129 # number of overall (read+write) accesses 135system.l2c.overall_accesses::cpu.inst 1013158 # number of overall (read+write) accesses 136system.l2c.overall_accesses::cpu.data 643198 # number of overall (read+write) accesses 137system.l2c.overall_accesses::total 1810561 # number of overall (read+write) accesses 138system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001105 # miss rate for ReadReq accesses 139system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001072 # miss rate for ReadReq accesses 140system.l2c.ReadReq_miss_rate::cpu.inst 0.017166 # miss rate for ReadReq accesses 141system.l2c.ReadReq_miss_rate::cpu.data 0.048266 # miss rate for ReadReq accesses 142system.l2c.UpgradeReq_miss_rate::cpu.data 0.986260 # miss rate for UpgradeReq accesses 143system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses 144system.l2c.ReadExReq_miss_rate::cpu.data 0.570224 # miss rate for ReadExReq accesses 145system.l2c.demand_miss_rate::cpu.dtb.walker 0.001105 # miss rate for demand accesses 146system.l2c.demand_miss_rate::cpu.itb.walker 0.001072 # miss rate for demand accesses 147system.l2c.demand_miss_rate::cpu.inst 0.017166 # miss rate for demand accesses 148system.l2c.demand_miss_rate::cpu.data 0.247981 # miss rate for demand accesses 149system.l2c.overall_miss_rate::cpu.dtb.walker 0.001105 # miss rate for overall accesses 150system.l2c.overall_miss_rate::cpu.itb.walker 0.001072 # miss rate for overall accesses 151system.l2c.overall_miss_rate::cpu.inst 0.017166 # miss rate for overall accesses 152system.l2c.overall_miss_rate::cpu.data 0.247981 # miss rate for overall accesses 153system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52207.006369 # average ReadReq miss latency 154system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077 # average ReadReq miss latency 155system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438 # average ReadReq miss latency 156system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058 # average ReadReq miss latency 157system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.324652 # average UpgradeReq miss latency 158system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency 159system.l2c.ReadExReq_avg_miss_latency::cpu.data 52500.078384 # average ReadExReq miss latency 160system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency 161system.l2c.demand_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency 162system.l2c.demand_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency 163system.l2c.demand_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency 164system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency 165system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency 166system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency 167system.l2c.overall_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked 172system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed 176system.l2c.writebacks::writebacks 102641 # number of writebacks 177system.l2c.writebacks::total 102641 # number of writebacks 178system.l2c.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 179system.l2c.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits 180system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 181system.l2c.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits 182system.l2c.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits 183system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 184system.l2c.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits 185system.l2c.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits 186system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits 187system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 157 # number of ReadReq MSHR misses 188system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses 189system.l2c.ReadReq_mshr_misses::cpu.inst 17382 # number of ReadReq MSHR misses 190system.l2c.ReadReq_mshr_misses::cpu.data 19085 # number of ReadReq MSHR misses 191system.l2c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses 192system.l2c.UpgradeReq_mshr_misses::cpu.data 3302 # number of UpgradeReq MSHR misses 193system.l2c.UpgradeReq_mshr_misses::total 3302 # number of UpgradeReq MSHR misses 194system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 195system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 196system.l2c.ReadExReq_mshr_misses::cpu.data 140335 # number of ReadExReq MSHR misses 197system.l2c.ReadExReq_mshr_misses::total 140335 # number of ReadExReq MSHR misses 198system.l2c.demand_mshr_misses::cpu.dtb.walker 157 # number of demand (read+write) MSHR misses 199system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses 200system.l2c.demand_mshr_misses::cpu.inst 17382 # number of demand (read+write) MSHR misses 201system.l2c.demand_mshr_misses::cpu.data 159420 # number of demand (read+write) MSHR misses 202system.l2c.demand_mshr_misses::total 176972 # number of demand (read+write) MSHR misses 203system.l2c.overall_mshr_misses::cpu.dtb.walker 157 # number of overall MSHR misses 204system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses 205system.l2c.overall_mshr_misses::cpu.inst 17382 # number of overall MSHR misses 206system.l2c.overall_mshr_misses::cpu.data 159420 # number of overall MSHR misses 207system.l2c.overall_mshr_misses::total 176972 # number of overall MSHR misses 208system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6288500 # number of ReadReq MSHR miss cycles 209system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 521000 # number of ReadReq MSHR miss cycles 210system.l2c.ReadReq_mshr_miss_latency::cpu.inst 698170500 # number of ReadReq MSHR miss cycles 211system.l2c.ReadReq_mshr_miss_latency::cpu.data 765243500 # number of ReadReq MSHR miss cycles 212system.l2c.ReadReq_mshr_miss_latency::total 1470223500 # number of ReadReq MSHR miss cycles 213system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132738500 # number of UpgradeReq MSHR miss cycles 214system.l2c.UpgradeReq_mshr_miss_latency::total 132738500 # number of UpgradeReq MSHR miss cycles 215system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 216system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 217system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5623589000 # number of ReadExReq MSHR miss cycles 218system.l2c.ReadExReq_mshr_miss_latency::total 5623589000 # number of ReadExReq MSHR miss cycles 219system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6288500 # number of demand (read+write) MSHR miss cycles 220system.l2c.demand_mshr_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) MSHR miss cycles 221system.l2c.demand_mshr_miss_latency::cpu.inst 698170500 # number of demand (read+write) MSHR miss cycles 222system.l2c.demand_mshr_miss_latency::cpu.data 6388832500 # number of demand (read+write) MSHR miss cycles 223system.l2c.demand_mshr_miss_latency::total 7093812500 # number of demand (read+write) MSHR miss cycles 224system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6288500 # number of overall MSHR miss cycles 225system.l2c.overall_mshr_miss_latency::cpu.itb.walker 521000 # number of overall MSHR miss cycles 226system.l2c.overall_mshr_miss_latency::cpu.inst 698170500 # number of overall MSHR miss cycles 227system.l2c.overall_mshr_miss_latency::cpu.data 6388832500 # number of overall MSHR miss cycles 228system.l2c.overall_mshr_miss_latency::total 7093812500 # number of overall MSHR miss cycles 229system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles 230system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765321500 # number of ReadReq MSHR uncacheable cycles 231system.l2c.ReadReq_mshr_uncacheable_latency::total 131770748500 # number of ReadReq MSHR uncacheable cycles 232system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346079731 # number of WriteReq MSHR uncacheable cycles 233system.l2c.WriteReq_mshr_uncacheable_latency::total 32346079731 # number of WriteReq MSHR uncacheable cycles 234system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles 235system.l2c.overall_mshr_uncacheable_latency::cpu.data 164111401231 # number of overall MSHR uncacheable cycles 236system.l2c.overall_mshr_uncacheable_latency::total 164116828231 # number of overall MSHR uncacheable cycles 237system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for ReadReq accesses 238system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for ReadReq accesses 239system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for ReadReq accesses 240system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048062 # mshr miss rate for ReadReq accesses 241system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986260 # mshr miss rate for UpgradeReq accesses 242system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses 243system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.570224 # mshr miss rate for ReadExReq accesses 244system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for demand accesses 245system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for demand accesses 246system.l2c.demand_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for demand accesses 247system.l2c.demand_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for demand accesses 248system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for overall accesses 249system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for overall accesses 250system.l2c.overall_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for overall accesses 251system.l2c.overall_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for overall accesses 252system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average ReadReq mshr miss latency 253system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average ReadReq mshr miss latency 254system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40166.292717 # average ReadReq mshr miss latency 255system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.594184 # average ReadReq mshr miss latency 256system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40199.424591 # average UpgradeReq mshr miss latency 257system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 258system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40072.604838 # average ReadExReq mshr miss latency 259system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency 260system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency 261system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency 262system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency 263system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency 264system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency 265system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency 266system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency 267system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 268system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 269system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 270system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 271system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 272system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 273system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 274system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 275system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 276system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 277system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 278system.cf0.dma_write_txs 0 # Number of DMA write transactions. 279system.cpu.dtb.inst_hits 0 # ITB inst hits 280system.cpu.dtb.inst_misses 0 # ITB inst misses 281system.cpu.dtb.read_hits 52069399 # DTB read hits 282system.cpu.dtb.read_misses 92258 # DTB read misses 283system.cpu.dtb.write_hits 11926847 # DTB write hits 284system.cpu.dtb.write_misses 25023 # DTB write misses 285system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 286system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 287system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 288system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 289system.cpu.dtb.flush_entries 4540 # Number of entries that have been flushed from TLB 290system.cpu.dtb.align_faults 5662 # Number of TLB faults due to alignment restrictions 291system.cpu.dtb.prefetch_faults 693 # Number of TLB faults due to prefetch 292system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 293system.cpu.dtb.perms_faults 2731 # Number of TLB faults due to permissions restrictions 294system.cpu.dtb.read_accesses 52161657 # DTB read accesses 295system.cpu.dtb.write_accesses 11951870 # DTB write accesses 296system.cpu.dtb.inst_accesses 0 # ITB inst accesses 297system.cpu.dtb.hits 63996246 # DTB hits 298system.cpu.dtb.misses 117281 # DTB misses 299system.cpu.dtb.accesses 64113527 # DTB accesses 300system.cpu.itb.inst_hits 13699541 # ITB inst hits 301system.cpu.itb.inst_misses 12131 # ITB inst misses 302system.cpu.itb.read_hits 0 # DTB read hits 303system.cpu.itb.read_misses 0 # DTB read misses 304system.cpu.itb.write_hits 0 # DTB write hits 305system.cpu.itb.write_misses 0 # DTB write misses 306system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 307system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 308system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 309system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 310system.cpu.itb.flush_entries 2626 # Number of entries that have been flushed from TLB 311system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 312system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 313system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.itb.perms_faults 6936 # Number of TLB faults due to permissions restrictions 315system.cpu.itb.read_accesses 0 # DTB read accesses 316system.cpu.itb.write_accesses 0 # DTB write accesses 317system.cpu.itb.inst_accesses 13711672 # ITB inst accesses 318system.cpu.itb.hits 13699541 # DTB hits 319system.cpu.itb.misses 12131 # DTB misses 320system.cpu.itb.accesses 13711672 # DTB accesses 321system.cpu.numCycles 411150559 # number of cpu cycles simulated 322system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 323system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 324system.cpu.BPredUnit.lookups 15631672 # Number of BP lookups 325system.cpu.BPredUnit.condPredicted 12342234 # Number of conditional branches predicted 326system.cpu.BPredUnit.condIncorrect 929456 # Number of conditional branches incorrect 327system.cpu.BPredUnit.BTBLookups 10552810 # Number of BTB lookups 328system.cpu.BPredUnit.BTBHits 8288947 # Number of BTB hits 329system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 330system.cpu.BPredUnit.usedRAS 1323523 # Number of times the RAS was used to get a target. 331system.cpu.BPredUnit.RASInCorrect 194787 # Number of incorrect RAS predictions. 332system.cpu.fetch.icacheStallCycles 32982972 # Number of cycles fetch is stalled on an Icache miss 333system.cpu.fetch.Insts 102837345 # Number of instructions fetch has processed 334system.cpu.fetch.Branches 15631672 # Number of branches that fetch encountered 335system.cpu.fetch.predictedBranches 9612470 # Number of branches that fetch has predicted taken 336system.cpu.fetch.Cycles 22590084 # Number of cycles fetch has run and was not squashing or blocked 337system.cpu.fetch.SquashCycles 6692504 # Number of cycles fetch has spent squashing 338system.cpu.fetch.TlbCycles 158663 # Number of cycles fetch has spent waiting for tlb 339system.cpu.fetch.BlockedCycles 89850563 # Number of cycles fetch has spent blocked 340system.cpu.fetch.MiscStallCycles 2746 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 341system.cpu.fetch.PendingTrapStallCycles 143204 # Number of stall cycles due to pending traps 342system.cpu.fetch.PendingQuiesceStallCycles 218934 # Number of stall cycles due to pending quiesce instructions 343system.cpu.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR 344system.cpu.fetch.CacheLines 13691858 # Number of cache lines fetched 345system.cpu.fetch.IcacheSquashes 996334 # Number of outstanding Icache misses that were squashed 346system.cpu.fetch.ItlbSquashes 6838 # Number of outstanding ITLB misses that were squashed 347system.cpu.fetch.rateDist::samples 150553763 # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::mean 0.848436 # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::stdev 2.233477 # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::0 127980574 85.01% 85.01% # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::1 1480097 0.98% 85.99% # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::2 1855620 1.23% 87.22% # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::3 2694532 1.79% 89.01% # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::4 1893570 1.26% 90.27% # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.rateDist::5 1188011 0.79% 91.06% # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::6 2948135 1.96% 93.02% # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::7 848652 0.56% 93.58% # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::8 9664572 6.42% 100.00% # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::total 150553763 # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.branchRate 0.038019 # Number of branch fetches per cycle 365system.cpu.fetch.rate 0.250121 # Number of inst fetches per cycle 366system.cpu.decode.IdleCycles 35091688 # Number of cycles decode is idle 367system.cpu.decode.BlockedCycles 89690975 # Number of cycles decode is blocked 368system.cpu.decode.RunCycles 20321625 # Number of cycles decode is running 369system.cpu.decode.UnblockCycles 1025705 # Number of cycles decode is unblocking 370system.cpu.decode.SquashCycles 4423770 # Number of cycles decode is squashing 371system.cpu.decode.BranchResolved 2273029 # Number of times decode resolved a branch 372system.cpu.decode.BranchMispred 186320 # Number of times decode detected a branch misprediction 373system.cpu.decode.DecodedInsts 119828190 # Number of instructions handled by decode 374system.cpu.decode.SquashedInsts 605140 # Number of squashed instructions handled by decode 375system.cpu.rename.SquashCycles 4423770 # Number of cycles rename is squashing 376system.cpu.rename.IdleCycles 37165531 # Number of cycles rename is idle 377system.cpu.rename.BlockCycles 37166387 # Number of cycles rename is blocking 378system.cpu.rename.serializeStallCycles 46484492 # count of cycles rename stalled for serializing inst 379system.cpu.rename.RunCycles 19226681 # Number of cycles rename is running 380system.cpu.rename.UnblockCycles 6086902 # Number of cycles rename is unblocking 381system.cpu.rename.RenamedInsts 112339029 # Number of instructions processed by rename 382system.cpu.rename.ROBFullEvents 3754 # Number of times rename has blocked due to ROB full 383system.cpu.rename.IQFullEvents 1012932 # Number of times rename has blocked due to IQ full 384system.cpu.rename.LSQFullEvents 4107831 # Number of times rename has blocked due to LSQ full 385system.cpu.rename.FullRegisterEvents 44905 # Number of times there has been no free registers 386system.cpu.rename.RenamedOperands 116884712 # Number of destination operands rename has renamed 387system.cpu.rename.RenameLookups 516607430 # Number of register rename lookups that rename has made 388system.cpu.rename.int_rename_lookups 516512877 # Number of integer rename lookups 389system.cpu.rename.fp_rename_lookups 94553 # Number of floating rename lookups 390system.cpu.rename.CommittedMaps 77495227 # Number of HB maps that are committed 391system.cpu.rename.UndoneMaps 39389484 # Number of HB maps that are undone due to squashing 392system.cpu.rename.serializingInsts 939636 # count of serializing insts renamed 393system.cpu.rename.tempSerializingInsts 835400 # count of temporary serializing insts renamed 394system.cpu.rename.skidInsts 12435347 # count of insts added to the skid buffer 395system.cpu.memDep0.insertedLoads 21635443 # Number of loads inserted to the mem dependence unit. 396system.cpu.memDep0.insertedStores 14050113 # Number of stores inserted to the mem dependence unit. 397system.cpu.memDep0.conflictingLoads 1939177 # Number of conflicting loads. 398system.cpu.memDep0.conflictingStores 2494760 # Number of conflicting stores. 399system.cpu.iq.iqInstsAdded 102209700 # Number of instructions added to the IQ (excludes non-spec) 400system.cpu.iq.iqNonSpecInstsAdded 1618930 # Number of non-speculative instructions added to the IQ 401system.cpu.iq.iqInstsIssued 126189021 # Number of instructions issued 402system.cpu.iq.iqSquashedInstsIssued 231742 # Number of squashed instructions issued 403system.cpu.iq.iqSquashedInstsExamined 26205661 # Number of squashed instructions iterated over during squash; mainly for profiling 404system.cpu.iq.iqSquashedOperandsExamined 71388624 # Number of squashed operands that are examined and possibly removed from graph 405system.cpu.iq.iqSquashedNonSpecRemoved 331981 # Number of squashed non-spec instructions that were removed 406system.cpu.iq.issued_per_cycle::samples 150553763 # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::mean 0.838166 # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::stdev 1.542583 # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 410system.cpu.iq.issued_per_cycle::0 105343416 69.97% 69.97% # Number of insts issued each cycle 411system.cpu.iq.issued_per_cycle::1 14065037 9.34% 79.31% # Number of insts issued each cycle 412system.cpu.iq.issued_per_cycle::2 7354541 4.88% 84.20% # Number of insts issued each cycle 413system.cpu.iq.issued_per_cycle::3 5909522 3.93% 88.12% # Number of insts issued each cycle 414system.cpu.iq.issued_per_cycle::4 12758140 8.47% 96.60% # Number of insts issued each cycle 415system.cpu.iq.issued_per_cycle::5 2807768 1.86% 98.46% # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::6 1730475 1.15% 99.61% # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::7 446826 0.30% 99.91% # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::8 138038 0.09% 100.00% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::total 150553763 # Number of insts issued each cycle 423system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::IntAlu 60599 0.68% 0.68% # attempts to use FU when none available 425system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available 426system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available 427system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available 428system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available 429system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available 430system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available 431system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available 432system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available 453system.cpu.iq.fu_full::MemRead 8416262 94.64% 95.32% # attempts to use FU when none available 454system.cpu.iq.fu_full::MemWrite 416317 4.68% 100.00% # attempts to use FU when none available 455system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 456system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 457system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued 458system.cpu.iq.FU_type_0::IntAlu 59665616 47.28% 47.37% # Type of FU issued 459system.cpu.iq.FU_type_0::IntMult 95635 0.08% 47.44% # Type of FU issued 460system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.44% # Type of FU issued 461system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.44% # Type of FU issued 462system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.44% # Type of FU issued 463system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.44% # Type of FU issued 464system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.44% # Type of FU issued 465system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.44% # Type of FU issued 466system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.44% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.44% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.44% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.44% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.44% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.44% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdMisc 36 0.00% 47.44% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.44% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.44% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdShift 48 0.00% 47.44% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.44% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.44% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.44% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.44% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.44% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.44% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.44% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdFloatMisc 2270 0.00% 47.44% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.44% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.44% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.44% # Type of FU issued 487system.cpu.iq.FU_type_0::MemRead 53732100 42.58% 90.03% # Type of FU issued 488system.cpu.iq.FU_type_0::MemWrite 12586768 9.97% 100.00% # Type of FU issued 489system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 490system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 491system.cpu.iq.FU_type_0::total 126189021 # Type of FU issued 492system.cpu.iq.rate 0.306917 # Inst issue rate 493system.cpu.iq.fu_busy_cnt 8893180 # FU busy when requested 494system.cpu.iq.fu_busy_rate 0.070475 # FU busy rate (busy events/executed inst) 495system.cpu.iq.int_inst_queue_reads 412149363 # Number of integer instruction queue reads 496system.cpu.iq.int_inst_queue_writes 130053896 # Number of integer instruction queue writes 497system.cpu.iq.int_inst_queue_wakeup_accesses 86886822 # Number of integer instruction queue wakeup accesses 498system.cpu.iq.fp_inst_queue_reads 24048 # Number of floating instruction queue reads 499system.cpu.iq.fp_inst_queue_writes 13080 # Number of floating instruction queue writes 500system.cpu.iq.fp_inst_queue_wakeup_accesses 10409 # Number of floating instruction queue wakeup accesses 501system.cpu.iq.int_alu_accesses 134962848 # Number of integer alu accesses 502system.cpu.iq.fp_alu_accesses 12823 # Number of floating point alu accesses 503system.cpu.iew.lsq.thread0.forwLoads 636825 # Number of loads that had data forwarded from stores 504system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 505system.cpu.iew.lsq.thread0.squashedLoads 5953964 # Number of loads squashed 506system.cpu.iew.lsq.thread0.ignoredResponses 11249 # Number of memory responses ignored because the instruction is squashed 507system.cpu.iew.lsq.thread0.memOrderViolation 33793 # Number of memory ordering violations 508system.cpu.iew.lsq.thread0.squashedStores 2270680 # Number of stores squashed 509system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 510system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 511system.cpu.iew.lsq.thread0.rescheduledLoads 34115287 # Number of loads that were rescheduled 512system.cpu.iew.lsq.thread0.cacheBlocked 1151875 # Number of times an access to memory failed due to the cache being blocked 513system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 514system.cpu.iew.iewSquashCycles 4423770 # Number of cycles IEW is squashing 515system.cpu.iew.iewBlockCycles 28606306 # Number of cycles IEW is blocking 516system.cpu.iew.iewUnblockCycles 435959 # Number of cycles IEW is unblocking 517system.cpu.iew.iewDispatchedInsts 104089793 # Number of instructions dispatched to IQ 518system.cpu.iew.iewDispSquashedInsts 334839 # Number of squashed instructions skipped by dispatch 519system.cpu.iew.iewDispLoadInsts 21635443 # Number of dispatched load instructions 520system.cpu.iew.iewDispStoreInsts 14050113 # Number of dispatched store instructions 521system.cpu.iew.iewDispNonSpecInsts 991881 # Number of dispatched non-speculative instructions 522system.cpu.iew.iewIQFullEvents 95881 # Number of times the IQ has become full, causing a stall 523system.cpu.iew.iewLSQFullEvents 11592 # Number of times the LSQ has become full, causing a stall 524system.cpu.iew.memOrderViolationEvents 33793 # Number of memory order violations 525system.cpu.iew.predictedTakenIncorrect 550966 # Number of branches that were predicted taken incorrectly 526system.cpu.iew.predictedNotTakenIncorrect 345374 # Number of branches that were predicted not taken incorrectly 527system.cpu.iew.branchMispredicts 896340 # Number of branch mispredicts detected at execute 528system.cpu.iew.iewExecutedInsts 122956903 # Number of executed instructions 529system.cpu.iew.iewExecLoadInsts 52760819 # Number of load instructions executed 530system.cpu.iew.iewExecSquashedInsts 3232118 # Number of squashed instructions skipped in execute 531system.cpu.iew.exec_swp 0 # number of swp insts executed 532system.cpu.iew.exec_nop 261163 # number of nop insts executed 533system.cpu.iew.exec_refs 65197273 # number of memory reference insts executed 534system.cpu.iew.exec_branches 11589071 # Number of branches executed 535system.cpu.iew.exec_stores 12436454 # Number of stores executed 536system.cpu.iew.exec_rate 0.299056 # Inst execution rate 537system.cpu.iew.wb_sent 121403477 # cumulative count of insts sent to commit 538system.cpu.iew.wb_count 86897231 # cumulative count of insts written-back 539system.cpu.iew.wb_producers 47438485 # num instructions producing a value 540system.cpu.iew.wb_consumers 88321921 # num instructions consuming a value 541system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 542system.cpu.iew.wb_rate 0.211351 # insts written-back per cycle 543system.cpu.iew.wb_fanout 0.537109 # average fanout of values written-back 544system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 545system.cpu.commit.commitCommittedInsts 59601672 # The number of committed instructions 546system.cpu.commit.commitCommittedOps 76942722 # The number of committed instructions 547system.cpu.commit.commitSquashedInsts 26965943 # The number of squashed insts skipped by commit 548system.cpu.commit.commitNonSpecStalls 1286949 # The number of times commit has been forced to stall to communicate backwards 549system.cpu.commit.branchMispredicts 790517 # The number of times a branch was mispredicted 550system.cpu.commit.committed_per_cycle::samples 146212348 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::mean 0.526240 # Number of insts commited each cycle 552system.cpu.commit.committed_per_cycle::stdev 1.505087 # Number of insts commited each cycle 553system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 554system.cpu.commit.committed_per_cycle::0 118498573 81.05% 81.05% # Number of insts commited each cycle 555system.cpu.commit.committed_per_cycle::1 13699176 9.37% 90.41% # Number of insts commited each cycle 556system.cpu.commit.committed_per_cycle::2 3966547 2.71% 93.13% # Number of insts commited each cycle 557system.cpu.commit.committed_per_cycle::3 2244227 1.53% 94.66% # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::4 1750329 1.20% 95.86% # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::5 1033206 0.71% 96.57% # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::6 1542131 1.05% 97.62% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::7 667633 0.46% 98.08% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::8 2810526 1.92% 100.00% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::total 146212348 # Number of insts commited each cycle 567system.cpu.commit.committedInsts 59601672 # Number of instructions committed 568system.cpu.commit.committedOps 76942722 # Number of ops (including micro ops) committed 569system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 570system.cpu.commit.refs 27460912 # Number of memory references committed 571system.cpu.commit.loads 15681479 # Number of loads committed 572system.cpu.commit.membars 413077 # Number of memory barriers committed 573system.cpu.commit.branches 9891359 # Number of branches committed 574system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 575system.cpu.commit.int_insts 68495555 # Number of committed integer instructions. 576system.cpu.commit.function_calls 995632 # Number of function calls committed. 577system.cpu.commit.bw_lim_events 2810526 # number cycles where commit BW limit reached 578system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 579system.cpu.rob.rob_reads 245553933 # The number of ROB reads 580system.cpu.rob.rob_writes 212368242 # The number of ROB writes 581system.cpu.timesIdled 1894262 # Number of times that the entire CPU went into an idle state and unscheduled itself 582system.cpu.idleCycles 260596796 # Total number of cycles that the CPU has spent unscheduled due to idling 583system.cpu.quiesceCycles 4592114044 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 584system.cpu.committedInsts 59451291 # Number of Instructions Simulated 585system.cpu.committedOps 76792341 # Number of Ops (including micro ops) Simulated 586system.cpu.committedInsts_total 59451291 # Number of Instructions Simulated 587system.cpu.cpi 6.915755 # CPI: Cycles Per Instruction 588system.cpu.cpi_total 6.915755 # CPI: Total CPI of All Threads 589system.cpu.ipc 0.144597 # IPC: Instructions Per Cycle 590system.cpu.ipc_total 0.144597 # IPC: Total IPC of All Threads 591system.cpu.int_regfile_reads 557431988 # number of integer regfile reads 592system.cpu.int_regfile_writes 89182974 # number of integer regfile writes 593system.cpu.fp_regfile_reads 8912 # number of floating regfile reads 594system.cpu.fp_regfile_writes 2994 # number of floating regfile writes 595system.cpu.misc_regfile_reads 135303561 # number of misc regfile reads 596system.cpu.misc_regfile_writes 912352 # number of misc regfile writes 597system.cpu.icache.replacements 1013837 # number of replacements 598system.cpu.icache.tagsinuse 511.616166 # Cycle average of tags in use 599system.cpu.icache.total_refs 12585526 # Total number of references to valid blocks. 600system.cpu.icache.sampled_refs 1014349 # Sample count of references to valid blocks. 601system.cpu.icache.avg_refs 12.407491 # Average number of references to valid blocks. 602system.cpu.icache.warmup_cycle 6289783000 # Cycle when the warmup percentage was hit. 603system.cpu.icache.occ_blocks::cpu.inst 511.616166 # Average occupied blocks per requestor 604system.cpu.icache.occ_percent::cpu.inst 0.999250 # Average percentage of cache occupancy 605system.cpu.icache.occ_percent::total 0.999250 # Average percentage of cache occupancy 606system.cpu.icache.ReadReq_hits::cpu.inst 12585526 # number of ReadReq hits 607system.cpu.icache.ReadReq_hits::total 12585526 # number of ReadReq hits 608system.cpu.icache.demand_hits::cpu.inst 12585526 # number of demand (read+write) hits 609system.cpu.icache.demand_hits::total 12585526 # number of demand (read+write) hits 610system.cpu.icache.overall_hits::cpu.inst 12585526 # number of overall hits 611system.cpu.icache.overall_hits::total 12585526 # number of overall hits 612system.cpu.icache.ReadReq_misses::cpu.inst 1106194 # number of ReadReq misses 613system.cpu.icache.ReadReq_misses::total 1106194 # number of ReadReq misses 614system.cpu.icache.demand_misses::cpu.inst 1106194 # number of demand (read+write) misses 615system.cpu.icache.demand_misses::total 1106194 # number of demand (read+write) misses 616system.cpu.icache.overall_misses::cpu.inst 1106194 # number of overall misses 617system.cpu.icache.overall_misses::total 1106194 # number of overall misses 618system.cpu.icache.ReadReq_miss_latency::cpu.inst 16291440480 # number of ReadReq miss cycles 619system.cpu.icache.ReadReq_miss_latency::total 16291440480 # number of ReadReq miss cycles 620system.cpu.icache.demand_miss_latency::cpu.inst 16291440480 # number of demand (read+write) miss cycles 621system.cpu.icache.demand_miss_latency::total 16291440480 # number of demand (read+write) miss cycles 622system.cpu.icache.overall_miss_latency::cpu.inst 16291440480 # number of overall miss cycles 623system.cpu.icache.overall_miss_latency::total 16291440480 # number of overall miss cycles 624system.cpu.icache.ReadReq_accesses::cpu.inst 13691720 # number of ReadReq accesses(hits+misses) 625system.cpu.icache.ReadReq_accesses::total 13691720 # number of ReadReq accesses(hits+misses) 626system.cpu.icache.demand_accesses::cpu.inst 13691720 # number of demand (read+write) accesses 627system.cpu.icache.demand_accesses::total 13691720 # number of demand (read+write) accesses 628system.cpu.icache.overall_accesses::cpu.inst 13691720 # number of overall (read+write) accesses 629system.cpu.icache.overall_accesses::total 13691720 # number of overall (read+write) accesses 630system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080793 # miss rate for ReadReq accesses 631system.cpu.icache.demand_miss_rate::cpu.inst 0.080793 # miss rate for demand accesses 632system.cpu.icache.overall_miss_rate::cpu.inst 0.080793 # miss rate for overall accesses 633system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384 # average ReadReq miss latency 634system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency 636system.cpu.icache.blocked_cycles::no_mshrs 3199983 # number of cycles access was blocked 637system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked 639system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked 641system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 642system.cpu.icache.fast_writes 0 # number of fast writes performed 643system.cpu.icache.cache_copies 0 # number of cache copies performed 644system.cpu.icache.writebacks::writebacks 59844 # number of writebacks 645system.cpu.icache.writebacks::total 59844 # number of writebacks 646system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91810 # number of ReadReq MSHR hits 647system.cpu.icache.ReadReq_mshr_hits::total 91810 # number of ReadReq MSHR hits 648system.cpu.icache.demand_mshr_hits::cpu.inst 91810 # number of demand (read+write) MSHR hits 649system.cpu.icache.demand_mshr_hits::total 91810 # number of demand (read+write) MSHR hits 650system.cpu.icache.overall_mshr_hits::cpu.inst 91810 # number of overall MSHR hits 651system.cpu.icache.overall_mshr_hits::total 91810 # number of overall MSHR hits 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014384 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 1014384 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 1014384 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 1014384 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 1014384 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 1014384 # number of overall MSHR misses 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12127535483 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 12127535483 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12127535483 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 12127535483 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12127535483 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 12127535483 # number of overall MSHR miss cycles 664system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles 665system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles 666system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles 667system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles 668system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for ReadReq accesses 669system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for demand accesses 670system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for overall accesses 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11955.566613 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 675system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 676system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 677system.cpu.dcache.replacements 645435 # number of replacements 678system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use 679system.cpu.dcache.total_refs 22022963 # Total number of references to valid blocks. 680system.cpu.dcache.sampled_refs 645947 # Sample count of references to valid blocks. 681system.cpu.dcache.avg_refs 34.094071 # Average number of references to valid blocks. 682system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit. 683system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor 684system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy 685system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy 686system.cpu.dcache.ReadReq_hits::cpu.data 14182326 # number of ReadReq hits 687system.cpu.dcache.ReadReq_hits::total 14182326 # number of ReadReq hits 688system.cpu.dcache.WriteReq_hits::cpu.data 7265741 # number of WriteReq hits 689system.cpu.dcache.WriteReq_hits::total 7265741 # number of WriteReq hits 690system.cpu.dcache.LoadLockedReq_hits::cpu.data 285851 # number of LoadLockedReq hits 691system.cpu.dcache.LoadLockedReq_hits::total 285851 # number of LoadLockedReq hits 692system.cpu.dcache.StoreCondReq_hits::cpu.data 285519 # number of StoreCondReq hits 693system.cpu.dcache.StoreCondReq_hits::total 285519 # number of StoreCondReq hits 694system.cpu.dcache.demand_hits::cpu.data 21448067 # number of demand (read+write) hits 695system.cpu.dcache.demand_hits::total 21448067 # number of demand (read+write) hits 696system.cpu.dcache.overall_hits::cpu.data 21448067 # number of overall hits 697system.cpu.dcache.overall_hits::total 21448067 # number of overall hits 698system.cpu.dcache.ReadReq_misses::cpu.data 745935 # number of ReadReq misses 699system.cpu.dcache.ReadReq_misses::total 745935 # number of ReadReq misses 700system.cpu.dcache.WriteReq_misses::cpu.data 2965804 # number of WriteReq misses 701system.cpu.dcache.WriteReq_misses::total 2965804 # number of WriteReq misses 702system.cpu.dcache.LoadLockedReq_misses::cpu.data 13758 # number of LoadLockedReq misses 703system.cpu.dcache.LoadLockedReq_misses::total 13758 # number of LoadLockedReq misses 704system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses 705system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses 706system.cpu.dcache.demand_misses::cpu.data 3711739 # number of demand (read+write) misses 707system.cpu.dcache.demand_misses::total 3711739 # number of demand (read+write) misses 708system.cpu.dcache.overall_misses::cpu.data 3711739 # number of overall misses 709system.cpu.dcache.overall_misses::total 3711739 # number of overall misses 710system.cpu.dcache.ReadReq_miss_latency::cpu.data 11230893500 # number of ReadReq miss cycles 711system.cpu.dcache.ReadReq_miss_latency::total 11230893500 # number of ReadReq miss cycles 712system.cpu.dcache.WriteReq_miss_latency::cpu.data 110142219264 # number of WriteReq miss cycles 713system.cpu.dcache.WriteReq_miss_latency::total 110142219264 # number of WriteReq miss cycles 714system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224423500 # number of LoadLockedReq miss cycles 715system.cpu.dcache.LoadLockedReq_miss_latency::total 224423500 # number of LoadLockedReq miss cycles 716system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 267500 # number of StoreCondReq miss cycles 717system.cpu.dcache.StoreCondReq_miss_latency::total 267500 # number of StoreCondReq miss cycles 718system.cpu.dcache.demand_miss_latency::cpu.data 121373112764 # number of demand (read+write) miss cycles 719system.cpu.dcache.demand_miss_latency::total 121373112764 # number of demand (read+write) miss cycles 720system.cpu.dcache.overall_miss_latency::cpu.data 121373112764 # number of overall miss cycles 721system.cpu.dcache.overall_miss_latency::total 121373112764 # number of overall miss cycles 722system.cpu.dcache.ReadReq_accesses::cpu.data 14928261 # number of ReadReq accesses(hits+misses) 723system.cpu.dcache.ReadReq_accesses::total 14928261 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.WriteReq_accesses::cpu.data 10231545 # number of WriteReq accesses(hits+misses) 725system.cpu.dcache.WriteReq_accesses::total 10231545 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299609 # number of LoadLockedReq accesses(hits+misses) 727system.cpu.dcache.LoadLockedReq_accesses::total 299609 # number of LoadLockedReq accesses(hits+misses) 728system.cpu.dcache.StoreCondReq_accesses::cpu.data 285529 # number of StoreCondReq accesses(hits+misses) 729system.cpu.dcache.StoreCondReq_accesses::total 285529 # number of StoreCondReq accesses(hits+misses) 730system.cpu.dcache.demand_accesses::cpu.data 25159806 # number of demand (read+write) accesses 731system.cpu.dcache.demand_accesses::total 25159806 # number of demand (read+write) accesses 732system.cpu.dcache.overall_accesses::cpu.data 25159806 # number of overall (read+write) accesses 733system.cpu.dcache.overall_accesses::total 25159806 # number of overall (read+write) accesses 734system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049968 # miss rate for ReadReq accesses 735system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289869 # miss rate for WriteReq accesses 736system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045920 # miss rate for LoadLockedReq accesses 737system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000035 # miss rate for StoreCondReq accesses 738system.cpu.dcache.demand_miss_rate::cpu.data 0.147527 # miss rate for demand accesses 739system.cpu.dcache.overall_miss_rate::cpu.data 0.147527 # miss rate for overall accesses 740system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.128885 # average ReadReq miss latency 741system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37137.389815 # average WriteReq miss latency 742system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16312.218346 # average LoadLockedReq miss latency 743system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26750 # average StoreCondReq miss latency 744system.cpu.dcache.demand_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency 745system.cpu.dcache.overall_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency 746system.cpu.dcache.blocked_cycles::no_mshrs 16852944 # number of cycles access was blocked 747system.cpu.dcache.blocked_cycles::no_targets 7563500 # number of cycles access was blocked 748system.cpu.dcache.blocked::no_mshrs 2993 # number of cycles access was blocked 749system.cpu.dcache.blocked::no_targets 267 # number of cycles access was blocked 750system.cpu.dcache.avg_blocked_cycles::no_mshrs 5630.786502 # average number of cycles each access was blocked 751system.cpu.dcache.avg_blocked_cycles::no_targets 28327.715356 # average number of cycles each access was blocked 752system.cpu.dcache.fast_writes 0 # number of fast writes performed 753system.cpu.dcache.cache_copies 0 # number of cache copies performed 754system.cpu.dcache.writebacks::writebacks 575111 # number of writebacks 755system.cpu.dcache.writebacks::total 575111 # number of writebacks 756system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358347 # number of ReadReq MSHR hits 757system.cpu.dcache.ReadReq_mshr_hits::total 358347 # number of ReadReq MSHR hits 758system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716460 # number of WriteReq MSHR hits 759system.cpu.dcache.WriteReq_mshr_hits::total 2716460 # number of WriteReq MSHR hits 760system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1395 # number of LoadLockedReq MSHR hits 761system.cpu.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits 762system.cpu.dcache.demand_mshr_hits::cpu.data 3074807 # number of demand (read+write) MSHR hits 763system.cpu.dcache.demand_mshr_hits::total 3074807 # number of demand (read+write) MSHR hits 764system.cpu.dcache.overall_mshr_hits::cpu.data 3074807 # number of overall MSHR hits 765system.cpu.dcache.overall_mshr_hits::total 3074807 # number of overall MSHR hits 766system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387588 # number of ReadReq MSHR misses 767system.cpu.dcache.ReadReq_mshr_misses::total 387588 # number of ReadReq MSHR misses 768system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249344 # number of WriteReq MSHR misses 769system.cpu.dcache.WriteReq_mshr_misses::total 249344 # number of WriteReq MSHR misses 770system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12363 # number of LoadLockedReq MSHR misses 771system.cpu.dcache.LoadLockedReq_mshr_misses::total 12363 # number of LoadLockedReq MSHR misses 772system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses 773system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses 774system.cpu.dcache.demand_mshr_misses::cpu.data 636932 # number of demand (read+write) MSHR misses 775system.cpu.dcache.demand_mshr_misses::total 636932 # number of demand (read+write) MSHR misses 776system.cpu.dcache.overall_mshr_misses::cpu.data 636932 # number of overall MSHR misses 777system.cpu.dcache.overall_mshr_misses::total 636932 # number of overall MSHR misses 778system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5281773000 # number of ReadReq MSHR miss cycles 779system.cpu.dcache.ReadReq_mshr_miss_latency::total 5281773000 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8909514444 # number of WriteReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency::total 8909514444 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 166180500 # number of LoadLockedReq MSHR miss cycles 783system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166180500 # number of LoadLockedReq MSHR miss cycles 784system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 235000 # number of StoreCondReq MSHR miss cycles 785system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 235000 # number of StoreCondReq MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191287444 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.demand_mshr_miss_latency::total 14191287444 # number of demand (read+write) MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191287444 # number of overall MSHR miss cycles 789system.cpu.dcache.overall_mshr_miss_latency::total 14191287444 # number of overall MSHR miss cycles 790system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500 # number of ReadReq MSHR uncacheable cycles 791system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500 # number of ReadReq MSHR uncacheable cycles 792system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42252638495 # number of WriteReq MSHR uncacheable cycles 793system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42252638495 # number of WriteReq MSHR uncacheable cycles 794system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995 # number of overall MSHR uncacheable cycles 795system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995 # number of overall MSHR uncacheable cycles 796system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025963 # mshr miss rate for ReadReq accesses 797system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024370 # mshr miss rate for WriteReq accesses 798system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041264 # mshr miss rate for LoadLockedReq accesses 799system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for StoreCondReq accesses 800system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for demand accesses 801system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for overall accesses 802system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223 # average ReadReq mshr miss latency 803system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067 # average WriteReq mshr miss latency 804system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708 # average LoadLockedReq mshr miss latency 805system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23500 # average StoreCondReq mshr miss latency 806system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency 807system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency 808system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 809system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 810system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 811system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 812system.iocache.replacements 0 # number of replacements 813system.iocache.tagsinuse 0 # Cycle average of tags in use 814system.iocache.total_refs 0 # Total number of references to valid blocks. 815system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 816system.iocache.avg_refs no_value # Average number of references to valid blocks. 817system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 818system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 819system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 820system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 821system.iocache.blocked::no_targets 0 # number of cycles access was blocked 822system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 823system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 824system.iocache.fast_writes 0 # number of fast writes performed 825system.iocache.cache_copies 0 # number of cache copies performed 826system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles 827system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles 828system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles 829system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles 830system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 831system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 832system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 833system.cpu.kern.inst.arm 0 # number of arm instructions executed 834system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed 835 836---------- End Simulation Statistics ---------- 837