stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.503566 # Number of seconds simulated 4sim_ticks 2503566110500 # Number of ticks simulated 5final_tick 2503566110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 76624 # Simulator instruction rate (inst/s) 8host_tick_rate 2498140220 # Simulator tick rate (ticks/s) 9host_mem_usage 386188 # Number of bytes of host memory used 10host_seconds 1002.17 # Real time elapsed on the host 11sim_insts 76790007 # Number of instructions simulated 12system.nvmem.bytes_read 64 # Number of bytes read from this memory 13system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory 14system.nvmem.bytes_written 0 # Number of bytes written to this memory 15system.nvmem.num_reads 1 # Number of read requests responded to by this memory 16system.nvmem.num_writes 0 # Number of write requests responded to by this memory 17system.nvmem.num_other 0 # Number of other requests responded to by this memory 18system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) 19system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) 20system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) 21system.physmem.bytes_read 130731152 # Number of bytes read from this memory 22system.physmem.bytes_inst_read 1101568 # Number of instructions bytes read from this memory 23system.physmem.bytes_written 9585992 # Number of bytes written to this memory 24system.physmem.num_reads 15117140 # Number of read requests responded to by this memory 25system.physmem.num_writes 856673 # Number of write requests responded to by this memory 26system.physmem.num_other 0 # Number of other requests responded to by this memory 27system.physmem.bw_read 52217975 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read 440000 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_write 3828935 # Write bandwidth from this memory (bytes/s) 30system.physmem.bw_total 56046910 # Total bandwidth to/from this memory (bytes/s) 31system.l2c.replacements 119509 # number of replacements 32system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use 33system.l2c.total_refs 1795434 # Total number of references to valid blocks. 34system.l2c.sampled_refs 150343 # Sample count of references to valid blocks. 35system.l2c.avg_refs 11.942252 # Average number of references to valid blocks. 36system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 37system.l2c.occ_blocks::0 11551.232252 # Average occupied blocks per context 38system.l2c.occ_blocks::1 14378.665001 # Average occupied blocks per context 39system.l2c.occ_percent::0 0.176258 # Average percentage of cache occupancy 40system.l2c.occ_percent::1 0.219401 # Average percentage of cache occupancy 41system.l2c.ReadReq_hits::0 1350292 # number of ReadReq hits 42system.l2c.ReadReq_hits::1 153003 # number of ReadReq hits 43system.l2c.ReadReq_hits::total 1503295 # number of ReadReq hits 44system.l2c.Writeback_hits::0 629881 # number of Writeback hits 45system.l2c.Writeback_hits::total 629881 # number of Writeback hits 46system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits 47system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits 48system.l2c.SCUpgradeReq_hits::0 16 # number of SCUpgradeReq hits 49system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits 50system.l2c.ReadExReq_hits::0 105934 # number of ReadExReq hits 51system.l2c.ReadExReq_hits::total 105934 # number of ReadExReq hits 52system.l2c.demand_hits::0 1456226 # number of demand (read+write) hits 53system.l2c.demand_hits::1 153003 # number of demand (read+write) hits 54system.l2c.demand_hits::total 1609229 # number of demand (read+write) hits 55system.l2c.overall_hits::0 1456226 # number of overall hits 56system.l2c.overall_hits::1 153003 # number of overall hits 57system.l2c.overall_hits::total 1609229 # number of overall hits 58system.l2c.ReadReq_misses::0 36080 # number of ReadReq misses 59system.l2c.ReadReq_misses::1 144 # number of ReadReq misses 60system.l2c.ReadReq_misses::total 36224 # number of ReadReq misses 61system.l2c.UpgradeReq_misses::0 3255 # number of UpgradeReq misses 62system.l2c.UpgradeReq_misses::total 3255 # number of UpgradeReq misses 63system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses 64system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 65system.l2c.ReadExReq_misses::0 140433 # number of ReadExReq misses 66system.l2c.ReadExReq_misses::total 140433 # number of ReadExReq misses 67system.l2c.demand_misses::0 176513 # number of demand (read+write) misses 68system.l2c.demand_misses::1 144 # number of demand (read+write) misses 69system.l2c.demand_misses::total 176657 # number of demand (read+write) misses 70system.l2c.overall_misses::0 176513 # number of overall misses 71system.l2c.overall_misses::1 144 # number of overall misses 72system.l2c.overall_misses::total 176657 # number of overall misses 73system.l2c.ReadReq_miss_latency 1894696500 # number of ReadReq miss cycles 74system.l2c.UpgradeReq_miss_latency 1006500 # number of UpgradeReq miss cycles 75system.l2c.ReadExReq_miss_latency 7384268500 # number of ReadExReq miss cycles 76system.l2c.demand_miss_latency 9278965000 # number of demand (read+write) miss cycles 77system.l2c.overall_miss_latency 9278965000 # number of overall miss cycles 78system.l2c.ReadReq_accesses::0 1386372 # number of ReadReq accesses(hits+misses) 79system.l2c.ReadReq_accesses::1 153147 # number of ReadReq accesses(hits+misses) 80system.l2c.ReadReq_accesses::total 1539519 # number of ReadReq accesses(hits+misses) 81system.l2c.Writeback_accesses::0 629881 # number of Writeback accesses(hits+misses) 82system.l2c.Writeback_accesses::total 629881 # number of Writeback accesses(hits+misses) 83system.l2c.UpgradeReq_accesses::0 3293 # number of UpgradeReq accesses(hits+misses) 84system.l2c.UpgradeReq_accesses::total 3293 # number of UpgradeReq accesses(hits+misses) 85system.l2c.SCUpgradeReq_accesses::0 18 # number of SCUpgradeReq accesses(hits+misses) 86system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) 87system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses) 88system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) 89system.l2c.demand_accesses::0 1632739 # number of demand (read+write) accesses 90system.l2c.demand_accesses::1 153147 # number of demand (read+write) accesses 91system.l2c.demand_accesses::total 1785886 # number of demand (read+write) accesses 92system.l2c.overall_accesses::0 1632739 # number of overall (read+write) accesses 93system.l2c.overall_accesses::1 153147 # number of overall (read+write) accesses 94system.l2c.overall_accesses::total 1785886 # number of overall (read+write) accesses 95system.l2c.ReadReq_miss_rate::0 0.026025 # miss rate for ReadReq accesses 96system.l2c.ReadReq_miss_rate::1 0.000940 # miss rate for ReadReq accesses 97system.l2c.ReadReq_miss_rate::total 0.026965 # miss rate for ReadReq accesses 98system.l2c.UpgradeReq_miss_rate::0 0.988460 # miss rate for UpgradeReq accesses 99system.l2c.SCUpgradeReq_miss_rate::0 0.111111 # miss rate for SCUpgradeReq accesses 100system.l2c.ReadExReq_miss_rate::0 0.570015 # miss rate for ReadExReq accesses 101system.l2c.demand_miss_rate::0 0.108109 # miss rate for demand accesses 102system.l2c.demand_miss_rate::1 0.000940 # miss rate for demand accesses 103system.l2c.demand_miss_rate::total 0.109049 # miss rate for demand accesses 104system.l2c.overall_miss_rate::0 0.108109 # miss rate for overall accesses 105system.l2c.overall_miss_rate::1 0.000940 # miss rate for overall accesses 106system.l2c.overall_miss_rate::total 0.109049 # miss rate for overall accesses 107system.l2c.ReadReq_avg_miss_latency::0 52513.761086 # average ReadReq miss latency 108system.l2c.ReadReq_avg_miss_latency::1 13157614.583333 # average ReadReq miss latency 109system.l2c.ReadReq_avg_miss_latency::total 13210128.344420 # average ReadReq miss latency 110system.l2c.UpgradeReq_avg_miss_latency::0 309.216590 # average UpgradeReq miss latency 111system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 112system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 113system.l2c.ReadExReq_avg_miss_latency::0 52582.145934 # average ReadExReq miss latency 114system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 115system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 116system.l2c.demand_avg_miss_latency::0 52568.167784 # average overall miss latency 117system.l2c.demand_avg_miss_latency::1 64437256.944444 # average overall miss latency 118system.l2c.demand_avg_miss_latency::total 64489825.112228 # average overall miss latency 119system.l2c.overall_avg_miss_latency::0 52568.167784 # average overall miss latency 120system.l2c.overall_avg_miss_latency::1 64437256.944444 # average overall miss latency 121system.l2c.overall_avg_miss_latency::total 64489825.112228 # average overall miss latency 122system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 123system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 124system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 125system.l2c.blocked::no_targets 0 # number of cycles access was blocked 126system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 127system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 128system.l2c.fast_writes 0 # number of fast writes performed 129system.l2c.cache_copies 0 # number of cache copies performed 130system.l2c.writebacks 102655 # number of writebacks 131system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits 132system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits 133system.l2c.overall_mshr_hits 94 # number of overall MSHR hits 134system.l2c.ReadReq_mshr_misses 36130 # number of ReadReq MSHR misses 135system.l2c.UpgradeReq_mshr_misses 3255 # number of UpgradeReq MSHR misses 136system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses 137system.l2c.ReadExReq_mshr_misses 140433 # number of ReadExReq MSHR misses 138system.l2c.demand_mshr_misses 176563 # number of demand (read+write) MSHR misses 139system.l2c.overall_mshr_misses 176563 # number of overall MSHR misses 140system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 141system.l2c.ReadReq_mshr_miss_latency 1449837500 # number of ReadReq MSHR miss cycles 142system.l2c.UpgradeReq_mshr_miss_latency 131527500 # number of UpgradeReq MSHR miss cycles 143system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles 144system.l2c.ReadExReq_mshr_miss_latency 5640075000 # number of ReadExReq MSHR miss cycles 145system.l2c.demand_mshr_miss_latency 7089912500 # number of demand (read+write) MSHR miss cycles 146system.l2c.overall_mshr_miss_latency 7089912500 # number of overall MSHR miss cycles 147system.l2c.ReadReq_mshr_uncacheable_latency 131769527500 # number of ReadReq MSHR uncacheable cycles 148system.l2c.WriteReq_mshr_uncacheable_latency 32342636570 # number of WriteReq MSHR uncacheable cycles 149system.l2c.overall_mshr_uncacheable_latency 164112164070 # number of overall MSHR uncacheable cycles 150system.l2c.ReadReq_mshr_miss_rate::0 0.026061 # mshr miss rate for ReadReq accesses 151system.l2c.ReadReq_mshr_miss_rate::1 0.235917 # mshr miss rate for ReadReq accesses 152system.l2c.ReadReq_mshr_miss_rate::total 0.261978 # mshr miss rate for ReadReq accesses 153system.l2c.UpgradeReq_mshr_miss_rate::0 0.988460 # mshr miss rate for UpgradeReq accesses 154system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 155system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 156system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.111111 # mshr miss rate for SCUpgradeReq accesses 157system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses 158system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses 159system.l2c.ReadExReq_mshr_miss_rate::0 0.570015 # mshr miss rate for ReadExReq accesses 160system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 161system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 162system.l2c.demand_mshr_miss_rate::0 0.108139 # mshr miss rate for demand accesses 163system.l2c.demand_mshr_miss_rate::1 1.152899 # mshr miss rate for demand accesses 164system.l2c.demand_mshr_miss_rate::total 1.261038 # mshr miss rate for demand accesses 165system.l2c.overall_mshr_miss_rate::0 0.108139 # mshr miss rate for overall accesses 166system.l2c.overall_mshr_miss_rate::1 1.152899 # mshr miss rate for overall accesses 167system.l2c.overall_mshr_miss_rate::total 1.261038 # mshr miss rate for overall accesses 168system.l2c.ReadReq_avg_mshr_miss_latency 40128.355937 # average ReadReq mshr miss latency 169system.l2c.UpgradeReq_avg_mshr_miss_latency 40407.834101 # average UpgradeReq mshr miss latency 170system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency 171system.l2c.ReadExReq_avg_mshr_miss_latency 40162.034565 # average ReadExReq mshr miss latency 172system.l2c.demand_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency 173system.l2c.overall_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency 174system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 175system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 176system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 177system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 178system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 179system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 180system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 181system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 182system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 183system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 184system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 185system.cf0.dma_write_txs 0 # Number of DMA write transactions. 186system.cpu.dtb.inst_hits 0 # ITB inst hits 187system.cpu.dtb.inst_misses 0 # ITB inst misses 188system.cpu.dtb.read_hits 52217329 # DTB read hits 189system.cpu.dtb.read_misses 90306 # DTB read misses 190system.cpu.dtb.write_hits 11974176 # DTB write hits 191system.cpu.dtb.write_misses 25588 # DTB write misses 192system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 193system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 194system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 195system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 196system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 197system.cpu.dtb.align_faults 5563 # Number of TLB faults due to alignment restrictions 198system.cpu.dtb.prefetch_faults 685 # Number of TLB faults due to prefetch 199system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 200system.cpu.dtb.perms_faults 2233 # Number of TLB faults due to permissions restrictions 201system.cpu.dtb.read_accesses 52307635 # DTB read accesses 202system.cpu.dtb.write_accesses 11999764 # DTB write accesses 203system.cpu.dtb.inst_accesses 0 # ITB inst accesses 204system.cpu.dtb.hits 64191505 # DTB hits 205system.cpu.dtb.misses 115894 # DTB misses 206system.cpu.dtb.accesses 64307399 # DTB accesses 207system.cpu.itb.inst_hits 14124795 # ITB inst hits 208system.cpu.itb.inst_misses 9853 # ITB inst misses 209system.cpu.itb.read_hits 0 # DTB read hits 210system.cpu.itb.read_misses 0 # DTB read misses 211system.cpu.itb.write_hits 0 # DTB write hits 212system.cpu.itb.write_misses 0 # DTB write misses 213system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 214system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 215system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 216system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 217system.cpu.itb.flush_entries 2606 # Number of entries that have been flushed from TLB 218system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 219system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 220system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 221system.cpu.itb.perms_faults 7868 # Number of TLB faults due to permissions restrictions 222system.cpu.itb.read_accesses 0 # DTB read accesses 223system.cpu.itb.write_accesses 0 # DTB write accesses 224system.cpu.itb.inst_accesses 14134648 # ITB inst accesses 225system.cpu.itb.hits 14124795 # DTB hits 226system.cpu.itb.misses 9853 # DTB misses 227system.cpu.itb.accesses 14134648 # DTB accesses 228system.cpu.numCycles 415912091 # number of cpu cycles simulated 229system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 230system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 231system.cpu.BPredUnit.lookups 16206323 # Number of BP lookups 232system.cpu.BPredUnit.condPredicted 12554772 # Number of conditional branches predicted 233system.cpu.BPredUnit.condIncorrect 1108177 # Number of conditional branches incorrect 234system.cpu.BPredUnit.BTBLookups 13916811 # Number of BTB lookups 235system.cpu.BPredUnit.BTBHits 10226428 # Number of BTB hits 236system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 237system.cpu.BPredUnit.usedRAS 1423283 # Number of times the RAS was used to get a target. 238system.cpu.BPredUnit.RASInCorrect 227054 # Number of incorrect RAS predictions. 239system.cpu.fetch.icacheStallCycles 32931583 # Number of cycles fetch is stalled on an Icache miss 240system.cpu.fetch.Insts 104747250 # Number of instructions fetch has processed 241system.cpu.fetch.Branches 16206323 # Number of branches that fetch encountered 242system.cpu.fetch.predictedBranches 11649711 # Number of branches that fetch has predicted taken 243system.cpu.fetch.Cycles 24460631 # Number of cycles fetch has run and was not squashing or blocked 244system.cpu.fetch.SquashCycles 7066944 # Number of cycles fetch has spent squashing 245system.cpu.fetch.TlbCycles 130925 # Number of cycles fetch has spent waiting for tlb 246system.cpu.fetch.BlockedCycles 92852979 # Number of cycles fetch has spent blocked 247system.cpu.fetch.MiscStallCycles 1378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 248system.cpu.fetch.PendingTrapStallCycles 144764 # Number of stall cycles due to pending traps 249system.cpu.fetch.PendingQuiesceStallCycles 217141 # Number of stall cycles due to pending quiesce instructions 250system.cpu.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR 251system.cpu.fetch.CacheLines 14116150 # Number of cache lines fetched 252system.cpu.fetch.IcacheSquashes 1044696 # Number of outstanding Icache misses that were squashed 253system.cpu.fetch.ItlbSquashes 4826 # Number of outstanding ITLB misses that were squashed 254system.cpu.fetch.rateDist::samples 155542524 # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::mean 0.838034 # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::stdev 2.183637 # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::0 131107701 84.29% 84.29% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::1 1736645 1.12% 85.41% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::2 2606210 1.68% 87.08% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::3 3650547 2.35% 89.43% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::4 2167045 1.39% 90.82% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::5 1435515 0.92% 91.75% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::6 2626627 1.69% 93.43% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::7 854151 0.55% 93.98% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::8 9358083 6.02% 100.00% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::total 155542524 # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.branchRate 0.038966 # Number of branch fetches per cycle 272system.cpu.fetch.rate 0.251849 # Number of inst fetches per cycle 273system.cpu.decode.IdleCycles 35137982 # Number of cycles decode is idle 274system.cpu.decode.BlockedCycles 92713675 # Number of cycles decode is blocked 275system.cpu.decode.RunCycles 21969277 # Number of cycles decode is running 276system.cpu.decode.UnblockCycles 1093477 # Number of cycles decode is unblocking 277system.cpu.decode.SquashCycles 4628113 # Number of cycles decode is squashing 278system.cpu.decode.BranchResolved 2313056 # Number of times decode resolved a branch 279system.cpu.decode.BranchMispred 177631 # Number of times decode detected a branch misprediction 280system.cpu.decode.DecodedInsts 122001156 # Number of instructions handled by decode 281system.cpu.decode.SquashedInsts 574106 # Number of squashed instructions handled by decode 282system.cpu.rename.SquashCycles 4628113 # Number of cycles rename is squashing 283system.cpu.rename.IdleCycles 37294552 # Number of cycles rename is idle 284system.cpu.rename.BlockCycles 36817406 # Number of cycles rename is blocking 285system.cpu.rename.serializeStallCycles 49929047 # count of cycles rename stalled for serializing inst 286system.cpu.rename.RunCycles 20901153 # Number of cycles rename is running 287system.cpu.rename.UnblockCycles 5972253 # Number of cycles rename is unblocking 288system.cpu.rename.RenamedInsts 113826701 # Number of instructions processed by rename 289system.cpu.rename.ROBFullEvents 4400 # Number of times rename has blocked due to ROB full 290system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full 291system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full 292system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers 293system.cpu.rename.RenamedOperands 118358543 # Number of destination operands rename has renamed 294system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made 295system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups 296system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups 297system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed 298system.cpu.rename.UndoneMaps 40865824 # Number of HB maps that are undone due to squashing 299system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed 300system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed 301system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer 302system.cpu.memDep0.insertedLoads 21982315 # Number of loads inserted to the mem dependence unit. 303system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit. 304system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads. 305system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores. 306system.cpu.iq.iqInstsAdded 102860211 # Number of instructions added to the IQ (excludes non-spec) 307system.cpu.iq.iqNonSpecInstsAdded 1874616 # Number of non-speculative instructions added to the IQ 308system.cpu.iq.iqInstsIssued 126873316 # Number of instructions issued 309system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued 310system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling 311system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph 312system.cpu.iq.iqSquashedNonSpecRemoved 374923 # Number of squashed non-spec instructions that were removed 313system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::0 108919716 70.03% 70.03% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::4 12766129 8.21% 96.99% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::5 2735746 1.76% 98.75% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::total 155542524 # Number of insts issued each cycle 330system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 331system.cpu.iq.fu_full::IntAlu 45891 0.52% 0.52% # attempts to use FU when none available 332system.cpu.iq.fu_full::IntMult 6 0.00% 0.52% # attempts to use FU when none available 333system.cpu.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available 334system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available 336system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available 337system.cpu.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available 360system.cpu.iq.fu_full::MemRead 8417784 94.58% 95.09% # attempts to use FU when none available 361system.cpu.iq.fu_full::MemWrite 436630 4.91% 100.00% # attempts to use FU when none available 362system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 363system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 364system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued 365system.cpu.iq.FU_type_0::IntAlu 60069482 47.35% 47.43% # Type of FU issued 366system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued 367system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued 368system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued 370system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued 371system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued 372system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 47.51% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.51% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatMisc 2251 0.00% 47.51% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.51% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued 394system.cpu.iq.FU_type_0::MemRead 53942685 42.52% 90.02% # Type of FU issued 395system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued 396system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 397system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 398system.cpu.iq.FU_type_0::total 126873316 # Type of FU issued 399system.cpu.iq.rate 0.305048 # Inst issue rate 400system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested 401system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst) 402system.cpu.iq.int_inst_queue_reads 418533128 # Number of integer instruction queue reads 403system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes 404system.cpu.iq.int_inst_queue_wakeup_accesses 87292108 # Number of integer instruction queue wakeup accesses 405system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads 406system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes 407system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses 408system.cpu.iq.int_alu_accesses 135654305 # Number of integer alu accesses 409system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses 410system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores 411system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 412system.cpu.iew.lsq.thread0.squashedLoads 6301517 # Number of loads squashed 413system.cpu.iew.lsq.thread0.ignoredResponses 11128 # Number of memory responses ignored because the instruction is squashed 414system.cpu.iew.lsq.thread0.memOrderViolation 32657 # Number of memory ordering violations 415system.cpu.iew.lsq.thread0.squashedStores 2389653 # Number of stores squashed 416system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 417system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 418system.cpu.iew.lsq.thread0.rescheduledLoads 34061869 # Number of loads that were rescheduled 419system.cpu.iew.lsq.thread0.cacheBlocked 1153605 # Number of times an access to memory failed due to the cache being blocked 420system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 421system.cpu.iew.iewSquashCycles 4628113 # Number of cycles IEW is squashing 422system.cpu.iew.iewBlockCycles 28345943 # Number of cycles IEW is blocking 423system.cpu.iew.iewUnblockCycles 419499 # Number of cycles IEW is unblocking 424system.cpu.iew.iewDispatchedInsts 104949442 # Number of instructions dispatched to IQ 425system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch 426system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions 427system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions 428system.cpu.iew.iewDispNonSpecInsts 1228031 # Number of dispatched non-speculative instructions 429system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall 430system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall 431system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations 432system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly 433system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly 434system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute 435system.cpu.iew.iewExecutedInsts 123429779 # Number of executed instructions 436system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed 437system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute 438system.cpu.iew.exec_swp 0 # number of swp insts executed 439system.cpu.iew.exec_nop 214615 # number of nop insts executed 440system.cpu.iew.exec_refs 65401525 # number of memory reference insts executed 441system.cpu.iew.exec_branches 11705842 # Number of branches executed 442system.cpu.iew.exec_stores 12487221 # Number of stores executed 443system.cpu.iew.exec_rate 0.296769 # Inst execution rate 444system.cpu.iew.wb_sent 121771133 # cumulative count of insts sent to commit 445system.cpu.iew.wb_count 87302554 # cumulative count of insts written-back 446system.cpu.iew.wb_producers 47043389 # num instructions producing a value 447system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value 448system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 449system.cpu.iew.wb_rate 0.209906 # insts written-back per cycle 450system.cpu.iew.wb_fanout 0.542984 # average fanout of values written-back 451system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 452system.cpu.commit.commitCommittedInsts 76940388 # The number of committed instructions 453system.cpu.commit.commitSquashedInsts 27793277 # The number of squashed insts skipped by commit 454system.cpu.commit.commitNonSpecStalls 1499693 # The number of times commit has been forced to stall to communicate backwards 455system.cpu.commit.branchMispredicts 977065 # The number of times a branch was mispredicted 456system.cpu.commit.committed_per_cycle::samples 150996763 # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::mean 0.509550 # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::stdev 1.459324 # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::0 122144480 80.89% 80.89% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::1 14839804 9.83% 90.72% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::2 4110999 2.72% 93.44% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::3 2181780 1.44% 94.89% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::4 1788910 1.18% 96.07% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::5 1360879 0.90% 96.97% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::6 1262027 0.84% 97.81% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::7 662023 0.44% 98.25% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::8 2645861 1.75% 100.00% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::total 150996763 # Number of insts commited each cycle 473system.cpu.commit.count 76940388 # Number of instructions committed 474system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 475system.cpu.commit.refs 27459875 # Number of memory references committed 476system.cpu.commit.loads 15680798 # Number of loads committed 477system.cpu.commit.membars 413062 # Number of memory barriers committed 478system.cpu.commit.branches 9891038 # Number of branches committed 479system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 480system.cpu.commit.int_insts 68493475 # Number of committed integer instructions. 481system.cpu.commit.function_calls 995603 # Number of function calls committed. 482system.cpu.commit.bw_lim_events 2645861 # number cycles where commit BW limit reached 483system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 484system.cpu.rob.rob_reads 251328068 # The number of ROB reads 485system.cpu.rob.rob_writes 214226863 # The number of ROB writes 486system.cpu.timesIdled 1877486 # Number of times that the entire CPU went into an idle state and unscheduled itself 487system.cpu.idleCycles 260369567 # Total number of cycles that the CPU has spent unscheduled due to idling 488system.cpu.quiesceCycles 4591132146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 489system.cpu.committedInsts 76790007 # Number of Instructions Simulated 490system.cpu.committedInsts_total 76790007 # Number of Instructions Simulated 491system.cpu.cpi 5.416227 # CPI: Cycles Per Instruction 492system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads 493system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle 494system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads 495system.cpu.int_regfile_reads 559625786 # number of integer regfile reads 496system.cpu.int_regfile_writes 89694789 # number of integer regfile writes 497system.cpu.fp_regfile_reads 8322 # number of floating regfile reads 498system.cpu.fp_regfile_writes 2832 # number of floating regfile writes 499system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads 500system.cpu.misc_regfile_writes 912282 # number of misc regfile writes 501system.cpu.icache.replacements 991618 # number of replacements 502system.cpu.icache.tagsinuse 511.615309 # Cycle average of tags in use 503system.cpu.icache.total_refs 13036767 # Total number of references to valid blocks. 504system.cpu.icache.sampled_refs 992130 # Sample count of references to valid blocks. 505system.cpu.icache.avg_refs 13.140180 # Average number of references to valid blocks. 506system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. 507system.cpu.icache.occ_blocks::0 511.615309 # Average occupied blocks per context 508system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy 509system.cpu.icache.ReadReq_hits::0 13036767 # number of ReadReq hits 510system.cpu.icache.ReadReq_hits::total 13036767 # number of ReadReq hits 511system.cpu.icache.demand_hits::0 13036767 # number of demand (read+write) hits 512system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 513system.cpu.icache.demand_hits::total 13036767 # number of demand (read+write) hits 514system.cpu.icache.overall_hits::0 13036767 # number of overall hits 515system.cpu.icache.overall_hits::1 0 # number of overall hits 516system.cpu.icache.overall_hits::total 13036767 # number of overall hits 517system.cpu.icache.ReadReq_misses::0 1079261 # number of ReadReq misses 518system.cpu.icache.ReadReq_misses::total 1079261 # number of ReadReq misses 519system.cpu.icache.demand_misses::0 1079261 # number of demand (read+write) misses 520system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 521system.cpu.icache.demand_misses::total 1079261 # number of demand (read+write) misses 522system.cpu.icache.overall_misses::0 1079261 # number of overall misses 523system.cpu.icache.overall_misses::1 0 # number of overall misses 524system.cpu.icache.overall_misses::total 1079261 # number of overall misses 525system.cpu.icache.ReadReq_miss_latency 15910722989 # number of ReadReq miss cycles 526system.cpu.icache.demand_miss_latency 15910722989 # number of demand (read+write) miss cycles 527system.cpu.icache.overall_miss_latency 15910722989 # number of overall miss cycles 528system.cpu.icache.ReadReq_accesses::0 14116028 # number of ReadReq accesses(hits+misses) 529system.cpu.icache.ReadReq_accesses::total 14116028 # number of ReadReq accesses(hits+misses) 530system.cpu.icache.demand_accesses::0 14116028 # number of demand (read+write) accesses 531system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 532system.cpu.icache.demand_accesses::total 14116028 # number of demand (read+write) accesses 533system.cpu.icache.overall_accesses::0 14116028 # number of overall (read+write) accesses 534system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 535system.cpu.icache.overall_accesses::total 14116028 # number of overall (read+write) accesses 536system.cpu.icache.ReadReq_miss_rate::0 0.076456 # miss rate for ReadReq accesses 537system.cpu.icache.demand_miss_rate::0 0.076456 # miss rate for demand accesses 538system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 539system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 540system.cpu.icache.overall_miss_rate::0 0.076456 # miss rate for overall accesses 541system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 542system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 543system.cpu.icache.ReadReq_avg_miss_latency::0 14742.238429 # average ReadReq miss latency 544system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 545system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 546system.cpu.icache.demand_avg_miss_latency::0 14742.238429 # average overall miss latency 547system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 548system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 549system.cpu.icache.overall_avg_miss_latency::0 14742.238429 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 552system.cpu.icache.blocked_cycles::no_mshrs 2475992 # number of cycles access was blocked 553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_mshrs 368 # number of cycles access was blocked 555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.icache.avg_blocked_cycles::no_mshrs 6728.239130 # average number of cycles each access was blocked 557system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 558system.cpu.icache.fast_writes 0 # number of fast writes performed 559system.cpu.icache.cache_copies 0 # number of cache copies performed 560system.cpu.icache.writebacks 57161 # number of writebacks 561system.cpu.icache.ReadReq_mshr_hits 87101 # number of ReadReq MSHR hits 562system.cpu.icache.demand_mshr_hits 87101 # number of demand (read+write) MSHR hits 563system.cpu.icache.overall_mshr_hits 87101 # number of overall MSHR hits 564system.cpu.icache.ReadReq_mshr_misses 992160 # number of ReadReq MSHR misses 565system.cpu.icache.demand_mshr_misses 992160 # number of demand (read+write) MSHR misses 566system.cpu.icache.overall_mshr_misses 992160 # number of overall MSHR misses 567system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 568system.cpu.icache.ReadReq_mshr_miss_latency 11856676492 # number of ReadReq MSHR miss cycles 569system.cpu.icache.demand_mshr_miss_latency 11856676492 # number of demand (read+write) MSHR miss cycles 570system.cpu.icache.overall_mshr_miss_latency 11856676492 # number of overall MSHR miss cycles 571system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles 572system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles 573system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070286 # mshr miss rate for ReadReq accesses 574system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 576system.cpu.icache.demand_mshr_miss_rate::0 0.070286 # mshr miss rate for demand accesses 577system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 578system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 579system.cpu.icache.overall_mshr_miss_rate::0 0.070286 # mshr miss rate for overall accesses 580system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 581system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 582system.cpu.icache.ReadReq_avg_mshr_miss_latency 11950.367372 # average ReadReq mshr miss latency 583system.cpu.icache.demand_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency 584system.cpu.icache.overall_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 586system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 587system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 588system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 589system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 590system.cpu.dcache.replacements 643915 # number of replacements 591system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use 592system.cpu.dcache.total_refs 22265831 # Total number of references to valid blocks. 593system.cpu.dcache.sampled_refs 644427 # Sample count of references to valid blocks. 594system.cpu.dcache.avg_refs 34.551363 # Average number of references to valid blocks. 595system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. 596system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context 597system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy 598system.cpu.dcache.ReadReq_hits::0 14412375 # number of ReadReq hits 599system.cpu.dcache.ReadReq_hits::total 14412375 # number of ReadReq hits 600system.cpu.dcache.WriteReq_hits::0 7264610 # number of WriteReq hits 601system.cpu.dcache.WriteReq_hits::total 7264610 # number of WriteReq hits 602system.cpu.dcache.LoadLockedReq_hits::0 299966 # number of LoadLockedReq hits 603system.cpu.dcache.LoadLockedReq_hits::total 299966 # number of LoadLockedReq hits 604system.cpu.dcache.StoreCondReq_hits::0 285484 # number of StoreCondReq hits 605system.cpu.dcache.StoreCondReq_hits::total 285484 # number of StoreCondReq hits 606system.cpu.dcache.demand_hits::0 21676985 # number of demand (read+write) hits 607system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 608system.cpu.dcache.demand_hits::total 21676985 # number of demand (read+write) hits 609system.cpu.dcache.overall_hits::0 21676985 # number of overall hits 610system.cpu.dcache.overall_hits::1 0 # number of overall hits 611system.cpu.dcache.overall_hits::total 21676985 # number of overall hits 612system.cpu.dcache.ReadReq_misses::0 724119 # number of ReadReq misses 613system.cpu.dcache.ReadReq_misses::total 724119 # number of ReadReq misses 614system.cpu.dcache.WriteReq_misses::0 2966647 # number of WriteReq misses 615system.cpu.dcache.WriteReq_misses::total 2966647 # number of WriteReq misses 616system.cpu.dcache.LoadLockedReq_misses::0 13487 # number of LoadLockedReq misses 617system.cpu.dcache.LoadLockedReq_misses::total 13487 # number of LoadLockedReq misses 618system.cpu.dcache.StoreCondReq_misses::0 18 # number of StoreCondReq misses 619system.cpu.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses 620system.cpu.dcache.demand_misses::0 3690766 # number of demand (read+write) misses 621system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 622system.cpu.dcache.demand_misses::total 3690766 # number of demand (read+write) misses 623system.cpu.dcache.overall_misses::0 3690766 # number of overall misses 624system.cpu.dcache.overall_misses::1 0 # number of overall misses 625system.cpu.dcache.overall_misses::total 3690766 # number of overall misses 626system.cpu.dcache.ReadReq_miss_latency 10885048500 # number of ReadReq miss cycles 627system.cpu.dcache.WriteReq_miss_latency 110351571736 # number of WriteReq miss cycles 628system.cpu.dcache.LoadLockedReq_miss_latency 219032000 # number of LoadLockedReq miss cycles 629system.cpu.dcache.StoreCondReq_miss_latency 343000 # number of StoreCondReq miss cycles 630system.cpu.dcache.demand_miss_latency 121236620236 # number of demand (read+write) miss cycles 631system.cpu.dcache.overall_miss_latency 121236620236 # number of overall miss cycles 632system.cpu.dcache.ReadReq_accesses::0 15136494 # number of ReadReq accesses(hits+misses) 633system.cpu.dcache.ReadReq_accesses::total 15136494 # number of ReadReq accesses(hits+misses) 634system.cpu.dcache.WriteReq_accesses::0 10231257 # number of WriteReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::total 10231257 # number of WriteReq accesses(hits+misses) 636system.cpu.dcache.LoadLockedReq_accesses::0 313453 # number of LoadLockedReq accesses(hits+misses) 637system.cpu.dcache.LoadLockedReq_accesses::total 313453 # number of LoadLockedReq accesses(hits+misses) 638system.cpu.dcache.StoreCondReq_accesses::0 285502 # number of StoreCondReq accesses(hits+misses) 639system.cpu.dcache.StoreCondReq_accesses::total 285502 # number of StoreCondReq accesses(hits+misses) 640system.cpu.dcache.demand_accesses::0 25367751 # number of demand (read+write) accesses 641system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 642system.cpu.dcache.demand_accesses::total 25367751 # number of demand (read+write) accesses 643system.cpu.dcache.overall_accesses::0 25367751 # number of overall (read+write) accesses 644system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 645system.cpu.dcache.overall_accesses::total 25367751 # number of overall (read+write) accesses 646system.cpu.dcache.ReadReq_miss_rate::0 0.047839 # miss rate for ReadReq accesses 647system.cpu.dcache.WriteReq_miss_rate::0 0.289959 # miss rate for WriteReq accesses 648system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043027 # miss rate for LoadLockedReq accesses 649system.cpu.dcache.StoreCondReq_miss_rate::0 0.000063 # miss rate for StoreCondReq accesses 650system.cpu.dcache.demand_miss_rate::0 0.145490 # miss rate for demand accesses 651system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 652system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 653system.cpu.dcache.overall_miss_rate::0 0.145490 # miss rate for overall accesses 654system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 655system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 656system.cpu.dcache.ReadReq_avg_miss_latency::0 15032.126626 # average ReadReq miss latency 657system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 658system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 659system.cpu.dcache.WriteReq_avg_miss_latency::0 37197.405602 # average WriteReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 661system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 662system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16240.231334 # average LoadLockedReq miss latency 663system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 664system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 665system.cpu.dcache.StoreCondReq_avg_miss_latency::0 19055.555556 # average StoreCondReq miss latency 666system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 667system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 668system.cpu.dcache.demand_avg_miss_latency::0 32848.633654 # average overall miss latency 669system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 670system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 671system.cpu.dcache.overall_avg_miss_latency::0 32848.633654 # average overall miss latency 672system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 673system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 674system.cpu.dcache.blocked_cycles::no_mshrs 16787932 # number of cycles access was blocked 675system.cpu.dcache.blocked_cycles::no_targets 7490000 # number of cycles access was blocked 676system.cpu.dcache.blocked::no_mshrs 2999 # number of cycles access was blocked 677system.cpu.dcache.blocked::no_targets 273 # number of cycles access was blocked 678system.cpu.dcache.avg_blocked_cycles::no_mshrs 5597.843281 # average number of cycles each access was blocked 679system.cpu.dcache.avg_blocked_cycles::no_targets 27435.897436 # average number of cycles each access was blocked 680system.cpu.dcache.fast_writes 0 # number of fast writes performed 681system.cpu.dcache.cache_copies 0 # number of cache copies performed 682system.cpu.dcache.writebacks 572720 # number of writebacks 683system.cpu.dcache.ReadReq_mshr_hits 338008 # number of ReadReq MSHR hits 684system.cpu.dcache.WriteReq_mshr_hits 2717083 # number of WriteReq MSHR hits 685system.cpu.dcache.LoadLockedReq_mshr_hits 1442 # number of LoadLockedReq MSHR hits 686system.cpu.dcache.demand_mshr_hits 3055091 # number of demand (read+write) MSHR hits 687system.cpu.dcache.overall_mshr_hits 3055091 # number of overall MSHR hits 688system.cpu.dcache.ReadReq_mshr_misses 386111 # number of ReadReq MSHR misses 689system.cpu.dcache.WriteReq_mshr_misses 249564 # number of WriteReq MSHR misses 690system.cpu.dcache.LoadLockedReq_mshr_misses 12045 # number of LoadLockedReq MSHR misses 691system.cpu.dcache.StoreCondReq_mshr_misses 18 # number of StoreCondReq MSHR misses 692system.cpu.dcache.demand_mshr_misses 635675 # number of demand (read+write) MSHR misses 693system.cpu.dcache.overall_mshr_misses 635675 # number of overall MSHR misses 694system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 695system.cpu.dcache.ReadReq_mshr_miss_latency 5247540500 # number of ReadReq MSHR miss cycles 696system.cpu.dcache.WriteReq_mshr_miss_latency 8926098932 # number of WriteReq MSHR miss cycles 697system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161654000 # number of LoadLockedReq MSHR miss cycles 698system.cpu.dcache.StoreCondReq_mshr_miss_latency 282500 # number of StoreCondReq MSHR miss cycles 699system.cpu.dcache.demand_mshr_miss_latency 14173639432 # number of demand (read+write) MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency 14173639432 # number of overall MSHR miss cycles 701system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158749000 # number of ReadReq MSHR uncacheable cycles 702system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258178710 # number of WriteReq MSHR uncacheable cycles 703system.cpu.dcache.overall_mshr_uncacheable_latency 189416927710 # number of overall MSHR uncacheable cycles 704system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025509 # mshr miss rate for ReadReq accesses 705system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 706system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 707system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024392 # mshr miss rate for WriteReq accesses 708system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 709system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 710system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038427 # mshr miss rate for LoadLockedReq accesses 711system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 712system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 713system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000063 # mshr miss rate for StoreCondReq accesses 714system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 715system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 716system.cpu.dcache.demand_mshr_miss_rate::0 0.025058 # mshr miss rate for demand accesses 717system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 718system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 719system.cpu.dcache.overall_mshr_miss_rate::0 0.025058 # mshr miss rate for overall accesses 720system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 721system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 722system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13590.756285 # average ReadReq mshr miss latency 723system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.772980 # average WriteReq mshr miss latency 724system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13420.838522 # average LoadLockedReq mshr miss latency 725system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15694.444444 # average StoreCondReq mshr miss latency 726system.cpu.dcache.demand_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency 727system.cpu.dcache.overall_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency 728system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 729system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 730system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 731system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 732system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 733system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 734system.iocache.replacements 0 # number of replacements 735system.iocache.tagsinuse 0 # Cycle average of tags in use 736system.iocache.total_refs 0 # Total number of references to valid blocks. 737system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 738system.iocache.avg_refs no_value # Average number of references to valid blocks. 739system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 740system.iocache.demand_hits::0 0 # number of demand (read+write) hits 741system.iocache.demand_hits::1 0 # number of demand (read+write) hits 742system.iocache.demand_hits::total 0 # number of demand (read+write) hits 743system.iocache.overall_hits::0 0 # number of overall hits 744system.iocache.overall_hits::1 0 # number of overall hits 745system.iocache.overall_hits::total 0 # number of overall hits 746system.iocache.demand_misses::0 0 # number of demand (read+write) misses 747system.iocache.demand_misses::1 0 # number of demand (read+write) misses 748system.iocache.demand_misses::total 0 # number of demand (read+write) misses 749system.iocache.overall_misses::0 0 # number of overall misses 750system.iocache.overall_misses::1 0 # number of overall misses 751system.iocache.overall_misses::total 0 # number of overall misses 752system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 753system.iocache.overall_miss_latency 0 # number of overall miss cycles 754system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 755system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 756system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 757system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 758system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 759system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 760system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 761system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 762system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 763system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 764system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 765system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 766system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 767system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 768system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 769system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 770system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 771system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 772system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 773system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 774system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 775system.iocache.blocked::no_targets 0 # number of cycles access was blocked 776system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 777system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 778system.iocache.fast_writes 0 # number of fast writes performed 779system.iocache.cache_copies 0 # number of cache copies performed 780system.iocache.writebacks 0 # number of writebacks 781system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 782system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 783system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 784system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 785system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 786system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 787system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 788system.iocache.ReadReq_mshr_uncacheable_latency 1307898920918 # number of ReadReq MSHR uncacheable cycles 789system.iocache.overall_mshr_uncacheable_latency 1307898920918 # number of overall MSHR uncacheable cycles 790system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 791system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 792system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 793system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 794system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 795system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 796system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 797system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 798system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 799system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 800system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 801system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 802system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 803system.cpu.kern.inst.arm 0 # number of arm instructions executed 804system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed 805 806---------- End Simulation Statistics ---------- 807