stats.txt revision 11245:1c5102c0a7a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832913 # Number of seconds simulated 4sim_ticks 2832912592000 # Number of ticks simulated 5final_tick 2832912592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 98871 # Simulator instruction rate (inst/s) 8host_op_rate 119922 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2476970660 # Simulator tick rate (ticks/s) 10host_mem_usage 585504 # Number of bytes of host memory used 11host_seconds 1143.70 # Real time elapsed on the host 12sim_insts 113079343 # Number of instructions simulated 13sim_ops 137154534 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1316096 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10702120 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1316096 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1316096 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7997312 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8014836 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 22811 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 169988 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 124958 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 129339 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 464573 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3312212 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3777780 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 464573 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 464573 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2823000 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2829186 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2823000 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 464573 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3318398 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6606966 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 169989 # Number of read requests accepted 55system.physmem.writeReqs 129339 # Number of write requests accepted 56system.physmem.readBursts 169989 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 129339 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10867584 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8027584 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10702184 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 8014836 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 48490 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11395 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10615 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11052 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11362 # Per bank write bursts 70system.physmem.perBankRdBursts::4 12761 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10093 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10904 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11084 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10554 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10523 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10030 # Per bank write bursts 77system.physmem.perBankRdBursts::11 8841 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9967 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10661 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9878 # Per bank write bursts 81system.physmem.perBankRdBursts::15 10086 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8599 # Per bank write bursts 83system.physmem.perBankWrBursts::1 7964 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8486 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8679 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7544 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7468 # Per bank write bursts 88system.physmem.perBankWrBursts::6 8077 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8182 # Per bank write bursts 90system.physmem.perBankWrBursts::8 8055 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7911 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7496 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6568 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7556 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8042 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7357 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7447 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 100system.physmem.totGap 2832912360000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 542 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 2996 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 166437 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 124958 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 150468 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 16446 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 725 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5730 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6051 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6673 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6911 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7819 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 7306 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8204 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8270 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8353 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9948 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7795 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7406 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6937 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6695 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 304 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 181 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 104 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 130 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 62097 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 304.283685 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 179.850271 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 324.574400 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 23280 37.49% 37.49% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14997 24.15% 61.64% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6479 10.43% 72.07% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3584 5.77% 77.85% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2530 4.07% 81.92% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1603 2.58% 84.50% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1574 2.53% 87.04% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1048 1.69% 88.72% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7002 11.28% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 62097 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6262 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.116097 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 564.155612 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6261 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 6262 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6262 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.030501 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.464444 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.039261 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5446 86.97% 86.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 116 1.85% 88.82% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 36 0.57% 89.40% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 167 2.67% 92.06% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 22 0.35% 92.41% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 138 2.20% 94.62% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 54 0.86% 95.48% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 12 0.19% 95.67% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 19 0.30% 95.98% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 16 0.26% 96.23% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 6 0.10% 96.33% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 3 0.05% 96.37% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 160 2.56% 98.93% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 6 0.10% 99.03% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 9 0.14% 99.17% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 25 0.40% 99.57% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 2 0.03% 99.60% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.62% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 1 0.02% 99.66% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::100-103 3 0.05% 99.71% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 1 0.02% 99.73% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 1 0.02% 99.74% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 13 0.21% 99.97% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 6262 # Writes before turning the bus around for reads 263system.physmem.totQLat 2134847750 # Total ticks spent queuing 264system.physmem.totMemAccLat 5318710250 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 849030000 # Total ticks spent in databus transfers 266system.physmem.avgQLat 12572.28 # Average queueing delay per DRAM burst 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 268system.physmem.avgMemAccLat 31322.28 # Average memory access latency per DRAM burst 269system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s 272system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.05 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 277system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 278system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing 279system.physmem.readRowHits 139313 # Number of row buffer hits during reads 280system.physmem.writeRowHits 93826 # Number of row buffer hits during writes 281system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 74.79 # Row buffer hit rate for writes 283system.physmem.avgGap 9464241.10 # Average gap between requests 284system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined 285system.physmem_0.actEnergy 247680720 # Energy for activate commands per rank (pJ) 286system.physmem_0.preEnergy 135143250 # Energy for precharge commands per rank (pJ) 287system.physmem_0.readEnergy 696267000 # Energy for read commands per rank (pJ) 288system.physmem_0.writeEnergy 421193520 # Energy for write commands per rank (pJ) 289system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) 290system.physmem_0.actBackEnergy 83693103705 # Energy for active background per rank (pJ) 291system.physmem_0.preBackEnergy 1626331305750 # Energy for precharge background per rank (pJ) 292system.physmem_0.totalEnergy 1896556621545 # Total energy per rank (pJ) 293system.physmem_0.averagePower 669.472831 # Core power per rank (mW) 294system.physmem_0.memoryStateTime::IDLE 2705407276500 # Time in different power states 295system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states 296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 297system.physmem_0.memoryStateTime::ACT 32908202000 # Time in different power states 298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 299system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ) 300system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ) 301system.physmem_1.readEnergy 628212000 # Energy for read commands per rank (pJ) 302system.physmem_1.writeEnergy 391599360 # Energy for write commands per rank (pJ) 303system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) 304system.physmem_1.actBackEnergy 81799663455 # Energy for active background per rank (pJ) 305system.physmem_1.preBackEnergy 1627992218250 # Energy for precharge background per rank (pJ) 306system.physmem_1.totalEnergy 1896186400140 # Total energy per rank (pJ) 307system.physmem_1.averagePower 669.342145 # Core power per rank (mW) 308system.physmem_1.memoryStateTime::IDLE 2708183660500 # Time in different power states 309system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states 310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 311system.physmem_1.memoryStateTime::ACT 30129768250 # Time in different power states 312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 313system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 314system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 315system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 316system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 317system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 318system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 319system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 324system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 325system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 326system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 327system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 328system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 329system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 330system.cf0.dma_write_txs 631 # Number of DMA write transactions. 331system.cpu.branchPred.lookups 46857763 # Number of BP lookups 332system.cpu.branchPred.condPredicted 24018162 # Number of conditional branches predicted 333system.cpu.branchPred.condIncorrect 1233841 # Number of conditional branches incorrect 334system.cpu.branchPred.BTBLookups 29502900 # Number of BTB lookups 335system.cpu.branchPred.BTBHits 21322687 # Number of BTB hits 336system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 337system.cpu.branchPred.BTBHitPct 72.273190 # BTB Hit Percentage 338system.cpu.branchPred.usedRAS 11723693 # Number of times the RAS was used to get a target. 339system.cpu.branchPred.RASInCorrect 33902 # Number of incorrect RAS predictions. 340system.cpu_clk_domain.clock 500 # Clock period in ticks 341system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 350system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 351system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 352system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 353system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 354system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 355system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 356system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 357system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 358system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 359system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 360system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 361system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 362system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 363system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 364system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 365system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 366system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 367system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 368system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 369system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 370system.cpu.dtb.walker.walks 71876 # Table walker walks requested 371system.cpu.dtb.walker.walksShort 71876 # Table walker walks initiated with short descriptors 372system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29748 # Level at which table walker walks with short descriptors terminate 373system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22357 # Level at which table walker walks with short descriptors terminate 374system.cpu.dtb.walker.walksSquashedBefore 19771 # Table walks squashed before starting 375system.cpu.dtb.walker.walkWaitTime::samples 52105 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkWaitTime::mean 423.395068 # Table walker wait (enqueue to first request) latency 377system.cpu.dtb.walker.walkWaitTime::stdev 2574.283993 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::0-4095 50327 96.59% 96.59% # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.12% 97.71% # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.01% 98.72% # Table walker wait (enqueue to first request) latency 381system.cpu.dtb.walker.walkWaitTime::12288-16383 339 0.65% 99.37% # Table walker wait (enqueue to first request) latency 382system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency 383system.cpu.dtb.walker.walkWaitTime::20480-24575 221 0.42% 99.89% # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency 386system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.95% # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::45056-49151 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::total 52105 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkCompletionTime::samples 17499 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::mean 11526.115778 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::gmean 9158.153521 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::stdev 8139.378931 # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::0-32767 17316 98.95% 98.95% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::total 17499 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walksPending::samples 131377054816 # Table walker pending requests distribution 405system.cpu.dtb.walker.walksPending::mean 0.616890 # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::stdev 0.493493 # Table walker pending requests distribution 407system.cpu.dtb.walker.walksPending::0-1 131322424316 99.96% 99.96% # Table walker pending requests distribution 408system.cpu.dtb.walker.walksPending::2-3 37436500 0.03% 99.99% # Table walker pending requests distribution 409system.cpu.dtb.walker.walksPending::4-5 7011000 0.01% 99.99% # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::6-7 6169000 0.00% 100.00% # Table walker pending requests distribution 411system.cpu.dtb.walker.walksPending::8-9 1200000 0.00% 100.00% # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution 414system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution 415system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution 416system.cpu.dtb.walker.walksPending::total 131377054816 # Table walker pending requests distribution 417system.cpu.dtb.walker.walkPageSizes::4K 6345 82.32% 82.32% # Table walker page sizes translated 418system.cpu.dtb.walker.walkPageSizes::1M 1363 17.68% 100.00% # Table walker page sizes translated 419system.cpu.dtb.walker.walkPageSizes::total 7708 # Table walker page sizes translated 420system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71876 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71876 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7708 # Table walker requests started/completed, data/inst 424system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7708 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin::total 79584 # Table walker requests started/completed, data/inst 427system.cpu.dtb.inst_hits 0 # ITB inst hits 428system.cpu.dtb.inst_misses 0 # ITB inst misses 429system.cpu.dtb.read_hits 25445789 # DTB read hits 430system.cpu.dtb.read_misses 61974 # DTB read misses 431system.cpu.dtb.write_hits 19906281 # DTB write hits 432system.cpu.dtb.write_misses 9902 # DTB write misses 433system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 434system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 435system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 436system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 437system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB 438system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions 439system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch 440system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 441system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions 442system.cpu.dtb.read_accesses 25507763 # DTB read accesses 443system.cpu.dtb.write_accesses 19916183 # DTB write accesses 444system.cpu.dtb.inst_accesses 0 # ITB inst accesses 445system.cpu.dtb.hits 45352070 # DTB hits 446system.cpu.dtb.misses 71876 # DTB misses 447system.cpu.dtb.accesses 45423946 # DTB accesses 448system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 457system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 458system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 459system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 460system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 461system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 463system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 464system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 465system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 466system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 467system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 468system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 469system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 470system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 471system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 472system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 473system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 474system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 475system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 476system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 477system.cpu.itb.walker.walks 11893 # Table walker walks requested 478system.cpu.itb.walker.walksShort 11893 # Table walker walks initiated with short descriptors 479system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate 480system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate 481system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting 482system.cpu.itb.walker.walkWaitTime::samples 11672 # Table walker wait (enqueue to first request) latency 483system.cpu.itb.walker.walkWaitTime::mean 618.017478 # Table walker wait (enqueue to first request) latency 484system.cpu.itb.walker.walkWaitTime::stdev 2885.502200 # Table walker wait (enqueue to first request) latency 485system.cpu.itb.walker.walkWaitTime::0-4095 11116 95.24% 95.24% # Table walker wait (enqueue to first request) latency 486system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency 487system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 98.24% # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.77% # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.61% # Table walker wait (enqueue to first request) latency 490system.cpu.itb.walker.walkWaitTime::20480-24575 33 0.28% 99.90% # Table walker wait (enqueue to first request) latency 491system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency 492system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency 493system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 494system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 495system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 496system.cpu.itb.walker.walkWaitTime::total 11672 # Table walker wait (enqueue to first request) latency 497system.cpu.itb.walker.walkCompletionTime::samples 3547 # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::mean 12874.259938 # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walkCompletionTime::gmean 10191.545390 # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walkCompletionTime::stdev 8701.526273 # Table walker service (enqueue to completion) latency 501system.cpu.itb.walker.walkCompletionTime::0-16383 2599 73.27% 73.27% # Table walker service (enqueue to completion) latency 502system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.09% 98.36% # Table walker service (enqueue to completion) latency 503system.cpu.itb.walker.walkCompletionTime::32768-49151 56 1.58% 99.94% # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency 505system.cpu.itb.walker.walkCompletionTime::total 3547 # Table walker service (enqueue to completion) latency 506system.cpu.itb.walker.walksPending::samples 24002810416 # Table walker pending requests distribution 507system.cpu.itb.walker.walksPending::mean 0.962951 # Table walker pending requests distribution 508system.cpu.itb.walker.walksPending::stdev 0.189029 # Table walker pending requests distribution 509system.cpu.itb.walker.walksPending::0 889895500 3.71% 3.71% # Table walker pending requests distribution 510system.cpu.itb.walker.walksPending::1 23112364416 96.29% 100.00% # Table walker pending requests distribution 511system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution 512system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution 513system.cpu.itb.walker.walksPending::total 24002810416 # Table walker pending requests distribution 514system.cpu.itb.walker.walkPageSizes::4K 3008 90.44% 90.44% # Table walker page sizes translated 515system.cpu.itb.walker.walkPageSizes::1M 318 9.56% 100.00% # Table walker page sizes translated 516system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated 517system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 518system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11893 # Table walker requests started/completed, data/inst 519system.cpu.itb.walker.walkRequestOrigin_Requested::total 11893 # Table walker requests started/completed, data/inst 520system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 521system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst 522system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst 523system.cpu.itb.walker.walkRequestOrigin::total 15219 # Table walker requests started/completed, data/inst 524system.cpu.itb.inst_hits 66221269 # ITB inst hits 525system.cpu.itb.inst_misses 11893 # ITB inst misses 526system.cpu.itb.read_hits 0 # DTB read hits 527system.cpu.itb.read_misses 0 # DTB read misses 528system.cpu.itb.write_hits 0 # DTB write hits 529system.cpu.itb.write_misses 0 # DTB write misses 530system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 531system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 532system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 533system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 534system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB 535system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 536system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 537system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 538system.cpu.itb.perms_faults 2209 # Number of TLB faults due to permissions restrictions 539system.cpu.itb.read_accesses 0 # DTB read accesses 540system.cpu.itb.write_accesses 0 # DTB write accesses 541system.cpu.itb.inst_accesses 66233162 # ITB inst accesses 542system.cpu.itb.hits 66221269 # DTB hits 543system.cpu.itb.misses 11893 # DTB misses 544system.cpu.itb.accesses 66233162 # DTB accesses 545system.cpu.numCycles 278796094 # number of cpu cycles simulated 546system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 547system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 548system.cpu.fetch.icacheStallCycles 104750737 # Number of cycles fetch is stalled on an Icache miss 549system.cpu.fetch.Insts 184597310 # Number of instructions fetch has processed 550system.cpu.fetch.Branches 46857763 # Number of branches that fetch encountered 551system.cpu.fetch.predictedBranches 33046380 # Number of branches that fetch has predicted taken 552system.cpu.fetch.Cycles 161828011 # Number of cycles fetch has run and was not squashing or blocked 553system.cpu.fetch.SquashCycles 6150220 # Number of cycles fetch has spent squashing 554system.cpu.fetch.TlbCycles 189816 # Number of cycles fetch has spent waiting for tlb 555system.cpu.fetch.MiscStallCycles 10180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 556system.cpu.fetch.PendingTrapStallCycles 357136 # Number of stall cycles due to pending traps 557system.cpu.fetch.PendingQuiesceStallCycles 560173 # Number of stall cycles due to pending quiesce instructions 558system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR 559system.cpu.fetch.CacheLines 66221459 # Number of cache lines fetched 560system.cpu.fetch.IcacheSquashes 1133676 # Number of outstanding Icache misses that were squashed 561system.cpu.fetch.ItlbSquashes 5180 # Number of outstanding ITLB misses that were squashed 562system.cpu.fetch.rateDist::samples 270771349 # Number of instructions fetched each cycle (Total) 563system.cpu.fetch.rateDist::mean 0.831471 # Number of instructions fetched each cycle (Total) 564system.cpu.fetch.rateDist::stdev 1.217911 # Number of instructions fetched each cycle (Total) 565system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 566system.cpu.fetch.rateDist::0 171553381 63.36% 63.36% # Number of instructions fetched each cycle (Total) 567system.cpu.fetch.rateDist::1 29224188 10.79% 74.15% # Number of instructions fetched each cycle (Total) 568system.cpu.fetch.rateDist::2 14067085 5.20% 79.35% # Number of instructions fetched each cycle (Total) 569system.cpu.fetch.rateDist::3 55926695 20.65% 100.00% # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 571system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 572system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::total 270771349 # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.branchRate 0.168072 # Number of branch fetches per cycle 575system.cpu.fetch.rate 0.662123 # Number of inst fetches per cycle 576system.cpu.decode.IdleCycles 77850364 # Number of cycles decode is idle 577system.cpu.decode.BlockedCycles 121893157 # Number of cycles decode is blocked 578system.cpu.decode.RunCycles 64586539 # Number of cycles decode is running 579system.cpu.decode.UnblockCycles 3844068 # Number of cycles decode is unblocking 580system.cpu.decode.SquashCycles 2597221 # Number of cycles decode is squashing 581system.cpu.decode.BranchResolved 3423151 # Number of times decode resolved a branch 582system.cpu.decode.BranchMispred 486287 # Number of times decode detected a branch misprediction 583system.cpu.decode.DecodedInsts 157328219 # Number of instructions handled by decode 584system.cpu.decode.SquashedInsts 3698916 # Number of squashed instructions handled by decode 585system.cpu.rename.SquashCycles 2597221 # Number of cycles rename is squashing 586system.cpu.rename.IdleCycles 83695488 # Number of cycles rename is idle 587system.cpu.rename.BlockCycles 11783440 # Number of cycles rename is blocking 588system.cpu.rename.serializeStallCycles 76673328 # count of cycles rename stalled for serializing inst 589system.cpu.rename.RunCycles 62587040 # Number of cycles rename is running 590system.cpu.rename.UnblockCycles 33434832 # Number of cycles rename is unblocking 591system.cpu.rename.RenamedInsts 146701505 # Number of instructions processed by rename 592system.cpu.rename.SquashedInsts 957116 # Number of squashed instructions processed by rename 593system.cpu.rename.ROBFullEvents 452960 # Number of times rename has blocked due to ROB full 594system.cpu.rename.IQFullEvents 63776 # Number of times rename has blocked due to IQ full 595system.cpu.rename.LQFullEvents 16375 # Number of times rename has blocked due to LQ full 596system.cpu.rename.SQFullEvents 30685156 # Number of times rename has blocked due to SQ full 597system.cpu.rename.RenamedOperands 150380164 # Number of destination operands rename has renamed 598system.cpu.rename.RenameLookups 678249075 # Number of register rename lookups that rename has made 599system.cpu.rename.int_rename_lookups 164321181 # Number of integer rename lookups 600system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups 601system.cpu.rename.CommittedMaps 141709271 # Number of HB maps that are committed 602system.cpu.rename.UndoneMaps 8670890 # Number of HB maps that are undone due to squashing 603system.cpu.rename.serializingInsts 2840534 # count of serializing insts renamed 604system.cpu.rename.tempSerializingInsts 2644382 # count of temporary serializing insts renamed 605system.cpu.rename.skidInsts 13862021 # count of insts added to the skid buffer 606system.cpu.memDep0.insertedLoads 26394587 # Number of loads inserted to the mem dependence unit. 607system.cpu.memDep0.insertedStores 21292605 # Number of stores inserted to the mem dependence unit. 608system.cpu.memDep0.conflictingLoads 1688978 # Number of conflicting loads. 609system.cpu.memDep0.conflictingStores 2214312 # Number of conflicting stores. 610system.cpu.iq.iqInstsAdded 143440731 # Number of instructions added to the IQ (excludes non-spec) 611system.cpu.iq.iqNonSpecInstsAdded 2121629 # Number of non-speculative instructions added to the IQ 612system.cpu.iq.iqInstsIssued 143228275 # Number of instructions issued 613system.cpu.iq.iqSquashedInstsIssued 270765 # Number of squashed instructions issued 614system.cpu.iq.iqSquashedInstsExamined 8407822 # Number of squashed instructions iterated over during squash; mainly for profiling 615system.cpu.iq.iqSquashedOperandsExamined 14697300 # Number of squashed operands that are examined and possibly removed from graph 616system.cpu.iq.iqSquashedNonSpecRemoved 125774 # Number of squashed non-spec instructions that were removed 617system.cpu.iq.issued_per_cycle::samples 270771349 # Number of insts issued each cycle 618system.cpu.iq.issued_per_cycle::mean 0.528964 # Number of insts issued each cycle 619system.cpu.iq.issued_per_cycle::stdev 0.865543 # Number of insts issued each cycle 620system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 621system.cpu.iq.issued_per_cycle::0 182535287 67.41% 67.41% # Number of insts issued each cycle 622system.cpu.iq.issued_per_cycle::1 45134238 16.67% 84.08% # Number of insts issued each cycle 623system.cpu.iq.issued_per_cycle::2 32022031 11.83% 95.91% # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::3 10269230 3.79% 99.70% # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::4 810530 0.30% 100.00% # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 627system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::total 270771349 # Number of insts issued each cycle 634system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 635system.cpu.iq.fu_full::IntAlu 7336420 32.74% 32.74% # attempts to use FU when none available 636system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available 637system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available 638system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available 639system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available 640system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available 641system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available 642system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available 643system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available 644system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available 645system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available 646system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available 647system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available 648system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available 649system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available 650system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available 651system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available 664system.cpu.iq.fu_full::MemRead 5631672 25.13% 57.86% # attempts to use FU when none available 665system.cpu.iq.fu_full::MemWrite 9443165 42.14% 100.00% # attempts to use FU when none available 666system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 667system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 668system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued 669system.cpu.iq.FU_type_0::IntAlu 95929589 66.98% 66.98% # Type of FU issued 670system.cpu.iq.FU_type_0::IntMult 113798 0.08% 67.06% # Type of FU issued 671system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 672system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 673system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 674system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 675system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 676system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 677system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 678system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued 679system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued 680system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued 681system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued 682system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued 683system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued 685system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued 686system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued 687system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued 688system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 691system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 692system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued 698system.cpu.iq.FU_type_0::MemRead 26176168 18.28% 85.34% # Type of FU issued 699system.cpu.iq.FU_type_0::MemWrite 20997807 14.66% 100.00% # Type of FU issued 700system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 701system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 702system.cpu.iq.FU_type_0::total 143228275 # Type of FU issued 703system.cpu.iq.rate 0.513738 # Inst issue rate 704system.cpu.iq.fu_busy_cnt 22411289 # FU busy when requested 705system.cpu.iq.fu_busy_rate 0.156473 # FU busy rate (busy events/executed inst) 706system.cpu.iq.int_inst_queue_reads 579874368 # Number of integer instruction queue reads 707system.cpu.iq.int_inst_queue_writes 153975557 # Number of integer instruction queue writes 708system.cpu.iq.int_inst_queue_wakeup_accesses 140119306 # Number of integer instruction queue wakeup accesses 709system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads 710system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes 711system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses 712system.cpu.iq.int_alu_accesses 165613882 # Number of integer alu accesses 713system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses 714system.cpu.iew.lsq.thread0.forwLoads 322775 # Number of loads that had data forwarded from stores 715system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 716system.cpu.iew.lsq.thread0.squashedLoads 1495918 # Number of loads squashed 717system.cpu.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed 718system.cpu.iew.lsq.thread0.memOrderViolation 18543 # Number of memory ordering violations 719system.cpu.iew.lsq.thread0.squashedStores 704297 # Number of stores squashed 720system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 721system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 722system.cpu.iew.lsq.thread0.rescheduledLoads 87804 # Number of loads that were rescheduled 723system.cpu.iew.lsq.thread0.cacheBlocked 6457 # Number of times an access to memory failed due to the cache being blocked 724system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 725system.cpu.iew.iewSquashCycles 2597221 # Number of cycles IEW is squashing 726system.cpu.iew.iewBlockCycles 1240950 # Number of cycles IEW is blocking 727system.cpu.iew.iewUnblockCycles 535645 # Number of cycles IEW is unblocking 728system.cpu.iew.iewDispatchedInsts 145763292 # Number of instructions dispatched to IQ 729system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 730system.cpu.iew.iewDispLoadInsts 26394587 # Number of dispatched load instructions 731system.cpu.iew.iewDispStoreInsts 21292605 # Number of dispatched store instructions 732system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions 733system.cpu.iew.iewIQFullEvents 17982 # Number of times the IQ has become full, causing a stall 734system.cpu.iew.iewLSQFullEvents 501480 # Number of times the LSQ has become full, causing a stall 735system.cpu.iew.memOrderViolationEvents 18543 # Number of memory order violations 736system.cpu.iew.predictedTakenIncorrect 317940 # Number of branches that were predicted taken incorrectly 737system.cpu.iew.predictedNotTakenIncorrect 471176 # Number of branches that were predicted not taken incorrectly 738system.cpu.iew.branchMispredicts 789116 # Number of branch mispredicts detected at execute 739system.cpu.iew.iewExecutedInsts 142285522 # Number of executed instructions 740system.cpu.iew.iewExecLoadInsts 25773547 # Number of load instructions executed 741system.cpu.iew.iewExecSquashedInsts 870984 # Number of squashed instructions skipped in execute 742system.cpu.iew.exec_swp 0 # number of swp insts executed 743system.cpu.iew.exec_nop 200932 # number of nop insts executed 744system.cpu.iew.exec_refs 46642466 # number of memory reference insts executed 745system.cpu.iew.exec_branches 26501161 # Number of branches executed 746system.cpu.iew.exec_stores 20868919 # Number of stores executed 747system.cpu.iew.exec_rate 0.510357 # Inst execution rate 748system.cpu.iew.wb_sent 141899022 # cumulative count of insts sent to commit 749system.cpu.iew.wb_count 140130673 # cumulative count of insts written-back 750system.cpu.iew.wb_producers 63222272 # num instructions producing a value 751system.cpu.iew.wb_consumers 95712658 # num instructions consuming a value 752system.cpu.iew.wb_rate 0.502628 # insts written-back per cycle 753system.cpu.iew.wb_fanout 0.660542 # average fanout of values written-back 754system.cpu.commit.commitSquashedInsts 7606616 # The number of squashed insts skipped by commit 755system.cpu.commit.commitNonSpecStalls 1995855 # The number of times commit has been forced to stall to communicate backwards 756system.cpu.commit.branchMispredicts 755952 # The number of times a branch was mispredicted 757system.cpu.commit.committed_per_cycle::samples 267837215 # Number of insts commited each cycle 758system.cpu.commit.committed_per_cycle::mean 0.512660 # Number of insts commited each cycle 759system.cpu.commit.committed_per_cycle::stdev 1.117818 # Number of insts commited each cycle 760system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 761system.cpu.commit.committed_per_cycle::0 194442706 72.60% 72.60% # Number of insts commited each cycle 762system.cpu.commit.committed_per_cycle::1 43232016 16.14% 88.74% # Number of insts commited each cycle 763system.cpu.commit.committed_per_cycle::2 15468771 5.78% 94.51% # Number of insts commited each cycle 764system.cpu.commit.committed_per_cycle::3 4394333 1.64% 96.15% # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::4 6341721 2.37% 98.52% # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::5 1685699 0.63% 99.15% # Number of insts commited each cycle 767system.cpu.commit.committed_per_cycle::6 801066 0.30% 99.45% # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::7 412117 0.15% 99.60% # Number of insts commited each cycle 769system.cpu.commit.committed_per_cycle::8 1058786 0.40% 100.00% # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::total 267837215 # Number of insts commited each cycle 774system.cpu.commit.committedInsts 113234248 # Number of instructions committed 775system.cpu.commit.committedOps 137309439 # Number of ops (including micro ops) committed 776system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 777system.cpu.commit.refs 45486977 # Number of memory references committed 778system.cpu.commit.loads 24898669 # Number of loads committed 779system.cpu.commit.membars 814916 # Number of memory barriers committed 780system.cpu.commit.branches 26015904 # Number of branches committed 781system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. 782system.cpu.commit.int_insts 120139692 # Number of committed integer instructions. 783system.cpu.commit.function_calls 4881505 # Number of function calls committed. 784system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 785system.cpu.commit.op_class_0::IntAlu 91701155 66.78% 66.78% # Class of committed instruction 786system.cpu.commit.op_class_0::IntMult 112732 0.08% 66.87% # Class of committed instruction 787system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 788system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 789system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 790system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 791system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 792system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 793system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 794system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction 795system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction 796system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction 797system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction 798system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction 799system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction 800system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction 801system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction 802system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 803system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 804system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 805system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 806system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 807system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 808system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 809system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 810system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction 811system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 813system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 814system.cpu.commit.op_class_0::MemRead 24898669 18.13% 85.01% # Class of committed instruction 815system.cpu.commit.op_class_0::MemWrite 20588308 14.99% 100.00% # Class of committed instruction 816system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 817system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 818system.cpu.commit.op_class_0::total 137309439 # Class of committed instruction 819system.cpu.commit.bw_lim_events 1058786 # number cycles where commit BW limit reached 820system.cpu.rob.rob_reads 389537878 # The number of ROB reads 821system.cpu.rob.rob_writes 292763814 # The number of ROB writes 822system.cpu.timesIdled 892824 # Number of times that the entire CPU went into an idle state and unscheduled itself 823system.cpu.idleCycles 8024745 # Total number of cycles that the CPU has spent unscheduled due to idling 824system.cpu.quiesceCycles 5387029091 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 825system.cpu.committedInsts 113079343 # Number of Instructions Simulated 826system.cpu.committedOps 137154534 # Number of Ops (including micro ops) Simulated 827system.cpu.cpi 2.465491 # CPI: Cycles Per Instruction 828system.cpu.cpi_total 2.465491 # CPI: Total CPI of All Threads 829system.cpu.ipc 0.405599 # IPC: Instructions Per Cycle 830system.cpu.ipc_total 0.405599 # IPC: Total IPC of All Threads 831system.cpu.int_regfile_reads 155725297 # number of integer regfile reads 832system.cpu.int_regfile_writes 88564293 # number of integer regfile writes 833system.cpu.fp_regfile_reads 9527 # number of floating regfile reads 834system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 835system.cpu.cc_regfile_reads 502644821 # number of cc regfile reads 836system.cpu.cc_regfile_writes 53156150 # number of cc regfile writes 837system.cpu.misc_regfile_reads 348441241 # number of misc regfile reads 838system.cpu.misc_regfile_writes 1521640 # number of misc regfile writes 839system.cpu.dcache.tags.replacements 837355 # number of replacements 840system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use 841system.cpu.dcache.tags.total_refs 40093226 # Total number of references to valid blocks. 842system.cpu.dcache.tags.sampled_refs 837867 # Sample count of references to valid blocks. 843system.cpu.dcache.tags.avg_refs 47.851540 # Average number of references to valid blocks. 844system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 845system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor 846system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 847system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 848system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 849system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 850system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id 851system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id 852system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 853system.cpu.dcache.tags.tag_accesses 179262562 # Number of tag accesses 854system.cpu.dcache.tags.data_accesses 179262562 # Number of data accesses 855system.cpu.dcache.ReadReq_hits::cpu.data 23296906 # number of ReadReq hits 856system.cpu.dcache.ReadReq_hits::total 23296906 # number of ReadReq hits 857system.cpu.dcache.WriteReq_hits::cpu.data 15545467 # number of WriteReq hits 858system.cpu.dcache.WriteReq_hits::total 15545467 # number of WriteReq hits 859system.cpu.dcache.SoftPFReq_hits::cpu.data 345973 # number of SoftPFReq hits 860system.cpu.dcache.SoftPFReq_hits::total 345973 # number of SoftPFReq hits 861system.cpu.dcache.LoadLockedReq_hits::cpu.data 441682 # number of LoadLockedReq hits 862system.cpu.dcache.LoadLockedReq_hits::total 441682 # number of LoadLockedReq hits 863system.cpu.dcache.StoreCondReq_hits::cpu.data 460325 # number of StoreCondReq hits 864system.cpu.dcache.StoreCondReq_hits::total 460325 # number of StoreCondReq hits 865system.cpu.dcache.demand_hits::cpu.data 38842373 # number of demand (read+write) hits 866system.cpu.dcache.demand_hits::total 38842373 # number of demand (read+write) hits 867system.cpu.dcache.overall_hits::cpu.data 39188346 # number of overall hits 868system.cpu.dcache.overall_hits::total 39188346 # number of overall hits 869system.cpu.dcache.ReadReq_misses::cpu.data 708692 # number of ReadReq misses 870system.cpu.dcache.ReadReq_misses::total 708692 # number of ReadReq misses 871system.cpu.dcache.WriteReq_misses::cpu.data 3602140 # number of WriteReq misses 872system.cpu.dcache.WriteReq_misses::total 3602140 # number of WriteReq misses 873system.cpu.dcache.SoftPFReq_misses::cpu.data 177879 # number of SoftPFReq misses 874system.cpu.dcache.SoftPFReq_misses::total 177879 # number of SoftPFReq misses 875system.cpu.dcache.LoadLockedReq_misses::cpu.data 27097 # number of LoadLockedReq misses 876system.cpu.dcache.LoadLockedReq_misses::total 27097 # number of LoadLockedReq misses 877system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses 878system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses 879system.cpu.dcache.demand_misses::cpu.data 4310832 # number of demand (read+write) misses 880system.cpu.dcache.demand_misses::total 4310832 # number of demand (read+write) misses 881system.cpu.dcache.overall_misses::cpu.data 4488711 # number of overall misses 882system.cpu.dcache.overall_misses::total 4488711 # number of overall misses 883system.cpu.dcache.ReadReq_miss_latency::cpu.data 11726844500 # number of ReadReq miss cycles 884system.cpu.dcache.ReadReq_miss_latency::total 11726844500 # number of ReadReq miss cycles 885system.cpu.dcache.WriteReq_miss_latency::cpu.data 232349107178 # number of WriteReq miss cycles 886system.cpu.dcache.WriteReq_miss_latency::total 232349107178 # number of WriteReq miss cycles 887system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373049000 # number of LoadLockedReq miss cycles 888system.cpu.dcache.LoadLockedReq_miss_latency::total 373049000 # number of LoadLockedReq miss cycles 889system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305000 # number of StoreCondReq miss cycles 890system.cpu.dcache.StoreCondReq_miss_latency::total 305000 # number of StoreCondReq miss cycles 891system.cpu.dcache.demand_miss_latency::cpu.data 244075951678 # number of demand (read+write) miss cycles 892system.cpu.dcache.demand_miss_latency::total 244075951678 # number of demand (read+write) miss cycles 893system.cpu.dcache.overall_miss_latency::cpu.data 244075951678 # number of overall miss cycles 894system.cpu.dcache.overall_miss_latency::total 244075951678 # number of overall miss cycles 895system.cpu.dcache.ReadReq_accesses::cpu.data 24005598 # number of ReadReq accesses(hits+misses) 896system.cpu.dcache.ReadReq_accesses::total 24005598 # number of ReadReq accesses(hits+misses) 897system.cpu.dcache.WriteReq_accesses::cpu.data 19147607 # number of WriteReq accesses(hits+misses) 898system.cpu.dcache.WriteReq_accesses::total 19147607 # number of WriteReq accesses(hits+misses) 899system.cpu.dcache.SoftPFReq_accesses::cpu.data 523852 # number of SoftPFReq accesses(hits+misses) 900system.cpu.dcache.SoftPFReq_accesses::total 523852 # number of SoftPFReq accesses(hits+misses) 901system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468779 # number of LoadLockedReq accesses(hits+misses) 902system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses) 903system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses) 904system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses) 905system.cpu.dcache.demand_accesses::cpu.data 43153205 # number of demand (read+write) accesses 906system.cpu.dcache.demand_accesses::total 43153205 # number of demand (read+write) accesses 907system.cpu.dcache.overall_accesses::cpu.data 43677057 # number of overall (read+write) accesses 908system.cpu.dcache.overall_accesses::total 43677057 # number of overall (read+write) accesses 909system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029522 # miss rate for ReadReq accesses 910system.cpu.dcache.ReadReq_miss_rate::total 0.029522 # miss rate for ReadReq accesses 911system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188125 # miss rate for WriteReq accesses 912system.cpu.dcache.WriteReq_miss_rate::total 0.188125 # miss rate for WriteReq accesses 913system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339560 # miss rate for SoftPFReq accesses 914system.cpu.dcache.SoftPFReq_miss_rate::total 0.339560 # miss rate for SoftPFReq accesses 915system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057803 # miss rate for LoadLockedReq accesses 916system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057803 # miss rate for LoadLockedReq accesses 917system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000015 # miss rate for StoreCondReq accesses 918system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses 919system.cpu.dcache.demand_miss_rate::cpu.data 0.099896 # miss rate for demand accesses 920system.cpu.dcache.demand_miss_rate::total 0.099896 # miss rate for demand accesses 921system.cpu.dcache.overall_miss_rate::cpu.data 0.102770 # miss rate for overall accesses 922system.cpu.dcache.overall_miss_rate::total 0.102770 # miss rate for overall accesses 923system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.166470 # average ReadReq miss latency 924system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.166470 # average ReadReq miss latency 925system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64503.075166 # average WriteReq miss latency 926system.cpu.dcache.WriteReq_avg_miss_latency::total 64503.075166 # average WriteReq miss latency 927system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13767.169797 # average LoadLockedReq miss latency 928system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13767.169797 # average LoadLockedReq miss latency 929system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571 # average StoreCondReq miss latency 930system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571 # average StoreCondReq miss latency 931system.cpu.dcache.demand_avg_miss_latency::cpu.data 56619.221458 # average overall miss latency 932system.cpu.dcache.demand_avg_miss_latency::total 56619.221458 # average overall miss latency 933system.cpu.dcache.overall_avg_miss_latency::cpu.data 54375.510403 # average overall miss latency 934system.cpu.dcache.overall_avg_miss_latency::total 54375.510403 # average overall miss latency 935system.cpu.dcache.blocked_cycles::no_mshrs 870696 # number of cycles access was blocked 936system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 937system.cpu.dcache.blocked::no_mshrs 6851 # number of cycles access was blocked 938system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 939system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.090352 # average number of cycles each access was blocked 940system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 941system.cpu.dcache.fast_writes 0 # number of fast writes performed 942system.cpu.dcache.cache_copies 0 # number of cache copies performed 943system.cpu.dcache.writebacks::writebacks 695416 # number of writebacks 944system.cpu.dcache.writebacks::total 695416 # number of writebacks 945system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295634 # number of ReadReq MSHR hits 946system.cpu.dcache.ReadReq_mshr_hits::total 295634 # number of ReadReq MSHR hits 947system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302552 # number of WriteReq MSHR hits 948system.cpu.dcache.WriteReq_mshr_hits::total 3302552 # number of WriteReq MSHR hits 949system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18703 # number of LoadLockedReq MSHR hits 950system.cpu.dcache.LoadLockedReq_mshr_hits::total 18703 # number of LoadLockedReq MSHR hits 951system.cpu.dcache.demand_mshr_hits::cpu.data 3598186 # number of demand (read+write) MSHR hits 952system.cpu.dcache.demand_mshr_hits::total 3598186 # number of demand (read+write) MSHR hits 953system.cpu.dcache.overall_mshr_hits::cpu.data 3598186 # number of overall MSHR hits 954system.cpu.dcache.overall_mshr_hits::total 3598186 # number of overall MSHR hits 955system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413058 # number of ReadReq MSHR misses 956system.cpu.dcache.ReadReq_mshr_misses::total 413058 # number of ReadReq MSHR misses 957system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299588 # number of WriteReq MSHR misses 958system.cpu.dcache.WriteReq_mshr_misses::total 299588 # number of WriteReq MSHR misses 959system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119604 # number of SoftPFReq MSHR misses 960system.cpu.dcache.SoftPFReq_mshr_misses::total 119604 # number of SoftPFReq MSHR misses 961system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8394 # number of LoadLockedReq MSHR misses 962system.cpu.dcache.LoadLockedReq_mshr_misses::total 8394 # number of LoadLockedReq MSHR misses 963system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses 964system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses 965system.cpu.dcache.demand_mshr_misses::cpu.data 712646 # number of demand (read+write) MSHR misses 966system.cpu.dcache.demand_mshr_misses::total 712646 # number of demand (read+write) MSHR misses 967system.cpu.dcache.overall_mshr_misses::cpu.data 832250 # number of overall MSHR misses 968system.cpu.dcache.overall_mshr_misses::total 832250 # number of overall MSHR misses 969system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 970system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable 971system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 972system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 973system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 974system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 975system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391901000 # number of ReadReq MSHR miss cycles 976system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391901000 # number of ReadReq MSHR miss cycles 977system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972155480 # number of WriteReq MSHR miss cycles 978system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972155480 # number of WriteReq MSHR miss cycles 979system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1700460500 # number of SoftPFReq MSHR miss cycles 980system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1700460500 # number of SoftPFReq MSHR miss cycles 981system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126799500 # number of LoadLockedReq MSHR miss cycles 982system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126799500 # number of LoadLockedReq MSHR miss cycles 983system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles 984system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles 985system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26364056480 # number of demand (read+write) MSHR miss cycles 986system.cpu.dcache.demand_mshr_miss_latency::total 26364056480 # number of demand (read+write) MSHR miss cycles 987system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064516980 # number of overall MSHR miss cycles 988system.cpu.dcache.overall_mshr_miss_latency::total 28064516980 # number of overall MSHR miss cycles 989system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276327500 # number of ReadReq MSHR uncacheable cycles 990system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276327500 # number of ReadReq MSHR uncacheable cycles 991system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075770951 # number of WriteReq MSHR uncacheable cycles 992system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075770951 # number of WriteReq MSHR uncacheable cycles 993system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098451 # number of overall MSHR uncacheable cycles 994system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098451 # number of overall MSHR uncacheable cycles 995system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017207 # mshr miss rate for ReadReq accesses 996system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017207 # mshr miss rate for ReadReq accesses 997system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015646 # mshr miss rate for WriteReq accesses 998system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015646 # mshr miss rate for WriteReq accesses 999system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228316 # mshr miss rate for SoftPFReq accesses 1000system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228316 # mshr miss rate for SoftPFReq accesses 1001system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017906 # mshr miss rate for LoadLockedReq accesses 1002system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017906 # mshr miss rate for LoadLockedReq accesses 1003system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses 1004system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses 1005system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016514 # mshr miss rate for demand accesses 1006system.cpu.dcache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses 1007system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019055 # mshr miss rate for overall accesses 1008system.cpu.dcache.overall_mshr_miss_rate::total 0.019055 # mshr miss rate for overall accesses 1009system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15474.584683 # average ReadReq mshr miss latency 1010system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15474.584683 # average ReadReq mshr miss latency 1011system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66665.405423 # average WriteReq mshr miss latency 1012system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66665.405423 # average WriteReq mshr miss latency 1013system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.421658 # average SoftPFReq mshr miss latency 1014system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.421658 # average SoftPFReq mshr miss latency 1015system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15105.968549 # average LoadLockedReq mshr miss latency 1016system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15105.968549 # average LoadLockedReq mshr miss latency 1017system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency 1018system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency 1019system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36994.603885 # average overall mshr miss latency 1020system.cpu.dcache.demand_avg_mshr_miss_latency::total 36994.603885 # average overall mshr miss latency 1021system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33721.258011 # average overall mshr miss latency 1022system.cpu.dcache.overall_avg_mshr_miss_latency::total 33721.258011 # average overall mshr miss latency 1023system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.164894 # average ReadReq mshr uncacheable latency 1024system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.164894 # average ReadReq mshr uncacheable latency 1025system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184004.747181 # average WriteReq mshr uncacheable latency 1026system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184004.747181 # average WriteReq mshr uncacheable latency 1027system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.683329 # average overall mshr uncacheable latency 1028system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.683329 # average overall mshr uncacheable latency 1029system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1030system.cpu.icache.tags.replacements 1886675 # number of replacements 1031system.cpu.icache.tags.tagsinuse 511.154168 # Cycle average of tags in use 1032system.cpu.icache.tags.total_refs 64239376 # Total number of references to valid blocks. 1033system.cpu.icache.tags.sampled_refs 1887187 # Sample count of references to valid blocks. 1034system.cpu.icache.tags.avg_refs 34.039751 # Average number of references to valid blocks. 1035system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit. 1036system.cpu.icache.tags.occ_blocks::cpu.inst 511.154168 # Average occupied blocks per requestor 1037system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy 1038system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy 1039system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1040system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 1041system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id 1042system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1043system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1044system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1045system.cpu.icache.tags.tag_accesses 68105664 # Number of tag accesses 1046system.cpu.icache.tags.data_accesses 68105664 # Number of data accesses 1047system.cpu.icache.ReadReq_hits::cpu.inst 64239376 # number of ReadReq hits 1048system.cpu.icache.ReadReq_hits::total 64239376 # number of ReadReq hits 1049system.cpu.icache.demand_hits::cpu.inst 64239376 # number of demand (read+write) hits 1050system.cpu.icache.demand_hits::total 64239376 # number of demand (read+write) hits 1051system.cpu.icache.overall_hits::cpu.inst 64239376 # number of overall hits 1052system.cpu.icache.overall_hits::total 64239376 # number of overall hits 1053system.cpu.icache.ReadReq_misses::cpu.inst 1979079 # number of ReadReq misses 1054system.cpu.icache.ReadReq_misses::total 1979079 # number of ReadReq misses 1055system.cpu.icache.demand_misses::cpu.inst 1979079 # number of demand (read+write) misses 1056system.cpu.icache.demand_misses::total 1979079 # number of demand (read+write) misses 1057system.cpu.icache.overall_misses::cpu.inst 1979079 # number of overall misses 1058system.cpu.icache.overall_misses::total 1979079 # number of overall misses 1059system.cpu.icache.ReadReq_miss_latency::cpu.inst 28144068491 # number of ReadReq miss cycles 1060system.cpu.icache.ReadReq_miss_latency::total 28144068491 # number of ReadReq miss cycles 1061system.cpu.icache.demand_miss_latency::cpu.inst 28144068491 # number of demand (read+write) miss cycles 1062system.cpu.icache.demand_miss_latency::total 28144068491 # number of demand (read+write) miss cycles 1063system.cpu.icache.overall_miss_latency::cpu.inst 28144068491 # number of overall miss cycles 1064system.cpu.icache.overall_miss_latency::total 28144068491 # number of overall miss cycles 1065system.cpu.icache.ReadReq_accesses::cpu.inst 66218455 # number of ReadReq accesses(hits+misses) 1066system.cpu.icache.ReadReq_accesses::total 66218455 # number of ReadReq accesses(hits+misses) 1067system.cpu.icache.demand_accesses::cpu.inst 66218455 # number of demand (read+write) accesses 1068system.cpu.icache.demand_accesses::total 66218455 # number of demand (read+write) accesses 1069system.cpu.icache.overall_accesses::cpu.inst 66218455 # number of overall (read+write) accesses 1070system.cpu.icache.overall_accesses::total 66218455 # number of overall (read+write) accesses 1071system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029887 # miss rate for ReadReq accesses 1072system.cpu.icache.ReadReq_miss_rate::total 0.029887 # miss rate for ReadReq accesses 1073system.cpu.icache.demand_miss_rate::cpu.inst 0.029887 # miss rate for demand accesses 1074system.cpu.icache.demand_miss_rate::total 0.029887 # miss rate for demand accesses 1075system.cpu.icache.overall_miss_rate::cpu.inst 0.029887 # miss rate for overall accesses 1076system.cpu.icache.overall_miss_rate::total 0.029887 # miss rate for overall accesses 1077system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14220.790828 # average ReadReq miss latency 1078system.cpu.icache.ReadReq_avg_miss_latency::total 14220.790828 # average ReadReq miss latency 1079system.cpu.icache.demand_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency 1080system.cpu.icache.demand_avg_miss_latency::total 14220.790828 # average overall miss latency 1081system.cpu.icache.overall_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency 1082system.cpu.icache.overall_avg_miss_latency::total 14220.790828 # average overall miss latency 1083system.cpu.icache.blocked_cycles::no_mshrs 5080 # number of cycles access was blocked 1084system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1085system.cpu.icache.blocked::no_mshrs 162 # number of cycles access was blocked 1086system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1087system.cpu.icache.avg_blocked_cycles::no_mshrs 31.358025 # average number of cycles each access was blocked 1088system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1089system.cpu.icache.fast_writes 0 # number of fast writes performed 1090system.cpu.icache.cache_copies 0 # number of cache copies performed 1091system.cpu.icache.writebacks::writebacks 1886675 # number of writebacks 1092system.cpu.icache.writebacks::total 1886675 # number of writebacks 1093system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91868 # number of ReadReq MSHR hits 1094system.cpu.icache.ReadReq_mshr_hits::total 91868 # number of ReadReq MSHR hits 1095system.cpu.icache.demand_mshr_hits::cpu.inst 91868 # number of demand (read+write) MSHR hits 1096system.cpu.icache.demand_mshr_hits::total 91868 # number of demand (read+write) MSHR hits 1097system.cpu.icache.overall_mshr_hits::cpu.inst 91868 # number of overall MSHR hits 1098system.cpu.icache.overall_mshr_hits::total 91868 # number of overall MSHR hits 1099system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887211 # number of ReadReq MSHR misses 1100system.cpu.icache.ReadReq_mshr_misses::total 1887211 # number of ReadReq MSHR misses 1101system.cpu.icache.demand_mshr_misses::cpu.inst 1887211 # number of demand (read+write) MSHR misses 1102system.cpu.icache.demand_mshr_misses::total 1887211 # number of demand (read+write) MSHR misses 1103system.cpu.icache.overall_mshr_misses::cpu.inst 1887211 # number of overall MSHR misses 1104system.cpu.icache.overall_mshr_misses::total 1887211 # number of overall MSHR misses 1105system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable 1106system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable 1107system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses 1108system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses 1109system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25180995493 # number of ReadReq MSHR miss cycles 1110system.cpu.icache.ReadReq_mshr_miss_latency::total 25180995493 # number of ReadReq MSHR miss cycles 1111system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25180995493 # number of demand (read+write) MSHR miss cycles 1112system.cpu.icache.demand_mshr_miss_latency::total 25180995493 # number of demand (read+write) MSHR miss cycles 1113system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25180995493 # number of overall MSHR miss cycles 1114system.cpu.icache.overall_mshr_miss_latency::total 25180995493 # number of overall MSHR miss cycles 1115system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377667500 # number of ReadReq MSHR uncacheable cycles 1116system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377667500 # number of ReadReq MSHR uncacheable cycles 1117system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377667500 # number of overall MSHR uncacheable cycles 1118system.cpu.icache.overall_mshr_uncacheable_latency::total 377667500 # number of overall MSHR uncacheable cycles 1119system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028500 # mshr miss rate for ReadReq accesses 1120system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028500 # mshr miss rate for ReadReq accesses 1121system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028500 # mshr miss rate for demand accesses 1122system.cpu.icache.demand_mshr_miss_rate::total 0.028500 # mshr miss rate for demand accesses 1123system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028500 # mshr miss rate for overall accesses 1124system.cpu.icache.overall_mshr_miss_rate::total 0.028500 # mshr miss rate for overall accesses 1125system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13342.967741 # average ReadReq mshr miss latency 1126system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13342.967741 # average ReadReq mshr miss latency 1127system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13342.967741 # average overall mshr miss latency 1128system.cpu.icache.demand_avg_mshr_miss_latency::total 13342.967741 # average overall mshr miss latency 1129system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13342.967741 # average overall mshr miss latency 1130system.cpu.icache.overall_avg_mshr_miss_latency::total 13342.967741 # average overall mshr miss latency 1131system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average ReadReq mshr uncacheable latency 1132system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949 # average ReadReq mshr uncacheable latency 1133system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average overall mshr uncacheable latency 1134system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949 # average overall mshr uncacheable latency 1135system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1136system.cpu.l2cache.tags.replacements 96487 # number of replacements 1137system.cpu.l2cache.tags.tagsinuse 65023.312748 # Cycle average of tags in use 1138system.cpu.l2cache.tags.total_refs 4997676 # Total number of references to valid blocks. 1139system.cpu.l2cache.tags.sampled_refs 161725 # Sample count of references to valid blocks. 1140system.cpu.l2cache.tags.avg_refs 30.902309 # Average number of references to valid blocks. 1141system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1142system.cpu.l2cache.tags.occ_blocks::writebacks 49475.678025 # Average occupied blocks per requestor 1143system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.897856 # Average occupied blocks per requestor 1144system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.835471 # Average occupied blocks per requestor 1145system.cpu.l2cache.tags.occ_blocks::cpu.inst 10343.602046 # Average occupied blocks per requestor 1146system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.299351 # Average occupied blocks per requestor 1147system.cpu.l2cache.tags.occ_percent::writebacks 0.754939 # Average percentage of cache occupancy 1148system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy 1149system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000028 # Average percentage of cache occupancy 1150system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157831 # Average percentage of cache occupancy 1151system.cpu.l2cache.tags.occ_percent::cpu.data 0.079213 # Average percentage of cache occupancy 1152system.cpu.l2cache.tags.occ_percent::total 0.992177 # Average percentage of cache occupancy 1153system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id 1154system.cpu.l2cache.tags.occ_task_id_blocks::1024 65226 # Occupied blocks per task id 1155system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 1156system.cpu.l2cache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 1157system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 1158system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id 1159system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6640 # Occupied blocks per task id 1160system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id 1161system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id 1162system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995270 # Percentage of cache occupancy per task id 1163system.cpu.l2cache.tags.tag_accesses 44233161 # Number of tag accesses 1164system.cpu.l2cache.tags.data_accesses 44233161 # Number of data accesses 1165system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54581 # number of ReadReq hits 1166system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11841 # number of ReadReq hits 1167system.cpu.l2cache.ReadReq_hits::total 66422 # number of ReadReq hits 1168system.cpu.l2cache.WritebackDirty_hits::writebacks 695416 # number of WritebackDirty hits 1169system.cpu.l2cache.WritebackDirty_hits::total 695416 # number of WritebackDirty hits 1170system.cpu.l2cache.WritebackClean_hits::writebacks 1846676 # number of WritebackClean hits 1171system.cpu.l2cache.WritebackClean_hits::total 1846676 # number of WritebackClean hits 1172system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits 1173system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits 1174system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits 1175system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits 1176system.cpu.l2cache.ReadExReq_hits::cpu.data 161568 # number of ReadExReq hits 1177system.cpu.l2cache.ReadExReq_hits::total 161568 # number of ReadExReq hits 1178system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867325 # number of ReadCleanReq hits 1179system.cpu.l2cache.ReadCleanReq_hits::total 1867325 # number of ReadCleanReq hits 1180system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527485 # number of ReadSharedReq hits 1181system.cpu.l2cache.ReadSharedReq_hits::total 527485 # number of ReadSharedReq hits 1182system.cpu.l2cache.demand_hits::cpu.dtb.walker 54581 # number of demand (read+write) hits 1183system.cpu.l2cache.demand_hits::cpu.itb.walker 11841 # number of demand (read+write) hits 1184system.cpu.l2cache.demand_hits::cpu.inst 1867325 # number of demand (read+write) hits 1185system.cpu.l2cache.demand_hits::cpu.data 689053 # number of demand (read+write) hits 1186system.cpu.l2cache.demand_hits::total 2622800 # number of demand (read+write) hits 1187system.cpu.l2cache.overall_hits::cpu.dtb.walker 54581 # number of overall hits 1188system.cpu.l2cache.overall_hits::cpu.itb.walker 11841 # number of overall hits 1189system.cpu.l2cache.overall_hits::cpu.inst 1867325 # number of overall hits 1190system.cpu.l2cache.overall_hits::cpu.data 689053 # number of overall hits 1191system.cpu.l2cache.overall_hits::total 2622800 # number of overall hits 1192system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses 1193system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses 1194system.cpu.l2cache.ReadReq_misses::total 29 # number of ReadReq misses 1195system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses 1196system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses 1197system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1198system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1199system.cpu.l2cache.ReadExReq_misses::cpu.data 135393 # number of ReadExReq misses 1200system.cpu.l2cache.ReadExReq_misses::total 135393 # number of ReadExReq misses 1201system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19844 # number of ReadCleanReq misses 1202system.cpu.l2cache.ReadCleanReq_misses::total 19844 # number of ReadCleanReq misses 1203system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13444 # number of ReadSharedReq misses 1204system.cpu.l2cache.ReadSharedReq_misses::total 13444 # number of ReadSharedReq misses 1205system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses 1206system.cpu.l2cache.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses 1207system.cpu.l2cache.demand_misses::cpu.inst 19844 # number of demand (read+write) misses 1208system.cpu.l2cache.demand_misses::cpu.data 148837 # number of demand (read+write) misses 1209system.cpu.l2cache.demand_misses::total 168710 # number of demand (read+write) misses 1210system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses 1211system.cpu.l2cache.overall_misses::cpu.itb.walker 8 # number of overall misses 1212system.cpu.l2cache.overall_misses::cpu.inst 19844 # number of overall misses 1213system.cpu.l2cache.overall_misses::cpu.data 148837 # number of overall misses 1214system.cpu.l2cache.overall_misses::total 168710 # number of overall misses 1215system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3081000 # number of ReadReq miss cycles 1216system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1062000 # number of ReadReq miss cycles 1217system.cpu.l2cache.ReadReq_miss_latency::total 4143000 # number of ReadReq miss cycles 1218system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2179500 # number of UpgradeReq miss cycles 1219system.cpu.l2cache.UpgradeReq_miss_latency::total 2179500 # number of UpgradeReq miss cycles 1220system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 1221system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 1222system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17603720000 # number of ReadExReq miss cycles 1223system.cpu.l2cache.ReadExReq_miss_latency::total 17603720000 # number of ReadExReq miss cycles 1224system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2626422000 # number of ReadCleanReq miss cycles 1225system.cpu.l2cache.ReadCleanReq_miss_latency::total 2626422000 # number of ReadCleanReq miss cycles 1226system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1819515000 # number of ReadSharedReq miss cycles 1227system.cpu.l2cache.ReadSharedReq_miss_latency::total 1819515000 # number of ReadSharedReq miss cycles 1228system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3081000 # number of demand (read+write) miss cycles 1229system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1062000 # number of demand (read+write) miss cycles 1230system.cpu.l2cache.demand_miss_latency::cpu.inst 2626422000 # number of demand (read+write) miss cycles 1231system.cpu.l2cache.demand_miss_latency::cpu.data 19423235000 # number of demand (read+write) miss cycles 1232system.cpu.l2cache.demand_miss_latency::total 22053800000 # number of demand (read+write) miss cycles 1233system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3081000 # number of overall miss cycles 1234system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1062000 # number of overall miss cycles 1235system.cpu.l2cache.overall_miss_latency::cpu.inst 2626422000 # number of overall miss cycles 1236system.cpu.l2cache.overall_miss_latency::cpu.data 19423235000 # number of overall miss cycles 1237system.cpu.l2cache.overall_miss_latency::total 22053800000 # number of overall miss cycles 1238system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54602 # number of ReadReq accesses(hits+misses) 1239system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11849 # number of ReadReq accesses(hits+misses) 1240system.cpu.l2cache.ReadReq_accesses::total 66451 # number of ReadReq accesses(hits+misses) 1241system.cpu.l2cache.WritebackDirty_accesses::writebacks 695416 # number of WritebackDirty accesses(hits+misses) 1242system.cpu.l2cache.WritebackDirty_accesses::total 695416 # number of WritebackDirty accesses(hits+misses) 1243system.cpu.l2cache.WritebackClean_accesses::writebacks 1846676 # number of WritebackClean accesses(hits+misses) 1244system.cpu.l2cache.WritebackClean_accesses::total 1846676 # number of WritebackClean accesses(hits+misses) 1245system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2754 # number of UpgradeReq accesses(hits+misses) 1246system.cpu.l2cache.UpgradeReq_accesses::total 2754 # number of UpgradeReq accesses(hits+misses) 1247system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) 1248system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) 1249system.cpu.l2cache.ReadExReq_accesses::cpu.data 296961 # number of ReadExReq accesses(hits+misses) 1250system.cpu.l2cache.ReadExReq_accesses::total 296961 # number of ReadExReq accesses(hits+misses) 1251system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887169 # number of ReadCleanReq accesses(hits+misses) 1252system.cpu.l2cache.ReadCleanReq_accesses::total 1887169 # number of ReadCleanReq accesses(hits+misses) 1253system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 540929 # number of ReadSharedReq accesses(hits+misses) 1254system.cpu.l2cache.ReadSharedReq_accesses::total 540929 # number of ReadSharedReq accesses(hits+misses) 1255system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54602 # number of demand (read+write) accesses 1256system.cpu.l2cache.demand_accesses::cpu.itb.walker 11849 # number of demand (read+write) accesses 1257system.cpu.l2cache.demand_accesses::cpu.inst 1887169 # number of demand (read+write) accesses 1258system.cpu.l2cache.demand_accesses::cpu.data 837890 # number of demand (read+write) accesses 1259system.cpu.l2cache.demand_accesses::total 2791510 # number of demand (read+write) accesses 1260system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54602 # number of overall (read+write) accesses 1261system.cpu.l2cache.overall_accesses::cpu.itb.walker 11849 # number of overall (read+write) accesses 1262system.cpu.l2cache.overall_accesses::cpu.inst 1887169 # number of overall (read+write) accesses 1263system.cpu.l2cache.overall_accesses::cpu.data 837890 # number of overall (read+write) accesses 1264system.cpu.l2cache.overall_accesses::total 2791510 # number of overall (read+write) accesses 1265system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000385 # miss rate for ReadReq accesses 1266system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000675 # miss rate for ReadReq accesses 1267system.cpu.l2cache.ReadReq_miss_rate::total 0.000436 # miss rate for ReadReq accesses 1268system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988017 # miss rate for UpgradeReq accesses 1269system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988017 # miss rate for UpgradeReq accesses 1270system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses 1271system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses 1272system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455929 # miss rate for ReadExReq accesses 1273system.cpu.l2cache.ReadExReq_miss_rate::total 0.455929 # miss rate for ReadExReq accesses 1274system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010515 # miss rate for ReadCleanReq accesses 1275system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010515 # miss rate for ReadCleanReq accesses 1276system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024854 # miss rate for ReadSharedReq accesses 1277system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024854 # miss rate for ReadSharedReq accesses 1278system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000385 # miss rate for demand accesses 1279system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000675 # miss rate for demand accesses 1280system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010515 # miss rate for demand accesses 1281system.cpu.l2cache.demand_miss_rate::cpu.data 0.177633 # miss rate for demand accesses 1282system.cpu.l2cache.demand_miss_rate::total 0.060437 # miss rate for demand accesses 1283system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000385 # miss rate for overall accesses 1284system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000675 # miss rate for overall accesses 1285system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010515 # miss rate for overall accesses 1286system.cpu.l2cache.overall_miss_rate::cpu.data 0.177633 # miss rate for overall accesses 1287system.cpu.l2cache.overall_miss_rate::total 0.060437 # miss rate for overall accesses 1288system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 146714.285714 # average ReadReq miss latency 1289system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132750 # average ReadReq miss latency 1290system.cpu.l2cache.ReadReq_avg_miss_latency::total 142862.068966 # average ReadReq miss latency 1291system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 800.992282 # average UpgradeReq miss latency 1292system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 800.992282 # average UpgradeReq miss latency 1293system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency 1294system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency 1295system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130019.424933 # average ReadExReq miss latency 1296system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130019.424933 # average ReadExReq miss latency 1297system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132353.456964 # average ReadCleanReq miss latency 1298system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132353.456964 # average ReadCleanReq miss latency 1299system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135340.300506 # average ReadSharedReq miss latency 1300system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135340.300506 # average ReadSharedReq miss latency 1301system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 146714.285714 # average overall miss latency 1302system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency 1303system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency 1304system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency 1305system.cpu.l2cache.demand_avg_miss_latency::total 130720.170707 # average overall miss latency 1306system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 146714.285714 # average overall miss latency 1307system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency 1308system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency 1309system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency 1310system.cpu.l2cache.overall_avg_miss_latency::total 130720.170707 # average overall miss latency 1311system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1312system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1313system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1314system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1315system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1316system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1317system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1318system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1319system.cpu.l2cache.writebacks::writebacks 88798 # number of writebacks 1320system.cpu.l2cache.writebacks::total 88798 # number of writebacks 1321system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits 1322system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits 1323system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits 1324system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits 1325system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits 1326system.cpu.l2cache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits 1327system.cpu.l2cache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits 1328system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits 1329system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits 1330system.cpu.l2cache.overall_mshr_hits::total 139 # number of overall MSHR hits 1331system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses 1332system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8 # number of ReadReq MSHR misses 1333system.cpu.l2cache.ReadReq_mshr_misses::total 29 # number of ReadReq MSHR misses 1334system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses 1335system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses 1336system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1337system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1338system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135393 # number of ReadExReq MSHR misses 1339system.cpu.l2cache.ReadExReq_mshr_misses::total 135393 # number of ReadExReq MSHR misses 1340system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19818 # number of ReadCleanReq MSHR misses 1341system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19818 # number of ReadCleanReq MSHR misses 1342system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13331 # number of ReadSharedReq MSHR misses 1343system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13331 # number of ReadSharedReq MSHR misses 1344system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses 1345system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8 # number of demand (read+write) MSHR misses 1346system.cpu.l2cache.demand_mshr_misses::cpu.inst 19818 # number of demand (read+write) MSHR misses 1347system.cpu.l2cache.demand_mshr_misses::cpu.data 148724 # number of demand (read+write) MSHR misses 1348system.cpu.l2cache.demand_mshr_misses::total 168571 # number of demand (read+write) MSHR misses 1349system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses 1350system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8 # number of overall MSHR misses 1351system.cpu.l2cache.overall_mshr_misses::cpu.inst 19818 # number of overall MSHR misses 1352system.cpu.l2cache.overall_mshr_misses::cpu.data 148724 # number of overall MSHR misses 1353system.cpu.l2cache.overall_mshr_misses::total 168571 # number of overall MSHR misses 1354system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable 1355system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 1356system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34133 # number of ReadReq MSHR uncacheable 1357system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1358system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 1359system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses 1360system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1361system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61718 # number of overall MSHR uncacheable misses 1362system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2871000 # number of ReadReq MSHR miss cycles 1363system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 982000 # number of ReadReq MSHR miss cycles 1364system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3853000 # number of ReadReq MSHR miss cycles 1365system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192556500 # number of UpgradeReq MSHR miss cycles 1366system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192556500 # number of UpgradeReq MSHR miss cycles 1367system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212500 # number of SCUpgradeReq MSHR miss cycles 1368system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212500 # number of SCUpgradeReq MSHR miss cycles 1369system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16249790000 # number of ReadExReq MSHR miss cycles 1370system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16249790000 # number of ReadExReq MSHR miss cycles 1371system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425294500 # number of ReadCleanReq MSHR miss cycles 1372system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425294500 # number of ReadCleanReq MSHR miss cycles 1373system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1672223500 # number of ReadSharedReq MSHR miss cycles 1374system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1672223500 # number of ReadSharedReq MSHR miss cycles 1375system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2871000 # number of demand (read+write) MSHR miss cycles 1376system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 982000 # number of demand (read+write) MSHR miss cycles 1377system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2425294500 # number of demand (read+write) MSHR miss cycles 1378system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17922013500 # number of demand (read+write) MSHR miss cycles 1379system.cpu.l2cache.demand_mshr_miss_latency::total 20351161000 # number of demand (read+write) MSHR miss cycles 1380system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2871000 # number of overall MSHR miss cycles 1381system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 982000 # number of overall MSHR miss cycles 1382system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425294500 # number of overall MSHR miss cycles 1383system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17922013500 # number of overall MSHR miss cycles 1384system.cpu.l2cache.overall_mshr_miss_latency::total 20351161000 # number of overall MSHR miss cycles 1385system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles 1386system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887205500 # number of ReadReq MSHR uncacheable cycles 1387system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227322500 # number of ReadReq MSHR uncacheable cycles 1388system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756953000 # number of WriteReq MSHR uncacheable cycles 1389system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756953000 # number of WriteReq MSHR uncacheable cycles 1390system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles 1391system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644158500 # number of overall MSHR uncacheable cycles 1392system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984275500 # number of overall MSHR uncacheable cycles 1393system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for ReadReq accesses 1394system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses 1395system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000436 # mshr miss rate for ReadReq accesses 1396system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988017 # mshr miss rate for UpgradeReq accesses 1397system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988017 # mshr miss rate for UpgradeReq accesses 1398system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses 1399system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses 1400system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455929 # mshr miss rate for ReadExReq accesses 1401system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455929 # mshr miss rate for ReadExReq accesses 1402system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for ReadCleanReq accesses 1403system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010501 # mshr miss rate for ReadCleanReq accesses 1404system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024645 # mshr miss rate for ReadSharedReq accesses 1405system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024645 # mshr miss rate for ReadSharedReq accesses 1406system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for demand accesses 1407system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses 1408system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for demand accesses 1409system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for demand accesses 1410system.cpu.l2cache.demand_mshr_miss_rate::total 0.060387 # mshr miss rate for demand accesses 1411system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for overall accesses 1412system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses 1413system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for overall accesses 1414system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for overall accesses 1415system.cpu.l2cache.overall_mshr_miss_rate::total 0.060387 # mshr miss rate for overall accesses 1416system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average ReadReq mshr miss latency 1417system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency 1418system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966 # average ReadReq mshr miss latency 1419system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70766.813671 # average UpgradeReq mshr miss latency 1420system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70766.813671 # average UpgradeReq mshr miss latency 1421system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency 1422system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency 1423system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120019.424933 # average ReadExReq mshr miss latency 1424system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120019.424933 # average ReadExReq mshr miss latency 1425system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122378.368150 # average ReadCleanReq mshr miss latency 1426system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122378.368150 # average ReadCleanReq mshr miss latency 1427system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125438.714275 # average ReadSharedReq mshr miss latency 1428system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125438.714275 # average ReadSharedReq mshr miss latency 1429system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency 1430system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency 1431system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency 1432system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency 1433system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency 1434system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency 1435system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency 1436system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency 1437system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency 1438system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency 1439system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency 1440system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.859713 # average ReadReq mshr uncacheable latency 1441system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.870536 # average ReadReq mshr uncacheable latency 1442system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.090810 # average WriteReq mshr uncacheable latency 1443system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.090810 # average WriteReq mshr uncacheable latency 1444system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency 1445system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.253228 # average overall mshr uncacheable latency 1446system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.234129 # average overall mshr uncacheable latency 1447system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1448system.cpu.toL2Bus.snoop_filter.tot_requests 5483387 # Total number of requests made to the snoop filter. 1449system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758318 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1450system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1451system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. 1452system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1453system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1454system.cpu.toL2Bus.trans_dist::ReadReq 128004 # Transaction distribution 1455system.cpu.toL2Bus.trans_dist::ReadResp 2556278 # Transaction distribution 1456system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1457system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1458system.cpu.toL2Bus.trans_dist::WritebackDirty 820384 # Transaction distribution 1459system.cpu.toL2Bus.trans_dist::WritebackClean 1846676 # Transaction distribution 1460system.cpu.toL2Bus.trans_dist::CleanEvict 142776 # Transaction distribution 1461system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution 1462system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution 1463system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution 1464system.cpu.toL2Bus.trans_dist::ReadExReq 296961 # Transaction distribution 1465system.cpu.toL2Bus.trans_dist::ReadExResp 296961 # Transaction distribution 1466system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887211 # Transaction distribution 1467system.cpu.toL2Bus.trans_dist::ReadSharedReq 541178 # Transaction distribution 1468system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution 1469system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627062 # Packet count per connected master and slave (bytes) 1470system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629120 # Packet count per connected master and slave (bytes) 1471system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31258 # Packet count per connected master and slave (bytes) 1472system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129064 # Packet count per connected master and slave (bytes) 1473system.cpu.toL2Bus.pkt_count::total 8416504 # Packet count per connected master and slave (bytes) 1474system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239014016 # Cumulative packet size per connected master and slave (bytes) 1475system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323369 # Cumulative packet size per connected master and slave (bytes) 1476system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47396 # Cumulative packet size per connected master and slave (bytes) 1477system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218408 # Cumulative packet size per connected master and slave (bytes) 1478system.cpu.toL2Bus.pkt_size::total 337603189 # Cumulative packet size per connected master and slave (bytes) 1479system.cpu.toL2Bus.snoops 196948 # Total snoops (count) 1480system.cpu.toL2Bus.snoop_fanout::samples 3052801 # Request fanout histogram 1481system.cpu.toL2Bus.snoop_fanout::mean 0.025889 # Request fanout histogram 1482system.cpu.toL2Bus.snoop_fanout::stdev 0.158805 # Request fanout histogram 1483system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1484system.cpu.toL2Bus.snoop_fanout::0 2973766 97.41% 97.41% # Request fanout histogram 1485system.cpu.toL2Bus.snoop_fanout::1 79035 2.59% 100.00% # Request fanout histogram 1486system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1487system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1488system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1489system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1490system.cpu.toL2Bus.snoop_fanout::total 3052801 # Request fanout histogram 1491system.cpu.toL2Bus.reqLayer0.occupancy 5399625997 # Layer occupancy (ticks) 1492system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1493system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks) 1494system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1495system.cpu.toL2Bus.respLayer0.occupancy 2834640846 # Layer occupancy (ticks) 1496system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1497system.cpu.toL2Bus.respLayer1.occupancy 1303359054 # Layer occupancy (ticks) 1498system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1499system.cpu.toL2Bus.respLayer2.occupancy 19415986 # Layer occupancy (ticks) 1500system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1501system.cpu.toL2Bus.respLayer3.occupancy 74513896 # Layer occupancy (ticks) 1502system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1503system.iobus.trans_dist::ReadReq 30198 # Transaction distribution 1504system.iobus.trans_dist::ReadResp 30198 # Transaction distribution 1505system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1506system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1507system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1508system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1509system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1510system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1511system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1512system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1513system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1514system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1515system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1516system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1517system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1518system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1519system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1520system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1521system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1522system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1523system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1524system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1525system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1526system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1527system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) 1528system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1531system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1532system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1533system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1534system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1535system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1536system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1537system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1538system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1539system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1540system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1541system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1542system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1543system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1544system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1545system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1546system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1547system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1548system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1549system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1550system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) 1551system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) 1552system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) 1553system.iobus.reqLayer0.occupancy 43090500 # Layer occupancy (ticks) 1554system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1555system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks) 1556system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1557system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) 1558system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1559system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) 1560system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1561system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) 1562system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1563system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) 1564system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1565system.iobus.reqLayer8.occupancy 648000 # Layer occupancy (ticks) 1566system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1567system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1568system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1569system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) 1570system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1571system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 1572system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1573system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 1574system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1575system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 1576system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1577system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 1578system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1579system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) 1580system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1581system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1582system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1583system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 1584system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1585system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 1586system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1587system.iobus.reqLayer23.occupancy 6193500 # Layer occupancy (ticks) 1588system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1589system.iobus.reqLayer24.occupancy 33084000 # Layer occupancy (ticks) 1590system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1591system.iobus.reqLayer25.occupancy 186380025 # Layer occupancy (ticks) 1592system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1593system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1594system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1595system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) 1596system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1597system.iocache.tags.replacements 36409 # number of replacements 1598system.iocache.tags.tagsinuse 1.005380 # Cycle average of tags in use 1599system.iocache.tags.total_refs 30 # Total number of references to valid blocks. 1600system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. 1601system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. 1602system.iocache.tags.warmup_cycle 256605907000 # Cycle when the warmup percentage was hit. 1603system.iocache.tags.occ_blocks::realview.ide 1.005380 # Average occupied blocks per requestor 1604system.iocache.tags.occ_percent::realview.ide 0.062836 # Average percentage of cache occupancy 1605system.iocache.tags.occ_percent::total 0.062836 # Average percentage of cache occupancy 1606system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1607system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1608system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1609system.iocache.tags.tag_accesses 328227 # Number of tag accesses 1610system.iocache.tags.data_accesses 328227 # Number of data accesses 1611system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits 1612system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits 1613system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses 1614system.iocache.ReadReq_misses::total 249 # number of ReadReq misses 1615system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses 1616system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses 1617system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses 1618system.iocache.demand_misses::total 249 # number of demand (read+write) misses 1619system.iocache.overall_misses::realview.ide 249 # number of overall misses 1620system.iocache.overall_misses::total 249 # number of overall misses 1621system.iocache.ReadReq_miss_latency::realview.ide 31316876 # number of ReadReq miss cycles 1622system.iocache.ReadReq_miss_latency::total 31316876 # number of ReadReq miss cycles 1623system.iocache.WriteLineReq_miss_latency::realview.ide 4717082149 # number of WriteLineReq miss cycles 1624system.iocache.WriteLineReq_miss_latency::total 4717082149 # number of WriteLineReq miss cycles 1625system.iocache.demand_miss_latency::realview.ide 31316876 # number of demand (read+write) miss cycles 1626system.iocache.demand_miss_latency::total 31316876 # number of demand (read+write) miss cycles 1627system.iocache.overall_miss_latency::realview.ide 31316876 # number of overall miss cycles 1628system.iocache.overall_miss_latency::total 31316876 # number of overall miss cycles 1629system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) 1630system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) 1631system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1632system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1633system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses 1634system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses 1635system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses 1636system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses 1637system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1638system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1639system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses 1640system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses 1641system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1642system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1643system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1644system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1645system.iocache.ReadReq_avg_miss_latency::realview.ide 125770.586345 # average ReadReq miss latency 1646system.iocache.ReadReq_avg_miss_latency::total 125770.586345 # average ReadReq miss latency 1647system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130324.137284 # average WriteLineReq miss latency 1648system.iocache.WriteLineReq_avg_miss_latency::total 130324.137284 # average WriteLineReq miss latency 1649system.iocache.demand_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency 1650system.iocache.demand_avg_miss_latency::total 125770.586345 # average overall miss latency 1651system.iocache.overall_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency 1652system.iocache.overall_avg_miss_latency::total 125770.586345 # average overall miss latency 1653system.iocache.blocked_cycles::no_mshrs 902 # number of cycles access was blocked 1654system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1655system.iocache.blocked::no_mshrs 96 # number of cycles access was blocked 1656system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1657system.iocache.avg_blocked_cycles::no_mshrs 9.395833 # average number of cycles each access was blocked 1658system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1659system.iocache.fast_writes 0 # number of fast writes performed 1660system.iocache.cache_copies 0 # number of cache copies performed 1661system.iocache.writebacks::writebacks 36160 # number of writebacks 1662system.iocache.writebacks::total 36160 # number of writebacks 1663system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses 1664system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses 1665system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses 1666system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses 1667system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses 1668system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses 1669system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses 1670system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses 1671system.iocache.ReadReq_mshr_miss_latency::realview.ide 18866876 # number of ReadReq MSHR miss cycles 1672system.iocache.ReadReq_mshr_miss_latency::total 18866876 # number of ReadReq MSHR miss cycles 1673system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907332149 # number of WriteLineReq MSHR miss cycles 1674system.iocache.WriteLineReq_mshr_miss_latency::total 2907332149 # number of WriteLineReq MSHR miss cycles 1675system.iocache.demand_mshr_miss_latency::realview.ide 18866876 # number of demand (read+write) MSHR miss cycles 1676system.iocache.demand_mshr_miss_latency::total 18866876 # number of demand (read+write) MSHR miss cycles 1677system.iocache.overall_mshr_miss_latency::realview.ide 18866876 # number of overall MSHR miss cycles 1678system.iocache.overall_mshr_miss_latency::total 18866876 # number of overall MSHR miss cycles 1679system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1680system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1681system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses 1682system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses 1683system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1684system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1685system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1686system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1687system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75770.586345 # average ReadReq mshr miss latency 1688system.iocache.ReadReq_avg_mshr_miss_latency::total 75770.586345 # average ReadReq mshr miss latency 1689system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80324.137284 # average WriteLineReq mshr miss latency 1690system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80324.137284 # average WriteLineReq mshr miss latency 1691system.iocache.demand_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency 1692system.iocache.demand_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency 1693system.iocache.overall_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency 1694system.iocache.overall_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency 1695system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1696system.membus.trans_dist::ReadReq 34133 # Transaction distribution 1697system.membus.trans_dist::ReadResp 67559 # Transaction distribution 1698system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1699system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1700system.membus.trans_dist::WritebackDirty 124958 # Transaction distribution 1701system.membus.trans_dist::CleanEvict 7701 # Transaction distribution 1702system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution 1703system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1704system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution 1705system.membus.trans_dist::ReadExReq 133521 # Transaction distribution 1706system.membus.trans_dist::ReadExResp 133521 # Transaction distribution 1707system.membus.trans_dist::ReadSharedReq 33427 # Transaction distribution 1708system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution 1709system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution 1710system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1711system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1712system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) 1713system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 454663 # Packet count per connected master and slave (bytes) 1714system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562233 # Packet count per connected master and slave (bytes) 1715system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes) 1716system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes) 1717system.membus.pkt_count::total 671059 # Packet count per connected master and slave (bytes) 1718system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1719system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1720system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) 1721system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16401756 # Cumulative packet size per connected master and slave (bytes) 1722system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565161 # Cumulative packet size per connected master and slave (bytes) 1723system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) 1724system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) 1725system.membus.pkt_size::total 18880361 # Cumulative packet size per connected master and slave (bytes) 1726system.membus.snoops 513 # Total snoops (count) 1727system.membus.snoop_fanout::samples 402363 # Request fanout histogram 1728system.membus.snoop_fanout::mean 1 # Request fanout histogram 1729system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1730system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1731system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1732system.membus.snoop_fanout::1 402363 100.00% 100.00% # Request fanout histogram 1733system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1734system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1735system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1736system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1737system.membus.snoop_fanout::total 402363 # Request fanout histogram 1738system.membus.reqLayer0.occupancy 83709500 # Layer occupancy (ticks) 1739system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1740system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1741system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1742system.membus.reqLayer2.occupancy 1749000 # Layer occupancy (ticks) 1743system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1744system.membus.reqLayer5.occupancy 873720378 # Layer occupancy (ticks) 1745system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1746system.membus.respLayer2.occupancy 987389399 # Layer occupancy (ticks) 1747system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1748system.membus.respLayer3.occupancy 64116283 # Layer occupancy (ticks) 1749system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1750system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1751system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1752system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1753system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1754system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1755system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1756system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1757system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1758system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1759system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1760system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1761system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1762system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1763system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1764system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1765system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1766system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1767system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1768system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1769system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1770system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1771system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1772system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1773system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1774system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1775system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1776system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1777system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1778system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1779system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1780system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1781system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1782system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1783system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1784system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1785system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1786system.realview.ethernet.droppedPackets 0 # number of packets dropped 1787system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1788system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1789system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1790system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1791system.cpu.kern.inst.arm 0 # number of arm instructions executed 1792system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 1793 1794---------- End Simulation Statistics ---------- 1795