stats.txt revision 10148:4574d5882066
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.526170 # Number of seconds simulated 4sim_ticks 2526169857500 # Number of ticks simulated 5final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 58326 # Simulator instruction rate (inst/s) 8host_op_rate 75048 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2443063970 # Simulator tick rate (ticks/s) 10host_mem_usage 467448 # Number of bytes of host memory used 11host_seconds 1034.02 # Real time elapsed on the host 12sim_insts 60309637 # Number of instructions simulated 13sim_ops 77601213 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory 21system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15096868 # Number of read requests accepted 55system.physmem.writeReqs 813159 # Number of write requests accepted 56system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 943297 # Per bank write bursts 67system.physmem.perBankRdBursts::1 937033 # Per bank write bursts 68system.physmem.perBankRdBursts::2 936962 # Per bank write bursts 69system.physmem.perBankRdBursts::3 936535 # Per bank write bursts 70system.physmem.perBankRdBursts::4 942693 # Per bank write bursts 71system.physmem.perBankRdBursts::5 936569 # Per bank write bursts 72system.physmem.perBankRdBursts::6 936319 # Per bank write bursts 73system.physmem.perBankRdBursts::7 936043 # Per bank write bursts 74system.physmem.perBankRdBursts::8 943596 # Per bank write bursts 75system.physmem.perBankRdBursts::9 936992 # Per bank write bursts 76system.physmem.perBankRdBursts::10 936414 # Per bank write bursts 77system.physmem.perBankRdBursts::11 935912 # Per bank write bursts 78system.physmem.perBankRdBursts::12 943556 # Per bank write bursts 79system.physmem.perBankRdBursts::13 937007 # Per bank write bursts 80system.physmem.perBankRdBursts::14 937039 # Per bank write bursts 81system.physmem.perBankRdBursts::15 936676 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6606 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6375 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6521 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6552 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6461 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6711 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6720 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6668 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7045 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6826 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6497 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6136 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7072 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6672 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6956 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6819 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2526168741500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 38 # Read request sizes (log2) 104system.physmem.readPktSize::3 14942208 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 154622 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 59141 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads 263system.physmem.totQLat 571195583500 # Total ticks spent queuing 264system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers 266system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks 267system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst 268system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 2.99 # Data bus utilization in percentage 277system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing 281system.physmem.readRowHits 14041195 # Number of row buffer hits during reads 282system.physmem.writeRowHits 91389 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes 285system.physmem.avgGap 158778.41 # Average gap between requests 286system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined 287system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state 288system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 289system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 290system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 291system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 292system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 293system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 294system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 295system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 296system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 297system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 298system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 299system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 300system.membus.throughput 54878638 # Throughput (bytes/s) 301system.membus.trans_dist::ReadReq 16149508 # Transaction distribution 302system.membus.trans_dist::ReadResp 16149508 # Transaction distribution 303system.membus.trans_dist::WriteReq 763349 # Transaction distribution 304system.membus.trans_dist::WriteResp 763349 # Transaction distribution 305system.membus.trans_dist::Writeback 59141 # Transaction distribution 306system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution 307system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 308system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution 309system.membus.trans_dist::ReadExReq 131433 # Transaction distribution 310system.membus.trans_dist::ReadExResp 131433 # Transaction distribution 311system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) 312system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) 314system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 315system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) 319system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes) 320system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes) 326system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) 327system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) 328system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes) 329system.membus.data_through_bus 138632762 # Total data (bytes) 330system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 331system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks) 332system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 333system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 334system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 335system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks) 336system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 337system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 338system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 339system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks) 340system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 341system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks) 342system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 343system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks) 344system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 345system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 346system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 347system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 348system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 349system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 350system.cf0.dma_write_txs 0 # Number of DMA write transactions. 351system.iobus.throughput 48266001 # Throughput (bytes/s) 352system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution 353system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution 354system.iobus.trans_dist::WriteReq 8174 # Transaction distribution 355system.iobus.trans_dist::WriteResp 8174 # Transaction distribution 356system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) 360system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 361system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 367system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 368system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 369system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 370system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 371system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 372system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 373system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 374system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 375system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 376system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 377system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 378system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 379system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) 380system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) 381system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) 382system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 388system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 394system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 395system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 396system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 398system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 399system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 400system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 401system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 402system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 403system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 404system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 405system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 406system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) 407system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) 408system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) 409system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) 410system.iobus.data_through_bus 121928118 # Total data (bytes) 411system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 412system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 413system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) 414system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 415system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) 416system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 417system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) 418system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 419system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 420system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 421system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 422system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 423system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 424system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 425system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 426system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 427system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 428system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 429system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 430system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 431system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 432system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 433system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 434system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 435system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 436system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 437system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 438system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 439system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 440system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 441system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 442system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 443system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 444system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 445system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 446system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 447system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 448system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 449system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 450system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 451system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 452system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 453system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 454system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 455system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 456system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 457system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) 458system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 459system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) 460system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 461system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks) 462system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 463system.cpu_clk_domain.clock 500 # Clock period in ticks 464system.cpu.branchPred.lookups 14755327 # Number of BP lookups 465system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted 466system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect 467system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups 468system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits 469system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 470system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage 471system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target. 472system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions. 473system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 474system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 475system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 476system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 477system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 478system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 479system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 480system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 481system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 482system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 483system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 484system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 485system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 486system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 494system.cpu.dtb.inst_hits 0 # ITB inst hits 495system.cpu.dtb.inst_misses 0 # ITB inst misses 496system.cpu.dtb.read_hits 51187284 # DTB read hits 497system.cpu.dtb.read_misses 65383 # DTB read misses 498system.cpu.dtb.write_hits 11703682 # DTB write hits 499system.cpu.dtb.write_misses 15916 # DTB write misses 500system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 501system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 502system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 503system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 504system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB 505system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions 506system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch 507system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 508system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions 509system.cpu.dtb.read_accesses 51252667 # DTB read accesses 510system.cpu.dtb.write_accesses 11719598 # DTB write accesses 511system.cpu.dtb.inst_accesses 0 # ITB inst accesses 512system.cpu.dtb.hits 62890966 # DTB hits 513system.cpu.dtb.misses 81299 # DTB misses 514system.cpu.dtb.accesses 62972265 # DTB accesses 515system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 516system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 517system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 518system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 519system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 520system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 521system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 522system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 523system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 524system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 525system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 526system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 527system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 528system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 529system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 530system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 531system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 532system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 533system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 534system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 535system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 536system.cpu.itb.inst_hits 11527099 # ITB inst hits 537system.cpu.itb.inst_misses 11249 # ITB inst misses 538system.cpu.itb.read_hits 0 # DTB read hits 539system.cpu.itb.read_misses 0 # DTB read misses 540system.cpu.itb.write_hits 0 # DTB write hits 541system.cpu.itb.write_misses 0 # DTB write misses 542system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 543system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 544system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 545system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 546system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB 547system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 548system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 549system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 550system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions 551system.cpu.itb.read_accesses 0 # DTB read accesses 552system.cpu.itb.write_accesses 0 # DTB write accesses 553system.cpu.itb.inst_accesses 11538348 # ITB inst accesses 554system.cpu.itb.hits 11527099 # DTB hits 555system.cpu.itb.misses 11249 # DTB misses 556system.cpu.itb.accesses 11538348 # DTB accesses 557system.cpu.numCycles 477119451 # number of cpu cycles simulated 558system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 559system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 560system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss 561system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed 562system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered 563system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken 564system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked 565system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing 566system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb 567system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked 568system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 569system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps 570system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions 571system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR 572system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched 573system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed 574system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed 575system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total) 581system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total) 582system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total) 584system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total) 585system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total) 586system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total) 588system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 590system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 591system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle 593system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle 594system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle 595system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked 596system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running 597system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking 598system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing 599system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch 600system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction 601system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode 602system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode 603system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing 604system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle 605system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking 606system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst 607system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running 608system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking 609system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename 610system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full 611system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full 612system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full 613system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers 614system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed 615system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made 616system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups 617system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups 618system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed 619system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing 620system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed 621system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed 622system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer 623system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit. 624system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit. 625system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads. 626system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores. 627system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec) 628system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ 629system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued 630system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued 631system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling 632system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph 633system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed 634system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle 641system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle 642system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle 643system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle 646system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle 651system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 652system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available 653system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available 654system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 655system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 656system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 657system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 658system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 659system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 660system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 681system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available 682system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available 683system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 684system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 685system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued 686system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued 687system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued 688system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued 689system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued 690system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued 691system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued 692system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued 693system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued 694system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued 715system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued 716system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued 717system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 718system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 719system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued 720system.cpu.iq.rate 0.257655 # Inst issue rate 721system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested 722system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst) 723system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads 724system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes 725system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses 726system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads 727system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes 728system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses 729system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses 730system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses 731system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores 732system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 733system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed 734system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed 735system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations 736system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed 737system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 738system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 739system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled 740system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked 741system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 742system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing 743system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking 744system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking 745system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ 746system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch 747system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions 748system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions 749system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions 750system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall 751system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall 752system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations 753system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly 754system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly 755system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute 756system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions 757system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed 758system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute 759system.cpu.iew.exec_swp 0 # number of swp insts executed 760system.cpu.iew.exec_nop 221278 # number of nop insts executed 761system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed 762system.cpu.iew.exec_branches 11821235 # Number of branches executed 763system.cpu.iew.exec_stores 12215513 # Number of stores executed 764system.cpu.iew.exec_rate 0.253301 # Inst execution rate 765system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit 766system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back 767system.cpu.iew.wb_producers 47029089 # num instructions producing a value 768system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value 769system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 770system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle 771system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back 772system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 773system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit 774system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards 775system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted 776system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 780system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle 783system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle 784system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle 785system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle 793system.cpu.commit.committedInsts 60460018 # Number of instructions committed 794system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed 795system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 796system.cpu.commit.refs 27386851 # Number of memory references committed 797system.cpu.commit.loads 15654790 # Number of loads committed 798system.cpu.commit.membars 403577 # Number of memory barriers committed 799system.cpu.commit.branches 10306380 # Number of branches committed 800system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 801system.cpu.commit.int_insts 69191623 # Number of committed integer instructions. 802system.cpu.commit.function_calls 991253 # Number of function calls committed. 803system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached 804system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 805system.cpu.rob.rob_reads 242979782 # The number of ROB reads 806system.cpu.rob.rob_writes 196005989 # The number of ROB writes 807system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself 808system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling 809system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 810system.cpu.committedInsts 60309637 # Number of Instructions Simulated 811system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated 812system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated 813system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction 814system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads 815system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle 816system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads 817system.cpu.int_regfile_reads 548697999 # number of integer regfile reads 818system.cpu.int_regfile_writes 87552825 # number of integer regfile writes 819system.cpu.fp_regfile_reads 8408 # number of floating regfile reads 820system.cpu.fp_regfile_writes 2932 # number of floating regfile writes 821system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads 822system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes 823system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s) 824system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution 825system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution 826system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution 828system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution 829system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution 830system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution 831system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution 832system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution 833system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution 834system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes) 835system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes) 836system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes) 837system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes) 838system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes) 839system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes) 840system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes) 841system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) 842system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes) 843system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes) 844system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes) 845system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes) 846system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks) 847system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 848system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks) 849system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 850system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks) 851system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 852system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks) 853system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 854system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks) 855system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 856system.cpu.icache.tags.replacements 980897 # number of replacements 857system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use 858system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks. 859system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks. 860system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks. 861system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit. 862system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor 863system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy 864system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy 865system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 867system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id 868system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id 869system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 870system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 871system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses 872system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses 873system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # number of ReadReq hits 874system.cpu.icache.ReadReq_hits::total 10462766 # number of ReadReq hits 875system.cpu.icache.demand_hits::cpu.inst 10462766 # number of demand (read+write) hits 876system.cpu.icache.demand_hits::total 10462766 # number of demand (read+write) hits 877system.cpu.icache.overall_hits::cpu.inst 10462766 # number of overall hits 878system.cpu.icache.overall_hits::total 10462766 # number of overall hits 879system.cpu.icache.ReadReq_misses::cpu.inst 1060743 # number of ReadReq misses 880system.cpu.icache.ReadReq_misses::total 1060743 # number of ReadReq misses 881system.cpu.icache.demand_misses::cpu.inst 1060743 # number of demand (read+write) misses 882system.cpu.icache.demand_misses::total 1060743 # number of demand (read+write) misses 883system.cpu.icache.overall_misses::cpu.inst 1060743 # number of overall misses 884system.cpu.icache.overall_misses::total 1060743 # number of overall misses 885system.cpu.icache.ReadReq_miss_latency::cpu.inst 14268635888 # number of ReadReq miss cycles 886system.cpu.icache.ReadReq_miss_latency::total 14268635888 # number of ReadReq miss cycles 887system.cpu.icache.demand_miss_latency::cpu.inst 14268635888 # number of demand (read+write) miss cycles 888system.cpu.icache.demand_miss_latency::total 14268635888 # number of demand (read+write) miss cycles 889system.cpu.icache.overall_miss_latency::cpu.inst 14268635888 # number of overall miss cycles 890system.cpu.icache.overall_miss_latency::total 14268635888 # number of overall miss cycles 891system.cpu.icache.ReadReq_accesses::cpu.inst 11523509 # number of ReadReq accesses(hits+misses) 892system.cpu.icache.ReadReq_accesses::total 11523509 # number of ReadReq accesses(hits+misses) 893system.cpu.icache.demand_accesses::cpu.inst 11523509 # number of demand (read+write) accesses 894system.cpu.icache.demand_accesses::total 11523509 # number of demand (read+write) accesses 895system.cpu.icache.overall_accesses::cpu.inst 11523509 # number of overall (read+write) accesses 896system.cpu.icache.overall_accesses::total 11523509 # number of overall (read+write) accesses 897system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092050 # miss rate for ReadReq accesses 898system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses 899system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses 900system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses 901system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses 902system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses 903system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency 904system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency 905system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency 906system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency 908system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency 909system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked 910system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.cpu.icache.blocked::no_mshrs 344 # number of cycles access was blocked 912system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 913system.cpu.icache.avg_blocked_cycles::no_mshrs 22.668605 # average number of cycles each access was blocked 914system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 915system.cpu.icache.fast_writes 0 # number of fast writes performed 916system.cpu.icache.cache_copies 0 # number of cache copies performed 917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79293 # number of ReadReq MSHR hits 918system.cpu.icache.ReadReq_mshr_hits::total 79293 # number of ReadReq MSHR hits 919system.cpu.icache.demand_mshr_hits::cpu.inst 79293 # number of demand (read+write) MSHR hits 920system.cpu.icache.demand_mshr_hits::total 79293 # number of demand (read+write) MSHR hits 921system.cpu.icache.overall_mshr_hits::cpu.inst 79293 # number of overall MSHR hits 922system.cpu.icache.overall_mshr_hits::total 79293 # number of overall MSHR hits 923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981450 # number of ReadReq MSHR misses 924system.cpu.icache.ReadReq_mshr_misses::total 981450 # number of ReadReq MSHR misses 925system.cpu.icache.demand_mshr_misses::cpu.inst 981450 # number of demand (read+write) MSHR misses 926system.cpu.icache.demand_mshr_misses::total 981450 # number of demand (read+write) MSHR misses 927system.cpu.icache.overall_mshr_misses::cpu.inst 981450 # number of overall MSHR misses 928system.cpu.icache.overall_mshr_misses::total 981450 # number of overall MSHR misses 929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587546773 # number of ReadReq MSHR miss cycles 930system.cpu.icache.ReadReq_mshr_miss_latency::total 11587546773 # number of ReadReq MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587546773 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::total 11587546773 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587546773 # number of overall MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::total 11587546773 # number of overall MSHR miss cycles 935system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9345000 # number of ReadReq MSHR uncacheable cycles 936system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9345000 # number of ReadReq MSHR uncacheable cycles 937system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9345000 # number of overall MSHR uncacheable cycles 938system.cpu.icache.overall_mshr_uncacheable_latency::total 9345000 # number of overall MSHR uncacheable cycles 939system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for ReadReq accesses 940system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085169 # mshr miss rate for ReadReq accesses 941system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for demand accesses 942system.cpu.icache.demand_mshr_miss_rate::total 0.085169 # mshr miss rate for demand accesses 943system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for overall accesses 944system.cpu.icache.overall_mshr_miss_rate::total 0.085169 # mshr miss rate for overall accesses 945system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432 # average ReadReq mshr miss latency 946system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432 # average ReadReq mshr miss latency 947system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency 948system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency 949system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency 950system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency 951system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 952system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 953system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 954system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 955system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 956system.cpu.l2cache.tags.replacements 64391 # number of replacements 957system.cpu.l2cache.tags.tagsinuse 51374.630920 # Cycle average of tags in use 958system.cpu.l2cache.tags.total_refs 1887139 # Total number of references to valid blocks. 959system.cpu.l2cache.tags.sampled_refs 129786 # Sample count of references to valid blocks. 960system.cpu.l2cache.tags.avg_refs 14.540390 # Average number of references to valid blocks. 961system.cpu.l2cache.tags.warmup_cycle 2490832751500 # Cycle when the warmup percentage was hit. 962system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159 # Average occupied blocks per requestor 963system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.305745 # Average occupied blocks per requestor 964system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000374 # Average occupied blocks per requestor 965system.cpu.l2cache.tags.occ_blocks::cpu.inst 8179.061871 # Average occupied blocks per requestor 966system.cpu.l2cache.tags.occ_blocks::cpu.data 6245.594773 # Average occupied blocks per requestor 967system.cpu.l2cache.tags.occ_percent::writebacks 0.563334 # Average percentage of cache occupancy 968system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000478 # Average percentage of cache occupancy 969system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 970system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124803 # Average percentage of cache occupancy 971system.cpu.l2cache.tags.occ_percent::cpu.data 0.095300 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::total 0.783915 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id 974system.cpu.l2cache.tags.occ_task_id_blocks::1024 65372 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3052 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6933 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54996 # Occupied blocks per task id 981system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id 982system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997498 # Percentage of cache occupancy per task id 983system.cpu.l2cache.tags.tag_accesses 18788998 # Number of tag accesses 984system.cpu.l2cache.tags.data_accesses 18788998 # Number of data accesses 985system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53598 # number of ReadReq hits 986system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10246 # number of ReadReq hits 987system.cpu.l2cache.ReadReq_hits::cpu.inst 967912 # number of ReadReq hits 988system.cpu.l2cache.ReadReq_hits::cpu.data 386978 # number of ReadReq hits 989system.cpu.l2cache.ReadReq_hits::total 1418734 # number of ReadReq hits 990system.cpu.l2cache.Writeback_hits::writebacks 607635 # number of Writeback hits 991system.cpu.l2cache.Writeback_hits::total 607635 # number of Writeback hits 992system.cpu.l2cache.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits 993system.cpu.l2cache.UpgradeReq_hits::total 46 # number of UpgradeReq hits 994system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits 995system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits 996system.cpu.l2cache.ReadExReq_hits::cpu.data 112878 # number of ReadExReq hits 997system.cpu.l2cache.ReadExReq_hits::total 112878 # number of ReadExReq hits 998system.cpu.l2cache.demand_hits::cpu.dtb.walker 53598 # number of demand (read+write) hits 999system.cpu.l2cache.demand_hits::cpu.itb.walker 10246 # number of demand (read+write) hits 1000system.cpu.l2cache.demand_hits::cpu.inst 967912 # number of demand (read+write) hits 1001system.cpu.l2cache.demand_hits::cpu.data 499856 # number of demand (read+write) hits 1002system.cpu.l2cache.demand_hits::total 1531612 # number of demand (read+write) hits 1003system.cpu.l2cache.overall_hits::cpu.dtb.walker 53598 # number of overall hits 1004system.cpu.l2cache.overall_hits::cpu.itb.walker 10246 # number of overall hits 1005system.cpu.l2cache.overall_hits::cpu.inst 967912 # number of overall hits 1006system.cpu.l2cache.overall_hits::cpu.data 499856 # number of overall hits 1007system.cpu.l2cache.overall_hits::total 1531612 # number of overall hits 1008system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 45 # number of ReadReq misses 1009system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1010system.cpu.l2cache.ReadReq_misses::cpu.inst 12357 # number of ReadReq misses 1011system.cpu.l2cache.ReadReq_misses::cpu.data 10744 # number of ReadReq misses 1012system.cpu.l2cache.ReadReq_misses::total 23148 # number of ReadReq misses 1013system.cpu.l2cache.UpgradeReq_misses::cpu.data 2913 # number of UpgradeReq misses 1014system.cpu.l2cache.UpgradeReq_misses::total 2913 # number of UpgradeReq misses 1015system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1016system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1017system.cpu.l2cache.ReadExReq_misses::cpu.data 133191 # number of ReadExReq misses 1018system.cpu.l2cache.ReadExReq_misses::total 133191 # number of ReadExReq misses 1019system.cpu.l2cache.demand_misses::cpu.dtb.walker 45 # number of demand (read+write) misses 1020system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1021system.cpu.l2cache.demand_misses::cpu.inst 12357 # number of demand (read+write) misses 1022system.cpu.l2cache.demand_misses::cpu.data 143935 # number of demand (read+write) misses 1023system.cpu.l2cache.demand_misses::total 156339 # number of demand (read+write) misses 1024system.cpu.l2cache.overall_misses::cpu.dtb.walker 45 # number of overall misses 1025system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1026system.cpu.l2cache.overall_misses::cpu.inst 12357 # number of overall misses 1027system.cpu.l2cache.overall_misses::cpu.data 143935 # number of overall misses 1028system.cpu.l2cache.overall_misses::total 156339 # number of overall misses 1029system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3974500 # number of ReadReq miss cycles 1030system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 412000 # number of ReadReq miss cycles 1031system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 905251250 # number of ReadReq miss cycles 1032system.cpu.l2cache.ReadReq_miss_latency::cpu.data 810262998 # number of ReadReq miss cycles 1033system.cpu.l2cache.ReadReq_miss_latency::total 1719900748 # number of ReadReq miss cycles 1034system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles 1035system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles 1036system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9827066492 # number of ReadExReq miss cycles 1037system.cpu.l2cache.ReadExReq_miss_latency::total 9827066492 # number of ReadExReq miss cycles 1038system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3974500 # number of demand (read+write) miss cycles 1039system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 412000 # number of demand (read+write) miss cycles 1040system.cpu.l2cache.demand_miss_latency::cpu.inst 905251250 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.demand_miss_latency::cpu.data 10637329490 # number of demand (read+write) miss cycles 1042system.cpu.l2cache.demand_miss_latency::total 11546967240 # number of demand (read+write) miss cycles 1043system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3974500 # number of overall miss cycles 1044system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 412000 # number of overall miss cycles 1045system.cpu.l2cache.overall_miss_latency::cpu.inst 905251250 # number of overall miss cycles 1046system.cpu.l2cache.overall_miss_latency::cpu.data 10637329490 # number of overall miss cycles 1047system.cpu.l2cache.overall_miss_latency::total 11546967240 # number of overall miss cycles 1048system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53643 # number of ReadReq accesses(hits+misses) 1049system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10248 # number of ReadReq accesses(hits+misses) 1050system.cpu.l2cache.ReadReq_accesses::cpu.inst 980269 # number of ReadReq accesses(hits+misses) 1051system.cpu.l2cache.ReadReq_accesses::cpu.data 397722 # number of ReadReq accesses(hits+misses) 1052system.cpu.l2cache.ReadReq_accesses::total 1441882 # number of ReadReq accesses(hits+misses) 1053system.cpu.l2cache.Writeback_accesses::writebacks 607635 # number of Writeback accesses(hits+misses) 1054system.cpu.l2cache.Writeback_accesses::total 607635 # number of Writeback accesses(hits+misses) 1055system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2959 # number of UpgradeReq accesses(hits+misses) 1056system.cpu.l2cache.UpgradeReq_accesses::total 2959 # number of UpgradeReq accesses(hits+misses) 1057system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses) 1058system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses) 1059system.cpu.l2cache.ReadExReq_accesses::cpu.data 246069 # number of ReadExReq accesses(hits+misses) 1060system.cpu.l2cache.ReadExReq_accesses::total 246069 # number of ReadExReq accesses(hits+misses) 1061system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53643 # number of demand (read+write) accesses 1062system.cpu.l2cache.demand_accesses::cpu.itb.walker 10248 # number of demand (read+write) accesses 1063system.cpu.l2cache.demand_accesses::cpu.inst 980269 # number of demand (read+write) accesses 1064system.cpu.l2cache.demand_accesses::cpu.data 643791 # number of demand (read+write) accesses 1065system.cpu.l2cache.demand_accesses::total 1687951 # number of demand (read+write) accesses 1066system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53643 # number of overall (read+write) accesses 1067system.cpu.l2cache.overall_accesses::cpu.itb.walker 10248 # number of overall (read+write) accesses 1068system.cpu.l2cache.overall_accesses::cpu.inst 980269 # number of overall (read+write) accesses 1069system.cpu.l2cache.overall_accesses::cpu.data 643791 # number of overall (read+write) accesses 1070system.cpu.l2cache.overall_accesses::total 1687951 # number of overall (read+write) accesses 1071system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000839 # miss rate for ReadReq accesses 1072system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000195 # miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027014 # miss rate for ReadReq accesses 1075system.cpu.l2cache.ReadReq_miss_rate::total 0.016054 # miss rate for ReadReq accesses 1076system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984454 # miss rate for UpgradeReq accesses 1077system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984454 # miss rate for UpgradeReq accesses 1078system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses 1079system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses 1080system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541275 # miss rate for ReadExReq accesses 1081system.cpu.l2cache.ReadExReq_miss_rate::total 0.541275 # miss rate for ReadExReq accesses 1082system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000839 # miss rate for demand accesses 1083system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000195 # miss rate for demand accesses 1084system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses 1085system.cpu.l2cache.demand_miss_rate::cpu.data 0.223574 # miss rate for demand accesses 1086system.cpu.l2cache.demand_miss_rate::total 0.092621 # miss rate for demand accesses 1087system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000839 # miss rate for overall accesses 1088system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000195 # miss rate for overall accesses 1089system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses 1090system.cpu.l2cache.overall_miss_rate::cpu.data 0.223574 # miss rate for overall accesses 1091system.cpu.l2cache.overall_miss_rate::total 0.092621 # miss rate for overall accesses 1092system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88322.222222 # average ReadReq miss latency 1093system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 206000 # average ReadReq miss latency 1094system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73258.173505 # average ReadReq miss latency 1095system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75415.394453 # average ReadReq miss latency 1096system.cpu.l2cache.ReadReq_avg_miss_latency::total 74300.187835 # average ReadReq miss latency 1097system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.412976 # average UpgradeReq miss latency 1098system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.412976 # average UpgradeReq miss latency 1099system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73781.760720 # average ReadExReq miss latency 1100system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73781.760720 # average ReadExReq miss latency 1101system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88322.222222 # average overall miss latency 1102system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 206000 # average overall miss latency 1103system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73258.173505 # average overall miss latency 1104system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73903.702991 # average overall miss latency 1105system.cpu.l2cache.demand_avg_miss_latency::total 73858.520523 # average overall miss latency 1106system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88322.222222 # average overall miss latency 1107system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 206000 # average overall miss latency 1108system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73258.173505 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73903.702991 # average overall miss latency 1110system.cpu.l2cache.overall_avg_miss_latency::total 73858.520523 # average overall miss latency 1111system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1112system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1113system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1114system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1115system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1116system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1117system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1118system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1119system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks 1120system.cpu.l2cache.writebacks::total 59141 # number of writebacks 1121system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits 1122system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits 1123system.cpu.l2cache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits 1124system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits 1125system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits 1126system.cpu.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits 1127system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits 1128system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits 1129system.cpu.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits 1130system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 45 # number of ReadReq MSHR misses 1131system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1132system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12342 # number of ReadReq MSHR misses 1133system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10679 # number of ReadReq MSHR misses 1134system.cpu.l2cache.ReadReq_mshr_misses::total 23068 # number of ReadReq MSHR misses 1135system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2913 # number of UpgradeReq MSHR misses 1136system.cpu.l2cache.UpgradeReq_mshr_misses::total 2913 # number of UpgradeReq MSHR misses 1137system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1138system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1139system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses 1140system.cpu.l2cache.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 45 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1143system.cpu.l2cache.demand_mshr_misses::cpu.inst 12342 # number of demand (read+write) MSHR misses 1144system.cpu.l2cache.demand_mshr_misses::cpu.data 143870 # number of demand (read+write) MSHR misses 1145system.cpu.l2cache.demand_mshr_misses::total 156259 # number of demand (read+write) MSHR misses 1146system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 45 # number of overall MSHR misses 1147system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1148system.cpu.l2cache.overall_mshr_misses::cpu.inst 12342 # number of overall MSHR misses 1149system.cpu.l2cache.overall_mshr_misses::cpu.data 143870 # number of overall MSHR misses 1150system.cpu.l2cache.overall_mshr_misses::total 156259 # number of overall MSHR misses 1151system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3417500 # number of ReadReq MSHR miss cycles 1152system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 387500 # number of ReadReq MSHR miss cycles 1153system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 749197750 # number of ReadReq MSHR miss cycles 1154system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 673040498 # number of ReadReq MSHR miss cycles 1155system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426043248 # number of ReadReq MSHR miss cycles 1156system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29132913 # number of UpgradeReq MSHR miss cycles 1157system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29132913 # number of UpgradeReq MSHR miss cycles 1158system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1159system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 1160system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8170239508 # number of ReadExReq MSHR miss cycles 1161system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8170239508 # number of ReadExReq MSHR miss cycles 1162system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3417500 # number of demand (read+write) MSHR miss cycles 1163system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 387500 # number of demand (read+write) MSHR miss cycles 1164system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 749197750 # number of demand (read+write) MSHR miss cycles 1165system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8843280006 # number of demand (read+write) MSHR miss cycles 1166system.cpu.l2cache.demand_mshr_miss_latency::total 9596282756 # number of demand (read+write) MSHR miss cycles 1167system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3417500 # number of overall MSHR miss cycles 1168system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 387500 # number of overall MSHR miss cycles 1169system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 749197750 # number of overall MSHR miss cycles 1170system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8843280006 # number of overall MSHR miss cycles 1171system.cpu.l2cache.overall_mshr_miss_latency::total 9596282756 # number of overall MSHR miss cycles 1172system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6814499 # number of ReadReq MSHR uncacheable cycles 1173system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250 # number of ReadReq MSHR uncacheable cycles 1174system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749 # number of ReadReq MSHR uncacheable cycles 1175system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17458567530 # number of WriteReq MSHR uncacheable cycles 1176system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17458567530 # number of WriteReq MSHR uncacheable cycles 1177system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6814499 # number of overall MSHR uncacheable cycles 1178system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780 # number of overall MSHR uncacheable cycles 1179system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279 # number of overall MSHR uncacheable cycles 1180system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses 1181system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for ReadReq accesses 1182system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for ReadReq accesses 1183system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026850 # mshr miss rate for ReadReq accesses 1184system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015999 # mshr miss rate for ReadReq accesses 1185system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984454 # mshr miss rate for UpgradeReq accesses 1186system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984454 # mshr miss rate for UpgradeReq accesses 1187system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses 1188system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses 1189system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541275 # mshr miss rate for ReadExReq accesses 1190system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541275 # mshr miss rate for ReadExReq accesses 1191system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses 1192system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for demand accesses 1193system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for demand accesses 1194system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for demand accesses 1195system.cpu.l2cache.demand_mshr_miss_rate::total 0.092573 # mshr miss rate for demand accesses 1196system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for overall accesses 1197system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for overall accesses 1198system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for overall accesses 1199system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for overall accesses 1200system.cpu.l2cache.overall_mshr_miss_rate::total 0.092573 # mshr miss rate for overall accesses 1201system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average ReadReq mshr miss latency 1202system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 193750 # average ReadReq mshr miss latency 1203system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276 # average ReadReq mshr miss latency 1204system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408 # average ReadReq mshr miss latency 1205system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803 # average ReadReq mshr miss latency 1206system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 1207system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 1208system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1209system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1210system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency 1211system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency 1212system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency 1213system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency 1214system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency 1215system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency 1216system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency 1217system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency 1218system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency 1219system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency 1220system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency 1221system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency 1222system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1223system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1224system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1225system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1226system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1227system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1228system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1229system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1230system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1231system.cpu.dcache.tags.replacements 643279 # number of replacements 1232system.cpu.dcache.tags.tagsinuse 511.993228 # Cycle average of tags in use 1233system.cpu.dcache.tags.total_refs 21514190 # Total number of references to valid blocks. 1234system.cpu.dcache.tags.sampled_refs 643791 # Sample count of references to valid blocks. 1235system.cpu.dcache.tags.avg_refs 33.417973 # Average number of references to valid blocks. 1236system.cpu.dcache.tags.warmup_cycle 43094250 # Cycle when the warmup percentage was hit. 1237system.cpu.dcache.tags.occ_blocks::cpu.data 511.993228 # Average occupied blocks per requestor 1238system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 1239system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy 1240system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1241system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1242system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 1243system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id 1244system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1245system.cpu.dcache.tags.tag_accesses 101537487 # Number of tag accesses 1246system.cpu.dcache.tags.data_accesses 101537487 # Number of data accesses 1247system.cpu.dcache.ReadReq_hits::cpu.data 13760648 # number of ReadReq hits 1248system.cpu.dcache.ReadReq_hits::total 13760648 # number of ReadReq hits 1249system.cpu.dcache.WriteReq_hits::cpu.data 7259865 # number of WriteReq hits 1250system.cpu.dcache.WriteReq_hits::total 7259865 # number of WriteReq hits 1251system.cpu.dcache.LoadLockedReq_hits::cpu.data 242998 # number of LoadLockedReq hits 1252system.cpu.dcache.LoadLockedReq_hits::total 242998 # number of LoadLockedReq hits 1253system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits 1254system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits 1255system.cpu.dcache.demand_hits::cpu.data 21020513 # number of demand (read+write) hits 1256system.cpu.dcache.demand_hits::total 21020513 # number of demand (read+write) hits 1257system.cpu.dcache.overall_hits::cpu.data 21020513 # number of overall hits 1258system.cpu.dcache.overall_hits::total 21020513 # number of overall hits 1259system.cpu.dcache.ReadReq_misses::cpu.data 736359 # number of ReadReq misses 1260system.cpu.dcache.ReadReq_misses::total 736359 # number of ReadReq misses 1261system.cpu.dcache.WriteReq_misses::cpu.data 2962417 # number of WriteReq misses 1262system.cpu.dcache.WriteReq_misses::total 2962417 # number of WriteReq misses 1263system.cpu.dcache.LoadLockedReq_misses::cpu.data 13527 # number of LoadLockedReq misses 1264system.cpu.dcache.LoadLockedReq_misses::total 13527 # number of LoadLockedReq misses 1265system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses 1266system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses 1267system.cpu.dcache.demand_misses::cpu.data 3698776 # number of demand (read+write) misses 1268system.cpu.dcache.demand_misses::total 3698776 # number of demand (read+write) misses 1269system.cpu.dcache.overall_misses::cpu.data 3698776 # number of overall misses 1270system.cpu.dcache.overall_misses::total 3698776 # number of overall misses 1271system.cpu.dcache.ReadReq_miss_latency::cpu.data 9982812336 # number of ReadReq miss cycles 1272system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles 1273system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles 1274system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles 1275system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles 1276system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles 1277system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles 1278system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles 1279system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles 1280system.cpu.dcache.demand_miss_latency::total 149727245915 # number of demand (read+write) miss cycles 1281system.cpu.dcache.overall_miss_latency::cpu.data 149727245915 # number of overall miss cycles 1282system.cpu.dcache.overall_miss_latency::total 149727245915 # number of overall miss cycles 1283system.cpu.dcache.ReadReq_accesses::cpu.data 14497007 # number of ReadReq accesses(hits+misses) 1284system.cpu.dcache.ReadReq_accesses::total 14497007 # number of ReadReq accesses(hits+misses) 1285system.cpu.dcache.WriteReq_accesses::cpu.data 10222282 # number of WriteReq accesses(hits+misses) 1286system.cpu.dcache.WriteReq_accesses::total 10222282 # number of WriteReq accesses(hits+misses) 1287system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256525 # number of LoadLockedReq accesses(hits+misses) 1288system.cpu.dcache.LoadLockedReq_accesses::total 256525 # number of LoadLockedReq accesses(hits+misses) 1289system.cpu.dcache.StoreCondReq_accesses::cpu.data 247610 # number of StoreCondReq accesses(hits+misses) 1290system.cpu.dcache.StoreCondReq_accesses::total 247610 # number of StoreCondReq accesses(hits+misses) 1291system.cpu.dcache.demand_accesses::cpu.data 24719289 # number of demand (read+write) accesses 1292system.cpu.dcache.demand_accesses::total 24719289 # number of demand (read+write) accesses 1293system.cpu.dcache.overall_accesses::cpu.data 24719289 # number of overall (read+write) accesses 1294system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses 1295system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses 1296system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses 1297system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses 1298system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses 1299system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses 1300system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses 1301system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses 1302system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # miss rate for StoreCondReq accesses 1303system.cpu.dcache.demand_miss_rate::cpu.data 0.149631 # miss rate for demand accesses 1304system.cpu.dcache.demand_miss_rate::total 0.149631 # miss rate for demand accesses 1305system.cpu.dcache.overall_miss_rate::cpu.data 0.149631 # miss rate for overall accesses 1306system.cpu.dcache.overall_miss_rate::total 0.149631 # miss rate for overall accesses 1307system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000 # average ReadReq miss latency 1308system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000 # average ReadReq miss latency 1309system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444 # average WriteReq miss latency 1310system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444 # average WriteReq miss latency 1311system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827 # average LoadLockedReq miss latency 1312system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827 # average LoadLockedReq miss latency 1313system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500 # average StoreCondReq miss latency 1314system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency 1315system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency 1316system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency 1317system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency 1318system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency 1319system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked 1320system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked 1321system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked 1322system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked 1323system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked 1324system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked 1325system.cpu.dcache.fast_writes 0 # number of fast writes performed 1326system.cpu.dcache.cache_copies 0 # number of cache copies performed 1327system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks 1328system.cpu.dcache.writebacks::total 607635 # number of writebacks 1329system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits 1330system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits 1331system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits 1332system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits 1333system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits 1334system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits 1335system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits 1336system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits 1337system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits 1338system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits 1339system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses 1340system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses 1341system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses 1342system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses 1343system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses 1344system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses 1345system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses 1346system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses 1347system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses 1348system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses 1349system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses 1350system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses 1351system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles 1352system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles 1353system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles 1354system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles 1355system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles 1356system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles 1357system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles 1358system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles 1359system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles 1360system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles 1361system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles 1362system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles 1363system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles 1364system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles 1365system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles 1366system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles 1367system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles 1368system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles 1369system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses 1370system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses 1371system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses 1372system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses 1373system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses 1374system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses 1375system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses 1376system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses 1377system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses 1378system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses 1379system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses 1380system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses 1381system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency 1382system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency 1383system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency 1384system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency 1385system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency 1386system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency 1387system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency 1388system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency 1389system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency 1390system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency 1391system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency 1392system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency 1393system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1394system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1395system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1396system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1397system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1398system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1399system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1400system.iocache.tags.replacements 0 # number of replacements 1401system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1402system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1403system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1404system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1405system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1406system.iocache.tags.tag_accesses 0 # Number of tag accesses 1407system.iocache.tags.data_accesses 0 # Number of data accesses 1408system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1409system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1410system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1411system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1412system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1413system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1414system.iocache.fast_writes 0 # number of fast writes performed 1415system.iocache.cache_copies 0 # number of cache copies performed 1416system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles 1417system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles 1418system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles 1419system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles 1420system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1421system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1422system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1423system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1424system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1425system.cpu.kern.inst.arm 0 # number of arm instructions executed 1426system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed 1427 1428---------- End Simulation Statistics ---------- 1429