stats.txt revision 8150
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 136897 # Simulator instruction rate (inst/s) 4host_mem_usage 384172 # Number of bytes of host memory used 5host_seconds 379.57 # Real time elapsed on the host 6host_tick_rate 222327398 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 51961461 # Number of instructions simulated 9sim_seconds 0.084388 # Number of seconds simulated 10sim_ticks 84388283500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 9710586 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 12489985 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 157419 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 644152 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 11960647 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 14006556 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 818238 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches 8358835 # Number of branches committed 20system.cpu.commit.COM:bw_lim_events 766788 # number cycles where commit BW limit reached 21system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 22system.cpu.commit.COM:committed_per_cycle::samples 96225527 # Number of insts commited each cycle 23system.cpu.commit.COM:committed_per_cycle::mean 0.541277 # Number of insts commited each cycle 24system.cpu.commit.COM:committed_per_cycle::stdev 1.325518 # Number of insts commited each cycle 25system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26system.cpu.commit.COM:committed_per_cycle::0 74314309 77.23% 77.23% # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::1 10868177 11.29% 88.52% # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::2 3539344 3.68% 92.20% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::3 1575243 1.64% 93.84% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::4 3605097 3.75% 97.59% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::5 765856 0.80% 98.38% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::6 506916 0.53% 98.91% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::7 283797 0.29% 99.20% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::8 766788 0.80% 100.00% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::total 96225527 # Number of insts commited each cycle 39system.cpu.commit.COM:count 52084641 # Number of instructions committed 40system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions. 41system.cpu.commit.COM:function_calls 529465 # Number of function calls committed. 42system.cpu.commit.COM:int_insts 42494142 # Number of committed integer instructions. 43system.cpu.commit.COM:loads 9208604 # Number of loads committed 44system.cpu.commit.COM:membars 3 # Number of memory barriers committed 45system.cpu.commit.COM:refs 16292498 # Number of memory references committed 46system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 47system.cpu.commit.branchMispredicts 712712 # The number of times a branch was mispredicted 48system.cpu.commit.commitCommittedInsts 52084641 # The number of committed instructions 49system.cpu.commit.commitNonSpecStalls 2962577 # The number of times commit has been forced to stall to communicate backwards 50system.cpu.commit.commitSquashedInsts 21317023 # The number of squashed insts skipped by commit 51system.cpu.committedInsts 51961461 # Number of Instructions Simulated 52system.cpu.committedInsts_total 51961461 # Number of Instructions Simulated 53system.cpu.cpi 3.248111 # CPI: Cycles Per Instruction 54system.cpu.cpi_total 3.248111 # CPI: Total CPI of All Threads 55system.cpu.dcache.LoadLockedReq_accesses::0 110709 # number of LoadLockedReq accesses(hits+misses) 56system.cpu.dcache.LoadLockedReq_accesses::total 110709 # number of LoadLockedReq accesses(hits+misses) 57system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15013.262803 # average LoadLockedReq miss latency 58system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 59system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 60system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11890.992284 # average LoadLockedReq mshr miss latency 61system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency 62system.cpu.dcache.LoadLockedReq_hits::0 104187 # number of LoadLockedReq hits 63system.cpu.dcache.LoadLockedReq_hits::total 104187 # number of LoadLockedReq hits 64system.cpu.dcache.LoadLockedReq_miss_latency 97916500 # number of LoadLockedReq miss cycles 65system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058911 # miss rate for LoadLockedReq accesses 66system.cpu.dcache.LoadLockedReq_misses::0 6522 # number of LoadLockedReq misses 67system.cpu.dcache.LoadLockedReq_misses::total 6522 # number of LoadLockedReq misses 68system.cpu.dcache.LoadLockedReq_mshr_hits 949 # number of LoadLockedReq MSHR hits 69system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66268500 # number of LoadLockedReq MSHR miss cycles 70system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050339 # mshr miss rate for LoadLockedReq accesses 71system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 72system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 73system.cpu.dcache.LoadLockedReq_mshr_misses 5573 # number of LoadLockedReq MSHR misses 74system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 312424000 # number of LoadLockedReq MSHR uncacheable cycles 75system.cpu.dcache.ReadReq_accesses::0 10044139 # number of ReadReq accesses(hits+misses) 76system.cpu.dcache.ReadReq_accesses::total 10044139 # number of ReadReq accesses(hits+misses) 77system.cpu.dcache.ReadReq_avg_miss_latency::0 14270.972361 # average ReadReq miss latency 78system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 79system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 80system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13253.335400 # average ReadReq mshr miss latency 81system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 82system.cpu.dcache.ReadReq_hits::0 9552480 # number of ReadReq hits 83system.cpu.dcache.ReadReq_hits::total 9552480 # number of ReadReq hits 84system.cpu.dcache.ReadReq_miss_latency 7016452000 # number of ReadReq miss cycles 85system.cpu.dcache.ReadReq_miss_rate::0 0.048950 # miss rate for ReadReq accesses 86system.cpu.dcache.ReadReq_misses::0 491659 # number of ReadReq misses 87system.cpu.dcache.ReadReq_misses::total 491659 # number of ReadReq misses 88system.cpu.dcache.ReadReq_mshr_hits 243263 # number of ReadReq MSHR hits 89system.cpu.dcache.ReadReq_mshr_miss_latency 3292075500 # number of ReadReq MSHR miss cycles 90system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.024730 # mshr miss rate for ReadReq accesses 91system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 92system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 93system.cpu.dcache.ReadReq_mshr_misses 248396 # number of ReadReq MSHR misses 94system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191881500 # number of ReadReq MSHR uncacheable cycles 95system.cpu.dcache.StoreCondReq_accesses::0 104612 # number of StoreCondReq accesses(hits+misses) 96system.cpu.dcache.StoreCondReq_accesses::total 104612 # number of StoreCondReq accesses(hits+misses) 97system.cpu.dcache.StoreCondReq_hits::0 104612 # number of StoreCondReq hits 98system.cpu.dcache.StoreCondReq_hits::total 104612 # number of StoreCondReq hits 99system.cpu.dcache.WriteReq_accesses::0 6670215 # number of WriteReq accesses(hits+misses) 100system.cpu.dcache.WriteReq_accesses::total 6670215 # number of WriteReq accesses(hits+misses) 101system.cpu.dcache.WriteReq_avg_miss_latency::0 39957.308282 # average WriteReq miss latency 102system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 103system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 104system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38553.884427 # average WriteReq mshr miss latency 105system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 106system.cpu.dcache.WriteReq_hits::0 4625539 # number of WriteReq hits 107system.cpu.dcache.WriteReq_hits::total 4625539 # number of WriteReq hits 108system.cpu.dcache.WriteReq_miss_latency 81699749268 # number of WriteReq miss cycles 109system.cpu.dcache.WriteReq_miss_rate::0 0.306538 # miss rate for WriteReq accesses 110system.cpu.dcache.WriteReq_misses::0 2044676 # number of WriteReq misses 111system.cpu.dcache.WriteReq_misses::total 2044676 # number of WriteReq misses 112system.cpu.dcache.WriteReq_mshr_hits 1874256 # number of WriteReq MSHR hits 113system.cpu.dcache.WriteReq_mshr_miss_latency 6570352984 # number of WriteReq MSHR miss cycles 114system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025549 # mshr miss rate for WriteReq accesses 115system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 116system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 117system.cpu.dcache.WriteReq_mshr_misses 170420 # number of WriteReq MSHR misses 118system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939854183 # number of WriteReq MSHR uncacheable cycles 119system.cpu.dcache.avg_blocked_cycles::no_mshrs 7310.688742 # average number of cycles each access was blocked 120system.cpu.dcache.avg_blocked_cycles::no_targets 21687.500000 # average number of cycles each access was blocked 121system.cpu.dcache.avg_refs 34.045188 # Average number of references to valid blocks. 122system.cpu.dcache.blocked::no_mshrs 906 # number of cycles access was blocked 123system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked 124system.cpu.dcache.blocked_cycles::no_mshrs 6623484 # number of cycles access was blocked 125system.cpu.dcache.blocked_cycles::no_targets 520500 # number of cycles access was blocked 126system.cpu.dcache.cache_copies 0 # number of cache copies performed 127system.cpu.dcache.demand_accesses::0 16714354 # number of demand (read+write) accesses 128system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 129system.cpu.dcache.demand_accesses::total 16714354 # number of demand (read+write) accesses 130system.cpu.dcache.demand_avg_miss_latency::0 34978.108676 # average overall miss latency 131system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 132system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 133system.cpu.dcache.demand_avg_mshr_miss_latency 23548.356519 # average overall mshr miss latency 134system.cpu.dcache.demand_hits::0 14178019 # number of demand (read+write) hits 135system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 136system.cpu.dcache.demand_hits::total 14178019 # number of demand (read+write) hits 137system.cpu.dcache.demand_miss_latency 88716201268 # number of demand (read+write) miss cycles 138system.cpu.dcache.demand_miss_rate::0 0.151746 # miss rate for demand accesses 139system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 140system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 141system.cpu.dcache.demand_misses::0 2536335 # number of demand (read+write) misses 142system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 143system.cpu.dcache.demand_misses::total 2536335 # number of demand (read+write) misses 144system.cpu.dcache.demand_mshr_hits 2117519 # number of demand (read+write) MSHR hits 145system.cpu.dcache.demand_mshr_miss_latency 9862428484 # number of demand (read+write) MSHR miss cycles 146system.cpu.dcache.demand_mshr_miss_rate::0 0.025057 # mshr miss rate for demand accesses 147system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 148system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 149system.cpu.dcache.demand_mshr_misses 418816 # number of demand (read+write) MSHR misses 150system.cpu.dcache.fast_writes 0 # number of fast writes performed 151system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 152system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 153system.cpu.dcache.occ_%::0 0.999523 # Average percentage of cache occupancy 154system.cpu.dcache.occ_blocks::0 511.755643 # Average occupied blocks per context 155system.cpu.dcache.overall_accesses::0 16714354 # number of overall (read+write) accesses 156system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 157system.cpu.dcache.overall_accesses::total 16714354 # number of overall (read+write) accesses 158system.cpu.dcache.overall_avg_miss_latency::0 34978.108676 # average overall miss latency 159system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 160system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 161system.cpu.dcache.overall_avg_mshr_miss_latency 23548.356519 # average overall mshr miss latency 162system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 163system.cpu.dcache.overall_hits::0 14178019 # number of overall hits 164system.cpu.dcache.overall_hits::1 0 # number of overall hits 165system.cpu.dcache.overall_hits::total 14178019 # number of overall hits 166system.cpu.dcache.overall_miss_latency 88716201268 # number of overall miss cycles 167system.cpu.dcache.overall_miss_rate::0 0.151746 # miss rate for overall accesses 168system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 169system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 170system.cpu.dcache.overall_misses::0 2536335 # number of overall misses 171system.cpu.dcache.overall_misses::1 0 # number of overall misses 172system.cpu.dcache.overall_misses::total 2536335 # number of overall misses 173system.cpu.dcache.overall_mshr_hits 2117519 # number of overall MSHR hits 174system.cpu.dcache.overall_mshr_miss_latency 9862428484 # number of overall MSHR miss cycles 175system.cpu.dcache.overall_mshr_miss_rate::0 0.025057 # mshr miss rate for overall accesses 176system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 177system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 178system.cpu.dcache.overall_mshr_misses 418816 # number of overall MSHR misses 179system.cpu.dcache.overall_mshr_uncacheable_latency 39131735683 # number of overall MSHR uncacheable cycles 180system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 181system.cpu.dcache.replacements 422122 # number of replacements 182system.cpu.dcache.sampled_refs 422634 # Sample count of references to valid blocks. 183system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 184system.cpu.dcache.tagsinuse 511.755643 # Cycle average of tags in use 185system.cpu.dcache.total_refs 14388654 # Total number of references to valid blocks. 186system.cpu.dcache.warmup_cycle 48260000 # Cycle when the warmup percentage was hit. 187system.cpu.dcache.writebacks 390579 # number of writebacks 188system.cpu.decode.DECODE:BlockedCycles 54500037 # Number of cycles decode is blocked 189system.cpu.decode.DECODE:BranchMispred 71855 # Number of times decode detected a branch misprediction 190system.cpu.decode.DECODE:BranchResolved 1270879 # Number of times decode resolved a branch 191system.cpu.decode.DECODE:DecodedInsts 84249767 # Number of instructions handled by decode 192system.cpu.decode.DECODE:IdleCycles 24736930 # Number of cycles decode is idle 193system.cpu.decode.DECODE:RunCycles 15841745 # Number of cycles decode is running 194system.cpu.decode.DECODE:SquashCycles 3334409 # Number of cycles decode is squashing 195system.cpu.decode.DECODE:SquashedInsts 234983 # Number of squashed instructions handled by decode 196system.cpu.decode.DECODE:UnblockCycles 1146787 # Number of cycles decode is unblocking 197system.cpu.dtb.accesses 36041317 # DTB accesses 198system.cpu.dtb.align_faults 1606 # Number of TLB faults due to alignment restrictions 199system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 200system.cpu.dtb.flush_entries 2757 # Number of entries that have been flushed from TLB 201system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID 203system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 204system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID 205system.cpu.dtb.hits 35961278 # DTB hits 206system.cpu.dtb.inst_accesses 0 # ITB inst accesses 207system.cpu.dtb.inst_hits 0 # ITB inst hits 208system.cpu.dtb.inst_misses 0 # ITB inst misses 209system.cpu.dtb.misses 80039 # DTB misses 210system.cpu.dtb.perms_faults 987 # Number of TLB faults due to permissions restrictions 211system.cpu.dtb.prefetch_faults 1022 # Number of TLB faults due to prefetch 212system.cpu.dtb.read_accesses 28355137 # DTB read accesses 213system.cpu.dtb.read_hits 28285868 # DTB read hits 214system.cpu.dtb.read_misses 69269 # DTB read misses 215system.cpu.dtb.write_accesses 7686180 # DTB write accesses 216system.cpu.dtb.write_hits 7675410 # DTB write hits 217system.cpu.dtb.write_misses 10770 # DTB write misses 218system.cpu.fetch.Branches 14006556 # Number of branches that fetch encountered 219system.cpu.fetch.CacheLines 6998275 # Number of cache lines fetched 220system.cpu.fetch.Cycles 17468426 # Number of cycles fetch has run and was not squashing or blocked 221system.cpu.fetch.IcacheSquashes 310113 # Number of outstanding Icache misses that were squashed 222system.cpu.fetch.Insts 71954338 # Number of instructions fetch has processed 223system.cpu.fetch.ItlbSquashes 4839 # Number of outstanding ITLB misses that were squashed 224system.cpu.fetch.MiscStallCycles 24771 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 225system.cpu.fetch.SquashCycles 1293063 # Number of cycles fetch has spent squashing 226system.cpu.fetch.TlbCycles 7917 # Number of cycles fetch has spent waiting for tlb 227system.cpu.fetch.branchRate 0.082989 # Number of branch fetches per cycle 228system.cpu.fetch.icacheStallCycles 6996896 # Number of cycles fetch is stalled on an Icache miss 229system.cpu.fetch.predictedBranches 10528824 # Number of branches that fetch has predicted taken 230system.cpu.fetch.rate 0.426329 # Number of inst fetches per cycle 231system.cpu.fetch.rateDist::samples 99559908 # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::mean 0.876249 # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::stdev 2.150340 # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::0 82110011 82.47% 82.47% # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::1 1333573 1.34% 83.81% # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::2 1775516 1.78% 85.60% # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::3 1526454 1.53% 87.13% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::4 4859277 4.88% 92.01% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::5 919627 0.92% 92.93% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::6 887823 0.89% 93.83% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::7 767860 0.77% 94.60% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::8 5379767 5.40% 100.00% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::total 99559908 # Number of instructions fetched each cycle (Total) 248system.cpu.fp_regfile_reads 5295 # number of floating regfile reads 249system.cpu.fp_regfile_writes 1908 # number of floating regfile writes 250system.cpu.icache.ReadReq_accesses::0 6998182 # number of ReadReq accesses(hits+misses) 251system.cpu.icache.ReadReq_accesses::total 6998182 # number of ReadReq accesses(hits+misses) 252system.cpu.icache.ReadReq_avg_miss_latency::0 14604.698564 # average ReadReq miss latency 253system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 254system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 255system.cpu.icache.ReadReq_avg_mshr_miss_latency 12005.361734 # average ReadReq mshr miss latency 256system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 257system.cpu.icache.ReadReq_hits::0 6432138 # number of ReadReq hits 258system.cpu.icache.ReadReq_hits::total 6432138 # number of ReadReq hits 259system.cpu.icache.ReadReq_miss_latency 8266901994 # number of ReadReq miss cycles 260system.cpu.icache.ReadReq_miss_rate::0 0.080884 # miss rate for ReadReq accesses 261system.cpu.icache.ReadReq_misses::0 566044 # number of ReadReq misses 262system.cpu.icache.ReadReq_misses::total 566044 # number of ReadReq misses 263system.cpu.icache.ReadReq_mshr_hits 56788 # number of ReadReq MSHR hits 264system.cpu.icache.ReadReq_mshr_miss_latency 6113802495 # number of ReadReq MSHR miss cycles 265system.cpu.icache.ReadReq_mshr_miss_rate::0 0.072770 # mshr miss rate for ReadReq accesses 266system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 267system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_mshr_misses 509256 # number of ReadReq MSHR misses 269system.cpu.icache.ReadReq_mshr_uncacheable_latency 4968000 # number of ReadReq MSHR uncacheable cycles 270system.cpu.icache.avg_blocked_cycles::no_mshrs 6198.435115 # average number of cycles each access was blocked 271system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 272system.cpu.icache.avg_refs 12.630486 # Average number of references to valid blocks. 273system.cpu.icache.blocked::no_mshrs 131 # number of cycles access was blocked 274system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked_cycles::no_mshrs 811995 # number of cycles access was blocked 276system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.cache_copies 0 # number of cache copies performed 278system.cpu.icache.demand_accesses::0 6998182 # number of demand (read+write) accesses 279system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 280system.cpu.icache.demand_accesses::total 6998182 # number of demand (read+write) accesses 281system.cpu.icache.demand_avg_miss_latency::0 14604.698564 # average overall miss latency 282system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 283system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 284system.cpu.icache.demand_avg_mshr_miss_latency 12005.361734 # average overall mshr miss latency 285system.cpu.icache.demand_hits::0 6432138 # number of demand (read+write) hits 286system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 287system.cpu.icache.demand_hits::total 6432138 # number of demand (read+write) hits 288system.cpu.icache.demand_miss_latency 8266901994 # number of demand (read+write) miss cycles 289system.cpu.icache.demand_miss_rate::0 0.080884 # miss rate for demand accesses 290system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 291system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 292system.cpu.icache.demand_misses::0 566044 # number of demand (read+write) misses 293system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 294system.cpu.icache.demand_misses::total 566044 # number of demand (read+write) misses 295system.cpu.icache.demand_mshr_hits 56788 # number of demand (read+write) MSHR hits 296system.cpu.icache.demand_mshr_miss_latency 6113802495 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.demand_mshr_miss_rate::0 0.072770 # mshr miss rate for demand accesses 298system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 299system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 300system.cpu.icache.demand_mshr_misses 509256 # number of demand (read+write) MSHR misses 301system.cpu.icache.fast_writes 0 # number of fast writes performed 302system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 303system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 304system.cpu.icache.occ_%::0 0.968631 # Average percentage of cache occupancy 305system.cpu.icache.occ_blocks::0 495.939326 # Average occupied blocks per context 306system.cpu.icache.overall_accesses::0 6998182 # number of overall (read+write) accesses 307system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 308system.cpu.icache.overall_accesses::total 6998182 # number of overall (read+write) accesses 309system.cpu.icache.overall_avg_miss_latency::0 14604.698564 # average overall miss latency 310system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 311system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 312system.cpu.icache.overall_avg_mshr_miss_latency 12005.361734 # average overall mshr miss latency 313system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 314system.cpu.icache.overall_hits::0 6432138 # number of overall hits 315system.cpu.icache.overall_hits::1 0 # number of overall hits 316system.cpu.icache.overall_hits::total 6432138 # number of overall hits 317system.cpu.icache.overall_miss_latency 8266901994 # number of overall miss cycles 318system.cpu.icache.overall_miss_rate::0 0.080884 # miss rate for overall accesses 319system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 320system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 321system.cpu.icache.overall_misses::0 566044 # number of overall misses 322system.cpu.icache.overall_misses::1 0 # number of overall misses 323system.cpu.icache.overall_misses::total 566044 # number of overall misses 324system.cpu.icache.overall_mshr_hits 56788 # number of overall MSHR hits 325system.cpu.icache.overall_mshr_miss_latency 6113802495 # number of overall MSHR miss cycles 326system.cpu.icache.overall_mshr_miss_rate::0 0.072770 # mshr miss rate for overall accesses 327system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 328system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 329system.cpu.icache.overall_mshr_misses 509256 # number of overall MSHR misses 330system.cpu.icache.overall_mshr_uncacheable_latency 4968000 # number of overall MSHR uncacheable cycles 331system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 332system.cpu.icache.replacements 508743 # number of replacements 333system.cpu.icache.sampled_refs 509255 # Sample count of references to valid blocks. 334system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 335system.cpu.icache.tagsinuse 495.939326 # Cycle average of tags in use 336system.cpu.icache.total_refs 6432138 # Total number of references to valid blocks. 337system.cpu.icache.warmup_cycle 6683845000 # Cycle when the warmup percentage was hit. 338system.cpu.icache.writebacks 41856 # number of writebacks 339system.cpu.idleCycles 69216660 # Total number of cycles that the CPU has spent unscheduled due to idling 340system.cpu.iew.EXEC:branches 10300528 # Number of branches executed 341system.cpu.iew.EXEC:nop 233998 # number of nop insts executed 342system.cpu.iew.EXEC:rate 0.477549 # Inst execution rate 343system.cpu.iew.EXEC:refs 36776263 # number of memory reference insts executed 344system.cpu.iew.EXEC:stores 7992235 # Number of stores executed 345system.cpu.iew.EXEC:swp 0 # number of swp insts executed 346system.cpu.iew.WB:consumers 64109547 # num instructions consuming a value 347system.cpu.iew.WB:count 62439853 # cumulative count of insts written-back 348system.cpu.iew.WB:fanout 0.508921 # average fanout of values written-back 349system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 350system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 351system.cpu.iew.WB:producers 32626666 # num instructions producing a value 352system.cpu.iew.WB:rate 0.369956 # insts written-back per cycle 353system.cpu.iew.WB:sent 79765366 # cumulative count of insts sent to commit 354system.cpu.iew.branchMispredicts 803947 # Number of branch mispredicts detected at execute 355system.cpu.iew.iewBlockCycles 21361717 # Number of cycles IEW is blocking 356system.cpu.iew.iewDispLoadInsts 14069931 # Number of dispatched load instructions 357system.cpu.iew.iewDispNonSpecInsts 4021819 # Number of dispatched non-speculative instructions 358system.cpu.iew.iewDispSquashedInsts 473480 # Number of squashed instructions skipped by dispatch 359system.cpu.iew.iewDispStoreInsts 9383175 # Number of dispatched store instructions 360system.cpu.iew.iewDispatchedInsts 75615816 # Number of instructions dispatched to IQ 361system.cpu.iew.iewExecLoadInsts 28784028 # Number of load instructions executed 362system.cpu.iew.iewExecSquashedInsts 1481918 # Number of squashed instructions skipped in execute 363system.cpu.iew.iewExecutedInsts 80599112 # Number of executed instructions 364system.cpu.iew.iewIQFullEvents 30204 # Number of times the IQ has become full, causing a stall 365system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 366system.cpu.iew.iewLSQFullEvents 45946 # Number of times the LSQ has become full, causing a stall 367system.cpu.iew.iewSquashCycles 3334409 # Number of cycles IEW is squashing 368system.cpu.iew.iewUnblockCycles 259259 # Number of cycles IEW is unblocking 369system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 370system.cpu.iew.lsq.thread.0.cacheBlocked 8096 # Number of times an access to memory failed due to the cache being blocked 371system.cpu.iew.lsq.thread.0.forwLoads 314225 # Number of loads that had data forwarded from stores 372system.cpu.iew.lsq.thread.0.ignoredResponses 20180 # Number of memory responses ignored because the instruction is squashed 373system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 374system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 375system.cpu.iew.lsq.thread.0.memOrderViolation 524894 # Number of memory ordering violations 376system.cpu.iew.lsq.thread.0.rescheduledLoads 17006252 # Number of loads that were rescheduled 377system.cpu.iew.lsq.thread.0.squashedLoads 4861327 # Number of loads squashed 378system.cpu.iew.lsq.thread.0.squashedStores 2299281 # Number of stores squashed 379system.cpu.iew.memOrderViolationEvents 524894 # Number of memory order violations 380system.cpu.iew.predictedNotTakenIncorrect 291334 # Number of branches that were predicted not taken incorrectly 381system.cpu.iew.predictedTakenIncorrect 512613 # Number of branches that were predicted taken incorrectly 382system.cpu.int_regfile_reads 187216676 # number of integer regfile reads 383system.cpu.int_regfile_writes 45171594 # number of integer regfile writes 384system.cpu.ipc 0.307871 # IPC: Instructions Per Cycle 385system.cpu.ipc_total 0.307871 # IPC: Total IPC of All Threads 386system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 2.92% 2.92% # Type of FU issued 387system.cpu.iq.ISSUE:FU_type_0::IntAlu 42044414 51.22% 54.14% # Type of FU issued 388system.cpu.iq.ISSUE:FU_type_0::IntMult 91848 0.11% 54.25% # Type of FU issued 389system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.25% # Type of FU issued 390system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.25% # Type of FU issued 391system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.25% # Type of FU issued 392system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.25% # Type of FU issued 393system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.25% # Type of FU issued 394system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.25% # Type of FU issued 395system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.25% # Type of FU issued 396system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.25% # Type of FU issued 397system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.25% # Type of FU issued 398system.cpu.iq.ISSUE:FU_type_0::SimdAlu 12 0.00% 54.25% # Type of FU issued 399system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.25% # Type of FU issued 400system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.25% # Type of FU issued 401system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.25% # Type of FU issued 402system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.25% # Type of FU issued 403system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.25% # Type of FU issued 404system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.25% # Type of FU issued 405system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 7 0.00% 54.25% # Type of FU issued 406system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.25% # Type of FU issued 407system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.25% # Type of FU issued 408system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.25% # Type of FU issued 409system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.25% # Type of FU issued 410system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.25% # Type of FU issued 411system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.25% # Type of FU issued 412system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 869 0.00% 54.25% # Type of FU issued 413system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.25% # Type of FU issued 414system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7 0.00% 54.25% # Type of FU issued 415system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.25% # Type of FU issued 416system.cpu.iq.ISSUE:FU_type_0::MemRead 29326853 35.73% 89.98% # Type of FU issued 417system.cpu.iq.ISSUE:FU_type_0::MemWrite 8224069 10.02% 100.00% # Type of FU issued 418system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 419system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 420system.cpu.iq.ISSUE:FU_type_0::total 82081030 # Type of FU issued 421system.cpu.iq.ISSUE:fu_busy_cnt 4843845 # FU busy when requested 422system.cpu.iq.ISSUE:fu_busy_rate 0.059013 # FU busy rate (busy events/executed inst) 423system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 424system.cpu.iq.ISSUE:fu_full::IntAlu 4773 0.10% 0.10% # attempts to use FU when none available 425system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 0.10% # attempts to use FU when none available 426system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available 427system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available 428system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.10% # attempts to use FU when none available 429system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.10% # attempts to use FU when none available 430system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.10% # attempts to use FU when none available 431system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.10% # attempts to use FU when none available 432system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.10% # attempts to use FU when none available 433system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.10% # attempts to use FU when none available 434system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.10% # attempts to use FU when none available 435system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.10% # attempts to use FU when none available 436system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.10% # attempts to use FU when none available 437system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.10% # attempts to use FU when none available 438system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.10% # attempts to use FU when none available 439system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.10% # attempts to use FU when none available 440system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.10% # attempts to use FU when none available 441system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.10% # attempts to use FU when none available 442system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.10% # attempts to use FU when none available 443system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.10% # attempts to use FU when none available 444system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.10% # attempts to use FU when none available 445system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available 446system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.10% # attempts to use FU when none available 447system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.10% # attempts to use FU when none available 448system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.10% # attempts to use FU when none available 449system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.10% # attempts to use FU when none available 450system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available 451system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available 452system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available 453system.cpu.iq.ISSUE:fu_full::MemRead 4516251 93.24% 93.34% # attempts to use FU when none available 454system.cpu.iq.ISSUE:fu_full::MemWrite 322820 6.66% 100.00% # attempts to use FU when none available 455system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 456system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 457system.cpu.iq.ISSUE:issued_per_cycle::samples 99559908 # Number of insts issued each cycle 458system.cpu.iq.ISSUE:issued_per_cycle::mean 0.824439 # Number of insts issued each cycle 459system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384503 # Number of insts issued each cycle 460system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 461system.cpu.iq.ISSUE:issued_per_cycle::0 62623940 62.90% 62.90% # Number of insts issued each cycle 462system.cpu.iq.ISSUE:issued_per_cycle::1 16850481 16.92% 79.83% # Number of insts issued each cycle 463system.cpu.iq.ISSUE:issued_per_cycle::2 7354837 7.39% 87.21% # Number of insts issued each cycle 464system.cpu.iq.ISSUE:issued_per_cycle::3 4227768 4.25% 91.46% # Number of insts issued each cycle 465system.cpu.iq.ISSUE:issued_per_cycle::4 6061654 6.09% 97.55% # Number of insts issued each cycle 466system.cpu.iq.ISSUE:issued_per_cycle::5 1452072 1.46% 99.01% # Number of insts issued each cycle 467system.cpu.iq.ISSUE:issued_per_cycle::6 668981 0.67% 99.68% # Number of insts issued each cycle 468system.cpu.iq.ISSUE:issued_per_cycle::7 244691 0.25% 99.92% # Number of insts issued each cycle 469system.cpu.iq.ISSUE:issued_per_cycle::8 75484 0.08% 100.00% # Number of insts issued each cycle 470system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 471system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 472system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 473system.cpu.iq.ISSUE:issued_per_cycle::total 99559908 # Number of insts issued each cycle 474system.cpu.iq.ISSUE:rate 0.486330 # Inst issue rate 475system.cpu.iq.fp_alu_accesses 8335 # Number of floating point alu accesses 476system.cpu.iq.fp_inst_queue_reads 15849 # Number of floating instruction queue reads 477system.cpu.iq.fp_inst_queue_wakeup_accesses 6220 # Number of floating instruction queue wakeup accesses 478system.cpu.iq.fp_inst_queue_writes 8867 # Number of floating instruction queue writes 479system.cpu.iq.int_alu_accesses 84523589 # Number of integer alu accesses 480system.cpu.iq.int_inst_queue_reads 268809983 # Number of integer instruction queue reads 481system.cpu.iq.int_inst_queue_wakeup_accesses 62433633 # Number of integer instruction queue wakeup accesses 482system.cpu.iq.int_inst_queue_writes 98520423 # Number of integer instruction queue writes 483system.cpu.iq.iqInstsAdded 71330415 # Number of instructions added to the IQ (excludes non-spec) 484system.cpu.iq.iqInstsIssued 82081030 # Number of instructions issued 485system.cpu.iq.iqNonSpecInstsAdded 4051403 # Number of non-speculative instructions added to the IQ 486system.cpu.iq.iqSquashedInstsExamined 22670381 # Number of squashed instructions iterated over during squash; mainly for profiling 487system.cpu.iq.iqSquashedInstsIssued 180259 # Number of squashed instructions issued 488system.cpu.iq.iqSquashedNonSpecRemoved 1088826 # Number of squashed non-spec instructions that were removed 489system.cpu.iq.iqSquashedOperandsExamined 31630143 # Number of squashed operands that are examined and possibly removed from graph 490system.cpu.itb.accesses 7013299 # DTB accesses 491system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 492system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 493system.cpu.itb.flush_entries 1597 # Number of entries that have been flushed from TLB 494system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 495system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID 496system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 497system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID 498system.cpu.itb.hits 7005382 # DTB hits 499system.cpu.itb.inst_accesses 7013299 # ITB inst accesses 500system.cpu.itb.inst_hits 7005382 # ITB inst hits 501system.cpu.itb.inst_misses 7917 # ITB inst misses 502system.cpu.itb.misses 7917 # DTB misses 503system.cpu.itb.perms_faults 6664 # Number of TLB faults due to permissions restrictions 504system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 505system.cpu.itb.read_accesses 0 # DTB read accesses 506system.cpu.itb.read_hits 0 # DTB read hits 507system.cpu.itb.read_misses 0 # DTB read misses 508system.cpu.itb.write_accesses 0 # DTB write accesses 509system.cpu.itb.write_hits 0 # DTB write hits 510system.cpu.itb.write_misses 0 # DTB write misses 511system.cpu.kern.inst.arm 0 # number of arm instructions executed 512system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 513system.cpu.memDep0.conflictingLoads 10842 # Number of conflicting loads. 514system.cpu.memDep0.conflictingStores 21645 # Number of conflicting stores. 515system.cpu.memDep0.insertedLoads 14069931 # Number of loads inserted to the mem dependence unit. 516system.cpu.memDep0.insertedStores 9383175 # Number of stores inserted to the mem dependence unit. 517system.cpu.misc_regfile_reads 92602547 # number of misc regfile reads 518system.cpu.misc_regfile_writes 661893 # number of misc regfile writes 519system.cpu.numCycles 168776568 # number of cpu cycles simulated 520system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 521system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 522system.cpu.rename.RENAME:BlockCycles 32961979 # Number of cycles rename is blocking 523system.cpu.rename.RENAME:CommittedMaps 36893255 # Number of HB maps that are committed 524system.cpu.rename.RENAME:IQFullEvents 568385 # Number of times rename has blocked due to IQ full 525system.cpu.rename.RENAME:IdleCycles 26505270 # Number of cycles rename is idle 526system.cpu.rename.RENAME:LSQFullEvents 2459966 # Number of times rename has blocked due to LSQ full 527system.cpu.rename.RENAME:ROBFullEvents 448573 # Number of times rename has blocked due to ROB full 528system.cpu.rename.RENAME:RenameLookups 208179443 # Number of register rename lookups that rename has made 529system.cpu.rename.RENAME:RenamedInsts 80158855 # Number of instructions processed by rename 530system.cpu.rename.RENAME:RenamedOperands 58599384 # Number of destination operands rename has renamed 531system.cpu.rename.RENAME:RunCycles 14253451 # Number of cycles rename is running 532system.cpu.rename.RENAME:SquashCycles 3334409 # Number of cycles rename is squashing 533system.cpu.rename.RENAME:UnblockCycles 5274094 # Number of cycles rename is unblocking 534system.cpu.rename.RENAME:UndoneMaps 21706128 # Number of HB maps that are undone due to squashing 535system.cpu.rename.RENAME:fp_rename_lookups 46818 # Number of floating rename lookups 536system.cpu.rename.RENAME:int_rename_lookups 208132625 # Number of integer rename lookups 537system.cpu.rename.RENAME:serializeStallCycles 17230705 # count of cycles rename stalled for serializing inst 538system.cpu.rename.RENAME:serializingInsts 870043 # count of serializing insts renamed 539system.cpu.rename.RENAME:skidInsts 14712923 # count of insts added to the skid buffer 540system.cpu.rename.RENAME:tempSerializingInsts 727497 # count of temporary serializing insts renamed 541system.cpu.rob.rob_reads 167920116 # The number of ROB reads 542system.cpu.rob.rob_writes 150187680 # The number of ROB writes 543system.cpu.timesIdled 1086772 # Number of times that the entire CPU went into an idle state and unscheduled itself 544system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 545system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 546system.iocache.avg_refs no_value # Average number of references to valid blocks. 547system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.iocache.blocked::no_targets 0 # number of cycles access was blocked 549system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 550system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 551system.iocache.cache_copies 0 # number of cache copies performed 552system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 553system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 554system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 555system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 556system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 557system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 558system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 559system.iocache.demand_hits::0 0 # number of demand (read+write) hits 560system.iocache.demand_hits::1 0 # number of demand (read+write) hits 561system.iocache.demand_hits::total 0 # number of demand (read+write) hits 562system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 563system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 564system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 565system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 566system.iocache.demand_misses::0 0 # number of demand (read+write) misses 567system.iocache.demand_misses::1 0 # number of demand (read+write) misses 568system.iocache.demand_misses::total 0 # number of demand (read+write) misses 569system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 570system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 571system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 572system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 573system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 574system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 575system.iocache.fast_writes 0 # number of fast writes performed 576system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 577system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 578system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 579system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 580system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 581system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 582system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 583system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 584system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 585system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 586system.iocache.overall_hits::0 0 # number of overall hits 587system.iocache.overall_hits::1 0 # number of overall hits 588system.iocache.overall_hits::total 0 # number of overall hits 589system.iocache.overall_miss_latency 0 # number of overall miss cycles 590system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 591system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 592system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 593system.iocache.overall_misses::0 0 # number of overall misses 594system.iocache.overall_misses::1 0 # number of overall misses 595system.iocache.overall_misses::total 0 # number of overall misses 596system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 597system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 598system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 599system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 600system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 601system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 602system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 603system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 604system.iocache.replacements 0 # number of replacements 605system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 606system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 607system.iocache.tagsinuse 0 # Cycle average of tags in use 608system.iocache.total_refs 0 # Total number of references to valid blocks. 609system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 610system.iocache.writebacks 0 # number of writebacks 611system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency 612system.l2c.LoadLockedReq_mshr_uncacheable_latency 234163500 # number of LoadLockedReq MSHR uncacheable cycles 613system.l2c.ReadExReq_accesses::0 168750 # number of ReadExReq accesses(hits+misses) 614system.l2c.ReadExReq_accesses::total 168750 # number of ReadExReq accesses(hits+misses) 615system.l2c.ReadExReq_avg_miss_latency::0 52449.907829 # average ReadExReq miss latency 616system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 617system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 618system.l2c.ReadExReq_avg_mshr_miss_latency 40012.010079 # average ReadExReq mshr miss latency 619system.l2c.ReadExReq_hits::0 60799 # number of ReadExReq hits 620system.l2c.ReadExReq_hits::total 60799 # number of ReadExReq hits 621system.l2c.ReadExReq_miss_latency 5662020000 # number of ReadExReq miss cycles 622system.l2c.ReadExReq_miss_rate::0 0.639710 # miss rate for ReadExReq accesses 623system.l2c.ReadExReq_misses::0 107951 # number of ReadExReq misses 624system.l2c.ReadExReq_misses::total 107951 # number of ReadExReq misses 625system.l2c.ReadExReq_mshr_miss_latency 4319336500 # number of ReadExReq MSHR miss cycles 626system.l2c.ReadExReq_mshr_miss_rate::0 0.639710 # mshr miss rate for ReadExReq accesses 627system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 628system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 629system.l2c.ReadExReq_mshr_misses 107951 # number of ReadExReq MSHR misses 630system.l2c.ReadReq_accesses::0 760723 # number of ReadReq accesses(hits+misses) 631system.l2c.ReadReq_accesses::1 115478 # number of ReadReq accesses(hits+misses) 632system.l2c.ReadReq_accesses::total 876201 # number of ReadReq accesses(hits+misses) 633system.l2c.ReadReq_avg_miss_latency::0 52673.934298 # average ReadReq miss latency 634system.l2c.ReadReq_avg_miss_latency::1 6776716.981132 # average ReadReq miss latency 635system.l2c.ReadReq_avg_miss_latency::total 6829390.915430 # average ReadReq miss latency 636system.l2c.ReadReq_avg_mshr_miss_latency 40041.287971 # average ReadReq mshr miss latency 637system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 638system.l2c.ReadReq_hits::0 740267 # number of ReadReq hits 639system.l2c.ReadReq_hits::1 115319 # number of ReadReq hits 640system.l2c.ReadReq_hits::total 855586 # number of ReadReq hits 641system.l2c.ReadReq_miss_latency 1077498000 # number of ReadReq miss cycles 642system.l2c.ReadReq_miss_rate::0 0.026890 # miss rate for ReadReq accesses 643system.l2c.ReadReq_miss_rate::1 0.001377 # miss rate for ReadReq accesses 644system.l2c.ReadReq_miss_rate::total 0.028267 # miss rate for ReadReq accesses 645system.l2c.ReadReq_misses::0 20456 # number of ReadReq misses 646system.l2c.ReadReq_misses::1 159 # number of ReadReq misses 647system.l2c.ReadReq_misses::total 20615 # number of ReadReq misses 648system.l2c.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits 649system.l2c.ReadReq_mshr_miss_latency 823849500 # number of ReadReq MSHR miss cycles 650system.l2c.ReadReq_mshr_miss_rate::0 0.027047 # mshr miss rate for ReadReq accesses 651system.l2c.ReadReq_mshr_miss_rate::1 0.178172 # mshr miss rate for ReadReq accesses 652system.l2c.ReadReq_mshr_miss_rate::total 0.205219 # mshr miss rate for ReadReq accesses 653system.l2c.ReadReq_mshr_misses 20575 # number of ReadReq MSHR misses 654system.l2c.ReadReq_mshr_uncacheable_latency 28940574500 # number of ReadReq MSHR uncacheable cycles 655system.l2c.UpgradeReq_accesses::0 1755 # number of UpgradeReq accesses(hits+misses) 656system.l2c.UpgradeReq_accesses::total 1755 # number of UpgradeReq accesses(hits+misses) 657system.l2c.UpgradeReq_avg_miss_latency::0 785.423926 # average UpgradeReq miss latency 658system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 659system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 660system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.580720 # average UpgradeReq mshr miss latency 661system.l2c.UpgradeReq_hits::0 33 # number of UpgradeReq hits 662system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits 663system.l2c.UpgradeReq_miss_latency 1352500 # number of UpgradeReq miss cycles 664system.l2c.UpgradeReq_miss_rate::0 0.981197 # miss rate for UpgradeReq accesses 665system.l2c.UpgradeReq_misses::0 1722 # number of UpgradeReq misses 666system.l2c.UpgradeReq_misses::total 1722 # number of UpgradeReq misses 667system.l2c.UpgradeReq_mshr_miss_latency 68881000 # number of UpgradeReq MSHR miss cycles 668system.l2c.UpgradeReq_mshr_miss_rate::0 0.981197 # mshr miss rate for UpgradeReq accesses 669system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 670system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 671system.l2c.UpgradeReq_mshr_misses 1722 # number of UpgradeReq MSHR misses 672system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 673system.l2c.WriteReq_mshr_uncacheable_latency 746022447 # number of WriteReq MSHR uncacheable cycles 674system.l2c.Writeback_accesses::0 432435 # number of Writeback accesses(hits+misses) 675system.l2c.Writeback_accesses::total 432435 # number of Writeback accesses(hits+misses) 676system.l2c.Writeback_hits::0 432435 # number of Writeback hits 677system.l2c.Writeback_hits::total 432435 # number of Writeback hits 678system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 679system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 680system.l2c.avg_refs 8.330108 # Average number of references to valid blocks. 681system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 682system.l2c.blocked::no_targets 0 # number of cycles access was blocked 683system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 684system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 685system.l2c.cache_copies 0 # number of cache copies performed 686system.l2c.demand_accesses::0 929473 # number of demand (read+write) accesses 687system.l2c.demand_accesses::1 115478 # number of demand (read+write) accesses 688system.l2c.demand_accesses::total 1044951 # number of demand (read+write) accesses 689system.l2c.demand_avg_miss_latency::0 52485.596580 # average overall miss latency 690system.l2c.demand_avg_miss_latency::1 42386905.660377 # average overall miss latency 691system.l2c.demand_avg_miss_latency::total 42439391.256957 # average overall miss latency 692system.l2c.demand_avg_mshr_miss_latency 40016.697011 # average overall mshr miss latency 693system.l2c.demand_hits::0 801066 # number of demand (read+write) hits 694system.l2c.demand_hits::1 115319 # number of demand (read+write) hits 695system.l2c.demand_hits::total 916385 # number of demand (read+write) hits 696system.l2c.demand_miss_latency 6739518000 # number of demand (read+write) miss cycles 697system.l2c.demand_miss_rate::0 0.138150 # miss rate for demand accesses 698system.l2c.demand_miss_rate::1 0.001377 # miss rate for demand accesses 699system.l2c.demand_miss_rate::total 0.139527 # miss rate for demand accesses 700system.l2c.demand_misses::0 128407 # number of demand (read+write) misses 701system.l2c.demand_misses::1 159 # number of demand (read+write) misses 702system.l2c.demand_misses::total 128566 # number of demand (read+write) misses 703system.l2c.demand_mshr_hits 40 # number of demand (read+write) MSHR hits 704system.l2c.demand_mshr_miss_latency 5143186000 # number of demand (read+write) MSHR miss cycles 705system.l2c.demand_mshr_miss_rate::0 0.138278 # mshr miss rate for demand accesses 706system.l2c.demand_mshr_miss_rate::1 1.112991 # mshr miss rate for demand accesses 707system.l2c.demand_mshr_miss_rate::total 1.251270 # mshr miss rate for demand accesses 708system.l2c.demand_mshr_misses 128526 # number of demand (read+write) MSHR misses 709system.l2c.fast_writes 0 # number of fast writes performed 710system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 711system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 712system.l2c.occ_%::0 0.099103 # Average percentage of cache occupancy 713system.l2c.occ_%::1 0.480856 # Average percentage of cache occupancy 714system.l2c.occ_blocks::0 6494.821877 # Average occupied blocks per context 715system.l2c.occ_blocks::1 31513.354871 # Average occupied blocks per context 716system.l2c.overall_accesses::0 929473 # number of overall (read+write) accesses 717system.l2c.overall_accesses::1 115478 # number of overall (read+write) accesses 718system.l2c.overall_accesses::total 1044951 # number of overall (read+write) accesses 719system.l2c.overall_avg_miss_latency::0 52485.596580 # average overall miss latency 720system.l2c.overall_avg_miss_latency::1 42386905.660377 # average overall miss latency 721system.l2c.overall_avg_miss_latency::total 42439391.256957 # average overall miss latency 722system.l2c.overall_avg_mshr_miss_latency 40016.697011 # average overall mshr miss latency 723system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 724system.l2c.overall_hits::0 801066 # number of overall hits 725system.l2c.overall_hits::1 115319 # number of overall hits 726system.l2c.overall_hits::total 916385 # number of overall hits 727system.l2c.overall_miss_latency 6739518000 # number of overall miss cycles 728system.l2c.overall_miss_rate::0 0.138150 # miss rate for overall accesses 729system.l2c.overall_miss_rate::1 0.001377 # miss rate for overall accesses 730system.l2c.overall_miss_rate::total 0.139527 # miss rate for overall accesses 731system.l2c.overall_misses::0 128407 # number of overall misses 732system.l2c.overall_misses::1 159 # number of overall misses 733system.l2c.overall_misses::total 128566 # number of overall misses 734system.l2c.overall_mshr_hits 40 # number of overall MSHR hits 735system.l2c.overall_mshr_miss_latency 5143186000 # number of overall MSHR miss cycles 736system.l2c.overall_mshr_miss_rate::0 0.138278 # mshr miss rate for overall accesses 737system.l2c.overall_mshr_miss_rate::1 1.112991 # mshr miss rate for overall accesses 738system.l2c.overall_mshr_miss_rate::total 1.251270 # mshr miss rate for overall accesses 739system.l2c.overall_mshr_misses 128526 # number of overall MSHR misses 740system.l2c.overall_mshr_uncacheable_latency 29686596947 # number of overall MSHR uncacheable cycles 741system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 742system.l2c.replacements 94872 # number of replacements 743system.l2c.sampled_refs 127034 # Sample count of references to valid blocks. 744system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 745system.l2c.tagsinuse 38008.176748 # Cycle average of tags in use 746system.l2c.total_refs 1058207 # Total number of references to valid blocks. 747system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 748system.l2c.writebacks 87774 # number of writebacks 749 750---------- End Simulation Statistics ---------- 751