simerr revision 11570
110513SAli.Saidi@ARM.comwarn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) 28150SN/Awarn: Sockets disabled, not accepting vnc client connections 38150SN/Awarn: Sockets disabled, not accepting terminal connections 48150SN/Awarn: Sockets disabled, not accepting gdb connections 511570SCurtis.Dunham@arm.comwarn: ClockedObject: More than one power state change request encountered within the same simulation tick 610451Snilay@cs.wisc.eduwarn: Existing EnergyCtrl, but no enabled DVFSHandler found. 710513SAli.Saidi@ARM.comwarn: Not doing anything for miscreg ACTLR 810513SAli.Saidi@ARM.comwarn: Not doing anything for write of miscreg ACTLR 98150SN/Awarn: The clidr register always reports 0 caches. 108470SN/Awarn: clidr LoUIS field of 0b001 to match current ARM implementations. 118150SN/Awarn: The csselr register isn't implemented. 1210513SAli.Saidi@ARM.comwarn: instruction 'mcr dccmvau' unimplemented 1310513SAli.Saidi@ARM.comwarn: instruction 'mcr icimvau' unimplemented 148528SN/Awarn: instruction 'mcr bpiallis' unimplemented 158528SN/Awarn: instruction 'mcr icialluis' unimplemented 168150SN/Awarn: instruction 'mcr dccimvac' unimplemented 1710513SAli.Saidi@ARM.comwarn: Tried to read RealView I/O at offset 0x60 that doesn't exist 1810513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 1910513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2010513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2110513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2210513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2310513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2410513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2510513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2610513SAli.Saidi@ARM.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist 2710513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] 2810513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] 2910513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] 3010513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] 3110513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] 3210513SAli.Saidi@ARM.comwarn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] 3310513SAli.Saidi@ARM.comwarn: Returning zero for read from miscreg pmcr 3410513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcntenclr 3510513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmintenclr 3610513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmovsr 3710513SAli.Saidi@ARM.comwarn: Ignoring write to miscreg pmcr 3810798Ssteve.reinhardt@amd.comwarn: instruction 'mcr dcisw' unimplemented 3910513SAli.Saidi@ARM.comwarn: instruction 'mcr bpiall' unimplemented 40