config.ini revision 8835:7c68f84d7c4e
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver 12boot_loader=/dist/m5/system/binaries/boot.arm 13boot_loader_mem=system.nvmem 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15flags_addr=268435504 16gic_cpu_addr=520093952 17init_param=0 18kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 19load_addr_mask=268435455 20machine_type=RealView_PBX 21mem_mode=timing 22memories=system.nvmem system.physmem 23midr_regval=890224640 24num_work_ids=16 25physmem=system.physmem 26readfile=tests/halt.sh 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.port[7] 36 37[system.bridge] 38type=Bridge 39delay=50000 40nack_delay=4000 41ranges=268435456:520093695 1073741824:18446744073709551615 42req_size=16 43resp_size=16 44write_ack=false 45master=system.iobus.port[0] 46slave=system.membus.port[0] 47 48[system.cf0] 49type=IdeDisk 50children=image 51delay=1000000 52driveID=master 53image=system.cf0.image 54 55[system.cf0.image] 56type=CowDiskImage 57children=child 58child=system.cf0.image.child 59image_file= 60read_only=false 61table_size=65536 62 63[system.cf0.image.child] 64type=RawDiskImage 65image_file=/dist/m5/system/disks/linux-arm-ael.img 66read_only=true 67 68[system.cpu] 69type=DerivO3CPU 70children=dcache dtb fuPool icache interrupts itb tracer 71BTBEntries=4096 72BTBTagSize=16 73LFSTSize=1024 74LQEntries=32 75LSQCheckLoads=true 76LSQDepCheckShift=4 77RASSize=16 78SQEntries=32 79SSITSize=1024 80activity=0 81backComSize=5 82cachePorts=200 83checker=Null 84choiceCtrBits=2 85choicePredictorSize=8192 86clock=500 87commitToDecodeDelay=1 88commitToFetchDelay=1 89commitToIEWDelay=1 90commitToRenameDelay=1 91commitWidth=8 92cpu_id=0 93decodeToFetchDelay=1 94decodeToRenameDelay=1 95decodeWidth=8 96defer_registration=false 97dispatchWidth=8 98do_checkpoint_insts=true 99do_quiesce=true 100do_statistics_insts=true 101dtb=system.cpu.dtb 102fetchToDecodeDelay=1 103fetchTrapLatency=1 104fetchWidth=8 105forwardComSize=5 106fuPool=system.cpu.fuPool 107function_trace=false 108function_trace_start=0 109globalCtrBits=2 110globalHistoryBits=13 111globalPredictorSize=8192 112iewToCommitDelay=1 113iewToDecodeDelay=1 114iewToFetchDelay=1 115iewToRenameDelay=1 116instShiftAmt=2 117interrupts=system.cpu.interrupts 118issueToExecuteDelay=1 119issueWidth=8 120itb=system.cpu.itb 121localCtrBits=2 122localHistoryBits=11 123localHistoryTableSize=2048 124localPredictorSize=2048 125max_insts_all_threads=0 126max_insts_any_thread=0 127max_loads_all_threads=0 128max_loads_any_thread=0 129needsTSO=false 130numIQEntries=64 131numPhysFloatRegs=256 132numPhysIntRegs=256 133numROBEntries=192 134numRobs=1 135numThreads=1 136phase=0 137predType=tournament 138profile=0 139progress_interval=0 140renameToDecodeDelay=1 141renameToFetchDelay=1 142renameToIEWDelay=2 143renameToROBDelay=1 144renameWidth=8 145smtCommitPolicy=RoundRobin 146smtFetchPolicy=SingleThread 147smtIQPolicy=Partitioned 148smtIQThreshold=100 149smtLSQPolicy=Partitioned 150smtLSQThreshold=100 151smtNumFetchingThreads=1 152smtROBPolicy=Partitioned 153smtROBThreshold=100 154squashWidth=8 155store_set_clear_period=250000 156system=system 157tracer=system.cpu.tracer 158trapLatency=13 159wbDepth=1 160wbWidth=8 161workload= 162dcache_port=system.cpu.dcache.cpu_side 163icache_port=system.cpu.icache.cpu_side 164 165[system.cpu.dcache] 166type=BaseCache 167addr_range=0:18446744073709551615 168assoc=4 169block_size=64 170forward_snoops=true 171hash_delay=1 172is_top_level=true 173latency=1000 174max_miss_count=0 175mshrs=4 176prefetch_on_access=false 177prefetcher=Null 178prioritizeRequests=false 179repl=Null 180size=32768 181subblock_size=0 182system=system 183tgts_per_mshr=20 184trace_addr=0 185two_queue=false 186write_buffers=8 187cpu_side=system.cpu.dcache_port 188mem_side=system.toL2Bus.port[2] 189 190[system.cpu.dtb] 191type=ArmTLB 192children=walker 193size=64 194walker=system.cpu.dtb.walker 195 196[system.cpu.dtb.walker] 197type=ArmTableWalker 198max_backoff=100000 199min_backoff=0 200sys=system 201port=system.toL2Bus.port[4] 202 203[system.cpu.fuPool] 204type=FUPool 205children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 206FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 207 208[system.cpu.fuPool.FUList0] 209type=FUDesc 210children=opList 211count=6 212opList=system.cpu.fuPool.FUList0.opList 213 214[system.cpu.fuPool.FUList0.opList] 215type=OpDesc 216issueLat=1 217opClass=IntAlu 218opLat=1 219 220[system.cpu.fuPool.FUList1] 221type=FUDesc 222children=opList0 opList1 223count=2 224opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 225 226[system.cpu.fuPool.FUList1.opList0] 227type=OpDesc 228issueLat=1 229opClass=IntMult 230opLat=3 231 232[system.cpu.fuPool.FUList1.opList1] 233type=OpDesc 234issueLat=19 235opClass=IntDiv 236opLat=20 237 238[system.cpu.fuPool.FUList2] 239type=FUDesc 240children=opList0 opList1 opList2 241count=4 242opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 243 244[system.cpu.fuPool.FUList2.opList0] 245type=OpDesc 246issueLat=1 247opClass=FloatAdd 248opLat=2 249 250[system.cpu.fuPool.FUList2.opList1] 251type=OpDesc 252issueLat=1 253opClass=FloatCmp 254opLat=2 255 256[system.cpu.fuPool.FUList2.opList2] 257type=OpDesc 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 267 268[system.cpu.fuPool.FUList3.opList0] 269type=OpDesc 270issueLat=1 271opClass=FloatMult 272opLat=4 273 274[system.cpu.fuPool.FUList3.opList1] 275type=OpDesc 276issueLat=12 277opClass=FloatDiv 278opLat=12 279 280[system.cpu.fuPool.FUList3.opList2] 281type=OpDesc 282issueLat=24 283opClass=FloatSqrt 284opLat=24 285 286[system.cpu.fuPool.FUList4] 287type=FUDesc 288children=opList 289count=0 290opList=system.cpu.fuPool.FUList4.opList 291 292[system.cpu.fuPool.FUList4.opList] 293type=OpDesc 294issueLat=1 295opClass=MemRead 296opLat=1 297 298[system.cpu.fuPool.FUList5] 299type=FUDesc 300children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 301count=4 302opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 303 304[system.cpu.fuPool.FUList5.opList00] 305type=OpDesc 306issueLat=1 307opClass=SimdAdd 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList01] 311type=OpDesc 312issueLat=1 313opClass=SimdAddAcc 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList02] 317type=OpDesc 318issueLat=1 319opClass=SimdAlu 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList03] 323type=OpDesc 324issueLat=1 325opClass=SimdCmp 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList04] 329type=OpDesc 330issueLat=1 331opClass=SimdCvt 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList05] 335type=OpDesc 336issueLat=1 337opClass=SimdMisc 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList06] 341type=OpDesc 342issueLat=1 343opClass=SimdMult 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList07] 347type=OpDesc 348issueLat=1 349opClass=SimdMultAcc 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList08] 353type=OpDesc 354issueLat=1 355opClass=SimdShift 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList09] 359type=OpDesc 360issueLat=1 361opClass=SimdShiftAcc 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList10] 365type=OpDesc 366issueLat=1 367opClass=SimdSqrt 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList11] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatAdd 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList12] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatAlu 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList13] 383type=OpDesc 384issueLat=1 385opClass=SimdFloatCmp 386opLat=1 387 388[system.cpu.fuPool.FUList5.opList14] 389type=OpDesc 390issueLat=1 391opClass=SimdFloatCvt 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList15] 395type=OpDesc 396issueLat=1 397opClass=SimdFloatDiv 398opLat=1 399 400[system.cpu.fuPool.FUList5.opList16] 401type=OpDesc 402issueLat=1 403opClass=SimdFloatMisc 404opLat=1 405 406[system.cpu.fuPool.FUList5.opList17] 407type=OpDesc 408issueLat=1 409opClass=SimdFloatMult 410opLat=1 411 412[system.cpu.fuPool.FUList5.opList18] 413type=OpDesc 414issueLat=1 415opClass=SimdFloatMultAcc 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList19] 419type=OpDesc 420issueLat=1 421opClass=SimdFloatSqrt 422opLat=1 423 424[system.cpu.fuPool.FUList6] 425type=FUDesc 426children=opList 427count=0 428opList=system.cpu.fuPool.FUList6.opList 429 430[system.cpu.fuPool.FUList6.opList] 431type=OpDesc 432issueLat=1 433opClass=MemWrite 434opLat=1 435 436[system.cpu.fuPool.FUList7] 437type=FUDesc 438children=opList0 opList1 439count=4 440opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 441 442[system.cpu.fuPool.FUList7.opList0] 443type=OpDesc 444issueLat=1 445opClass=MemRead 446opLat=1 447 448[system.cpu.fuPool.FUList7.opList1] 449type=OpDesc 450issueLat=1 451opClass=MemWrite 452opLat=1 453 454[system.cpu.fuPool.FUList8] 455type=FUDesc 456children=opList 457count=1 458opList=system.cpu.fuPool.FUList8.opList 459 460[system.cpu.fuPool.FUList8.opList] 461type=OpDesc 462issueLat=3 463opClass=IprAccess 464opLat=3 465 466[system.cpu.icache] 467type=BaseCache 468addr_range=0:18446744073709551615 469assoc=1 470block_size=64 471forward_snoops=true 472hash_delay=1 473is_top_level=true 474latency=1000 475max_miss_count=0 476mshrs=4 477prefetch_on_access=false 478prefetcher=Null 479prioritizeRequests=false 480repl=Null 481size=32768 482subblock_size=0 483system=system 484tgts_per_mshr=20 485trace_addr=0 486two_queue=false 487write_buffers=8 488cpu_side=system.cpu.icache_port 489mem_side=system.toL2Bus.port[1] 490 491[system.cpu.interrupts] 492type=ArmInterrupts 493 494[system.cpu.itb] 495type=ArmTLB 496children=walker 497size=64 498walker=system.cpu.itb.walker 499 500[system.cpu.itb.walker] 501type=ArmTableWalker 502max_backoff=100000 503min_backoff=0 504sys=system 505port=system.toL2Bus.port[3] 506 507[system.cpu.tracer] 508type=ExeTracer 509 510[system.intrctrl] 511type=IntrControl 512sys=system 513 514[system.iobus] 515type=Bus 516block_size=64 517bus_id=0 518clock=1000 519header_cycles=1 520use_default_range=false 521width=64 522port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side 523 524[system.iocache] 525type=BaseCache 526addr_range=0:268435455 527assoc=8 528block_size=64 529forward_snoops=false 530hash_delay=1 531is_top_level=false 532latency=50000 533max_miss_count=0 534mshrs=20 535prefetch_on_access=false 536prefetcher=Null 537prioritizeRequests=false 538repl=Null 539size=1024 540subblock_size=0 541system=system 542tgts_per_mshr=12 543trace_addr=0 544two_queue=false 545write_buffers=8 546cpu_side=system.iobus.port[28] 547mem_side=system.membus.port[8] 548 549[system.l2c] 550type=BaseCache 551addr_range=0:18446744073709551615 552assoc=8 553block_size=64 554forward_snoops=true 555hash_delay=1 556is_top_level=false 557latency=10000 558max_miss_count=0 559mshrs=92 560prefetch_on_access=false 561prefetcher=Null 562prioritizeRequests=false 563repl=Null 564size=4194304 565subblock_size=0 566system=system 567tgts_per_mshr=16 568trace_addr=0 569two_queue=false 570write_buffers=8 571cpu_side=system.toL2Bus.port[0] 572mem_side=system.membus.port[9] 573 574[system.membus] 575type=Bus 576children=badaddr_responder 577block_size=64 578bus_id=1 579clock=1000 580header_cycles=1 581use_default_range=false 582width=64 583default=system.membus.badaddr_responder.pio 584port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side 585 586[system.membus.badaddr_responder] 587type=IsaFake 588fake_mem=false 589pio_addr=0 590pio_latency=1000 591pio_size=8 592ret_bad_addr=true 593ret_data16=65535 594ret_data32=4294967295 595ret_data64=18446744073709551615 596ret_data8=255 597system=system 598update_data=false 599warn_access=warn 600pio=system.membus.default 601 602[system.nvmem] 603type=PhysicalMemory 604file= 605latency=30000 606latency_var=0 607null=false 608range=2147483648:2214592511 609zero=true 610port=system.membus.port[1] 611 612[system.physmem] 613type=PhysicalMemory 614file= 615latency=30000 616latency_var=0 617null=false 618range=0:134217727 619zero=true 620port=system.membus.port[2] 621 622[system.realview] 623type=RealView 624children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 625intrctrl=system.intrctrl 626pci_cfg_base=0 627system=system 628 629[system.realview.a9scu] 630type=A9SCU 631pio_addr=520093696 632pio_latency=1000 633system=system 634pio=system.membus.port[5] 635 636[system.realview.aaci_fake] 637type=AmbaFake 638amba_id=0 639ignore_access=false 640pio_addr=268451840 641pio_latency=1000 642system=system 643pio=system.iobus.port[24] 644 645[system.realview.cf_ctrl] 646type=IdeController 647BAR0=402653184 648BAR0LegacyIO=true 649BAR0Size=16 650BAR1=402653440 651BAR1LegacyIO=true 652BAR1Size=1 653BAR2=1 654BAR2LegacyIO=false 655BAR2Size=8 656BAR3=1 657BAR3LegacyIO=false 658BAR3Size=4 659BAR4=1 660BAR4LegacyIO=false 661BAR4Size=16 662BAR5=1 663BAR5LegacyIO=false 664BAR5Size=0 665BIST=0 666CacheLineSize=0 667CardbusCIS=0 668ClassCode=1 669Command=1 670DeviceID=28945 671ExpansionROM=0 672HeaderType=0 673InterruptLine=31 674InterruptPin=1 675LatencyTimer=0 676MaximumLatency=0 677MinimumGrant=0 678ProgIF=133 679Revision=0 680Status=640 681SubClassCode=1 682SubsystemID=0 683SubsystemVendorID=0 684VendorID=32902 685config_latency=20000 686ctrl_offset=2 687disks=system.cf0 688io_shift=1 689max_backoff_delay=10000000 690min_backoff_delay=4000 691pci_bus=2 692pci_dev=7 693pci_func=0 694pio_latency=1000 695platform=system.realview 696system=system 697config=system.iobus.port[10] 698dma=system.iobus.port[11] 699pio=system.iobus.port[9] 700 701[system.realview.clcd] 702type=Pl111 703amba_id=1315089 704clock=41667 705gic=system.realview.gic 706int_num=55 707max_backoff_delay=10000000 708min_backoff_delay=4000 709pio_addr=268566528 710pio_latency=10000 711system=system 712vnc=system.vncserver 713dma=system.iobus.port[6] 714pio=system.iobus.port[5] 715 716[system.realview.dmac_fake] 717type=AmbaFake 718amba_id=0 719ignore_access=false 720pio_addr=268632064 721pio_latency=1000 722system=system 723pio=system.iobus.port[12] 724 725[system.realview.flash_fake] 726type=IsaFake 727fake_mem=true 728pio_addr=1073741824 729pio_latency=1000 730pio_size=536870912 731ret_bad_addr=false 732ret_data16=65535 733ret_data32=4294967295 734ret_data64=18446744073709551615 735ret_data8=255 736system=system 737update_data=false 738warn_access= 739pio=system.iobus.port[27] 740 741[system.realview.gic] 742type=Gic 743cpu_addr=520093952 744cpu_pio_delay=10000 745dist_addr=520097792 746dist_pio_delay=10000 747int_latency=10000 748it_lines=128 749platform=system.realview 750system=system 751pio=system.membus.port[3] 752 753[system.realview.gpio0_fake] 754type=AmbaFake 755amba_id=0 756ignore_access=false 757pio_addr=268513280 758pio_latency=1000 759system=system 760pio=system.iobus.port[19] 761 762[system.realview.gpio1_fake] 763type=AmbaFake 764amba_id=0 765ignore_access=false 766pio_addr=268517376 767pio_latency=1000 768system=system 769pio=system.iobus.port[20] 770 771[system.realview.gpio2_fake] 772type=AmbaFake 773amba_id=0 774ignore_access=false 775pio_addr=268521472 776pio_latency=1000 777system=system 778pio=system.iobus.port[21] 779 780[system.realview.kmi0] 781type=Pl050 782amba_id=1314896 783gic=system.realview.gic 784int_delay=1000000 785int_num=52 786is_mouse=false 787pio_addr=268460032 788pio_latency=1000 789system=system 790vnc=system.vncserver 791pio=system.iobus.port[7] 792 793[system.realview.kmi1] 794type=Pl050 795amba_id=1314896 796gic=system.realview.gic 797int_delay=1000000 798int_num=53 799is_mouse=true 800pio_addr=268464128 801pio_latency=1000 802system=system 803vnc=system.vncserver 804pio=system.iobus.port[8] 805 806[system.realview.l2x0_fake] 807type=IsaFake 808fake_mem=false 809pio_addr=520101888 810pio_latency=1000 811pio_size=4095 812ret_bad_addr=false 813ret_data16=65535 814ret_data32=4294967295 815ret_data64=18446744073709551615 816ret_data8=255 817system=system 818update_data=false 819warn_access= 820pio=system.membus.port[4] 821 822[system.realview.local_cpu_timer] 823type=CpuLocalTimer 824clock=1000 825gic=system.realview.gic 826int_num_timer=29 827int_num_watchdog=30 828pio_addr=520095232 829pio_latency=1000 830system=system 831pio=system.membus.port[6] 832 833[system.realview.mmc_fake] 834type=AmbaFake 835amba_id=0 836ignore_access=false 837pio_addr=268455936 838pio_latency=1000 839system=system 840pio=system.iobus.port[25] 841 842[system.realview.realview_io] 843type=RealViewCtrl 844idreg=0 845pio_addr=268435456 846pio_latency=1000 847proc_id0=201326592 848proc_id1=201327138 849system=system 850pio=system.iobus.port[2] 851 852[system.realview.rtc_fake] 853type=AmbaFake 854amba_id=266289 855ignore_access=false 856pio_addr=268529664 857pio_latency=1000 858system=system 859pio=system.iobus.port[26] 860 861[system.realview.sci_fake] 862type=AmbaFake 863amba_id=0 864ignore_access=false 865pio_addr=268492800 866pio_latency=1000 867system=system 868pio=system.iobus.port[23] 869 870[system.realview.smc_fake] 871type=AmbaFake 872amba_id=0 873ignore_access=false 874pio_addr=269357056 875pio_latency=1000 876system=system 877pio=system.iobus.port[16] 878 879[system.realview.sp810_fake] 880type=AmbaFake 881amba_id=0 882ignore_access=true 883pio_addr=268439552 884pio_latency=1000 885system=system 886pio=system.iobus.port[17] 887 888[system.realview.ssp_fake] 889type=AmbaFake 890amba_id=0 891ignore_access=false 892pio_addr=268488704 893pio_latency=1000 894system=system 895pio=system.iobus.port[22] 896 897[system.realview.timer0] 898type=Sp804 899amba_id=1316868 900clock0=1000000 901clock1=1000000 902gic=system.realview.gic 903int_num0=36 904int_num1=36 905pio_addr=268505088 906pio_latency=1000 907system=system 908pio=system.iobus.port[3] 909 910[system.realview.timer1] 911type=Sp804 912amba_id=1316868 913clock0=1000000 914clock1=1000000 915gic=system.realview.gic 916int_num0=37 917int_num1=37 918pio_addr=268509184 919pio_latency=1000 920system=system 921pio=system.iobus.port[4] 922 923[system.realview.uart] 924type=Pl011 925end_on_eot=false 926gic=system.realview.gic 927int_delay=100000 928int_num=44 929pio_addr=268472320 930pio_latency=1000 931platform=system.realview 932system=system 933terminal=system.terminal 934pio=system.iobus.port[1] 935 936[system.realview.uart1_fake] 937type=AmbaFake 938amba_id=0 939ignore_access=false 940pio_addr=268476416 941pio_latency=1000 942system=system 943pio=system.iobus.port[13] 944 945[system.realview.uart2_fake] 946type=AmbaFake 947amba_id=0 948ignore_access=false 949pio_addr=268480512 950pio_latency=1000 951system=system 952pio=system.iobus.port[14] 953 954[system.realview.uart3_fake] 955type=AmbaFake 956amba_id=0 957ignore_access=false 958pio_addr=268484608 959pio_latency=1000 960system=system 961pio=system.iobus.port[15] 962 963[system.realview.watchdog_fake] 964type=AmbaFake 965amba_id=0 966ignore_access=false 967pio_addr=268500992 968pio_latency=1000 969system=system 970pio=system.iobus.port[18] 971 972[system.terminal] 973type=Terminal 974intr_control=system.intrctrl 975number=0 976output=true 977port=3456 978 979[system.toL2Bus] 980type=Bus 981block_size=64 982bus_id=0 983clock=1000 984header_cycles=1 985use_default_range=false 986width=64 987port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 988 989[system.vncserver] 990type=VncServer 991frame_capture=false 992number=0 993port=5900 994 995