stats.txt revision 9308:f634a34f2f0b
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.603785 # Number of seconds simulated 4sim_ticks 2603784540500 # Number of ticks simulated 5final_tick 2603784540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 66983 # Simulator instruction rate (inst/s) 8host_op_rate 86203 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2766471262 # Simulator tick rate (ticks/s) 10host_mem_usage 391460 # Number of bytes of host memory used 11host_seconds 941.19 # Real time elapsed on the host 12sim_insts 63043892 # Number of instructions simulated 13sim_ops 81133946 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 398208 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4365108 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 424768 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5242032 # Number of bytes read from this memory 22system.physmem.bytes_read::total 131542884 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 398208 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 424768 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 822976 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4259200 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7288336 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6222 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68277 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6637 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 81933 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 15301920 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66550 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 823834 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 46513268 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 152934 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 1676447 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 516 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 163135 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2013236 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 50519881 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 152934 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 163135 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 316069 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 1635773 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 6529 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 1156830 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2799132 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1635773 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46513268 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 152934 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 1682976 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 516 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 163135 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 3170066 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 53319012 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 72716 # number of replacements 88system.l2c.tagsinuse 53054.127627 # Cycle average of tags in use 89system.l2c.total_refs 1921007 # Total number of references to valid blocks. 90system.l2c.sampled_refs 137887 # Sample count of references to valid blocks. 91system.l2c.avg_refs 13.931748 # Average number of references to valid blocks. 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93system.l2c.occ_blocks::writebacks 37702.750245 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 4.539457 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.000261 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 4229.509835 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 2960.828509 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 15.234392 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 4027.989211 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 4113.275716 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.575298 # Average percentage of cache occupancy 102system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 104system.l2c.occ_percent::cpu0.inst 0.064537 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.045179 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000232 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.061462 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.062764 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.809542 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 35167 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 5217 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 398405 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 165702 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 54913 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 6451 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 614994 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 202172 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1483021 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 584447 # number of Writeback hits 120system.l2c.Writeback_hits::total 584447 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1035 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 765 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1800 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 171 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 381 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 48064 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 58867 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 106931 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 35167 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 5217 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 398405 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 213766 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 54913 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 6451 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 614994 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 261039 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1589952 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 35167 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 5217 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 398405 # number of overall hits 142system.l2c.overall_hits::cpu0.data 213766 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 54913 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 6451 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 614994 # number of overall hits 146system.l2c.overall_hits::cpu1.data 261039 # number of overall hits 147system.l2c.overall_hits::total 1589952 # number of overall hits 148system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 150system.l2c.ReadReq_misses::cpu0.inst 6098 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 6350 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu1.inst 6599 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 6280 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 25362 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 5678 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 4325 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 10003 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 781 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 592 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1373 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 63319 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 76915 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 140234 # number of ReadExReq misses 165system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu0.inst 6098 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 69669 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu1.inst 6599 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 83195 # number of demand (read+write) misses 172system.l2c.demand_misses::total 165596 # number of demand (read+write) misses 173system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 175system.l2c.overall_misses::cpu0.inst 6098 # number of overall misses 176system.l2c.overall_misses::cpu0.data 69669 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 6599 # number of overall misses 179system.l2c.overall_misses::cpu1.data 83195 # number of overall misses 180system.l2c.overall_misses::total 165596 # number of overall misses 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 629000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112000 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 325278000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 333913000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1103000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 350966000 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 330367497 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1342368497 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 20556482 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 27727000 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 48283482 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1413500 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7215998 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 8629498 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3400238492 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 4067056495 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7467294987 # number of ReadExReq miss cycles 198system.l2c.demand_miss_latency::cpu0.dtb.walker 629000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 112000 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu0.inst 325278000 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3734151492 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 1103000 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 350966000 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 4397423992 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8809663484 # number of demand (read+write) miss cycles 206system.l2c.overall_miss_latency::cpu0.dtb.walker 629000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 112000 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu0.inst 325278000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3734151492 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 1103000 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 350966000 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 4397423992 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8809663484 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 35179 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 5219 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 404503 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 172052 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 54934 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 6451 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 621593 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 208452 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1508383 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 584447 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 584447 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 6713 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 5090 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 11803 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 991 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 763 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1754 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 111383 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 135782 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 247165 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 35179 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 5219 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 404503 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 283435 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 54934 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 6451 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 621593 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 344234 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1755548 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 35179 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 5219 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 404503 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 283435 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 54934 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 6451 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 621593 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 344234 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1755548 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000341 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000383 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.015075 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.036907 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.010616 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.030127 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.016814 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.845822 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.849705 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.847496 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.788093 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.775885 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.782782 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.568480 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.566459 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.567370 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000341 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.000383 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.015075 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.245802 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.010616 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.241682 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.094327 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000341 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.000383 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.015075 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.245802 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.010616 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.241682 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.094327 # miss rate for overall accesses 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52416.666667 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56000 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53341.751394 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52584.724409 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52523.809524 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53184.724958 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52606.289331 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52928.337552 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3620.373723 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6410.867052 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 4826.900130 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1809.859155 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12189.185811 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 6285.140568 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53700.129377 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52877.286550 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 53248.819737 # average ReadExReq miss latency 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52416.666667 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56000 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 53341.751394 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 53598.465487 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52523.809524 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 53184.724958 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52856.830242 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 53199.736008 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52416.666667 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56000 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 53341.751394 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 53598.465487 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52523.809524 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 53184.724958 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52856.830242 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 53199.736008 # average overall miss latency 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # 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number of overall MSHR hits 339system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits 340system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 341system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits 342system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits 343system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses 344system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 345system.l2c.ReadReq_mshr_misses::cpu0.inst 6091 # number of ReadReq MSHR misses 346system.l2c.ReadReq_mshr_misses::cpu0.data 6312 # number of ReadReq MSHR misses 347system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses 348system.l2c.ReadReq_mshr_misses::cpu1.inst 6592 # number of ReadReq MSHR misses 349system.l2c.ReadReq_mshr_misses::cpu1.data 6255 # number of ReadReq MSHR misses 350system.l2c.ReadReq_mshr_misses::total 25285 # number of ReadReq MSHR misses 351system.l2c.UpgradeReq_mshr_misses::cpu0.data 5678 # number of UpgradeReq MSHR misses 352system.l2c.UpgradeReq_mshr_misses::cpu1.data 4325 # number of UpgradeReq MSHR misses 353system.l2c.UpgradeReq_mshr_misses::total 10003 # number of UpgradeReq MSHR misses 354system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 781 # number of SCUpgradeReq MSHR misses 355system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 592 # number of SCUpgradeReq MSHR misses 356system.l2c.SCUpgradeReq_mshr_misses::total 1373 # number of SCUpgradeReq MSHR misses 357system.l2c.ReadExReq_mshr_misses::cpu0.data 63319 # number of ReadExReq MSHR misses 358system.l2c.ReadExReq_mshr_misses::cpu1.data 76915 # number of ReadExReq MSHR misses 359system.l2c.ReadExReq_mshr_misses::total 140234 # number of ReadExReq MSHR misses 360system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses 361system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 362system.l2c.demand_mshr_misses::cpu0.inst 6091 # number of demand (read+write) MSHR misses 363system.l2c.demand_mshr_misses::cpu0.data 69631 # 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number of UpgradeReq MSHR miss cycles 387system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31270497 # number of SCUpgradeReq MSHR miss cycles 388system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23695494 # number of SCUpgradeReq MSHR miss cycles 389system.l2c.SCUpgradeReq_mshr_miss_latency::total 54965991 # number of SCUpgradeReq MSHR miss cycles 390system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2625078492 # number of ReadExReq MSHR miss cycles 391system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3115392495 # number of ReadExReq MSHR miss cycles 392system.l2c.ReadExReq_mshr_miss_latency::total 5740470987 # number of ReadExReq MSHR miss cycles 393system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 481500 # number of demand (read+write) MSHR miss cycles 394system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles 395system.l2c.demand_mshr_miss_latency::cpu0.inst 250628000 # number of demand (read+write) MSHR miss cycles 396system.l2c.demand_mshr_miss_latency::cpu0.data 2880180492 # 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number of overall MSHR miss cycles 407system.l2c.overall_mshr_miss_latency::cpu1.data 3368133992 # number of overall MSHR miss cycles 408system.l2c.overall_mshr_miss_latency::total 6770551984 # number of overall MSHR miss cycles 409system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5539000 # number of ReadReq MSHR uncacheable cycles 410system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12313115973 # number of ReadReq MSHR uncacheable cycles 411system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2149000 # number of ReadReq MSHR uncacheable cycles 412system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154642396483 # number of ReadReq MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_uncacheable_latency::total 166963200456 # number of ReadReq MSHR uncacheable cycles 414system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1155932498 # number of WriteReq MSHR uncacheable cycles 415system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31335895497 # number of WriteReq MSHR uncacheable cycles 416system.l2c.WriteReq_mshr_uncacheable_latency::total 32491827995 # number of WriteReq MSHR uncacheable cycles 417system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5539000 # number of overall MSHR uncacheable cycles 418system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13469048471 # number of overall MSHR uncacheable cycles 419system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2149000 # number of overall MSHR uncacheable cycles 420system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185978291980 # number of overall MSHR uncacheable cycles 421system.l2c.overall_mshr_uncacheable_latency::total 199455028451 # number of overall MSHR uncacheable cycles 422system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000341 # mshr miss rate for ReadReq accesses 423system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000383 # mshr miss rate for ReadReq accesses 424system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015058 # mshr miss rate for ReadReq accesses 425system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036687 # mshr miss rate for ReadReq accesses 426system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for ReadReq accesses 427system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010605 # mshr miss rate for ReadReq accesses 428system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030007 # mshr miss rate for ReadReq accesses 429system.l2c.ReadReq_mshr_miss_rate::total 0.016763 # mshr miss rate for ReadReq accesses 430system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.845822 # mshr miss rate for UpgradeReq accesses 431system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849705 # mshr miss rate for UpgradeReq accesses 432system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses 433system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.788093 # mshr miss rate for SCUpgradeReq accesses 434system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.775885 # mshr miss rate for SCUpgradeReq accesses 435system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.782782 # mshr miss rate for SCUpgradeReq accesses 436system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.568480 # mshr miss rate for ReadExReq accesses 437system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566459 # mshr miss rate for ReadExReq accesses 438system.l2c.ReadExReq_mshr_miss_rate::total 0.567370 # mshr miss rate for ReadExReq accesses 439system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000341 # mshr miss rate for demand accesses 440system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000383 # mshr miss rate for demand accesses 441system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015058 # mshr miss rate for demand accesses 442system.l2c.demand_mshr_miss_rate::cpu0.data 0.245668 # mshr miss rate for demand accesses 443system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for demand accesses 444system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010605 # mshr miss rate for demand accesses 445system.l2c.demand_mshr_miss_rate::cpu1.data 0.241609 # mshr miss rate for demand accesses 446system.l2c.demand_mshr_miss_rate::total 0.094283 # mshr miss rate for demand accesses 447system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000341 # mshr miss rate for overall accesses 448system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000383 # mshr miss rate for overall accesses 449system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015058 # mshr miss rate for overall accesses 450system.l2c.overall_mshr_miss_rate::cpu0.data 0.245668 # mshr miss rate for overall accesses 451system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for overall accesses 452system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010605 # mshr miss rate for overall accesses 453system.l2c.overall_mshr_miss_rate::cpu1.data 0.241609 # mshr miss rate for overall accesses 454system.l2c.overall_mshr_miss_rate::total 0.094283 # mshr miss rate for overall accesses 455system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average ReadReq mshr miss latency 456system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency 457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average ReadReq mshr miss latency 458system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40415.399240 # average ReadReq mshr miss latency 459system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average ReadReq mshr miss latency 460system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average ReadReq mshr miss latency 461system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40406.314468 # average ReadReq mshr miss latency 462system.l2c.ReadReq_avg_mshr_miss_latency::total 40738.817362 # average ReadReq mshr miss latency 463system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40030.815252 # average UpgradeReq mshr miss latency 464system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.056416 # average UpgradeReq mshr miss latency 465system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40039.134560 # average UpgradeReq mshr miss latency 466system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40039.048656 # average SCUpgradeReq mshr miss latency 467system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.172297 # average SCUpgradeReq mshr miss latency 468system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40033.496723 # average SCUpgradeReq mshr miss latency 469system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41457.990366 # average ReadExReq mshr miss latency 470system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40504.355392 # average ReadExReq mshr miss latency 471system.l2c.ReadExReq_avg_mshr_miss_latency::total 40934.944357 # average ReadExReq mshr miss latency 472system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average overall mshr miss latency 473system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency 474system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average overall mshr miss latency 475system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41363.480232 # average overall mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40496.981989 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::total 40904.983621 # average overall mshr miss latency 480system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40125 # average overall mshr miss latency 481system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41147.266459 # average overall mshr miss latency 483system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41363.480232 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40309.523810 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.091626 # average overall mshr miss latency 486system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40496.981989 # average overall mshr miss latency 487system.l2c.overall_avg_mshr_miss_latency::total 40904.983621 # average overall mshr miss latency 488system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 489system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 490system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 491system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 492system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 493system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 494system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 495system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 496system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 497system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 498system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 499system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 500system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 501system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 502system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 503system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 504system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 505system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 506system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 507system.cf0.dma_write_txs 0 # Number of DMA write transactions. 508system.cpu0.dtb.inst_hits 0 # ITB inst hits 509system.cpu0.dtb.inst_misses 0 # ITB inst misses 510system.cpu0.dtb.read_hits 9065848 # DTB read hits 511system.cpu0.dtb.read_misses 36360 # DTB read misses 512system.cpu0.dtb.write_hits 5285915 # DTB write hits 513system.cpu0.dtb.write_misses 6625 # DTB write misses 514system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 515system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 517system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 518system.cpu0.dtb.flush_entries 2165 # Number of entries that have been flushed from TLB 519system.cpu0.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions 520system.cpu0.dtb.prefetch_faults 342 # Number of TLB faults due to prefetch 521system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions 523system.cpu0.dtb.read_accesses 9102208 # DTB read accesses 524system.cpu0.dtb.write_accesses 5292540 # DTB write accesses 525system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 526system.cpu0.dtb.hits 14351763 # DTB hits 527system.cpu0.dtb.misses 42985 # DTB misses 528system.cpu0.dtb.accesses 14394748 # DTB accesses 529system.cpu0.itb.inst_hits 4413372 # ITB inst hits 530system.cpu0.itb.inst_misses 5476 # ITB inst misses 531system.cpu0.itb.read_hits 0 # DTB read hits 532system.cpu0.itb.read_misses 0 # DTB read misses 533system.cpu0.itb.write_hits 0 # DTB write hits 534system.cpu0.itb.write_misses 0 # DTB write misses 535system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 536system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 537system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 538system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 539system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB 540system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 541system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 542system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 543system.cpu0.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions 544system.cpu0.itb.read_accesses 0 # DTB read accesses 545system.cpu0.itb.write_accesses 0 # DTB write accesses 546system.cpu0.itb.inst_accesses 4418848 # ITB inst accesses 547system.cpu0.itb.hits 4413372 # DTB hits 548system.cpu0.itb.misses 5476 # DTB misses 549system.cpu0.itb.accesses 4418848 # DTB accesses 550system.cpu0.numCycles 70012496 # number of cpu cycles simulated 551system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 552system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 553system.cpu0.BPredUnit.lookups 6217398 # Number of BP lookups 554system.cpu0.BPredUnit.condPredicted 4733750 # Number of conditional branches predicted 555system.cpu0.BPredUnit.condIncorrect 327130 # Number of conditional branches incorrect 556system.cpu0.BPredUnit.BTBLookups 4014715 # Number of BTB lookups 557system.cpu0.BPredUnit.BTBHits 3051469 # Number of BTB hits 558system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 559system.cpu0.BPredUnit.usedRAS 700588 # Number of times the RAS was used to get a target. 560system.cpu0.BPredUnit.RASInCorrect 31775 # Number of incorrect RAS predictions. 561system.cpu0.fetch.icacheStallCycles 12151517 # Number of cycles fetch is stalled on an Icache miss 562system.cpu0.fetch.Insts 33217564 # Number of instructions fetch has processed 563system.cpu0.fetch.Branches 6217398 # Number of branches that fetch encountered 564system.cpu0.fetch.predictedBranches 3752057 # Number of branches that fetch has predicted taken 565system.cpu0.fetch.Cycles 7806548 # Number of cycles fetch has run and was not squashing or blocked 566system.cpu0.fetch.SquashCycles 1581421 # Number of cycles fetch has spent squashing 567system.cpu0.fetch.TlbCycles 67728 # Number of cycles fetch has spent waiting for tlb 568system.cpu0.fetch.BlockedCycles 22157211 # Number of cycles fetch has spent blocked 569system.cpu0.fetch.MiscStallCycles 5913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 570system.cpu0.fetch.PendingTrapStallCycles 54633 # Number of stall cycles due to pending traps 571system.cpu0.fetch.PendingQuiesceStallCycles 92488 # Number of stall cycles due to pending quiesce instructions 572system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR 573system.cpu0.fetch.CacheLines 4411708 # Number of cache lines fetched 574system.cpu0.fetch.IcacheSquashes 171100 # Number of outstanding Icache misses that were squashed 575system.cpu0.fetch.ItlbSquashes 2593 # Number of outstanding ITLB misses that were squashed 576system.cpu0.fetch.rateDist::samples 43471985 # Number of instructions fetched each cycle (Total) 577system.cpu0.fetch.rateDist::mean 0.986228 # Number of instructions fetched each cycle (Total) 578system.cpu0.fetch.rateDist::stdev 2.366083 # Number of instructions fetched each cycle (Total) 579system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 580system.cpu0.fetch.rateDist::0 35673429 82.06% 82.06% # Number of instructions fetched each cycle (Total) 581system.cpu0.fetch.rateDist::1 623255 1.43% 83.49% # Number of instructions fetched each cycle (Total) 582system.cpu0.fetch.rateDist::2 822107 1.89% 85.39% # Number of instructions fetched each cycle (Total) 583system.cpu0.fetch.rateDist::3 699884 1.61% 87.00% # Number of instructions fetched each cycle (Total) 584system.cpu0.fetch.rateDist::4 794381 1.83% 88.82% # Number of instructions fetched each cycle (Total) 585system.cpu0.fetch.rateDist::5 577438 1.33% 90.15% # Number of instructions fetched each cycle (Total) 586system.cpu0.fetch.rateDist::6 719535 1.66% 91.81% # Number of instructions fetched each cycle (Total) 587system.cpu0.fetch.rateDist::7 371399 0.85% 92.66% # Number of instructions fetched each cycle (Total) 588system.cpu0.fetch.rateDist::8 3190557 7.34% 100.00% # Number of instructions fetched each cycle (Total) 589system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 590system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 591system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 592system.cpu0.fetch.rateDist::total 43471985 # Number of instructions fetched each cycle (Total) 593system.cpu0.fetch.branchRate 0.088804 # Number of branch fetches per cycle 594system.cpu0.fetch.rate 0.474452 # Number of inst fetches per cycle 595system.cpu0.decode.IdleCycles 12679354 # Number of cycles decode is idle 596system.cpu0.decode.BlockedCycles 22114744 # Number of cycles decode is blocked 597system.cpu0.decode.RunCycles 7023055 # Number of cycles decode is running 598system.cpu0.decode.UnblockCycles 583785 # Number of cycles decode is unblocking 599system.cpu0.decode.SquashCycles 1071047 # Number of cycles decode is squashing 600system.cpu0.decode.BranchResolved 976895 # Number of times decode resolved a branch 601system.cpu0.decode.BranchMispred 65884 # Number of times decode detected a branch misprediction 602system.cpu0.decode.DecodedInsts 41430285 # Number of instructions handled by decode 603system.cpu0.decode.SquashedInsts 215511 # Number of squashed instructions handled by decode 604system.cpu0.rename.SquashCycles 1071047 # Number of cycles rename is squashing 605system.cpu0.rename.IdleCycles 13270486 # Number of cycles rename is idle 606system.cpu0.rename.BlockCycles 5876098 # Number of cycles rename is blocking 607system.cpu0.rename.serializeStallCycles 14061413 # count of cycles rename stalled for serializing inst 608system.cpu0.rename.RunCycles 6963478 # Number of cycles rename is running 609system.cpu0.rename.UnblockCycles 2229463 # Number of cycles rename is unblocking 610system.cpu0.rename.RenamedInsts 40231881 # Number of instructions processed by rename 611system.cpu0.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full 612system.cpu0.rename.IQFullEvents 440788 # Number of times rename has blocked due to IQ full 613system.cpu0.rename.LSQFullEvents 1249784 # Number of times rename has blocked due to LSQ full 614system.cpu0.rename.FullRegisterEvents 63 # Number of times there has been no free registers 615system.cpu0.rename.RenamedOperands 40621534 # Number of destination operands rename has renamed 616system.cpu0.rename.RenameLookups 181781749 # Number of register rename lookups that rename has made 617system.cpu0.rename.int_rename_lookups 181747462 # Number of integer rename lookups 618system.cpu0.rename.fp_rename_lookups 34287 # Number of floating rename lookups 619system.cpu0.rename.CommittedMaps 31667723 # Number of HB maps that are committed 620system.cpu0.rename.UndoneMaps 8953810 # Number of HB maps that are undone due to squashing 621system.cpu0.rename.serializingInsts 461246 # count of serializing insts renamed 622system.cpu0.rename.tempSerializingInsts 417498 # count of temporary serializing insts renamed 623system.cpu0.rename.skidInsts 5499956 # count of insts added to the skid buffer 624system.cpu0.memDep0.insertedLoads 7912486 # Number of loads inserted to the mem dependence unit. 625system.cpu0.memDep0.insertedStores 5888217 # Number of stores inserted to the mem dependence unit. 626system.cpu0.memDep0.conflictingLoads 1140849 # Number of conflicting loads. 627system.cpu0.memDep0.conflictingStores 1237786 # Number of conflicting stores. 628system.cpu0.iq.iqInstsAdded 37992607 # Number of instructions added to the IQ (excludes non-spec) 629system.cpu0.iq.iqNonSpecInstsAdded 949484 # Number of non-speculative instructions added to the IQ 630system.cpu0.iq.iqInstsIssued 38225982 # Number of instructions issued 631system.cpu0.iq.iqSquashedInstsIssued 89034 # Number of squashed instructions issued 632system.cpu0.iq.iqSquashedInstsExamined 6781394 # Number of squashed instructions iterated over during squash; mainly for profiling 633system.cpu0.iq.iqSquashedOperandsExamined 14357702 # Number of squashed operands that are examined and possibly removed from graph 634system.cpu0.iq.iqSquashedNonSpecRemoved 260797 # Number of squashed non-spec instructions that were removed 635system.cpu0.iq.issued_per_cycle::samples 43471985 # Number of insts issued each cycle 636system.cpu0.iq.issued_per_cycle::mean 0.879325 # Number of insts issued each cycle 637system.cpu0.iq.issued_per_cycle::stdev 1.495049 # Number of insts issued each cycle 638system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 639system.cpu0.iq.issued_per_cycle::0 27798434 63.95% 63.95% # Number of insts issued each cycle 640system.cpu0.iq.issued_per_cycle::1 6055917 13.93% 77.88% # Number of insts issued each cycle 641system.cpu0.iq.issued_per_cycle::2 3289826 7.57% 85.44% # Number of insts issued each cycle 642system.cpu0.iq.issued_per_cycle::3 2491193 5.73% 91.17% # Number of insts issued each cycle 643system.cpu0.iq.issued_per_cycle::4 2118698 4.87% 96.05% # Number of insts issued each cycle 644system.cpu0.iq.issued_per_cycle::5 969648 2.23% 98.28% # Number of insts issued each cycle 645system.cpu0.iq.issued_per_cycle::6 500024 1.15% 99.43% # Number of insts issued each cycle 646system.cpu0.iq.issued_per_cycle::7 192302 0.44% 99.87% # Number of insts issued each cycle 647system.cpu0.iq.issued_per_cycle::8 55943 0.13% 100.00% # Number of insts issued each cycle 648system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 649system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 650system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 651system.cpu0.iq.issued_per_cycle::total 43471985 # Number of insts issued each cycle 652system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 653system.cpu0.iq.fu_full::IntAlu 25214 2.35% 2.35% # attempts to use FU when none available 654system.cpu0.iq.fu_full::IntMult 458 0.04% 2.39% # attempts to use FU when none available 655system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.39% # attempts to use FU when none available 656system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.39% # attempts to use FU when none available 657system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.39% # attempts to use FU when none available 658system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.39% # attempts to use FU when none available 659system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.39% # attempts to use FU when none available 660system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.39% # attempts to use FU when none available 661system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.39% # attempts to use FU when none available 662system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.39% # attempts to use FU when none available 663system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.39% # attempts to use FU when none available 664system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.39% # attempts to use FU when none available 665system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.39% # attempts to use FU when none available 666system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.39% # attempts to use FU when none available 667system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.39% # attempts to use FU when none available 668system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.39% # attempts to use FU when none available 669system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.39% # attempts to use FU when none available 670system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.39% # attempts to use FU when none available 671system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.39% # attempts to use FU when none available 672system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.39% # attempts to use FU when none available 673system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.39% # attempts to use FU when none available 674system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.39% # attempts to use FU when none available 675system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.39% # attempts to use FU when none available 676system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.39% # attempts to use FU when none available 677system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.39% # attempts to use FU when none available 678system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.39% # attempts to use FU when none available 679system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.39% # attempts to use FU when none available 680system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.39% # attempts to use FU when none available 681system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.39% # attempts to use FU when none available 682system.cpu0.iq.fu_full::MemRead 837969 78.03% 80.42% # attempts to use FU when none available 683system.cpu0.iq.fu_full::MemWrite 210208 19.58% 100.00% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 685system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 686system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued 687system.cpu0.iq.FU_type_0::IntAlu 22961950 60.07% 60.21% # Type of FU issued 688system.cpu0.iq.FU_type_0::IntMult 49879 0.13% 60.34% # Type of FU issued 689system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued 690system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued 691system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued 692system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued 693system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued 694system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued 695system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued 696system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued 697system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued 698system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued 699system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued 700system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued 701system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 60.34% # Type of FU issued 702system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued 703system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued 704system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued 705system.cpu0.iq.FU_type_0::SimdShiftAcc 12 0.00% 60.34% # Type of FU issued 706system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued 707system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued 708system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued 709system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued 710system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued 711system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued 712system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued 713system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued 714system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued 715system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued 716system.cpu0.iq.FU_type_0::MemRead 9545903 24.97% 85.31% # Type of FU issued 717system.cpu0.iq.FU_type_0::MemWrite 5615312 14.69% 100.00% # Type of FU issued 718system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 719system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 720system.cpu0.iq.FU_type_0::total 38225982 # Type of FU issued 721system.cpu0.iq.rate 0.545988 # Inst issue rate 722system.cpu0.iq.fu_busy_cnt 1073849 # FU busy when requested 723system.cpu0.iq.fu_busy_rate 0.028092 # FU busy rate (busy events/executed inst) 724system.cpu0.iq.int_inst_queue_reads 121121114 # Number of integer instruction queue reads 725system.cpu0.iq.int_inst_queue_writes 45731569 # Number of integer instruction queue writes 726system.cpu0.iq.int_inst_queue_wakeup_accesses 35283041 # Number of integer instruction queue wakeup accesses 727system.cpu0.iq.fp_inst_queue_reads 8365 # Number of floating instruction queue reads 728system.cpu0.iq.fp_inst_queue_writes 4658 # Number of floating instruction queue writes 729system.cpu0.iq.fp_inst_queue_wakeup_accesses 3880 # Number of floating instruction queue wakeup accesses 730system.cpu0.iq.int_alu_accesses 39243245 # Number of integer alu accesses 731system.cpu0.iq.fp_alu_accesses 4372 # Number of floating point alu accesses 732system.cpu0.iew.lsq.thread0.forwLoads 321528 # Number of loads that had data forwarded from stores 733system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 734system.cpu0.iew.lsq.thread0.squashedLoads 1492825 # Number of loads squashed 735system.cpu0.iew.lsq.thread0.ignoredResponses 3508 # Number of memory responses ignored because the instruction is squashed 736system.cpu0.iew.lsq.thread0.memOrderViolation 13401 # Number of memory ordering violations 737system.cpu0.iew.lsq.thread0.squashedStores 615446 # Number of stores squashed 738system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 739system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 740system.cpu0.iew.lsq.thread0.rescheduledLoads 2149535 # Number of loads that were rescheduled 741system.cpu0.iew.lsq.thread0.cacheBlocked 5390 # Number of times an access to memory failed due to the cache being blocked 742system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 743system.cpu0.iew.iewSquashCycles 1071047 # Number of cycles IEW is squashing 744system.cpu0.iew.iewBlockCycles 4218607 # Number of cycles IEW is blocking 745system.cpu0.iew.iewUnblockCycles 98464 # Number of cycles IEW is unblocking 746system.cpu0.iew.iewDispatchedInsts 39061403 # Number of instructions dispatched to IQ 747system.cpu0.iew.iewDispSquashedInsts 95550 # Number of squashed instructions skipped by dispatch 748system.cpu0.iew.iewDispLoadInsts 7912486 # Number of dispatched load instructions 749system.cpu0.iew.iewDispStoreInsts 5888217 # Number of dispatched store instructions 750system.cpu0.iew.iewDispNonSpecInsts 616723 # Number of dispatched non-speculative instructions 751system.cpu0.iew.iewIQFullEvents 40108 # Number of times the IQ has become full, causing a stall 752system.cpu0.iew.iewLSQFullEvents 2851 # Number of times the LSQ has become full, causing a stall 753system.cpu0.iew.memOrderViolationEvents 13401 # Number of memory order violations 754system.cpu0.iew.predictedTakenIncorrect 172679 # Number of branches that were predicted taken incorrectly 755system.cpu0.iew.predictedNotTakenIncorrect 129654 # Number of branches that were predicted not taken incorrectly 756system.cpu0.iew.branchMispredicts 302333 # Number of branch mispredicts detected at execute 757system.cpu0.iew.iewExecutedInsts 37800204 # Number of executed instructions 758system.cpu0.iew.iewExecLoadInsts 9383648 # Number of load instructions executed 759system.cpu0.iew.iewExecSquashedInsts 425778 # Number of squashed instructions skipped in execute 760system.cpu0.iew.exec_swp 0 # number of swp insts executed 761system.cpu0.iew.exec_nop 119312 # number of nop insts executed 762system.cpu0.iew.exec_refs 14941647 # number of memory reference insts executed 763system.cpu0.iew.exec_branches 4991029 # Number of branches executed 764system.cpu0.iew.exec_stores 5557999 # Number of stores executed 765system.cpu0.iew.exec_rate 0.539907 # Inst execution rate 766system.cpu0.iew.wb_sent 37583639 # cumulative count of insts sent to commit 767system.cpu0.iew.wb_count 35286921 # cumulative count of insts written-back 768system.cpu0.iew.wb_producers 18740450 # num instructions producing a value 769system.cpu0.iew.wb_consumers 35992151 # num instructions consuming a value 770system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 771system.cpu0.iew.wb_rate 0.504009 # insts written-back per cycle 772system.cpu0.iew.wb_fanout 0.520682 # average fanout of values written-back 773system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 774system.cpu0.commit.commitSquashedInsts 6642216 # The number of squashed insts skipped by commit 775system.cpu0.commit.commitNonSpecStalls 688687 # The number of times commit has been forced to stall to communicate backwards 776system.cpu0.commit.branchMispredicts 262418 # The number of times a branch was mispredicted 777system.cpu0.commit.committed_per_cycle::samples 42437322 # Number of insts commited each cycle 778system.cpu0.commit.committed_per_cycle::mean 0.753690 # Number of insts commited each cycle 779system.cpu0.commit.committed_per_cycle::stdev 1.709171 # Number of insts commited each cycle 780system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 781system.cpu0.commit.committed_per_cycle::0 30360862 71.54% 71.54% # Number of insts commited each cycle 782system.cpu0.commit.committed_per_cycle::1 5984991 14.10% 85.65% # Number of insts commited each cycle 783system.cpu0.commit.committed_per_cycle::2 1981270 4.67% 90.31% # Number of insts commited each cycle 784system.cpu0.commit.committed_per_cycle::3 1011467 2.38% 92.70% # Number of insts commited each cycle 785system.cpu0.commit.committed_per_cycle::4 801137 1.89% 94.59% # Number of insts commited each cycle 786system.cpu0.commit.committed_per_cycle::5 524678 1.24% 95.82% # Number of insts commited each cycle 787system.cpu0.commit.committed_per_cycle::6 395620 0.93% 96.75% # Number of insts commited each cycle 788system.cpu0.commit.committed_per_cycle::7 217374 0.51% 97.27% # Number of insts commited each cycle 789system.cpu0.commit.committed_per_cycle::8 1159923 2.73% 100.00% # Number of insts commited each cycle 790system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 791system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 792system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 793system.cpu0.commit.committed_per_cycle::total 42437322 # Number of insts commited each cycle 794system.cpu0.commit.committedInsts 24255943 # Number of instructions committed 795system.cpu0.commit.committedOps 31984592 # Number of ops (including micro ops) committed 796system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 797system.cpu0.commit.refs 11692432 # Number of memory references committed 798system.cpu0.commit.loads 6419661 # Number of loads committed 799system.cpu0.commit.membars 234476 # Number of memory barriers committed 800system.cpu0.commit.branches 4345348 # Number of branches committed 801system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 802system.cpu0.commit.int_insts 28253924 # Number of committed integer instructions. 803system.cpu0.commit.function_calls 499843 # Number of function calls committed. 804system.cpu0.commit.bw_lim_events 1159923 # number cycles where commit BW limit reached 805system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 806system.cpu0.rob.rob_reads 79019948 # The number of ROB reads 807system.cpu0.rob.rob_writes 78326882 # The number of ROB writes 808system.cpu0.timesIdled 363516 # Number of times that the entire CPU went into an idle state and unscheduled itself 809system.cpu0.idleCycles 26540511 # Total number of cycles that the CPU has spent unscheduled due to idling 810system.cpu0.quiesceCycles 5137512787 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 811system.cpu0.committedInsts 24175201 # Number of Instructions Simulated 812system.cpu0.committedOps 31903850 # Number of Ops (including micro ops) Simulated 813system.cpu0.committedInsts_total 24175201 # Number of Instructions Simulated 814system.cpu0.cpi 2.896046 # CPI: Cycles Per Instruction 815system.cpu0.cpi_total 2.896046 # CPI: Total CPI of All Threads 816system.cpu0.ipc 0.345298 # IPC: Instructions Per Cycle 817system.cpu0.ipc_total 0.345298 # IPC: Total IPC of All Threads 818system.cpu0.int_regfile_reads 176381452 # number of integer regfile reads 819system.cpu0.int_regfile_writes 35063385 # number of integer regfile writes 820system.cpu0.fp_regfile_reads 3376 # number of floating regfile reads 821system.cpu0.fp_regfile_writes 954 # number of floating regfile writes 822system.cpu0.misc_regfile_reads 47472836 # number of misc regfile reads 823system.cpu0.misc_regfile_writes 527620 # number of misc regfile writes 824system.cpu0.icache.replacements 404634 # number of replacements 825system.cpu0.icache.tagsinuse 511.577738 # Cycle average of tags in use 826system.cpu0.icache.total_refs 3973841 # Total number of references to valid blocks. 827system.cpu0.icache.sampled_refs 405146 # Sample count of references to valid blocks. 828system.cpu0.icache.avg_refs 9.808417 # Average number of references to valid blocks. 829system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit. 830system.cpu0.icache.occ_blocks::cpu0.inst 511.577738 # Average occupied blocks per requestor 831system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy 832system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy 833system.cpu0.icache.ReadReq_hits::cpu0.inst 3973841 # number of ReadReq hits 834system.cpu0.icache.ReadReq_hits::total 3973841 # number of ReadReq hits 835system.cpu0.icache.demand_hits::cpu0.inst 3973841 # number of demand (read+write) hits 836system.cpu0.icache.demand_hits::total 3973841 # number of demand (read+write) hits 837system.cpu0.icache.overall_hits::cpu0.inst 3973841 # number of overall hits 838system.cpu0.icache.overall_hits::total 3973841 # number of overall hits 839system.cpu0.icache.ReadReq_misses::cpu0.inst 437728 # number of ReadReq misses 840system.cpu0.icache.ReadReq_misses::total 437728 # number of ReadReq misses 841system.cpu0.icache.demand_misses::cpu0.inst 437728 # number of demand (read+write) misses 842system.cpu0.icache.demand_misses::total 437728 # number of demand (read+write) misses 843system.cpu0.icache.overall_misses::cpu0.inst 437728 # number of overall misses 844system.cpu0.icache.overall_misses::total 437728 # number of overall misses 845system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5954762997 # number of ReadReq miss cycles 846system.cpu0.icache.ReadReq_miss_latency::total 5954762997 # number of ReadReq miss cycles 847system.cpu0.icache.demand_miss_latency::cpu0.inst 5954762997 # number of demand (read+write) miss cycles 848system.cpu0.icache.demand_miss_latency::total 5954762997 # number of demand (read+write) miss cycles 849system.cpu0.icache.overall_miss_latency::cpu0.inst 5954762997 # number of overall miss cycles 850system.cpu0.icache.overall_miss_latency::total 5954762997 # number of overall miss cycles 851system.cpu0.icache.ReadReq_accesses::cpu0.inst 4411569 # number of ReadReq accesses(hits+misses) 852system.cpu0.icache.ReadReq_accesses::total 4411569 # number of ReadReq accesses(hits+misses) 853system.cpu0.icache.demand_accesses::cpu0.inst 4411569 # number of demand (read+write) accesses 854system.cpu0.icache.demand_accesses::total 4411569 # number of demand (read+write) accesses 855system.cpu0.icache.overall_accesses::cpu0.inst 4411569 # number of overall (read+write) accesses 856system.cpu0.icache.overall_accesses::total 4411569 # number of overall (read+write) accesses 857system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099223 # miss rate for ReadReq accesses 858system.cpu0.icache.ReadReq_miss_rate::total 0.099223 # miss rate for ReadReq accesses 859system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099223 # miss rate for demand accesses 860system.cpu0.icache.demand_miss_rate::total 0.099223 # miss rate for demand accesses 861system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099223 # miss rate for overall accesses 862system.cpu0.icache.overall_miss_rate::total 0.099223 # miss rate for overall accesses 863system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13603.797328 # average ReadReq miss latency 864system.cpu0.icache.ReadReq_avg_miss_latency::total 13603.797328 # average ReadReq miss latency 865system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency 866system.cpu0.icache.demand_avg_miss_latency::total 13603.797328 # average overall miss latency 867system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency 868system.cpu0.icache.overall_avg_miss_latency::total 13603.797328 # average overall miss latency 869system.cpu0.icache.blocked_cycles::no_mshrs 2654 # number of cycles access was blocked 870system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 871system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked 872system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 873system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.430556 # average number of cycles each access was blocked 874system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 875system.cpu0.icache.fast_writes 0 # number of fast writes performed 876system.cpu0.icache.cache_copies 0 # number of cache copies performed 877system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32567 # number of ReadReq MSHR hits 878system.cpu0.icache.ReadReq_mshr_hits::total 32567 # number of ReadReq MSHR hits 879system.cpu0.icache.demand_mshr_hits::cpu0.inst 32567 # number of demand (read+write) MSHR hits 880system.cpu0.icache.demand_mshr_hits::total 32567 # number of demand (read+write) MSHR hits 881system.cpu0.icache.overall_mshr_hits::cpu0.inst 32567 # number of overall MSHR hits 882system.cpu0.icache.overall_mshr_hits::total 32567 # number of overall MSHR hits 883system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405161 # number of ReadReq MSHR misses 884system.cpu0.icache.ReadReq_mshr_misses::total 405161 # number of ReadReq MSHR misses 885system.cpu0.icache.demand_mshr_misses::cpu0.inst 405161 # number of demand (read+write) MSHR misses 886system.cpu0.icache.demand_mshr_misses::total 405161 # number of demand (read+write) MSHR misses 887system.cpu0.icache.overall_mshr_misses::cpu0.inst 405161 # number of overall MSHR misses 888system.cpu0.icache.overall_mshr_misses::total 405161 # number of overall MSHR misses 889system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4858454497 # number of ReadReq MSHR miss cycles 890system.cpu0.icache.ReadReq_mshr_miss_latency::total 4858454497 # number of ReadReq MSHR miss cycles 891system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4858454497 # number of demand (read+write) MSHR miss cycles 892system.cpu0.icache.demand_mshr_miss_latency::total 4858454497 # number of demand (read+write) MSHR miss cycles 893system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4858454497 # number of overall MSHR miss cycles 894system.cpu0.icache.overall_mshr_miss_latency::total 4858454497 # number of overall MSHR miss cycles 895system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8271000 # number of ReadReq MSHR uncacheable cycles 896system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8271000 # number of ReadReq MSHR uncacheable cycles 897system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8271000 # number of overall MSHR uncacheable cycles 898system.cpu0.icache.overall_mshr_uncacheable_latency::total 8271000 # number of overall MSHR uncacheable cycles 899system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for ReadReq accesses 900system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091841 # mshr miss rate for ReadReq accesses 901system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for demand accesses 902system.cpu0.icache.demand_mshr_miss_rate::total 0.091841 # mshr miss rate for demand accesses 903system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091841 # mshr miss rate for overall accesses 904system.cpu0.icache.overall_mshr_miss_rate::total 0.091841 # mshr miss rate for overall accesses 905system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average ReadReq mshr miss latency 906system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11991.416985 # average ReadReq mshr miss latency 907system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency 908system.cpu0.icache.demand_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency 909system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11991.416985 # average overall mshr miss latency 910system.cpu0.icache.overall_avg_mshr_miss_latency::total 11991.416985 # average overall mshr miss latency 911system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 912system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 913system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 914system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 915system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 916system.cpu0.dcache.replacements 275305 # number of replacements 917system.cpu0.dcache.tagsinuse 476.472696 # Cycle average of tags in use 918system.cpu0.dcache.total_refs 9563233 # Total number of references to valid blocks. 919system.cpu0.dcache.sampled_refs 275817 # Sample count of references to valid blocks. 920system.cpu0.dcache.avg_refs 34.672384 # Average number of references to valid blocks. 921system.cpu0.dcache.warmup_cycle 50121000 # Cycle when the warmup percentage was hit. 922system.cpu0.dcache.occ_blocks::cpu0.data 476.472696 # Average occupied blocks per requestor 923system.cpu0.dcache.occ_percent::cpu0.data 0.930611 # Average percentage of cache occupancy 924system.cpu0.dcache.occ_percent::total 0.930611 # Average percentage of cache occupancy 925system.cpu0.dcache.ReadReq_hits::cpu0.data 5934886 # number of ReadReq hits 926system.cpu0.dcache.ReadReq_hits::total 5934886 # number of ReadReq hits 927system.cpu0.dcache.WriteReq_hits::cpu0.data 3237835 # number of WriteReq hits 928system.cpu0.dcache.WriteReq_hits::total 3237835 # number of WriteReq hits 929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174610 # number of LoadLockedReq hits 930system.cpu0.dcache.LoadLockedReq_hits::total 174610 # number of LoadLockedReq hits 931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171576 # number of StoreCondReq hits 932system.cpu0.dcache.StoreCondReq_hits::total 171576 # number of StoreCondReq hits 933system.cpu0.dcache.demand_hits::cpu0.data 9172721 # number of demand (read+write) hits 934system.cpu0.dcache.demand_hits::total 9172721 # number of demand (read+write) hits 935system.cpu0.dcache.overall_hits::cpu0.data 9172721 # number of overall hits 936system.cpu0.dcache.overall_hits::total 9172721 # number of overall hits 937system.cpu0.dcache.ReadReq_misses::cpu0.data 390009 # number of ReadReq misses 938system.cpu0.dcache.ReadReq_misses::total 390009 # number of ReadReq misses 939system.cpu0.dcache.WriteReq_misses::cpu0.data 1580289 # number of WriteReq misses 940system.cpu0.dcache.WriteReq_misses::total 1580289 # number of WriteReq misses 941system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses 942system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses 943system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7755 # number of StoreCondReq misses 944system.cpu0.dcache.StoreCondReq_misses::total 7755 # number of StoreCondReq misses 945system.cpu0.dcache.demand_misses::cpu0.data 1970298 # number of demand (read+write) misses 946system.cpu0.dcache.demand_misses::total 1970298 # number of demand (read+write) misses 947system.cpu0.dcache.overall_misses::cpu0.data 1970298 # number of overall misses 948system.cpu0.dcache.overall_misses::total 1970298 # number of overall misses 949system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5381478000 # number of ReadReq miss cycles 950system.cpu0.dcache.ReadReq_miss_latency::total 5381478000 # number of ReadReq miss cycles 951system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64293852363 # number of WriteReq miss cycles 952system.cpu0.dcache.WriteReq_miss_latency::total 64293852363 # number of WriteReq miss cycles 953system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88752000 # number of LoadLockedReq miss cycles 954system.cpu0.dcache.LoadLockedReq_miss_latency::total 88752000 # number of LoadLockedReq miss cycles 955system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 73359500 # number of StoreCondReq miss cycles 956system.cpu0.dcache.StoreCondReq_miss_latency::total 73359500 # number of StoreCondReq miss cycles 957system.cpu0.dcache.demand_miss_latency::cpu0.data 69675330363 # number of demand (read+write) miss cycles 958system.cpu0.dcache.demand_miss_latency::total 69675330363 # number of demand (read+write) miss cycles 959system.cpu0.dcache.overall_miss_latency::cpu0.data 69675330363 # number of overall miss cycles 960system.cpu0.dcache.overall_miss_latency::total 69675330363 # number of overall miss cycles 961system.cpu0.dcache.ReadReq_accesses::cpu0.data 6324895 # number of ReadReq accesses(hits+misses) 962system.cpu0.dcache.ReadReq_accesses::total 6324895 # number of ReadReq accesses(hits+misses) 963system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818124 # number of WriteReq accesses(hits+misses) 964system.cpu0.dcache.WriteReq_accesses::total 4818124 # number of WriteReq accesses(hits+misses) 965system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183513 # number of LoadLockedReq accesses(hits+misses) 966system.cpu0.dcache.LoadLockedReq_accesses::total 183513 # number of LoadLockedReq accesses(hits+misses) 967system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179331 # number of StoreCondReq accesses(hits+misses) 968system.cpu0.dcache.StoreCondReq_accesses::total 179331 # number of StoreCondReq accesses(hits+misses) 969system.cpu0.dcache.demand_accesses::cpu0.data 11143019 # number of demand (read+write) accesses 970system.cpu0.dcache.demand_accesses::total 11143019 # number of demand (read+write) accesses 971system.cpu0.dcache.overall_accesses::cpu0.data 11143019 # number of overall (read+write) accesses 972system.cpu0.dcache.overall_accesses::total 11143019 # number of overall (read+write) accesses 973system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061663 # miss rate for ReadReq accesses 974system.cpu0.dcache.ReadReq_miss_rate::total 0.061663 # miss rate for ReadReq accesses 975system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327988 # miss rate for WriteReq accesses 976system.cpu0.dcache.WriteReq_miss_rate::total 0.327988 # miss rate for WriteReq accesses 977system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048514 # miss rate for LoadLockedReq accesses 978system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048514 # miss rate for LoadLockedReq accesses 979system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043244 # miss rate for StoreCondReq accesses 980system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043244 # miss rate for StoreCondReq accesses 981system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176819 # miss rate for demand accesses 982system.cpu0.dcache.demand_miss_rate::total 0.176819 # miss rate for demand accesses 983system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176819 # miss rate for overall accesses 984system.cpu0.dcache.overall_miss_rate::total 0.176819 # miss rate for overall accesses 985system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13798.343115 # average ReadReq miss latency 986system.cpu0.dcache.ReadReq_avg_miss_latency::total 13798.343115 # average ReadReq miss latency 987system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40684.869896 # average WriteReq miss latency 988system.cpu0.dcache.WriteReq_avg_miss_latency::total 40684.869896 # average WriteReq miss latency 989system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.774570 # average LoadLockedReq miss latency 990system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.774570 # average LoadLockedReq miss latency 991system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9459.638943 # average StoreCondReq miss latency 992system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9459.638943 # average StoreCondReq miss latency 993system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35362.838699 # average overall miss latency 994system.cpu0.dcache.demand_avg_miss_latency::total 35362.838699 # average overall miss latency 995system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35362.838699 # average overall miss latency 996system.cpu0.dcache.overall_avg_miss_latency::total 35362.838699 # average overall miss latency 997system.cpu0.dcache.blocked_cycles::no_mshrs 7486 # number of cycles access was blocked 998system.cpu0.dcache.blocked_cycles::no_targets 3477 # number of cycles access was blocked 999system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked 1000system.cpu0.dcache.blocked::no_targets 90 # number of cycles access was blocked 1001system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.464029 # average number of cycles each access was blocked 1002system.cpu0.dcache.avg_blocked_cycles::no_targets 38.633333 # average number of cycles each access was blocked 1003system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1004system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1005system.cpu0.dcache.writebacks::writebacks 255914 # number of writebacks 1006system.cpu0.dcache.writebacks::total 255914 # number of writebacks 1007system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200897 # number of ReadReq MSHR hits 1008system.cpu0.dcache.ReadReq_mshr_hits::total 200897 # number of ReadReq MSHR hits 1009system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449259 # number of WriteReq MSHR hits 1010system.cpu0.dcache.WriteReq_mshr_hits::total 1449259 # number of WriteReq MSHR hits 1011system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 477 # number of LoadLockedReq MSHR hits 1012system.cpu0.dcache.LoadLockedReq_mshr_hits::total 477 # number of LoadLockedReq MSHR hits 1013system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650156 # number of demand (read+write) MSHR hits 1014system.cpu0.dcache.demand_mshr_hits::total 1650156 # number of demand (read+write) MSHR hits 1015system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650156 # number of overall MSHR hits 1016system.cpu0.dcache.overall_mshr_hits::total 1650156 # number of overall MSHR hits 1017system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189112 # number of ReadReq MSHR misses 1018system.cpu0.dcache.ReadReq_mshr_misses::total 189112 # number of ReadReq MSHR misses 1019system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131030 # number of WriteReq MSHR misses 1020system.cpu0.dcache.WriteReq_mshr_misses::total 131030 # number of WriteReq MSHR misses 1021system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8426 # number of LoadLockedReq MSHR misses 1022system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8426 # number of LoadLockedReq MSHR misses 1023system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7752 # number of StoreCondReq MSHR misses 1024system.cpu0.dcache.StoreCondReq_mshr_misses::total 7752 # number of StoreCondReq MSHR misses 1025system.cpu0.dcache.demand_mshr_misses::cpu0.data 320142 # number of demand (read+write) MSHR misses 1026system.cpu0.dcache.demand_mshr_misses::total 320142 # number of demand (read+write) MSHR misses 1027system.cpu0.dcache.overall_mshr_misses::cpu0.data 320142 # number of overall MSHR misses 1028system.cpu0.dcache.overall_mshr_misses::total 320142 # number of overall MSHR misses 1029system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2327531500 # number of ReadReq MSHR miss cycles 1030system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2327531500 # number of ReadReq MSHR miss cycles 1031system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4469430491 # number of WriteReq MSHR miss cycles 1032system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4469430491 # number of WriteReq MSHR miss cycles 1033system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67004000 # number of LoadLockedReq MSHR miss cycles 1034system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67004000 # number of LoadLockedReq MSHR miss cycles 1035system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 57855500 # number of StoreCondReq MSHR miss cycles 1036system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 57855500 # number of StoreCondReq MSHR miss cycles 1037system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6796961991 # number of demand (read+write) MSHR miss cycles 1038system.cpu0.dcache.demand_mshr_miss_latency::total 6796961991 # number of demand (read+write) MSHR miss cycles 1039system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6796961991 # number of overall MSHR miss cycles 1040system.cpu0.dcache.overall_mshr_miss_latency::total 6796961991 # number of overall MSHR miss cycles 1041system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432598000 # number of ReadReq MSHR uncacheable cycles 1042system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432598000 # number of ReadReq MSHR uncacheable cycles 1043system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1289898395 # number of WriteReq MSHR uncacheable cycles 1044system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1289898395 # number of WriteReq MSHR uncacheable cycles 1045system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14722496395 # number of overall MSHR uncacheable cycles 1046system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14722496395 # number of overall MSHR uncacheable cycles 1047system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029900 # mshr miss rate for ReadReq accesses 1048system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadReq accesses 1049system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027195 # mshr miss rate for WriteReq accesses 1050system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027195 # mshr miss rate for WriteReq accesses 1051system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045915 # mshr miss rate for LoadLockedReq accesses 1052system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045915 # mshr miss rate for LoadLockedReq accesses 1053system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043227 # mshr miss rate for StoreCondReq accesses 1054system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043227 # mshr miss rate for StoreCondReq accesses 1055system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for demand accesses 1056system.cpu0.dcache.demand_mshr_miss_rate::total 0.028730 # mshr miss rate for demand accesses 1057system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for overall accesses 1058system.cpu0.dcache.overall_mshr_miss_rate::total 0.028730 # mshr miss rate for overall accesses 1059system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12307.688037 # average ReadReq mshr miss latency 1060system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12307.688037 # average ReadReq mshr miss latency 1061system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34109.978562 # average WriteReq mshr miss latency 1062system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34109.978562 # average WriteReq mshr miss latency 1063system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7952.053169 # average LoadLockedReq mshr miss latency 1064system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.053169 # average LoadLockedReq mshr miss latency 1065system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7463.299794 # average StoreCondReq mshr miss latency 1066system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7463.299794 # average StoreCondReq mshr miss latency 1067system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency 1068system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency 1069system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency 1070system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency 1071system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1072system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1073system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1074system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1075system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1076system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1077system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1078system.cpu1.dtb.inst_hits 0 # ITB inst hits 1079system.cpu1.dtb.inst_misses 0 # ITB inst misses 1080system.cpu1.dtb.read_hits 43411799 # DTB read hits 1081system.cpu1.dtb.read_misses 44882 # DTB read misses 1082system.cpu1.dtb.write_hits 7014123 # DTB write hits 1083system.cpu1.dtb.write_misses 11858 # DTB write misses 1084system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1085system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1086system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1087system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1088system.cpu1.dtb.flush_entries 2347 # Number of entries that have been flushed from TLB 1089system.cpu1.dtb.align_faults 3336 # Number of TLB faults due to alignment restrictions 1090system.cpu1.dtb.prefetch_faults 317 # Number of TLB faults due to prefetch 1091system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1092system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions 1093system.cpu1.dtb.read_accesses 43456681 # DTB read accesses 1094system.cpu1.dtb.write_accesses 7025981 # DTB write accesses 1095system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1096system.cpu1.dtb.hits 50425922 # DTB hits 1097system.cpu1.dtb.misses 56740 # DTB misses 1098system.cpu1.dtb.accesses 50482662 # DTB accesses 1099system.cpu1.itb.inst_hits 9129638 # ITB inst hits 1100system.cpu1.itb.inst_misses 6055 # ITB inst misses 1101system.cpu1.itb.read_hits 0 # DTB read hits 1102system.cpu1.itb.read_misses 0 # DTB read misses 1103system.cpu1.itb.write_hits 0 # DTB write hits 1104system.cpu1.itb.write_misses 0 # DTB write misses 1105system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1106system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1107system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1108system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1109system.cpu1.itb.flush_entries 1576 # Number of entries that have been flushed from TLB 1110system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1111system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1112system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1113system.cpu1.itb.perms_faults 1653 # Number of TLB faults due to permissions restrictions 1114system.cpu1.itb.read_accesses 0 # DTB read accesses 1115system.cpu1.itb.write_accesses 0 # DTB write accesses 1116system.cpu1.itb.inst_accesses 9135693 # ITB inst accesses 1117system.cpu1.itb.hits 9129638 # DTB hits 1118system.cpu1.itb.misses 6055 # DTB misses 1119system.cpu1.itb.accesses 9135693 # DTB accesses 1120system.cpu1.numCycles 413048277 # number of cpu cycles simulated 1121system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1122system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1123system.cpu1.BPredUnit.lookups 9610060 # Number of BP lookups 1124system.cpu1.BPredUnit.condPredicted 7888453 # Number of conditional branches predicted 1125system.cpu1.BPredUnit.condIncorrect 467347 # Number of conditional branches incorrect 1126system.cpu1.BPredUnit.BTBLookups 6680212 # Number of BTB lookups 1127system.cpu1.BPredUnit.BTBHits 5602853 # Number of BTB hits 1128system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1129system.cpu1.BPredUnit.usedRAS 834872 # Number of times the RAS was used to get a target. 1130system.cpu1.BPredUnit.RASInCorrect 50683 # Number of incorrect RAS predictions. 1131system.cpu1.fetch.icacheStallCycles 20902821 # Number of cycles fetch is stalled on an Icache miss 1132system.cpu1.fetch.Insts 71155819 # Number of instructions fetch has processed 1133system.cpu1.fetch.Branches 9610060 # Number of branches that fetch encountered 1134system.cpu1.fetch.predictedBranches 6437725 # Number of branches that fetch has predicted taken 1135system.cpu1.fetch.Cycles 15200148 # Number of cycles fetch has run and was not squashing or blocked 1136system.cpu1.fetch.SquashCycles 4519747 # Number of cycles fetch has spent squashing 1137system.cpu1.fetch.TlbCycles 75962 # Number of cycles fetch has spent waiting for tlb 1138system.cpu1.fetch.BlockedCycles 79085155 # Number of cycles fetch has spent blocked 1139system.cpu1.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1140system.cpu1.fetch.PendingTrapStallCycles 48956 # Number of stall cycles due to pending traps 1141system.cpu1.fetch.PendingQuiesceStallCycles 142448 # Number of stall cycles due to pending quiesce instructions 1142system.cpu1.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR 1143system.cpu1.fetch.CacheLines 9127576 # Number of cache lines fetched 1144system.cpu1.fetch.IcacheSquashes 837727 # Number of outstanding Icache misses that were squashed 1145system.cpu1.fetch.ItlbSquashes 3443 # Number of outstanding ITLB misses that were squashed 1146system.cpu1.fetch.rateDist::samples 118542872 # Number of instructions fetched each cycle (Total) 1147system.cpu1.fetch.rateDist::mean 0.725366 # Number of instructions fetched each cycle (Total) 1148system.cpu1.fetch.rateDist::stdev 2.076680 # Number of instructions fetched each cycle (Total) 1149system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1150system.cpu1.fetch.rateDist::0 103350754 87.18% 87.18% # Number of instructions fetched each cycle (Total) 1151system.cpu1.fetch.rateDist::1 840912 0.71% 87.89% # Number of instructions fetched each cycle (Total) 1152system.cpu1.fetch.rateDist::2 1013712 0.86% 88.75% # Number of instructions fetched each cycle (Total) 1153system.cpu1.fetch.rateDist::3 2056350 1.73% 90.48% # Number of instructions fetched each cycle (Total) 1154system.cpu1.fetch.rateDist::4 1628340 1.37% 91.86% # Number of instructions fetched each cycle (Total) 1155system.cpu1.fetch.rateDist::5 605586 0.51% 92.37% # Number of instructions fetched each cycle (Total) 1156system.cpu1.fetch.rateDist::6 2262195 1.91% 94.28% # Number of instructions fetched each cycle (Total) 1157system.cpu1.fetch.rateDist::7 445115 0.38% 94.65% # Number of instructions fetched each cycle (Total) 1158system.cpu1.fetch.rateDist::8 6339908 5.35% 100.00% # Number of instructions fetched each cycle (Total) 1159system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1160system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1161system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1162system.cpu1.fetch.rateDist::total 118542872 # Number of instructions fetched each cycle (Total) 1163system.cpu1.fetch.branchRate 0.023266 # Number of branch fetches per cycle 1164system.cpu1.fetch.rate 0.172270 # Number of inst fetches per cycle 1165system.cpu1.decode.IdleCycles 22607772 # Number of cycles decode is idle 1166system.cpu1.decode.BlockedCycles 78712094 # Number of cycles decode is blocked 1167system.cpu1.decode.RunCycles 13698658 # Number of cycles decode is running 1168system.cpu1.decode.UnblockCycles 543937 # Number of cycles decode is unblocking 1169system.cpu1.decode.SquashCycles 2980411 # Number of cycles decode is squashing 1170system.cpu1.decode.BranchResolved 1178240 # Number of times decode resolved a branch 1171system.cpu1.decode.BranchMispred 102814 # Number of times decode detected a branch misprediction 1172system.cpu1.decode.DecodedInsts 80488884 # Number of instructions handled by decode 1173system.cpu1.decode.SquashedInsts 342985 # Number of squashed instructions handled by decode 1174system.cpu1.rename.SquashCycles 2980411 # Number of cycles rename is squashing 1175system.cpu1.rename.IdleCycles 24131061 # Number of cycles rename is idle 1176system.cpu1.rename.BlockCycles 32829819 # Number of cycles rename is blocking 1177system.cpu1.rename.serializeStallCycles 41497762 # count of cycles rename stalled for serializing inst 1178system.cpu1.rename.RunCycles 12625753 # Number of cycles rename is running 1179system.cpu1.rename.UnblockCycles 4478066 # Number of cycles rename is unblocking 1180system.cpu1.rename.RenamedInsts 74194515 # Number of instructions processed by rename 1181system.cpu1.rename.ROBFullEvents 19311 # Number of times rename has blocked due to ROB full 1182system.cpu1.rename.IQFullEvents 694411 # Number of times rename has blocked due to IQ full 1183system.cpu1.rename.LSQFullEvents 3187694 # Number of times rename has blocked due to LSQ full 1184system.cpu1.rename.FullRegisterEvents 34028 # Number of times there has been no free registers 1185system.cpu1.rename.RenamedOperands 78612274 # Number of destination operands rename has renamed 1186system.cpu1.rename.RenameLookups 341980095 # Number of register rename lookups that rename has made 1187system.cpu1.rename.int_rename_lookups 341920829 # Number of integer rename lookups 1188system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups 1189system.cpu1.rename.CommittedMaps 50181552 # Number of HB maps that are committed 1190system.cpu1.rename.UndoneMaps 28430722 # Number of HB maps that are undone due to squashing 1191system.cpu1.rename.serializingInsts 479709 # count of serializing insts renamed 1192system.cpu1.rename.tempSerializingInsts 419295 # count of temporary serializing insts renamed 1193system.cpu1.rename.skidInsts 8182404 # count of insts added to the skid buffer 1194system.cpu1.memDep0.insertedLoads 13956070 # Number of loads inserted to the mem dependence unit. 1195system.cpu1.memDep0.insertedStores 8535310 # Number of stores inserted to the mem dependence unit. 1196system.cpu1.memDep0.conflictingLoads 1073815 # Number of conflicting loads. 1197system.cpu1.memDep0.conflictingStores 1496663 # Number of conflicting stores. 1198system.cpu1.iq.iqInstsAdded 66987245 # Number of instructions added to the IQ (excludes non-spec) 1199system.cpu1.iq.iqNonSpecInstsAdded 1207542 # Number of non-speculative instructions added to the IQ 1200system.cpu1.iq.iqInstsIssued 91662010 # Number of instructions issued 1201system.cpu1.iq.iqSquashedInstsIssued 107326 # Number of squashed instructions issued 1202system.cpu1.iq.iqSquashedInstsExamined 18596353 # Number of squashed instructions iterated over during squash; mainly for profiling 1203system.cpu1.iq.iqSquashedOperandsExamined 52788554 # Number of squashed operands that are examined and possibly removed from graph 1204system.cpu1.iq.iqSquashedNonSpecRemoved 287891 # Number of squashed non-spec instructions that were removed 1205system.cpu1.iq.issued_per_cycle::samples 118542872 # Number of insts issued each cycle 1206system.cpu1.iq.issued_per_cycle::mean 0.773239 # Number of insts issued each cycle 1207system.cpu1.iq.issued_per_cycle::stdev 1.509704 # Number of insts issued each cycle 1208system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1209system.cpu1.iq.issued_per_cycle::0 87045508 73.43% 73.43% # Number of insts issued each cycle 1210system.cpu1.iq.issued_per_cycle::1 8827320 7.45% 80.88% # Number of insts issued each cycle 1211system.cpu1.iq.issued_per_cycle::2 4565356 3.85% 84.73% # Number of insts issued each cycle 1212system.cpu1.iq.issued_per_cycle::3 3971386 3.35% 88.08% # Number of insts issued each cycle 1213system.cpu1.iq.issued_per_cycle::4 10748062 9.07% 97.14% # Number of insts issued each cycle 1214system.cpu1.iq.issued_per_cycle::5 1958505 1.65% 98.80% # Number of insts issued each cycle 1215system.cpu1.iq.issued_per_cycle::6 1059536 0.89% 99.69% # Number of insts issued each cycle 1216system.cpu1.iq.issued_per_cycle::7 289761 0.24% 99.93% # Number of insts issued each cycle 1217system.cpu1.iq.issued_per_cycle::8 77438 0.07% 100.00% # Number of insts issued each cycle 1218system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1219system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1220system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1221system.cpu1.iq.issued_per_cycle::total 118542872 # Number of insts issued each cycle 1222system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1223system.cpu1.iq.fu_full::IntAlu 27804 0.35% 0.35% # attempts to use FU when none available 1224system.cpu1.iq.fu_full::IntMult 991 0.01% 0.36% # attempts to use FU when none available 1225system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available 1226system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available 1227system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available 1228system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available 1229system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available 1230system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available 1231system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available 1232system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available 1233system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available 1234system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available 1235system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available 1236system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available 1237system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available 1238system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available 1239system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available 1240system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available 1241system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available 1242system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available 1243system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available 1244system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available 1245system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available 1246system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available 1247system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available 1248system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available 1249system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available 1250system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available 1251system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available 1252system.cpu1.iq.fu_full::MemRead 7575099 95.91% 96.28% # attempts to use FU when none available 1253system.cpu1.iq.fu_full::MemWrite 294066 3.72% 100.00% # attempts to use FU when none available 1254system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1255system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1256system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued 1257system.cpu1.iq.FU_type_0::IntAlu 39285679 42.86% 43.20% # Type of FU issued 1258system.cpu1.iq.FU_type_0::IntMult 61425 0.07% 43.27% # Type of FU issued 1259system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.27% # Type of FU issued 1260system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.27% # Type of FU issued 1261system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.27% # Type of FU issued 1262system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.27% # Type of FU issued 1263system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.27% # Type of FU issued 1264system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.27% # Type of FU issued 1265system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.27% # Type of FU issued 1266system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.27% # Type of FU issued 1267system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.27% # Type of FU issued 1268system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.27% # Type of FU issued 1269system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.27% # Type of FU issued 1270system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.27% # Type of FU issued 1271system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.27% # Type of FU issued 1272system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.27% # Type of FU issued 1273system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.27% # Type of FU issued 1274system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.27% # Type of FU issued 1275system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.27% # Type of FU issued 1276system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.27% # Type of FU issued 1277system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.27% # Type of FU issued 1278system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.27% # Type of FU issued 1279system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.27% # Type of FU issued 1280system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.27% # Type of FU issued 1281system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.27% # Type of FU issued 1282system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 43.27% # Type of FU issued 1283system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.27% # Type of FU issued 1284system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.27% # Type of FU issued 1285system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.27% # Type of FU issued 1286system.cpu1.iq.FU_type_0::MemRead 44600762 48.66% 91.93% # Type of FU issued 1287system.cpu1.iq.FU_type_0::MemWrite 7398685 8.07% 100.00% # Type of FU issued 1288system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1289system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1290system.cpu1.iq.FU_type_0::total 91662010 # Type of FU issued 1291system.cpu1.iq.rate 0.221916 # Inst issue rate 1292system.cpu1.iq.fu_busy_cnt 7897960 # FU busy when requested 1293system.cpu1.iq.fu_busy_rate 0.086164 # FU busy rate (busy events/executed inst) 1294system.cpu1.iq.int_inst_queue_reads 309913949 # Number of integer instruction queue reads 1295system.cpu1.iq.int_inst_queue_writes 86800137 # Number of integer instruction queue writes 1296system.cpu1.iq.int_inst_queue_wakeup_accesses 55536555 # Number of integer instruction queue wakeup accesses 1297system.cpu1.iq.fp_inst_queue_reads 14796 # Number of floating instruction queue reads 1298system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes 1299system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses 1300system.cpu1.iq.int_alu_accesses 99238492 # Number of integer alu accesses 1301system.cpu1.iq.fp_alu_accesses 7741 # Number of floating point alu accesses 1302system.cpu1.iew.lsq.thread0.forwLoads 357612 # Number of loads that had data forwarded from stores 1303system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1304system.cpu1.iew.lsq.thread0.squashedLoads 3966417 # Number of loads squashed 1305system.cpu1.iew.lsq.thread0.ignoredResponses 4317 # Number of memory responses ignored because the instruction is squashed 1306system.cpu1.iew.lsq.thread0.memOrderViolation 17649 # Number of memory ordering violations 1307system.cpu1.iew.lsq.thread0.squashedStores 1516764 # Number of stores squashed 1308system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1309system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1310system.cpu1.iew.lsq.thread0.rescheduledLoads 31964885 # Number of loads that were rescheduled 1311system.cpu1.iew.lsq.thread0.cacheBlocked 1028430 # Number of times an access to memory failed due to the cache being blocked 1312system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1313system.cpu1.iew.iewSquashCycles 2980411 # Number of cycles IEW is squashing 1314system.cpu1.iew.iewBlockCycles 24884610 # Number of cycles IEW is blocking 1315system.cpu1.iew.iewUnblockCycles 372296 # Number of cycles IEW is unblocking 1316system.cpu1.iew.iewDispatchedInsts 68300564 # Number of instructions dispatched to IQ 1317system.cpu1.iew.iewDispSquashedInsts 134907 # Number of squashed instructions skipped by dispatch 1318system.cpu1.iew.iewDispLoadInsts 13956070 # Number of dispatched load instructions 1319system.cpu1.iew.iewDispStoreInsts 8535310 # Number of dispatched store instructions 1320system.cpu1.iew.iewDispNonSpecInsts 896808 # Number of dispatched non-speculative instructions 1321system.cpu1.iew.iewIQFullEvents 67508 # Number of times the IQ has become full, causing a stall 1322system.cpu1.iew.iewLSQFullEvents 3396 # Number of times the LSQ has become full, causing a stall 1323system.cpu1.iew.memOrderViolationEvents 17649 # Number of memory order violations 1324system.cpu1.iew.predictedTakenIncorrect 244559 # Number of branches that were predicted taken incorrectly 1325system.cpu1.iew.predictedNotTakenIncorrect 171299 # Number of branches that were predicted not taken incorrectly 1326system.cpu1.iew.branchMispredicts 415858 # Number of branch mispredicts detected at execute 1327system.cpu1.iew.iewExecutedInsts 88842251 # Number of executed instructions 1328system.cpu1.iew.iewExecLoadInsts 43794323 # Number of load instructions executed 1329system.cpu1.iew.iewExecSquashedInsts 2819759 # Number of squashed instructions skipped in execute 1330system.cpu1.iew.exec_swp 0 # number of swp insts executed 1331system.cpu1.iew.exec_nop 105777 # number of nop insts executed 1332system.cpu1.iew.exec_refs 51113945 # number of memory reference insts executed 1333system.cpu1.iew.exec_branches 7256967 # Number of branches executed 1334system.cpu1.iew.exec_stores 7319622 # Number of stores executed 1335system.cpu1.iew.exec_rate 0.215089 # Inst execution rate 1336system.cpu1.iew.wb_sent 87693649 # cumulative count of insts sent to commit 1337system.cpu1.iew.wb_count 55543356 # cumulative count of insts written-back 1338system.cpu1.iew.wb_producers 30809625 # num instructions producing a value 1339system.cpu1.iew.wb_consumers 54951337 # num instructions consuming a value 1340system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1341system.cpu1.iew.wb_rate 0.134472 # insts written-back per cycle 1342system.cpu1.iew.wb_fanout 0.560671 # average fanout of values written-back 1343system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1344system.cpu1.commit.commitSquashedInsts 18558974 # The number of squashed insts skipped by commit 1345system.cpu1.commit.commitNonSpecStalls 919651 # The number of times commit has been forced to stall to communicate backwards 1346system.cpu1.commit.branchMispredicts 366370 # The number of times a branch was mispredicted 1347system.cpu1.commit.committed_per_cycle::samples 115610884 # Number of insts commited each cycle 1348system.cpu1.commit.committed_per_cycle::mean 0.426428 # Number of insts commited each cycle 1349system.cpu1.commit.committed_per_cycle::stdev 1.387814 # Number of insts commited each cycle 1350system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1351system.cpu1.commit.committed_per_cycle::0 98380656 85.10% 85.10% # Number of insts commited each cycle 1352system.cpu1.commit.committed_per_cycle::1 8456019 7.31% 92.41% # Number of insts commited each cycle 1353system.cpu1.commit.committed_per_cycle::2 2240447 1.94% 94.35% # Number of insts commited each cycle 1354system.cpu1.commit.committed_per_cycle::3 1287846 1.11% 95.46% # Number of insts commited each cycle 1355system.cpu1.commit.committed_per_cycle::4 1284560 1.11% 96.57% # Number of insts commited each cycle 1356system.cpu1.commit.committed_per_cycle::5 584416 0.51% 97.08% # Number of insts commited each cycle 1357system.cpu1.commit.committed_per_cycle::6 1022455 0.88% 97.96% # Number of insts commited each cycle 1358system.cpu1.commit.committed_per_cycle::7 531646 0.46% 98.42% # Number of insts commited each cycle 1359system.cpu1.commit.committed_per_cycle::8 1822839 1.58% 100.00% # Number of insts commited each cycle 1360system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1361system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1362system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1363system.cpu1.commit.committed_per_cycle::total 115610884 # Number of insts commited each cycle 1364system.cpu1.commit.committedInsts 38938330 # Number of instructions committed 1365system.cpu1.commit.committedOps 49299735 # Number of ops (including micro ops) committed 1366system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1367system.cpu1.commit.refs 17008199 # Number of memory references committed 1368system.cpu1.commit.loads 9989653 # Number of loads committed 1369system.cpu1.commit.membars 202304 # Number of memory barriers committed 1370system.cpu1.commit.branches 6136573 # Number of branches committed 1371system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1372system.cpu1.commit.int_insts 43691789 # Number of committed integer instructions. 1373system.cpu1.commit.function_calls 556207 # Number of function calls committed. 1374system.cpu1.commit.bw_lim_events 1822839 # number cycles where commit BW limit reached 1375system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1376system.cpu1.rob.rob_reads 180532357 # The number of ROB reads 1377system.cpu1.rob.rob_writes 138785705 # The number of ROB writes 1378system.cpu1.timesIdled 1423841 # Number of times that the entire CPU went into an idle state and unscheduled itself 1379system.cpu1.idleCycles 294505405 # Total number of cycles that the CPU has spent unscheduled due to idling 1380system.cpu1.quiesceCycles 4793867333 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1381system.cpu1.committedInsts 38868691 # Number of Instructions Simulated 1382system.cpu1.committedOps 49230096 # Number of Ops (including micro ops) Simulated 1383system.cpu1.committedInsts_total 38868691 # Number of Instructions Simulated 1384system.cpu1.cpi 10.626761 # CPI: Cycles Per Instruction 1385system.cpu1.cpi_total 10.626761 # CPI: Total CPI of All Threads 1386system.cpu1.ipc 0.094102 # IPC: Instructions Per Cycle 1387system.cpu1.ipc_total 0.094102 # IPC: Total IPC of All Threads 1388system.cpu1.int_regfile_reads 397649399 # number of integer regfile reads 1389system.cpu1.int_regfile_writes 58356680 # number of integer regfile writes 1390system.cpu1.fp_regfile_reads 4927 # number of floating regfile reads 1391system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes 1392system.cpu1.misc_regfile_reads 90861332 # number of misc regfile reads 1393system.cpu1.misc_regfile_writes 429704 # number of misc regfile writes 1394system.cpu1.icache.replacements 621691 # number of replacements 1395system.cpu1.icache.tagsinuse 498.705536 # Cycle average of tags in use 1396system.cpu1.icache.total_refs 8457096 # Total number of references to valid blocks. 1397system.cpu1.icache.sampled_refs 622203 # Sample count of references to valid blocks. 1398system.cpu1.icache.avg_refs 13.592181 # Average number of references to valid blocks. 1399system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit. 1400system.cpu1.icache.occ_blocks::cpu1.inst 498.705536 # Average occupied blocks per requestor 1401system.cpu1.icache.occ_percent::cpu1.inst 0.974034 # Average percentage of cache occupancy 1402system.cpu1.icache.occ_percent::total 0.974034 # Average percentage of cache occupancy 1403system.cpu1.icache.ReadReq_hits::cpu1.inst 8457096 # number of ReadReq hits 1404system.cpu1.icache.ReadReq_hits::total 8457096 # number of ReadReq hits 1405system.cpu1.icache.demand_hits::cpu1.inst 8457096 # number of demand (read+write) hits 1406system.cpu1.icache.demand_hits::total 8457096 # number of demand (read+write) hits 1407system.cpu1.icache.overall_hits::cpu1.inst 8457096 # number of overall hits 1408system.cpu1.icache.overall_hits::total 8457096 # number of overall hits 1409system.cpu1.icache.ReadReq_misses::cpu1.inst 670427 # number of ReadReq misses 1410system.cpu1.icache.ReadReq_misses::total 670427 # number of ReadReq misses 1411system.cpu1.icache.demand_misses::cpu1.inst 670427 # number of demand (read+write) misses 1412system.cpu1.icache.demand_misses::total 670427 # number of demand (read+write) misses 1413system.cpu1.icache.overall_misses::cpu1.inst 670427 # number of overall misses 1414system.cpu1.icache.overall_misses::total 670427 # number of overall misses 1415system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8963788993 # number of ReadReq miss cycles 1416system.cpu1.icache.ReadReq_miss_latency::total 8963788993 # number of ReadReq miss cycles 1417system.cpu1.icache.demand_miss_latency::cpu1.inst 8963788993 # number of demand (read+write) miss cycles 1418system.cpu1.icache.demand_miss_latency::total 8963788993 # number of demand (read+write) miss cycles 1419system.cpu1.icache.overall_miss_latency::cpu1.inst 8963788993 # number of overall miss cycles 1420system.cpu1.icache.overall_miss_latency::total 8963788993 # number of overall miss cycles 1421system.cpu1.icache.ReadReq_accesses::cpu1.inst 9127523 # number of ReadReq accesses(hits+misses) 1422system.cpu1.icache.ReadReq_accesses::total 9127523 # number of ReadReq accesses(hits+misses) 1423system.cpu1.icache.demand_accesses::cpu1.inst 9127523 # number of demand (read+write) accesses 1424system.cpu1.icache.demand_accesses::total 9127523 # number of demand (read+write) accesses 1425system.cpu1.icache.overall_accesses::cpu1.inst 9127523 # number of overall (read+write) accesses 1426system.cpu1.icache.overall_accesses::total 9127523 # number of overall (read+write) accesses 1427system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073451 # miss rate for ReadReq accesses 1428system.cpu1.icache.ReadReq_miss_rate::total 0.073451 # miss rate for ReadReq accesses 1429system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073451 # miss rate for demand accesses 1430system.cpu1.icache.demand_miss_rate::total 0.073451 # miss rate for demand accesses 1431system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073451 # miss rate for overall accesses 1432system.cpu1.icache.overall_miss_rate::total 0.073451 # miss rate for overall accesses 1433system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13370.268490 # average ReadReq miss latency 1434system.cpu1.icache.ReadReq_avg_miss_latency::total 13370.268490 # average ReadReq miss latency 1435system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency 1436system.cpu1.icache.demand_avg_miss_latency::total 13370.268490 # average overall miss latency 1437system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency 1438system.cpu1.icache.overall_avg_miss_latency::total 13370.268490 # average overall miss latency 1439system.cpu1.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked 1440system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1441system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked 1442system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1443system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.184211 # average number of cycles each access was blocked 1444system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1445system.cpu1.icache.fast_writes 0 # number of fast writes performed 1446system.cpu1.icache.cache_copies 0 # number of cache copies performed 1447system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48189 # number of ReadReq MSHR hits 1448system.cpu1.icache.ReadReq_mshr_hits::total 48189 # number of ReadReq MSHR hits 1449system.cpu1.icache.demand_mshr_hits::cpu1.inst 48189 # number of demand (read+write) MSHR hits 1450system.cpu1.icache.demand_mshr_hits::total 48189 # number of demand (read+write) MSHR hits 1451system.cpu1.icache.overall_mshr_hits::cpu1.inst 48189 # number of overall MSHR hits 1452system.cpu1.icache.overall_mshr_hits::total 48189 # number of overall MSHR hits 1453system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622238 # number of ReadReq MSHR misses 1454system.cpu1.icache.ReadReq_mshr_misses::total 622238 # number of ReadReq MSHR misses 1455system.cpu1.icache.demand_mshr_misses::cpu1.inst 622238 # number of demand (read+write) MSHR misses 1456system.cpu1.icache.demand_mshr_misses::total 622238 # number of demand (read+write) MSHR misses 1457system.cpu1.icache.overall_mshr_misses::cpu1.inst 622238 # number of overall MSHR misses 1458system.cpu1.icache.overall_mshr_misses::total 622238 # number of overall MSHR misses 1459system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328903994 # number of ReadReq MSHR miss cycles 1460system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328903994 # number of ReadReq MSHR miss cycles 1461system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328903994 # number of demand (read+write) MSHR miss cycles 1462system.cpu1.icache.demand_mshr_miss_latency::total 7328903994 # number of demand (read+write) MSHR miss cycles 1463system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328903994 # number of overall MSHR miss cycles 1464system.cpu1.icache.overall_mshr_miss_latency::total 7328903994 # number of overall MSHR miss cycles 1465system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3208500 # number of ReadReq MSHR uncacheable cycles 1466system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3208500 # number of ReadReq MSHR uncacheable cycles 1467system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3208500 # number of overall MSHR uncacheable cycles 1468system.cpu1.icache.overall_mshr_uncacheable_latency::total 3208500 # number of overall MSHR uncacheable cycles 1469system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for ReadReq accesses 1470system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068172 # mshr miss rate for ReadReq accesses 1471system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for demand accesses 1472system.cpu1.icache.demand_mshr_miss_rate::total 0.068172 # mshr miss rate for demand accesses 1473system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for overall accesses 1474system.cpu1.icache.overall_mshr_miss_rate::total 0.068172 # mshr miss rate for overall accesses 1475system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average ReadReq mshr miss latency 1476system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11778.297041 # average ReadReq mshr miss latency 1477system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency 1478system.cpu1.icache.demand_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency 1479system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency 1480system.cpu1.icache.overall_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency 1481system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1482system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1483system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1484system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1485system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1486system.cpu1.dcache.replacements 363699 # number of replacements 1487system.cpu1.dcache.tagsinuse 487.062362 # Cycle average of tags in use 1488system.cpu1.dcache.total_refs 13149394 # Total number of references to valid blocks. 1489system.cpu1.dcache.sampled_refs 364069 # Sample count of references to valid blocks. 1490system.cpu1.dcache.avg_refs 36.117862 # Average number of references to valid blocks. 1491system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit. 1492system.cpu1.dcache.occ_blocks::cpu1.data 487.062362 # Average occupied blocks per requestor 1493system.cpu1.dcache.occ_percent::cpu1.data 0.951294 # Average percentage of cache occupancy 1494system.cpu1.dcache.occ_percent::total 0.951294 # Average percentage of cache occupancy 1495system.cpu1.dcache.ReadReq_hits::cpu1.data 8615849 # number of ReadReq hits 1496system.cpu1.dcache.ReadReq_hits::total 8615849 # number of ReadReq hits 1497system.cpu1.dcache.WriteReq_hits::cpu1.data 4289025 # number of WriteReq hits 1498system.cpu1.dcache.WriteReq_hits::total 4289025 # number of WriteReq hits 1499system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104659 # number of LoadLockedReq hits 1500system.cpu1.dcache.LoadLockedReq_hits::total 104659 # number of LoadLockedReq hits 1501system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100738 # number of StoreCondReq hits 1502system.cpu1.dcache.StoreCondReq_hits::total 100738 # number of StoreCondReq hits 1503system.cpu1.dcache.demand_hits::cpu1.data 12904874 # number of demand (read+write) hits 1504system.cpu1.dcache.demand_hits::total 12904874 # number of demand (read+write) hits 1505system.cpu1.dcache.overall_hits::cpu1.data 12904874 # number of overall hits 1506system.cpu1.dcache.overall_hits::total 12904874 # number of overall hits 1507system.cpu1.dcache.ReadReq_misses::cpu1.data 398775 # number of ReadReq misses 1508system.cpu1.dcache.ReadReq_misses::total 398775 # number of ReadReq misses 1509system.cpu1.dcache.WriteReq_misses::cpu1.data 1559814 # number of WriteReq misses 1510system.cpu1.dcache.WriteReq_misses::total 1559814 # number of WriteReq misses 1511system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14251 # number of LoadLockedReq misses 1512system.cpu1.dcache.LoadLockedReq_misses::total 14251 # number of LoadLockedReq misses 1513system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10935 # number of StoreCondReq misses 1514system.cpu1.dcache.StoreCondReq_misses::total 10935 # number of StoreCondReq misses 1515system.cpu1.dcache.demand_misses::cpu1.data 1958589 # number of demand (read+write) misses 1516system.cpu1.dcache.demand_misses::total 1958589 # number of demand (read+write) misses 1517system.cpu1.dcache.overall_misses::cpu1.data 1958589 # number of overall misses 1518system.cpu1.dcache.overall_misses::total 1958589 # number of overall misses 1519system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5911762000 # number of ReadReq miss cycles 1520system.cpu1.dcache.ReadReq_miss_latency::total 5911762000 # number of ReadReq miss cycles 1521system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56390406018 # number of WriteReq miss cycles 1522system.cpu1.dcache.WriteReq_miss_latency::total 56390406018 # number of WriteReq miss cycles 1523system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131021000 # number of LoadLockedReq miss cycles 1524system.cpu1.dcache.LoadLockedReq_miss_latency::total 131021000 # number of LoadLockedReq miss cycles 1525system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 76240500 # number of StoreCondReq miss cycles 1526system.cpu1.dcache.StoreCondReq_miss_latency::total 76240500 # number of StoreCondReq miss cycles 1527system.cpu1.dcache.demand_miss_latency::cpu1.data 62302168018 # number of demand (read+write) miss cycles 1528system.cpu1.dcache.demand_miss_latency::total 62302168018 # number of demand (read+write) miss cycles 1529system.cpu1.dcache.overall_miss_latency::cpu1.data 62302168018 # number of overall miss cycles 1530system.cpu1.dcache.overall_miss_latency::total 62302168018 # number of overall miss cycles 1531system.cpu1.dcache.ReadReq_accesses::cpu1.data 9014624 # number of ReadReq accesses(hits+misses) 1532system.cpu1.dcache.ReadReq_accesses::total 9014624 # number of ReadReq accesses(hits+misses) 1533system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848839 # number of WriteReq accesses(hits+misses) 1534system.cpu1.dcache.WriteReq_accesses::total 5848839 # number of WriteReq accesses(hits+misses) 1535system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 118910 # number of LoadLockedReq accesses(hits+misses) 1536system.cpu1.dcache.LoadLockedReq_accesses::total 118910 # number of LoadLockedReq accesses(hits+misses) 1537system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111673 # number of StoreCondReq accesses(hits+misses) 1538system.cpu1.dcache.StoreCondReq_accesses::total 111673 # number of StoreCondReq accesses(hits+misses) 1539system.cpu1.dcache.demand_accesses::cpu1.data 14863463 # number of demand (read+write) accesses 1540system.cpu1.dcache.demand_accesses::total 14863463 # number of demand (read+write) accesses 1541system.cpu1.dcache.overall_accesses::cpu1.data 14863463 # number of overall (read+write) accesses 1542system.cpu1.dcache.overall_accesses::total 14863463 # number of overall (read+write) accesses 1543system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044236 # miss rate for ReadReq accesses 1544system.cpu1.dcache.ReadReq_miss_rate::total 0.044236 # miss rate for ReadReq accesses 1545system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.266688 # miss rate for WriteReq accesses 1546system.cpu1.dcache.WriteReq_miss_rate::total 0.266688 # miss rate for WriteReq accesses 1547system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119847 # miss rate for LoadLockedReq accesses 1548system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119847 # miss rate for LoadLockedReq accesses 1549system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses 1550system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses 1551system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131772 # miss rate for demand accesses 1552system.cpu1.dcache.demand_miss_rate::total 0.131772 # miss rate for demand accesses 1553system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131772 # miss rate for overall accesses 1554system.cpu1.dcache.overall_miss_rate::total 0.131772 # miss rate for overall accesses 1555system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14824.805968 # average ReadReq miss latency 1556system.cpu1.dcache.ReadReq_avg_miss_latency::total 14824.805968 # average ReadReq miss latency 1557system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36152.006597 # average WriteReq miss latency 1558system.cpu1.dcache.WriteReq_avg_miss_latency::total 36152.006597 # average WriteReq miss latency 1559system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9193.810961 # average LoadLockedReq miss latency 1560system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9193.810961 # average LoadLockedReq miss latency 1561system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6972.153635 # average StoreCondReq miss latency 1562system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6972.153635 # average StoreCondReq miss latency 1563system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency 1564system.cpu1.dcache.demand_avg_miss_latency::total 31809.720170 # average overall miss latency 1565system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency 1566system.cpu1.dcache.overall_avg_miss_latency::total 31809.720170 # average overall miss latency 1567system.cpu1.dcache.blocked_cycles::no_mshrs 24015 # number of cycles access was blocked 1568system.cpu1.dcache.blocked_cycles::no_targets 11108 # number of cycles access was blocked 1569system.cpu1.dcache.blocked::no_mshrs 3240 # number of cycles access was blocked 1570system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked 1571system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.412037 # average number of cycles each access was blocked 1572system.cpu1.dcache.avg_blocked_cycles::no_targets 66.119048 # average number of cycles each access was blocked 1573system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1574system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1575system.cpu1.dcache.writebacks::writebacks 328533 # number of writebacks 1576system.cpu1.dcache.writebacks::total 328533 # number of writebacks 1577system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 166830 # number of ReadReq MSHR hits 1578system.cpu1.dcache.ReadReq_mshr_hits::total 166830 # number of ReadReq MSHR hits 1579system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1397003 # number of WriteReq MSHR hits 1580system.cpu1.dcache.WriteReq_mshr_hits::total 1397003 # number of WriteReq MSHR hits 1581system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1431 # number of LoadLockedReq MSHR hits 1582system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1431 # number of LoadLockedReq MSHR hits 1583system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563833 # number of demand (read+write) MSHR hits 1584system.cpu1.dcache.demand_mshr_hits::total 1563833 # number of demand (read+write) MSHR hits 1585system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563833 # number of overall MSHR hits 1586system.cpu1.dcache.overall_mshr_hits::total 1563833 # number of overall MSHR hits 1587system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231945 # number of ReadReq MSHR misses 1588system.cpu1.dcache.ReadReq_mshr_misses::total 231945 # number of ReadReq MSHR misses 1589system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162811 # number of WriteReq MSHR misses 1590system.cpu1.dcache.WriteReq_mshr_misses::total 162811 # number of WriteReq MSHR misses 1591system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12820 # number of LoadLockedReq MSHR misses 1592system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12820 # number of LoadLockedReq MSHR misses 1593system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10928 # number of StoreCondReq MSHR misses 1594system.cpu1.dcache.StoreCondReq_mshr_misses::total 10928 # number of StoreCondReq MSHR misses 1595system.cpu1.dcache.demand_mshr_misses::cpu1.data 394756 # number of demand (read+write) MSHR misses 1596system.cpu1.dcache.demand_mshr_misses::total 394756 # number of demand (read+write) MSHR misses 1597system.cpu1.dcache.overall_mshr_misses::cpu1.data 394756 # number of overall MSHR misses 1598system.cpu1.dcache.overall_mshr_misses::total 394756 # number of overall MSHR misses 1599system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2840785000 # number of ReadReq MSHR miss cycles 1600system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2840785000 # number of ReadReq MSHR miss cycles 1601system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5178833227 # number of WriteReq MSHR miss cycles 1602system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5178833227 # number of WriteReq MSHR miss cycles 1603system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89705500 # number of LoadLockedReq MSHR miss cycles 1604system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89705500 # number of LoadLockedReq MSHR miss cycles 1605system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54384500 # number of StoreCondReq MSHR miss cycles 1606system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54384500 # number of StoreCondReq MSHR miss cycles 1607system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8019618227 # number of demand (read+write) MSHR miss cycles 1608system.cpu1.dcache.demand_mshr_miss_latency::total 8019618227 # number of demand (read+write) MSHR miss cycles 1609system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8019618227 # number of overall MSHR miss cycles 1610system.cpu1.dcache.overall_mshr_miss_latency::total 8019618227 # number of overall MSHR miss cycles 1611system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169259240500 # number of ReadReq MSHR uncacheable cycles 1612system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169259240500 # number of ReadReq MSHR uncacheable cycles 1613system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40718348836 # number of WriteReq MSHR uncacheable cycles 1614system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40718348836 # number of WriteReq MSHR uncacheable cycles 1615system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209977589336 # number of overall MSHR uncacheable cycles 1616system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209977589336 # number of overall MSHR uncacheable cycles 1617system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025730 # mshr miss rate for ReadReq accesses 1618system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025730 # mshr miss rate for ReadReq accesses 1619system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027836 # mshr miss rate for WriteReq accesses 1620system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027836 # mshr miss rate for WriteReq accesses 1621system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107813 # mshr miss rate for LoadLockedReq accesses 1622system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107813 # mshr miss rate for LoadLockedReq accesses 1623system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097857 # mshr miss rate for StoreCondReq accesses 1624system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097857 # mshr miss rate for StoreCondReq accesses 1625system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for demand accesses 1626system.cpu1.dcache.demand_mshr_miss_rate::total 0.026559 # mshr miss rate for demand accesses 1627system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for overall accesses 1628system.cpu1.dcache.overall_mshr_miss_rate::total 0.026559 # mshr miss rate for overall accesses 1629system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12247.666473 # average ReadReq mshr miss latency 1630system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12247.666473 # average ReadReq mshr miss latency 1631system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31808.865660 # average WriteReq mshr miss latency 1632system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31808.865660 # average WriteReq mshr miss latency 1633system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6997.308892 # average LoadLockedReq mshr miss latency 1634system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6997.308892 # average LoadLockedReq mshr miss latency 1635system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4976.619693 # average StoreCondReq mshr miss latency 1636system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4976.619693 # average StoreCondReq mshr miss latency 1637system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency 1638system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency 1639system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency 1640system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency 1641system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1642system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1643system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1644system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1645system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1646system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1647system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1648system.iocache.replacements 0 # number of replacements 1649system.iocache.tagsinuse 0 # Cycle average of tags in use 1650system.iocache.total_refs 0 # Total number of references to valid blocks. 1651system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1652system.iocache.avg_refs nan # Average number of references to valid blocks. 1653system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1654system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1655system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1656system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1657system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1658system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1659system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1660system.iocache.fast_writes 0 # number of fast writes performed 1661system.iocache.cache_copies 0 # number of cache copies performed 1662system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of ReadReq MSHR uncacheable cycles 1663system.iocache.ReadReq_mshr_uncacheable_latency::total 1218779341193 # number of ReadReq MSHR uncacheable cycles 1664system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of overall MSHR uncacheable cycles 1665system.iocache.overall_mshr_uncacheable_latency::total 1218779341193 # number of overall MSHR uncacheable cycles 1666system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1667system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1668system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1669system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1670system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1671system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1672system.cpu0.kern.inst.quiesce 43799 # number of quiesce instructions executed 1673system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1674system.cpu1.kern.inst.quiesce 53911 # number of quiesce instructions executed 1675 1676---------- End Simulation Statistics ---------- 1677