stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.570834 # Number of seconds simulated 4sim_ticks 2570833934500 # Number of ticks simulated 5final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 53678 # Simulator instruction rate (inst/s) 8host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2225327298 # Simulator tick rate (ticks/s) 10host_mem_usage 390932 # Number of bytes of host memory used 11host_seconds 1155.26 # Real time elapsed on the host 12sim_insts 62012062 # Number of instructions simulated 13sim_ops 80088895 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory 23system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 30system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) 73system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 74system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory 76system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 79system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 80system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory 82system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 86system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) 87system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) 88system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 89system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) 90system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) 91system.l2c.replacements 130926 # number of replacements 92system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use 93system.l2c.total_refs 1855308 # Total number of references to valid blocks. 94system.l2c.sampled_refs 161029 # Sample count of references to valid blocks. 95system.l2c.avg_refs 11.521577 # Average number of references to valid blocks. 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 97system.l2c.occ_blocks::writebacks 15187.159331 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 17.600608 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.006762 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu0.inst 2177.920948 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 1032.752170 # Average occupied blocks per requestor 102system.l2c.occ_blocks::cpu1.dtb.walker 22.717912 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.014158 # Average occupied blocks per requestor 104system.l2c.occ_blocks::cpu1.inst 4068.026765 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 5070.431306 # Average occupied blocks per requestor 106system.l2c.occ_percent::writebacks 0.231738 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu0.dtb.walker 0.000269 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 109system.l2c.occ_percent::cpu0.inst 0.033232 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.015759 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000347 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.062073 # Average percentage of cache occupancy 114system.l2c.occ_percent::cpu1.data 0.077369 # Average percentage of cache occupancy 115system.l2c.occ_percent::total 0.420786 # Average percentage of cache occupancy 116system.l2c.ReadReq_hits::cpu0.dtb.walker 51294 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu0.inst 335682 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu0.data 133493 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.dtb.walker 112013 # number of ReadReq hits 121system.l2c.ReadReq_hits::cpu1.itb.walker 7283 # number of ReadReq hits 122system.l2c.ReadReq_hits::cpu1.inst 702787 # number of ReadReq hits 123system.l2c.ReadReq_hits::cpu1.data 231603 # number of ReadReq hits 124system.l2c.ReadReq_hits::total 1579905 # number of ReadReq hits 125system.l2c.Writeback_hits::writebacks 606768 # number of Writeback hits 126system.l2c.Writeback_hits::total 606768 # number of Writeback hits 127system.l2c.UpgradeReq_hits::cpu0.data 925 # number of UpgradeReq hits 128system.l2c.UpgradeReq_hits::cpu1.data 1139 # number of UpgradeReq hits 129system.l2c.UpgradeReq_hits::total 2064 # number of UpgradeReq hits 130system.l2c.SCUpgradeReq_hits::cpu0.data 217 # number of SCUpgradeReq hits 131system.l2c.SCUpgradeReq_hits::cpu1.data 388 # number of SCUpgradeReq hits 132system.l2c.SCUpgradeReq_hits::total 605 # number of SCUpgradeReq hits 133system.l2c.ReadExReq_hits::cpu0.data 35350 # number of ReadExReq hits 134system.l2c.ReadExReq_hits::cpu1.data 66066 # number of ReadExReq hits 135system.l2c.ReadExReq_hits::total 101416 # number of ReadExReq hits 136system.l2c.demand_hits::cpu0.dtb.walker 51294 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu0.itb.walker 5750 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu0.inst 335682 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu0.data 168843 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.dtb.walker 112013 # number of demand (read+write) hits 141system.l2c.demand_hits::cpu1.itb.walker 7283 # number of demand (read+write) hits 142system.l2c.demand_hits::cpu1.inst 702787 # number of demand (read+write) hits 143system.l2c.demand_hits::cpu1.data 297669 # number of demand (read+write) hits 144system.l2c.demand_hits::total 1681321 # number of demand (read+write) hits 145system.l2c.overall_hits::cpu0.dtb.walker 51294 # number of overall hits 146system.l2c.overall_hits::cpu0.itb.walker 5750 # number of overall hits 147system.l2c.overall_hits::cpu0.inst 335682 # number of overall hits 148system.l2c.overall_hits::cpu0.data 168843 # number of overall hits 149system.l2c.overall_hits::cpu1.dtb.walker 112013 # number of overall hits 150system.l2c.overall_hits::cpu1.itb.walker 7283 # number of overall hits 151system.l2c.overall_hits::cpu1.inst 702787 # number of overall hits 152system.l2c.overall_hits::cpu1.data 297669 # number of overall hits 153system.l2c.overall_hits::total 1681321 # number of overall hits 154system.l2c.ReadReq_misses::cpu0.dtb.walker 84 # number of ReadReq misses 155system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses 156system.l2c.ReadReq_misses::cpu0.inst 8376 # number of ReadReq misses 157system.l2c.ReadReq_misses::cpu0.data 8805 # number of ReadReq misses 158system.l2c.ReadReq_misses::cpu1.dtb.walker 61 # number of ReadReq misses 159system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 160system.l2c.ReadReq_misses::cpu1.inst 10197 # number of ReadReq misses 161system.l2c.ReadReq_misses::cpu1.data 12824 # number of ReadReq misses 162system.l2c.ReadReq_misses::total 40353 # number of ReadReq misses 163system.l2c.UpgradeReq_misses::cpu0.data 5201 # number of UpgradeReq misses 164system.l2c.UpgradeReq_misses::cpu1.data 5819 # number of UpgradeReq misses 165system.l2c.UpgradeReq_misses::total 11020 # number of UpgradeReq misses 166system.l2c.SCUpgradeReq_misses::cpu0.data 788 # number of SCUpgradeReq misses 167system.l2c.SCUpgradeReq_misses::cpu1.data 600 # number of SCUpgradeReq misses 168system.l2c.SCUpgradeReq_misses::total 1388 # number of SCUpgradeReq misses 169system.l2c.ReadExReq_misses::cpu0.data 65908 # number of ReadExReq misses 170system.l2c.ReadExReq_misses::cpu1.data 81633 # number of ReadExReq misses 171system.l2c.ReadExReq_misses::total 147541 # number of ReadExReq misses 172system.l2c.demand_misses::cpu0.dtb.walker 84 # number of demand (read+write) misses 173system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses 174system.l2c.demand_misses::cpu0.inst 8376 # number of demand (read+write) misses 175system.l2c.demand_misses::cpu0.data 74713 # number of demand (read+write) misses 176system.l2c.demand_misses::cpu1.dtb.walker 61 # number of demand (read+write) misses 177system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu1.inst 10197 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu1.data 94457 # number of demand (read+write) misses 180system.l2c.demand_misses::total 187894 # number of demand (read+write) misses 181system.l2c.overall_misses::cpu0.dtb.walker 84 # number of overall misses 182system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses 183system.l2c.overall_misses::cpu0.inst 8376 # number of overall misses 184system.l2c.overall_misses::cpu0.data 74713 # number of overall misses 185system.l2c.overall_misses::cpu1.dtb.walker 61 # number of overall misses 186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 10197 # number of overall misses 188system.l2c.overall_misses::cpu1.data 94457 # number of overall misses 189system.l2c.overall_misses::total 187894 # number of overall misses 190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4383500 # number of ReadReq miss cycles 191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 261000 # number of ReadReq miss cycles 192system.l2c.ReadReq_miss_latency::cpu0.inst 438009000 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu0.data 459487500 # number of ReadReq miss cycles 194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 3183500 # number of ReadReq miss cycles 195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles 196system.l2c.ReadReq_miss_latency::cpu1.inst 533470500 # number of ReadReq miss cycles 197system.l2c.ReadReq_miss_latency::cpu1.data 669975500 # number of ReadReq miss cycles 198system.l2c.ReadReq_miss_latency::total 2108822500 # number of ReadReq miss cycles 199system.l2c.UpgradeReq_miss_latency::cpu0.data 18089500 # number of UpgradeReq miss cycles 200system.l2c.UpgradeReq_miss_latency::cpu1.data 38874000 # number of UpgradeReq miss cycles 201system.l2c.UpgradeReq_miss_latency::total 56963500 # number of UpgradeReq miss cycles 202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2245500 # number of SCUpgradeReq miss cycles 203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5381000 # number of SCUpgradeReq miss cycles 204system.l2c.SCUpgradeReq_miss_latency::total 7626500 # number of SCUpgradeReq miss cycles 205system.l2c.ReadExReq_miss_latency::cpu0.data 3455909999 # number of ReadExReq miss cycles 206system.l2c.ReadExReq_miss_latency::cpu1.data 4284020000 # number of ReadExReq miss cycles 207system.l2c.ReadExReq_miss_latency::total 7739929999 # number of ReadExReq miss cycles 208system.l2c.demand_miss_latency::cpu0.dtb.walker 4383500 # number of demand (read+write) miss cycles 209system.l2c.demand_miss_latency::cpu0.itb.walker 261000 # number of demand (read+write) miss cycles 210system.l2c.demand_miss_latency::cpu0.inst 438009000 # number of demand (read+write) miss cycles 211system.l2c.demand_miss_latency::cpu0.data 3915397499 # number of demand (read+write) miss cycles 212system.l2c.demand_miss_latency::cpu1.dtb.walker 3183500 # number of demand (read+write) miss cycles 213system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles 214system.l2c.demand_miss_latency::cpu1.inst 533470500 # number of demand (read+write) miss cycles 215system.l2c.demand_miss_latency::cpu1.data 4953995500 # number of demand (read+write) miss cycles 216system.l2c.demand_miss_latency::total 9848752499 # number of demand (read+write) miss cycles 217system.l2c.overall_miss_latency::cpu0.dtb.walker 4383500 # number of overall miss cycles 218system.l2c.overall_miss_latency::cpu0.itb.walker 261000 # number of overall miss cycles 219system.l2c.overall_miss_latency::cpu0.inst 438009000 # number of overall miss cycles 220system.l2c.overall_miss_latency::cpu0.data 3915397499 # number of overall miss cycles 221system.l2c.overall_miss_latency::cpu1.dtb.walker 3183500 # number of overall miss cycles 222system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles 223system.l2c.overall_miss_latency::cpu1.inst 533470500 # number of overall miss cycles 224system.l2c.overall_miss_latency::cpu1.data 4953995500 # number of overall miss cycles 225system.l2c.overall_miss_latency::total 9848752499 # number of overall miss cycles 226system.l2c.ReadReq_accesses::cpu0.dtb.walker 51378 # number of ReadReq accesses(hits+misses) 227system.l2c.ReadReq_accesses::cpu0.itb.walker 5755 # number of ReadReq accesses(hits+misses) 228system.l2c.ReadReq_accesses::cpu0.inst 344058 # number of ReadReq accesses(hits+misses) 229system.l2c.ReadReq_accesses::cpu0.data 142298 # number of ReadReq accesses(hits+misses) 230system.l2c.ReadReq_accesses::cpu1.dtb.walker 112074 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu1.itb.walker 7284 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu1.inst 712984 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu1.data 244427 # number of ReadReq accesses(hits+misses) 234system.l2c.ReadReq_accesses::total 1620258 # number of ReadReq accesses(hits+misses) 235system.l2c.Writeback_accesses::writebacks 606768 # number of Writeback accesses(hits+misses) 236system.l2c.Writeback_accesses::total 606768 # number of Writeback accesses(hits+misses) 237system.l2c.UpgradeReq_accesses::cpu0.data 6126 # number of UpgradeReq accesses(hits+misses) 238system.l2c.UpgradeReq_accesses::cpu1.data 6958 # number of UpgradeReq accesses(hits+misses) 239system.l2c.UpgradeReq_accesses::total 13084 # number of UpgradeReq accesses(hits+misses) 240system.l2c.SCUpgradeReq_accesses::cpu0.data 1005 # number of SCUpgradeReq accesses(hits+misses) 241system.l2c.SCUpgradeReq_accesses::cpu1.data 988 # number of SCUpgradeReq accesses(hits+misses) 242system.l2c.SCUpgradeReq_accesses::total 1993 # number of SCUpgradeReq accesses(hits+misses) 243system.l2c.ReadExReq_accesses::cpu0.data 101258 # number of ReadExReq accesses(hits+misses) 244system.l2c.ReadExReq_accesses::cpu1.data 147699 # number of ReadExReq accesses(hits+misses) 245system.l2c.ReadExReq_accesses::total 248957 # number of ReadExReq accesses(hits+misses) 246system.l2c.demand_accesses::cpu0.dtb.walker 51378 # number of demand (read+write) accesses 247system.l2c.demand_accesses::cpu0.itb.walker 5755 # number of demand (read+write) accesses 248system.l2c.demand_accesses::cpu0.inst 344058 # number of demand (read+write) accesses 249system.l2c.demand_accesses::cpu0.data 243556 # number of demand (read+write) accesses 250system.l2c.demand_accesses::cpu1.dtb.walker 112074 # number of demand (read+write) accesses 251system.l2c.demand_accesses::cpu1.itb.walker 7284 # number of demand (read+write) accesses 252system.l2c.demand_accesses::cpu1.inst 712984 # number of demand (read+write) accesses 253system.l2c.demand_accesses::cpu1.data 392126 # number of demand (read+write) accesses 254system.l2c.demand_accesses::total 1869215 # number of demand (read+write) accesses 255system.l2c.overall_accesses::cpu0.dtb.walker 51378 # number of overall (read+write) accesses 256system.l2c.overall_accesses::cpu0.itb.walker 5755 # number of overall (read+write) accesses 257system.l2c.overall_accesses::cpu0.inst 344058 # number of overall (read+write) accesses 258system.l2c.overall_accesses::cpu0.data 243556 # number of overall (read+write) accesses 259system.l2c.overall_accesses::cpu1.dtb.walker 112074 # number of overall (read+write) accesses 260system.l2c.overall_accesses::cpu1.itb.walker 7284 # number of overall (read+write) accesses 261system.l2c.overall_accesses::cpu1.inst 712984 # number of overall (read+write) accesses 262system.l2c.overall_accesses::cpu1.data 392126 # number of overall (read+write) accesses 263system.l2c.overall_accesses::total 1869215 # number of overall (read+write) accesses 264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for ReadReq accesses 265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000869 # miss rate for ReadReq accesses 266system.l2c.ReadReq_miss_rate::cpu0.inst 0.024345 # miss rate for ReadReq accesses 267system.l2c.ReadReq_miss_rate::cpu0.data 0.061877 # miss rate for ReadReq accesses 268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses 274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses 275system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses 277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses 280system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses 281system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses 283system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses 284system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.data 0.306759 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.306759 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses 299system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.838160 # average ReadReq miss latency 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average ReadReq miss latency 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency 308system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency 311system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency 314system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency 317system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency 320system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 324system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency 329system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52405.839666 # average overall miss latency 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 333system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency 336system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 337system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 338system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 339system.l2c.blocked::no_targets 0 # number of cycles access was blocked 340system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 341system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 342system.l2c.fast_writes 0 # number of fast writes performed 343system.l2c.cache_copies 0 # number of cache copies performed 344system.l2c.writebacks::writebacks 111665 # number of writebacks 345system.l2c.writebacks::total 111665 # number of writebacks 346system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits 347system.l2c.ReadReq_mshr_hits::cpu0.data 47 # number of ReadReq MSHR hits 348system.l2c.ReadReq_mshr_hits::cpu1.inst 12 # number of ReadReq MSHR hits 349system.l2c.ReadReq_mshr_hits::cpu1.data 34 # number of ReadReq MSHR hits 350system.l2c.ReadReq_mshr_hits::total 96 # number of ReadReq MSHR hits 351system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 352system.l2c.demand_mshr_hits::cpu0.data 47 # number of demand (read+write) MSHR hits 353system.l2c.demand_mshr_hits::cpu1.inst 12 # number of demand (read+write) MSHR hits 354system.l2c.demand_mshr_hits::cpu1.data 34 # number of demand (read+write) MSHR hits 355system.l2c.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits 356system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 357system.l2c.overall_mshr_hits::cpu0.data 47 # number of overall MSHR hits 358system.l2c.overall_mshr_hits::cpu1.inst 12 # number of overall MSHR hits 359system.l2c.overall_mshr_hits::cpu1.data 34 # number of overall MSHR hits 360system.l2c.overall_mshr_hits::total 96 # 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number of UpgradeReq MSHR misses 373system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 788 # number of SCUpgradeReq MSHR misses 374system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 600 # number of SCUpgradeReq MSHR misses 375system.l2c.SCUpgradeReq_mshr_misses::total 1388 # number of SCUpgradeReq MSHR misses 376system.l2c.ReadExReq_mshr_misses::cpu0.data 65908 # number of ReadExReq MSHR misses 377system.l2c.ReadExReq_mshr_misses::cpu1.data 81633 # number of ReadExReq MSHR misses 378system.l2c.ReadExReq_mshr_misses::total 147541 # number of ReadExReq MSHR misses 379system.l2c.demand_mshr_misses::cpu0.dtb.walker 84 # number of demand (read+write) MSHR misses 380system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses 381system.l2c.demand_mshr_misses::cpu0.inst 8373 # number of demand (read+write) MSHR misses 382system.l2c.demand_mshr_misses::cpu0.data 74666 # number of demand (read+write) MSHR misses 383system.l2c.demand_mshr_misses::cpu1.dtb.walker 61 # number of demand (read+write) MSHR misses 384system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 385system.l2c.demand_mshr_misses::cpu1.inst 10185 # number of demand (read+write) MSHR misses 386system.l2c.demand_mshr_misses::cpu1.data 94423 # number of demand (read+write) MSHR misses 387system.l2c.demand_mshr_misses::total 187798 # number of demand (read+write) MSHR misses 388system.l2c.overall_mshr_misses::cpu0.dtb.walker 84 # number of overall MSHR misses 389system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses 390system.l2c.overall_mshr_misses::cpu0.inst 8373 # number of overall MSHR misses 391system.l2c.overall_mshr_misses::cpu0.data 74666 # number of overall MSHR misses 392system.l2c.overall_mshr_misses::cpu1.dtb.walker 61 # number of overall MSHR misses 393system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 394system.l2c.overall_mshr_misses::cpu1.inst 10185 # number of overall MSHR misses 395system.l2c.overall_mshr_misses::cpu1.data 94423 # number of overall MSHR misses 396system.l2c.overall_mshr_misses::total 187798 # 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number of overall MSHR miss cycles 428system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2444000 # number of overall MSHR miss cycles 429system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles 430system.l2c.overall_mshr_miss_latency::cpu1.inst 408650000 # number of overall MSHR miss cycles 431system.l2c.overall_mshr_miss_latency::cpu1.data 3785632000 # number of overall MSHR miss cycles 432system.l2c.overall_mshr_miss_latency::total 7525261999 # number of overall MSHR miss cycles 433system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5668500 # number of ReadReq MSHR uncacheable cycles 434system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8235934000 # number of ReadReq MSHR uncacheable cycles 435system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles 436system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123713083500 # number of ReadReq MSHR uncacheable cycles 437system.l2c.ReadReq_mshr_uncacheable_latency::total 131956617000 # number of ReadReq MSHR uncacheable cycles 438system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 706976980 # number of WriteReq MSHR uncacheable cycles 439system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31815648332 # number of WriteReq MSHR uncacheable cycles 440system.l2c.WriteReq_mshr_uncacheable_latency::total 32522625312 # number of WriteReq MSHR uncacheable cycles 441system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5668500 # number of overall MSHR uncacheable cycles 442system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8942910980 # number of overall MSHR uncacheable cycles 443system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155528731832 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::total 164479242312 # number of overall MSHR uncacheable cycles 446system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for ReadReq accesses 447system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for ReadReq accesses 449system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061547 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses 452system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses 453system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses 454system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses 455system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses 456system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses 457system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses 458system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses 459system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses 460system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses 461system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses 462system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses 463system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses 464system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses 466system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses 467system.l2c.demand_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for demand accesses 469system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses 470system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses 471system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses 472system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses 473system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses 474system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses 475system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses 476system.l2c.overall_mshr_miss_rate::cpu0.data 0.306566 # mshr miss rate for overall accesses 477system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544 # mshr miss rate for overall accesses 478system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses 479system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses 480system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses 481system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses 482system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency 483system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency 484system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency 485system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40057.319023 # average ReadReq mshr miss latency 486system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average ReadReq mshr miss latency 487system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 488system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency 489system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency 490system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency 491system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency 492system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency 493system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency 494system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency 495system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency 496system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency 497system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency 498system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency 499system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency 500system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency 501system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency 502system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency 503system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency 504system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency 505system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 506system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency 507system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency 508system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency 509system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency 510system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency 511system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency 512system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency 513system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency 514system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 515system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency 516system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency 517system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency 518system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 519system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 520system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 521system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 522system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 523system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 524system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 525system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 526system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 527system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 528system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 529system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 530system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 531system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 533system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 534system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 535system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 536system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 537system.cf0.dma_write_txs 0 # Number of DMA write transactions. 538system.cpu0.dtb.inst_hits 0 # ITB inst hits 539system.cpu0.dtb.inst_misses 0 # ITB inst misses 540system.cpu0.dtb.read_hits 7530160 # DTB read hits 541system.cpu0.dtb.read_misses 32787 # DTB read misses 542system.cpu0.dtb.write_hits 4446652 # DTB write hits 543system.cpu0.dtb.write_misses 6213 # DTB write misses 544system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 545system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 546system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 547system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 548system.cpu0.dtb.flush_entries 2035 # Number of entries that have been flushed from TLB 549system.cpu0.dtb.align_faults 4401 # Number of TLB faults due to alignment restrictions 550system.cpu0.dtb.prefetch_faults 226 # Number of TLB faults due to prefetch 551system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 552system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions 553system.cpu0.dtb.read_accesses 7562947 # DTB read accesses 554system.cpu0.dtb.write_accesses 4452865 # DTB write accesses 555system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 556system.cpu0.dtb.hits 11976812 # DTB hits 557system.cpu0.dtb.misses 39000 # DTB misses 558system.cpu0.dtb.accesses 12015812 # DTB accesses 559system.cpu0.itb.inst_hits 3834120 # ITB inst hits 560system.cpu0.itb.inst_misses 4594 # ITB inst misses 561system.cpu0.itb.read_hits 0 # DTB read hits 562system.cpu0.itb.read_misses 0 # DTB read misses 563system.cpu0.itb.write_hits 0 # DTB write hits 564system.cpu0.itb.write_misses 0 # DTB write misses 565system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 566system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 567system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 568system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 569system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB 570system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 571system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 572system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 573system.cpu0.itb.perms_faults 1800 # Number of TLB faults due to permissions restrictions 574system.cpu0.itb.read_accesses 0 # DTB read accesses 575system.cpu0.itb.write_accesses 0 # DTB write accesses 576system.cpu0.itb.inst_accesses 3838714 # ITB inst accesses 577system.cpu0.itb.hits 3834120 # DTB hits 578system.cpu0.itb.misses 4594 # DTB misses 579system.cpu0.itb.accesses 3838714 # DTB accesses 580system.cpu0.numCycles 55537360 # number of cpu cycles simulated 581system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 582system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 583system.cpu0.BPredUnit.lookups 5204671 # Number of BP lookups 584system.cpu0.BPredUnit.condPredicted 3944570 # Number of conditional branches predicted 585system.cpu0.BPredUnit.condIncorrect 296840 # Number of conditional branches incorrect 586system.cpu0.BPredUnit.BTBLookups 3413720 # Number of BTB lookups 587system.cpu0.BPredUnit.BTBHits 2557176 # Number of BTB hits 588system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 589system.cpu0.BPredUnit.usedRAS 459948 # Number of times the RAS was used to get a target. 590system.cpu0.BPredUnit.RASInCorrect 62294 # Number of incorrect RAS predictions. 591system.cpu0.fetch.icacheStallCycles 10542481 # Number of cycles fetch is stalled on an Icache miss 592system.cpu0.fetch.Insts 27454720 # Number of instructions fetch has processed 593system.cpu0.fetch.Branches 5204671 # Number of branches that fetch encountered 594system.cpu0.fetch.predictedBranches 3017124 # Number of branches that fetch has predicted taken 595system.cpu0.fetch.Cycles 6462624 # Number of cycles fetch has run and was not squashing or blocked 596system.cpu0.fetch.SquashCycles 1388283 # Number of cycles fetch has spent squashing 597system.cpu0.fetch.TlbCycles 64249 # Number of cycles fetch has spent waiting for tlb 598system.cpu0.fetch.BlockedCycles 17511747 # Number of cycles fetch has spent blocked 599system.cpu0.fetch.MiscStallCycles 6585 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 600system.cpu0.fetch.PendingTrapStallCycles 32170 # Number of stall cycles due to pending traps 601system.cpu0.fetch.PendingQuiesceStallCycles 74952 # Number of stall cycles due to pending quiesce instructions 602system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR 603system.cpu0.fetch.CacheLines 3831976 # Number of cache lines fetched 604system.cpu0.fetch.IcacheSquashes 163321 # Number of outstanding Icache misses that were squashed 605system.cpu0.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed 606system.cpu0.fetch.rateDist::samples 35682594 # Number of instructions fetched each cycle (Total) 607system.cpu0.fetch.rateDist::mean 1.003010 # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.rateDist::stdev 2.394306 # Number of instructions fetched each cycle (Total) 609system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 610system.cpu0.fetch.rateDist::0 29226357 81.91% 81.91% # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.rateDist::1 522599 1.46% 83.37% # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::2 706764 1.98% 85.35% # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::3 578503 1.62% 86.97% # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::4 534782 1.50% 88.47% # Number of instructions fetched each cycle (Total) 615system.cpu0.fetch.rateDist::5 477839 1.34% 89.81% # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.rateDist::6 574033 1.61% 91.42% # Number of instructions fetched each cycle (Total) 617system.cpu0.fetch.rateDist::7 347894 0.97% 92.39% # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::8 2713823 7.61% 100.00% # Number of instructions fetched each cycle (Total) 619system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 620system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 621system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 622system.cpu0.fetch.rateDist::total 35682594 # Number of instructions fetched each cycle (Total) 623system.cpu0.fetch.branchRate 0.093715 # Number of branch fetches per cycle 624system.cpu0.fetch.rate 0.494347 # Number of inst fetches per cycle 625system.cpu0.decode.IdleCycles 10901751 # Number of cycles decode is idle 626system.cpu0.decode.BlockedCycles 17564449 # Number of cycles decode is blocked 627system.cpu0.decode.RunCycles 5807943 # Number of cycles decode is running 628system.cpu0.decode.UnblockCycles 476099 # Number of cycles decode is unblocking 629system.cpu0.decode.SquashCycles 932352 # Number of cycles decode is squashing 630system.cpu0.decode.BranchResolved 836954 # Number of times decode resolved a branch 631system.cpu0.decode.BranchMispred 56324 # Number of times decode detected a branch misprediction 632system.cpu0.decode.DecodedInsts 34505102 # Number of instructions handled by decode 633system.cpu0.decode.SquashedInsts 181228 # Number of squashed instructions handled by decode 634system.cpu0.rename.SquashCycles 932352 # Number of cycles rename is squashing 635system.cpu0.rename.IdleCycles 11416627 # Number of cycles rename is idle 636system.cpu0.rename.BlockCycles 4596309 # Number of cycles rename is blocking 637system.cpu0.rename.serializeStallCycles 11321409 # count of cycles rename stalled for serializing inst 638system.cpu0.rename.RunCycles 5748941 # Number of cycles rename is running 639system.cpu0.rename.UnblockCycles 1666956 # Number of cycles rename is unblocking 640system.cpu0.rename.RenamedInsts 33335658 # Number of instructions processed by rename 641system.cpu0.rename.ROBFullEvents 999 # Number of times rename has blocked due to ROB full 642system.cpu0.rename.IQFullEvents 358087 # Number of times rename has blocked due to IQ full 643system.cpu0.rename.LSQFullEvents 883877 # Number of times rename has blocked due to LSQ full 644system.cpu0.rename.FullRegisterEvents 110 # Number of times there has been no free registers 645system.cpu0.rename.RenamedOperands 33439844 # Number of destination operands rename has renamed 646system.cpu0.rename.RenameLookups 151572898 # Number of register rename lookups that rename has made 647system.cpu0.rename.int_rename_lookups 151532196 # Number of integer rename lookups 648system.cpu0.rename.fp_rename_lookups 40702 # Number of floating rename lookups 649system.cpu0.rename.CommittedMaps 25794881 # Number of HB maps that are committed 650system.cpu0.rename.UndoneMaps 7644963 # Number of HB maps that are undone due to squashing 651system.cpu0.rename.serializingInsts 390853 # count of serializing insts renamed 652system.cpu0.rename.tempSerializingInsts 354451 # count of temporary serializing insts renamed 653system.cpu0.rename.skidInsts 4284069 # count of insts added to the skid buffer 654system.cpu0.memDep0.insertedLoads 6465672 # Number of loads inserted to the mem dependence unit. 655system.cpu0.memDep0.insertedStores 4994701 # Number of stores inserted to the mem dependence unit. 656system.cpu0.memDep0.conflictingLoads 841470 # Number of conflicting loads. 657system.cpu0.memDep0.conflictingStores 890235 # Number of conflicting stores. 658system.cpu0.iq.iqInstsAdded 31482040 # Number of instructions added to the IQ (excludes non-spec) 659system.cpu0.iq.iqNonSpecInstsAdded 658671 # Number of non-speculative instructions added to the IQ 660system.cpu0.iq.iqInstsIssued 31606585 # Number of instructions issued 661system.cpu0.iq.iqSquashedInstsIssued 78774 # Number of squashed instructions issued 662system.cpu0.iq.iqSquashedInstsExamined 5676384 # Number of squashed instructions iterated over during squash; mainly for profiling 663system.cpu0.iq.iqSquashedOperandsExamined 13082280 # Number of squashed operands that are examined and possibly removed from graph 664system.cpu0.iq.iqSquashedNonSpecRemoved 117406 # Number of squashed non-spec instructions that were removed 665system.cpu0.iq.issued_per_cycle::samples 35682594 # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::mean 0.885770 # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::stdev 1.514582 # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::0 22866556 64.08% 64.08% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::1 4972769 13.94% 78.02% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::2 2602679 7.29% 85.31% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::3 1960706 5.49% 90.81% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::4 1807368 5.07% 95.87% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::5 768762 2.15% 98.03% # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::6 499053 1.40% 99.43% # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::7 158868 0.45% 99.87% # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::8 45833 0.13% 100.00% # Number of insts issued each cycle 678system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 679system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 680system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 681system.cpu0.iq.issued_per_cycle::total 35682594 # Number of insts issued each cycle 682system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 683system.cpu0.iq.fu_full::IntAlu 26479 2.83% 2.83% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IntMult 454 0.05% 2.88% # attempts to use FU when none available 685system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.88% # attempts to use FU when none available 686system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.88% # attempts to use FU when none available 687system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.88% # attempts to use FU when none available 688system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.88% # attempts to use FU when none available 689system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.88% # attempts to use FU when none available 690system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.88% # attempts to use FU when none available 691system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.88% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.88% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.88% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.88% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.88% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.88% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.88% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.88% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.88% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.88% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.88% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.88% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.88% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.88% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.88% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.88% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.88% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.88% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.88% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.88% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.88% # attempts to use FU when none available 712system.cpu0.iq.fu_full::MemRead 724595 77.49% 80.37% # attempts to use FU when none available 713system.cpu0.iq.fu_full::MemWrite 183504 19.63% 100.00% # attempts to use FU when none available 714system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 715system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 716system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued 717system.cpu0.iq.FU_type_0::IntAlu 18849345 59.64% 59.68% # Type of FU issued 718system.cpu0.iq.FU_type_0::IntMult 42325 0.13% 59.82% # Type of FU issued 719system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.82% # Type of FU issued 720system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.82% # Type of FU issued 721system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.82% # Type of FU issued 722system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.82% # Type of FU issued 723system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.82% # Type of FU issued 724system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.82% # Type of FU issued 725system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.82% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.82% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.82% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.82% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.82% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.82% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.82% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.82% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.82% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.82% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.82% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.82% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.82% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.82% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.82% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.82% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.82% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.82% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.82% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.82% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.82% # Type of FU issued 746system.cpu0.iq.FU_type_0::MemRead 7946092 25.14% 84.96% # Type of FU issued 747system.cpu0.iq.FU_type_0::MemWrite 4753870 15.04% 100.00% # Type of FU issued 748system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 749system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 750system.cpu0.iq.FU_type_0::total 31606585 # Type of FU issued 751system.cpu0.iq.rate 0.569105 # Inst issue rate 752system.cpu0.iq.fu_busy_cnt 935032 # FU busy when requested 753system.cpu0.iq.fu_busy_rate 0.029583 # FU busy rate (busy events/executed inst) 754system.cpu0.iq.int_inst_queue_reads 99937037 # Number of integer instruction queue reads 755system.cpu0.iq.int_inst_queue_writes 37821084 # Number of integer instruction queue writes 756system.cpu0.iq.int_inst_queue_wakeup_accesses 28987180 # Number of integer instruction queue wakeup accesses 757system.cpu0.iq.fp_inst_queue_reads 10596 # Number of floating instruction queue reads 758system.cpu0.iq.fp_inst_queue_writes 5532 # Number of floating instruction queue writes 759system.cpu0.iq.fp_inst_queue_wakeup_accesses 4395 # Number of floating instruction queue wakeup accesses 760system.cpu0.iq.int_alu_accesses 32521589 # Number of integer alu accesses 761system.cpu0.iq.fp_alu_accesses 5747 # Number of floating point alu accesses 762system.cpu0.iew.lsq.thread0.forwLoads 248744 # Number of loads that had data forwarded from stores 763system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 764system.cpu0.iew.lsq.thread0.squashedLoads 1245744 # Number of loads squashed 765system.cpu0.iew.lsq.thread0.ignoredResponses 3732 # Number of memory responses ignored because the instruction is squashed 766system.cpu0.iew.lsq.thread0.memOrderViolation 10021 # Number of memory ordering violations 767system.cpu0.iew.lsq.thread0.squashedStores 530307 # Number of stores squashed 768system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 769system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 770system.cpu0.iew.lsq.thread0.rescheduledLoads 1901421 # Number of loads that were rescheduled 771system.cpu0.iew.lsq.thread0.cacheBlocked 5034 # Number of times an access to memory failed due to the cache being blocked 772system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 773system.cpu0.iew.iewSquashCycles 932352 # Number of cycles IEW is squashing 774system.cpu0.iew.iewBlockCycles 3503280 # Number of cycles IEW is blocking 775system.cpu0.iew.iewUnblockCycles 78441 # Number of cycles IEW is unblocking 776system.cpu0.iew.iewDispatchedInsts 32200235 # Number of instructions dispatched to IQ 777system.cpu0.iew.iewDispSquashedInsts 121893 # Number of squashed instructions skipped by dispatch 778system.cpu0.iew.iewDispLoadInsts 6465672 # Number of dispatched load instructions 779system.cpu0.iew.iewDispStoreInsts 4994701 # Number of dispatched store instructions 780system.cpu0.iew.iewDispNonSpecInsts 398658 # Number of dispatched non-speculative instructions 781system.cpu0.iew.iewIQFullEvents 37609 # Number of times the IQ has become full, causing a stall 782system.cpu0.iew.iewLSQFullEvents 4704 # Number of times the LSQ has become full, causing a stall 783system.cpu0.iew.memOrderViolationEvents 10021 # Number of memory order violations 784system.cpu0.iew.predictedTakenIncorrect 177778 # Number of branches that were predicted taken incorrectly 785system.cpu0.iew.predictedNotTakenIncorrect 116282 # Number of branches that were predicted not taken incorrectly 786system.cpu0.iew.branchMispredicts 294060 # Number of branch mispredicts detected at execute 787system.cpu0.iew.iewExecutedInsts 31219910 # Number of executed instructions 788system.cpu0.iew.iewExecLoadInsts 7794602 # Number of load instructions executed 789system.cpu0.iew.iewExecSquashedInsts 386675 # Number of squashed instructions skipped in execute 790system.cpu0.iew.exec_swp 0 # number of swp insts executed 791system.cpu0.iew.exec_nop 59524 # number of nop insts executed 792system.cpu0.iew.exec_refs 12495671 # number of memory reference insts executed 793system.cpu0.iew.exec_branches 4074655 # Number of branches executed 794system.cpu0.iew.exec_stores 4701069 # Number of stores executed 795system.cpu0.iew.exec_rate 0.562142 # Inst execution rate 796system.cpu0.iew.wb_sent 31018630 # cumulative count of insts sent to commit 797system.cpu0.iew.wb_count 28991575 # cumulative count of insts written-back 798system.cpu0.iew.wb_producers 15563441 # num instructions producing a value 799system.cpu0.iew.wb_consumers 30561631 # num instructions consuming a value 800system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 801system.cpu0.iew.wb_rate 0.522019 # insts written-back per cycle 802system.cpu0.iew.wb_fanout 0.509248 # average fanout of values written-back 803system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 804system.cpu0.commit.commitCommittedInsts 19778635 # The number of committed instructions 805system.cpu0.commit.commitCommittedOps 26259365 # The number of committed instructions 806system.cpu0.commit.commitSquashedInsts 5789320 # The number of squashed insts skipped by commit 807system.cpu0.commit.commitNonSpecStalls 541265 # The number of times commit has been forced to stall to communicate backwards 808system.cpu0.commit.branchMispredicts 257580 # The number of times a branch was mispredicted 809system.cpu0.commit.committed_per_cycle::samples 34779040 # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::mean 0.755034 # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::stdev 1.721723 # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 813system.cpu0.commit.committed_per_cycle::0 24914736 71.64% 71.64% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::1 4928764 14.17% 85.81% # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::2 1604217 4.61% 90.42% # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::3 793137 2.28% 92.70% # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::4 618967 1.78% 94.48% # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::5 369015 1.06% 95.54% # Number of insts commited each cycle 819system.cpu0.commit.committed_per_cycle::6 397376 1.14% 96.69% # Number of insts commited each cycle 820system.cpu0.commit.committed_per_cycle::7 185067 0.53% 97.22% # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::8 967761 2.78% 100.00% # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 823system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::total 34779040 # Number of insts commited each cycle 826system.cpu0.commit.committedInsts 19778635 # Number of instructions committed 827system.cpu0.commit.committedOps 26259365 # Number of ops (including micro ops) committed 828system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 829system.cpu0.commit.refs 9684322 # Number of memory references committed 830system.cpu0.commit.loads 5219928 # Number of loads committed 831system.cpu0.commit.membars 194188 # Number of memory barriers committed 832system.cpu0.commit.branches 3591028 # Number of branches committed 833system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. 834system.cpu0.commit.int_insts 23338580 # Number of committed integer instructions. 835system.cpu0.commit.function_calls 422336 # Number of function calls committed. 836system.cpu0.commit.bw_lim_events 967761 # number cycles where commit BW limit reached 837system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 838system.cpu0.rob.rob_reads 65245448 # The number of ROB reads 839system.cpu0.rob.rob_writes 65031517 # The number of ROB writes 840system.cpu0.timesIdled 363170 # Number of times that the entire CPU went into an idle state and unscheduled itself 841system.cpu0.idleCycles 19854766 # Total number of cycles that the CPU has spent unscheduled due to idling 842system.cpu0.quiesceCycles 5085481268 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 843system.cpu0.committedInsts 19754081 # Number of Instructions Simulated 844system.cpu0.committedOps 26234811 # Number of Ops (including micro ops) Simulated 845system.cpu0.committedInsts_total 19754081 # Number of Instructions Simulated 846system.cpu0.cpi 2.811437 # CPI: Cycles Per Instruction 847system.cpu0.cpi_total 2.811437 # CPI: Total CPI of All Threads 848system.cpu0.ipc 0.355690 # IPC: Instructions Per Cycle 849system.cpu0.ipc_total 0.355690 # IPC: Total IPC of All Threads 850system.cpu0.int_regfile_reads 145547438 # number of integer regfile reads 851system.cpu0.int_regfile_writes 28450023 # number of integer regfile writes 852system.cpu0.fp_regfile_reads 4554 # number of floating regfile reads 853system.cpu0.fp_regfile_writes 434 # number of floating regfile writes 854system.cpu0.misc_regfile_reads 38991088 # number of misc regfile reads 855system.cpu0.misc_regfile_writes 443778 # number of misc regfile writes 856system.cpu0.icache.replacements 345092 # number of replacements 857system.cpu0.icache.tagsinuse 511.631515 # Cycle average of tags in use 858system.cpu0.icache.total_refs 3456613 # Total number of references to valid blocks. 859system.cpu0.icache.sampled_refs 345604 # Sample count of references to valid blocks. 860system.cpu0.icache.avg_refs 10.001658 # Average number of references to valid blocks. 861system.cpu0.icache.warmup_cycle 6336390000 # Cycle when the warmup percentage was hit. 862system.cpu0.icache.occ_blocks::cpu0.inst 511.631515 # Average occupied blocks per requestor 863system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy 864system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy 865system.cpu0.icache.ReadReq_hits::cpu0.inst 3456613 # number of ReadReq hits 866system.cpu0.icache.ReadReq_hits::total 3456613 # number of ReadReq hits 867system.cpu0.icache.demand_hits::cpu0.inst 3456613 # number of demand (read+write) hits 868system.cpu0.icache.demand_hits::total 3456613 # number of demand (read+write) hits 869system.cpu0.icache.overall_hits::cpu0.inst 3456613 # number of overall hits 870system.cpu0.icache.overall_hits::total 3456613 # number of overall hits 871system.cpu0.icache.ReadReq_misses::cpu0.inst 375216 # number of ReadReq misses 872system.cpu0.icache.ReadReq_misses::total 375216 # number of ReadReq misses 873system.cpu0.icache.demand_misses::cpu0.inst 375216 # number of demand (read+write) misses 874system.cpu0.icache.demand_misses::total 375216 # number of demand (read+write) misses 875system.cpu0.icache.overall_misses::cpu0.inst 375216 # number of overall misses 876system.cpu0.icache.overall_misses::total 375216 # number of overall misses 877system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5700257984 # number of ReadReq miss cycles 878system.cpu0.icache.ReadReq_miss_latency::total 5700257984 # number of ReadReq miss cycles 879system.cpu0.icache.demand_miss_latency::cpu0.inst 5700257984 # number of demand (read+write) miss cycles 880system.cpu0.icache.demand_miss_latency::total 5700257984 # number of demand (read+write) miss cycles 881system.cpu0.icache.overall_miss_latency::cpu0.inst 5700257984 # number of overall miss cycles 882system.cpu0.icache.overall_miss_latency::total 5700257984 # number of overall miss cycles 883system.cpu0.icache.ReadReq_accesses::cpu0.inst 3831829 # number of ReadReq accesses(hits+misses) 884system.cpu0.icache.ReadReq_accesses::total 3831829 # number of ReadReq accesses(hits+misses) 885system.cpu0.icache.demand_accesses::cpu0.inst 3831829 # number of demand (read+write) accesses 886system.cpu0.icache.demand_accesses::total 3831829 # number of demand (read+write) accesses 887system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses 888system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses 889system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses 890system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses 891system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses 892system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses 893system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses 894system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses 895system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency 896system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency 897system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency 898system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency 899system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency 900system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency 901system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked 902system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked 904system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu0.icache.avg_blocked_cycles::no_mshrs 8546.023041 # average number of cycles each access was blocked 906system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu0.icache.fast_writes 0 # number of fast writes performed 908system.cpu0.icache.cache_copies 0 # number of cache copies performed 909system.cpu0.icache.writebacks::writebacks 19422 # number of writebacks 910system.cpu0.icache.writebacks::total 19422 # number of writebacks 911system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29600 # number of ReadReq MSHR hits 912system.cpu0.icache.ReadReq_mshr_hits::total 29600 # number of ReadReq MSHR hits 913system.cpu0.icache.demand_mshr_hits::cpu0.inst 29600 # number of demand (read+write) MSHR hits 914system.cpu0.icache.demand_mshr_hits::total 29600 # number of demand (read+write) MSHR hits 915system.cpu0.icache.overall_mshr_hits::cpu0.inst 29600 # number of overall MSHR hits 916system.cpu0.icache.overall_mshr_hits::total 29600 # number of overall MSHR hits 917system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 345616 # number of ReadReq MSHR misses 918system.cpu0.icache.ReadReq_mshr_misses::total 345616 # number of ReadReq MSHR misses 919system.cpu0.icache.demand_mshr_misses::cpu0.inst 345616 # number of demand (read+write) MSHR misses 920system.cpu0.icache.demand_mshr_misses::total 345616 # number of demand (read+write) MSHR misses 921system.cpu0.icache.overall_mshr_misses::cpu0.inst 345616 # number of overall MSHR misses 922system.cpu0.icache.overall_mshr_misses::total 345616 # number of overall MSHR misses 923system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4268453987 # number of ReadReq MSHR miss cycles 924system.cpu0.icache.ReadReq_mshr_miss_latency::total 4268453987 # number of ReadReq MSHR miss cycles 925system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4268453987 # number of demand (read+write) MSHR miss cycles 926system.cpu0.icache.demand_mshr_miss_latency::total 4268453987 # number of demand (read+write) MSHR miss cycles 927system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4268453987 # number of overall MSHR miss cycles 928system.cpu0.icache.overall_mshr_miss_latency::total 4268453987 # number of overall MSHR miss cycles 929system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles 930system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles 931system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles 932system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles 933system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses 934system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses 935system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses 936system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses 937system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses 938system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses 939system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency 940system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency 941system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency 942system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency 943system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency 944system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency 945system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 946system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 947system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 948system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 949system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 950system.cpu0.dcache.replacements 232498 # number of replacements 951system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use 952system.cpu0.dcache.total_refs 7750511 # Total number of references to valid blocks. 953system.cpu0.dcache.sampled_refs 232862 # Sample count of references to valid blocks. 954system.cpu0.dcache.avg_refs 33.283709 # Average number of references to valid blocks. 955system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit. 956system.cpu0.dcache.occ_blocks::cpu0.data 430.308093 # Average occupied blocks per requestor 957system.cpu0.dcache.occ_percent::cpu0.data 0.840445 # Average percentage of cache occupancy 958system.cpu0.dcache.occ_percent::total 0.840445 # Average percentage of cache occupancy 959system.cpu0.dcache.ReadReq_hits::cpu0.data 4805960 # number of ReadReq hits 960system.cpu0.dcache.ReadReq_hits::total 4805960 # number of ReadReq hits 961system.cpu0.dcache.WriteReq_hits::cpu0.data 2599019 # number of WriteReq hits 962system.cpu0.dcache.WriteReq_hits::total 2599019 # number of WriteReq hits 963system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154744 # number of LoadLockedReq hits 964system.cpu0.dcache.LoadLockedReq_hits::total 154744 # number of LoadLockedReq hits 965system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152410 # number of StoreCondReq hits 966system.cpu0.dcache.StoreCondReq_hits::total 152410 # number of StoreCondReq hits 967system.cpu0.dcache.demand_hits::cpu0.data 7404979 # number of demand (read+write) hits 968system.cpu0.dcache.demand_hits::total 7404979 # number of demand (read+write) hits 969system.cpu0.dcache.overall_hits::cpu0.data 7404979 # number of overall hits 970system.cpu0.dcache.overall_hits::total 7404979 # number of overall hits 971system.cpu0.dcache.ReadReq_misses::cpu0.data 332693 # number of ReadReq misses 972system.cpu0.dcache.ReadReq_misses::total 332693 # number of ReadReq misses 973system.cpu0.dcache.WriteReq_misses::cpu0.data 1446995 # number of WriteReq misses 974system.cpu0.dcache.WriteReq_misses::total 1446995 # number of WriteReq misses 975system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8853 # number of LoadLockedReq misses 976system.cpu0.dcache.LoadLockedReq_misses::total 8853 # number of LoadLockedReq misses 977system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7938 # number of StoreCondReq misses 978system.cpu0.dcache.StoreCondReq_misses::total 7938 # number of StoreCondReq misses 979system.cpu0.dcache.demand_misses::cpu0.data 1779688 # number of demand (read+write) misses 980system.cpu0.dcache.demand_misses::total 1779688 # number of demand (read+write) misses 981system.cpu0.dcache.overall_misses::cpu0.data 1779688 # number of overall misses 982system.cpu0.dcache.overall_misses::total 1779688 # number of overall misses 983system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4680931500 # number of ReadReq miss cycles 984system.cpu0.dcache.ReadReq_miss_latency::total 4680931500 # number of ReadReq miss cycles 985system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59628860399 # number of WriteReq miss cycles 986system.cpu0.dcache.WriteReq_miss_latency::total 59628860399 # number of WriteReq miss cycles 987system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99729000 # number of LoadLockedReq miss cycles 988system.cpu0.dcache.LoadLockedReq_miss_latency::total 99729000 # number of LoadLockedReq miss cycles 989system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 85543000 # number of StoreCondReq miss cycles 990system.cpu0.dcache.StoreCondReq_miss_latency::total 85543000 # number of StoreCondReq miss cycles 991system.cpu0.dcache.demand_miss_latency::cpu0.data 64309791899 # number of demand (read+write) miss cycles 992system.cpu0.dcache.demand_miss_latency::total 64309791899 # number of demand (read+write) miss cycles 993system.cpu0.dcache.overall_miss_latency::cpu0.data 64309791899 # number of overall miss cycles 994system.cpu0.dcache.overall_miss_latency::total 64309791899 # number of overall miss cycles 995system.cpu0.dcache.ReadReq_accesses::cpu0.data 5138653 # number of ReadReq accesses(hits+misses) 996system.cpu0.dcache.ReadReq_accesses::total 5138653 # number of ReadReq accesses(hits+misses) 997system.cpu0.dcache.WriteReq_accesses::cpu0.data 4046014 # number of WriteReq accesses(hits+misses) 998system.cpu0.dcache.WriteReq_accesses::total 4046014 # number of WriteReq accesses(hits+misses) 999system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163597 # number of LoadLockedReq accesses(hits+misses) 1000system.cpu0.dcache.LoadLockedReq_accesses::total 163597 # number of LoadLockedReq accesses(hits+misses) 1001system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160348 # number of StoreCondReq accesses(hits+misses) 1002system.cpu0.dcache.StoreCondReq_accesses::total 160348 # number of StoreCondReq accesses(hits+misses) 1003system.cpu0.dcache.demand_accesses::cpu0.data 9184667 # number of demand (read+write) accesses 1004system.cpu0.dcache.demand_accesses::total 9184667 # number of demand (read+write) accesses 1005system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses 1006system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses 1007system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses 1008system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses 1009system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses 1010system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses 1011system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses 1012system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses 1013system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses 1014system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses 1015system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses 1016system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses 1017system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses 1018system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses 1019system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency 1020system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency 1021system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency 1022system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency 1023system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency 1024system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency 1025system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency 1026system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency 1027system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency 1028system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency 1029system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency 1030system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency 1031system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked 1032system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked 1033system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked 1034system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked 1035system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10316.831395 # average number of cycles each access was blocked 1036system.cpu0.dcache.avg_blocked_cycles::no_targets 20542.553191 # average number of cycles each access was blocked 1037system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1038system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1039system.cpu0.dcache.writebacks::writebacks 208397 # number of writebacks 1040system.cpu0.dcache.writebacks::total 208397 # number of writebacks 1041system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174332 # number of ReadReq MSHR hits 1042system.cpu0.dcache.ReadReq_mshr_hits::total 174332 # number of ReadReq MSHR hits 1043system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1328335 # number of WriteReq MSHR hits 1044system.cpu0.dcache.WriteReq_mshr_hits::total 1328335 # number of WriteReq MSHR hits 1045system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 667 # number of LoadLockedReq MSHR hits 1046system.cpu0.dcache.LoadLockedReq_mshr_hits::total 667 # number of LoadLockedReq MSHR hits 1047system.cpu0.dcache.demand_mshr_hits::cpu0.data 1502667 # number of demand (read+write) MSHR hits 1048system.cpu0.dcache.demand_mshr_hits::total 1502667 # number of demand (read+write) MSHR hits 1049system.cpu0.dcache.overall_mshr_hits::cpu0.data 1502667 # number of overall MSHR hits 1050system.cpu0.dcache.overall_mshr_hits::total 1502667 # number of overall MSHR hits 1051system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 158361 # number of ReadReq MSHR misses 1052system.cpu0.dcache.ReadReq_mshr_misses::total 158361 # number of ReadReq MSHR misses 1053system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 118660 # number of WriteReq MSHR misses 1054system.cpu0.dcache.WriteReq_mshr_misses::total 118660 # number of WriteReq MSHR misses 1055system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8186 # number of LoadLockedReq MSHR misses 1056system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8186 # number of LoadLockedReq MSHR misses 1057system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7931 # number of StoreCondReq MSHR misses 1058system.cpu0.dcache.StoreCondReq_mshr_misses::total 7931 # number of StoreCondReq MSHR misses 1059system.cpu0.dcache.demand_mshr_misses::cpu0.data 277021 # number of demand (read+write) MSHR misses 1060system.cpu0.dcache.demand_mshr_misses::total 277021 # number of demand (read+write) MSHR misses 1061system.cpu0.dcache.overall_mshr_misses::cpu0.data 277021 # number of overall MSHR misses 1062system.cpu0.dcache.overall_mshr_misses::total 277021 # number of overall MSHR misses 1063system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2036266500 # number of ReadReq MSHR miss cycles 1064system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2036266500 # number of ReadReq MSHR miss cycles 1065system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4269140489 # number of WriteReq MSHR miss cycles 1066system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4269140489 # number of WriteReq MSHR miss cycles 1067system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66637500 # number of LoadLockedReq MSHR miss cycles 1068system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66637500 # number of LoadLockedReq MSHR miss cycles 1069system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 61703000 # number of StoreCondReq MSHR miss cycles 1070system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 61703000 # number of StoreCondReq MSHR miss cycles 1071system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6305406989 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.dcache.demand_mshr_miss_latency::total 6305406989 # number of demand (read+write) MSHR miss cycles 1073system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6305406989 # number of overall MSHR miss cycles 1074system.cpu0.dcache.overall_mshr_miss_latency::total 6305406989 # number of overall MSHR miss cycles 1075system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9221981000 # number of ReadReq MSHR uncacheable cycles 1076system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9221981000 # number of ReadReq MSHR uncacheable cycles 1077system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843217391 # number of WriteReq MSHR uncacheable cycles 1078system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 # number of WriteReq MSHR uncacheable cycles 1079system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles 1080system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles 1081system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses 1082system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses 1083system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses 1084system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses 1085system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses 1086system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses 1087system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses 1088system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses 1089system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses 1090system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses 1091system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses 1092system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses 1093system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency 1094system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency 1095system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency 1096system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency 1097system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency 1098system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency 1099system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency 1100system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency 1101system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency 1102system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency 1103system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency 1104system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency 1105system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1106system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1107system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1108system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1109system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1110system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1111system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1112system.cpu1.dtb.inst_hits 0 # ITB inst hits 1113system.cpu1.dtb.inst_misses 0 # ITB inst misses 1114system.cpu1.dtb.read_hits 45335988 # DTB read hits 1115system.cpu1.dtb.read_misses 67766 # DTB read misses 1116system.cpu1.dtb.write_hits 7974825 # DTB write hits 1117system.cpu1.dtb.write_misses 20571 # DTB write misses 1118system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1119system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1120system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1121system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1122system.cpu1.dtb.flush_entries 2707 # Number of entries that have been flushed from TLB 1123system.cpu1.dtb.align_faults 7654 # Number of TLB faults due to alignment restrictions 1124system.cpu1.dtb.prefetch_faults 597 # Number of TLB faults due to prefetch 1125system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1126system.cpu1.dtb.perms_faults 1825 # Number of TLB faults due to permissions restrictions 1127system.cpu1.dtb.read_accesses 45403754 # DTB read accesses 1128system.cpu1.dtb.write_accesses 7995396 # DTB write accesses 1129system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1130system.cpu1.dtb.hits 53310813 # DTB hits 1131system.cpu1.dtb.misses 88337 # DTB misses 1132system.cpu1.dtb.accesses 53399150 # DTB accesses 1133system.cpu1.itb.inst_hits 10447082 # ITB inst hits 1134system.cpu1.itb.inst_misses 7775 # ITB inst misses 1135system.cpu1.itb.read_hits 0 # DTB read hits 1136system.cpu1.itb.read_misses 0 # DTB read misses 1137system.cpu1.itb.write_hits 0 # DTB write hits 1138system.cpu1.itb.write_misses 0 # DTB write misses 1139system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1140system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1141system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1142system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1143system.cpu1.itb.flush_entries 1562 # Number of entries that have been flushed from TLB 1144system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1145system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1146system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1147system.cpu1.itb.perms_faults 5028 # Number of TLB faults due to permissions restrictions 1148system.cpu1.itb.read_accesses 0 # DTB read accesses 1149system.cpu1.itb.write_accesses 0 # DTB write accesses 1150system.cpu1.itb.inst_accesses 10454857 # ITB inst accesses 1151system.cpu1.itb.hits 10447082 # DTB hits 1152system.cpu1.itb.misses 7775 # DTB misses 1153system.cpu1.itb.accesses 10454857 # DTB accesses 1154system.cpu1.numCycles 361402922 # number of cpu cycles simulated 1155system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1156system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1157system.cpu1.BPredUnit.lookups 11186826 # Number of BP lookups 1158system.cpu1.BPredUnit.condPredicted 8978228 # Number of conditional branches predicted 1159system.cpu1.BPredUnit.condIncorrect 659649 # Number of conditional branches incorrect 1160system.cpu1.BPredUnit.BTBLookups 7702930 # Number of BTB lookups 1161system.cpu1.BPredUnit.BTBHits 6115228 # Number of BTB hits 1162system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1163system.cpu1.BPredUnit.usedRAS 914050 # Number of times the RAS was used to get a target. 1164system.cpu1.BPredUnit.RASInCorrect 143881 # Number of incorrect RAS predictions. 1165system.cpu1.fetch.icacheStallCycles 24238168 # Number of cycles fetch is stalled on an Icache miss 1166system.cpu1.fetch.Insts 79362685 # Number of instructions fetch has processed 1167system.cpu1.fetch.Branches 11186826 # Number of branches that fetch encountered 1168system.cpu1.fetch.predictedBranches 7029278 # Number of branches that fetch has predicted taken 1169system.cpu1.fetch.Cycles 17037334 # Number of cycles fetch has run and was not squashing or blocked 1170system.cpu1.fetch.SquashCycles 5514806 # Number of cycles fetch has spent squashing 1171system.cpu1.fetch.TlbCycles 104106 # Number of cycles fetch has spent waiting for tlb 1172system.cpu1.fetch.BlockedCycles 74528918 # Number of cycles fetch has spent blocked 1173system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1174system.cpu1.fetch.PendingTrapStallCycles 113982 # Number of stall cycles due to pending traps 1175system.cpu1.fetch.PendingQuiesceStallCycles 165536 # Number of stall cycles due to pending quiesce instructions 1176system.cpu1.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR 1177system.cpu1.fetch.CacheLines 10441784 # Number of cache lines fetched 1178system.cpu1.fetch.IcacheSquashes 854309 # Number of outstanding Icache misses that were squashed 1179system.cpu1.fetch.ItlbSquashes 4213 # Number of outstanding ITLB misses that were squashed 1180system.cpu1.fetch.rateDist::samples 119977470 # Number of instructions fetched each cycle (Total) 1181system.cpu1.fetch.rateDist::mean 0.807329 # Number of instructions fetched each cycle (Total) 1182system.cpu1.fetch.rateDist::stdev 2.185858 # Number of instructions fetched each cycle (Total) 1183system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1184system.cpu1.fetch.rateDist::0 102950411 85.81% 85.81% # Number of instructions fetched each cycle (Total) 1185system.cpu1.fetch.rateDist::1 1027065 0.86% 86.66% # Number of instructions fetched each cycle (Total) 1186system.cpu1.fetch.rateDist::2 1252290 1.04% 87.71% # Number of instructions fetched each cycle (Total) 1187system.cpu1.fetch.rateDist::3 2222542 1.85% 89.56% # Number of instructions fetched each cycle (Total) 1188system.cpu1.fetch.rateDist::4 1450508 1.21% 90.77% # Number of instructions fetched each cycle (Total) 1189system.cpu1.fetch.rateDist::5 763655 0.64% 91.41% # Number of instructions fetched each cycle (Total) 1190system.cpu1.fetch.rateDist::6 2450140 2.04% 93.45% # Number of instructions fetched each cycle (Total) 1191system.cpu1.fetch.rateDist::7 546027 0.46% 93.90% # Number of instructions fetched each cycle (Total) 1192system.cpu1.fetch.rateDist::8 7314832 6.10% 100.00% # Number of instructions fetched each cycle (Total) 1193system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1194system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1195system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1196system.cpu1.fetch.rateDist::total 119977470 # Number of instructions fetched each cycle (Total) 1197system.cpu1.fetch.branchRate 0.030954 # Number of branch fetches per cycle 1198system.cpu1.fetch.rate 0.219596 # Number of inst fetches per cycle 1199system.cpu1.decode.IdleCycles 25932861 # Number of cycles decode is idle 1200system.cpu1.decode.BlockedCycles 74439661 # Number of cycles decode is blocked 1201system.cpu1.decode.RunCycles 15341871 # Number of cycles decode is running 1202system.cpu1.decode.UnblockCycles 600655 # Number of cycles decode is unblocking 1203system.cpu1.decode.SquashCycles 3662422 # Number of cycles decode is squashing 1204system.cpu1.decode.BranchResolved 1558576 # Number of times decode resolved a branch 1205system.cpu1.decode.BranchMispred 123600 # Number of times decode detected a branch misprediction 1206system.cpu1.decode.DecodedInsts 90136794 # Number of instructions handled by decode 1207system.cpu1.decode.SquashedInsts 402223 # Number of squashed instructions handled by decode 1208system.cpu1.rename.SquashCycles 3662422 # Number of cycles rename is squashing 1209system.cpu1.rename.IdleCycles 27545183 # Number of cycles rename is idle 1210system.cpu1.rename.BlockCycles 32824542 # Number of cycles rename is blocking 1211system.cpu1.rename.serializeStallCycles 37049772 # count of cycles rename stalled for serializing inst 1212system.cpu1.rename.RunCycles 14316379 # Number of cycles rename is running 1213system.cpu1.rename.UnblockCycles 4579172 # Number of cycles rename is unblocking 1214system.cpu1.rename.RenamedInsts 83629464 # Number of instructions processed by rename 1215system.cpu1.rename.ROBFullEvents 2956 # Number of times rename has blocked due to ROB full 1216system.cpu1.rename.IQFullEvents 679775 # Number of times rename has blocked due to IQ full 1217system.cpu1.rename.LSQFullEvents 3317472 # Number of times rename has blocked due to LSQ full 1218system.cpu1.rename.FullRegisterEvents 46248 # Number of times there has been no free registers 1219system.cpu1.rename.RenamedOperands 88354418 # Number of destination operands rename has renamed 1220system.cpu1.rename.RenameLookups 386338466 # Number of register rename lookups that rename has made 1221system.cpu1.rename.int_rename_lookups 386288470 # Number of integer rename lookups 1222system.cpu1.rename.fp_rename_lookups 49996 # Number of floating rename lookups 1223system.cpu1.rename.CommittedMaps 54988347 # Number of HB maps that are committed 1224system.cpu1.rename.UndoneMaps 33366070 # Number of HB maps that are undone due to squashing 1225system.cpu1.rename.serializingInsts 602019 # count of serializing insts renamed 1226system.cpu1.rename.tempSerializingInsts 524737 # count of temporary serializing insts renamed 1227system.cpu1.rename.skidInsts 8626692 # count of insts added to the skid buffer 1228system.cpu1.memDep0.insertedLoads 16066963 # Number of loads inserted to the mem dependence unit. 1229system.cpu1.memDep0.insertedStores 9656417 # Number of stores inserted to the mem dependence unit. 1230system.cpu1.memDep0.conflictingLoads 1282659 # Number of conflicting loads. 1231system.cpu1.memDep0.conflictingStores 1811239 # Number of conflicting stores. 1232system.cpu1.iq.iqInstsAdded 75062782 # Number of instructions added to the IQ (excludes non-spec) 1233system.cpu1.iq.iqNonSpecInstsAdded 1031692 # Number of non-speculative instructions added to the IQ 1234system.cpu1.iq.iqInstsIssued 98462898 # Number of instructions issued 1235system.cpu1.iq.iqSquashedInstsIssued 155624 # Number of squashed instructions issued 1236system.cpu1.iq.iqSquashedInstsExamined 21632122 # Number of squashed instructions iterated over during squash; mainly for profiling 1237system.cpu1.iq.iqSquashedOperandsExamined 61142717 # Number of squashed operands that are examined and possibly removed from graph 1238system.cpu1.iq.iqSquashedNonSpecRemoved 223849 # Number of squashed non-spec instructions that were removed 1239system.cpu1.iq.issued_per_cycle::samples 119977470 # Number of insts issued each cycle 1240system.cpu1.iq.issued_per_cycle::mean 0.820678 # Number of insts issued each cycle 1241system.cpu1.iq.issued_per_cycle::stdev 1.544702 # Number of insts issued each cycle 1242system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1243system.cpu1.iq.issued_per_cycle::0 85994383 71.68% 71.68% # Number of insts issued each cycle 1244system.cpu1.iq.issued_per_cycle::1 9640016 8.03% 79.71% # Number of insts issued each cycle 1245system.cpu1.iq.issued_per_cycle::2 5133014 4.28% 83.99% # Number of insts issued each cycle 1246system.cpu1.iq.issued_per_cycle::3 4263453 3.55% 87.54% # Number of insts issued each cycle 1247system.cpu1.iq.issued_per_cycle::4 11149849 9.29% 96.84% # Number of insts issued each cycle 1248system.cpu1.iq.issued_per_cycle::5 2119505 1.77% 98.60% # Number of insts issued each cycle 1249system.cpu1.iq.issued_per_cycle::6 1269612 1.06% 99.66% # Number of insts issued each cycle 1250system.cpu1.iq.issued_per_cycle::7 309202 0.26% 99.92% # Number of insts issued each cycle 1251system.cpu1.iq.issued_per_cycle::8 98436 0.08% 100.00% # Number of insts issued each cycle 1252system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1253system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1254system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1255system.cpu1.iq.issued_per_cycle::total 119977470 # Number of insts issued each cycle 1256system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1257system.cpu1.iq.fu_full::IntAlu 44202 0.54% 0.54% # attempts to use FU when none available 1258system.cpu1.iq.fu_full::IntMult 979 0.01% 0.56% # attempts to use FU when none available 1259system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available 1260system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available 1261system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available 1262system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available 1263system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available 1264system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available 1265system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available 1266system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available 1267system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available 1268system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available 1269system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available 1270system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available 1271system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available 1272system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available 1273system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available 1274system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available 1275system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available 1276system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available 1277system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available 1278system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available 1279system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available 1280system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available 1281system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available 1282system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available 1283system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available 1284system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available 1285system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available 1286system.cpu1.iq.fu_full::MemRead 7732056 95.26% 95.82% # attempts to use FU when none available 1287system.cpu1.iq.fu_full::MemWrite 339451 4.18% 100.00% # attempts to use FU when none available 1288system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1289system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1290system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued 1291system.cpu1.iq.FU_type_0::IntAlu 43271411 43.95% 44.04% # Type of FU issued 1292system.cpu1.iq.FU_type_0::IntMult 69911 0.07% 44.11% # Type of FU issued 1293system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.11% # Type of FU issued 1294system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.11% # Type of FU issued 1295system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.11% # Type of FU issued 1296system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.11% # Type of FU issued 1297system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.11% # Type of FU issued 1298system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.11% # Type of FU issued 1299system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.11% # Type of FU issued 1300system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.11% # Type of FU issued 1301system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.11% # Type of FU issued 1302system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.11% # Type of FU issued 1303system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.11% # Type of FU issued 1304system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.11% # Type of FU issued 1305system.cpu1.iq.FU_type_0::SimdMisc 29 0.00% 44.11% # Type of FU issued 1306system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.11% # Type of FU issued 1307system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.11% # Type of FU issued 1308system.cpu1.iq.FU_type_0::SimdShift 39 0.00% 44.11% # Type of FU issued 1309system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 44.11% # Type of FU issued 1310system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.11% # Type of FU issued 1311system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.11% # Type of FU issued 1312system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.11% # Type of FU issued 1313system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.11% # Type of FU issued 1314system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.11% # Type of FU issued 1315system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.11% # Type of FU issued 1316system.cpu1.iq.FU_type_0::SimdFloatMisc 1782 0.00% 44.11% # Type of FU issued 1317system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.11% # Type of FU issued 1318system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 44.11% # Type of FU issued 1319system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.11% # Type of FU issued 1320system.cpu1.iq.FU_type_0::MemRead 46626317 47.35% 91.47% # Type of FU issued 1321system.cpu1.iq.FU_type_0::MemWrite 8400570 8.53% 100.00% # Type of FU issued 1322system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1323system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1324system.cpu1.iq.FU_type_0::total 98462898 # Type of FU issued 1325system.cpu1.iq.rate 0.272446 # Inst issue rate 1326system.cpu1.iq.fu_busy_cnt 8116688 # FU busy when requested 1327system.cpu1.iq.fu_busy_rate 0.082434 # FU busy rate (busy events/executed inst) 1328system.cpu1.iq.int_inst_queue_reads 325251459 # Number of integer instruction queue reads 1329system.cpu1.iq.int_inst_queue_writes 97743765 # Number of integer instruction queue writes 1330system.cpu1.iq.int_inst_queue_wakeup_accesses 61686980 # Number of integer instruction queue wakeup accesses 1331system.cpu1.iq.fp_inst_queue_reads 12182 # Number of floating instruction queue reads 1332system.cpu1.iq.fp_inst_queue_writes 6832 # Number of floating instruction queue writes 1333system.cpu1.iq.fp_inst_queue_wakeup_accesses 5554 # Number of floating instruction queue wakeup accesses 1334system.cpu1.iq.int_alu_accesses 106480420 # Number of integer alu accesses 1335system.cpu1.iq.fp_alu_accesses 6347 # Number of floating point alu accesses 1336system.cpu1.iew.lsq.thread0.forwLoads 431690 # Number of loads that had data forwarded from stores 1337system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1338system.cpu1.iew.lsq.thread0.squashedLoads 4883583 # Number of loads squashed 1339system.cpu1.iew.lsq.thread0.ignoredResponses 7497 # Number of memory responses ignored because the instruction is squashed 1340system.cpu1.iew.lsq.thread0.memOrderViolation 24780 # Number of memory ordering violations 1341system.cpu1.iew.lsq.thread0.squashedStores 1835710 # Number of stores squashed 1342system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1343system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1344system.cpu1.iew.lsq.thread0.rescheduledLoads 32214526 # Number of loads that were rescheduled 1345system.cpu1.iew.lsq.thread0.cacheBlocked 1149867 # Number of times an access to memory failed due to the cache being blocked 1346system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1347system.cpu1.iew.iewSquashCycles 3662422 # Number of cycles IEW is squashing 1348system.cpu1.iew.iewBlockCycles 25277331 # Number of cycles IEW is blocking 1349system.cpu1.iew.iewUnblockCycles 367624 # Number of cycles IEW is unblocking 1350system.cpu1.iew.iewDispatchedInsts 76304263 # Number of instructions dispatched to IQ 1351system.cpu1.iew.iewDispSquashedInsts 229674 # Number of squashed instructions skipped by dispatch 1352system.cpu1.iew.iewDispLoadInsts 16066963 # Number of dispatched load instructions 1353system.cpu1.iew.iewDispStoreInsts 9656417 # Number of dispatched store instructions 1354system.cpu1.iew.iewDispNonSpecInsts 636963 # Number of dispatched non-speculative instructions 1355system.cpu1.iew.iewIQFullEvents 63488 # Number of times the IQ has become full, causing a stall 1356system.cpu1.iew.iewLSQFullEvents 8504 # Number of times the LSQ has become full, causing a stall 1357system.cpu1.iew.memOrderViolationEvents 24780 # Number of memory order violations 1358system.cpu1.iew.predictedTakenIncorrect 400468 # Number of branches that were predicted taken incorrectly 1359system.cpu1.iew.predictedNotTakenIncorrect 244624 # Number of branches that were predicted not taken incorrectly 1360system.cpu1.iew.branchMispredicts 645092 # Number of branch mispredicts detected at execute 1361system.cpu1.iew.iewExecutedInsts 95561838 # Number of executed instructions 1362system.cpu1.iew.iewExecLoadInsts 45782046 # Number of load instructions executed 1363system.cpu1.iew.iewExecSquashedInsts 2901060 # Number of squashed instructions skipped in execute 1364system.cpu1.iew.exec_swp 0 # number of swp insts executed 1365system.cpu1.iew.exec_nop 209789 # number of nop insts executed 1366system.cpu1.iew.exec_refs 54078244 # number of memory reference insts executed 1367system.cpu1.iew.exec_branches 8068913 # Number of branches executed 1368system.cpu1.iew.exec_stores 8296198 # Number of stores executed 1369system.cpu1.iew.exec_rate 0.264419 # Inst execution rate 1370system.cpu1.iew.wb_sent 94191755 # cumulative count of insts sent to commit 1371system.cpu1.iew.wb_count 61692534 # cumulative count of insts written-back 1372system.cpu1.iew.wb_producers 33977338 # num instructions producing a value 1373system.cpu1.iew.wb_consumers 61891561 # num instructions consuming a value 1374system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1375system.cpu1.iew.wb_rate 0.170703 # insts written-back per cycle 1376system.cpu1.iew.wb_fanout 0.548982 # average fanout of values written-back 1377system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1378system.cpu1.commit.commitCommittedInsts 42383808 # The number of committed instructions 1379system.cpu1.commit.commitCommittedOps 53979911 # The number of committed instructions 1380system.cpu1.commit.commitSquashedInsts 22261112 # The number of squashed insts skipped by commit 1381system.cpu1.commit.commitNonSpecStalls 807843 # The number of times commit has been forced to stall to communicate backwards 1382system.cpu1.commit.branchMispredicts 569017 # The number of times a branch was mispredicted 1383system.cpu1.commit.committed_per_cycle::samples 116371049 # Number of insts commited each cycle 1384system.cpu1.commit.committed_per_cycle::mean 0.463860 # Number of insts commited each cycle 1385system.cpu1.commit.committed_per_cycle::stdev 1.434767 # Number of insts commited each cycle 1386system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1387system.cpu1.commit.committed_per_cycle::0 97273421 83.59% 83.59% # Number of insts commited each cycle 1388system.cpu1.commit.committed_per_cycle::1 9394437 8.07% 91.66% # Number of insts commited each cycle 1389system.cpu1.commit.committed_per_cycle::2 2575050 2.21% 93.87% # Number of insts commited each cycle 1390system.cpu1.commit.committed_per_cycle::3 1580988 1.36% 95.23% # Number of insts commited each cycle 1391system.cpu1.commit.committed_per_cycle::4 1207821 1.04% 96.27% # Number of insts commited each cycle 1392system.cpu1.commit.committed_per_cycle::5 698590 0.60% 96.87% # Number of insts commited each cycle 1393system.cpu1.commit.committed_per_cycle::6 1120414 0.96% 97.83% # Number of insts commited each cycle 1394system.cpu1.commit.committed_per_cycle::7 516932 0.44% 98.28% # Number of insts commited each cycle 1395system.cpu1.commit.committed_per_cycle::8 2003396 1.72% 100.00% # Number of insts commited each cycle 1396system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1397system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1398system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1399system.cpu1.commit.committed_per_cycle::total 116371049 # Number of insts commited each cycle 1400system.cpu1.commit.committedInsts 42383808 # Number of instructions committed 1401system.cpu1.commit.committedOps 53979911 # Number of ops (including micro ops) committed 1402system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1403system.cpu1.commit.refs 19004087 # Number of memory references committed 1404system.cpu1.commit.loads 11183380 # Number of loads committed 1405system.cpu1.commit.membars 242516 # Number of memory barriers committed 1406system.cpu1.commit.branches 6784179 # Number of branches committed 1407system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. 1408system.cpu1.commit.int_insts 48067133 # Number of committed integer instructions. 1409system.cpu1.commit.function_calls 633379 # Number of function calls committed. 1410system.cpu1.commit.bw_lim_events 2003396 # number cycles where commit BW limit reached 1411system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1412system.cpu1.rob.rob_reads 189385035 # The number of ROB reads 1413system.cpu1.rob.rob_writes 156267900 # The number of ROB writes 1414system.cpu1.timesIdled 1564769 # Number of times that the entire CPU went into an idle state and unscheduled itself 1415system.cpu1.idleCycles 241425452 # Total number of cycles that the CPU has spent unscheduled due to idling 1416system.cpu1.quiesceCycles 4780203327 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1417system.cpu1.committedInsts 42257981 # Number of Instructions Simulated 1418system.cpu1.committedOps 53854084 # Number of Ops (including micro ops) Simulated 1419system.cpu1.committedInsts_total 42257981 # Number of Instructions Simulated 1420system.cpu1.cpi 8.552300 # CPI: Cycles Per Instruction 1421system.cpu1.cpi_total 8.552300 # CPI: Total CPI of All Threads 1422system.cpu1.ipc 0.116928 # IPC: Instructions Per Cycle 1423system.cpu1.ipc_total 0.116928 # IPC: Total IPC of All Threads 1424system.cpu1.int_regfile_reads 430079753 # number of integer regfile reads 1425system.cpu1.int_regfile_writes 64515100 # number of integer regfile writes 1426system.cpu1.fp_regfile_reads 4419 # number of floating regfile reads 1427system.cpu1.fp_regfile_writes 2066 # number of floating regfile writes 1428system.cpu1.misc_regfile_reads 102262967 # number of misc regfile reads 1429system.cpu1.misc_regfile_writes 513108 # number of misc regfile writes 1430system.cpu1.icache.replacements 714529 # number of replacements 1431system.cpu1.icache.tagsinuse 498.761723 # Cycle average of tags in use 1432system.cpu1.icache.total_refs 9665211 # Total number of references to valid blocks. 1433system.cpu1.icache.sampled_refs 715041 # Sample count of references to valid blocks. 1434system.cpu1.icache.avg_refs 13.517003 # Average number of references to valid blocks. 1435system.cpu1.icache.warmup_cycle 74296656000 # Cycle when the warmup percentage was hit. 1436system.cpu1.icache.occ_blocks::cpu1.inst 498.761723 # Average occupied blocks per requestor 1437system.cpu1.icache.occ_percent::cpu1.inst 0.974144 # Average percentage of cache occupancy 1438system.cpu1.icache.occ_percent::total 0.974144 # Average percentage of cache occupancy 1439system.cpu1.icache.ReadReq_hits::cpu1.inst 9665211 # number of ReadReq hits 1440system.cpu1.icache.ReadReq_hits::total 9665211 # number of ReadReq hits 1441system.cpu1.icache.demand_hits::cpu1.inst 9665211 # number of demand (read+write) hits 1442system.cpu1.icache.demand_hits::total 9665211 # number of demand (read+write) hits 1443system.cpu1.icache.overall_hits::cpu1.inst 9665211 # number of overall hits 1444system.cpu1.icache.overall_hits::total 9665211 # number of overall hits 1445system.cpu1.icache.ReadReq_misses::cpu1.inst 776521 # number of ReadReq misses 1446system.cpu1.icache.ReadReq_misses::total 776521 # number of ReadReq misses 1447system.cpu1.icache.demand_misses::cpu1.inst 776521 # number of demand (read+write) misses 1448system.cpu1.icache.demand_misses::total 776521 # number of demand (read+write) misses 1449system.cpu1.icache.overall_misses::cpu1.inst 776521 # number of overall misses 1450system.cpu1.icache.overall_misses::total 776521 # number of overall misses 1451system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11390030990 # number of ReadReq miss cycles 1452system.cpu1.icache.ReadReq_miss_latency::total 11390030990 # number of ReadReq miss cycles 1453system.cpu1.icache.demand_miss_latency::cpu1.inst 11390030990 # number of demand (read+write) miss cycles 1454system.cpu1.icache.demand_miss_latency::total 11390030990 # number of demand (read+write) miss cycles 1455system.cpu1.icache.overall_miss_latency::cpu1.inst 11390030990 # number of overall miss cycles 1456system.cpu1.icache.overall_miss_latency::total 11390030990 # number of overall miss cycles 1457system.cpu1.icache.ReadReq_accesses::cpu1.inst 10441732 # number of ReadReq accesses(hits+misses) 1458system.cpu1.icache.ReadReq_accesses::total 10441732 # number of ReadReq accesses(hits+misses) 1459system.cpu1.icache.demand_accesses::cpu1.inst 10441732 # number of demand (read+write) accesses 1460system.cpu1.icache.demand_accesses::total 10441732 # number of demand (read+write) accesses 1461system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses 1462system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses 1463system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses 1464system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses 1465system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses 1466system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses 1467system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses 1468system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses 1469system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency 1470system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency 1471system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency 1472system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency 1473system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency 1474system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency 1475system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked 1476system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1477system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked 1478system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1479system.cpu1.icache.avg_blocked_cycles::no_mshrs 6609.210084 # average number of cycles each access was blocked 1480system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1481system.cpu1.icache.fast_writes 0 # number of fast writes performed 1482system.cpu1.icache.cache_copies 0 # number of cache copies performed 1483system.cpu1.icache.writebacks::writebacks 32858 # number of writebacks 1484system.cpu1.icache.writebacks::total 32858 # number of writebacks 1485system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 61445 # number of ReadReq MSHR hits 1486system.cpu1.icache.ReadReq_mshr_hits::total 61445 # number of ReadReq MSHR hits 1487system.cpu1.icache.demand_mshr_hits::cpu1.inst 61445 # number of demand (read+write) MSHR hits 1488system.cpu1.icache.demand_mshr_hits::total 61445 # number of demand (read+write) MSHR hits 1489system.cpu1.icache.overall_mshr_hits::cpu1.inst 61445 # number of overall MSHR hits 1490system.cpu1.icache.overall_mshr_hits::total 61445 # number of overall MSHR hits 1491system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 715076 # number of ReadReq MSHR misses 1492system.cpu1.icache.ReadReq_mshr_misses::total 715076 # number of ReadReq MSHR misses 1493system.cpu1.icache.demand_mshr_misses::cpu1.inst 715076 # number of demand (read+write) MSHR misses 1494system.cpu1.icache.demand_mshr_misses::total 715076 # number of demand (read+write) MSHR misses 1495system.cpu1.icache.overall_mshr_misses::cpu1.inst 715076 # number of overall MSHR misses 1496system.cpu1.icache.overall_mshr_misses::total 715076 # number of overall MSHR misses 1497system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8506439492 # number of ReadReq MSHR miss cycles 1498system.cpu1.icache.ReadReq_mshr_miss_latency::total 8506439492 # number of ReadReq MSHR miss cycles 1499system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8506439492 # number of demand (read+write) MSHR miss cycles 1500system.cpu1.icache.demand_mshr_miss_latency::total 8506439492 # number of demand (read+write) MSHR miss cycles 1501system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8506439492 # number of overall MSHR miss cycles 1502system.cpu1.icache.overall_mshr_miss_latency::total 8506439492 # number of overall MSHR miss cycles 1503system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles 1504system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles 1505system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles 1506system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles 1507system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses 1508system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses 1509system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses 1510system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses 1511system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses 1512system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses 1513system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency 1514system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency 1515system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency 1516system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency 1517system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency 1518system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency 1519system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1520system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1521system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1522system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1523system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1524system.cpu1.dcache.replacements 417022 # number of replacements 1525system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use 1526system.cpu1.dcache.total_refs 15242379 # Total number of references to valid blocks. 1527system.cpu1.dcache.sampled_refs 417534 # Sample count of references to valid blocks. 1528system.cpu1.dcache.avg_refs 36.505719 # Average number of references to valid blocks. 1529system.cpu1.dcache.warmup_cycle 72565634000 # Cycle when the warmup percentage was hit. 1530system.cpu1.dcache.occ_blocks::cpu1.data 464.475329 # Average occupied blocks per requestor 1531system.cpu1.dcache.occ_percent::cpu1.data 0.907178 # Average percentage of cache occupancy 1532system.cpu1.dcache.occ_percent::total 0.907178 # Average percentage of cache occupancy 1533system.cpu1.dcache.ReadReq_hits::cpu1.data 10057492 # number of ReadReq hits 1534system.cpu1.dcache.ReadReq_hits::total 10057492 # number of ReadReq hits 1535system.cpu1.dcache.WriteReq_hits::cpu1.data 4888994 # number of WriteReq hits 1536system.cpu1.dcache.WriteReq_hits::total 4888994 # number of WriteReq hits 1537system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 126446 # number of LoadLockedReq hits 1538system.cpu1.dcache.LoadLockedReq_hits::total 126446 # number of LoadLockedReq hits 1539system.cpu1.dcache.StoreCondReq_hits::cpu1.data 120021 # number of StoreCondReq hits 1540system.cpu1.dcache.StoreCondReq_hits::total 120021 # number of StoreCondReq hits 1541system.cpu1.dcache.demand_hits::cpu1.data 14946486 # number of demand (read+write) hits 1542system.cpu1.dcache.demand_hits::total 14946486 # number of demand (read+write) hits 1543system.cpu1.dcache.overall_hits::cpu1.data 14946486 # number of overall hits 1544system.cpu1.dcache.overall_hits::total 14946486 # number of overall hits 1545system.cpu1.dcache.ReadReq_misses::cpu1.data 473003 # number of ReadReq misses 1546system.cpu1.dcache.ReadReq_misses::total 473003 # number of ReadReq misses 1547system.cpu1.dcache.WriteReq_misses::cpu1.data 1726377 # number of WriteReq misses 1548system.cpu1.dcache.WriteReq_misses::total 1726377 # number of WriteReq misses 1549system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14767 # number of LoadLockedReq misses 1550system.cpu1.dcache.LoadLockedReq_misses::total 14767 # number of LoadLockedReq misses 1551system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10580 # number of StoreCondReq misses 1552system.cpu1.dcache.StoreCondReq_misses::total 10580 # number of StoreCondReq misses 1553system.cpu1.dcache.demand_misses::cpu1.data 2199380 # number of demand (read+write) misses 1554system.cpu1.dcache.demand_misses::total 2199380 # number of demand (read+write) misses 1555system.cpu1.dcache.overall_misses::cpu1.data 2199380 # number of overall misses 1556system.cpu1.dcache.overall_misses::total 2199380 # number of overall misses 1557system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7143574500 # number of ReadReq miss cycles 1558system.cpu1.dcache.ReadReq_miss_latency::total 7143574500 # number of ReadReq miss cycles 1559system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 57173185397 # number of WriteReq miss cycles 1560system.cpu1.dcache.WriteReq_miss_latency::total 57173185397 # number of WriteReq miss cycles 1561system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 177446500 # number of LoadLockedReq miss cycles 1562system.cpu1.dcache.LoadLockedReq_miss_latency::total 177446500 # number of LoadLockedReq miss cycles 1563system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 91928500 # number of StoreCondReq miss cycles 1564system.cpu1.dcache.StoreCondReq_miss_latency::total 91928500 # number of StoreCondReq miss cycles 1565system.cpu1.dcache.demand_miss_latency::cpu1.data 64316759897 # number of demand (read+write) miss cycles 1566system.cpu1.dcache.demand_miss_latency::total 64316759897 # number of demand (read+write) miss cycles 1567system.cpu1.dcache.overall_miss_latency::cpu1.data 64316759897 # number of overall miss cycles 1568system.cpu1.dcache.overall_miss_latency::total 64316759897 # number of overall miss cycles 1569system.cpu1.dcache.ReadReq_accesses::cpu1.data 10530495 # number of ReadReq accesses(hits+misses) 1570system.cpu1.dcache.ReadReq_accesses::total 10530495 # number of ReadReq accesses(hits+misses) 1571system.cpu1.dcache.WriteReq_accesses::cpu1.data 6615371 # number of WriteReq accesses(hits+misses) 1572system.cpu1.dcache.WriteReq_accesses::total 6615371 # number of WriteReq accesses(hits+misses) 1573system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 141213 # number of LoadLockedReq accesses(hits+misses) 1574system.cpu1.dcache.LoadLockedReq_accesses::total 141213 # number of LoadLockedReq accesses(hits+misses) 1575system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130601 # number of StoreCondReq accesses(hits+misses) 1576system.cpu1.dcache.StoreCondReq_accesses::total 130601 # number of StoreCondReq accesses(hits+misses) 1577system.cpu1.dcache.demand_accesses::cpu1.data 17145866 # number of demand (read+write) accesses 1578system.cpu1.dcache.demand_accesses::total 17145866 # number of demand (read+write) accesses 1579system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses 1580system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses 1581system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses 1582system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses 1583system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses 1584system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses 1585system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses 1586system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses 1587system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses 1588system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses 1589system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses 1590system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses 1591system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses 1592system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses 1593system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency 1594system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency 1595system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency 1596system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency 1597system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency 1598system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency 1599system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency 1600system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency 1601system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency 1602system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency 1603system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency 1604system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency 1605system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked 1606system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked 1607system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked 1608system.cpu1.dcache.blocked::no_targets 149 # number of cycles access was blocked 1609system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4702.128642 # average number of cycles each access was blocked 1610system.cpu1.dcache.avg_blocked_cycles::no_targets 35590.604027 # average number of cycles each access was blocked 1611system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1612system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1613system.cpu1.dcache.writebacks::writebacks 346093 # number of writebacks 1614system.cpu1.dcache.writebacks::total 346093 # number of writebacks 1615system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 202550 # number of ReadReq MSHR hits 1616system.cpu1.dcache.ReadReq_mshr_hits::total 202550 # number of ReadReq MSHR hits 1617system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1548902 # number of WriteReq MSHR hits 1618system.cpu1.dcache.WriteReq_mshr_hits::total 1548902 # number of WriteReq MSHR hits 1619system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1254 # number of LoadLockedReq MSHR hits 1620system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1254 # number of LoadLockedReq MSHR hits 1621system.cpu1.dcache.demand_mshr_hits::cpu1.data 1751452 # number of demand (read+write) MSHR hits 1622system.cpu1.dcache.demand_mshr_hits::total 1751452 # number of demand (read+write) MSHR hits 1623system.cpu1.dcache.overall_mshr_hits::cpu1.data 1751452 # number of overall MSHR hits 1624system.cpu1.dcache.overall_mshr_hits::total 1751452 # number of overall MSHR hits 1625system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270453 # number of ReadReq MSHR misses 1626system.cpu1.dcache.ReadReq_mshr_misses::total 270453 # number of ReadReq MSHR misses 1627system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177475 # number of WriteReq MSHR misses 1628system.cpu1.dcache.WriteReq_mshr_misses::total 177475 # number of WriteReq MSHR misses 1629system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13513 # number of LoadLockedReq MSHR misses 1630system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13513 # number of LoadLockedReq MSHR misses 1631system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10575 # number of StoreCondReq MSHR misses 1632system.cpu1.dcache.StoreCondReq_mshr_misses::total 10575 # number of StoreCondReq MSHR misses 1633system.cpu1.dcache.demand_mshr_misses::cpu1.data 447928 # number of demand (read+write) MSHR misses 1634system.cpu1.dcache.demand_mshr_misses::total 447928 # number of demand (read+write) MSHR misses 1635system.cpu1.dcache.overall_mshr_misses::cpu1.data 447928 # number of overall MSHR misses 1636system.cpu1.dcache.overall_mshr_misses::total 447928 # number of overall MSHR misses 1637system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3409672000 # number of ReadReq MSHR miss cycles 1638system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3409672000 # number of ReadReq MSHR miss cycles 1639system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5551338067 # number of WriteReq MSHR miss cycles 1640system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5551338067 # number of WriteReq MSHR miss cycles 1641system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 121446000 # number of LoadLockedReq MSHR miss cycles 1642system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 121446000 # number of LoadLockedReq MSHR miss cycles 1643system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60146500 # number of StoreCondReq MSHR miss cycles 1644system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60146500 # number of StoreCondReq MSHR miss cycles 1645system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1646system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1647system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8961010067 # number of demand (read+write) MSHR miss cycles 1648system.cpu1.dcache.demand_mshr_miss_latency::total 8961010067 # number of demand (read+write) MSHR miss cycles 1649system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8961010067 # number of overall MSHR miss cycles 1650system.cpu1.dcache.overall_mshr_miss_latency::total 8961010067 # number of overall MSHR miss cycles 1651system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000 # number of ReadReq MSHR uncacheable cycles 1652system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000 # number of ReadReq MSHR uncacheable cycles 1653system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41662340533 # number of WriteReq MSHR uncacheable cycles 1654system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 # number of WriteReq MSHR uncacheable cycles 1655system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles 1656system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles 1657system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses 1658system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses 1659system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses 1660system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses 1661system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses 1662system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses 1663system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses 1664system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses 1665system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses 1666system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses 1667system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses 1668system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses 1669system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency 1670system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency 1671system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency 1672system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency 1673system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency 1674system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency 1675system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency 1676system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency 1677system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1678system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1679system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency 1680system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency 1681system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency 1682system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency 1683system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1684system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1685system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1686system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1687system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1688system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1689system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1690system.iocache.replacements 0 # number of replacements 1691system.iocache.tagsinuse 0 # Cycle average of tags in use 1692system.iocache.total_refs 0 # Total number of references to valid blocks. 1693system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1694system.iocache.avg_refs nan # Average number of references to valid blocks. 1695system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1696system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1697system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1698system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1699system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1700system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1701system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1702system.iocache.fast_writes 0 # number of fast writes performed 1703system.iocache.cache_copies 0 # number of cache copies performed 1704system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of ReadReq MSHR uncacheable cycles 1705system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 # number of ReadReq MSHR uncacheable cycles 1706system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles 1707system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles 1708system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1709system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1710system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1711system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1712system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1713system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1714system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed 1715system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1716system.cpu1.kern.inst.quiesce 61621 # number of quiesce instructions executed 1717 1718---------- End Simulation Statistics ---------- 1719