linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.570834                       # Number of seconds simulated
sim_ticks                                2570833934500                       # Number of ticks simulated
final_tick                               2570833934500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  63716                       # Simulator instruction rate (inst/s)
host_op_rate                                    82290                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2641493756                       # Simulator tick rate (ticks/s)
host_mem_usage                                 388068                       # Number of bytes of host memory used
host_seconds                                   973.25                       # Real time elapsed on the host
sim_insts                                    62012062                       # Number of instructions simulated
sim_ops                                      80088895                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                   131429540                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                1199424                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                 10175696                       # Number of bytes written to this memory
system.physmem.num_reads                     15128117                       # Number of read requests responded to by this memory
system.physmem.num_writes                      868949                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       51123310                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    466551                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                       3958130                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                      55081440                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read                  384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read             384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
system.realview.nvmem.num_reads                     6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
system.realview.nvmem.bw_read                     149                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read                149                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total                    149                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        130926                       # number of replacements
system.l2c.tagsinuse                     27576.629960                       # Cycle average of tags in use
system.l2c.total_refs                         1855308                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        161029                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         11.521577                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        15187.159331                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker      17.600608                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.006762                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          2177.920948                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          1032.752170                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker      22.717912                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker       0.014158                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          4068.026765                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          5070.431306                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.231738                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000269                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.033232                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.015759                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000347                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.062073                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.077369                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.420786                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker        51294                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         5750                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             335682                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             133493                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       112013                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7283                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             702787                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             231603                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1579905                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          606768                       # number of Writeback hits
system.l2c.Writeback_hits::total               606768                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             925                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1139                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2064                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           217                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           388                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               605                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            35350                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            66066                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               101416                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         51294                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5750                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              335682                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              168843                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        112013                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7283                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              702787                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              297669                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1681321                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        51294                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5750                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             335682                       # number of overall hits
system.l2c.overall_hits::cpu0.data             168843                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       112013                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7283                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             702787                       # number of overall hits
system.l2c.overall_hits::cpu1.data             297669                       # number of overall hits
system.l2c.overall_hits::total                1681321                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           84                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             8376                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             8805                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           61                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            10197                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            12824                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                40353                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          5201                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          5819                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11020                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          788                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          600                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1388                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          65908                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          81633                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             147541                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           84                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              8376                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             74713                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           61                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10197                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             94457                       # number of demand (read+write) misses
system.l2c.demand_misses::total                187894                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           84                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             8376                       # number of overall misses
system.l2c.overall_misses::cpu0.data            74713                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           61                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10197                       # number of overall misses
system.l2c.overall_misses::cpu1.data            94457                       # number of overall misses
system.l2c.overall_misses::total               187894                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      4383500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       261000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    438009000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    459487500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      3183500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        52000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    533470500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    669975500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2108822500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     18089500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     38874000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     56963500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2245500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      5381000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      7626500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3455909999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4284020000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7739929999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      4383500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       261000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    438009000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3915397499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker      3183500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        52000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    533470500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4953995500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      9848752499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      4383500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       261000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    438009000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3915397499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker      3183500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        52000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    533470500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4953995500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     9848752499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        51378                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         5755                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         344058                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         142298                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       112074                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7284                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         712984                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         244427                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1620258                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       606768                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           606768                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6126                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         6958                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           13084                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         1005                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          988                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1993                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       101258                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       147699                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           248957                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        51378                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5755                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          344058                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          243556                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       112074                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7284                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          712984                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          392126                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1869215                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        51378                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5755                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         344058                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         243556                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       112074                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7284                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         712984                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         392126                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1869215                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001635                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000869                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.024345                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.061877                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000544                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000137                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.014302                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.052466                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.849004                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.836304                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.784080                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.607287                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.650892                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.552698                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001635                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000869                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.024345                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.306759                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000544                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000137                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.014302                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.240884                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001635                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000869                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.024345                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.306759                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000544                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000137                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.014302                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.240884                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        52200                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.838160                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3478.081138                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6680.529301                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2849.619289                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  8968.333333                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        52200                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52405.839666                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        52200                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52405.839666                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              111665                       # number of writebacks
system.l2c.writebacks::total                   111665                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            47                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            12                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            34                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                96                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             47                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             34                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 96                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            47                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            34                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                96                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           84                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            5                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         8373                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         8758                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           61                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        10185                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        12790                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           40257                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         5201                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         5819                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11020                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          788                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          600                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1388                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        65908                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        81633                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        147541                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           84                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         8373                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        74666                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           61                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10185                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        94423                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           187798                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           84                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         8373                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        74666                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           61                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10185                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        94423                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          187798                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3364000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       201000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    335581500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    350822000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      2444000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    408650000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    512397000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1613499500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    208363000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    232936000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    441299000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31554000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     24037000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     55591000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2638527499                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3273235000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5911762499                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      3364000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       201000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    335581500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2989349499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      2444000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        40000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    408650000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3785632000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   7525261999                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      3364000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       201000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    335581500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2989349499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      2444000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        40000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    408650000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3785632000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   7525261999                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5668500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   8235934000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      1931000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123713083500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131956617000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    706976980                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  31815648332                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  32522625312                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5668500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8942910980                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      1931000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155528731832                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 164479242312                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001635                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000869                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.024336                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.061547                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000544                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000137                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014285                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.052326                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.849004                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.836304                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.784080                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.607287                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.650892                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.552698                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001635                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000869                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.024336                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.306566                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000544                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000137                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014285                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.240798                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001635                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000869                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.024336                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.306566                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000544                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000137                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014285                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.240798                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40200                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40057.319023                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40200                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.288257                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40200                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.288257                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     7530160                       # DTB read hits
system.cpu0.dtb.read_misses                     32787                       # DTB read misses
system.cpu0.dtb.write_hits                    4446652                       # DTB write hits
system.cpu0.dtb.write_misses                     6213                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2035                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     4401                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   226                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      789                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 7562947                       # DTB read accesses
system.cpu0.dtb.write_accesses                4452865                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         11976812                       # DTB hits
system.cpu0.dtb.misses                          39000                       # DTB misses
system.cpu0.dtb.accesses                     12015812                       # DTB accesses
system.cpu0.itb.inst_hits                     3834120                       # ITB inst hits
system.cpu0.itb.inst_misses                      4594                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1377                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1800                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 3838714                       # ITB inst accesses
system.cpu0.itb.hits                          3834120                       # DTB hits
system.cpu0.itb.misses                           4594                       # DTB misses
system.cpu0.itb.accesses                      3838714                       # DTB accesses
system.cpu0.numCycles                        55537360                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                 5204671                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           3944570                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            296840                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              3413720                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 2557176                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  459948                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              62294                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          10542481                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      27454720                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    5204671                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           3017124                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      6462624                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1388283                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     64249                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              17511747                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                6585                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles        32170                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles        74952                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          276                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  3831976                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               163321                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3020                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          35682594                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.003010                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.394306                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                29226357     81.91%     81.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  522599      1.46%     83.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  706764      1.98%     85.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  578503      1.62%     86.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  534782      1.50%     88.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  477839      1.34%     89.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  574033      1.61%     91.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  347894      0.97%     92.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 2713823      7.61%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            35682594                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.093715                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.494347                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                10901751                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             17564449                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  5807943                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               476099                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                932352                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              836954                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                56324                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              34505102                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               181228                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles                932352                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                11416627                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                4596309                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      11321409                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  5748941                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              1666956                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              33335658                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                  999                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                358087                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents               883877                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             110                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           33439844                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            151572898                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       151532196                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            40702                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             25794881                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 7644963                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            390853                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        354451                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  4284069                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             6465672                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            4994701                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads           841470                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          890235                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  31482040                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded             658671                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 31606585                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            78774                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        5676384                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     13082280                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        117406                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     35682594                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.885770                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.514582                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           22866556     64.08%     64.08% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            4972769     13.94%     78.02% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            2602679      7.29%     85.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            1960706      5.49%     90.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            1807368      5.07%     95.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             768762      2.15%     98.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             499053      1.40%     99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             158868      0.45%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              45833      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       35682594                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  26479      2.83%      2.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   454      0.05%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.88% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                724595     77.49%     80.37% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               183504     19.63%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            14281      0.05%      0.05% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             18849345     59.64%     59.68% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               42325      0.13%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  8      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 8      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              3      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc           650      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     59.82% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             7946092     25.14%     84.96% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            4753870     15.04%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              31606585                       # Type of FU issued
system.cpu0.iq.rate                          0.569105                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     935032                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.029583                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads          99937037                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         37821084                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     28987180                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              10596                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              5532                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         4395                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              32521589                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   5747                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          248744                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1245744                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3732                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        10021                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       530307                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      1901421                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         5034                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                932352                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                3503280                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                78441                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           32200235                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           121893                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              6465672                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             4994701                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            398658                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 37609                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 4704                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         10021                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        177778                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       116282                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              294060                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             31219910                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              7794602                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           386675                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        59524                       # number of nop insts executed
system.cpu0.iew.exec_refs                    12495671                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 4074655                       # Number of branches executed
system.cpu0.iew.exec_stores                   4701069                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.562142                       # Inst execution rate
system.cpu0.iew.wb_sent                      31018630                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     28991575                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 15563441                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 30561631                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.522019                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.509248                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      19778635                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps        26259365                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts        5789320                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         541265                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           257580                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     34779040                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.755034                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.721723                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     24914736     71.64%     71.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      4928764     14.17%     85.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1604217      4.61%     90.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       793137      2.28%     92.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       618967      1.78%     94.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       369015      1.06%     95.54% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       397376      1.14%     96.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       185067      0.53%     97.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8       967761      2.78%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     34779040                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            19778635                       # Number of instructions committed
system.cpu0.commit.committedOps              26259365                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                       9684322                       # Number of memory references committed
system.cpu0.commit.loads                      5219928                       # Number of loads committed
system.cpu0.commit.membars                     194188                       # Number of memory barriers committed
system.cpu0.commit.branches                   3591028                       # Number of branches committed
system.cpu0.commit.fp_insts                      4336                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 23338580                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              422336                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events               967761                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                    65245448                       # The number of ROB reads
system.cpu0.rob.rob_writes                   65031517                       # The number of ROB writes
system.cpu0.timesIdled                         363170                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       19854766                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5085481268                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   19754081                       # Number of Instructions Simulated
system.cpu0.committedOps                     26234811                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             19754081                       # Number of Instructions Simulated
system.cpu0.cpi                              2.811437                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.811437                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.355690                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.355690                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               145547438                       # number of integer regfile reads
system.cpu0.int_regfile_writes               28450023                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     4554                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                     434                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               38991088                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                443778                       # number of misc regfile writes
system.cpu0.icache.replacements                345092                       # number of replacements
system.cpu0.icache.tagsinuse               511.631515                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 3456613                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                345604                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 10.001658                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle            6336390000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   511.631515                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.999280                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.999280                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      3456613                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        3456613                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      3456613                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         3456613                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      3456613                       # number of overall hits
system.cpu0.icache.overall_hits::total        3456613                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       375216                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       375216                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       375216                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        375216                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       375216                       # number of overall misses
system.cpu0.icache.overall_misses::total       375216                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5700257984                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5700257984                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5700257984                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5700257984                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5700257984                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5700257984                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      3831829                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      3831829                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      3831829                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      3831829                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      3831829                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      3831829                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.097921                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.097921                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.097921                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1854487                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              217                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs  8546.023041                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks        19422                       # number of writebacks
system.cpu0.icache.writebacks::total            19422                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        29600                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        29600                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        29600                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        29600                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        29600                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        29600                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       345616                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       345616                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       345616                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       345616                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       345616                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       345616                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4268453987                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4268453987                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4268453987                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4268453987                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4268453987                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4268453987                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7615500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7615500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7615500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      7615500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090196                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090196                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090196                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                232498                       # number of replacements
system.cpu0.dcache.tagsinuse               430.308093                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 7750511                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                232862                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 33.283709                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              49672000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   430.308093                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.840445                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.840445                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      4805960                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        4805960                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      2599019                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       2599019                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       154744                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       154744                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       152410                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       152410                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      7404979                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         7404979                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      7404979                       # number of overall hits
system.cpu0.dcache.overall_hits::total        7404979                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       332693                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       332693                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1446995                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1446995                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8853                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         8853                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7938                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7938                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1779688                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1779688                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1779688                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1779688                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4680931500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4680931500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  59628860399                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  59628860399                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     99729000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     99729000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     85543000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     85543000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  64309791899                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  64309791899                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  64309791899                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  64309791899                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5138653                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      5138653                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      4046014                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      4046014                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       163597                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       163597                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       160348                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       160348                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      9184667                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total      9184667                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      9184667                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total      9184667                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.064743                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.357635                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054115                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.049505                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.193767                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.193767                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      3548990                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      1931000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              344                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets             94                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10316.831395                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 20542.553191                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       208397                       # number of writebacks
system.cpu0.dcache.writebacks::total           208397                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       174332                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       174332                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1328335                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1328335                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          667                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          667                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1502667                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1502667                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1502667                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1502667                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       158361                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       158361                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       118660                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       118660                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8186                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8186                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7931                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7931                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       277021                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       277021                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       277021                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       277021                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2036266500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2036266500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4269140489                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4269140489                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     66637500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     66637500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     61703000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     61703000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6305406989                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6305406989                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6305406989                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6305406989                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   9221981000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   9221981000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    843217391                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    843217391                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10065198391                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10065198391                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030818                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.029328                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.050038                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.049461                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.030161                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030161                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8140.422673                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7779.977304                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    45335988                       # DTB read hits
system.cpu1.dtb.read_misses                     67766                       # DTB read misses
system.cpu1.dtb.write_hits                    7974825                       # DTB write hits
system.cpu1.dtb.write_misses                    20571                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2707                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     7654                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   597                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     1825                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                45403754                       # DTB read accesses
system.cpu1.dtb.write_accesses                7995396                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         53310813                       # DTB hits
system.cpu1.dtb.misses                          88337                       # DTB misses
system.cpu1.dtb.accesses                     53399150                       # DTB accesses
system.cpu1.itb.inst_hits                    10447082                       # ITB inst hits
system.cpu1.itb.inst_misses                      7775                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1562                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     5028                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                10454857                       # ITB inst accesses
system.cpu1.itb.hits                         10447082                       # DTB hits
system.cpu1.itb.misses                           7775                       # DTB misses
system.cpu1.itb.accesses                     10454857                       # DTB accesses
system.cpu1.numCycles                       361402922                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                11186826                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           8978228                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            659649                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              7702930                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 6115228                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  914050                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect             143881                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles          24238168                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      79362685                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   11186826                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           7029278                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     17037334                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                5514806                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                    104106                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              74528918                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                5814                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       113982                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       165536                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          353                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 10441784                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               854309                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   4213                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         119977470                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.807329                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.185858                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               102950411     85.81%     85.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                 1027065      0.86%     86.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 1252290      1.04%     87.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 2222542      1.85%     89.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1450508      1.21%     90.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  763655      0.64%     91.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 2450140      2.04%     93.45% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  546027      0.46%     93.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 7314832      6.10%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           119977470                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.030954                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.219596                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                25932861                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             74439661                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 15341871                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               600655                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               3662422                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1558576                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               123600                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              90136794                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               402223                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               3662422                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                27545183                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               32824542                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      37049772                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 14316379                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              4579172                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              83629464                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 2956                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                679775                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              3317472                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           46248                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           88354418                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            386338466                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       386288470                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            49996                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             54988347                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                33366070                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            602019                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        524737                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  8626692                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            16066963                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            9656417                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          1282659                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1811239                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  75062782                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded            1031692                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 98462898                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           155624                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       21632122                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     61142717                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        223849                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    119977470                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.820678                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.544702                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           85994383     71.68%     71.68% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            9640016      8.03%     79.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            5133014      4.28%     83.99% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            4263453      3.55%     87.54% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           11149849      9.29%     96.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            2119505      1.77%     98.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6            1269612      1.06%     99.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             309202      0.26%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              98436      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      119977470                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  44202      0.54%      0.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   979      0.01%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               7732056     95.26%     95.82% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               339451      4.18%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            92819      0.09%      0.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             43271411     43.95%     44.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               69911      0.07%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 29      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                39      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          1782      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     44.11% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            46626317     47.35%     91.47% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            8400570      8.53%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              98462898                       # Type of FU issued
system.cpu1.iq.rate                          0.272446                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    8116688                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.082434                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         325251459                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         97743765                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     61686980                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              12182                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6832                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5554                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             106480420                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6347                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          431690                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      4883583                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         7497                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        24780                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1835710                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     32214526                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      1149867                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               3662422                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               25277331                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               367624                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           76304263                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           229674                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             16066963                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             9656417                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            636963                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 63488                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 8504                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         24780                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        400468                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       244624                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              645092                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             95561838                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             45782046                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2901060                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       209789                       # number of nop insts executed
system.cpu1.iew.exec_refs                    54078244                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 8068913                       # Number of branches executed
system.cpu1.iew.exec_stores                   8296198                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.264419                       # Inst execution rate
system.cpu1.iew.wb_sent                      94191755                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     61692534                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 33977338                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 61891561                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.170703                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.548982                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts      42383808                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps        53979911                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts       22261112                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         807843                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           569017                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    116371049                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.463860                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.434767                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     97273421     83.59%     83.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      9394437      8.07%     91.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      2575050      2.21%     93.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1580988      1.36%     95.23% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1207821      1.04%     96.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       698590      0.60%     96.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      1120414      0.96%     97.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       516932      0.44%     98.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      2003396      1.72%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    116371049                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            42383808                       # Number of instructions committed
system.cpu1.commit.committedOps              53979911                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      19004087                       # Number of memory references committed
system.cpu1.commit.loads                     11183380                       # Number of loads committed
system.cpu1.commit.membars                     242516                       # Number of memory barriers committed
system.cpu1.commit.branches                   6784179                       # Number of branches committed
system.cpu1.commit.fp_insts                      5428                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 48067133                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              633379                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              2003396                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   189385035                       # The number of ROB reads
system.cpu1.rob.rob_writes                  156267900                       # The number of ROB writes
system.cpu1.timesIdled                        1564769                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      241425452                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  4780203327                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   42257981                       # Number of Instructions Simulated
system.cpu1.committedOps                     53854084                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             42257981                       # Number of Instructions Simulated
system.cpu1.cpi                              8.552300                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        8.552300                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.116928                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.116928                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               430079753                       # number of integer regfile reads
system.cpu1.int_regfile_writes               64515100                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4419                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    2066                       # number of floating regfile writes
system.cpu1.misc_regfile_reads              102262967                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                513108                       # number of misc regfile writes
system.cpu1.icache.replacements                714529                       # number of replacements
system.cpu1.icache.tagsinuse               498.761723                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 9665211                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                715041                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 13.517003                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74296656000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   498.761723                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.974144                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.974144                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst      9665211                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        9665211                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst      9665211                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         9665211                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst      9665211                       # number of overall hits
system.cpu1.icache.overall_hits::total        9665211                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       776521                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       776521                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       776521                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        776521                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       776521                       # number of overall misses
system.cpu1.icache.overall_misses::total       776521                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  11390030990                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  11390030990                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  11390030990                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  11390030990                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  11390030990                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  11390030990                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     10441732                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     10441732                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     10441732                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     10441732                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     10441732                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     10441732                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.074367                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.074367                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.074367                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      1572992                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              238                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  6609.210084                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks        32858                       # number of writebacks
system.cpu1.icache.writebacks::total            32858                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        61445                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        61445                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        61445                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        61445                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        61445                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        61445                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       715076                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       715076                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       715076                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       715076                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       715076                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       715076                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8506439492                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   8506439492                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8506439492                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   8506439492                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8506439492                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   8506439492                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      2572500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      2572500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      2572500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      2572500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.068483                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.068483                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.068483                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                417022                       # number of replacements
system.cpu1.dcache.tagsinuse               464.475329                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                15242379                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                417534                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 36.505719                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           72565634000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   464.475329                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.907178                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.907178                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data     10057492                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       10057492                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4888994                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4888994                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       126446                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total       126446                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data       120021                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total       120021                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     14946486                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        14946486                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     14946486                       # number of overall hits
system.cpu1.dcache.overall_hits::total       14946486                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       473003                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       473003                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1726377                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1726377                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14767                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        14767                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10580                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10580                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      2199380                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       2199380                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      2199380                       # number of overall misses
system.cpu1.dcache.overall_misses::total      2199380                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   7143574500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   7143574500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  57173185397                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  57173185397                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    177446500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    177446500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     91928500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     91928500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  64316759897                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  64316759897                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  64316759897                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  64316759897                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     10530495                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     10530495                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6615371                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6615371                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       141213                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       141213                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       130601                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       130601                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     17145866                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     17145866                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     17145866                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     17145866                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.044917                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.260965                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.104573                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.081010                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.128275                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.128275                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8688.894140                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     15169067                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      5303000                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3226                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            149                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4702.128642                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 35590.604027                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       346093                       # number of writebacks
system.cpu1.dcache.writebacks::total           346093                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       202550                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       202550                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1548902                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      1548902                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1254                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1254                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1751452                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1751452                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1751452                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1751452                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       270453                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       270453                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       177475                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       177475                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        13513                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        13513                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10575                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10575                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       447928                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       447928                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       447928                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       447928                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3409672000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3409672000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5551338067                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5551338067                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    121446000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    121446000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     60146500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     60146500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8961010067                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   8961010067                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8961010067                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   8961010067                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  41662340533                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  41662340533                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025683                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026828                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.095692                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.080972                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026125                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026125                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8987.345519                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5687.612293                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1308180699879                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   36058                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   61621                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------