stats.txt revision 8835:7c68f84d7c4e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.582494 # Number of seconds simulated 4sim_ticks 2582494330500 # Number of ticks simulated 5final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 80373 # Simulator instruction rate (inst/s) 8host_op_rate 103823 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3357432165 # Simulator tick rate (ticks/s) 10host_mem_usage 383300 # Number of bytes of host memory used 11host_seconds 769.19 # Real time elapsed on the host 12sim_insts 61822124 # Number of instructions simulated 13sim_ops 79859495 # Number of ops (including micro ops) simulated 14system.nvmem.bytes_read 384 # Number of bytes read from this memory 15system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory 16system.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.nvmem.num_reads 6 # Number of read requests responded to by this memory 18system.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) 21system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) 22system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) 23system.physmem.bytes_read 131499364 # Number of bytes read from this memory 24system.physmem.bytes_inst_read 1184000 # Number of instructions bytes read from this memory 25system.physmem.bytes_written 10236688 # Number of bytes written to this memory 26system.physmem.num_reads 15129208 # Number of read requests responded to by this memory 27system.physmem.num_writes 869902 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 50919517 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 458471 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 3963876 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 54883393 # Total bandwidth to/from this memory (bytes/s) 33system.l2c.replacements 132156 # number of replacements 34system.l2c.tagsinuse 27576.843805 # Cycle average of tags in use 35system.l2c.total_refs 1820044 # Total number of references to valid blocks. 36system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. 37system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 15356.692298 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu0.dtb.walker 22.670587 # Average occupied blocks per requestor 41system.l2c.occ_blocks::cpu0.itb.walker 1.636552 # Average occupied blocks per requestor 42system.l2c.occ_blocks::cpu0.inst 3410.170856 # Average occupied blocks per requestor 43system.l2c.occ_blocks::cpu0.data 1587.790766 # Average occupied blocks per requestor 44system.l2c.occ_blocks::cpu1.dtb.walker 18.616033 # Average occupied blocks per requestor 45system.l2c.occ_blocks::cpu1.itb.walker 3.576285 # Average occupied blocks per requestor 46system.l2c.occ_blocks::cpu1.inst 2636.430831 # Average occupied blocks per requestor 47system.l2c.occ_blocks::cpu1.data 4539.259596 # Average occupied blocks per requestor 48system.l2c.occ_percent::writebacks 0.234325 # Average percentage of cache occupancy 49system.l2c.occ_percent::cpu0.dtb.walker 0.000346 # Average percentage of cache occupancy 50system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu0.inst 0.052035 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu0.data 0.024228 # Average percentage of cache occupancy 53system.l2c.occ_percent::cpu1.dtb.walker 0.000284 # Average percentage of cache occupancy 54system.l2c.occ_percent::cpu1.itb.walker 0.000055 # Average percentage of cache occupancy 55system.l2c.occ_percent::cpu1.inst 0.040229 # Average percentage of cache occupancy 56system.l2c.occ_percent::cpu1.data 0.069264 # Average percentage of cache occupancy 57system.l2c.occ_percent::total 0.420789 # Average percentage of cache occupancy 58system.l2c.ReadReq_hits::cpu0.dtb.walker 89183 # number of ReadReq hits 59system.l2c.ReadReq_hits::cpu0.itb.walker 17213 # number of ReadReq hits 60system.l2c.ReadReq_hits::cpu0.inst 526448 # number of ReadReq hits 61system.l2c.ReadReq_hits::cpu0.data 212618 # number of ReadReq hits 62system.l2c.ReadReq_hits::cpu1.dtb.walker 73946 # number of ReadReq hits 63system.l2c.ReadReq_hits::cpu1.itb.walker 3915 # number of ReadReq hits 64system.l2c.ReadReq_hits::cpu1.inst 477126 # number of ReadReq hits 65system.l2c.ReadReq_hits::cpu1.data 150598 # number of ReadReq hits 66system.l2c.ReadReq_hits::total 1551047 # number of ReadReq hits 67system.l2c.Writeback_hits::writebacks 599046 # number of Writeback hits 68system.l2c.Writeback_hits::total 599046 # number of Writeback hits 69system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits 70system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits 71system.l2c.UpgradeReq_hits::total 1992 # number of UpgradeReq hits 72system.l2c.SCUpgradeReq_hits::cpu0.data 175 # number of SCUpgradeReq hits 73system.l2c.SCUpgradeReq_hits::cpu1.data 443 # number of SCUpgradeReq hits 74system.l2c.SCUpgradeReq_hits::total 618 # number of SCUpgradeReq hits 75system.l2c.ReadExReq_hits::cpu0.data 58603 # number of ReadExReq hits 76system.l2c.ReadExReq_hits::cpu1.data 38925 # number of ReadExReq hits 77system.l2c.ReadExReq_hits::total 97528 # number of ReadExReq hits 78system.l2c.demand_hits::cpu0.dtb.walker 89183 # number of demand (read+write) hits 79system.l2c.demand_hits::cpu0.itb.walker 17213 # number of demand (read+write) hits 80system.l2c.demand_hits::cpu0.inst 526448 # number of demand (read+write) hits 81system.l2c.demand_hits::cpu0.data 271221 # number of demand (read+write) hits 82system.l2c.demand_hits::cpu1.dtb.walker 73946 # number of demand (read+write) hits 83system.l2c.demand_hits::cpu1.itb.walker 3915 # number of demand (read+write) hits 84system.l2c.demand_hits::cpu1.inst 477126 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu1.data 189523 # number of demand (read+write) hits 86system.l2c.demand_hits::total 1648575 # number of demand (read+write) hits 87system.l2c.overall_hits::cpu0.dtb.walker 89183 # number of overall hits 88system.l2c.overall_hits::cpu0.itb.walker 17213 # number of overall hits 89system.l2c.overall_hits::cpu0.inst 526448 # number of overall hits 90system.l2c.overall_hits::cpu0.data 271221 # number of overall hits 91system.l2c.overall_hits::cpu1.dtb.walker 73946 # number of overall hits 92system.l2c.overall_hits::cpu1.itb.walker 3915 # number of overall hits 93system.l2c.overall_hits::cpu1.inst 477126 # number of overall hits 94system.l2c.overall_hits::cpu1.data 189523 # number of overall hits 95system.l2c.overall_hits::total 1648575 # number of overall hits 96system.l2c.ReadReq_misses::cpu0.dtb.walker 70 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu0.itb.walker 10 # number of ReadReq misses 98system.l2c.ReadReq_misses::cpu0.inst 10849 # number of ReadReq misses 99system.l2c.ReadReq_misses::cpu0.data 8938 # number of ReadReq misses 100system.l2c.ReadReq_misses::cpu1.dtb.walker 78 # number of ReadReq misses 101system.l2c.ReadReq_misses::cpu1.itb.walker 12 # number of ReadReq misses 102system.l2c.ReadReq_misses::cpu1.inst 7504 # number of ReadReq misses 103system.l2c.ReadReq_misses::cpu1.data 13059 # number of ReadReq misses 104system.l2c.ReadReq_misses::total 40520 # number of ReadReq misses 105system.l2c.UpgradeReq_misses::cpu0.data 7351 # number of UpgradeReq misses 106system.l2c.UpgradeReq_misses::cpu1.data 3816 # number of UpgradeReq misses 107system.l2c.UpgradeReq_misses::total 11167 # number of UpgradeReq misses 108system.l2c.SCUpgradeReq_misses::cpu0.data 849 # number of SCUpgradeReq misses 109system.l2c.SCUpgradeReq_misses::cpu1.data 448 # number of SCUpgradeReq misses 110system.l2c.SCUpgradeReq_misses::total 1297 # number of SCUpgradeReq misses 111system.l2c.ReadExReq_misses::cpu0.data 97885 # number of ReadExReq misses 112system.l2c.ReadExReq_misses::cpu1.data 50394 # number of ReadExReq misses 113system.l2c.ReadExReq_misses::total 148279 # number of ReadExReq misses 114system.l2c.demand_misses::cpu0.dtb.walker 70 # number of demand (read+write) misses 115system.l2c.demand_misses::cpu0.itb.walker 10 # number of demand (read+write) misses 116system.l2c.demand_misses::cpu0.inst 10849 # number of demand (read+write) misses 117system.l2c.demand_misses::cpu0.data 106823 # number of demand (read+write) misses 118system.l2c.demand_misses::cpu1.dtb.walker 78 # number of demand (read+write) misses 119system.l2c.demand_misses::cpu1.itb.walker 12 # number of demand (read+write) misses 120system.l2c.demand_misses::cpu1.inst 7504 # number of demand (read+write) misses 121system.l2c.demand_misses::cpu1.data 63453 # number of demand (read+write) misses 122system.l2c.demand_misses::total 188799 # number of demand (read+write) misses 123system.l2c.overall_misses::cpu0.dtb.walker 70 # number of overall misses 124system.l2c.overall_misses::cpu0.itb.walker 10 # number of overall misses 125system.l2c.overall_misses::cpu0.inst 10849 # number of overall misses 126system.l2c.overall_misses::cpu0.data 106823 # number of overall misses 127system.l2c.overall_misses::cpu1.dtb.walker 78 # number of overall misses 128system.l2c.overall_misses::cpu1.itb.walker 12 # number of overall misses 129system.l2c.overall_misses::cpu1.inst 7504 # number of overall misses 130system.l2c.overall_misses::cpu1.data 63453 # number of overall misses 131system.l2c.overall_misses::total 188799 # number of overall misses 132system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3650500 # number of ReadReq miss cycles 133system.l2c.ReadReq_miss_latency::cpu0.itb.walker 521000 # number of ReadReq miss cycles 134system.l2c.ReadReq_miss_latency::cpu0.inst 567333500 # number of ReadReq miss cycles 135system.l2c.ReadReq_miss_latency::cpu0.data 466408000 # number of ReadReq miss cycles 136system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 4067500 # number of ReadReq miss cycles 137system.l2c.ReadReq_miss_latency::cpu1.itb.walker 625000 # number of ReadReq miss cycles 138system.l2c.ReadReq_miss_latency::cpu1.inst 392575500 # number of ReadReq miss cycles 139system.l2c.ReadReq_miss_latency::cpu1.data 681928000 # number of ReadReq miss cycles 140system.l2c.ReadReq_miss_latency::total 2117109000 # number of ReadReq miss cycles 141system.l2c.UpgradeReq_miss_latency::cpu0.data 27539500 # number of UpgradeReq miss cycles 142system.l2c.UpgradeReq_miss_latency::cpu1.data 32790500 # number of UpgradeReq miss cycles 143system.l2c.UpgradeReq_miss_latency::total 60330000 # number of UpgradeReq miss cycles 144system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1772000 # number of SCUpgradeReq miss cycles 145system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5901500 # number of SCUpgradeReq miss cycles 146system.l2c.SCUpgradeReq_miss_latency::total 7673500 # number of SCUpgradeReq miss cycles 147system.l2c.ReadExReq_miss_latency::cpu0.data 5139681999 # number of ReadExReq miss cycles 148system.l2c.ReadExReq_miss_latency::cpu1.data 2639420000 # number of ReadExReq miss cycles 149system.l2c.ReadExReq_miss_latency::total 7779101999 # number of ReadExReq miss cycles 150system.l2c.demand_miss_latency::cpu0.dtb.walker 3650500 # number of demand (read+write) miss cycles 151system.l2c.demand_miss_latency::cpu0.itb.walker 521000 # number of demand (read+write) miss cycles 152system.l2c.demand_miss_latency::cpu0.inst 567333500 # number of demand (read+write) miss cycles 153system.l2c.demand_miss_latency::cpu0.data 5606089999 # number of demand (read+write) miss cycles 154system.l2c.demand_miss_latency::cpu1.dtb.walker 4067500 # number of demand (read+write) miss cycles 155system.l2c.demand_miss_latency::cpu1.itb.walker 625000 # number of demand (read+write) miss cycles 156system.l2c.demand_miss_latency::cpu1.inst 392575500 # number of demand (read+write) miss cycles 157system.l2c.demand_miss_latency::cpu1.data 3321348000 # number of demand (read+write) miss cycles 158system.l2c.demand_miss_latency::total 9896210999 # number of demand (read+write) miss cycles 159system.l2c.overall_miss_latency::cpu0.dtb.walker 3650500 # number of overall miss cycles 160system.l2c.overall_miss_latency::cpu0.itb.walker 521000 # number of overall miss cycles 161system.l2c.overall_miss_latency::cpu0.inst 567333500 # number of overall miss cycles 162system.l2c.overall_miss_latency::cpu0.data 5606089999 # number of overall miss cycles 163system.l2c.overall_miss_latency::cpu1.dtb.walker 4067500 # number of overall miss cycles 164system.l2c.overall_miss_latency::cpu1.itb.walker 625000 # number of overall miss cycles 165system.l2c.overall_miss_latency::cpu1.inst 392575500 # number of overall miss cycles 166system.l2c.overall_miss_latency::cpu1.data 3321348000 # number of overall miss cycles 167system.l2c.overall_miss_latency::total 9896210999 # number of overall miss cycles 168system.l2c.ReadReq_accesses::cpu0.dtb.walker 89253 # number of ReadReq accesses(hits+misses) 169system.l2c.ReadReq_accesses::cpu0.itb.walker 17223 # number of ReadReq accesses(hits+misses) 170system.l2c.ReadReq_accesses::cpu0.inst 537297 # number of ReadReq accesses(hits+misses) 171system.l2c.ReadReq_accesses::cpu0.data 221556 # number of ReadReq accesses(hits+misses) 172system.l2c.ReadReq_accesses::cpu1.dtb.walker 74024 # number of ReadReq accesses(hits+misses) 173system.l2c.ReadReq_accesses::cpu1.itb.walker 3927 # number of ReadReq accesses(hits+misses) 174system.l2c.ReadReq_accesses::cpu1.inst 484630 # number of ReadReq accesses(hits+misses) 175system.l2c.ReadReq_accesses::cpu1.data 163657 # number of ReadReq accesses(hits+misses) 176system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) 177system.l2c.Writeback_accesses::writebacks 599046 # number of Writeback accesses(hits+misses) 178system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) 179system.l2c.UpgradeReq_accesses::cpu0.data 8343 # number of UpgradeReq accesses(hits+misses) 180system.l2c.UpgradeReq_accesses::cpu1.data 4816 # number of UpgradeReq accesses(hits+misses) 181system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) 182system.l2c.SCUpgradeReq_accesses::cpu0.data 1024 # number of SCUpgradeReq accesses(hits+misses) 183system.l2c.SCUpgradeReq_accesses::cpu1.data 891 # number of SCUpgradeReq accesses(hits+misses) 184system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) 185system.l2c.ReadExReq_accesses::cpu0.data 156488 # number of ReadExReq accesses(hits+misses) 186system.l2c.ReadExReq_accesses::cpu1.data 89319 # number of ReadExReq accesses(hits+misses) 187system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) 188system.l2c.demand_accesses::cpu0.dtb.walker 89253 # number of demand (read+write) accesses 189system.l2c.demand_accesses::cpu0.itb.walker 17223 # number of demand (read+write) accesses 190system.l2c.demand_accesses::cpu0.inst 537297 # number of demand (read+write) accesses 191system.l2c.demand_accesses::cpu0.data 378044 # number of demand (read+write) accesses 192system.l2c.demand_accesses::cpu1.dtb.walker 74024 # number of demand (read+write) accesses 193system.l2c.demand_accesses::cpu1.itb.walker 3927 # number of demand (read+write) accesses 194system.l2c.demand_accesses::cpu1.inst 484630 # number of demand (read+write) accesses 195system.l2c.demand_accesses::cpu1.data 252976 # number of demand (read+write) accesses 196system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses 197system.l2c.overall_accesses::cpu0.dtb.walker 89253 # number of overall (read+write) accesses 198system.l2c.overall_accesses::cpu0.itb.walker 17223 # number of overall (read+write) accesses 199system.l2c.overall_accesses::cpu0.inst 537297 # number of overall (read+write) accesses 200system.l2c.overall_accesses::cpu0.data 378044 # number of overall (read+write) accesses 201system.l2c.overall_accesses::cpu1.dtb.walker 74024 # number of overall (read+write) accesses 202system.l2c.overall_accesses::cpu1.itb.walker 3927 # number of overall (read+write) accesses 203system.l2c.overall_accesses::cpu1.inst 484630 # number of overall (read+write) accesses 204system.l2c.overall_accesses::cpu1.data 252976 # number of overall (read+write) accesses 205system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses 206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for ReadReq accesses 207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000581 # miss rate for ReadReq accesses 208system.l2c.ReadReq_miss_rate::cpu0.inst 0.020192 # miss rate for ReadReq accesses 209system.l2c.ReadReq_miss_rate::cpu0.data 0.040342 # miss rate for ReadReq accesses 210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for ReadReq accesses 211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.003056 # miss rate for ReadReq accesses 212system.l2c.ReadReq_miss_rate::cpu1.inst 0.015484 # miss rate for ReadReq accesses 213system.l2c.ReadReq_miss_rate::cpu1.data 0.079795 # miss rate for ReadReq accesses 214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.881098 # miss rate for UpgradeReq accesses 215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792359 # miss rate for UpgradeReq accesses 216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.829102 # miss rate for SCUpgradeReq accesses 217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.502806 # miss rate for SCUpgradeReq accesses 218system.l2c.ReadExReq_miss_rate::cpu0.data 0.625511 # miss rate for ReadExReq accesses 219system.l2c.ReadExReq_miss_rate::cpu1.data 0.564202 # miss rate for ReadExReq accesses 220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for demand accesses 221system.l2c.demand_miss_rate::cpu0.itb.walker 0.000581 # miss rate for demand accesses 222system.l2c.demand_miss_rate::cpu0.inst 0.020192 # miss rate for demand accesses 223system.l2c.demand_miss_rate::cpu0.data 0.282568 # miss rate for demand accesses 224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for demand accesses 225system.l2c.demand_miss_rate::cpu1.itb.walker 0.003056 # miss rate for demand accesses 226system.l2c.demand_miss_rate::cpu1.inst 0.015484 # miss rate for demand accesses 227system.l2c.demand_miss_rate::cpu1.data 0.250826 # miss rate for demand accesses 228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for overall accesses 229system.l2c.overall_miss_rate::cpu0.itb.walker 0.000581 # miss rate for overall accesses 230system.l2c.overall_miss_rate::cpu0.inst 0.020192 # miss rate for overall accesses 231system.l2c.overall_miss_rate::cpu0.data 0.282568 # miss rate for overall accesses 232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for overall accesses 233system.l2c.overall_miss_rate::cpu1.itb.walker 0.003056 # miss rate for overall accesses 234system.l2c.overall_miss_rate::cpu1.inst 0.015484 # miss rate for overall accesses 235system.l2c.overall_miss_rate::cpu1.data 0.250826 # miss rate for overall accesses 236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency 237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52100 # average ReadReq miss latency 238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.621532 # average ReadReq miss latency 239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52182.591184 # average ReadReq miss latency 240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average ReadReq miss latency 241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52083.333333 # average ReadReq miss latency 242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52315.498401 # average ReadReq miss latency 243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52219.006049 # average ReadReq miss latency 244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3746.361039 # average UpgradeReq miss latency 245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8592.898323 # average UpgradeReq miss latency 246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2087.161366 # average SCUpgradeReq miss latency 247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13172.991071 # average SCUpgradeReq miss latency 248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52507.350452 # average ReadExReq miss latency 249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52375.679644 # average ReadExReq miss latency 250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency 251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency 252system.l2c.demand_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency 253system.l2c.demand_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency 254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency 255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency 256system.l2c.demand_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency 257system.l2c.demand_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency 258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency 259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency 260system.l2c.overall_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency 261system.l2c.overall_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency 262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency 263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency 264system.l2c.overall_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency 265system.l2c.overall_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency 266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 269system.l2c.blocked::no_targets 0 # number of cycles access was blocked 270system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 271system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 272system.l2c.fast_writes 0 # number of fast writes performed 273system.l2c.cache_copies 0 # number of cache copies performed 274system.l2c.writebacks::writebacks 112618 # number of writebacks 275system.l2c.writebacks::total 112618 # number of writebacks 276system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits 277system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits 278system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits 279system.l2c.ReadReq_mshr_hits::cpu1.data 37 # number of ReadReq MSHR hits 280system.l2c.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits 281system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 282system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits 283system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 284system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits 285system.l2c.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits 286system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 287system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits 288system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 289system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits 290system.l2c.overall_mshr_hits::total 97 # number of overall MSHR hits 291system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 70 # number of ReadReq MSHR misses 292system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 10 # number of ReadReq MSHR misses 293system.l2c.ReadReq_mshr_misses::cpu0.inst 10841 # number of ReadReq MSHR misses 294system.l2c.ReadReq_mshr_misses::cpu0.data 8896 # number of ReadReq MSHR misses 295system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 78 # number of ReadReq MSHR misses 296system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 12 # number of ReadReq MSHR misses 297system.l2c.ReadReq_mshr_misses::cpu1.inst 7494 # number of ReadReq MSHR misses 298system.l2c.ReadReq_mshr_misses::cpu1.data 13022 # number of ReadReq MSHR misses 299system.l2c.ReadReq_mshr_misses::total 40423 # number of ReadReq MSHR misses 300system.l2c.UpgradeReq_mshr_misses::cpu0.data 7351 # number of UpgradeReq MSHR misses 301system.l2c.UpgradeReq_mshr_misses::cpu1.data 3816 # number of UpgradeReq MSHR misses 302system.l2c.UpgradeReq_mshr_misses::total 11167 # number of UpgradeReq MSHR misses 303system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 849 # number of SCUpgradeReq MSHR misses 304system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 448 # number of SCUpgradeReq MSHR misses 305system.l2c.SCUpgradeReq_mshr_misses::total 1297 # number of SCUpgradeReq MSHR misses 306system.l2c.ReadExReq_mshr_misses::cpu0.data 97885 # number of ReadExReq MSHR misses 307system.l2c.ReadExReq_mshr_misses::cpu1.data 50394 # number of ReadExReq MSHR misses 308system.l2c.ReadExReq_mshr_misses::total 148279 # number of ReadExReq MSHR misses 309system.l2c.demand_mshr_misses::cpu0.dtb.walker 70 # number of demand (read+write) MSHR misses 310system.l2c.demand_mshr_misses::cpu0.itb.walker 10 # number of demand (read+write) MSHR misses 311system.l2c.demand_mshr_misses::cpu0.inst 10841 # number of demand (read+write) MSHR misses 312system.l2c.demand_mshr_misses::cpu0.data 106781 # number of demand (read+write) MSHR misses 313system.l2c.demand_mshr_misses::cpu1.dtb.walker 78 # number of demand (read+write) MSHR misses 314system.l2c.demand_mshr_misses::cpu1.itb.walker 12 # number of demand (read+write) MSHR misses 315system.l2c.demand_mshr_misses::cpu1.inst 7494 # number of demand (read+write) MSHR misses 316system.l2c.demand_mshr_misses::cpu1.data 63416 # number of demand (read+write) MSHR misses 317system.l2c.demand_mshr_misses::total 188702 # number of demand (read+write) MSHR misses 318system.l2c.overall_mshr_misses::cpu0.dtb.walker 70 # number of overall MSHR misses 319system.l2c.overall_mshr_misses::cpu0.itb.walker 10 # number of overall MSHR misses 320system.l2c.overall_mshr_misses::cpu0.inst 10841 # number of overall MSHR misses 321system.l2c.overall_mshr_misses::cpu0.data 106781 # number of overall MSHR misses 322system.l2c.overall_mshr_misses::cpu1.dtb.walker 78 # number of overall MSHR misses 323system.l2c.overall_mshr_misses::cpu1.itb.walker 12 # number of overall MSHR misses 324system.l2c.overall_mshr_misses::cpu1.inst 7494 # number of overall MSHR misses 325system.l2c.overall_mshr_misses::cpu1.data 63416 # number of overall MSHR misses 326system.l2c.overall_mshr_misses::total 188702 # number of overall MSHR misses 327system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2801500 # number of ReadReq MSHR miss cycles 328system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 401000 # number of ReadReq MSHR miss cycles 329system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 434490500 # number of ReadReq MSHR miss cycles 330system.l2c.ReadReq_mshr_miss_latency::cpu0.data 356315000 # number of ReadReq MSHR miss cycles 331system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3121000 # number of ReadReq MSHR miss cycles 332system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 480000 # number of ReadReq MSHR miss cycles 333system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300775500 # number of ReadReq MSHR miss cycles 334system.l2c.ReadReq_mshr_miss_latency::cpu1.data 521480000 # number of ReadReq MSHR miss cycles 335system.l2c.ReadReq_mshr_miss_latency::total 1619864500 # number of ReadReq MSHR miss cycles 336system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 294259500 # number of UpgradeReq MSHR miss cycles 337system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 152703500 # number of UpgradeReq MSHR miss cycles 338system.l2c.UpgradeReq_mshr_miss_latency::total 446963000 # number of UpgradeReq MSHR miss cycles 339system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 33985000 # number of SCUpgradeReq MSHR miss cycles 340system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17954000 # number of SCUpgradeReq MSHR miss cycles 341system.l2c.SCUpgradeReq_mshr_miss_latency::total 51939000 # number of SCUpgradeReq MSHR miss cycles 342system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3922908499 # number of ReadExReq MSHR miss cycles 343system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2018431500 # number of ReadExReq MSHR miss cycles 344system.l2c.ReadExReq_mshr_miss_latency::total 5941339999 # number of ReadExReq MSHR miss cycles 345system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2801500 # number of demand (read+write) MSHR miss cycles 346system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 401000 # number of demand (read+write) MSHR miss cycles 347system.l2c.demand_mshr_miss_latency::cpu0.inst 434490500 # number of demand (read+write) MSHR miss cycles 348system.l2c.demand_mshr_miss_latency::cpu0.data 4279223499 # number of demand (read+write) MSHR miss cycles 349system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3121000 # number of demand (read+write) MSHR miss cycles 350system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 480000 # number of demand (read+write) MSHR miss cycles 351system.l2c.demand_mshr_miss_latency::cpu1.inst 300775500 # number of demand (read+write) MSHR miss cycles 352system.l2c.demand_mshr_miss_latency::cpu1.data 2539911500 # number of demand (read+write) MSHR miss cycles 353system.l2c.demand_mshr_miss_latency::total 7561204499 # number of demand (read+write) MSHR miss cycles 354system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2801500 # number of overall MSHR miss cycles 355system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 401000 # number of overall MSHR miss cycles 356system.l2c.overall_mshr_miss_latency::cpu0.inst 434490500 # number of overall MSHR miss cycles 357system.l2c.overall_mshr_miss_latency::cpu0.data 4279223499 # number of overall MSHR miss cycles 358system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3121000 # number of overall MSHR miss cycles 359system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 480000 # number of overall MSHR miss cycles 360system.l2c.overall_mshr_miss_latency::cpu1.inst 300775500 # number of overall MSHR miss cycles 361system.l2c.overall_mshr_miss_latency::cpu1.data 2539911500 # number of overall MSHR miss cycles 362system.l2c.overall_mshr_miss_latency::total 7561204499 # number of overall MSHR miss cycles 363system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4981000 # number of ReadReq MSHR uncacheable cycles 364system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 124405850500 # number of ReadReq MSHR uncacheable cycles 365system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1891000 # number of ReadReq MSHR uncacheable cycles 366system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 7552193500 # number of ReadReq MSHR uncacheable cycles 367system.l2c.ReadReq_mshr_uncacheable_latency::total 131964916000 # number of ReadReq MSHR uncacheable cycles 368system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 881564880 # number of WriteReq MSHR uncacheable cycles 369system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31653443800 # number of WriteReq MSHR uncacheable cycles 370system.l2c.WriteReq_mshr_uncacheable_latency::total 32535008680 # number of WriteReq MSHR uncacheable cycles 371system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4981000 # number of overall MSHR uncacheable cycles 372system.l2c.overall_mshr_uncacheable_latency::cpu0.data 125287415380 # number of overall MSHR uncacheable cycles 373system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1891000 # number of overall MSHR uncacheable cycles 374system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39205637300 # number of overall MSHR uncacheable cycles 375system.l2c.overall_mshr_uncacheable_latency::total 164499924680 # number of overall MSHR uncacheable cycles 376system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for ReadReq accesses 377system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for ReadReq accesses 378system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for ReadReq accesses 379system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.040152 # mshr miss rate for ReadReq accesses 380system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for ReadReq accesses 381system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for ReadReq accesses 382system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for ReadReq accesses 383system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.079569 # mshr miss rate for ReadReq accesses 384system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.881098 # mshr miss rate for UpgradeReq accesses 385system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792359 # mshr miss rate for UpgradeReq accesses 386system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.829102 # mshr miss rate for SCUpgradeReq accesses 387system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.502806 # mshr miss rate for SCUpgradeReq accesses 388system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.625511 # mshr miss rate for ReadExReq accesses 389system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564202 # mshr miss rate for ReadExReq accesses 390system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for demand accesses 391system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for demand accesses 392system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for demand accesses 393system.l2c.demand_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for demand accesses 394system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for demand accesses 395system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for demand accesses 396system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for demand accesses 397system.l2c.demand_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for demand accesses 398system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for overall accesses 399system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for overall accesses 400system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for overall accesses 401system.l2c.overall_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for overall accesses 402system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for overall accesses 403system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for overall accesses 404system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for overall accesses 405system.l2c.overall_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for overall accesses 406system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average ReadReq mshr miss latency 407system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average ReadReq mshr miss latency 408system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average ReadReq mshr miss latency 409system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40053.394784 # average ReadReq mshr miss latency 410system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average ReadReq mshr miss latency 411system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 412system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average ReadReq mshr miss latency 413system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40046.075872 # average ReadReq mshr miss latency 414system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.859883 # average UpgradeReq mshr miss latency 415system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40016.640461 # average UpgradeReq mshr miss latency 416system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.446408 # average SCUpgradeReq mshr miss latency 417system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.892857 # average SCUpgradeReq mshr miss latency 418system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40076.707350 # average ReadExReq mshr miss latency 419system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40053.012263 # average ReadExReq mshr miss latency 420system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency 421system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency 422system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency 423system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency 424system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency 425system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 426system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency 427system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency 428system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency 429system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency 430system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency 431system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency 432system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency 433system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 434system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency 435system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency 436system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 437system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 438system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 439system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 440system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 441system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 442system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 443system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 444system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 445system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 446system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 447system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 448system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 449system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 450system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 451system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 452system.cf0.dma_write_txs 0 # Number of DMA write transactions. 453system.cpu0.dtb.inst_hits 0 # ITB inst hits 454system.cpu0.dtb.inst_misses 0 # ITB inst misses 455system.cpu0.dtb.read_hits 42410626 # DTB read hits 456system.cpu0.dtb.read_misses 55840 # DTB read misses 457system.cpu0.dtb.write_hits 6900244 # DTB write hits 458system.cpu0.dtb.write_misses 11203 # DTB write misses 459system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 460system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 462system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 463system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB 464system.cpu0.dtb.align_faults 9414 # Number of TLB faults due to alignment restrictions 465system.cpu0.dtb.prefetch_faults 598 # Number of TLB faults due to prefetch 466system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu0.dtb.perms_faults 1544 # Number of TLB faults due to permissions restrictions 468system.cpu0.dtb.read_accesses 42466466 # DTB read accesses 469system.cpu0.dtb.write_accesses 6911447 # DTB write accesses 470system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 471system.cpu0.dtb.hits 49310870 # DTB hits 472system.cpu0.dtb.misses 67043 # DTB misses 473system.cpu0.dtb.accesses 49377913 # DTB accesses 474system.cpu0.itb.inst_hits 6428492 # ITB inst hits 475system.cpu0.itb.inst_misses 17283 # ITB inst misses 476system.cpu0.itb.read_hits 0 # DTB read hits 477system.cpu0.itb.read_misses 0 # DTB read misses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 481system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 482system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 483system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 484system.cpu0.itb.flush_entries 1596 # Number of entries that have been flushed from TLB 485system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 486system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 487system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 488system.cpu0.itb.perms_faults 5840 # Number of TLB faults due to permissions restrictions 489system.cpu0.itb.read_accesses 0 # DTB read accesses 490system.cpu0.itb.write_accesses 0 # DTB write accesses 491system.cpu0.itb.inst_accesses 6445775 # ITB inst accesses 492system.cpu0.itb.hits 6428492 # DTB hits 493system.cpu0.itb.misses 17283 # DTB misses 494system.cpu0.itb.accesses 6445775 # DTB accesses 495system.cpu0.numCycles 352483912 # number of cpu cycles simulated 496system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 497system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 498system.cpu0.BPredUnit.lookups 8645116 # Number of BP lookups 499system.cpu0.BPredUnit.condPredicted 6399988 # Number of conditional branches predicted 500system.cpu0.BPredUnit.condIncorrect 634817 # Number of conditional branches incorrect 501system.cpu0.BPredUnit.BTBLookups 7331445 # Number of BTB lookups 502system.cpu0.BPredUnit.BTBHits 5034787 # Number of BTB hits 503system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 504system.cpu0.BPredUnit.usedRAS 805074 # Number of times the RAS was used to get a target. 505system.cpu0.BPredUnit.RASInCorrect 135243 # Number of incorrect RAS predictions. 506system.cpu0.fetch.icacheStallCycles 16860833 # Number of cycles fetch is stalled on an Icache miss 507system.cpu0.fetch.Insts 45928818 # Number of instructions fetch has processed 508system.cpu0.fetch.Branches 8645116 # Number of branches that fetch encountered 509system.cpu0.fetch.predictedBranches 5839861 # Number of branches that fetch has predicted taken 510system.cpu0.fetch.Cycles 11494054 # Number of cycles fetch has run and was not squashing or blocked 511system.cpu0.fetch.SquashCycles 2657796 # Number of cycles fetch has spent squashing 512system.cpu0.fetch.TlbCycles 106861 # Number of cycles fetch has spent waiting for tlb 513system.cpu0.fetch.BlockedCycles 79215676 # Number of cycles fetch has spent blocked 514system.cpu0.fetch.MiscStallCycles 7529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 515system.cpu0.fetch.PendingTrapStallCycles 114865 # Number of stall cycles due to pending traps 516system.cpu0.fetch.PendingQuiesceStallCycles 114660 # Number of stall cycles due to pending quiesce instructions 517system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR 518system.cpu0.fetch.CacheLines 6422476 # Number of cache lines fetched 519system.cpu0.fetch.IcacheSquashes 290012 # Number of outstanding Icache misses that were squashed 520system.cpu0.fetch.ItlbSquashes 8748 # Number of outstanding ITLB misses that were squashed 521system.cpu0.fetch.rateDist::samples 109764102 # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::mean 0.540930 # Number of instructions fetched each cycle (Total) 523system.cpu0.fetch.rateDist::stdev 1.795930 # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 525system.cpu0.fetch.rateDist::0 98288129 89.54% 89.54% # Number of instructions fetched each cycle (Total) 526system.cpu0.fetch.rateDist::1 1143186 1.04% 90.59% # Number of instructions fetched each cycle (Total) 527system.cpu0.fetch.rateDist::2 1488169 1.36% 91.94% # Number of instructions fetched each cycle (Total) 528system.cpu0.fetch.rateDist::3 1267497 1.15% 93.10% # Number of instructions fetched each cycle (Total) 529system.cpu0.fetch.rateDist::4 1112191 1.01% 94.11% # Number of instructions fetched each cycle (Total) 530system.cpu0.fetch.rateDist::5 871683 0.79% 94.90% # Number of instructions fetched each cycle (Total) 531system.cpu0.fetch.rateDist::6 797932 0.73% 95.63% # Number of instructions fetched each cycle (Total) 532system.cpu0.fetch.rateDist::7 504639 0.46% 96.09% # Number of instructions fetched each cycle (Total) 533system.cpu0.fetch.rateDist::8 4290676 3.91% 100.00% # Number of instructions fetched each cycle (Total) 534system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 535system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 536system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 537system.cpu0.fetch.rateDist::total 109764102 # Number of instructions fetched each cycle (Total) 538system.cpu0.fetch.branchRate 0.024526 # Number of branch fetches per cycle 539system.cpu0.fetch.rate 0.130300 # Number of inst fetches per cycle 540system.cpu0.decode.IdleCycles 18029022 # Number of cycles decode is idle 541system.cpu0.decode.BlockedCycles 78891581 # Number of cycles decode is blocked 542system.cpu0.decode.RunCycles 10335231 # Number of cycles decode is running 543system.cpu0.decode.UnblockCycles 746808 # Number of cycles decode is unblocking 544system.cpu0.decode.SquashCycles 1761460 # Number of cycles decode is squashing 545system.cpu0.decode.BranchResolved 1349167 # Number of times decode resolved a branch 546system.cpu0.decode.BranchMispred 89318 # Number of times decode detected a branch misprediction 547system.cpu0.decode.DecodedInsts 56878279 # Number of instructions handled by decode 548system.cpu0.decode.SquashedInsts 297096 # Number of squashed instructions handled by decode 549system.cpu0.rename.SquashCycles 1761460 # Number of cycles rename is squashing 550system.cpu0.rename.IdleCycles 19090042 # Number of cycles rename is idle 551system.cpu0.rename.BlockCycles 33342572 # Number of cycles rename is blocking 552system.cpu0.rename.serializeStallCycles 41068842 # count of cycles rename stalled for serializing inst 553system.cpu0.rename.RunCycles 10032499 # Number of cycles rename is running 554system.cpu0.rename.UnblockCycles 4468687 # Number of cycles rename is unblocking 555system.cpu0.rename.RenamedInsts 54513639 # Number of instructions processed by rename 556system.cpu0.rename.ROBFullEvents 1476 # Number of times rename has blocked due to ROB full 557system.cpu0.rename.IQFullEvents 586863 # Number of times rename has blocked due to IQ full 558system.cpu0.rename.LSQFullEvents 3152149 # Number of times rename has blocked due to LSQ full 559system.cpu0.rename.FullRegisterEvents 190 # Number of times there has been no free registers 560system.cpu0.rename.RenamedOperands 54798998 # Number of destination operands rename has renamed 561system.cpu0.rename.RenameLookups 247626093 # Number of register rename lookups that rename has made 562system.cpu0.rename.int_rename_lookups 247578647 # Number of integer rename lookups 563system.cpu0.rename.fp_rename_lookups 47446 # Number of floating rename lookups 564system.cpu0.rename.CommittedMaps 41436679 # Number of HB maps that are committed 565system.cpu0.rename.UndoneMaps 13362318 # Number of HB maps that are undone due to squashing 566system.cpu0.rename.serializingInsts 827066 # count of serializing insts renamed 567system.cpu0.rename.tempSerializingInsts 763098 # count of temporary serializing insts renamed 568system.cpu0.rename.skidInsts 8512546 # count of insts added to the skid buffer 569system.cpu0.memDep0.insertedLoads 11778849 # Number of loads inserted to the mem dependence unit. 570system.cpu0.memDep0.insertedStores 7693096 # Number of stores inserted to the mem dependence unit. 571system.cpu0.memDep0.conflictingLoads 1451709 # Number of conflicting loads. 572system.cpu0.memDep0.conflictingStores 1599658 # Number of conflicting stores. 573system.cpu0.iq.iqInstsAdded 50981510 # Number of instructions added to the IQ (excludes non-spec) 574system.cpu0.iq.iqNonSpecInstsAdded 1297142 # Number of non-speculative instructions added to the IQ 575system.cpu0.iq.iqInstsIssued 80275629 # Number of instructions issued 576system.cpu0.iq.iqSquashedInstsIssued 138322 # Number of squashed instructions issued 577system.cpu0.iq.iqSquashedInstsExamined 9920481 # Number of squashed instructions iterated over during squash; mainly for profiling 578system.cpu0.iq.iqSquashedOperandsExamined 22908706 # Number of squashed operands that are examined and possibly removed from graph 579system.cpu0.iq.iqSquashedNonSpecRemoved 252718 # Number of squashed non-spec instructions that were removed 580system.cpu0.iq.issued_per_cycle::samples 109764102 # Number of insts issued each cycle 581system.cpu0.iq.issued_per_cycle::mean 0.731347 # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::stdev 1.440423 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 584system.cpu0.iq.issued_per_cycle::0 80151995 73.02% 73.02% # Number of insts issued each cycle 585system.cpu0.iq.issued_per_cycle::1 10117120 9.22% 82.24% # Number of insts issued each cycle 586system.cpu0.iq.issued_per_cycle::2 4139720 3.77% 86.01% # Number of insts issued each cycle 587system.cpu0.iq.issued_per_cycle::3 3156304 2.88% 88.89% # Number of insts issued each cycle 588system.cpu0.iq.issued_per_cycle::4 9950540 9.07% 97.95% # Number of insts issued each cycle 589system.cpu0.iq.issued_per_cycle::5 1264670 1.15% 99.10% # Number of insts issued each cycle 590system.cpu0.iq.issued_per_cycle::6 681180 0.62% 99.72% # Number of insts issued each cycle 591system.cpu0.iq.issued_per_cycle::7 223017 0.20% 99.93% # Number of insts issued each cycle 592system.cpu0.iq.issued_per_cycle::8 79556 0.07% 100.00% # Number of insts issued each cycle 593system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 594system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 595system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 596system.cpu0.iq.issued_per_cycle::total 109764102 # Number of insts issued each cycle 597system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 598system.cpu0.iq.fu_full::IntAlu 38058 0.47% 0.47% # attempts to use FU when none available 599system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available 600system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available 601system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available 602system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available 603system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.48% # attempts to use FU when none available 604system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.48% # attempts to use FU when none available 605system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.48% # attempts to use FU when none available 606system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.48% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.48% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.48% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.48% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.48% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.48% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.48% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.48% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.48% # attempts to use FU when none available 615system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.48% # attempts to use FU when none available 616system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.48% # attempts to use FU when none available 617system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.48% # attempts to use FU when none available 618system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.48% # attempts to use FU when none available 619system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.48% # attempts to use FU when none available 620system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.48% # attempts to use FU when none available 621system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.48% # attempts to use FU when none available 622system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.48% # attempts to use FU when none available 623system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # attempts to use FU when none available 624system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available 625system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available 626system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available 627system.cpu0.iq.fu_full::MemRead 7704046 95.93% 96.41% # attempts to use FU when none available 628system.cpu0.iq.fu_full::MemWrite 287948 3.59% 100.00% # attempts to use FU when none available 629system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 630system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 631system.cpu0.iq.FU_type_0::No_OpClass 88478 0.11% 0.11% # Type of FU issued 632system.cpu0.iq.FU_type_0::IntAlu 29722864 37.03% 37.14% # Type of FU issued 633system.cpu0.iq.FU_type_0::IntMult 62274 0.08% 37.21% # Type of FU issued 634system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.21% # Type of FU issued 635system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.21% # Type of FU issued 636system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.21% # Type of FU issued 637system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.21% # Type of FU issued 638system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.21% # Type of FU issued 639system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.21% # Type of FU issued 640system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.21% # Type of FU issued 641system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.21% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.21% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.21% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.21% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.21% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdMisc 3 0.00% 37.21% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.21% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.21% # Type of FU issued 649system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.21% # Type of FU issued 650system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 37.21% # Type of FU issued 651system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.21% # Type of FU issued 652system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.21% # Type of FU issued 653system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.21% # Type of FU issued 654system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.21% # Type of FU issued 655system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.21% # Type of FU issued 656system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.21% # Type of FU issued 657system.cpu0.iq.FU_type_0::SimdFloatMisc 1682 0.00% 37.22% # Type of FU issued 658system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.22% # Type of FU issued 659system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 37.22% # Type of FU issued 660system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.22% # Type of FU issued 661system.cpu0.iq.FU_type_0::MemRead 43138789 53.74% 90.95% # Type of FU issued 662system.cpu0.iq.FU_type_0::MemWrite 7261531 9.05% 100.00% # Type of FU issued 663system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 664system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 665system.cpu0.iq.FU_type_0::total 80275629 # Type of FU issued 666system.cpu0.iq.rate 0.227743 # Inst issue rate 667system.cpu0.iq.fu_busy_cnt 8030678 # FU busy when requested 668system.cpu0.iq.fu_busy_rate 0.100039 # FU busy rate (busy events/executed inst) 669system.cpu0.iq.int_inst_queue_reads 278539843 # Number of integer instruction queue reads 670system.cpu0.iq.int_inst_queue_writes 62212125 # Number of integer instruction queue writes 671system.cpu0.iq.int_inst_queue_wakeup_accesses 46665965 # Number of integer instruction queue wakeup accesses 672system.cpu0.iq.fp_inst_queue_reads 11176 # Number of floating instruction queue reads 673system.cpu0.iq.fp_inst_queue_writes 6795 # Number of floating instruction queue writes 674system.cpu0.iq.fp_inst_queue_wakeup_accesses 5030 # Number of floating instruction queue wakeup accesses 675system.cpu0.iq.int_alu_accesses 88212004 # Number of integer alu accesses 676system.cpu0.iq.fp_alu_accesses 5825 # Number of floating point alu accesses 677system.cpu0.iew.lsq.thread0.forwLoads 398434 # Number of loads that had data forwarded from stores 678system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 679system.cpu0.iew.lsq.thread0.squashedLoads 2535542 # Number of loads squashed 680system.cpu0.iew.lsq.thread0.ignoredResponses 5119 # Number of memory responses ignored because the instruction is squashed 681system.cpu0.iew.lsq.thread0.memOrderViolation 20483 # Number of memory ordering violations 682system.cpu0.iew.lsq.thread0.squashedStores 1000305 # Number of stores squashed 683system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 684system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 685system.cpu0.iew.lsq.thread0.rescheduledLoads 32220121 # Number of loads that were rescheduled 686system.cpu0.iew.lsq.thread0.cacheBlocked 13276 # Number of times an access to memory failed due to the cache being blocked 687system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 688system.cpu0.iew.iewSquashCycles 1761460 # Number of cycles IEW is squashing 689system.cpu0.iew.iewBlockCycles 25970226 # Number of cycles IEW is blocking 690system.cpu0.iew.iewUnblockCycles 355776 # Number of cycles IEW is unblocking 691system.cpu0.iew.iewDispatchedInsts 52452605 # Number of instructions dispatched to IQ 692system.cpu0.iew.iewDispSquashedInsts 244534 # Number of squashed instructions skipped by dispatch 693system.cpu0.iew.iewDispLoadInsts 11778849 # Number of dispatched load instructions 694system.cpu0.iew.iewDispStoreInsts 7693096 # Number of dispatched store instructions 695system.cpu0.iew.iewDispNonSpecInsts 864933 # Number of dispatched non-speculative instructions 696system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall 697system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall 698system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations 699system.cpu0.iew.predictedTakenIncorrect 506933 # Number of branches that were predicted taken incorrectly 700system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly 701system.cpu0.iew.branchMispredicts 642785 # Number of branch mispredicts detected at execute 702system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions 703system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed 704system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute 705system.cpu0.iew.exec_swp 0 # number of swp insts executed 706system.cpu0.iew.exec_nop 173953 # number of nop insts executed 707system.cpu0.iew.exec_refs 50020846 # number of memory reference insts executed 708system.cpu0.iew.exec_branches 6431362 # Number of branches executed 709system.cpu0.iew.exec_stores 7171156 # Number of stores executed 710system.cpu0.iew.exec_rate 0.225691 # Inst execution rate 711system.cpu0.iew.wb_sent 79131384 # cumulative count of insts sent to commit 712system.cpu0.iew.wb_count 46670995 # cumulative count of insts written-back 713system.cpu0.iew.wb_producers 24791862 # num instructions producing a value 714system.cpu0.iew.wb_consumers 46093474 # num instructions consuming a value 715system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 716system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle 717system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back 718system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 719system.cpu0.commit.commitCommittedInsts 31935522 # The number of committed instructions 720system.cpu0.commit.commitCommittedOps 41923639 # The number of committed instructions 721system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit 722system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards 723system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted 724system.cpu0.commit.committed_per_cycle::samples 108046246 # Number of insts commited each cycle 725system.cpu0.commit.committed_per_cycle::mean 0.388016 # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::stdev 1.248887 # Number of insts commited each cycle 727system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 728system.cpu0.commit.committed_per_cycle::0 91022248 84.24% 84.24% # Number of insts commited each cycle 729system.cpu0.commit.committed_per_cycle::1 9317978 8.62% 92.87% # Number of insts commited each cycle 730system.cpu0.commit.committed_per_cycle::2 2446901 2.26% 95.13% # Number of insts commited each cycle 731system.cpu0.commit.committed_per_cycle::3 1345942 1.25% 96.38% # Number of insts commited each cycle 732system.cpu0.commit.committed_per_cycle::4 1037116 0.96% 97.34% # Number of insts commited each cycle 733system.cpu0.commit.committed_per_cycle::5 636722 0.59% 97.93% # Number of insts commited each cycle 734system.cpu0.commit.committed_per_cycle::6 665653 0.62% 98.54% # Number of insts commited each cycle 735system.cpu0.commit.committed_per_cycle::7 241447 0.22% 98.77% # Number of insts commited each cycle 736system.cpu0.commit.committed_per_cycle::8 1332239 1.23% 100.00% # Number of insts commited each cycle 737system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 738system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 739system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 740system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle 741system.cpu0.commit.committedInsts 31935522 # Number of instructions committed 742system.cpu0.commit.committedOps 41923639 # Number of ops (including micro ops) committed 743system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 744system.cpu0.commit.refs 15936098 # Number of memory references committed 745system.cpu0.commit.loads 9243307 # Number of loads committed 746system.cpu0.commit.membars 288653 # Number of memory barriers committed 747system.cpu0.commit.branches 5542289 # Number of branches committed 748system.cpu0.commit.fp_insts 4852 # Number of committed floating point instructions. 749system.cpu0.commit.int_insts 37169940 # Number of committed integer instructions. 750system.cpu0.commit.function_calls 620184 # Number of function calls committed. 751system.cpu0.commit.bw_lim_events 1332239 # number cycles where commit BW limit reached 752system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 753system.cpu0.rob.rob_reads 157931724 # The number of ROB reads 754system.cpu0.rob.rob_writes 106372981 # The number of ROB writes 755system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself 756system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling 757system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 758system.cpu0.committedInsts 31809695 # Number of Instructions Simulated 759system.cpu0.committedOps 41797812 # Number of Ops (including micro ops) Simulated 760system.cpu0.committedInsts_total 31809695 # Number of Instructions Simulated 761system.cpu0.cpi 11.081021 # CPI: Cycles Per Instruction 762system.cpu0.cpi_total 11.081021 # CPI: Total CPI of All Threads 763system.cpu0.ipc 0.090244 # IPC: Instructions Per Cycle 764system.cpu0.ipc_total 0.090244 # IPC: Total IPC of All Threads 765system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads 766system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes 767system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads 768system.cpu0.fp_regfile_writes 1336 # number of floating regfile writes 769system.cpu0.misc_regfile_reads 65704114 # number of misc regfile reads 770system.cpu0.misc_regfile_writes 635920 # number of misc regfile writes 771system.cpu0.icache.replacements 538787 # number of replacements 772system.cpu0.icache.tagsinuse 511.612990 # Cycle average of tags in use 773system.cpu0.icache.total_refs 5838964 # Total number of references to valid blocks. 774system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. 775system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. 776system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. 777system.cpu0.icache.occ_blocks::cpu0.inst 511.612990 # Average occupied blocks per requestor 778system.cpu0.icache.occ_percent::cpu0.inst 0.999244 # Average percentage of cache occupancy 779system.cpu0.icache.occ_percent::total 0.999244 # Average percentage of cache occupancy 780system.cpu0.icache.ReadReq_hits::cpu0.inst 5838964 # number of ReadReq hits 781system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits 782system.cpu0.icache.demand_hits::cpu0.inst 5838964 # number of demand (read+write) hits 783system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits 784system.cpu0.icache.overall_hits::cpu0.inst 5838964 # number of overall hits 785system.cpu0.icache.overall_hits::total 5838964 # number of overall hits 786system.cpu0.icache.ReadReq_misses::cpu0.inst 583385 # number of ReadReq misses 787system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses 788system.cpu0.icache.demand_misses::cpu0.inst 583385 # number of demand (read+write) misses 789system.cpu0.icache.demand_misses::total 583385 # number of demand (read+write) misses 790system.cpu0.icache.overall_misses::cpu0.inst 583385 # number of overall misses 791system.cpu0.icache.overall_misses::total 583385 # number of overall misses 792system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8740145988 # number of ReadReq miss cycles 793system.cpu0.icache.ReadReq_miss_latency::total 8740145988 # number of ReadReq miss cycles 794system.cpu0.icache.demand_miss_latency::cpu0.inst 8740145988 # number of demand (read+write) miss cycles 795system.cpu0.icache.demand_miss_latency::total 8740145988 # number of demand (read+write) miss cycles 796system.cpu0.icache.overall_miss_latency::cpu0.inst 8740145988 # number of overall miss cycles 797system.cpu0.icache.overall_miss_latency::total 8740145988 # number of overall miss cycles 798system.cpu0.icache.ReadReq_accesses::cpu0.inst 6422349 # number of ReadReq accesses(hits+misses) 799system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses) 800system.cpu0.icache.demand_accesses::cpu0.inst 6422349 # number of demand (read+write) accesses 801system.cpu0.icache.demand_accesses::total 6422349 # number of demand (read+write) accesses 802system.cpu0.icache.overall_accesses::cpu0.inst 6422349 # number of overall (read+write) accesses 803system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses 804system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090837 # miss rate for ReadReq accesses 805system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090837 # miss rate for demand accesses 806system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090837 # miss rate for overall accesses 807system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14981.780450 # average ReadReq miss latency 808system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency 809system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency 810system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked 811system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 812system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked 813system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 814system.cpu0.icache.avg_blocked_cycles::no_mshrs 6808.295833 # average number of cycles each access was blocked 815system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 816system.cpu0.icache.fast_writes 0 # number of fast writes performed 817system.cpu0.icache.cache_copies 0 # number of cache copies performed 818system.cpu0.icache.writebacks::writebacks 29665 # number of writebacks 819system.cpu0.icache.writebacks::total 29665 # number of writebacks 820system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44065 # number of ReadReq MSHR hits 821system.cpu0.icache.ReadReq_mshr_hits::total 44065 # number of ReadReq MSHR hits 822system.cpu0.icache.demand_mshr_hits::cpu0.inst 44065 # number of demand (read+write) MSHR hits 823system.cpu0.icache.demand_mshr_hits::total 44065 # number of demand (read+write) MSHR hits 824system.cpu0.icache.overall_mshr_hits::cpu0.inst 44065 # number of overall MSHR hits 825system.cpu0.icache.overall_mshr_hits::total 44065 # number of overall MSHR hits 826system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539320 # number of ReadReq MSHR misses 827system.cpu0.icache.ReadReq_mshr_misses::total 539320 # number of ReadReq MSHR misses 828system.cpu0.icache.demand_mshr_misses::cpu0.inst 539320 # number of demand (read+write) MSHR misses 829system.cpu0.icache.demand_mshr_misses::total 539320 # number of demand (read+write) MSHR misses 830system.cpu0.icache.overall_mshr_misses::cpu0.inst 539320 # number of overall MSHR misses 831system.cpu0.icache.overall_mshr_misses::total 539320 # number of overall MSHR misses 832system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6552239991 # number of ReadReq MSHR miss cycles 833system.cpu0.icache.ReadReq_mshr_miss_latency::total 6552239991 # number of ReadReq MSHR miss cycles 834system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6552239991 # number of demand (read+write) MSHR miss cycles 835system.cpu0.icache.demand_mshr_miss_latency::total 6552239991 # number of demand (read+write) MSHR miss cycles 836system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6552239991 # number of overall MSHR miss cycles 837system.cpu0.icache.overall_mshr_miss_latency::total 6552239991 # number of overall MSHR miss cycles 838system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6685500 # number of ReadReq MSHR uncacheable cycles 839system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6685500 # number of ReadReq MSHR uncacheable cycles 840system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6685500 # number of overall MSHR uncacheable cycles 841system.cpu0.icache.overall_mshr_uncacheable_latency::total 6685500 # number of overall MSHR uncacheable cycles 842system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for ReadReq accesses 843system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for demand accesses 844system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for overall accesses 845system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average ReadReq mshr miss latency 846system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency 847system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency 848system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 849system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 850system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 851system.cpu0.dcache.replacements 372182 # number of replacements 852system.cpu0.dcache.tagsinuse 487.992960 # Cycle average of tags in use 853system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks. 854system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks. 855system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks. 856system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. 857system.cpu0.dcache.occ_blocks::cpu0.data 487.992960 # Average occupied blocks per requestor 858system.cpu0.dcache.occ_percent::cpu0.data 0.953111 # Average percentage of cache occupancy 859system.cpu0.dcache.occ_percent::total 0.953111 # Average percentage of cache occupancy 860system.cpu0.dcache.ReadReq_hits::cpu0.data 7966835 # number of ReadReq hits 861system.cpu0.dcache.ReadReq_hits::total 7966835 # number of ReadReq hits 862system.cpu0.dcache.WriteReq_hits::cpu0.data 4346487 # number of WriteReq hits 863system.cpu0.dcache.WriteReq_hits::total 4346487 # number of WriteReq hits 864system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 221211 # number of LoadLockedReq hits 865system.cpu0.dcache.LoadLockedReq_hits::total 221211 # number of LoadLockedReq hits 866system.cpu0.dcache.StoreCondReq_hits::cpu0.data 199868 # number of StoreCondReq hits 867system.cpu0.dcache.StoreCondReq_hits::total 199868 # number of StoreCondReq hits 868system.cpu0.dcache.demand_hits::cpu0.data 12313322 # number of demand (read+write) hits 869system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits 870system.cpu0.dcache.overall_hits::cpu0.data 12313322 # number of overall hits 871system.cpu0.dcache.overall_hits::total 12313322 # number of overall hits 872system.cpu0.dcache.ReadReq_misses::cpu0.data 463412 # number of ReadReq misses 873system.cpu0.dcache.ReadReq_misses::total 463412 # number of ReadReq misses 874system.cpu0.dcache.WriteReq_misses::cpu0.data 1864293 # number of WriteReq misses 875system.cpu0.dcache.WriteReq_misses::total 1864293 # number of WriteReq misses 876system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10042 # number of LoadLockedReq misses 877system.cpu0.dcache.LoadLockedReq_misses::total 10042 # number of LoadLockedReq misses 878system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7686 # number of StoreCondReq misses 879system.cpu0.dcache.StoreCondReq_misses::total 7686 # number of StoreCondReq misses 880system.cpu0.dcache.demand_misses::cpu0.data 2327705 # number of demand (read+write) misses 881system.cpu0.dcache.demand_misses::total 2327705 # number of demand (read+write) misses 882system.cpu0.dcache.overall_misses::cpu0.data 2327705 # number of overall misses 883system.cpu0.dcache.overall_misses::total 2327705 # number of overall misses 884system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6478995500 # number of ReadReq miss cycles 885system.cpu0.dcache.ReadReq_miss_latency::total 6478995500 # number of ReadReq miss cycles 886system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 70420524827 # number of WriteReq miss cycles 887system.cpu0.dcache.WriteReq_miss_latency::total 70420524827 # number of WriteReq miss cycles 888system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 122158000 # number of LoadLockedReq miss cycles 889system.cpu0.dcache.LoadLockedReq_miss_latency::total 122158000 # number of LoadLockedReq miss cycles 890system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 87202500 # number of StoreCondReq miss cycles 891system.cpu0.dcache.StoreCondReq_miss_latency::total 87202500 # number of StoreCondReq miss cycles 892system.cpu0.dcache.demand_miss_latency::cpu0.data 76899520327 # number of demand (read+write) miss cycles 893system.cpu0.dcache.demand_miss_latency::total 76899520327 # number of demand (read+write) miss cycles 894system.cpu0.dcache.overall_miss_latency::cpu0.data 76899520327 # number of overall miss cycles 895system.cpu0.dcache.overall_miss_latency::total 76899520327 # number of overall miss cycles 896system.cpu0.dcache.ReadReq_accesses::cpu0.data 8430247 # number of ReadReq accesses(hits+misses) 897system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) 898system.cpu0.dcache.WriteReq_accesses::cpu0.data 6210780 # number of WriteReq accesses(hits+misses) 899system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) 900system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 231253 # number of LoadLockedReq accesses(hits+misses) 901system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) 902system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 207554 # number of StoreCondReq accesses(hits+misses) 903system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) 904system.cpu0.dcache.demand_accesses::cpu0.data 14641027 # number of demand (read+write) accesses 905system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses 906system.cpu0.dcache.overall_accesses::cpu0.data 14641027 # number of overall (read+write) accesses 907system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses 908system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.054970 # miss rate for ReadReq accesses 909system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.300171 # miss rate for WriteReq accesses 910system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.043424 # miss rate for LoadLockedReq accesses 911system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037031 # miss rate for StoreCondReq accesses 912system.cpu0.dcache.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses 913system.cpu0.dcache.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses 914system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13981.069761 # average ReadReq miss latency 915system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37773.313973 # average WriteReq miss latency 916system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12164.708225 # average LoadLockedReq miss latency 917system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11345.628415 # average StoreCondReq miss latency 918system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency 919system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency 920system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked 921system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked 922system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked 923system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked 924system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7939.679157 # average number of cycles each access was blocked 925system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked 926system.cpu0.dcache.fast_writes 0 # number of fast writes performed 927system.cpu0.dcache.cache_copies 0 # number of cache copies performed 928system.cpu0.dcache.writebacks::writebacks 327766 # number of writebacks 929system.cpu0.dcache.writebacks::total 327766 # number of writebacks 930system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223882 # number of ReadReq MSHR hits 931system.cpu0.dcache.ReadReq_mshr_hits::total 223882 # number of ReadReq MSHR hits 932system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1685987 # number of WriteReq MSHR hits 933system.cpu0.dcache.WriteReq_mshr_hits::total 1685987 # number of WriteReq MSHR hits 934system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 318 # number of LoadLockedReq MSHR hits 935system.cpu0.dcache.LoadLockedReq_mshr_hits::total 318 # number of LoadLockedReq MSHR hits 936system.cpu0.dcache.demand_mshr_hits::cpu0.data 1909869 # number of demand (read+write) MSHR hits 937system.cpu0.dcache.demand_mshr_hits::total 1909869 # number of demand (read+write) MSHR hits 938system.cpu0.dcache.overall_mshr_hits::cpu0.data 1909869 # number of overall MSHR hits 939system.cpu0.dcache.overall_mshr_hits::total 1909869 # number of overall MSHR hits 940system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 239530 # number of ReadReq MSHR misses 941system.cpu0.dcache.ReadReq_mshr_misses::total 239530 # number of ReadReq MSHR misses 942system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178306 # number of WriteReq MSHR misses 943system.cpu0.dcache.WriteReq_mshr_misses::total 178306 # number of WriteReq MSHR misses 944system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9724 # number of LoadLockedReq MSHR misses 945system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9724 # number of LoadLockedReq MSHR misses 946system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7685 # number of StoreCondReq MSHR misses 947system.cpu0.dcache.StoreCondReq_mshr_misses::total 7685 # number of StoreCondReq MSHR misses 948system.cpu0.dcache.demand_mshr_misses::cpu0.data 417836 # number of demand (read+write) MSHR misses 949system.cpu0.dcache.demand_mshr_misses::total 417836 # number of demand (read+write) MSHR misses 950system.cpu0.dcache.overall_mshr_misses::cpu0.data 417836 # number of overall MSHR misses 951system.cpu0.dcache.overall_mshr_misses::total 417836 # number of overall MSHR misses 952system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2943060000 # number of ReadReq MSHR miss cycles 953system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2943060000 # number of ReadReq MSHR miss cycles 954system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6370530485 # number of WriteReq MSHR miss cycles 955system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6370530485 # number of WriteReq MSHR miss cycles 956system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87975000 # number of LoadLockedReq MSHR miss cycles 957system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87975000 # number of LoadLockedReq MSHR miss cycles 958system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 64109000 # number of StoreCondReq MSHR miss cycles 959system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 64109000 # number of StoreCondReq MSHR miss cycles 960system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 961system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 962system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9313590485 # number of demand (read+write) MSHR miss cycles 963system.cpu0.dcache.demand_mshr_miss_latency::total 9313590485 # number of demand (read+write) MSHR miss cycles 964system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9313590485 # number of overall MSHR miss cycles 965system.cpu0.dcache.overall_mshr_miss_latency::total 9313590485 # number of overall MSHR miss cycles 966system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 138958680000 # number of ReadReq MSHR uncacheable cycles 967system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 138958680000 # number of ReadReq MSHR uncacheable cycles 968system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1038766498 # number of WriteReq MSHR uncacheable cycles 969system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1038766498 # number of WriteReq MSHR uncacheable cycles 970system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 139997446498 # number of overall MSHR uncacheable cycles 971system.cpu0.dcache.overall_mshr_uncacheable_latency::total 139997446498 # number of overall MSHR uncacheable cycles 972system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028413 # mshr miss rate for ReadReq accesses 973system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028709 # mshr miss rate for WriteReq accesses 974system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042049 # mshr miss rate for LoadLockedReq accesses 975system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037027 # mshr miss rate for StoreCondReq accesses 976system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for demand accesses 977system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for overall accesses 978system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12286.811673 # average ReadReq mshr miss latency 979system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35728.076930 # average WriteReq mshr miss latency 980system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9047.202797 # average LoadLockedReq mshr miss latency 981system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8342.094990 # average StoreCondReq mshr miss latency 982system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 983system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency 984system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency 985system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 986system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 987system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 988system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 989system.cpu1.dtb.inst_hits 0 # ITB inst hits 990system.cpu1.dtb.inst_misses 0 # ITB inst misses 991system.cpu1.dtb.read_hits 10576968 # DTB read hits 992system.cpu1.dtb.read_misses 41875 # DTB read misses 993system.cpu1.dtb.write_hits 5530754 # DTB write hits 994system.cpu1.dtb.write_misses 15302 # DTB write misses 995system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 996system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 997system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 998system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 999system.cpu1.dtb.flush_entries 1929 # Number of entries that have been flushed from TLB 1000system.cpu1.dtb.align_faults 3229 # Number of TLB faults due to alignment restrictions 1001system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch 1002system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1003system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions 1004system.cpu1.dtb.read_accesses 10618843 # DTB read accesses 1005system.cpu1.dtb.write_accesses 5546056 # DTB write accesses 1006system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1007system.cpu1.dtb.hits 16107722 # DTB hits 1008system.cpu1.dtb.misses 57177 # DTB misses 1009system.cpu1.dtb.accesses 16164899 # DTB accesses 1010system.cpu1.itb.inst_hits 8214514 # ITB inst hits 1011system.cpu1.itb.inst_misses 3039 # ITB inst misses 1012system.cpu1.itb.read_hits 0 # DTB read hits 1013system.cpu1.itb.read_misses 0 # DTB read misses 1014system.cpu1.itb.write_hits 0 # DTB write hits 1015system.cpu1.itb.write_misses 0 # DTB write misses 1016system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1017system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1018system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1019system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1020system.cpu1.itb.flush_entries 1364 # Number of entries that have been flushed from TLB 1021system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1022system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1023system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1024system.cpu1.itb.perms_faults 2090 # Number of TLB faults due to permissions restrictions 1025system.cpu1.itb.read_accesses 0 # DTB read accesses 1026system.cpu1.itb.write_accesses 0 # DTB write accesses 1027system.cpu1.itb.inst_accesses 8217553 # ITB inst accesses 1028system.cpu1.itb.hits 8214514 # DTB hits 1029system.cpu1.itb.misses 3039 # DTB misses 1030system.cpu1.itb.accesses 8217553 # DTB accesses 1031system.cpu1.numCycles 69079827 # number of cpu cycles simulated 1032system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1033system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1034system.cpu1.BPredUnit.lookups 8333886 # Number of BP lookups 1035system.cpu1.BPredUnit.condPredicted 6743827 # Number of conditional branches predicted 1036system.cpu1.BPredUnit.condIncorrect 503378 # Number of conditional branches incorrect 1037system.cpu1.BPredUnit.BTBLookups 7264644 # Number of BTB lookups 1038system.cpu1.BPredUnit.BTBHits 5697386 # Number of BTB hits 1039system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1040system.cpu1.BPredUnit.usedRAS 681249 # Number of times the RAS was used to get a target. 1041system.cpu1.BPredUnit.RASInCorrect 107003 # Number of incorrect RAS predictions. 1042system.cpu1.fetch.icacheStallCycles 17615974 # Number of cycles fetch is stalled on an Icache miss 1043system.cpu1.fetch.Insts 62597753 # Number of instructions fetch has processed 1044system.cpu1.fetch.Branches 8333886 # Number of branches that fetch encountered 1045system.cpu1.fetch.predictedBranches 6378635 # Number of branches that fetch has predicted taken 1046system.cpu1.fetch.Cycles 13915716 # Number of cycles fetch has run and was not squashing or blocked 1047system.cpu1.fetch.SquashCycles 4638538 # Number of cycles fetch has spent squashing 1048system.cpu1.fetch.TlbCycles 47230 # Number of cycles fetch has spent waiting for tlb 1049system.cpu1.fetch.BlockedCycles 15838358 # Number of cycles fetch has spent blocked 1050system.cpu1.fetch.MiscStallCycles 6458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1051system.cpu1.fetch.PendingTrapStallCycles 32444 # Number of stall cycles due to pending traps 1052system.cpu1.fetch.PendingQuiesceStallCycles 124703 # Number of stall cycles due to pending quiesce instructions 1053system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR 1054system.cpu1.fetch.CacheLines 8212062 # Number of cache lines fetched 1055system.cpu1.fetch.IcacheSquashes 760593 # Number of outstanding Icache misses that were squashed 1056system.cpu1.fetch.ItlbSquashes 1708 # Number of outstanding ITLB misses that were squashed 1057system.cpu1.fetch.rateDist::samples 50714542 # Number of instructions fetched each cycle (Total) 1058system.cpu1.fetch.rateDist::mean 1.493810 # Number of instructions fetched each cycle (Total) 1059system.cpu1.fetch.rateDist::stdev 2.745034 # Number of instructions fetched each cycle (Total) 1060system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1061system.cpu1.fetch.rateDist::0 36806671 72.58% 72.58% # Number of instructions fetched each cycle (Total) 1062system.cpu1.fetch.rateDist::1 703817 1.39% 73.96% # Number of instructions fetched each cycle (Total) 1063system.cpu1.fetch.rateDist::2 1220981 2.41% 76.37% # Number of instructions fetched each cycle (Total) 1064system.cpu1.fetch.rateDist::3 2510265 4.95% 81.32% # Number of instructions fetched each cycle (Total) 1065system.cpu1.fetch.rateDist::4 1144946 2.26% 83.58% # Number of instructions fetched each cycle (Total) 1066system.cpu1.fetch.rateDist::5 645263 1.27% 84.85% # Number of instructions fetched each cycle (Total) 1067system.cpu1.fetch.rateDist::6 1889491 3.73% 88.58% # Number of instructions fetched each cycle (Total) 1068system.cpu1.fetch.rateDist::7 406577 0.80% 89.38% # Number of instructions fetched each cycle (Total) 1069system.cpu1.fetch.rateDist::8 5386531 10.62% 100.00% # Number of instructions fetched each cycle (Total) 1070system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1071system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1072system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1073system.cpu1.fetch.rateDist::total 50714542 # Number of instructions fetched each cycle (Total) 1074system.cpu1.fetch.branchRate 0.120641 # Number of branch fetches per cycle 1075system.cpu1.fetch.rate 0.906165 # Number of inst fetches per cycle 1076system.cpu1.decode.IdleCycles 18659331 # Number of cycles decode is idle 1077system.cpu1.decode.BlockedCycles 16106637 # Number of cycles decode is blocked 1078system.cpu1.decode.RunCycles 12510231 # Number of cycles decode is running 1079system.cpu1.decode.UnblockCycles 383783 # Number of cycles decode is unblocking 1080system.cpu1.decode.SquashCycles 3054560 # Number of cycles decode is squashing 1081system.cpu1.decode.BranchResolved 1080138 # Number of times decode resolved a branch 1082system.cpu1.decode.BranchMispred 80287 # Number of times decode detected a branch misprediction 1083system.cpu1.decode.DecodedInsts 69798471 # Number of instructions handled by decode 1084system.cpu1.decode.SquashedInsts 258266 # Number of squashed instructions handled by decode 1085system.cpu1.rename.SquashCycles 3054560 # Number of cycles rename is squashing 1086system.cpu1.rename.IdleCycles 19806381 # Number of cycles rename is idle 1087system.cpu1.rename.BlockCycles 3656042 # Number of cycles rename is blocking 1088system.cpu1.rename.serializeStallCycles 10855578 # count of cycles rename stalled for serializing inst 1089system.cpu1.rename.RunCycles 11745212 # Number of cycles rename is running 1090system.cpu1.rename.UnblockCycles 1596769 # Number of cycles rename is unblocking 1091system.cpu1.rename.RenamedInsts 63854983 # Number of instructions processed by rename 1092system.cpu1.rename.ROBFullEvents 3125 # Number of times rename has blocked due to ROB full 1093system.cpu1.rename.IQFullEvents 323865 # Number of times rename has blocked due to IQ full 1094system.cpu1.rename.LSQFullEvents 877546 # Number of times rename has blocked due to LSQ full 1095system.cpu1.rename.FullRegisterEvents 38196 # Number of times there has been no free registers 1096system.cpu1.rename.RenamedOperands 68287616 # Number of destination operands rename has renamed 1097system.cpu1.rename.RenameLookups 296328670 # Number of register rename lookups that rename has made 1098system.cpu1.rename.int_rename_lookups 296276198 # Number of integer rename lookups 1099system.cpu1.rename.fp_rename_lookups 52472 # Number of floating rename lookups 1100system.cpu1.rename.CommittedMaps 39108035 # Number of HB maps that are committed 1101system.cpu1.rename.UndoneMaps 29179581 # Number of HB maps that are undone due to squashing 1102system.cpu1.rename.serializingInsts 433573 # count of serializing insts renamed 1103system.cpu1.rename.tempSerializingInsts 381926 # count of temporary serializing insts renamed 1104system.cpu1.rename.skidInsts 4171821 # count of insts added to the skid buffer 1105system.cpu1.memDep0.insertedLoads 11087265 # Number of loads inserted to the mem dependence unit. 1106system.cpu1.memDep0.insertedStores 7018828 # Number of stores inserted to the mem dependence unit. 1107system.cpu1.memDep0.conflictingLoads 641698 # Number of conflicting loads. 1108system.cpu1.memDep0.conflictingStores 916656 # Number of conflicting stores. 1109system.cpu1.iq.iqInstsAdded 56054776 # Number of instructions added to the IQ (excludes non-spec) 1110system.cpu1.iq.iqNonSpecInstsAdded 651703 # Number of non-speculative instructions added to the IQ 1111system.cpu1.iq.iqInstsIssued 50356280 # Number of instructions issued 1112system.cpu1.iq.iqSquashedInstsIssued 119136 # Number of squashed instructions issued 1113system.cpu1.iq.iqSquashedInstsExamined 18241893 # Number of squashed instructions iterated over during squash; mainly for profiling 1114system.cpu1.iq.iqSquashedOperandsExamined 52675305 # Number of squashed operands that are examined and possibly removed from graph 1115system.cpu1.iq.iqSquashedNonSpecRemoved 132202 # Number of squashed non-spec instructions that were removed 1116system.cpu1.iq.issued_per_cycle::samples 50714542 # Number of insts issued each cycle 1117system.cpu1.iq.issued_per_cycle::mean 0.992936 # Number of insts issued each cycle 1118system.cpu1.iq.issued_per_cycle::stdev 1.616562 # Number of insts issued each cycle 1119system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1120system.cpu1.iq.issued_per_cycle::0 32179059 63.45% 63.45% # Number of insts issued each cycle 1121system.cpu1.iq.issued_per_cycle::1 5535325 10.91% 74.37% # Number of insts issued each cycle 1122system.cpu1.iq.issued_per_cycle::2 3792419 7.48% 81.84% # Number of insts issued each cycle 1123system.cpu1.iq.issued_per_cycle::3 3611748 7.12% 88.97% # Number of insts issued each cycle 1124system.cpu1.iq.issued_per_cycle::4 2992147 5.90% 94.87% # Number of insts issued each cycle 1125system.cpu1.iq.issued_per_cycle::5 1532229 3.02% 97.89% # Number of insts issued each cycle 1126system.cpu1.iq.issued_per_cycle::6 792020 1.56% 99.45% # Number of insts issued each cycle 1127system.cpu1.iq.issued_per_cycle::7 217740 0.43% 99.88% # Number of insts issued each cycle 1128system.cpu1.iq.issued_per_cycle::8 61855 0.12% 100.00% # Number of insts issued each cycle 1129system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1130system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1131system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1132system.cpu1.iq.issued_per_cycle::total 50714542 # Number of insts issued each cycle 1133system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1134system.cpu1.iq.fu_full::IntAlu 15740 1.54% 1.54% # attempts to use FU when none available 1135system.cpu1.iq.fu_full::IntMult 1188 0.12% 1.66% # attempts to use FU when none available 1136system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available 1137system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available 1138system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available 1139system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available 1140system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available 1141system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available 1142system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available 1143system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available 1144system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available 1145system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available 1146system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available 1147system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available 1148system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available 1149system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available 1150system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available 1151system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available 1152system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available 1153system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available 1154system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available 1155system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available 1156system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available 1157system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available 1158system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available 1159system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available 1160system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available 1161system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available 1162system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available 1163system.cpu1.iq.fu_full::MemRead 747449 73.17% 74.83% # attempts to use FU when none available 1164system.cpu1.iq.fu_full::MemWrite 257163 25.17% 100.00% # attempts to use FU when none available 1165system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1166system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1167system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued 1168system.cpu1.iq.FU_type_0::IntAlu 32754833 65.05% 65.08% # Type of FU issued 1169system.cpu1.iq.FU_type_0::IntMult 50290 0.10% 65.18% # Type of FU issued 1170system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued 1171system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued 1172system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued 1173system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued 1174system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued 1175system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued 1176system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued 1177system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued 1178system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued 1179system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued 1180system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued 1181system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued 1182system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 65.18% # Type of FU issued 1183system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued 1184system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued 1185system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.18% # Type of FU issued 1186system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 65.18% # Type of FU issued 1187system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued 1188system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued 1189system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued 1190system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued 1191system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued 1192system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued 1193system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.18% # Type of FU issued 1194system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.18% # Type of FU issued 1195system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 65.18% # Type of FU issued 1196system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.18% # Type of FU issued 1197system.cpu1.iq.FU_type_0::MemRead 11616605 23.07% 88.25% # Type of FU issued 1198system.cpu1.iq.FU_type_0::MemWrite 5915163 11.75% 100.00% # Type of FU issued 1199system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1200system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1201system.cpu1.iq.FU_type_0::total 50356280 # Type of FU issued 1202system.cpu1.iq.rate 0.728958 # Inst issue rate 1203system.cpu1.iq.fu_busy_cnt 1021540 # FU busy when requested 1204system.cpu1.iq.fu_busy_rate 0.020286 # FU busy rate (busy events/executed inst) 1205system.cpu1.iq.int_inst_queue_reads 152611934 # Number of integer instruction queue reads 1206system.cpu1.iq.int_inst_queue_writes 74953147 # Number of integer instruction queue writes 1207system.cpu1.iq.int_inst_queue_wakeup_accesses 44267008 # Number of integer instruction queue wakeup accesses 1208system.cpu1.iq.fp_inst_queue_reads 12764 # Number of floating instruction queue reads 1209system.cpu1.iq.fp_inst_queue_writes 7028 # Number of floating instruction queue writes 1210system.cpu1.iq.fp_inst_queue_wakeup_accesses 5816 # Number of floating instruction queue wakeup accesses 1211system.cpu1.iq.int_alu_accesses 51352530 # Number of integer alu accesses 1212system.cpu1.iq.fp_alu_accesses 6668 # Number of floating point alu accesses 1213system.cpu1.iew.lsq.thread0.forwLoads 264404 # Number of loads that had data forwarded from stores 1214system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1215system.cpu1.iew.lsq.thread0.squashedLoads 3974504 # Number of loads squashed 1216system.cpu1.iew.lsq.thread0.ignoredResponses 7309 # Number of memory responses ignored because the instruction is squashed 1217system.cpu1.iew.lsq.thread0.memOrderViolation 12272 # Number of memory ordering violations 1218system.cpu1.iew.lsq.thread0.squashedStores 1480206 # Number of stores squashed 1219system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1220system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1221system.cpu1.iew.lsq.thread0.rescheduledLoads 1850099 # Number of loads that were rescheduled 1222system.cpu1.iew.lsq.thread0.cacheBlocked 1138705 # Number of times an access to memory failed due to the cache being blocked 1223system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1224system.cpu1.iew.iewSquashCycles 3054560 # Number of cycles IEW is squashing 1225system.cpu1.iew.iewBlockCycles 2510034 # Number of cycles IEW is blocking 1226system.cpu1.iew.iewUnblockCycles 71099 # Number of cycles IEW is unblocking 1227system.cpu1.iew.iewDispatchedInsts 56757065 # Number of instructions dispatched to IQ 1228system.cpu1.iew.iewDispSquashedInsts 253770 # Number of squashed instructions skipped by dispatch 1229system.cpu1.iew.iewDispLoadInsts 11087265 # Number of dispatched load instructions 1230system.cpu1.iew.iewDispStoreInsts 7018828 # Number of dispatched store instructions 1231system.cpu1.iew.iewDispNonSpecInsts 408322 # Number of dispatched non-speculative instructions 1232system.cpu1.iew.iewIQFullEvents 28335 # Number of times the IQ has become full, causing a stall 1233system.cpu1.iew.iewLSQFullEvents 3451 # Number of times the LSQ has become full, causing a stall 1234system.cpu1.iew.memOrderViolationEvents 12272 # Number of memory order violations 1235system.cpu1.iew.predictedTakenIncorrect 384395 # Number of branches that were predicted taken incorrectly 1236system.cpu1.iew.predictedNotTakenIncorrect 124639 # Number of branches that were predicted not taken incorrectly 1237system.cpu1.iew.branchMispredicts 509034 # Number of branch mispredicts detected at execute 1238system.cpu1.iew.iewExecutedInsts 47564456 # Number of executed instructions 1239system.cpu1.iew.iewExecLoadInsts 10848097 # Number of load instructions executed 1240system.cpu1.iew.iewExecSquashedInsts 2791824 # Number of squashed instructions skipped in execute 1241system.cpu1.iew.exec_swp 0 # number of swp insts executed 1242system.cpu1.iew.exec_nop 50586 # number of nop insts executed 1243system.cpu1.iew.exec_refs 16669887 # number of memory reference insts executed 1244system.cpu1.iew.exec_branches 5808702 # Number of branches executed 1245system.cpu1.iew.exec_stores 5821790 # Number of stores executed 1246system.cpu1.iew.exec_rate 0.688543 # Inst execution rate 1247system.cpu1.iew.wb_sent 46305936 # cumulative count of insts sent to commit 1248system.cpu1.iew.wb_count 44272824 # cumulative count of insts written-back 1249system.cpu1.iew.wb_producers 24255669 # num instructions producing a value 1250system.cpu1.iew.wb_consumers 44425528 # num instructions consuming a value 1251system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1252system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle 1253system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back 1254system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1255system.cpu1.commit.commitCommittedInsts 30036983 # The number of committed instructions 1256system.cpu1.commit.commitCommittedOps 38086237 # The number of committed instructions 1257system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit 1258system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards 1259system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted 1260system.cpu1.commit.committed_per_cycle::samples 47701192 # Number of insts commited each cycle 1261system.cpu1.commit.committed_per_cycle::mean 0.798434 # Number of insts commited each cycle 1262system.cpu1.commit.committed_per_cycle::stdev 1.833708 # Number of insts commited each cycle 1263system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1264system.cpu1.commit.committed_per_cycle::0 34720154 72.79% 72.79% # Number of insts commited each cycle 1265system.cpu1.commit.committed_per_cycle::1 6104752 12.80% 85.58% # Number of insts commited each cycle 1266system.cpu1.commit.committed_per_cycle::2 1842443 3.86% 89.45% # Number of insts commited each cycle 1267system.cpu1.commit.committed_per_cycle::3 962149 2.02% 91.46% # Number of insts commited each cycle 1268system.cpu1.commit.committed_per_cycle::4 825618 1.73% 93.19% # Number of insts commited each cycle 1269system.cpu1.commit.committed_per_cycle::5 737310 1.55% 94.74% # Number of insts commited each cycle 1270system.cpu1.commit.committed_per_cycle::6 600667 1.26% 96.00% # Number of insts commited each cycle 1271system.cpu1.commit.committed_per_cycle::7 447664 0.94% 96.94% # Number of insts commited each cycle 1272system.cpu1.commit.committed_per_cycle::8 1460435 3.06% 100.00% # Number of insts commited each cycle 1273system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1274system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1275system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1276system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle 1277system.cpu1.commit.committedInsts 30036983 # Number of instructions committed 1278system.cpu1.commit.committedOps 38086237 # Number of ops (including micro ops) committed 1279system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1280system.cpu1.commit.refs 12651383 # Number of memory references committed 1281system.cpu1.commit.loads 7112761 # Number of loads committed 1282system.cpu1.commit.membars 148646 # Number of memory barriers committed 1283system.cpu1.commit.branches 4805168 # Number of branches committed 1284system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. 1285system.cpu1.commit.int_insts 34028190 # Number of committed integer instructions. 1286system.cpu1.commit.function_calls 433251 # Number of function calls committed. 1287system.cpu1.commit.bw_lim_events 1460435 # number cycles where commit BW limit reached 1288system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1289system.cpu1.rob.rob_reads 102142645 # The number of ROB reads 1290system.cpu1.rob.rob_writes 116493771 # The number of ROB writes 1291system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself 1292system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling 1293system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1294system.cpu1.committedInsts 30012429 # Number of Instructions Simulated 1295system.cpu1.committedOps 38061683 # Number of Ops (including micro ops) Simulated 1296system.cpu1.committedInsts_total 30012429 # Number of Instructions Simulated 1297system.cpu1.cpi 2.301707 # CPI: Cycles Per Instruction 1298system.cpu1.cpi_total 2.301707 # CPI: Total CPI of All Threads 1299system.cpu1.ipc 0.434460 # IPC: Instructions Per Cycle 1300system.cpu1.ipc_total 0.434460 # IPC: Total IPC of All Threads 1301system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads 1302system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes 1303system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads 1304system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes 1305system.cpu1.misc_regfile_reads 77318861 # number of misc regfile reads 1306system.cpu1.misc_regfile_writes 323177 # number of misc regfile writes 1307system.cpu1.icache.replacements 485586 # number of replacements 1308system.cpu1.icache.tagsinuse 498.788681 # Cycle average of tags in use 1309system.cpu1.icache.total_refs 7684975 # Total number of references to valid blocks. 1310system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. 1311system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. 1312system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. 1313system.cpu1.icache.occ_blocks::cpu1.inst 498.788681 # Average occupied blocks per requestor 1314system.cpu1.icache.occ_percent::cpu1.inst 0.974197 # Average percentage of cache occupancy 1315system.cpu1.icache.occ_percent::total 0.974197 # Average percentage of cache occupancy 1316system.cpu1.icache.ReadReq_hits::cpu1.inst 7684975 # number of ReadReq hits 1317system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits 1318system.cpu1.icache.demand_hits::cpu1.inst 7684975 # number of demand (read+write) hits 1319system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits 1320system.cpu1.icache.overall_hits::cpu1.inst 7684975 # number of overall hits 1321system.cpu1.icache.overall_hits::total 7684975 # number of overall hits 1322system.cpu1.icache.ReadReq_misses::cpu1.inst 527035 # number of ReadReq misses 1323system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses 1324system.cpu1.icache.demand_misses::cpu1.inst 527035 # number of demand (read+write) misses 1325system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses 1326system.cpu1.icache.overall_misses::cpu1.inst 527035 # number of overall misses 1327system.cpu1.icache.overall_misses::total 527035 # number of overall misses 1328system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7752735997 # number of ReadReq miss cycles 1329system.cpu1.icache.ReadReq_miss_latency::total 7752735997 # number of ReadReq miss cycles 1330system.cpu1.icache.demand_miss_latency::cpu1.inst 7752735997 # number of demand (read+write) miss cycles 1331system.cpu1.icache.demand_miss_latency::total 7752735997 # number of demand (read+write) miss cycles 1332system.cpu1.icache.overall_miss_latency::cpu1.inst 7752735997 # number of overall miss cycles 1333system.cpu1.icache.overall_miss_latency::total 7752735997 # number of overall miss cycles 1334system.cpu1.icache.ReadReq_accesses::cpu1.inst 8212010 # number of ReadReq accesses(hits+misses) 1335system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) 1336system.cpu1.icache.demand_accesses::cpu1.inst 8212010 # number of demand (read+write) accesses 1337system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses 1338system.cpu1.icache.overall_accesses::cpu1.inst 8212010 # number of overall (read+write) accesses 1339system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses 1340system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.064179 # miss rate for ReadReq accesses 1341system.cpu1.icache.demand_miss_rate::cpu1.inst 0.064179 # miss rate for demand accesses 1342system.cpu1.icache.overall_miss_rate::cpu1.inst 0.064179 # miss rate for overall accesses 1343system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14710.097047 # average ReadReq miss latency 1344system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency 1345system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency 1346system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked 1347system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1348system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked 1349system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1350system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 # average number of cycles each access was blocked 1351system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1352system.cpu1.icache.fast_writes 0 # number of fast writes performed 1353system.cpu1.icache.cache_copies 0 # number of cache copies performed 1354system.cpu1.icache.writebacks::writebacks 18538 # number of writebacks 1355system.cpu1.icache.writebacks::total 18538 # number of writebacks 1356system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 40914 # number of ReadReq MSHR hits 1357system.cpu1.icache.ReadReq_mshr_hits::total 40914 # number of ReadReq MSHR hits 1358system.cpu1.icache.demand_mshr_hits::cpu1.inst 40914 # number of demand (read+write) MSHR hits 1359system.cpu1.icache.demand_mshr_hits::total 40914 # number of demand (read+write) MSHR hits 1360system.cpu1.icache.overall_mshr_hits::cpu1.inst 40914 # number of overall MSHR hits 1361system.cpu1.icache.overall_mshr_hits::total 40914 # number of overall MSHR hits 1362system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 486121 # number of ReadReq MSHR misses 1363system.cpu1.icache.ReadReq_mshr_misses::total 486121 # number of ReadReq MSHR misses 1364system.cpu1.icache.demand_mshr_misses::cpu1.inst 486121 # number of demand (read+write) MSHR misses 1365system.cpu1.icache.demand_mshr_misses::total 486121 # number of demand (read+write) MSHR misses 1366system.cpu1.icache.overall_mshr_misses::cpu1.inst 486121 # number of overall MSHR misses 1367system.cpu1.icache.overall_mshr_misses::total 486121 # number of overall MSHR misses 1368system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5799471497 # number of ReadReq MSHR miss cycles 1369system.cpu1.icache.ReadReq_mshr_miss_latency::total 5799471497 # number of ReadReq MSHR miss cycles 1370system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5799471497 # number of demand (read+write) MSHR miss cycles 1371system.cpu1.icache.demand_mshr_miss_latency::total 5799471497 # number of demand (read+write) MSHR miss cycles 1372system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5799471497 # number of overall MSHR miss cycles 1373system.cpu1.icache.overall_mshr_miss_latency::total 5799471497 # number of overall MSHR miss cycles 1374system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2517500 # number of ReadReq MSHR uncacheable cycles 1375system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2517500 # number of ReadReq MSHR uncacheable cycles 1376system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2517500 # number of overall MSHR uncacheable cycles 1377system.cpu1.icache.overall_mshr_uncacheable_latency::total 2517500 # number of overall MSHR uncacheable cycles 1378system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for ReadReq accesses 1379system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for demand accesses 1380system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for overall accesses 1381system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average ReadReq mshr miss latency 1382system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency 1383system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency 1384system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1385system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1386system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1387system.cpu1.dcache.replacements 272200 # number of replacements 1388system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use 1389system.cpu1.dcache.total_refs 10416163 # Total number of references to valid blocks. 1390system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. 1391system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. 1392system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. 1393system.cpu1.dcache.occ_blocks::cpu1.data 447.953212 # Average occupied blocks per requestor 1394system.cpu1.dcache.occ_percent::cpu1.data 0.874909 # Average percentage of cache occupancy 1395system.cpu1.dcache.occ_percent::total 0.874909 # Average percentage of cache occupancy 1396system.cpu1.dcache.ReadReq_hits::cpu1.data 7085363 # number of ReadReq hits 1397system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits 1398system.cpu1.dcache.WriteReq_hits::cpu1.data 3139669 # number of WriteReq hits 1399system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits 1400system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75360 # number of LoadLockedReq hits 1401system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits 1402system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72622 # number of StoreCondReq hits 1403system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits 1404system.cpu1.dcache.demand_hits::cpu1.data 10225032 # number of demand (read+write) hits 1405system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits 1406system.cpu1.dcache.overall_hits::cpu1.data 10225032 # number of overall hits 1407system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits 1408system.cpu1.dcache.ReadReq_misses::cpu1.data 323287 # number of ReadReq misses 1409system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses 1410system.cpu1.dcache.WriteReq_misses::cpu1.data 1273508 # number of WriteReq misses 1411system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses 1412system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12669 # number of LoadLockedReq misses 1413system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses 1414system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11046 # number of StoreCondReq misses 1415system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses 1416system.cpu1.dcache.demand_misses::cpu1.data 1596795 # number of demand (read+write) misses 1417system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses 1418system.cpu1.dcache.overall_misses::cpu1.data 1596795 # number of overall misses 1419system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses 1420system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5044696500 # number of ReadReq miss cycles 1421system.cpu1.dcache.ReadReq_miss_latency::total 5044696500 # number of ReadReq miss cycles 1422system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 46343696337 # number of WriteReq miss cycles 1423system.cpu1.dcache.WriteReq_miss_latency::total 46343696337 # number of WriteReq miss cycles 1424system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 148164500 # number of LoadLockedReq miss cycles 1425system.cpu1.dcache.LoadLockedReq_miss_latency::total 148164500 # number of LoadLockedReq miss cycles 1426system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87512500 # number of StoreCondReq miss cycles 1427system.cpu1.dcache.StoreCondReq_miss_latency::total 87512500 # number of StoreCondReq miss cycles 1428system.cpu1.dcache.demand_miss_latency::cpu1.data 51388392837 # number of demand (read+write) miss cycles 1429system.cpu1.dcache.demand_miss_latency::total 51388392837 # number of demand (read+write) miss cycles 1430system.cpu1.dcache.overall_miss_latency::cpu1.data 51388392837 # number of overall miss cycles 1431system.cpu1.dcache.overall_miss_latency::total 51388392837 # number of overall miss cycles 1432system.cpu1.dcache.ReadReq_accesses::cpu1.data 7408650 # number of ReadReq accesses(hits+misses) 1433system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses) 1434system.cpu1.dcache.WriteReq_accesses::cpu1.data 4413177 # number of WriteReq accesses(hits+misses) 1435system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses) 1436system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 88029 # number of LoadLockedReq accesses(hits+misses) 1437system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses) 1438system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83668 # number of StoreCondReq accesses(hits+misses) 1439system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses) 1440system.cpu1.dcache.demand_accesses::cpu1.data 11821827 # number of demand (read+write) accesses 1441system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses 1442system.cpu1.dcache.overall_accesses::cpu1.data 11821827 # number of overall (read+write) accesses 1443system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses 1444system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.043636 # miss rate for ReadReq accesses 1445system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.288569 # miss rate for WriteReq accesses 1446system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.143918 # miss rate for LoadLockedReq accesses 1447system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.132022 # miss rate for StoreCondReq accesses 1448system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135072 # miss rate for demand accesses 1449system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135072 # miss rate for overall accesses 1450system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.390217 # average ReadReq miss latency 1451system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36390.581243 # average WriteReq miss latency 1452system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11695.043018 # average LoadLockedReq miss latency 1453system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7922.551150 # average StoreCondReq miss latency 1454system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency 1455system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency 1456system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked 1457system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked 1458system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked 1459system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked 1460system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4235.796880 # average number of cycles each access was blocked 1461system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked 1462system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1463system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1464system.cpu1.dcache.writebacks::writebacks 223077 # number of writebacks 1465system.cpu1.dcache.writebacks::total 223077 # number of writebacks 1466system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 133946 # number of ReadReq MSHR hits 1467system.cpu1.dcache.ReadReq_mshr_hits::total 133946 # number of ReadReq MSHR hits 1468system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1157260 # number of WriteReq MSHR hits 1469system.cpu1.dcache.WriteReq_mshr_hits::total 1157260 # number of WriteReq MSHR hits 1470system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1008 # number of LoadLockedReq MSHR hits 1471system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1008 # number of LoadLockedReq MSHR hits 1472system.cpu1.dcache.demand_mshr_hits::cpu1.data 1291206 # number of demand (read+write) MSHR hits 1473system.cpu1.dcache.demand_mshr_hits::total 1291206 # number of demand (read+write) MSHR hits 1474system.cpu1.dcache.overall_mshr_hits::cpu1.data 1291206 # number of overall MSHR hits 1475system.cpu1.dcache.overall_mshr_hits::total 1291206 # number of overall MSHR hits 1476system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189341 # number of ReadReq MSHR misses 1477system.cpu1.dcache.ReadReq_mshr_misses::total 189341 # number of ReadReq MSHR misses 1478system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 116248 # number of WriteReq MSHR misses 1479system.cpu1.dcache.WriteReq_mshr_misses::total 116248 # number of WriteReq MSHR misses 1480system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11661 # number of LoadLockedReq MSHR misses 1481system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11661 # number of LoadLockedReq MSHR misses 1482system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 11046 # number of StoreCondReq MSHR misses 1483system.cpu1.dcache.StoreCondReq_mshr_misses::total 11046 # number of StoreCondReq MSHR misses 1484system.cpu1.dcache.demand_mshr_misses::cpu1.data 305589 # number of demand (read+write) MSHR misses 1485system.cpu1.dcache.demand_mshr_misses::total 305589 # number of demand (read+write) MSHR misses 1486system.cpu1.dcache.overall_mshr_misses::cpu1.data 305589 # number of overall MSHR misses 1487system.cpu1.dcache.overall_mshr_misses::total 305589 # number of overall MSHR misses 1488system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2489937000 # number of ReadReq MSHR miss cycles 1489system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2489937000 # number of ReadReq MSHR miss cycles 1490system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3452864547 # number of WriteReq MSHR miss cycles 1491system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3452864547 # number of WriteReq MSHR miss cycles 1492system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99179500 # number of LoadLockedReq MSHR miss cycles 1493system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99179500 # number of LoadLockedReq MSHR miss cycles 1494system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54297000 # number of StoreCondReq MSHR miss cycles 1495system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54297000 # number of StoreCondReq MSHR miss cycles 1496system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5942801547 # number of demand (read+write) MSHR miss cycles 1497system.cpu1.dcache.demand_mshr_miss_latency::total 5942801547 # number of demand (read+write) MSHR miss cycles 1498system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5942801547 # number of overall MSHR miss cycles 1499system.cpu1.dcache.overall_mshr_miss_latency::total 5942801547 # number of overall MSHR miss cycles 1500system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 8455613500 # number of ReadReq MSHR uncacheable cycles 1501system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 8455613500 # number of ReadReq MSHR uncacheable cycles 1502system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41497603581 # number of WriteReq MSHR uncacheable cycles 1503system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41497603581 # number of WriteReq MSHR uncacheable cycles 1504system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 49953217081 # number of overall MSHR uncacheable cycles 1505system.cpu1.dcache.overall_mshr_uncacheable_latency::total 49953217081 # number of overall MSHR uncacheable cycles 1506system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025557 # mshr miss rate for ReadReq accesses 1507system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026341 # mshr miss rate for WriteReq accesses 1508system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132468 # mshr miss rate for LoadLockedReq accesses 1509system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.132022 # mshr miss rate for StoreCondReq accesses 1510system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for demand accesses 1511system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for overall accesses 1512system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.543200 # average ReadReq mshr miss latency 1513system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29702.571631 # average WriteReq mshr miss latency 1514system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8505.231112 # average LoadLockedReq mshr miss latency 1515system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4915.535035 # average StoreCondReq mshr miss latency 1516system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency 1517system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency 1518system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1519system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1520system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1521system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1522system.iocache.replacements 0 # number of replacements 1523system.iocache.tagsinuse 0 # Cycle average of tags in use 1524system.iocache.total_refs 0 # Total number of references to valid blocks. 1525system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1526system.iocache.avg_refs no_value # Average number of references to valid blocks. 1527system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1528system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1529system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1530system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1531system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1532system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1533system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1534system.iocache.fast_writes 0 # number of fast writes performed 1535system.iocache.cache_copies 0 # number of cache copies performed 1536system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of ReadReq MSHR uncacheable cycles 1537system.iocache.ReadReq_mshr_uncacheable_latency::total 1308174844926 # number of ReadReq MSHR uncacheable cycles 1538system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of overall MSHR uncacheable cycles 1539system.iocache.overall_mshr_uncacheable_latency::total 1308174844926 # number of overall MSHR uncacheable cycles 1540system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1541system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1542system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1543system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1544system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed 1545system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1546system.cpu1.kern.inst.quiesce 41930 # number of quiesce instructions executed 1547 1548---------- End Simulation Statistics ---------- 1549