stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.582494 # Number of seconds simulated 4sim_ticks 2582494395500 # Number of ticks simulated 5final_tick 2582494395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 77486 # Simulator instruction rate (inst/s) 8host_tick_rate 2505663009 # Simulator tick rate (ticks/s) 9host_mem_usage 386072 # Number of bytes of host memory used 10host_seconds 1030.66 # Real time elapsed on the host 11sim_insts 79862069 # Number of instructions simulated 12system.nvmem.bytes_read 384 # Number of bytes read from this memory 13system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory 14system.nvmem.bytes_written 0 # Number of bytes written to this memory 15system.nvmem.num_reads 6 # Number of read requests responded to by this memory 16system.nvmem.num_writes 0 # Number of write requests responded to by this memory 17system.nvmem.num_other 0 # Number of other requests responded to by this memory 18system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) 19system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) 20system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) 21system.physmem.bytes_read 131490980 # Number of bytes read from this memory 22system.physmem.bytes_inst_read 1177856 # Number of instructions bytes read from this memory 23system.physmem.bytes_written 10251344 # Number of bytes written to this memory 24system.physmem.num_reads 15129077 # Number of read requests responded to by this memory 25system.physmem.num_writes 870131 # Number of write requests responded to by this memory 26system.physmem.num_other 0 # Number of other requests responded to by this memory 27system.physmem.bw_read 50916269 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read 456092 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_write 3969551 # Write bandwidth from this memory (bytes/s) 30system.physmem.bw_total 54885821 # Total bandwidth to/from this memory (bytes/s) 31system.l2c.replacements 132200 # number of replacements 32system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use 33system.l2c.total_refs 1817822 # Total number of references to valid blocks. 34system.l2c.sampled_refs 162144 # Sample count of references to valid blocks. 35system.l2c.avg_refs 11.211158 # Average number of references to valid blocks. 36system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 37system.l2c.occ_blocks::0 5000.897751 # Average occupied blocks per context 38system.l2c.occ_blocks::1 7176.831699 # Average occupied blocks per context 39system.l2c.occ_blocks::2 15405.259775 # Average occupied blocks per context 40system.l2c.occ_percent::0 0.076308 # Average percentage of cache occupancy 41system.l2c.occ_percent::1 0.109510 # Average percentage of cache occupancy 42system.l2c.occ_percent::2 0.235066 # Average percentage of cache occupancy 43system.l2c.ReadReq_hits::0 738573 # number of ReadReq hits 44system.l2c.ReadReq_hits::1 628212 # number of ReadReq hits 45system.l2c.ReadReq_hits::2 178875 # number of ReadReq hits 46system.l2c.ReadReq_hits::total 1545660 # number of ReadReq hits 47system.l2c.Writeback_hits::0 598786 # number of Writeback hits 48system.l2c.Writeback_hits::total 598786 # number of Writeback hits 49system.l2c.UpgradeReq_hits::0 1039 # number of UpgradeReq hits 50system.l2c.UpgradeReq_hits::1 1048 # number of UpgradeReq hits 51system.l2c.UpgradeReq_hits::total 2087 # number of UpgradeReq hits 52system.l2c.SCUpgradeReq_hits::0 175 # number of SCUpgradeReq hits 53system.l2c.SCUpgradeReq_hits::1 451 # number of SCUpgradeReq hits 54system.l2c.SCUpgradeReq_hits::total 626 # number of SCUpgradeReq hits 55system.l2c.ReadExReq_hits::0 58347 # number of ReadExReq hits 56system.l2c.ReadExReq_hits::1 39083 # number of ReadExReq hits 57system.l2c.ReadExReq_hits::total 97430 # number of ReadExReq hits 58system.l2c.demand_hits::0 796920 # number of demand (read+write) hits 59system.l2c.demand_hits::1 667295 # number of demand (read+write) hits 60system.l2c.demand_hits::2 178875 # number of demand (read+write) hits 61system.l2c.demand_hits::total 1643090 # number of demand (read+write) hits 62system.l2c.overall_hits::0 796920 # number of overall hits 63system.l2c.overall_hits::1 667295 # number of overall hits 64system.l2c.overall_hits::2 178875 # number of overall hits 65system.l2c.overall_hits::total 1643090 # number of overall hits 66system.l2c.ReadReq_misses::0 19694 # number of ReadReq misses 67system.l2c.ReadReq_misses::1 20569 # number of ReadReq misses 68system.l2c.ReadReq_misses::2 168 # number of ReadReq misses 69system.l2c.ReadReq_misses::total 40431 # number of ReadReq misses 70system.l2c.UpgradeReq_misses::0 7390 # number of UpgradeReq misses 71system.l2c.UpgradeReq_misses::1 3840 # number of UpgradeReq misses 72system.l2c.UpgradeReq_misses::total 11230 # number of UpgradeReq misses 73system.l2c.SCUpgradeReq_misses::0 864 # number of SCUpgradeReq misses 74system.l2c.SCUpgradeReq_misses::1 454 # number of SCUpgradeReq misses 75system.l2c.SCUpgradeReq_misses::total 1318 # number of SCUpgradeReq misses 76system.l2c.ReadExReq_misses::0 97999 # number of ReadExReq misses 77system.l2c.ReadExReq_misses::1 50217 # number of ReadExReq misses 78system.l2c.ReadExReq_misses::total 148216 # number of ReadExReq misses 79system.l2c.demand_misses::0 117693 # number of demand (read+write) misses 80system.l2c.demand_misses::1 70786 # number of demand (read+write) misses 81system.l2c.demand_misses::2 168 # number of demand (read+write) misses 82system.l2c.demand_misses::total 188647 # number of demand (read+write) misses 83system.l2c.overall_misses::0 117693 # number of overall misses 84system.l2c.overall_misses::1 70786 # number of overall misses 85system.l2c.overall_misses::2 168 # number of overall misses 86system.l2c.overall_misses::total 188647 # number of overall misses 87system.l2c.ReadReq_miss_latency 2112279500 # number of ReadReq miss cycles 88system.l2c.UpgradeReq_miss_latency 61500500 # number of UpgradeReq miss cycles 89system.l2c.SCUpgradeReq_miss_latency 8037000 # number of SCUpgradeReq miss cycles 90system.l2c.ReadExReq_miss_latency 7780237999 # number of ReadExReq miss cycles 91system.l2c.demand_miss_latency 9892517499 # number of demand (read+write) miss cycles 92system.l2c.overall_miss_latency 9892517499 # number of overall miss cycles 93system.l2c.ReadReq_accesses::0 758267 # number of ReadReq accesses(hits+misses) 94system.l2c.ReadReq_accesses::1 648781 # number of ReadReq accesses(hits+misses) 95system.l2c.ReadReq_accesses::2 179043 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::total 1586091 # number of ReadReq accesses(hits+misses) 97system.l2c.Writeback_accesses::0 598786 # number of Writeback accesses(hits+misses) 98system.l2c.Writeback_accesses::total 598786 # number of Writeback accesses(hits+misses) 99system.l2c.UpgradeReq_accesses::0 8429 # number of UpgradeReq accesses(hits+misses) 100system.l2c.UpgradeReq_accesses::1 4888 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 13317 # number of UpgradeReq accesses(hits+misses) 102system.l2c.SCUpgradeReq_accesses::0 1039 # number of SCUpgradeReq accesses(hits+misses) 103system.l2c.SCUpgradeReq_accesses::1 905 # number of SCUpgradeReq accesses(hits+misses) 104system.l2c.SCUpgradeReq_accesses::total 1944 # number of SCUpgradeReq accesses(hits+misses) 105system.l2c.ReadExReq_accesses::0 156346 # number of ReadExReq accesses(hits+misses) 106system.l2c.ReadExReq_accesses::1 89300 # number of ReadExReq accesses(hits+misses) 107system.l2c.ReadExReq_accesses::total 245646 # number of ReadExReq accesses(hits+misses) 108system.l2c.demand_accesses::0 914613 # number of demand (read+write) accesses 109system.l2c.demand_accesses::1 738081 # number of demand (read+write) accesses 110system.l2c.demand_accesses::2 179043 # number of demand (read+write) accesses 111system.l2c.demand_accesses::total 1831737 # number of demand (read+write) accesses 112system.l2c.overall_accesses::0 914613 # number of overall (read+write) accesses 113system.l2c.overall_accesses::1 738081 # number of overall (read+write) accesses 114system.l2c.overall_accesses::2 179043 # number of overall (read+write) accesses 115system.l2c.overall_accesses::total 1831737 # number of overall (read+write) accesses 116system.l2c.ReadReq_miss_rate::0 0.025972 # miss rate for ReadReq accesses 117system.l2c.ReadReq_miss_rate::1 0.031704 # miss rate for ReadReq accesses 118system.l2c.ReadReq_miss_rate::2 0.000938 # miss rate for ReadReq accesses 119system.l2c.ReadReq_miss_rate::total 0.058615 # miss rate for ReadReq accesses 120system.l2c.UpgradeReq_miss_rate::0 0.876735 # miss rate for UpgradeReq accesses 121system.l2c.UpgradeReq_miss_rate::1 0.785597 # miss rate for UpgradeReq accesses 122system.l2c.SCUpgradeReq_miss_rate::0 0.831569 # miss rate for SCUpgradeReq accesses 123system.l2c.SCUpgradeReq_miss_rate::1 0.501657 # miss rate for SCUpgradeReq accesses 124system.l2c.ReadExReq_miss_rate::0 0.626808 # miss rate for ReadExReq accesses 125system.l2c.ReadExReq_miss_rate::1 0.562340 # miss rate for ReadExReq accesses 126system.l2c.demand_miss_rate::0 0.128681 # miss rate for demand accesses 127system.l2c.demand_miss_rate::1 0.095905 # miss rate for demand accesses 128system.l2c.demand_miss_rate::2 0.000938 # miss rate for demand accesses 129system.l2c.demand_miss_rate::total 0.225524 # miss rate for demand accesses 130system.l2c.overall_miss_rate::0 0.128681 # miss rate for overall accesses 131system.l2c.overall_miss_rate::1 0.095905 # miss rate for overall accesses 132system.l2c.overall_miss_rate::2 0.000938 # miss rate for overall accesses 133system.l2c.overall_miss_rate::total 0.225524 # miss rate for overall accesses 134system.l2c.ReadReq_avg_miss_latency::0 107254.976135 # average ReadReq miss latency 135system.l2c.ReadReq_avg_miss_latency::1 102692.376878 # average ReadReq miss latency 136system.l2c.ReadReq_avg_miss_latency::2 12573092.261905 # average ReadReq miss latency 137system.l2c.ReadReq_avg_miss_latency::total 12783039.614917 # average ReadReq miss latency 138system.l2c.UpgradeReq_avg_miss_latency::0 8322.124493 # average UpgradeReq miss latency 139system.l2c.UpgradeReq_avg_miss_latency::1 16015.755208 # average UpgradeReq miss latency 140system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency 141system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 142system.l2c.SCUpgradeReq_avg_miss_latency::0 9302.083333 # average SCUpgradeReq miss latency 143system.l2c.SCUpgradeReq_avg_miss_latency::1 17702.643172 # average SCUpgradeReq miss latency 144system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency 145system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency 146system.l2c.ReadExReq_avg_miss_latency::0 79390.993775 # average ReadExReq miss latency 147system.l2c.ReadExReq_avg_miss_latency::1 154932.353566 # average ReadExReq miss latency 148system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency 149system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 150system.l2c.demand_avg_miss_latency::0 84053.575820 # average overall miss latency 151system.l2c.demand_avg_miss_latency::1 139752.458099 # average overall miss latency 152system.l2c.demand_avg_miss_latency::2 58884032.732143 # average overall miss latency 153system.l2c.demand_avg_miss_latency::total 59107838.766062 # average overall miss latency 154system.l2c.overall_avg_miss_latency::0 84053.575820 # average overall miss latency 155system.l2c.overall_avg_miss_latency::1 139752.458099 # average overall miss latency 156system.l2c.overall_avg_miss_latency::2 58884032.732143 # average overall miss latency 157system.l2c.overall_avg_miss_latency::total 59107838.766062 # average overall miss latency 158system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 159system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 160system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 161system.l2c.blocked::no_targets 0 # number of cycles access was blocked 162system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 163system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 164system.l2c.fast_writes 0 # number of fast writes performed 165system.l2c.cache_copies 0 # number of cache copies performed 166system.l2c.writebacks 112847 # number of writebacks 167system.l2c.ReadReq_mshr_hits 98 # number of ReadReq MSHR hits 168system.l2c.demand_mshr_hits 98 # number of demand (read+write) MSHR hits 169system.l2c.overall_mshr_hits 98 # number of overall MSHR hits 170system.l2c.ReadReq_mshr_misses 40333 # number of ReadReq MSHR misses 171system.l2c.UpgradeReq_mshr_misses 11230 # number of UpgradeReq MSHR misses 172system.l2c.SCUpgradeReq_mshr_misses 1318 # number of SCUpgradeReq MSHR misses 173system.l2c.ReadExReq_mshr_misses 148216 # number of ReadExReq MSHR misses 174system.l2c.demand_mshr_misses 188549 # number of demand (read+write) MSHR misses 175system.l2c.overall_mshr_misses 188549 # number of overall MSHR misses 176system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 177system.l2c.ReadReq_mshr_miss_latency 1616144000 # number of ReadReq MSHR miss cycles 178system.l2c.UpgradeReq_mshr_miss_latency 449664000 # number of UpgradeReq MSHR miss cycles 179system.l2c.SCUpgradeReq_mshr_miss_latency 52753500 # number of SCUpgradeReq MSHR miss cycles 180system.l2c.ReadExReq_mshr_miss_latency 5939088499 # number of ReadExReq MSHR miss cycles 181system.l2c.demand_mshr_miss_latency 7555232499 # number of demand (read+write) MSHR miss cycles 182system.l2c.overall_mshr_miss_latency 7555232499 # number of overall MSHR miss cycles 183system.l2c.ReadReq_mshr_uncacheable_latency 131965191500 # number of ReadReq MSHR uncacheable cycles 184system.l2c.WriteReq_mshr_uncacheable_latency 32542078084 # number of WriteReq MSHR uncacheable cycles 185system.l2c.overall_mshr_uncacheable_latency 164507269584 # number of overall MSHR uncacheable cycles 186system.l2c.ReadReq_mshr_miss_rate::0 0.053191 # mshr miss rate for ReadReq accesses 187system.l2c.ReadReq_mshr_miss_rate::1 0.062167 # mshr miss rate for ReadReq accesses 188system.l2c.ReadReq_mshr_miss_rate::2 0.225270 # mshr miss rate for ReadReq accesses 189system.l2c.ReadReq_mshr_miss_rate::total 0.340628 # mshr miss rate for ReadReq accesses 190system.l2c.UpgradeReq_mshr_miss_rate::0 1.332305 # mshr miss rate for UpgradeReq accesses 191system.l2c.UpgradeReq_mshr_miss_rate::1 2.297463 # mshr miss rate for UpgradeReq accesses 192system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses 193system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 194system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.268527 # mshr miss rate for SCUpgradeReq accesses 195system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456354 # mshr miss rate for SCUpgradeReq accesses 196system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses 197system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses 198system.l2c.ReadExReq_mshr_miss_rate::0 0.948000 # mshr miss rate for ReadExReq accesses 199system.l2c.ReadExReq_mshr_miss_rate::1 1.659754 # mshr miss rate for ReadExReq accesses 200system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses 201system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 202system.l2c.demand_mshr_miss_rate::0 0.206152 # mshr miss rate for demand accesses 203system.l2c.demand_mshr_miss_rate::1 0.255458 # mshr miss rate for demand accesses 204system.l2c.demand_mshr_miss_rate::2 1.053093 # mshr miss rate for demand accesses 205system.l2c.demand_mshr_miss_rate::total 1.514703 # mshr miss rate for demand accesses 206system.l2c.overall_mshr_miss_rate::0 0.206152 # mshr miss rate for overall accesses 207system.l2c.overall_mshr_miss_rate::1 0.255458 # mshr miss rate for overall accesses 208system.l2c.overall_mshr_miss_rate::2 1.053093 # mshr miss rate for overall accesses 209system.l2c.overall_mshr_miss_rate::total 1.514703 # mshr miss rate for overall accesses 210system.l2c.ReadReq_avg_mshr_miss_latency 40070.017108 # average ReadReq mshr miss latency 211system.l2c.UpgradeReq_avg_mshr_miss_latency 40041.317898 # average UpgradeReq mshr miss latency 212system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40025.417299 # average SCUpgradeReq mshr miss latency 213system.l2c.ReadExReq_avg_mshr_miss_latency 40070.495082 # average ReadExReq mshr miss latency 214system.l2c.demand_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency 215system.l2c.overall_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency 216system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 217system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 218system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 219system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 220system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 221system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 222system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 223system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 224system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 225system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 226system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 227system.cf0.dma_write_txs 0 # Number of DMA write transactions. 228system.cpu0.dtb.inst_hits 0 # ITB inst hits 229system.cpu0.dtb.inst_misses 0 # ITB inst misses 230system.cpu0.dtb.read_hits 42404013 # DTB read hits 231system.cpu0.dtb.read_misses 55271 # DTB read misses 232system.cpu0.dtb.write_hits 6896316 # DTB write hits 233system.cpu0.dtb.write_misses 11117 # DTB write misses 234system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 235system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 236system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 237system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 238system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB 239system.cpu0.dtb.align_faults 10190 # Number of TLB faults due to alignment restrictions 240system.cpu0.dtb.prefetch_faults 580 # Number of TLB faults due to prefetch 241system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 242system.cpu0.dtb.perms_faults 1489 # Number of TLB faults due to permissions restrictions 243system.cpu0.dtb.read_accesses 42459284 # DTB read accesses 244system.cpu0.dtb.write_accesses 6907433 # DTB write accesses 245system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 246system.cpu0.dtb.hits 49300329 # DTB hits 247system.cpu0.dtb.misses 66388 # DTB misses 248system.cpu0.dtb.accesses 49366717 # DTB accesses 249system.cpu0.itb.inst_hits 6430047 # ITB inst hits 250system.cpu0.itb.inst_misses 17344 # ITB inst misses 251system.cpu0.itb.read_hits 0 # DTB read hits 252system.cpu0.itb.read_misses 0 # DTB read misses 253system.cpu0.itb.write_hits 0 # DTB write hits 254system.cpu0.itb.write_misses 0 # DTB write misses 255system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 256system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 257system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 258system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 259system.cpu0.itb.flush_entries 1577 # Number of entries that have been flushed from TLB 260system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 261system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 262system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 263system.cpu0.itb.perms_faults 5810 # Number of TLB faults due to permissions restrictions 264system.cpu0.itb.read_accesses 0 # DTB read accesses 265system.cpu0.itb.write_accesses 0 # DTB write accesses 266system.cpu0.itb.inst_accesses 6447391 # ITB inst accesses 267system.cpu0.itb.hits 6430047 # DTB hits 268system.cpu0.itb.misses 17344 # DTB misses 269system.cpu0.itb.accesses 6447391 # DTB accesses 270system.cpu0.numCycles 352464224 # number of cpu cycles simulated 271system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 273system.cpu0.BPredUnit.lookups 8639262 # Number of BP lookups 274system.cpu0.BPredUnit.condPredicted 6396113 # Number of conditional branches predicted 275system.cpu0.BPredUnit.condIncorrect 634960 # Number of conditional branches incorrect 276system.cpu0.BPredUnit.BTBLookups 7354016 # Number of BTB lookups 277system.cpu0.BPredUnit.BTBHits 5046946 # Number of BTB hits 278system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 279system.cpu0.BPredUnit.usedRAS 806008 # Number of times the RAS was used to get a target. 280system.cpu0.BPredUnit.RASInCorrect 135144 # Number of incorrect RAS predictions. 281system.cpu0.fetch.icacheStallCycles 16864575 # Number of cycles fetch is stalled on an Icache miss 282system.cpu0.fetch.Insts 45911459 # Number of instructions fetch has processed 283system.cpu0.fetch.Branches 8639262 # Number of branches that fetch encountered 284system.cpu0.fetch.predictedBranches 5852954 # Number of branches that fetch has predicted taken 285system.cpu0.fetch.Cycles 11507352 # Number of cycles fetch has run and was not squashing or blocked 286system.cpu0.fetch.SquashCycles 2656909 # Number of cycles fetch has spent squashing 287system.cpu0.fetch.TlbCycles 105092 # Number of cycles fetch has spent waiting for tlb 288system.cpu0.fetch.BlockedCycles 79183942 # Number of cycles fetch has spent blocked 289system.cpu0.fetch.MiscStallCycles 2005 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 290system.cpu0.fetch.PendingTrapStallCycles 114543 # Number of stall cycles due to pending traps 291system.cpu0.fetch.PendingQuiesceStallCycles 115021 # Number of stall cycles due to pending quiesce instructions 292system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR 293system.cpu0.fetch.CacheLines 6424056 # Number of cache lines fetched 294system.cpu0.fetch.IcacheSquashes 290090 # Number of outstanding Icache misses that were squashed 295system.cpu0.fetch.ItlbSquashes 8736 # Number of outstanding ITLB misses that were squashed 296system.cpu0.fetch.rateDist::samples 109741052 # Number of instructions fetched each cycle (Total) 297system.cpu0.fetch.rateDist::mean 0.540842 # Number of instructions fetched each cycle (Total) 298system.cpu0.fetch.rateDist::stdev 1.794710 # Number of instructions fetched each cycle (Total) 299system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 300system.cpu0.fetch.rateDist::0 98251365 89.53% 89.53% # Number of instructions fetched each cycle (Total) 301system.cpu0.fetch.rateDist::1 1141553 1.04% 90.57% # Number of instructions fetched each cycle (Total) 302system.cpu0.fetch.rateDist::2 1483062 1.35% 91.92% # Number of instructions fetched each cycle (Total) 303system.cpu0.fetch.rateDist::3 1305311 1.19% 93.11% # Number of instructions fetched each cycle (Total) 304system.cpu0.fetch.rateDist::4 1111109 1.01% 94.12% # Number of instructions fetched each cycle (Total) 305system.cpu0.fetch.rateDist::5 877492 0.80% 94.92% # Number of instructions fetched each cycle (Total) 306system.cpu0.fetch.rateDist::6 783730 0.71% 95.64% # Number of instructions fetched each cycle (Total) 307system.cpu0.fetch.rateDist::7 504789 0.46% 96.10% # Number of instructions fetched each cycle (Total) 308system.cpu0.fetch.rateDist::8 4282641 3.90% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 312system.cpu0.fetch.rateDist::total 109741052 # Number of instructions fetched each cycle (Total) 313system.cpu0.fetch.branchRate 0.024511 # Number of branch fetches per cycle 314system.cpu0.fetch.rate 0.130258 # Number of inst fetches per cycle 315system.cpu0.decode.IdleCycles 18015904 # Number of cycles decode is idle 316system.cpu0.decode.BlockedCycles 78867966 # Number of cycles decode is blocked 317system.cpu0.decode.RunCycles 10351735 # Number of cycles decode is running 318system.cpu0.decode.UnblockCycles 744902 # Number of cycles decode is unblocking 319system.cpu0.decode.SquashCycles 1760545 # Number of cycles decode is squashing 320system.cpu0.decode.BranchResolved 1349765 # Number of times decode resolved a branch 321system.cpu0.decode.BranchMispred 89024 # Number of times decode detected a branch misprediction 322system.cpu0.decode.DecodedInsts 56859019 # Number of instructions handled by decode 323system.cpu0.decode.SquashedInsts 296865 # Number of squashed instructions handled by decode 324system.cpu0.rename.SquashCycles 1760545 # Number of cycles rename is squashing 325system.cpu0.rename.IdleCycles 19077781 # Number of cycles rename is idle 326system.cpu0.rename.BlockCycles 33324855 # Number of cycles rename is blocking 327system.cpu0.rename.serializeStallCycles 41068350 # count of cycles rename stalled for serializing inst 328system.cpu0.rename.RunCycles 10047301 # Number of cycles rename is running 329system.cpu0.rename.UnblockCycles 4462220 # Number of cycles rename is unblocking 330system.cpu0.rename.RenamedInsts 54490886 # Number of instructions processed by rename 331system.cpu0.rename.ROBFullEvents 1483 # Number of times rename has blocked due to ROB full 332system.cpu0.rename.IQFullEvents 580883 # Number of times rename has blocked due to IQ full 333system.cpu0.rename.LSQFullEvents 3149232 # Number of times rename has blocked due to LSQ full 334system.cpu0.rename.FullRegisterEvents 205 # Number of times there has been no free registers 335system.cpu0.rename.RenamedOperands 54779837 # Number of destination operands rename has renamed 336system.cpu0.rename.RenameLookups 247536349 # Number of register rename lookups that rename has made 337system.cpu0.rename.int_rename_lookups 247487579 # Number of integer rename lookups 338system.cpu0.rename.fp_rename_lookups 48770 # Number of floating rename lookups 339system.cpu0.rename.CommittedMaps 41441157 # Number of HB maps that are committed 340system.cpu0.rename.UndoneMaps 13338679 # Number of HB maps that are undone due to squashing 341system.cpu0.rename.serializingInsts 828868 # count of serializing insts renamed 342system.cpu0.rename.tempSerializingInsts 763855 # count of temporary serializing insts renamed 343system.cpu0.rename.skidInsts 8500592 # count of insts added to the skid buffer 344system.cpu0.memDep0.insertedLoads 11770384 # Number of loads inserted to the mem dependence unit. 345system.cpu0.memDep0.insertedStores 7686805 # Number of stores inserted to the mem dependence unit. 346system.cpu0.memDep0.conflictingLoads 1443183 # Number of conflicting loads. 347system.cpu0.memDep0.conflictingStores 1570137 # Number of conflicting stores. 348system.cpu0.iq.iqInstsAdded 50961905 # Number of instructions added to the IQ (excludes non-spec) 349system.cpu0.iq.iqNonSpecInstsAdded 1297752 # Number of non-speculative instructions added to the IQ 350system.cpu0.iq.iqInstsIssued 80276174 # Number of instructions issued 351system.cpu0.iq.iqSquashedInstsIssued 137636 # Number of squashed instructions issued 352system.cpu0.iq.iqSquashedInstsExamined 9888896 # Number of squashed instructions iterated over during squash; mainly for profiling 353system.cpu0.iq.iqSquashedOperandsExamined 22816025 # Number of squashed operands that are examined and possibly removed from graph 354system.cpu0.iq.iqSquashedNonSpecRemoved 253324 # Number of squashed non-spec instructions that were removed 355system.cpu0.iq.issued_per_cycle::samples 109741052 # Number of insts issued each cycle 356system.cpu0.iq.issued_per_cycle::mean 0.731505 # Number of insts issued each cycle 357system.cpu0.iq.issued_per_cycle::stdev 1.440076 # Number of insts issued each cycle 358system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 359system.cpu0.iq.issued_per_cycle::0 80125799 73.01% 73.01% # Number of insts issued each cycle 360system.cpu0.iq.issued_per_cycle::1 10111373 9.21% 82.23% # Number of insts issued each cycle 361system.cpu0.iq.issued_per_cycle::2 4133530 3.77% 85.99% # Number of insts issued each cycle 362system.cpu0.iq.issued_per_cycle::3 3177611 2.90% 88.89% # Number of insts issued each cycle 363system.cpu0.iq.issued_per_cycle::4 9954078 9.07% 97.96% # Number of insts issued each cycle 364system.cpu0.iq.issued_per_cycle::5 1265279 1.15% 99.11% # Number of insts issued each cycle 365system.cpu0.iq.issued_per_cycle::6 670333 0.61% 99.72% # Number of insts issued each cycle 366system.cpu0.iq.issued_per_cycle::7 224189 0.20% 99.93% # Number of insts issued each cycle 367system.cpu0.iq.issued_per_cycle::8 78860 0.07% 100.00% # Number of insts issued each cycle 368system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 369system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 370system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 371system.cpu0.iq.issued_per_cycle::total 109741052 # Number of insts issued each cycle 372system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 373system.cpu0.iq.fu_full::IntAlu 37808 0.47% 0.47% # attempts to use FU when none available 374system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available 375system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available 376system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available 377system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available 378system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.48% # attempts to use FU when none available 379system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.48% # attempts to use FU when none available 380system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.48% # attempts to use FU when none available 381system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.48% # attempts to use FU when none available 382system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.48% # attempts to use FU when none available 383system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.48% # attempts to use FU when none available 384system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.48% # attempts to use FU when none available 385system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.48% # attempts to use FU when none available 386system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.48% # attempts to use FU when none available 387system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.48% # attempts to use FU when none available 388system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.48% # attempts to use FU when none available 389system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.48% # attempts to use FU when none available 390system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.48% # attempts to use FU when none available 391system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.48% # attempts to use FU when none available 392system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.48% # attempts to use FU when none available 393system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.48% # attempts to use FU when none available 394system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.48% # attempts to use FU when none available 395system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.48% # attempts to use FU when none available 396system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.48% # attempts to use FU when none available 397system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.48% # attempts to use FU when none available 398system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # attempts to use FU when none available 399system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available 400system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available 401system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available 402system.cpu0.iq.fu_full::MemRead 7704393 95.96% 96.44% # attempts to use FU when none available 403system.cpu0.iq.fu_full::MemWrite 285533 3.56% 100.00% # attempts to use FU when none available 404system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 406system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued 407system.cpu0.iq.FU_type_0::IntAlu 29731481 37.04% 37.15% # Type of FU issued 408system.cpu0.iq.FU_type_0::IntMult 62351 0.08% 37.22% # Type of FU issued 409system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.22% # Type of FU issued 410system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.22% # Type of FU issued 411system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.22% # Type of FU issued 412system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.22% # Type of FU issued 413system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.22% # Type of FU issued 414system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.22% # Type of FU issued 415system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.22% # Type of FU issued 416system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.22% # Type of FU issued 417system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.22% # Type of FU issued 418system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.22% # Type of FU issued 419system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.22% # Type of FU issued 420system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.22% # Type of FU issued 421system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 37.22% # Type of FU issued 422system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.22% # Type of FU issued 423system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.22% # Type of FU issued 424system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.22% # Type of FU issued 425system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.22% # Type of FU issued 426system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.22% # Type of FU issued 427system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.22% # Type of FU issued 428system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.22% # Type of FU issued 429system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.22% # Type of FU issued 430system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.22% # Type of FU issued 431system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.22% # Type of FU issued 432system.cpu0.iq.FU_type_0::SimdFloatMisc 1694 0.00% 37.23% # Type of FU issued 433system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.23% # Type of FU issued 434system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 37.23% # Type of FU issued 435system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.23% # Type of FU issued 436system.cpu0.iq.FU_type_0::MemRead 43135014 53.73% 90.96% # Type of FU issued 437system.cpu0.iq.FU_type_0::MemWrite 7257159 9.04% 100.00% # Type of FU issued 438system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 439system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 440system.cpu0.iq.FU_type_0::total 80276174 # Type of FU issued 441system.cpu0.iq.rate 0.227757 # Inst issue rate 442system.cpu0.iq.fu_busy_cnt 8028360 # FU busy when requested 443system.cpu0.iq.fu_busy_rate 0.100009 # FU busy rate (busy events/executed inst) 444system.cpu0.iq.int_inst_queue_reads 278513864 # Number of integer instruction queue reads 445system.cpu0.iq.int_inst_queue_writes 62161443 # Number of integer instruction queue writes 446system.cpu0.iq.int_inst_queue_wakeup_accesses 46668615 # Number of integer instruction queue wakeup accesses 447system.cpu0.iq.fp_inst_queue_reads 11568 # Number of floating instruction queue reads 448system.cpu0.iq.fp_inst_queue_writes 6980 # Number of floating instruction queue writes 449system.cpu0.iq.fp_inst_queue_wakeup_accesses 5172 # Number of floating instruction queue wakeup accesses 450system.cpu0.iq.int_alu_accesses 88210042 # Number of integer alu accesses 451system.cpu0.iq.fp_alu_accesses 6031 # Number of floating point alu accesses 452system.cpu0.iew.lsq.thread0.forwLoads 399886 # Number of loads that had data forwarded from stores 453system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 454system.cpu0.iew.lsq.thread0.squashedLoads 2526229 # Number of loads squashed 455system.cpu0.iew.lsq.thread0.ignoredResponses 5188 # Number of memory responses ignored because the instruction is squashed 456system.cpu0.iew.lsq.thread0.memOrderViolation 20554 # Number of memory ordering violations 457system.cpu0.iew.lsq.thread0.squashedStores 993550 # Number of stores squashed 458system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 459system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 460system.cpu0.iew.lsq.thread0.rescheduledLoads 32220160 # Number of loads that were rescheduled 461system.cpu0.iew.lsq.thread0.cacheBlocked 13300 # Number of times an access to memory failed due to the cache being blocked 462system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 463system.cpu0.iew.iewSquashCycles 1760545 # Number of cycles IEW is squashing 464system.cpu0.iew.iewBlockCycles 25952608 # Number of cycles IEW is blocking 465system.cpu0.iew.iewUnblockCycles 355602 # Number of cycles IEW is unblocking 466system.cpu0.iew.iewDispatchedInsts 52433539 # Number of instructions dispatched to IQ 467system.cpu0.iew.iewDispSquashedInsts 243567 # Number of squashed instructions skipped by dispatch 468system.cpu0.iew.iewDispLoadInsts 11770384 # Number of dispatched load instructions 469system.cpu0.iew.iewDispStoreInsts 7686805 # Number of dispatched store instructions 470system.cpu0.iew.iewDispNonSpecInsts 865740 # Number of dispatched non-speculative instructions 471system.cpu0.iew.iewIQFullEvents 62160 # Number of times the IQ has become full, causing a stall 472system.cpu0.iew.iewLSQFullEvents 5553 # Number of times the LSQ has become full, causing a stall 473system.cpu0.iew.memOrderViolationEvents 20554 # Number of memory order violations 474system.cpu0.iew.predictedTakenIncorrect 507509 # Number of branches that were predicted taken incorrectly 475system.cpu0.iew.predictedNotTakenIncorrect 136100 # Number of branches that were predicted not taken incorrectly 476system.cpu0.iew.branchMispredicts 643609 # Number of branch mispredicts detected at execute 477system.cpu0.iew.iewExecutedInsts 79551295 # Number of executed instructions 478system.cpu0.iew.iewExecLoadInsts 42843907 # Number of load instructions executed 479system.cpu0.iew.iewExecSquashedInsts 724879 # Number of squashed instructions skipped in execute 480system.cpu0.iew.exec_swp 0 # number of swp insts executed 481system.cpu0.iew.exec_nop 173882 # number of nop insts executed 482system.cpu0.iew.exec_refs 50011427 # number of memory reference insts executed 483system.cpu0.iew.exec_branches 6433542 # Number of branches executed 484system.cpu0.iew.exec_stores 7167520 # Number of stores executed 485system.cpu0.iew.exec_rate 0.225700 # Inst execution rate 486system.cpu0.iew.wb_sent 79133797 # cumulative count of insts sent to commit 487system.cpu0.iew.wb_count 46673787 # cumulative count of insts written-back 488system.cpu0.iew.wb_producers 24793926 # num instructions producing a value 489system.cpu0.iew.wb_consumers 46078393 # num instructions consuming a value 490system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 491system.cpu0.iew.wb_rate 0.132421 # insts written-back per cycle 492system.cpu0.iew.wb_fanout 0.538081 # average fanout of values written-back 493system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 494system.cpu0.commit.commitCommittedInsts 41927345 # The number of committed instructions 495system.cpu0.commit.commitSquashedInsts 10365163 # The number of squashed insts skipped by commit 496system.cpu0.commit.commitNonSpecStalls 1044428 # The number of times commit has been forced to stall to communicate backwards 497system.cpu0.commit.branchMispredicts 567784 # The number of times a branch was mispredicted 498system.cpu0.commit.committed_per_cycle::samples 108024119 # Number of insts commited each cycle 499system.cpu0.commit.committed_per_cycle::mean 0.388129 # Number of insts commited each cycle 500system.cpu0.commit.committed_per_cycle::stdev 1.248779 # Number of insts commited each cycle 501system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 502system.cpu0.commit.committed_per_cycle::0 90994296 84.24% 84.24% # Number of insts commited each cycle 503system.cpu0.commit.committed_per_cycle::1 9318293 8.63% 92.86% # Number of insts commited each cycle 504system.cpu0.commit.committed_per_cycle::2 2453548 2.27% 95.13% # Number of insts commited each cycle 505system.cpu0.commit.committed_per_cycle::3 1344047 1.24% 96.38% # Number of insts commited each cycle 506system.cpu0.commit.committed_per_cycle::4 1036100 0.96% 97.34% # Number of insts commited each cycle 507system.cpu0.commit.committed_per_cycle::5 648919 0.60% 97.94% # Number of insts commited each cycle 508system.cpu0.commit.committed_per_cycle::6 654404 0.61% 98.54% # Number of insts commited each cycle 509system.cpu0.commit.committed_per_cycle::7 241700 0.22% 98.77% # Number of insts commited each cycle 510system.cpu0.commit.committed_per_cycle::8 1332812 1.23% 100.00% # Number of insts commited each cycle 511system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 512system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 513system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 514system.cpu0.commit.committed_per_cycle::total 108024119 # Number of insts commited each cycle 515system.cpu0.commit.count 41927345 # Number of instructions committed 516system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 517system.cpu0.commit.refs 15937410 # Number of memory references committed 518system.cpu0.commit.loads 9244155 # Number of loads committed 519system.cpu0.commit.membars 288635 # Number of memory barriers committed 520system.cpu0.commit.branches 5542672 # Number of branches committed 521system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. 522system.cpu0.commit.int_insts 37173454 # Number of committed integer instructions. 523system.cpu0.commit.function_calls 620264 # Number of function calls committed. 524system.cpu0.commit.bw_lim_events 1332812 # number cycles where commit BW limit reached 525system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 526system.cpu0.rob.rob_reads 157900366 # The number of ROB reads 527system.cpu0.rob.rob_writes 106355397 # The number of ROB writes 528system.cpu0.timesIdled 1453890 # Number of times that the entire CPU went into an idle state and unscheduled itself 529system.cpu0.idleCycles 242723172 # Total number of cycles that the CPU has spent unscheduled due to idling 530system.cpu0.quiesceCycles 4812468828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 531system.cpu0.committedInsts 41801518 # Number of Instructions Simulated 532system.cpu0.committedInsts_total 41801518 # Number of Instructions Simulated 533system.cpu0.cpi 8.431852 # CPI: Cycles Per Instruction 534system.cpu0.cpi_total 8.431852 # CPI: Total CPI of All Threads 535system.cpu0.ipc 0.118598 # IPC: Instructions Per Cycle 536system.cpu0.ipc_total 0.118598 # IPC: Total IPC of All Threads 537system.cpu0.int_regfile_reads 354175079 # number of integer regfile reads 538system.cpu0.int_regfile_writes 46137251 # number of integer regfile writes 539system.cpu0.fp_regfile_reads 4205 # number of floating regfile reads 540system.cpu0.fp_regfile_writes 1348 # number of floating regfile writes 541system.cpu0.misc_regfile_reads 65629786 # number of misc regfile reads 542system.cpu0.misc_regfile_writes 635954 # number of misc regfile writes 543system.cpu0.icache.replacements 539173 # number of replacements 544system.cpu0.icache.tagsinuse 511.623608 # Cycle average of tags in use 545system.cpu0.icache.total_refs 5839899 # Total number of references to valid blocks. 546system.cpu0.icache.sampled_refs 539685 # Sample count of references to valid blocks. 547system.cpu0.icache.avg_refs 10.820940 # Average number of references to valid blocks. 548system.cpu0.icache.warmup_cycle 16020223000 # Cycle when the warmup percentage was hit. 549system.cpu0.icache.occ_blocks::0 511.623608 # Average occupied blocks per context 550system.cpu0.icache.occ_percent::0 0.999265 # Average percentage of cache occupancy 551system.cpu0.icache.ReadReq_hits::0 5839899 # number of ReadReq hits 552system.cpu0.icache.ReadReq_hits::total 5839899 # number of ReadReq hits 553system.cpu0.icache.demand_hits::0 5839899 # number of demand (read+write) hits 554system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits 555system.cpu0.icache.demand_hits::total 5839899 # number of demand (read+write) hits 556system.cpu0.icache.overall_hits::0 5839899 # number of overall hits 557system.cpu0.icache.overall_hits::1 0 # number of overall hits 558system.cpu0.icache.overall_hits::total 5839899 # number of overall hits 559system.cpu0.icache.ReadReq_misses::0 584029 # number of ReadReq misses 560system.cpu0.icache.ReadReq_misses::total 584029 # number of ReadReq misses 561system.cpu0.icache.demand_misses::0 584029 # number of demand (read+write) misses 562system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses 563system.cpu0.icache.demand_misses::total 584029 # number of demand (read+write) misses 564system.cpu0.icache.overall_misses::0 584029 # number of overall misses 565system.cpu0.icache.overall_misses::1 0 # number of overall misses 566system.cpu0.icache.overall_misses::total 584029 # number of overall misses 567system.cpu0.icache.ReadReq_miss_latency 8742056490 # number of ReadReq miss cycles 568system.cpu0.icache.demand_miss_latency 8742056490 # number of demand (read+write) miss cycles 569system.cpu0.icache.overall_miss_latency 8742056490 # number of overall miss cycles 570system.cpu0.icache.ReadReq_accesses::0 6423928 # number of ReadReq accesses(hits+misses) 571system.cpu0.icache.ReadReq_accesses::total 6423928 # number of ReadReq accesses(hits+misses) 572system.cpu0.icache.demand_accesses::0 6423928 # number of demand (read+write) accesses 573system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses 574system.cpu0.icache.demand_accesses::total 6423928 # number of demand (read+write) accesses 575system.cpu0.icache.overall_accesses::0 6423928 # number of overall (read+write) accesses 576system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses 577system.cpu0.icache.overall_accesses::total 6423928 # number of overall (read+write) accesses 578system.cpu0.icache.ReadReq_miss_rate::0 0.090915 # miss rate for ReadReq accesses 579system.cpu0.icache.demand_miss_rate::0 0.090915 # miss rate for demand accesses 580system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 581system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses 582system.cpu0.icache.overall_miss_rate::0 0.090915 # miss rate for overall accesses 583system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 584system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses 585system.cpu0.icache.ReadReq_avg_miss_latency::0 14968.531511 # average ReadReq miss latency 586system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 587system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 588system.cpu0.icache.demand_avg_miss_latency::0 14968.531511 # average overall miss latency 589system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency 590system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency 591system.cpu0.icache.overall_avg_miss_latency::0 14968.531511 # average overall miss latency 592system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency 593system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency 594system.cpu0.icache.blocked_cycles::no_mshrs 1586493 # number of cycles access was blocked 595system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 596system.cpu0.icache.blocked::no_mshrs 210 # number of cycles access was blocked 597system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 598system.cpu0.icache.avg_blocked_cycles::no_mshrs 7554.728571 # average number of cycles each access was blocked 599system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 600system.cpu0.icache.fast_writes 0 # number of fast writes performed 601system.cpu0.icache.cache_copies 0 # number of cache copies performed 602system.cpu0.icache.writebacks 29902 # number of writebacks 603system.cpu0.icache.ReadReq_mshr_hits 44323 # number of ReadReq MSHR hits 604system.cpu0.icache.demand_mshr_hits 44323 # number of demand (read+write) MSHR hits 605system.cpu0.icache.overall_mshr_hits 44323 # number of overall MSHR hits 606system.cpu0.icache.ReadReq_mshr_misses 539706 # number of ReadReq MSHR misses 607system.cpu0.icache.demand_mshr_misses 539706 # number of demand (read+write) MSHR misses 608system.cpu0.icache.overall_mshr_misses 539706 # number of overall MSHR misses 609system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 610system.cpu0.icache.ReadReq_mshr_miss_latency 6552393493 # number of ReadReq MSHR miss cycles 611system.cpu0.icache.demand_mshr_miss_latency 6552393493 # number of demand (read+write) MSHR miss cycles 612system.cpu0.icache.overall_mshr_miss_latency 6552393493 # number of overall MSHR miss cycles 613system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles 614system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles 615system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084015 # mshr miss rate for ReadReq accesses 616system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 617system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 618system.cpu0.icache.demand_mshr_miss_rate::0 0.084015 # mshr miss rate for demand accesses 619system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 620system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 621system.cpu0.icache.overall_mshr_miss_rate::0 0.084015 # mshr miss rate for overall accesses 622system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 623system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 624system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12140.671945 # average ReadReq mshr miss latency 625system.cpu0.icache.demand_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency 626system.cpu0.icache.overall_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency 627system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 628system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 629system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 630system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 631system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 632system.cpu0.dcache.replacements 372215 # number of replacements 633system.cpu0.dcache.tagsinuse 487.071305 # Cycle average of tags in use 634system.cpu0.dcache.total_refs 12774859 # Total number of references to valid blocks. 635system.cpu0.dcache.sampled_refs 372727 # Sample count of references to valid blocks. 636system.cpu0.dcache.avg_refs 34.274037 # Average number of references to valid blocks. 637system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. 638system.cpu0.dcache.occ_blocks::0 487.071305 # Average occupied blocks per context 639system.cpu0.dcache.occ_percent::0 0.951311 # Average percentage of cache occupancy 640system.cpu0.dcache.ReadReq_hits::0 7959466 # number of ReadReq hits 641system.cpu0.dcache.ReadReq_hits::total 7959466 # number of ReadReq hits 642system.cpu0.dcache.WriteReq_hits::0 4347928 # number of WriteReq hits 643system.cpu0.dcache.WriteReq_hits::total 4347928 # number of WriteReq hits 644system.cpu0.dcache.LoadLockedReq_hits::0 221270 # number of LoadLockedReq hits 645system.cpu0.dcache.LoadLockedReq_hits::total 221270 # number of LoadLockedReq hits 646system.cpu0.dcache.StoreCondReq_hits::0 199751 # number of StoreCondReq hits 647system.cpu0.dcache.StoreCondReq_hits::total 199751 # number of StoreCondReq hits 648system.cpu0.dcache.demand_hits::0 12307394 # number of demand (read+write) hits 649system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits 650system.cpu0.dcache.demand_hits::total 12307394 # number of demand (read+write) hits 651system.cpu0.dcache.overall_hits::0 12307394 # number of overall hits 652system.cpu0.dcache.overall_hits::1 0 # number of overall hits 653system.cpu0.dcache.overall_hits::total 12307394 # number of overall hits 654system.cpu0.dcache.ReadReq_misses::0 462880 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 462880 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::0 1863380 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 1863380 # number of WriteReq misses 658system.cpu0.dcache.LoadLockedReq_misses::0 9956 # number of LoadLockedReq misses 659system.cpu0.dcache.LoadLockedReq_misses::total 9956 # number of LoadLockedReq misses 660system.cpu0.dcache.StoreCondReq_misses::0 7770 # number of StoreCondReq misses 661system.cpu0.dcache.StoreCondReq_misses::total 7770 # number of StoreCondReq misses 662system.cpu0.dcache.demand_misses::0 2326260 # number of demand (read+write) misses 663system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses 664system.cpu0.dcache.demand_misses::total 2326260 # number of demand (read+write) misses 665system.cpu0.dcache.overall_misses::0 2326260 # number of overall misses 666system.cpu0.dcache.overall_misses::1 0 # number of overall misses 667system.cpu0.dcache.overall_misses::total 2326260 # number of overall misses 668system.cpu0.dcache.ReadReq_miss_latency 6451753000 # number of ReadReq miss cycles 669system.cpu0.dcache.WriteReq_miss_latency 70471171342 # number of WriteReq miss cycles 670system.cpu0.dcache.LoadLockedReq_miss_latency 120838000 # number of LoadLockedReq miss cycles 671system.cpu0.dcache.StoreCondReq_miss_latency 88450500 # number of StoreCondReq miss cycles 672system.cpu0.dcache.demand_miss_latency 76922924342 # number of demand (read+write) miss cycles 673system.cpu0.dcache.overall_miss_latency 76922924342 # number of overall miss cycles 674system.cpu0.dcache.ReadReq_accesses::0 8422346 # number of ReadReq accesses(hits+misses) 675system.cpu0.dcache.ReadReq_accesses::total 8422346 # number of ReadReq accesses(hits+misses) 676system.cpu0.dcache.WriteReq_accesses::0 6211308 # number of WriteReq accesses(hits+misses) 677system.cpu0.dcache.WriteReq_accesses::total 6211308 # number of WriteReq accesses(hits+misses) 678system.cpu0.dcache.LoadLockedReq_accesses::0 231226 # number of LoadLockedReq accesses(hits+misses) 679system.cpu0.dcache.LoadLockedReq_accesses::total 231226 # number of LoadLockedReq accesses(hits+misses) 680system.cpu0.dcache.StoreCondReq_accesses::0 207521 # number of StoreCondReq accesses(hits+misses) 681system.cpu0.dcache.StoreCondReq_accesses::total 207521 # number of StoreCondReq accesses(hits+misses) 682system.cpu0.dcache.demand_accesses::0 14633654 # number of demand (read+write) accesses 683system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 684system.cpu0.dcache.demand_accesses::total 14633654 # number of demand (read+write) accesses 685system.cpu0.dcache.overall_accesses::0 14633654 # number of overall (read+write) accesses 686system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 687system.cpu0.dcache.overall_accesses::total 14633654 # number of overall (read+write) accesses 688system.cpu0.dcache.ReadReq_miss_rate::0 0.054959 # miss rate for ReadReq accesses 689system.cpu0.dcache.WriteReq_miss_rate::0 0.299998 # miss rate for WriteReq accesses 690system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043057 # miss rate for LoadLockedReq accesses 691system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037442 # miss rate for StoreCondReq accesses 692system.cpu0.dcache.demand_miss_rate::0 0.158966 # miss rate for demand accesses 693system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 694system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 695system.cpu0.dcache.overall_miss_rate::0 0.158966 # miss rate for overall accesses 696system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 697system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 698system.cpu0.dcache.ReadReq_avg_miss_latency::0 13938.284221 # average ReadReq miss latency 699system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 700system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 701system.cpu0.dcache.WriteReq_avg_miss_latency::0 37819.001675 # average WriteReq miss latency 702system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 703system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 704system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12137.203696 # average LoadLockedReq miss latency 705system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 706system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 707system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11383.590734 # average StoreCondReq miss latency 708system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 709system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 710system.cpu0.dcache.demand_avg_miss_latency::0 33067.208456 # average overall miss latency 711system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 712system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency 713system.cpu0.dcache.overall_avg_miss_latency::0 33067.208456 # average overall miss latency 714system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 715system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency 716system.cpu0.dcache.blocked_cycles::no_mshrs 6759989 # number of cycles access was blocked 717system.cpu0.dcache.blocked_cycles::no_targets 1802000 # number of cycles access was blocked 718system.cpu0.dcache.blocked::no_mshrs 868 # number of cycles access was blocked 719system.cpu0.dcache.blocked::no_targets 123 # number of cycles access was blocked 720system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7788.005760 # average number of cycles each access was blocked 721system.cpu0.dcache.avg_blocked_cycles::no_targets 14650.406504 # average number of cycles each access was blocked 722system.cpu0.dcache.fast_writes 0 # number of fast writes performed 723system.cpu0.dcache.cache_copies 0 # number of cache copies performed 724system.cpu0.dcache.writebacks 326934 # number of writebacks 725system.cpu0.dcache.ReadReq_mshr_hits 223096 # number of ReadReq MSHR hits 726system.cpu0.dcache.WriteReq_mshr_hits 1684995 # number of WriteReq MSHR hits 727system.cpu0.dcache.LoadLockedReq_mshr_hits 326 # number of LoadLockedReq MSHR hits 728system.cpu0.dcache.demand_mshr_hits 1908091 # number of demand (read+write) MSHR hits 729system.cpu0.dcache.overall_mshr_hits 1908091 # number of overall MSHR hits 730system.cpu0.dcache.ReadReq_mshr_misses 239784 # number of ReadReq MSHR misses 731system.cpu0.dcache.WriteReq_mshr_misses 178385 # number of WriteReq MSHR misses 732system.cpu0.dcache.LoadLockedReq_mshr_misses 9630 # number of LoadLockedReq MSHR misses 733system.cpu0.dcache.StoreCondReq_mshr_misses 7769 # number of StoreCondReq MSHR misses 734system.cpu0.dcache.demand_mshr_misses 418169 # number of demand (read+write) MSHR misses 735system.cpu0.dcache.overall_mshr_misses 418169 # number of overall MSHR misses 736system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 737system.cpu0.dcache.ReadReq_mshr_miss_latency 2937322500 # number of ReadReq MSHR miss cycles 738system.cpu0.dcache.WriteReq_mshr_miss_latency 6377417488 # number of WriteReq MSHR miss cycles 739system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86877000 # number of LoadLockedReq MSHR miss cycles 740system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65112500 # number of StoreCondReq MSHR miss cycles 741system.cpu0.dcache.demand_mshr_miss_latency 9314739988 # number of demand (read+write) MSHR miss cycles 742system.cpu0.dcache.overall_mshr_miss_latency 9314739988 # number of overall MSHR miss cycles 743system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959379000 # number of ReadReq MSHR uncacheable cycles 744system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038732984 # number of WriteReq MSHR uncacheable cycles 745system.cpu0.dcache.overall_mshr_uncacheable_latency 139998111984 # number of overall MSHR uncacheable cycles 746system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028470 # mshr miss rate for ReadReq accesses 747system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 748system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 749system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028719 # mshr miss rate for WriteReq accesses 750system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 751system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041648 # mshr miss rate for LoadLockedReq accesses 753system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 754system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 755system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037437 # mshr miss rate for StoreCondReq accesses 756system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 758system.cpu0.dcache.demand_mshr_miss_rate::0 0.028576 # mshr miss rate for demand accesses 759system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 760system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 761system.cpu0.dcache.overall_mshr_miss_rate::0 0.028576 # mshr miss rate for overall accesses 762system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 763system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12249.868632 # average ReadReq mshr miss latency 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35750.861833 # average WriteReq mshr miss latency 766system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9021.495327 # average LoadLockedReq mshr miss latency 767system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8381.065774 # average StoreCondReq mshr miss latency 768system.cpu0.dcache.demand_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency 769system.cpu0.dcache.overall_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency 770system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 771system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 772system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 773system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 774system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 775system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.cpu1.dtb.inst_hits 0 # ITB inst hits 777system.cpu1.dtb.inst_misses 0 # ITB inst misses 778system.cpu1.dtb.read_hits 10573739 # DTB read hits 779system.cpu1.dtb.read_misses 42015 # DTB read misses 780system.cpu1.dtb.write_hits 5529871 # DTB write hits 781system.cpu1.dtb.write_misses 15191 # DTB write misses 782system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 783system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 784system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 785system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 786system.cpu1.dtb.flush_entries 1927 # Number of entries that have been flushed from TLB 787system.cpu1.dtb.align_faults 3403 # Number of TLB faults due to alignment restrictions 788system.cpu1.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch 789system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 790system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions 791system.cpu1.dtb.read_accesses 10615754 # DTB read accesses 792system.cpu1.dtb.write_accesses 5545062 # DTB write accesses 793system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 794system.cpu1.dtb.hits 16103610 # DTB hits 795system.cpu1.dtb.misses 57206 # DTB misses 796system.cpu1.dtb.accesses 16160816 # DTB accesses 797system.cpu1.itb.inst_hits 8206065 # ITB inst hits 798system.cpu1.itb.inst_misses 3031 # ITB inst misses 799system.cpu1.itb.read_hits 0 # DTB read hits 800system.cpu1.itb.read_misses 0 # DTB read misses 801system.cpu1.itb.write_hits 0 # DTB write hits 802system.cpu1.itb.write_misses 0 # DTB write misses 803system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 804system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 805system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 806system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 807system.cpu1.itb.flush_entries 1367 # Number of entries that have been flushed from TLB 808system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 809system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 810system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 811system.cpu1.itb.perms_faults 2156 # Number of TLB faults due to permissions restrictions 812system.cpu1.itb.read_accesses 0 # DTB read accesses 813system.cpu1.itb.write_accesses 0 # DTB write accesses 814system.cpu1.itb.inst_accesses 8209096 # ITB inst accesses 815system.cpu1.itb.hits 8206065 # DTB hits 816system.cpu1.itb.misses 3031 # DTB misses 817system.cpu1.itb.accesses 8209096 # DTB accesses 818system.cpu1.numCycles 69056369 # number of cpu cycles simulated 819system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 820system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 821system.cpu1.BPredUnit.lookups 8325282 # Number of BP lookups 822system.cpu1.BPredUnit.condPredicted 6737041 # Number of conditional branches predicted 823system.cpu1.BPredUnit.condIncorrect 502555 # Number of conditional branches incorrect 824system.cpu1.BPredUnit.BTBLookups 7261407 # Number of BTB lookups 825system.cpu1.BPredUnit.BTBHits 5699060 # Number of BTB hits 826system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 827system.cpu1.BPredUnit.usedRAS 682916 # Number of times the RAS was used to get a target. 828system.cpu1.BPredUnit.RASInCorrect 107380 # Number of incorrect RAS predictions. 829system.cpu1.fetch.icacheStallCycles 17608500 # Number of cycles fetch is stalled on an Icache miss 830system.cpu1.fetch.Insts 62544782 # Number of instructions fetch has processed 831system.cpu1.fetch.Branches 8325282 # Number of branches that fetch encountered 832system.cpu1.fetch.predictedBranches 6381976 # Number of branches that fetch has predicted taken 833system.cpu1.fetch.Cycles 13909998 # Number of cycles fetch has run and was not squashing or blocked 834system.cpu1.fetch.SquashCycles 4633998 # Number of cycles fetch has spent squashing 835system.cpu1.fetch.TlbCycles 45331 # Number of cycles fetch has spent waiting for tlb 836system.cpu1.fetch.BlockedCycles 15806576 # Number of cycles fetch has spent blocked 837system.cpu1.fetch.MiscStallCycles 3075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 838system.cpu1.fetch.PendingTrapStallCycles 32937 # Number of stall cycles due to pending traps 839system.cpu1.fetch.PendingQuiesceStallCycles 125179 # Number of stall cycles due to pending quiesce instructions 840system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR 841system.cpu1.fetch.CacheLines 8203545 # Number of cache lines fetched 842system.cpu1.fetch.IcacheSquashes 759342 # Number of outstanding Icache misses that were squashed 843system.cpu1.fetch.ItlbSquashes 1683 # Number of outstanding ITLB misses that were squashed 844system.cpu1.fetch.rateDist::samples 50660963 # Number of instructions fetched each cycle (Total) 845system.cpu1.fetch.rateDist::mean 1.494360 # Number of instructions fetched each cycle (Total) 846system.cpu1.fetch.rateDist::stdev 2.745003 # Number of instructions fetched each cycle (Total) 847system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 848system.cpu1.fetch.rateDist::0 36758800 72.56% 72.56% # Number of instructions fetched each cycle (Total) 849system.cpu1.fetch.rateDist::1 702781 1.39% 73.95% # Number of instructions fetched each cycle (Total) 850system.cpu1.fetch.rateDist::2 1220162 2.41% 76.35% # Number of instructions fetched each cycle (Total) 851system.cpu1.fetch.rateDist::3 2515175 4.96% 81.32% # Number of instructions fetched each cycle (Total) 852system.cpu1.fetch.rateDist::4 1141377 2.25% 83.57% # Number of instructions fetched each cycle (Total) 853system.cpu1.fetch.rateDist::5 650709 1.28% 84.86% # Number of instructions fetched each cycle (Total) 854system.cpu1.fetch.rateDist::6 1886656 3.72% 88.58% # Number of instructions fetched each cycle (Total) 855system.cpu1.fetch.rateDist::7 404310 0.80% 89.38% # Number of instructions fetched each cycle (Total) 856system.cpu1.fetch.rateDist::8 5380993 10.62% 100.00% # Number of instructions fetched each cycle (Total) 857system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 858system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 859system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 860system.cpu1.fetch.rateDist::total 50660963 # Number of instructions fetched each cycle (Total) 861system.cpu1.fetch.branchRate 0.120558 # Number of branch fetches per cycle 862system.cpu1.fetch.rate 0.905706 # Number of inst fetches per cycle 863system.cpu1.decode.IdleCycles 18651451 # Number of cycles decode is idle 864system.cpu1.decode.BlockedCycles 16071797 # Number of cycles decode is blocked 865system.cpu1.decode.RunCycles 12503703 # Number of cycles decode is running 866system.cpu1.decode.UnblockCycles 383683 # Number of cycles decode is unblocking 867system.cpu1.decode.SquashCycles 3050329 # Number of cycles decode is squashing 868system.cpu1.decode.BranchResolved 1080503 # Number of times decode resolved a branch 869system.cpu1.decode.BranchMispred 80301 # Number of times decode detected a branch misprediction 870system.cpu1.decode.DecodedInsts 69737045 # Number of instructions handled by decode 871system.cpu1.decode.SquashedInsts 259727 # Number of squashed instructions handled by decode 872system.cpu1.rename.SquashCycles 3050329 # Number of cycles rename is squashing 873system.cpu1.rename.IdleCycles 19796555 # Number of cycles rename is idle 874system.cpu1.rename.BlockCycles 3624603 # Number of cycles rename is blocking 875system.cpu1.rename.serializeStallCycles 10867059 # count of cycles rename stalled for serializing inst 876system.cpu1.rename.RunCycles 11733074 # Number of cycles rename is running 877system.cpu1.rename.UnblockCycles 1589343 # Number of cycles rename is unblocking 878system.cpu1.rename.RenamedInsts 63809564 # Number of instructions processed by rename 879system.cpu1.rename.ROBFullEvents 2981 # Number of times rename has blocked due to ROB full 880system.cpu1.rename.IQFullEvents 320281 # Number of times rename has blocked due to IQ full 881system.cpu1.rename.LSQFullEvents 864112 # Number of times rename has blocked due to LSQ full 882system.cpu1.rename.FullRegisterEvents 38202 # Number of times there has been no free registers 883system.cpu1.rename.RenamedOperands 68239803 # Number of destination operands rename has renamed 884system.cpu1.rename.RenameLookups 296124940 # Number of register rename lookups that rename has made 885system.cpu1.rename.int_rename_lookups 296072200 # Number of integer rename lookups 886system.cpu1.rename.fp_rename_lookups 52740 # Number of floating rename lookups 887system.cpu1.rename.CommittedMaps 39106608 # Number of HB maps that are committed 888system.cpu1.rename.UndoneMaps 29133195 # Number of HB maps that are undone due to squashing 889system.cpu1.rename.serializingInsts 434621 # count of serializing insts renamed 890system.cpu1.rename.tempSerializingInsts 382462 # count of temporary serializing insts renamed 891system.cpu1.rename.skidInsts 4203927 # count of insts added to the skid buffer 892system.cpu1.memDep0.insertedLoads 11080202 # Number of loads inserted to the mem dependence unit. 893system.cpu1.memDep0.insertedStores 7013216 # Number of stores inserted to the mem dependence unit. 894system.cpu1.memDep0.conflictingLoads 634211 # Number of conflicting loads. 895system.cpu1.memDep0.conflictingStores 885799 # Number of conflicting stores. 896system.cpu1.iq.iqInstsAdded 56015216 # Number of instructions added to the IQ (excludes non-spec) 897system.cpu1.iq.iqNonSpecInstsAdded 652114 # Number of non-speculative instructions added to the IQ 898system.cpu1.iq.iqInstsIssued 50333331 # Number of instructions issued 899system.cpu1.iq.iqSquashedInstsIssued 120412 # Number of squashed instructions issued 900system.cpu1.iq.iqSquashedInstsExamined 18201885 # Number of squashed instructions iterated over during squash; mainly for profiling 901system.cpu1.iq.iqSquashedOperandsExamined 52559759 # Number of squashed operands that are examined and possibly removed from graph 902system.cpu1.iq.iqSquashedNonSpecRemoved 132486 # Number of squashed non-spec instructions that were removed 903system.cpu1.iq.issued_per_cycle::samples 50660963 # Number of insts issued each cycle 904system.cpu1.iq.issued_per_cycle::mean 0.993533 # Number of insts issued each cycle 905system.cpu1.iq.issued_per_cycle::stdev 1.617126 # Number of insts issued each cycle 906system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 907system.cpu1.iq.issued_per_cycle::0 32144545 63.45% 63.45% # Number of insts issued each cycle 908system.cpu1.iq.issued_per_cycle::1 5530112 10.92% 74.37% # Number of insts issued each cycle 909system.cpu1.iq.issued_per_cycle::2 3775848 7.45% 81.82% # Number of insts issued each cycle 910system.cpu1.iq.issued_per_cycle::3 3605586 7.12% 88.94% # Number of insts issued each cycle 911system.cpu1.iq.issued_per_cycle::4 2986827 5.90% 94.83% # Number of insts issued each cycle 912system.cpu1.iq.issued_per_cycle::5 1557942 3.08% 97.91% # Number of insts issued each cycle 913system.cpu1.iq.issued_per_cycle::6 784538 1.55% 99.46% # Number of insts issued each cycle 914system.cpu1.iq.issued_per_cycle::7 214001 0.42% 99.88% # Number of insts issued each cycle 915system.cpu1.iq.issued_per_cycle::8 61564 0.12% 100.00% # Number of insts issued each cycle 916system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 917system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 918system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 919system.cpu1.iq.issued_per_cycle::total 50660963 # Number of insts issued each cycle 920system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 921system.cpu1.iq.fu_full::IntAlu 15475 1.52% 1.52% # attempts to use FU when none available 922system.cpu1.iq.fu_full::IntMult 1190 0.12% 1.63% # attempts to use FU when none available 923system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available 924system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available 925system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available 926system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available 927system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available 928system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available 929system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available 930system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available 931system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available 932system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available 933system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available 934system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available 935system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available 936system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available 937system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available 938system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available 939system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available 940system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available 941system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available 942system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available 943system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available 944system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available 945system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available 946system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available 947system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available 948system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available 949system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available 950system.cpu1.iq.fu_full::MemRead 748820 73.38% 75.02% # attempts to use FU when none available 951system.cpu1.iq.fu_full::MemWrite 254917 24.98% 100.00% # attempts to use FU when none available 952system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 953system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 954system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued 955system.cpu1.iq.FU_type_0::IntAlu 32741822 65.05% 65.09% # Type of FU issued 956system.cpu1.iq.FU_type_0::IntMult 50334 0.10% 65.19% # Type of FU issued 957system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.19% # Type of FU issued 958system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.19% # Type of FU issued 959system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.19% # Type of FU issued 960system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.19% # Type of FU issued 961system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.19% # Type of FU issued 962system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.19% # Type of FU issued 963system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.19% # Type of FU issued 964system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.19% # Type of FU issued 965system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.19% # Type of FU issued 966system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.19% # Type of FU issued 967system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.19% # Type of FU issued 968system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.19% # Type of FU issued 969system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.19% # Type of FU issued 970system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.19% # Type of FU issued 971system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.19% # Type of FU issued 972system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.19% # Type of FU issued 973system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.19% # Type of FU issued 974system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.19% # Type of FU issued 975system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.19% # Type of FU issued 976system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.19% # Type of FU issued 977system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.19% # Type of FU issued 978system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.19% # Type of FU issued 979system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.19% # Type of FU issued 980system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.19% # Type of FU issued 981system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.19% # Type of FU issued 982system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 65.19% # Type of FU issued 983system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.19% # Type of FU issued 984system.cpu1.iq.FU_type_0::MemRead 11609954 23.07% 88.25% # Type of FU issued 985system.cpu1.iq.FU_type_0::MemWrite 5911828 11.75% 100.00% # Type of FU issued 986system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 987system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 988system.cpu1.iq.FU_type_0::total 50333331 # Type of FU issued 989system.cpu1.iq.rate 0.728873 # Inst issue rate 990system.cpu1.iq.fu_busy_cnt 1020402 # FU busy when requested 991system.cpu1.iq.fu_busy_rate 0.020273 # FU busy rate (busy events/executed inst) 992system.cpu1.iq.int_inst_queue_reads 152512648 # Number of integer instruction queue reads 993system.cpu1.iq.int_inst_queue_writes 74873900 # Number of integer instruction queue writes 994system.cpu1.iq.int_inst_queue_wakeup_accesses 44249478 # Number of integer instruction queue wakeup accesses 995system.cpu1.iq.fp_inst_queue_reads 12744 # Number of floating instruction queue reads 996system.cpu1.iq.fp_inst_queue_writes 7082 # Number of floating instruction queue writes 997system.cpu1.iq.fp_inst_queue_wakeup_accesses 5800 # Number of floating instruction queue wakeup accesses 998system.cpu1.iq.int_alu_accesses 51328452 # Number of integer alu accesses 999system.cpu1.iq.fp_alu_accesses 6659 # Number of floating point alu accesses 1000system.cpu1.iew.lsq.thread0.forwLoads 264599 # Number of loads that had data forwarded from stores 1001system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1002system.cpu1.iew.lsq.thread0.squashedLoads 3968304 # Number of loads squashed 1003system.cpu1.iew.lsq.thread0.ignoredResponses 7379 # Number of memory responses ignored because the instruction is squashed 1004system.cpu1.iew.lsq.thread0.memOrderViolation 12210 # Number of memory ordering violations 1005system.cpu1.iew.lsq.thread0.squashedStores 1474293 # Number of stores squashed 1006system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1007system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1008system.cpu1.iew.lsq.thread0.rescheduledLoads 1850149 # Number of loads that were rescheduled 1009system.cpu1.iew.lsq.thread0.cacheBlocked 1139663 # Number of times an access to memory failed due to the cache being blocked 1010system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1011system.cpu1.iew.iewSquashCycles 3050329 # Number of cycles IEW is squashing 1012system.cpu1.iew.iewBlockCycles 2505738 # Number of cycles IEW is blocking 1013system.cpu1.iew.iewUnblockCycles 70750 # Number of cycles IEW is unblocking 1014system.cpu1.iew.iewDispatchedInsts 56718238 # Number of instructions dispatched to IQ 1015system.cpu1.iew.iewDispSquashedInsts 255272 # Number of squashed instructions skipped by dispatch 1016system.cpu1.iew.iewDispLoadInsts 11080202 # Number of dispatched load instructions 1017system.cpu1.iew.iewDispStoreInsts 7013216 # Number of dispatched store instructions 1018system.cpu1.iew.iewDispNonSpecInsts 408861 # Number of dispatched non-speculative instructions 1019system.cpu1.iew.iewIQFullEvents 28043 # Number of times the IQ has become full, causing a stall 1020system.cpu1.iew.iewLSQFullEvents 3317 # Number of times the LSQ has become full, causing a stall 1021system.cpu1.iew.memOrderViolationEvents 12210 # Number of memory order violations 1022system.cpu1.iew.predictedTakenIncorrect 383709 # Number of branches that were predicted taken incorrectly 1023system.cpu1.iew.predictedNotTakenIncorrect 125709 # Number of branches that were predicted not taken incorrectly 1024system.cpu1.iew.branchMispredicts 509418 # Number of branch mispredicts detected at execute 1025system.cpu1.iew.iewExecutedInsts 47546383 # Number of executed instructions 1026system.cpu1.iew.iewExecLoadInsts 10844490 # Number of load instructions executed 1027system.cpu1.iew.iewExecSquashedInsts 2786948 # Number of squashed instructions skipped in execute 1028system.cpu1.iew.exec_swp 0 # number of swp insts executed 1029system.cpu1.iew.exec_nop 50908 # number of nop insts executed 1030system.cpu1.iew.exec_refs 16665607 # number of memory reference insts executed 1031system.cpu1.iew.exec_branches 5805305 # Number of branches executed 1032system.cpu1.iew.exec_stores 5821117 # Number of stores executed 1033system.cpu1.iew.exec_rate 0.688516 # Inst execution rate 1034system.cpu1.iew.wb_sent 46287732 # cumulative count of insts sent to commit 1035system.cpu1.iew.wb_count 44255278 # cumulative count of insts written-back 1036system.cpu1.iew.wb_producers 24264943 # num instructions producing a value 1037system.cpu1.iew.wb_consumers 44435618 # num instructions consuming a value 1038system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1039system.cpu1.iew.wb_rate 0.640857 # insts written-back per cycle 1040system.cpu1.iew.wb_fanout 0.546070 # average fanout of values written-back 1041system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1042system.cpu1.commit.commitCommittedInsts 38085105 # The number of committed instructions 1043system.cpu1.commit.commitSquashedInsts 18540440 # The number of squashed insts skipped by commit 1044system.cpu1.commit.commitNonSpecStalls 519628 # The number of times commit has been forced to stall to communicate backwards 1045system.cpu1.commit.branchMispredicts 449695 # The number of times a branch was mispredicted 1046system.cpu1.commit.committed_per_cycle::samples 47651856 # Number of insts commited each cycle 1047system.cpu1.commit.committed_per_cycle::mean 0.799237 # Number of insts commited each cycle 1048system.cpu1.commit.committed_per_cycle::stdev 1.835547 # Number of insts commited each cycle 1049system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1050system.cpu1.commit.committed_per_cycle::0 34686600 72.79% 72.79% # Number of insts commited each cycle 1051system.cpu1.commit.committed_per_cycle::1 6094128 12.79% 85.58% # Number of insts commited each cycle 1052system.cpu1.commit.committed_per_cycle::2 1835097 3.85% 89.43% # Number of insts commited each cycle 1053system.cpu1.commit.committed_per_cycle::3 960943 2.02% 91.45% # Number of insts commited each cycle 1054system.cpu1.commit.committed_per_cycle::4 825753 1.73% 93.18% # Number of insts commited each cycle 1055system.cpu1.commit.committed_per_cycle::5 740854 1.55% 94.74% # Number of insts commited each cycle 1056system.cpu1.commit.committed_per_cycle::6 593786 1.25% 95.98% # Number of insts commited each cycle 1057system.cpu1.commit.committed_per_cycle::7 449604 0.94% 96.93% # Number of insts commited each cycle 1058system.cpu1.commit.committed_per_cycle::8 1465091 3.07% 100.00% # Number of insts commited each cycle 1059system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1060system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1061system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1062system.cpu1.commit.committed_per_cycle::total 47651856 # Number of insts commited each cycle 1063system.cpu1.commit.count 38085105 # Number of instructions committed 1064system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1065system.cpu1.commit.refs 12650821 # Number of memory references committed 1066system.cpu1.commit.loads 7111898 # Number of loads committed 1067system.cpu1.commit.membars 148710 # Number of memory barriers committed 1068system.cpu1.commit.branches 4804442 # Number of branches committed 1069system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. 1070system.cpu1.commit.int_insts 34027730 # Number of committed integer instructions. 1071system.cpu1.commit.function_calls 433273 # Number of function calls committed. 1072system.cpu1.commit.bw_lim_events 1465091 # number cycles where commit BW limit reached 1073system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1074system.cpu1.rob.rob_reads 102053926 # The number of ROB reads 1075system.cpu1.rob.rob_writes 116420763 # The number of ROB writes 1076system.cpu1.timesIdled 449905 # Number of times that the entire CPU went into an idle state and unscheduled itself 1077system.cpu1.idleCycles 18395406 # Total number of cycles that the CPU has spent unscheduled due to idling 1078system.cpu1.quiesceCycles 5095165422 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1079system.cpu1.committedInsts 38060551 # Number of Instructions Simulated 1080system.cpu1.committedInsts_total 38060551 # Number of Instructions Simulated 1081system.cpu1.cpi 1.814382 # CPI: Cycles Per Instruction 1082system.cpu1.cpi_total 1.814382 # CPI: Total CPI of All Threads 1083system.cpu1.ipc 0.551152 # IPC: Instructions Per Cycle 1084system.cpu1.ipc_total 0.551152 # IPC: Total IPC of All Threads 1085system.cpu1.int_regfile_reads 222777169 # number of integer regfile reads 1086system.cpu1.int_regfile_writes 47147395 # number of integer regfile writes 1087system.cpu1.fp_regfile_reads 4225 # number of floating regfile reads 1088system.cpu1.fp_regfile_writes 1812 # number of floating regfile writes 1089system.cpu1.misc_regfile_reads 77230796 # number of misc regfile reads 1090system.cpu1.misc_regfile_writes 323252 # number of misc regfile writes 1091system.cpu1.icache.replacements 485904 # number of replacements 1092system.cpu1.icache.tagsinuse 498.788757 # Cycle average of tags in use 1093system.cpu1.icache.total_refs 7675789 # Total number of references to valid blocks. 1094system.cpu1.icache.sampled_refs 486416 # Sample count of references to valid blocks. 1095system.cpu1.icache.avg_refs 15.780297 # Average number of references to valid blocks. 1096system.cpu1.icache.warmup_cycle 74237229000 # Cycle when the warmup percentage was hit. 1097system.cpu1.icache.occ_blocks::0 498.788757 # Average occupied blocks per context 1098system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy 1099system.cpu1.icache.ReadReq_hits::0 7675789 # number of ReadReq hits 1100system.cpu1.icache.ReadReq_hits::total 7675789 # number of ReadReq hits 1101system.cpu1.icache.demand_hits::0 7675789 # number of demand (read+write) hits 1102system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits 1103system.cpu1.icache.demand_hits::total 7675789 # number of demand (read+write) hits 1104system.cpu1.icache.overall_hits::0 7675789 # number of overall hits 1105system.cpu1.icache.overall_hits::1 0 # number of overall hits 1106system.cpu1.icache.overall_hits::total 7675789 # number of overall hits 1107system.cpu1.icache.ReadReq_misses::0 527703 # number of ReadReq misses 1108system.cpu1.icache.ReadReq_misses::total 527703 # number of ReadReq misses 1109system.cpu1.icache.demand_misses::0 527703 # number of demand (read+write) misses 1110system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses 1111system.cpu1.icache.demand_misses::total 527703 # number of demand (read+write) misses 1112system.cpu1.icache.overall_misses::0 527703 # number of overall misses 1113system.cpu1.icache.overall_misses::1 0 # number of overall misses 1114system.cpu1.icache.overall_misses::total 527703 # number of overall misses 1115system.cpu1.icache.ReadReq_miss_latency 7760328997 # number of ReadReq miss cycles 1116system.cpu1.icache.demand_miss_latency 7760328997 # number of demand (read+write) miss cycles 1117system.cpu1.icache.overall_miss_latency 7760328997 # number of overall miss cycles 1118system.cpu1.icache.ReadReq_accesses::0 8203492 # number of ReadReq accesses(hits+misses) 1119system.cpu1.icache.ReadReq_accesses::total 8203492 # number of ReadReq accesses(hits+misses) 1120system.cpu1.icache.demand_accesses::0 8203492 # number of demand (read+write) accesses 1121system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses 1122system.cpu1.icache.demand_accesses::total 8203492 # number of demand (read+write) accesses 1123system.cpu1.icache.overall_accesses::0 8203492 # number of overall (read+write) accesses 1124system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses 1125system.cpu1.icache.overall_accesses::total 8203492 # number of overall (read+write) accesses 1126system.cpu1.icache.ReadReq_miss_rate::0 0.064327 # miss rate for ReadReq accesses 1127system.cpu1.icache.demand_miss_rate::0 0.064327 # miss rate for demand accesses 1128system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 1129system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses 1130system.cpu1.icache.overall_miss_rate::0 0.064327 # miss rate for overall accesses 1131system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 1132system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses 1133system.cpu1.icache.ReadReq_avg_miss_latency::0 14705.864846 # average ReadReq miss latency 1134system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 1135system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 1136system.cpu1.icache.demand_avg_miss_latency::0 14705.864846 # average overall miss latency 1137system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency 1138system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency 1139system.cpu1.icache.overall_avg_miss_latency::0 14705.864846 # average overall miss latency 1140system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency 1141system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency 1142system.cpu1.icache.blocked_cycles::no_mshrs 1243497 # number of cycles access was blocked 1143system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1144system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked 1145system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1146system.cpu1.icache.avg_blocked_cycles::no_mshrs 7446.089820 # average number of cycles each access was blocked 1147system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1148system.cpu1.icache.fast_writes 0 # number of fast writes performed 1149system.cpu1.icache.cache_copies 0 # number of cache copies performed 1150system.cpu1.icache.writebacks 18536 # number of writebacks 1151system.cpu1.icache.ReadReq_mshr_hits 41257 # number of ReadReq MSHR hits 1152system.cpu1.icache.demand_mshr_hits 41257 # number of demand (read+write) MSHR hits 1153system.cpu1.icache.overall_mshr_hits 41257 # number of overall MSHR hits 1154system.cpu1.icache.ReadReq_mshr_misses 486446 # number of ReadReq MSHR misses 1155system.cpu1.icache.demand_mshr_misses 486446 # number of demand (read+write) MSHR misses 1156system.cpu1.icache.overall_mshr_misses 486446 # number of overall MSHR misses 1157system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1158system.cpu1.icache.ReadReq_mshr_miss_latency 5802515997 # number of ReadReq MSHR miss cycles 1159system.cpu1.icache.demand_mshr_miss_latency 5802515997 # number of demand (read+write) MSHR miss cycles 1160system.cpu1.icache.overall_mshr_miss_latency 5802515997 # number of overall MSHR miss cycles 1161system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles 1162system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles 1163system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059297 # mshr miss rate for ReadReq accesses 1164system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 1165system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 1166system.cpu1.icache.demand_mshr_miss_rate::0 0.059297 # mshr miss rate for demand accesses 1167system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 1168system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 1169system.cpu1.icache.overall_mshr_miss_rate::0 0.059297 # mshr miss rate for overall accesses 1170system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 1171system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 1172system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11928.386701 # average ReadReq mshr miss latency 1173system.cpu1.icache.demand_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency 1174system.cpu1.icache.overall_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency 1175system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1176system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1177system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 1178system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1179system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1180system.cpu1.dcache.replacements 272184 # number of replacements 1181system.cpu1.dcache.tagsinuse 444.922817 # Cycle average of tags in use 1182system.cpu1.dcache.total_refs 10410516 # Total number of references to valid blocks. 1183system.cpu1.dcache.sampled_refs 272526 # Sample count of references to valid blocks. 1184system.cpu1.dcache.avg_refs 38.200084 # Average number of references to valid blocks. 1185system.cpu1.dcache.warmup_cycle 66749899000 # Cycle when the warmup percentage was hit. 1186system.cpu1.dcache.occ_blocks::0 444.922817 # Average occupied blocks per context 1187system.cpu1.dcache.occ_percent::0 0.868990 # Average percentage of cache occupancy 1188system.cpu1.dcache.ReadReq_hits::0 7080702 # number of ReadReq hits 1189system.cpu1.dcache.ReadReq_hits::total 7080702 # number of ReadReq hits 1190system.cpu1.dcache.WriteReq_hits::0 3139041 # number of WriteReq hits 1191system.cpu1.dcache.WriteReq_hits::total 3139041 # number of WriteReq hits 1192system.cpu1.dcache.LoadLockedReq_hits::0 75297 # number of LoadLockedReq hits 1193system.cpu1.dcache.LoadLockedReq_hits::total 75297 # number of LoadLockedReq hits 1194system.cpu1.dcache.StoreCondReq_hits::0 72589 # number of StoreCondReq hits 1195system.cpu1.dcache.StoreCondReq_hits::total 72589 # number of StoreCondReq hits 1196system.cpu1.dcache.demand_hits::0 10219743 # number of demand (read+write) hits 1197system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits 1198system.cpu1.dcache.demand_hits::total 10219743 # number of demand (read+write) hits 1199system.cpu1.dcache.overall_hits::0 10219743 # number of overall hits 1200system.cpu1.dcache.overall_hits::1 0 # number of overall hits 1201system.cpu1.dcache.overall_hits::total 10219743 # number of overall hits 1202system.cpu1.dcache.ReadReq_misses::0 323641 # number of ReadReq misses 1203system.cpu1.dcache.ReadReq_misses::total 323641 # number of ReadReq misses 1204system.cpu1.dcache.WriteReq_misses::0 1274421 # number of WriteReq misses 1205system.cpu1.dcache.WriteReq_misses::total 1274421 # number of WriteReq misses 1206system.cpu1.dcache.LoadLockedReq_misses::0 12692 # number of LoadLockedReq misses 1207system.cpu1.dcache.LoadLockedReq_misses::total 12692 # number of LoadLockedReq misses 1208system.cpu1.dcache.StoreCondReq_misses::0 11088 # number of StoreCondReq misses 1209system.cpu1.dcache.StoreCondReq_misses::total 11088 # number of StoreCondReq misses 1210system.cpu1.dcache.demand_misses::0 1598062 # number of demand (read+write) misses 1211system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses 1212system.cpu1.dcache.demand_misses::total 1598062 # number of demand (read+write) misses 1213system.cpu1.dcache.overall_misses::0 1598062 # number of overall misses 1214system.cpu1.dcache.overall_misses::1 0 # number of overall misses 1215system.cpu1.dcache.overall_misses::total 1598062 # number of overall misses 1216system.cpu1.dcache.ReadReq_miss_latency 5056918000 # number of ReadReq miss cycles 1217system.cpu1.dcache.WriteReq_miss_latency 46262292366 # number of WriteReq miss cycles 1218system.cpu1.dcache.LoadLockedReq_miss_latency 147873000 # number of LoadLockedReq miss cycles 1219system.cpu1.dcache.StoreCondReq_miss_latency 87994000 # number of StoreCondReq miss cycles 1220system.cpu1.dcache.demand_miss_latency 51319210366 # number of demand (read+write) miss cycles 1221system.cpu1.dcache.overall_miss_latency 51319210366 # number of overall miss cycles 1222system.cpu1.dcache.ReadReq_accesses::0 7404343 # number of ReadReq accesses(hits+misses) 1223system.cpu1.dcache.ReadReq_accesses::total 7404343 # number of ReadReq accesses(hits+misses) 1224system.cpu1.dcache.WriteReq_accesses::0 4413462 # number of WriteReq accesses(hits+misses) 1225system.cpu1.dcache.WriteReq_accesses::total 4413462 # number of WriteReq accesses(hits+misses) 1226system.cpu1.dcache.LoadLockedReq_accesses::0 87989 # number of LoadLockedReq accesses(hits+misses) 1227system.cpu1.dcache.LoadLockedReq_accesses::total 87989 # number of LoadLockedReq accesses(hits+misses) 1228system.cpu1.dcache.StoreCondReq_accesses::0 83677 # number of StoreCondReq accesses(hits+misses) 1229system.cpu1.dcache.StoreCondReq_accesses::total 83677 # number of StoreCondReq accesses(hits+misses) 1230system.cpu1.dcache.demand_accesses::0 11817805 # number of demand (read+write) accesses 1231system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 1232system.cpu1.dcache.demand_accesses::total 11817805 # number of demand (read+write) accesses 1233system.cpu1.dcache.overall_accesses::0 11817805 # number of overall (read+write) accesses 1234system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 1235system.cpu1.dcache.overall_accesses::total 11817805 # number of overall (read+write) accesses 1236system.cpu1.dcache.ReadReq_miss_rate::0 0.043710 # miss rate for ReadReq accesses 1237system.cpu1.dcache.WriteReq_miss_rate::0 0.288758 # miss rate for WriteReq accesses 1238system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144245 # miss rate for LoadLockedReq accesses 1239system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132510 # miss rate for StoreCondReq accesses 1240system.cpu1.dcache.demand_miss_rate::0 0.135225 # miss rate for demand accesses 1241system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 1242system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 1243system.cpu1.dcache.overall_miss_rate::0 0.135225 # miss rate for overall accesses 1244system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 1245system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 1246system.cpu1.dcache.ReadReq_avg_miss_latency::0 15625.084584 # average ReadReq miss latency 1247system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 1248system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 1249system.cpu1.dcache.WriteReq_avg_miss_latency::0 36300.635635 # average WriteReq miss latency 1250system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 1251system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 1252system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11650.882446 # average LoadLockedReq miss latency 1253system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 1254system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 1255system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7935.966811 # average StoreCondReq miss latency 1256system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 1257system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 1258system.cpu1.dcache.demand_avg_miss_latency::0 32113.403839 # average overall miss latency 1259system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 1260system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency 1261system.cpu1.dcache.overall_avg_miss_latency::0 32113.403839 # average overall miss latency 1262system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 1263system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency 1264system.cpu1.dcache.blocked_cycles::no_mshrs 13353050 # number of cycles access was blocked 1265system.cpu1.dcache.blocked_cycles::no_targets 5461500 # number of cycles access was blocked 1266system.cpu1.dcache.blocked::no_mshrs 3087 # number of cycles access was blocked 1267system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked 1268system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4325.574992 # average number of cycles each access was blocked 1269system.cpu1.dcache.avg_blocked_cycles::no_targets 34134.375000 # average number of cycles each access was blocked 1270system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1271system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1272system.cpu1.dcache.writebacks 223414 # number of writebacks 1273system.cpu1.dcache.ReadReq_mshr_hits 134188 # number of ReadReq MSHR hits 1274system.cpu1.dcache.WriteReq_mshr_hits 1158095 # number of WriteReq MSHR hits 1275system.cpu1.dcache.LoadLockedReq_mshr_hits 989 # number of LoadLockedReq MSHR hits 1276system.cpu1.dcache.demand_mshr_hits 1292283 # number of demand (read+write) MSHR hits 1277system.cpu1.dcache.overall_mshr_hits 1292283 # number of overall MSHR hits 1278system.cpu1.dcache.ReadReq_mshr_misses 189453 # number of ReadReq MSHR misses 1279system.cpu1.dcache.WriteReq_mshr_misses 116326 # number of WriteReq MSHR misses 1280system.cpu1.dcache.LoadLockedReq_mshr_misses 11703 # number of LoadLockedReq MSHR misses 1281system.cpu1.dcache.StoreCondReq_mshr_misses 11087 # number of StoreCondReq MSHR misses 1282system.cpu1.dcache.demand_mshr_misses 305779 # number of demand (read+write) MSHR misses 1283system.cpu1.dcache.overall_mshr_misses 305779 # number of overall MSHR misses 1284system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1285system.cpu1.dcache.ReadReq_mshr_miss_latency 2493574500 # number of ReadReq MSHR miss cycles 1286system.cpu1.dcache.WriteReq_mshr_miss_latency 3446976050 # number of WriteReq MSHR miss cycles 1287system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 98971000 # number of LoadLockedReq MSHR miss cycles 1288system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54655500 # number of StoreCondReq MSHR miss cycles 1289system.cpu1.dcache.demand_mshr_miss_latency 5940550550 # number of demand (read+write) MSHR miss cycles 1290system.cpu1.dcache.overall_mshr_miss_latency 5940550550 # number of overall MSHR miss cycles 1291system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455171000 # number of ReadReq MSHR uncacheable cycles 1292system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503599517 # number of WriteReq MSHR uncacheable cycles 1293system.cpu1.dcache.overall_mshr_uncacheable_latency 49958770517 # number of overall MSHR uncacheable cycles 1294system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025587 # mshr miss rate for ReadReq accesses 1295system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 1296system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 1297system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026357 # mshr miss rate for WriteReq accesses 1298system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 1299system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 1300system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133005 # mshr miss rate for LoadLockedReq accesses 1301system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 1302system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 1303system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132498 # mshr miss rate for StoreCondReq accesses 1304system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 1305system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 1306system.cpu1.dcache.demand_mshr_miss_rate::0 0.025874 # mshr miss rate for demand accesses 1307system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 1308system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 1309system.cpu1.dcache.overall_mshr_miss_rate::0 0.025874 # mshr miss rate for overall accesses 1310system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 1311system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 1312system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13161.968932 # average ReadReq mshr miss latency 1313system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29632.034541 # average WriteReq mshr miss latency 1314system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8456.891395 # average LoadLockedReq mshr miss latency 1315system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4929.692433 # average StoreCondReq mshr miss latency 1316system.cpu1.dcache.demand_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency 1317system.cpu1.dcache.overall_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency 1318system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1319system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 1320system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1321system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 1322system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1323system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1324system.iocache.replacements 0 # number of replacements 1325system.iocache.tagsinuse 0 # Cycle average of tags in use 1326system.iocache.total_refs 0 # Total number of references to valid blocks. 1327system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1328system.iocache.avg_refs no_value # Average number of references to valid blocks. 1329system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1330system.iocache.demand_hits::0 0 # number of demand (read+write) hits 1331system.iocache.demand_hits::1 0 # number of demand (read+write) hits 1332system.iocache.demand_hits::total 0 # number of demand (read+write) hits 1333system.iocache.overall_hits::0 0 # number of overall hits 1334system.iocache.overall_hits::1 0 # number of overall hits 1335system.iocache.overall_hits::total 0 # number of overall hits 1336system.iocache.demand_misses::0 0 # number of demand (read+write) misses 1337system.iocache.demand_misses::1 0 # number of demand (read+write) misses 1338system.iocache.demand_misses::total 0 # number of demand (read+write) misses 1339system.iocache.overall_misses::0 0 # number of overall misses 1340system.iocache.overall_misses::1 0 # number of overall misses 1341system.iocache.overall_misses::total 0 # number of overall misses 1342system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 1343system.iocache.overall_miss_latency 0 # number of overall miss cycles 1344system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 1345system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 1346system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 1347system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 1348system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 1349system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 1350system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 1351system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 1352system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 1353system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 1354system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 1355system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 1356system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 1357system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 1358system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 1359system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 1360system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 1361system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 1362system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1363system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1364system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1365system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1366system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1367system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1368system.iocache.fast_writes 0 # number of fast writes performed 1369system.iocache.cache_copies 0 # number of cache copies performed 1370system.iocache.writebacks 0 # number of writebacks 1371system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1372system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 1373system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 1374system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 1375system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1376system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 1377system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 1378system.iocache.ReadReq_mshr_uncacheable_latency 1308164258694 # number of ReadReq MSHR uncacheable cycles 1379system.iocache.overall_mshr_uncacheable_latency 1308164258694 # number of overall MSHR uncacheable cycles 1380system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 1381system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 1382system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 1383system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 1384system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 1385system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 1386system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 1387system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 1388system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1389system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1390system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 1391system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1392system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1393system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1394system.cpu0.kern.inst.quiesce 55740 # number of quiesce instructions executed 1395system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1396system.cpu1.kern.inst.quiesce 41953 # number of quiesce instructions executed 1397 1398---------- End Simulation Statistics ---------- 1399