stats.txt revision 11589:af2f7fef4875
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825947 # Number of seconds simulated 4sim_ticks 2825947406000 # Number of ticks simulated 5final_tick 2825947406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 132633 # Simulator instruction rate (inst/s) 8host_op_rate 160894 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3120208803 # Simulator tick rate (ticks/s) 10host_mem_usage 618508 # Number of bytes of host memory used 11host_seconds 905.69 # Real time elapsed on the host 12sim_insts 120124543 # Number of instructions simulated 13sim_ops 145720076 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1303616 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1321960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8513856 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 181024 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 635732 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 529024 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 28system.physmem.bytes_read::total 12488540 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 1303616 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 181024 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 1484640 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 8962368 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 35system.physmem.bytes_written::total 8979932 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 22616 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 21176 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 133029 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 2896 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 9954 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 8266 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 197989 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 140037 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 144428 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 461302 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 467794 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 3012744 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 64058 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 224962 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 187202 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 4419240 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 461302 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 64058 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 525360 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 3171456 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 3177671 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 3171456 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 461302 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 473995 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 3012744 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 64058 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 224977 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 187202 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 7596911 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 197990 # Number of read requests accepted 85system.physmem.writeReqs 144428 # Number of write requests accepted 86system.physmem.readBursts 197990 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 144428 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 12662400 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue 90system.physmem.bytesWritten 8992448 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 12488604 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 8979932 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 12407 # Per bank write bursts 97system.physmem.perBankRdBursts::1 12295 # Per bank write bursts 98system.physmem.perBankRdBursts::2 12935 # Per bank write bursts 99system.physmem.perBankRdBursts::3 12653 # Per bank write bursts 100system.physmem.perBankRdBursts::4 14543 # Per bank write bursts 101system.physmem.perBankRdBursts::5 12106 # Per bank write bursts 102system.physmem.perBankRdBursts::6 12653 # Per bank write bursts 103system.physmem.perBankRdBursts::7 12509 # Per bank write bursts 104system.physmem.perBankRdBursts::8 12223 # Per bank write bursts 105system.physmem.perBankRdBursts::9 12064 # Per bank write bursts 106system.physmem.perBankRdBursts::10 11718 # Per bank write bursts 107system.physmem.perBankRdBursts::11 11008 # Per bank write bursts 108system.physmem.perBankRdBursts::12 11914 # Per bank write bursts 109system.physmem.perBankRdBursts::13 13060 # Per bank write bursts 110system.physmem.perBankRdBursts::14 12107 # Per bank write bursts 111system.physmem.perBankRdBursts::15 11655 # Per bank write bursts 112system.physmem.perBankWrBursts::0 9105 # Per bank write bursts 113system.physmem.perBankWrBursts::1 9127 # Per bank write bursts 114system.physmem.perBankWrBursts::2 9615 # Per bank write bursts 115system.physmem.perBankWrBursts::3 9150 # Per bank write bursts 116system.physmem.perBankWrBursts::4 8481 # Per bank write bursts 117system.physmem.perBankWrBursts::5 8750 # Per bank write bursts 118system.physmem.perBankWrBursts::6 8993 # Per bank write bursts 119system.physmem.perBankWrBursts::7 8806 # Per bank write bursts 120system.physmem.perBankWrBursts::8 8720 # Per bank write bursts 121system.physmem.perBankWrBursts::9 8569 # Per bank write bursts 122system.physmem.perBankWrBursts::10 8518 # Per bank write bursts 123system.physmem.perBankWrBursts::11 8119 # Per bank write bursts 124system.physmem.perBankWrBursts::12 8743 # Per bank write bursts 125system.physmem.perBankWrBursts::13 9182 # Per bank write bursts 126system.physmem.perBankWrBursts::14 8573 # Per bank write bursts 127system.physmem.perBankWrBursts::15 8056 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 6 # Number of times write queue was full causing retry 130system.physmem.totGap 2825947136000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 551 # Read request sizes (log2) 134system.physmem.readPktSize::3 28 # Read request sizes (log2) 135system.physmem.readPktSize::4 3086 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 194325 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 4391 # Write request sizes (log2) 141system.physmem.writePktSize::3 0 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 140037 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 60161 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 72217 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 15830 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 12957 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 8715 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 7515 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 6523 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 4740 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 1512 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 744 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 304 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 2737 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 4277 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 4910 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 5685 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 6030 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 6974 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 7661 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 8689 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 10204 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 10681 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 9419 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 9434 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 10925 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 9108 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 8385 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 7984 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 686 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 515 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 290 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 232 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 149 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 125 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 129 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 129 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 92378 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 234.414947 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 132.500025 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 299.048436 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 50794 54.98% 54.98% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 17715 19.18% 74.16% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 5941 6.43% 80.59% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 3366 3.64% 84.24% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 2816 3.05% 87.28% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 1529 1.66% 88.94% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 925 1.00% 89.94% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 990 1.07% 91.01% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 8302 8.99% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 92378 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 6992 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 28.296339 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 556.591514 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-2047 6990 99.97% 99.97% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 6992 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 6992 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.095395 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.609227 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 12.295574 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 5854 83.72% 83.72% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 392 5.61% 89.33% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 80 1.14% 90.47% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 62 0.89% 91.36% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 277 3.96% 95.32% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 20 0.29% 95.61% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 15 0.21% 95.82% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 24 0.34% 96.17% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 25 0.36% 96.52% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 12 0.17% 96.70% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 9 0.13% 96.82% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 14 0.20% 97.03% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 142 2.03% 99.06% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 4 0.06% 99.11% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 10 0.14% 99.26% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 7 0.10% 99.36% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 6 0.09% 99.44% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 1 0.01% 99.46% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 2 0.03% 99.49% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 1 0.01% 99.50% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 3 0.04% 99.54% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 2 0.03% 99.57% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::108-111 3 0.04% 99.61% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::112-115 1 0.01% 99.63% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::124-127 1 0.01% 99.64% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 14 0.20% 99.84% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::132-135 2 0.03% 99.87% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::156-159 3 0.04% 99.93% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 6992 # Writes before turning the bus around for reads 300system.physmem.totQLat 6748582846 # Total ticks spent queuing 301system.physmem.totMemAccLat 10458270346 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 989250000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 34109.59 # Average queueing delay per DRAM burst 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 305system.physmem.avgMemAccLat 52859.59 # Average memory access latency per DRAM burst 306system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s 307system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s 308system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.06 # Data bus utilization in percentage 312system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 313system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 314system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing 316system.physmem.readRowHits 165284 # Number of row buffer hits during reads 317system.physmem.writeRowHits 80694 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 57.42 # Row buffer hit rate for writes 320system.physmem.avgGap 8252916.42 # Average gap between requests 321system.physmem.pageHitRate 72.69 # Row buffer hit rate, read and write combined 322system.physmem_0.actEnergy 361058040 # Energy for activate commands per rank (pJ) 323system.physmem_0.preEnergy 197005875 # Energy for precharge commands per rank (pJ) 324system.physmem_0.readEnergy 796387800 # Energy for read commands per rank (pJ) 325system.physmem_0.writeEnergy 466734960 # Energy for write commands per rank (pJ) 326system.physmem_0.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) 327system.physmem_0.actBackEnergy 79734690540 # Energy for active background per rank (pJ) 328system.physmem_0.preBackEnergy 1625622381750 # Energy for precharge background per rank (pJ) 329system.physmem_0.totalEnergy 1891755025365 # Total energy per rank (pJ) 330system.physmem_0.averagePower 669.424618 # Core power per rank (mW) 331system.physmem_0.memoryStateTime::IDLE 2704272847388 # Time in different power states 332system.physmem_0.memoryStateTime::REF 94364400000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 27304587612 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.physmem_1.actEnergy 337319640 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 184053375 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 746834400 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 443750400 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 79554512970 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 1625780432250 # Energy for precharge background per rank (pJ) 343system.physmem_1.totalEnergy 1891623669435 # Total energy per rank (pJ) 344system.physmem_1.averagePower 669.378136 # Core power per rank (mW) 345system.physmem_1.memoryStateTime::IDLE 2704538486760 # Time in different power states 346system.physmem_1.memoryStateTime::REF 94364400000 # Time in different power states 347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 348system.physmem_1.memoryStateTime::ACT 27044516240 # Time in different power states 349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 350system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 351system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 357system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 360system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 367system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 368system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) 369system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 370system.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 371system.bridge.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 372system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 373system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 374system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 375system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 376system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 377system.cf0.dma_write_txs 631 # Number of DMA write transactions. 378system.cpu0.branchPred.lookups 53058502 # Number of BP lookups 379system.cpu0.branchPred.condPredicted 24374377 # Number of conditional branches predicted 380system.cpu0.branchPred.condIncorrect 933450 # Number of conditional branches incorrect 381system.cpu0.branchPred.BTBLookups 32093175 # Number of BTB lookups 382system.cpu0.branchPred.BTBHits 13944864 # Number of BTB hits 383system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 384system.cpu0.branchPred.BTBHitPct 43.451182 # BTB Hit Percentage 385system.cpu0.branchPred.usedRAS 15470259 # Number of times the RAS was used to get a target. 386system.cpu0.branchPred.RASInCorrect 33206 # Number of incorrect RAS predictions. 387system.cpu0.branchPred.indirectLookups 10120086 # Number of indirect predictor lookups. 388system.cpu0.branchPred.indirectHits 9964746 # Number of indirect target hits. 389system.cpu0.branchPred.indirectMisses 155340 # Number of indirect misses. 390system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. 391system.cpu_clk_domain.clock 500 # Clock period in ticks 392system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 402system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 403system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 404system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 405system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 406system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 410system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 411system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 412system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 414system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 416system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 417system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 418system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 419system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 420system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 421system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 422system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 423system.cpu0.dtb.walker.walks 67164 # Table walker walks requested 424system.cpu0.dtb.walker.walksShort 67164 # Table walker walks initiated with short descriptors 425system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25323 # Level at which table walker walks with short descriptors terminate 426system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19031 # Level at which table walker walks with short descriptors terminate 427system.cpu0.dtb.walker.walksSquashedBefore 22810 # Table walks squashed before starting 428system.cpu0.dtb.walker.walkWaitTime::samples 44354 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::mean 458.594490 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::stdev 2953.911408 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::0-8191 43233 97.47% 97.47% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::8192-16383 862 1.94% 99.42% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::16384-24575 108 0.24% 99.66% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.90% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.92% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::total 44354 # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkCompletionTime::samples 17047 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::mean 11038.716490 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::gmean 9658.702439 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::stdev 6683.029230 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::0-16383 15750 92.39% 92.39% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1185 6.95% 99.34% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::32768-49151 75 0.44% 99.78% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::49152-65535 14 0.08% 99.87% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::98304-114687 14 0.08% 99.98% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.01% 99.99% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::total 17047 # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walksPending::samples 85757506152 # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::mean 0.515718 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::stdev 0.512261 # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::0-1 85699757152 99.93% 99.93% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::2-3 40650000 0.05% 99.98% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::4-5 7189500 0.01% 99.99% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::6-7 4730000 0.01% 99.99% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::8-9 1448500 0.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::10-11 1006500 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::12-13 1064000 0.00% 100.00% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::14-15 1646000 0.00% 100.00% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::total 85757506152 # Table walker pending requests distribution 468system.cpu0.dtb.walker.walkPageSizes::4K 5272 77.42% 77.42% # Table walker page sizes translated 469system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.58% 100.00% # Table walker page sizes translated 470system.cpu0.dtb.walker.walkPageSizes::total 6810 # Table walker page sizes translated 471system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67164 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67164 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6810 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6810 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin::total 73974 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.inst_hits 0 # ITB inst hits 479system.cpu0.dtb.inst_misses 0 # ITB inst misses 480system.cpu0.dtb.read_hits 23645826 # DTB read hits 481system.cpu0.dtb.read_misses 56383 # DTB read misses 482system.cpu0.dtb.write_hits 17571331 # DTB write hits 483system.cpu0.dtb.write_misses 10781 # DTB write misses 484system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 485system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 488system.cpu0.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB 489system.cpu0.dtb.align_faults 213 # Number of TLB faults due to alignment restrictions 490system.cpu0.dtb.prefetch_faults 2243 # Number of TLB faults due to prefetch 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.dtb.perms_faults 818 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 23702209 # DTB read accesses 494system.cpu0.dtb.write_accesses 17582112 # DTB write accesses 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 496system.cpu0.dtb.hits 41217157 # DTB hits 497system.cpu0.dtb.misses 67164 # DTB misses 498system.cpu0.dtb.accesses 41284321 # DTB accesses 499system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 500system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 509system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 510system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 511system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 512system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 513system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 514system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 515system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 517system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 518system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 519system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 524system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 525system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 526system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 527system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 528system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 529system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 530system.cpu0.itb.walker.walks 10883 # Table walker walks requested 531system.cpu0.itb.walker.walksShort 10883 # Table walker walks initiated with short descriptors 532system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3898 # Level at which table walker walks with short descriptors terminate 533system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5925 # Level at which table walker walks with short descriptors terminate 534system.cpu0.itb.walker.walksSquashedBefore 1060 # Table walks squashed before starting 535system.cpu0.itb.walker.walkWaitTime::samples 9823 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::mean 449.709865 # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::stdev 2327.234590 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::0-4095 9434 96.04% 96.04% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::4096-8191 184 1.87% 97.91% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.61% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.68% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.18% 99.87% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.91% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 549system.cpu0.itb.walker.walkWaitTime::total 9823 # Table walker wait (enqueue to first request) latency 550system.cpu0.itb.walker.walkCompletionTime::samples 3631 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::mean 11923.299367 # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::gmean 11119.549027 # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::stdev 4771.165368 # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::0-8191 614 16.91% 16.91% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::8192-16383 2801 77.14% 94.05% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.96% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.15% # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 0.74% 99.89% # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.97% # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 561system.cpu0.itb.walker.walkCompletionTime::total 3631 # Table walker service (enqueue to completion) latency 562system.cpu0.itb.walker.walksPending::samples 21332036712 # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::mean 0.795904 # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::stdev 0.403169 # Table walker pending requests distribution 565system.cpu0.itb.walker.walksPending::0 4354826000 20.41% 20.41% # Table walker pending requests distribution 566system.cpu0.itb.walker.walksPending::1 16976239212 79.58% 100.00% # Table walker pending requests distribution 567system.cpu0.itb.walker.walksPending::2 901500 0.00% 100.00% # Table walker pending requests distribution 568system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution 569system.cpu0.itb.walker.walksPending::total 21332036712 # Table walker pending requests distribution 570system.cpu0.itb.walker.walkPageSizes::4K 2243 87.24% 87.24% # Table walker page sizes translated 571system.cpu0.itb.walker.walkPageSizes::1M 328 12.76% 100.00% # Table walker page sizes translated 572system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated 573system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10883 # Table walker requests started/completed, data/inst 575system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10883 # Table walker requests started/completed, data/inst 576system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 577system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst 578system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst 579system.cpu0.itb.walker.walkRequestOrigin::total 13454 # Table walker requests started/completed, data/inst 580system.cpu0.itb.inst_hits 72708520 # ITB inst hits 581system.cpu0.itb.inst_misses 10883 # ITB inst misses 582system.cpu0.itb.read_hits 0 # DTB read hits 583system.cpu0.itb.read_misses 0 # DTB read misses 584system.cpu0.itb.write_hits 0 # DTB write hits 585system.cpu0.itb.write_misses 0 # DTB write misses 586system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 587system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 588system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 589system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 590system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB 591system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 592system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 593system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 594system.cpu0.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions 595system.cpu0.itb.read_accesses 0 # DTB read accesses 596system.cpu0.itb.write_accesses 0 # DTB write accesses 597system.cpu0.itb.inst_accesses 72719403 # ITB inst accesses 598system.cpu0.itb.hits 72708520 # DTB hits 599system.cpu0.itb.misses 10883 # DTB misses 600system.cpu0.itb.accesses 72719403 # DTB accesses 601system.cpu0.numPwrStateTransitions 3678 # Number of power state transitions 602system.cpu0.pwrStateClkGateDist::samples 1839 # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::mean 1481668762.034258 # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::stdev 23877600166.586662 # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::underflows 1061 57.69% 57.69% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.03% 99.73% # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::max_value 499971949600 # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::total 1839 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateResidencyTicks::ON 101158552619 # Cumulative time (in ticks) in various power states 613system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724788853381 # Cumulative time (in ticks) in various power states 614system.cpu0.numCycles 202318013 # number of cpu cycles simulated 615system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 616system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 617system.cpu0.fetch.icacheStallCycles 20370009 # Number of cycles fetch is stalled on an Icache miss 618system.cpu0.fetch.Insts 195788924 # Number of instructions fetch has processed 619system.cpu0.fetch.Branches 53058502 # Number of branches that fetch encountered 620system.cpu0.fetch.predictedBranches 39379869 # Number of branches that fetch has predicted taken 621system.cpu0.fetch.Cycles 174489676 # Number of cycles fetch has run and was not squashing or blocked 622system.cpu0.fetch.SquashCycles 5690920 # Number of cycles fetch has spent squashing 623system.cpu0.fetch.TlbCycles 148682 # Number of cycles fetch has spent waiting for tlb 624system.cpu0.fetch.MiscStallCycles 56911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 625system.cpu0.fetch.PendingTrapStallCycles 412776 # Number of stall cycles due to pending traps 626system.cpu0.fetch.PendingQuiesceStallCycles 413906 # Number of stall cycles due to pending quiesce instructions 627system.cpu0.fetch.IcacheWaitRetryStallCycles 90774 # Number of stall cycles due to full MSHR 628system.cpu0.fetch.CacheLines 72708226 # Number of cache lines fetched 629system.cpu0.fetch.IcacheSquashes 258373 # Number of outstanding Icache misses that were squashed 630system.cpu0.fetch.ItlbSquashes 5359 # Number of outstanding ITLB misses that were squashed 631system.cpu0.fetch.rateDist::samples 198828194 # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::mean 1.203611 # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::stdev 1.307839 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::0 93974548 47.26% 47.26% # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::1 30342793 15.26% 62.53% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::2 14563641 7.32% 69.85% # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::3 59947212 30.15% 100.00% # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 641system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 642system.cpu0.fetch.rateDist::total 198828194 # Number of instructions fetched each cycle (Total) 643system.cpu0.fetch.branchRate 0.262253 # Number of branch fetches per cycle 644system.cpu0.fetch.rate 0.967729 # Number of inst fetches per cycle 645system.cpu0.decode.IdleCycles 25600367 # Number of cycles decode is idle 646system.cpu0.decode.BlockedCycles 106949118 # Number of cycles decode is blocked 647system.cpu0.decode.RunCycles 58799478 # Number of cycles decode is running 648system.cpu0.decode.UnblockCycles 4963264 # Number of cycles decode is unblocking 649system.cpu0.decode.SquashCycles 2515967 # Number of cycles decode is squashing 650system.cpu0.decode.BranchResolved 3058039 # Number of times decode resolved a branch 651system.cpu0.decode.BranchMispred 333585 # Number of times decode detected a branch misprediction 652system.cpu0.decode.DecodedInsts 154217934 # Number of instructions handled by decode 653system.cpu0.decode.SquashedInsts 3811468 # Number of squashed instructions handled by decode 654system.cpu0.rename.SquashCycles 2515967 # Number of cycles rename is squashing 655system.cpu0.rename.IdleCycles 34209280 # Number of cycles rename is idle 656system.cpu0.rename.BlockCycles 12450122 # Number of cycles rename is blocking 657system.cpu0.rename.serializeStallCycles 83570932 # count of cycles rename stalled for serializing inst 658system.cpu0.rename.RunCycles 55016631 # Number of cycles rename is running 659system.cpu0.rename.UnblockCycles 11065262 # Number of cycles rename is unblocking 660system.cpu0.rename.RenamedInsts 137539344 # Number of instructions processed by rename 661system.cpu0.rename.SquashedInsts 1033397 # Number of squashed instructions processed by rename 662system.cpu0.rename.ROBFullEvents 1452682 # Number of times rename has blocked due to ROB full 663system.cpu0.rename.IQFullEvents 164882 # Number of times rename has blocked due to IQ full 664system.cpu0.rename.LQFullEvents 58749 # Number of times rename has blocked due to LQ full 665system.cpu0.rename.SQFullEvents 6858829 # Number of times rename has blocked due to SQ full 666system.cpu0.rename.RenamedOperands 141646141 # Number of destination operands rename has renamed 667system.cpu0.rename.RenameLookups 634543216 # Number of register rename lookups that rename has made 668system.cpu0.rename.int_rename_lookups 152633070 # Number of integer rename lookups 669system.cpu0.rename.fp_rename_lookups 9368 # Number of floating rename lookups 670system.cpu0.rename.CommittedMaps 130461493 # Number of HB maps that are committed 671system.cpu0.rename.UndoneMaps 11184637 # Number of HB maps that are undone due to squashing 672system.cpu0.rename.serializingInsts 2697680 # count of serializing insts renamed 673system.cpu0.rename.tempSerializingInsts 2556046 # count of temporary serializing insts renamed 674system.cpu0.rename.skidInsts 22573700 # count of insts added to the skid buffer 675system.cpu0.memDep0.insertedLoads 24576087 # Number of loads inserted to the mem dependence unit. 676system.cpu0.memDep0.insertedStores 19059052 # Number of stores inserted to the mem dependence unit. 677system.cpu0.memDep0.conflictingLoads 1700091 # Number of conflicting loads. 678system.cpu0.memDep0.conflictingStores 2321608 # Number of conflicting stores. 679system.cpu0.iq.iqInstsAdded 134608055 # Number of instructions added to the IQ (excludes non-spec) 680system.cpu0.iq.iqNonSpecInstsAdded 1714170 # Number of non-speculative instructions added to the IQ 681system.cpu0.iq.iqInstsIssued 132746710 # Number of instructions issued 682system.cpu0.iq.iqSquashedInstsIssued 453040 # Number of squashed instructions issued 683system.cpu0.iq.iqSquashedInstsExamined 10578491 # Number of squashed instructions iterated over during squash; mainly for profiling 684system.cpu0.iq.iqSquashedOperandsExamined 21717645 # Number of squashed operands that are examined and possibly removed from graph 685system.cpu0.iq.iqSquashedNonSpecRemoved 121089 # Number of squashed non-spec instructions that were removed 686system.cpu0.iq.issued_per_cycle::samples 198828194 # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::mean 0.667645 # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::stdev 0.963186 # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::0 122140771 61.43% 61.43% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::1 33611714 16.90% 78.34% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::2 31218891 15.70% 94.04% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::3 10730115 5.40% 99.43% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::4 1126646 0.57% 100.00% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 701system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 702system.cpu0.iq.issued_per_cycle::total 198828194 # Number of insts issued each cycle 703system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 704system.cpu0.iq.fu_full::IntAlu 10786366 43.89% 43.89% # attempts to use FU when none available 705system.cpu0.iq.fu_full::IntMult 65 0.00% 43.89% # attempts to use FU when none available 706system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.89% # attempts to use FU when none available 707system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.89% # attempts to use FU when none available 708system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.89% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.89% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.89% # attempts to use FU when none available 711system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.89% # attempts to use FU when none available 712system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.89% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.89% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.89% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.89% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.89% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.89% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.89% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.89% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.89% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.89% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.89% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.89% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.89% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.89% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.89% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.89% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.89% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.89% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.89% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.89% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.89% # attempts to use FU when none available 733system.cpu0.iq.fu_full::MemRead 5629308 22.91% 66.79% # attempts to use FU when none available 734system.cpu0.iq.fu_full::MemWrite 8160859 33.21% 100.00% # attempts to use FU when none available 735system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 736system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 737system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued 738system.cpu0.iq.FU_type_0::IntAlu 89668905 67.55% 67.55% # Type of FU issued 739system.cpu0.iq.FU_type_0::IntMult 111084 0.08% 67.63% # Type of FU issued 740system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued 741system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued 742system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued 743system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.63% # Type of FU issued 744system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.63% # Type of FU issued 745system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.63% # Type of FU issued 746system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.63% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.63% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.63% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.63% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.63% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.63% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.63% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.63% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.63% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.63% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.63% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.63% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.63% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatMisc 8099 0.01% 67.64% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued 767system.cpu0.iq.FU_type_0::MemRead 24336393 18.33% 85.97% # Type of FU issued 768system.cpu0.iq.FU_type_0::MemWrite 18619956 14.03% 100.00% # Type of FU issued 769system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 770system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 771system.cpu0.iq.FU_type_0::total 132746710 # Type of FU issued 772system.cpu0.iq.rate 0.656129 # Inst issue rate 773system.cpu0.iq.fu_busy_cnt 24576598 # FU busy when requested 774system.cpu0.iq.fu_busy_rate 0.185139 # FU busy rate (busy events/executed inst) 775system.cpu0.iq.int_inst_queue_reads 489318685 # Number of integer instruction queue reads 776system.cpu0.iq.int_inst_queue_writes 146908772 # Number of integer instruction queue writes 777system.cpu0.iq.int_inst_queue_wakeup_accesses 129217545 # Number of integer instruction queue wakeup accesses 778system.cpu0.iq.fp_inst_queue_reads 32566 # Number of floating instruction queue reads 779system.cpu0.iq.fp_inst_queue_writes 11248 # Number of floating instruction queue writes 780system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses 781system.cpu0.iq.int_alu_accesses 157299800 # Number of integer alu accesses 782system.cpu0.iq.fp_alu_accesses 21235 # Number of floating point alu accesses 783system.cpu0.iew.lsq.thread0.forwLoads 365614 # Number of loads that had data forwarded from stores 784system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 785system.cpu0.iew.lsq.thread0.squashedLoads 1914996 # Number of loads squashed 786system.cpu0.iew.lsq.thread0.ignoredResponses 2485 # Number of memory responses ignored because the instruction is squashed 787system.cpu0.iew.lsq.thread0.memOrderViolation 19372 # Number of memory ordering violations 788system.cpu0.iew.lsq.thread0.squashedStores 896753 # Number of stores squashed 789system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 790system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 791system.cpu0.iew.lsq.thread0.rescheduledLoads 121022 # Number of loads that were rescheduled 792system.cpu0.iew.lsq.thread0.cacheBlocked 362352 # Number of times an access to memory failed due to the cache being blocked 793system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 794system.cpu0.iew.iewSquashCycles 2515967 # Number of cycles IEW is squashing 795system.cpu0.iew.iewBlockCycles 1594217 # Number of cycles IEW is blocking 796system.cpu0.iew.iewUnblockCycles 188418 # Number of cycles IEW is unblocking 797system.cpu0.iew.iewDispatchedInsts 136474692 # Number of instructions dispatched to IQ 798system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 799system.cpu0.iew.iewDispLoadInsts 24576087 # Number of dispatched load instructions 800system.cpu0.iew.iewDispStoreInsts 19059052 # Number of dispatched store instructions 801system.cpu0.iew.iewDispNonSpecInsts 876204 # Number of dispatched non-speculative instructions 802system.cpu0.iew.iewIQFullEvents 28441 # Number of times the IQ has become full, causing a stall 803system.cpu0.iew.iewLSQFullEvents 136041 # Number of times the LSQ has become full, causing a stall 804system.cpu0.iew.memOrderViolationEvents 19372 # Number of memory order violations 805system.cpu0.iew.predictedTakenIncorrect 261507 # Number of branches that were predicted taken incorrectly 806system.cpu0.iew.predictedNotTakenIncorrect 398935 # Number of branches that were predicted not taken incorrectly 807system.cpu0.iew.branchMispredicts 660442 # Number of branch mispredicts detected at execute 808system.cpu0.iew.iewExecutedInsts 131715074 # Number of executed instructions 809system.cpu0.iew.iewExecLoadInsts 23894149 # Number of load instructions executed 810system.cpu0.iew.iewExecSquashedInsts 964599 # Number of squashed instructions skipped in execute 811system.cpu0.iew.exec_swp 0 # number of swp insts executed 812system.cpu0.iew.exec_nop 152467 # number of nop insts executed 813system.cpu0.iew.exec_refs 42353114 # number of memory reference insts executed 814system.cpu0.iew.exec_branches 25555008 # Number of branches executed 815system.cpu0.iew.exec_stores 18458965 # Number of stores executed 816system.cpu0.iew.exec_rate 0.651030 # Inst execution rate 817system.cpu0.iew.wb_sent 131158694 # cumulative count of insts sent to commit 818system.cpu0.iew.wb_count 129227262 # cumulative count of insts written-back 819system.cpu0.iew.wb_producers 65946343 # num instructions producing a value 820system.cpu0.iew.wb_consumers 106655009 # num instructions consuming a value 821system.cpu0.iew.wb_rate 0.638733 # insts written-back per cycle 822system.cpu0.iew.wb_fanout 0.618315 # average fanout of values written-back 823system.cpu0.commit.commitSquashedInsts 9548145 # The number of squashed insts skipped by commit 824system.cpu0.commit.commitNonSpecStalls 1593081 # The number of times commit has been forced to stall to communicate backwards 825system.cpu0.commit.branchMispredicts 603957 # The number of times a branch was mispredicted 826system.cpu0.commit.committed_per_cycle::samples 195669167 # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::mean 0.643258 # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::stdev 1.340979 # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::0 135298586 69.15% 69.15% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::1 33412613 17.08% 86.22% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::2 12639367 6.46% 92.68% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::3 3246710 1.66% 94.34% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::4 4896676 2.50% 96.84% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::5 2794942 1.43% 98.27% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::6 1306268 0.67% 98.94% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::7 556762 0.28% 99.22% # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::8 1517243 0.78% 100.00% # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::total 195669167 # Number of insts commited each cycle 843system.cpu0.commit.committedInsts 103932879 # Number of instructions committed 844system.cpu0.commit.committedOps 125865777 # Number of ops (including micro ops) committed 845system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 846system.cpu0.commit.refs 40823389 # Number of memory references committed 847system.cpu0.commit.loads 22661090 # Number of loads committed 848system.cpu0.commit.membars 647148 # Number of memory barriers committed 849system.cpu0.commit.branches 24954311 # Number of branches committed 850system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. 851system.cpu0.commit.int_insts 109885490 # Number of committed integer instructions. 852system.cpu0.commit.function_calls 4835541 # Number of function calls committed. 853system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 854system.cpu0.commit.op_class_0::IntAlu 84925464 67.47% 67.47% # Class of committed instruction 855system.cpu0.commit.op_class_0::IntMult 108825 0.09% 67.56% # Class of committed instruction 856system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction 857system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction 858system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction 859system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.56% # Class of committed instruction 860system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.56% # Class of committed instruction 861system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.56% # Class of committed instruction 862system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.56% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.56% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.56% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.56% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.56% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.56% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.56% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.56% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.56% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.56% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.56% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.56% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.56% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatMisc 8099 0.01% 67.57% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction 883system.cpu0.commit.op_class_0::MemRead 22661090 18.00% 85.57% # Class of committed instruction 884system.cpu0.commit.op_class_0::MemWrite 18162299 14.43% 100.00% # Class of committed instruction 885system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 886system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 887system.cpu0.commit.op_class_0::total 125865777 # Class of committed instruction 888system.cpu0.commit.bw_lim_events 1517243 # number cycles where commit BW limit reached 889system.cpu0.rob.rob_reads 306278084 # The number of ROB reads 890system.cpu0.rob.rob_writes 273977566 # The number of ROB writes 891system.cpu0.timesIdled 123981 # Number of times that the entire CPU went into an idle state and unscheduled itself 892system.cpu0.idleCycles 3489819 # Total number of cycles that the CPU has spent unscheduled due to idling 893system.cpu0.quiesceCycles 5449576943 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 894system.cpu0.committedInsts 103810827 # Number of Instructions Simulated 895system.cpu0.committedOps 125743725 # Number of Ops (including micro ops) Simulated 896system.cpu0.cpi 1.948911 # CPI: Cycles Per Instruction 897system.cpu0.cpi_total 1.948911 # CPI: Total CPI of All Threads 898system.cpu0.ipc 0.513107 # IPC: Instructions Per Cycle 899system.cpu0.ipc_total 0.513107 # IPC: Total IPC of All Threads 900system.cpu0.int_regfile_reads 142709258 # number of integer regfile reads 901system.cpu0.int_regfile_writes 81672792 # number of integer regfile writes 902system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads 903system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 904system.cpu0.cc_regfile_reads 464864695 # number of cc regfile reads 905system.cpu0.cc_regfile_writes 49723023 # number of cc regfile writes 906system.cpu0.misc_regfile_reads 392114938 # number of misc regfile reads 907system.cpu0.misc_regfile_writes 1224736 # number of misc regfile writes 908system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 909system.cpu0.dcache.tags.replacements 709879 # number of replacements 910system.cpu0.dcache.tags.tagsinuse 499.426037 # Cycle average of tags in use 911system.cpu0.dcache.tags.total_refs 37661762 # Total number of references to valid blocks. 912system.cpu0.dcache.tags.sampled_refs 710391 # Sample count of references to valid blocks. 913system.cpu0.dcache.tags.avg_refs 53.015539 # Average number of references to valid blocks. 914system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. 915system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.426037 # Average occupied blocks per requestor 916system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975441 # Average percentage of cache occupancy 917system.cpu0.dcache.tags.occ_percent::total 0.975441 # Average percentage of cache occupancy 918system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 919system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id 920system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id 921system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 922system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 923system.cpu0.dcache.tags.tag_accesses 81162963 # Number of tag accesses 924system.cpu0.dcache.tags.data_accesses 81162963 # Number of data accesses 925system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 926system.cpu0.dcache.ReadReq_hits::cpu0.data 21452365 # number of ReadReq hits 927system.cpu0.dcache.ReadReq_hits::total 21452365 # number of ReadReq hits 928system.cpu0.dcache.WriteReq_hits::cpu0.data 14987011 # number of WriteReq hits 929system.cpu0.dcache.WriteReq_hits::total 14987011 # number of WriteReq hits 930system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308699 # number of SoftPFReq hits 931system.cpu0.dcache.SoftPFReq_hits::total 308699 # number of SoftPFReq hits 932system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363086 # number of LoadLockedReq hits 933system.cpu0.dcache.LoadLockedReq_hits::total 363086 # number of LoadLockedReq hits 934system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361018 # number of StoreCondReq hits 935system.cpu0.dcache.StoreCondReq_hits::total 361018 # number of StoreCondReq hits 936system.cpu0.dcache.demand_hits::cpu0.data 36439376 # number of demand (read+write) hits 937system.cpu0.dcache.demand_hits::total 36439376 # number of demand (read+write) hits 938system.cpu0.dcache.overall_hits::cpu0.data 36748075 # number of overall hits 939system.cpu0.dcache.overall_hits::total 36748075 # number of overall hits 940system.cpu0.dcache.ReadReq_misses::cpu0.data 646473 # number of ReadReq misses 941system.cpu0.dcache.ReadReq_misses::total 646473 # number of ReadReq misses 942system.cpu0.dcache.WriteReq_misses::cpu0.data 1887751 # number of WriteReq misses 943system.cpu0.dcache.WriteReq_misses::total 1887751 # number of WriteReq misses 944system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147620 # number of SoftPFReq misses 945system.cpu0.dcache.SoftPFReq_misses::total 147620 # number of SoftPFReq misses 946system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25081 # number of LoadLockedReq misses 947system.cpu0.dcache.LoadLockedReq_misses::total 25081 # number of LoadLockedReq misses 948system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20154 # number of StoreCondReq misses 949system.cpu0.dcache.StoreCondReq_misses::total 20154 # number of StoreCondReq misses 950system.cpu0.dcache.demand_misses::cpu0.data 2534224 # number of demand (read+write) misses 951system.cpu0.dcache.demand_misses::total 2534224 # number of demand (read+write) misses 952system.cpu0.dcache.overall_misses::cpu0.data 2681844 # number of overall misses 953system.cpu0.dcache.overall_misses::total 2681844 # number of overall misses 954system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8640238000 # number of ReadReq miss cycles 955system.cpu0.dcache.ReadReq_miss_latency::total 8640238000 # number of ReadReq miss cycles 956system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29904279351 # number of WriteReq miss cycles 957system.cpu0.dcache.WriteReq_miss_latency::total 29904279351 # number of WriteReq miss cycles 958system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399794500 # number of LoadLockedReq miss cycles 959system.cpu0.dcache.LoadLockedReq_miss_latency::total 399794500 # number of LoadLockedReq miss cycles 960system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485945500 # number of StoreCondReq miss cycles 961system.cpu0.dcache.StoreCondReq_miss_latency::total 485945500 # number of StoreCondReq miss cycles 962system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 390500 # number of StoreCondFailReq miss cycles 963system.cpu0.dcache.StoreCondFailReq_miss_latency::total 390500 # number of StoreCondFailReq miss cycles 964system.cpu0.dcache.demand_miss_latency::cpu0.data 38544517351 # number of demand (read+write) miss cycles 965system.cpu0.dcache.demand_miss_latency::total 38544517351 # number of demand (read+write) miss cycles 966system.cpu0.dcache.overall_miss_latency::cpu0.data 38544517351 # number of overall miss cycles 967system.cpu0.dcache.overall_miss_latency::total 38544517351 # number of overall miss cycles 968system.cpu0.dcache.ReadReq_accesses::cpu0.data 22098838 # number of ReadReq accesses(hits+misses) 969system.cpu0.dcache.ReadReq_accesses::total 22098838 # number of ReadReq accesses(hits+misses) 970system.cpu0.dcache.WriteReq_accesses::cpu0.data 16874762 # number of WriteReq accesses(hits+misses) 971system.cpu0.dcache.WriteReq_accesses::total 16874762 # number of WriteReq accesses(hits+misses) 972system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456319 # number of SoftPFReq accesses(hits+misses) 973system.cpu0.dcache.SoftPFReq_accesses::total 456319 # number of SoftPFReq accesses(hits+misses) 974system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388167 # number of LoadLockedReq accesses(hits+misses) 975system.cpu0.dcache.LoadLockedReq_accesses::total 388167 # number of LoadLockedReq accesses(hits+misses) 976system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381172 # number of StoreCondReq accesses(hits+misses) 977system.cpu0.dcache.StoreCondReq_accesses::total 381172 # number of StoreCondReq accesses(hits+misses) 978system.cpu0.dcache.demand_accesses::cpu0.data 38973600 # number of demand (read+write) accesses 979system.cpu0.dcache.demand_accesses::total 38973600 # number of demand (read+write) accesses 980system.cpu0.dcache.overall_accesses::cpu0.data 39429919 # number of overall (read+write) accesses 981system.cpu0.dcache.overall_accesses::total 39429919 # number of overall (read+write) accesses 982system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029254 # miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_miss_rate::total 0.029254 # miss rate for ReadReq accesses 984system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111868 # miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_miss_rate::total 0.111868 # miss rate for WriteReq accesses 986system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323502 # miss rate for SoftPFReq accesses 987system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323502 # miss rate for SoftPFReq accesses 988system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064614 # miss rate for LoadLockedReq accesses 989system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064614 # miss rate for LoadLockedReq accesses 990system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052874 # miss rate for StoreCondReq accesses 991system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052874 # miss rate for StoreCondReq accesses 992system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065024 # miss rate for demand accesses 993system.cpu0.dcache.demand_miss_rate::total 0.065024 # miss rate for demand accesses 994system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068015 # miss rate for overall accesses 995system.cpu0.dcache.overall_miss_rate::total 0.068015 # miss rate for overall accesses 996system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13365.195453 # average ReadReq miss latency 997system.cpu0.dcache.ReadReq_avg_miss_latency::total 13365.195453 # average ReadReq miss latency 998system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15841.220241 # average WriteReq miss latency 999system.cpu0.dcache.WriteReq_avg_miss_latency::total 15841.220241 # average WriteReq miss latency 1000system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15940.133966 # average LoadLockedReq miss latency 1001system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15940.133966 # average LoadLockedReq miss latency 1002system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24111.615560 # average StoreCondReq miss latency 1003system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24111.615560 # average StoreCondReq miss latency 1004system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1005system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1006system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15209.593687 # average overall miss latency 1007system.cpu0.dcache.demand_avg_miss_latency::total 15209.593687 # average overall miss latency 1008system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14372.393529 # average overall miss latency 1009system.cpu0.dcache.overall_avg_miss_latency::total 14372.393529 # average overall miss latency 1010system.cpu0.dcache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked 1011system.cpu0.dcache.blocked_cycles::no_targets 4275244 # number of cycles access was blocked 1012system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked 1013system.cpu0.dcache.blocked::no_targets 201901 # number of cycles access was blocked 1014system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.069767 # average number of cycles each access was blocked 1015system.cpu0.dcache.avg_blocked_cycles::no_targets 21.174952 # average number of cycles each access was blocked 1016system.cpu0.dcache.writebacks::writebacks 709879 # number of writebacks 1017system.cpu0.dcache.writebacks::total 709879 # number of writebacks 1018system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 258972 # number of ReadReq MSHR hits 1019system.cpu0.dcache.ReadReq_mshr_hits::total 258972 # number of ReadReq MSHR hits 1020system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563802 # number of WriteReq MSHR hits 1021system.cpu0.dcache.WriteReq_mshr_hits::total 1563802 # number of WriteReq MSHR hits 1022system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18565 # number of LoadLockedReq MSHR hits 1023system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18565 # number of LoadLockedReq MSHR hits 1024system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822774 # number of demand (read+write) MSHR hits 1025system.cpu0.dcache.demand_mshr_hits::total 1822774 # number of demand (read+write) MSHR hits 1026system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822774 # number of overall MSHR hits 1027system.cpu0.dcache.overall_mshr_hits::total 1822774 # number of overall MSHR hits 1028system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387501 # number of ReadReq MSHR misses 1029system.cpu0.dcache.ReadReq_mshr_misses::total 387501 # number of ReadReq MSHR misses 1030system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323949 # number of WriteReq MSHR misses 1031system.cpu0.dcache.WriteReq_mshr_misses::total 323949 # number of WriteReq MSHR misses 1032system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101413 # number of SoftPFReq MSHR misses 1033system.cpu0.dcache.SoftPFReq_mshr_misses::total 101413 # number of SoftPFReq MSHR misses 1034system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6516 # number of LoadLockedReq MSHR misses 1035system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6516 # number of LoadLockedReq MSHR misses 1036system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20154 # number of StoreCondReq MSHR misses 1037system.cpu0.dcache.StoreCondReq_mshr_misses::total 20154 # number of StoreCondReq MSHR misses 1038system.cpu0.dcache.demand_mshr_misses::cpu0.data 711450 # number of demand (read+write) MSHR misses 1039system.cpu0.dcache.demand_mshr_misses::total 711450 # number of demand (read+write) MSHR misses 1040system.cpu0.dcache.overall_mshr_misses::cpu0.data 812863 # number of overall MSHR misses 1041system.cpu0.dcache.overall_mshr_misses::total 812863 # number of overall MSHR misses 1042system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31772 # number of ReadReq MSHR uncacheable 1043system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31772 # number of ReadReq MSHR uncacheable 1044system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28451 # number of WriteReq MSHR uncacheable 1045system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28451 # number of WriteReq MSHR uncacheable 1046system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60223 # number of overall MSHR uncacheable misses 1047system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60223 # number of overall MSHR uncacheable misses 1048system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4575351000 # number of ReadReq MSHR miss cycles 1049system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4575351000 # number of ReadReq MSHR miss cycles 1050system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6134433385 # number of WriteReq MSHR miss cycles 1051system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6134433385 # number of WriteReq MSHR miss cycles 1052system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1666291000 # number of SoftPFReq MSHR miss cycles 1053system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1666291000 # number of SoftPFReq MSHR miss cycles 1054system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103051000 # number of LoadLockedReq MSHR miss cycles 1055system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103051000 # number of LoadLockedReq MSHR miss cycles 1056system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 465800500 # number of StoreCondReq MSHR miss cycles 1057system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 465800500 # number of StoreCondReq MSHR miss cycles 1058system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 381500 # number of StoreCondFailReq MSHR miss cycles 1059system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 381500 # number of StoreCondFailReq MSHR miss cycles 1060system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10709784385 # number of demand (read+write) MSHR miss cycles 1061system.cpu0.dcache.demand_mshr_miss_latency::total 10709784385 # number of demand (read+write) MSHR miss cycles 1062system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376075385 # number of overall MSHR miss cycles 1063system.cpu0.dcache.overall_mshr_miss_latency::total 12376075385 # number of overall MSHR miss cycles 1064system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621057500 # number of ReadReq MSHR uncacheable cycles 1065system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621057500 # number of ReadReq MSHR uncacheable cycles 1066system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621057500 # number of overall MSHR uncacheable cycles 1067system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621057500 # number of overall MSHR uncacheable cycles 1068system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017535 # mshr miss rate for ReadReq accesses 1069system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017535 # mshr miss rate for ReadReq accesses 1070system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019197 # mshr miss rate for WriteReq accesses 1071system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019197 # mshr miss rate for WriteReq accesses 1072system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222241 # mshr miss rate for SoftPFReq accesses 1073system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222241 # mshr miss rate for SoftPFReq accesses 1074system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016787 # mshr miss rate for LoadLockedReq accesses 1075system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016787 # mshr miss rate for LoadLockedReq accesses 1076system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052874 # mshr miss rate for StoreCondReq accesses 1077system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052874 # mshr miss rate for StoreCondReq accesses 1078system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018255 # mshr miss rate for demand accesses 1079system.cpu0.dcache.demand_mshr_miss_rate::total 0.018255 # mshr miss rate for demand accesses 1080system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020615 # mshr miss rate for overall accesses 1081system.cpu0.dcache.overall_mshr_miss_rate::total 0.020615 # mshr miss rate for overall accesses 1082system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11807.326949 # average ReadReq mshr miss latency 1083system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11807.326949 # average ReadReq mshr miss latency 1084system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18936.417106 # average WriteReq mshr miss latency 1085system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18936.417106 # average WriteReq mshr miss latency 1086system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16430.743593 # average SoftPFReq mshr miss latency 1087system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16430.743593 # average SoftPFReq mshr miss latency 1088system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15815.070595 # average LoadLockedReq mshr miss latency 1089system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15815.070595 # average LoadLockedReq mshr miss latency 1090system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23112.062122 # average StoreCondReq mshr miss latency 1091system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23112.062122 # average StoreCondReq mshr miss latency 1092system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1093system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1094system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15053.460377 # average overall mshr miss latency 1095system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15053.460377 # average overall mshr miss latency 1096system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15225.290590 # average overall mshr miss latency 1097system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15225.290590 # average overall mshr miss latency 1098system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208392.845902 # average ReadReq mshr uncacheable latency 1099system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208392.845902 # average ReadReq mshr uncacheable latency 1100system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109942.339306 # average overall mshr uncacheable latency 1101system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109942.339306 # average overall mshr uncacheable latency 1102system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1103system.cpu0.icache.tags.replacements 1252995 # number of replacements 1104system.cpu0.icache.tags.tagsinuse 511.762307 # Cycle average of tags in use 1105system.cpu0.icache.tags.total_refs 71397425 # Total number of references to valid blocks. 1106system.cpu0.icache.tags.sampled_refs 1253507 # Sample count of references to valid blocks. 1107system.cpu0.icache.tags.avg_refs 56.958138 # Average number of references to valid blocks. 1108system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. 1109system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762307 # Average occupied blocks per requestor 1110system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999536 # Average percentage of cache occupancy 1111system.cpu0.icache.tags.occ_percent::total 0.999536 # Average percentage of cache occupancy 1112system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1113system.cpu0.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id 1114system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id 1115system.cpu0.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id 1116system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1117system.cpu0.icache.tags.tag_accesses 146662859 # Number of tag accesses 1118system.cpu0.icache.tags.data_accesses 146662859 # Number of data accesses 1119system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1120system.cpu0.icache.ReadReq_hits::cpu0.inst 71397425 # number of ReadReq hits 1121system.cpu0.icache.ReadReq_hits::total 71397425 # number of ReadReq hits 1122system.cpu0.icache.demand_hits::cpu0.inst 71397425 # number of demand (read+write) hits 1123system.cpu0.icache.demand_hits::total 71397425 # number of demand (read+write) hits 1124system.cpu0.icache.overall_hits::cpu0.inst 71397425 # number of overall hits 1125system.cpu0.icache.overall_hits::total 71397425 # number of overall hits 1126system.cpu0.icache.ReadReq_misses::cpu0.inst 1307231 # number of ReadReq misses 1127system.cpu0.icache.ReadReq_misses::total 1307231 # number of ReadReq misses 1128system.cpu0.icache.demand_misses::cpu0.inst 1307231 # number of demand (read+write) misses 1129system.cpu0.icache.demand_misses::total 1307231 # number of demand (read+write) misses 1130system.cpu0.icache.overall_misses::cpu0.inst 1307231 # number of overall misses 1131system.cpu0.icache.overall_misses::total 1307231 # number of overall misses 1132system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13217921463 # number of ReadReq miss cycles 1133system.cpu0.icache.ReadReq_miss_latency::total 13217921463 # number of ReadReq miss cycles 1134system.cpu0.icache.demand_miss_latency::cpu0.inst 13217921463 # number of demand (read+write) miss cycles 1135system.cpu0.icache.demand_miss_latency::total 13217921463 # number of demand (read+write) miss cycles 1136system.cpu0.icache.overall_miss_latency::cpu0.inst 13217921463 # number of overall miss cycles 1137system.cpu0.icache.overall_miss_latency::total 13217921463 # number of overall miss cycles 1138system.cpu0.icache.ReadReq_accesses::cpu0.inst 72704656 # number of ReadReq accesses(hits+misses) 1139system.cpu0.icache.ReadReq_accesses::total 72704656 # number of ReadReq accesses(hits+misses) 1140system.cpu0.icache.demand_accesses::cpu0.inst 72704656 # number of demand (read+write) accesses 1141system.cpu0.icache.demand_accesses::total 72704656 # number of demand (read+write) accesses 1142system.cpu0.icache.overall_accesses::cpu0.inst 72704656 # number of overall (read+write) accesses 1143system.cpu0.icache.overall_accesses::total 72704656 # number of overall (read+write) accesses 1144system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017980 # miss rate for ReadReq accesses 1145system.cpu0.icache.ReadReq_miss_rate::total 0.017980 # miss rate for ReadReq accesses 1146system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017980 # miss rate for demand accesses 1147system.cpu0.icache.demand_miss_rate::total 0.017980 # miss rate for demand accesses 1148system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017980 # miss rate for overall accesses 1149system.cpu0.icache.overall_miss_rate::total 0.017980 # miss rate for overall accesses 1150system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10111.389236 # average ReadReq miss latency 1151system.cpu0.icache.ReadReq_avg_miss_latency::total 10111.389236 # average ReadReq miss latency 1152system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10111.389236 # average overall miss latency 1153system.cpu0.icache.demand_avg_miss_latency::total 10111.389236 # average overall miss latency 1154system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10111.389236 # average overall miss latency 1155system.cpu0.icache.overall_avg_miss_latency::total 10111.389236 # average overall miss latency 1156system.cpu0.icache.blocked_cycles::no_mshrs 1578280 # number of cycles access was blocked 1157system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked 1158system.cpu0.icache.blocked::no_mshrs 112202 # number of cycles access was blocked 1159system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked 1160system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.066416 # average number of cycles each access was blocked 1161system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked 1162system.cpu0.icache.writebacks::writebacks 1252995 # number of writebacks 1163system.cpu0.icache.writebacks::total 1252995 # number of writebacks 1164system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53683 # number of ReadReq MSHR hits 1165system.cpu0.icache.ReadReq_mshr_hits::total 53683 # number of ReadReq MSHR hits 1166system.cpu0.icache.demand_mshr_hits::cpu0.inst 53683 # number of demand (read+write) MSHR hits 1167system.cpu0.icache.demand_mshr_hits::total 53683 # number of demand (read+write) MSHR hits 1168system.cpu0.icache.overall_mshr_hits::cpu0.inst 53683 # number of overall MSHR hits 1169system.cpu0.icache.overall_mshr_hits::total 53683 # number of overall MSHR hits 1170system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1253548 # number of ReadReq MSHR misses 1171system.cpu0.icache.ReadReq_mshr_misses::total 1253548 # number of ReadReq MSHR misses 1172system.cpu0.icache.demand_mshr_misses::cpu0.inst 1253548 # number of demand (read+write) MSHR misses 1173system.cpu0.icache.demand_mshr_misses::total 1253548 # number of demand (read+write) MSHR misses 1174system.cpu0.icache.overall_mshr_misses::cpu0.inst 1253548 # number of overall MSHR misses 1175system.cpu0.icache.overall_mshr_misses::total 1253548 # number of overall MSHR misses 1176system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1177system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1178system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1179system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1180system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11993376465 # number of ReadReq MSHR miss cycles 1181system.cpu0.icache.ReadReq_mshr_miss_latency::total 11993376465 # number of ReadReq MSHR miss cycles 1182system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11993376465 # number of demand (read+write) MSHR miss cycles 1183system.cpu0.icache.demand_mshr_miss_latency::total 11993376465 # number of demand (read+write) MSHR miss cycles 1184system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11993376465 # number of overall MSHR miss cycles 1185system.cpu0.icache.overall_mshr_miss_latency::total 11993376465 # number of overall MSHR miss cycles 1186system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles 1187system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles 1188system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles 1189system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles 1190system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for ReadReq accesses 1191system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses 1192system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for demand accesses 1193system.cpu0.icache.demand_mshr_miss_rate::total 0.017242 # mshr miss rate for demand accesses 1194system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for overall accesses 1195system.cpu0.icache.overall_mshr_miss_rate::total 0.017242 # mshr miss rate for overall accesses 1196system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average ReadReq mshr miss latency 1197system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9567.544653 # average ReadReq mshr miss latency 1198system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average overall mshr miss latency 1199system.cpu0.icache.demand_avg_mshr_miss_latency::total 9567.544653 # average overall mshr miss latency 1200system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average overall mshr miss latency 1201system.cpu0.icache.overall_avg_mshr_miss_latency::total 9567.544653 # average overall mshr miss latency 1202system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency 1203system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency 1204system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency 1205system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency 1206system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1207system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837427 # number of hwpf issued 1208system.cpu0.l2cache.prefetcher.pfIdentified 1839978 # number of prefetch candidates identified 1209system.cpu0.l2cache.prefetcher.pfBufferHit 2305 # number of redundant prefetches already in prefetch queue 1210system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1211system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1212system.cpu0.l2cache.prefetcher.pfSpanPage 236878 # number of prefetches not generated due to page crossing 1213system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1214system.cpu0.l2cache.tags.replacements 277234 # number of replacements 1215system.cpu0.l2cache.tags.tagsinuse 16111.552153 # Cycle average of tags in use 1216system.cpu0.l2cache.tags.total_refs 3276769 # Total number of references to valid blocks. 1217system.cpu0.l2cache.tags.sampled_refs 293338 # Sample count of references to valid blocks. 1218system.cpu0.l2cache.tags.avg_refs 11.170626 # Average number of references to valid blocks. 1219system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1220system.cpu0.l2cache.tags.occ_blocks::writebacks 14693.899751 # Average occupied blocks per requestor 1221system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.282247 # Average occupied blocks per requestor 1222system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.429995 # Average occupied blocks per requestor 1223system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1405.940159 # Average occupied blocks per requestor 1224system.cpu0.l2cache.tags.occ_percent::writebacks 0.896844 # Average percentage of cache occupancy 1225system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000689 # Average percentage of cache occupancy 1226system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000026 # Average percentage of cache occupancy 1227system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085812 # Average percentage of cache occupancy 1228system.cpu0.l2cache.tags.occ_percent::total 0.983371 # Average percentage of cache occupancy 1229system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1005 # Occupied blocks per task id 1230system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 1231system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id 1232system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id 1233system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id 1234system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id 1235system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id 1236system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1237system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 1238system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 1239system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 1240system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 460 # Occupied blocks per task id 1241system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4705 # Occupied blocks per task id 1242system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7019 # Occupied blocks per task id 1243system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2801 # Occupied blocks per task id 1244system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061340 # Percentage of cache occupancy per task id 1245system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 1246system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920959 # Percentage of cache occupancy per task id 1247system.cpu0.l2cache.tags.tag_accesses 66263541 # Number of tag accesses 1248system.cpu0.l2cache.tags.data_accesses 66263541 # Number of data accesses 1249system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1250system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55477 # number of ReadReq hits 1251system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13130 # number of ReadReq hits 1252system.cpu0.l2cache.ReadReq_hits::total 68607 # number of ReadReq hits 1253system.cpu0.l2cache.WritebackDirty_hits::writebacks 482403 # number of WritebackDirty hits 1254system.cpu0.l2cache.WritebackDirty_hits::total 482403 # number of WritebackDirty hits 1255system.cpu0.l2cache.WritebackClean_hits::writebacks 1449230 # number of WritebackClean hits 1256system.cpu0.l2cache.WritebackClean_hits::total 1449230 # number of WritebackClean hits 1257system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 1258system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 1259system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221307 # number of ReadExReq hits 1260system.cpu0.l2cache.ReadExReq_hits::total 221307 # number of ReadExReq hits 1261system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1200077 # number of ReadCleanReq hits 1262system.cpu0.l2cache.ReadCleanReq_hits::total 1200077 # number of ReadCleanReq hits 1263system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398579 # number of ReadSharedReq hits 1264system.cpu0.l2cache.ReadSharedReq_hits::total 398579 # number of ReadSharedReq hits 1265system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55477 # number of demand (read+write) hits 1266system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13130 # number of demand (read+write) hits 1267system.cpu0.l2cache.demand_hits::cpu0.inst 1200077 # number of demand (read+write) hits 1268system.cpu0.l2cache.demand_hits::cpu0.data 619886 # number of demand (read+write) hits 1269system.cpu0.l2cache.demand_hits::total 1888570 # number of demand (read+write) hits 1270system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55477 # number of overall hits 1271system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13130 # number of overall hits 1272system.cpu0.l2cache.overall_hits::cpu0.inst 1200077 # number of overall hits 1273system.cpu0.l2cache.overall_hits::cpu0.data 619886 # number of overall hits 1274system.cpu0.l2cache.overall_hits::total 1888570 # number of overall hits 1275system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 420 # number of ReadReq misses 1276system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 151 # number of ReadReq misses 1277system.cpu0.l2cache.ReadReq_misses::total 571 # number of ReadReq misses 1278system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55011 # number of UpgradeReq misses 1279system.cpu0.l2cache.UpgradeReq_misses::total 55011 # number of UpgradeReq misses 1280system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20153 # number of SCUpgradeReq misses 1281system.cpu0.l2cache.SCUpgradeReq_misses::total 20153 # number of SCUpgradeReq misses 1282system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1283system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1284system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47810 # number of ReadExReq misses 1285system.cpu0.l2cache.ReadExReq_misses::total 47810 # number of ReadExReq misses 1286system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 53438 # number of ReadCleanReq misses 1287system.cpu0.l2cache.ReadCleanReq_misses::total 53438 # number of ReadCleanReq misses 1288system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96741 # number of ReadSharedReq misses 1289system.cpu0.l2cache.ReadSharedReq_misses::total 96741 # number of ReadSharedReq misses 1290system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 420 # number of demand (read+write) misses 1291system.cpu0.l2cache.demand_misses::cpu0.itb.walker 151 # number of demand (read+write) misses 1292system.cpu0.l2cache.demand_misses::cpu0.inst 53438 # number of demand (read+write) misses 1293system.cpu0.l2cache.demand_misses::cpu0.data 144551 # number of demand (read+write) misses 1294system.cpu0.l2cache.demand_misses::total 198560 # number of demand (read+write) misses 1295system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 420 # number of overall misses 1296system.cpu0.l2cache.overall_misses::cpu0.itb.walker 151 # number of overall misses 1297system.cpu0.l2cache.overall_misses::cpu0.inst 53438 # number of overall misses 1298system.cpu0.l2cache.overall_misses::cpu0.data 144551 # number of overall misses 1299system.cpu0.l2cache.overall_misses::total 198560 # number of overall misses 1300system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11930500 # number of ReadReq miss cycles 1301system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3564500 # number of ReadReq miss cycles 1302system.cpu0.l2cache.ReadReq_miss_latency::total 15495000 # number of ReadReq miss cycles 1303system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 109148000 # number of UpgradeReq miss cycles 1304system.cpu0.l2cache.UpgradeReq_miss_latency::total 109148000 # number of UpgradeReq miss cycles 1305system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 23796000 # number of SCUpgradeReq miss cycles 1306system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 23796000 # number of SCUpgradeReq miss cycles 1307system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 365500 # number of SCUpgradeFailReq miss cycles 1308system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 365500 # number of SCUpgradeFailReq miss cycles 1309system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2790491998 # number of ReadExReq miss cycles 1310system.cpu0.l2cache.ReadExReq_miss_latency::total 2790491998 # number of ReadExReq miss cycles 1311system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2793539000 # number of ReadCleanReq miss cycles 1312system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2793539000 # number of ReadCleanReq miss cycles 1313system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2953442497 # number of ReadSharedReq miss cycles 1314system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2953442497 # number of ReadSharedReq miss cycles 1315system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11930500 # number of demand (read+write) miss cycles 1316system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3564500 # number of demand (read+write) miss cycles 1317system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2793539000 # number of demand (read+write) miss cycles 1318system.cpu0.l2cache.demand_miss_latency::cpu0.data 5743934495 # number of demand (read+write) miss cycles 1319system.cpu0.l2cache.demand_miss_latency::total 8552968495 # number of demand (read+write) miss cycles 1320system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11930500 # number of overall miss cycles 1321system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3564500 # number of overall miss cycles 1322system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2793539000 # number of overall miss cycles 1323system.cpu0.l2cache.overall_miss_latency::cpu0.data 5743934495 # number of overall miss cycles 1324system.cpu0.l2cache.overall_miss_latency::total 8552968495 # number of overall miss cycles 1325system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55897 # number of ReadReq accesses(hits+misses) 1326system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13281 # number of ReadReq accesses(hits+misses) 1327system.cpu0.l2cache.ReadReq_accesses::total 69178 # number of ReadReq accesses(hits+misses) 1328system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482403 # number of WritebackDirty accesses(hits+misses) 1329system.cpu0.l2cache.WritebackDirty_accesses::total 482403 # number of WritebackDirty accesses(hits+misses) 1330system.cpu0.l2cache.WritebackClean_accesses::writebacks 1449230 # number of WritebackClean accesses(hits+misses) 1331system.cpu0.l2cache.WritebackClean_accesses::total 1449230 # number of WritebackClean accesses(hits+misses) 1332system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55012 # number of UpgradeReq accesses(hits+misses) 1333system.cpu0.l2cache.UpgradeReq_accesses::total 55012 # number of UpgradeReq accesses(hits+misses) 1334system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20153 # number of SCUpgradeReq accesses(hits+misses) 1335system.cpu0.l2cache.SCUpgradeReq_accesses::total 20153 # number of SCUpgradeReq accesses(hits+misses) 1336system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1337system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1338system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269117 # number of ReadExReq accesses(hits+misses) 1339system.cpu0.l2cache.ReadExReq_accesses::total 269117 # number of ReadExReq accesses(hits+misses) 1340system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1253515 # number of ReadCleanReq accesses(hits+misses) 1341system.cpu0.l2cache.ReadCleanReq_accesses::total 1253515 # number of ReadCleanReq accesses(hits+misses) 1342system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 495320 # number of ReadSharedReq accesses(hits+misses) 1343system.cpu0.l2cache.ReadSharedReq_accesses::total 495320 # number of ReadSharedReq accesses(hits+misses) 1344system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55897 # number of demand (read+write) accesses 1345system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13281 # number of demand (read+write) accesses 1346system.cpu0.l2cache.demand_accesses::cpu0.inst 1253515 # number of demand (read+write) accesses 1347system.cpu0.l2cache.demand_accesses::cpu0.data 764437 # number of demand (read+write) accesses 1348system.cpu0.l2cache.demand_accesses::total 2087130 # number of demand (read+write) accesses 1349system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55897 # number of overall (read+write) accesses 1350system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13281 # number of overall (read+write) accesses 1351system.cpu0.l2cache.overall_accesses::cpu0.inst 1253515 # number of overall (read+write) accesses 1352system.cpu0.l2cache.overall_accesses::cpu0.data 764437 # number of overall (read+write) accesses 1353system.cpu0.l2cache.overall_accesses::total 2087130 # number of overall (read+write) accesses 1354system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007514 # miss rate for ReadReq accesses 1355system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.011370 # miss rate for ReadReq accesses 1356system.cpu0.l2cache.ReadReq_miss_rate::total 0.008254 # miss rate for ReadReq accesses 1357system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses 1358system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses 1359system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1360system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1361system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1362system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1363system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.177655 # miss rate for ReadExReq accesses 1364system.cpu0.l2cache.ReadExReq_miss_rate::total 0.177655 # miss rate for ReadExReq accesses 1365system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042631 # miss rate for ReadCleanReq accesses 1366system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042631 # miss rate for ReadCleanReq accesses 1367system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.195310 # miss rate for ReadSharedReq accesses 1368system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.195310 # miss rate for ReadSharedReq accesses 1369system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007514 # miss rate for demand accesses 1370system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.011370 # miss rate for demand accesses 1371system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042631 # miss rate for demand accesses 1372system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189095 # miss rate for demand accesses 1373system.cpu0.l2cache.demand_miss_rate::total 0.095135 # miss rate for demand accesses 1374system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007514 # miss rate for overall accesses 1375system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.011370 # miss rate for overall accesses 1376system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042631 # miss rate for overall accesses 1377system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189095 # miss rate for overall accesses 1378system.cpu0.l2cache.overall_miss_rate::total 0.095135 # miss rate for overall accesses 1379system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28405.952381 # average ReadReq miss latency 1380system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23605.960265 # average ReadReq miss latency 1381system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27136.602452 # average ReadReq miss latency 1382system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1984.112268 # average UpgradeReq miss latency 1383system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1984.112268 # average UpgradeReq miss latency 1384system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1180.767131 # average SCUpgradeReq miss latency 1385system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1180.767131 # average SCUpgradeReq miss latency 1386system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 365500 # average SCUpgradeFailReq miss latency 1387system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 365500 # average SCUpgradeFailReq miss latency 1388system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 58366.283163 # average ReadExReq miss latency 1389system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 58366.283163 # average ReadExReq miss latency 1390system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52276.264082 # average ReadCleanReq miss latency 1391system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52276.264082 # average ReadCleanReq miss latency 1392system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30529.377379 # average ReadSharedReq miss latency 1393system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30529.377379 # average ReadSharedReq miss latency 1394system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28405.952381 # average overall miss latency 1395system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23605.960265 # average overall miss latency 1396system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52276.264082 # average overall miss latency 1397system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39736.387123 # average overall miss latency 1398system.cpu0.l2cache.demand_avg_miss_latency::total 43074.982348 # average overall miss latency 1399system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28405.952381 # average overall miss latency 1400system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23605.960265 # average overall miss latency 1401system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52276.264082 # average overall miss latency 1402system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39736.387123 # average overall miss latency 1403system.cpu0.l2cache.overall_avg_miss_latency::total 43074.982348 # average overall miss latency 1404system.cpu0.l2cache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked 1405system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1406system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked 1407system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1408system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 1409system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1410system.cpu0.l2cache.unused_prefetches 10219 # number of HardPF blocks evicted w/o reference 1411system.cpu0.l2cache.writebacks::writebacks 230013 # number of writebacks 1412system.cpu0.l2cache.writebacks::total 230013 # number of writebacks 1413system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5832 # number of ReadExReq MSHR hits 1414system.cpu0.l2cache.ReadExReq_mshr_hits::total 5832 # number of ReadExReq MSHR hits 1415system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 47 # number of ReadCleanReq MSHR hits 1416system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 47 # number of ReadCleanReq MSHR hits 1417system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 763 # number of ReadSharedReq MSHR hits 1418system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 763 # number of ReadSharedReq MSHR hits 1419system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 47 # number of demand (read+write) MSHR hits 1420system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6595 # number of demand (read+write) MSHR hits 1421system.cpu0.l2cache.demand_mshr_hits::total 6642 # number of demand (read+write) MSHR hits 1422system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 47 # number of overall MSHR hits 1423system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6595 # number of overall MSHR hits 1424system.cpu0.l2cache.overall_mshr_hits::total 6642 # number of overall MSHR hits 1425system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 420 # number of ReadReq MSHR misses 1426system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 151 # number of ReadReq MSHR misses 1427system.cpu0.l2cache.ReadReq_mshr_misses::total 571 # number of ReadReq MSHR misses 1428system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 257265 # number of HardPFReq MSHR misses 1429system.cpu0.l2cache.HardPFReq_mshr_misses::total 257265 # number of HardPFReq MSHR misses 1430system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55011 # number of UpgradeReq MSHR misses 1431system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55011 # number of UpgradeReq MSHR misses 1432system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20153 # number of SCUpgradeReq MSHR misses 1433system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20153 # number of SCUpgradeReq MSHR misses 1434system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1435system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1436system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41978 # number of ReadExReq MSHR misses 1437system.cpu0.l2cache.ReadExReq_mshr_misses::total 41978 # number of ReadExReq MSHR misses 1438system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 53391 # number of ReadCleanReq MSHR misses 1439system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 53391 # number of ReadCleanReq MSHR misses 1440system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95978 # number of ReadSharedReq MSHR misses 1441system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95978 # number of ReadSharedReq MSHR misses 1442system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 420 # number of demand (read+write) MSHR misses 1443system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 151 # number of demand (read+write) MSHR misses 1444system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 53391 # number of demand (read+write) MSHR misses 1445system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137956 # number of demand (read+write) MSHR misses 1446system.cpu0.l2cache.demand_mshr_misses::total 191918 # number of demand (read+write) MSHR misses 1447system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 420 # number of overall MSHR misses 1448system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 151 # number of overall MSHR misses 1449system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 53391 # number of overall MSHR misses 1450system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137956 # number of overall MSHR misses 1451system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 257265 # number of overall MSHR misses 1452system.cpu0.l2cache.overall_mshr_misses::total 449183 # number of overall MSHR misses 1453system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1454system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31772 # number of ReadReq MSHR uncacheable 1455system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34775 # number of ReadReq MSHR uncacheable 1456system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28451 # number of WriteReq MSHR uncacheable 1457system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28451 # number of WriteReq MSHR uncacheable 1458system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1459system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60223 # number of overall MSHR uncacheable misses 1460system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63226 # number of overall MSHR uncacheable misses 1461system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9410500 # number of ReadReq MSHR miss cycles 1462system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2658500 # number of ReadReq MSHR miss cycles 1463system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12069000 # number of ReadReq MSHR miss cycles 1464system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15460252226 # number of HardPFReq MSHR miss cycles 1465system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15460252226 # number of HardPFReq MSHR miss cycles 1466system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1068009500 # number of UpgradeReq MSHR miss cycles 1467system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1068009500 # number of UpgradeReq MSHR miss cycles 1468system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 313481500 # number of SCUpgradeReq MSHR miss cycles 1469system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 313481500 # number of SCUpgradeReq MSHR miss cycles 1470system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 311500 # number of SCUpgradeFailReq MSHR miss cycles 1471system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 311500 # number of SCUpgradeFailReq MSHR miss cycles 1472system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1799415000 # number of ReadExReq MSHR miss cycles 1473system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1799415000 # number of ReadExReq MSHR miss cycles 1474system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2471910000 # number of ReadCleanReq MSHR miss cycles 1475system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2471910000 # number of ReadCleanReq MSHR miss cycles 1476system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2337830497 # number of ReadSharedReq MSHR miss cycles 1477system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2337830497 # number of ReadSharedReq MSHR miss cycles 1478system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9410500 # number of demand (read+write) MSHR miss cycles 1479system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2658500 # number of demand (read+write) MSHR miss cycles 1480system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2471910000 # number of demand (read+write) MSHR miss cycles 1481system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4137245497 # number of demand (read+write) MSHR miss cycles 1482system.cpu0.l2cache.demand_mshr_miss_latency::total 6621224497 # number of demand (read+write) MSHR miss cycles 1483system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9410500 # number of overall MSHR miss cycles 1484system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2658500 # number of overall MSHR miss cycles 1485system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2471910000 # number of overall MSHR miss cycles 1486system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4137245497 # number of overall MSHR miss cycles 1487system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15460252226 # number of overall MSHR miss cycles 1488system.cpu0.l2cache.overall_mshr_miss_latency::total 22081476723 # number of overall MSHR miss cycles 1489system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles 1490system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366599000 # number of ReadReq MSHR uncacheable cycles 1491system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613220000 # number of ReadReq MSHR uncacheable cycles 1492system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles 1493system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366599000 # number of overall MSHR uncacheable cycles 1494system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613220000 # number of overall MSHR uncacheable cycles 1495system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for ReadReq accesses 1496system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for ReadReq accesses 1497system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008254 # mshr miss rate for ReadReq accesses 1498system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1499system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1500system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses 1501system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses 1502system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1503system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1504system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1505system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1506system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155984 # mshr miss rate for ReadExReq accesses 1507system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155984 # mshr miss rate for ReadExReq accesses 1508system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for ReadCleanReq accesses 1509system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042593 # mshr miss rate for ReadCleanReq accesses 1510system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193770 # mshr miss rate for ReadSharedReq accesses 1511system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193770 # mshr miss rate for ReadSharedReq accesses 1512system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for demand accesses 1513system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for demand accesses 1514system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for demand accesses 1515system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for demand accesses 1516system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091953 # mshr miss rate for demand accesses 1517system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for overall accesses 1518system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for overall accesses 1519system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for overall accesses 1520system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for overall accesses 1521system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1522system.cpu0.l2cache.overall_mshr_miss_rate::total 0.215216 # mshr miss rate for overall accesses 1523system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average ReadReq mshr miss latency 1524system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average ReadReq mshr miss latency 1525system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21136.602452 # average ReadReq mshr miss latency 1526system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average HardPFReq mshr miss latency 1527system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60094.658138 # average HardPFReq mshr miss latency 1528system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19414.471651 # average UpgradeReq mshr miss latency 1529system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19414.471651 # average UpgradeReq mshr miss latency 1530system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15555.078648 # average SCUpgradeReq mshr miss latency 1531system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15555.078648 # average SCUpgradeReq mshr miss latency 1532system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency 1533system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency 1534system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42865.667731 # average ReadExReq mshr miss latency 1535system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42865.667731 # average ReadExReq mshr miss latency 1536system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average ReadCleanReq mshr miss latency 1537system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46298.252514 # average ReadCleanReq mshr miss latency 1538system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24357.983048 # average ReadSharedReq mshr miss latency 1539system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24357.983048 # average ReadSharedReq mshr miss latency 1540system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency 1541system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency 1542system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency 1543system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency 1544system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34500.278749 # average overall mshr miss latency 1545system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency 1546system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency 1547system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency 1548system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency 1549system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average overall mshr miss latency 1550system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49159.199531 # average overall mshr miss latency 1551system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency 1552system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200383.954425 # average ReadReq mshr uncacheable latency 1553system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190171.675054 # average ReadReq mshr uncacheable latency 1554system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency 1555system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105717.068230 # average overall mshr uncacheable latency 1556system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104596.526745 # average overall mshr uncacheable latency 1557system.cpu0.toL2Bus.snoop_filter.tot_requests 4076758 # Total number of requests made to the snoop filter. 1558system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058809 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1559system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31269 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1560system.cpu0.toL2Bus.snoop_filter.tot_snoops 324106 # Total number of snoops made to the snoop filter. 1561system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 319070 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1562system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5036 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1563system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1564system.cpu0.toL2Bus.trans_dist::ReadReq 113929 # Transaction distribution 1565system.cpu0.toL2Bus.trans_dist::ReadResp 1910818 # Transaction distribution 1566system.cpu0.toL2Bus.trans_dist::WriteReq 28451 # Transaction distribution 1567system.cpu0.toL2Bus.trans_dist::WriteResp 28451 # Transaction distribution 1568system.cpu0.toL2Bus.trans_dist::WritebackDirty 712670 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::WritebackClean 1480466 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::CleanEvict 204485 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::HardPFReq 327834 # Transaction distribution 1572system.cpu0.toL2Bus.trans_dist::UpgradeReq 86644 # Transaction distribution 1573system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42628 # Transaction distribution 1574system.cpu0.toL2Bus.trans_dist::UpgradeResp 112569 # Transaction distribution 1575system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 27 # Transaction distribution 1576system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution 1577system.cpu0.toL2Bus.trans_dist::ReadExReq 287578 # Transaction distribution 1578system.cpu0.toL2Bus.trans_dist::ReadExResp 284142 # Transaction distribution 1579system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1253548 # Transaction distribution 1580system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576173 # Transaction distribution 1581system.cpu0.toL2Bus.trans_dist::InvalidateReq 3244 # Transaction distribution 1582system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3766063 # Packet count per connected master and slave (bytes) 1583system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2610032 # Packet count per connected master and slave (bytes) 1584system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29029 # Packet count per connected master and slave (bytes) 1585system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119282 # Packet count per connected master and slave (bytes) 1586system.cpu0.toL2Bus.pkt_count::total 6524406 # Packet count per connected master and slave (bytes) 1587system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160464624 # Cumulative packet size per connected master and slave (bytes) 1588system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98586020 # Cumulative packet size per connected master and slave (bytes) 1589system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53124 # Cumulative packet size per connected master and slave (bytes) 1590system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) 1591system.cpu0.toL2Bus.pkt_size::total 259327356 # Cumulative packet size per connected master and slave (bytes) 1592system.cpu0.toL2Bus.snoops 1029792 # Total snoops (count) 1593system.cpu0.toL2Bus.snoopTraffic 18816792 # Total snoop traffic (bytes) 1594system.cpu0.toL2Bus.snoop_fanout::samples 3154811 # Request fanout histogram 1595system.cpu0.toL2Bus.snoop_fanout::mean 0.120834 # Request fanout histogram 1596system.cpu0.toL2Bus.snoop_fanout::stdev 0.330795 # Request fanout histogram 1597system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1598system.cpu0.toL2Bus.snoop_fanout::0 2778640 88.08% 88.08% # Request fanout histogram 1599system.cpu0.toL2Bus.snoop_fanout::1 371135 11.76% 99.84% # Request fanout histogram 1600system.cpu0.toL2Bus.snoop_fanout::2 5036 0.16% 100.00% # Request fanout histogram 1601system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1602system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1603system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1604system.cpu0.toL2Bus.snoop_fanout::total 3154811 # Request fanout histogram 1605system.cpu0.toL2Bus.reqLayer0.occupancy 4076288994 # Layer occupancy (ticks) 1606system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1607system.cpu0.toL2Bus.snoopLayer0.occupancy 113402059 # Layer occupancy (ticks) 1608system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1609system.cpu0.toL2Bus.respLayer0.occupancy 1883892360 # Layer occupancy (ticks) 1610system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1611system.cpu0.toL2Bus.respLayer1.occupancy 1231592300 # Layer occupancy (ticks) 1612system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1613system.cpu0.toL2Bus.respLayer2.occupancy 15761972 # Layer occupancy (ticks) 1614system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1615system.cpu0.toL2Bus.respLayer3.occupancy 63433401 # Layer occupancy (ticks) 1616system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1617system.cpu1.branchPred.lookups 4691512 # Number of BP lookups 1618system.cpu1.branchPred.condPredicted 2780704 # Number of conditional branches predicted 1619system.cpu1.branchPred.condIncorrect 269312 # Number of conditional branches incorrect 1620system.cpu1.branchPred.BTBLookups 2468444 # Number of BTB lookups 1621system.cpu1.branchPred.BTBHits 1570862 # Number of BTB hits 1622system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1623system.cpu1.branchPred.BTBHitPct 63.637741 # BTB Hit Percentage 1624system.cpu1.branchPred.usedRAS 878870 # Number of times the RAS was used to get a target. 1625system.cpu1.branchPred.RASInCorrect 7026 # Number of incorrect RAS predictions. 1626system.cpu1.branchPred.indirectLookups 249224 # Number of indirect predictor lookups. 1627system.cpu1.branchPred.indirectHits 213650 # Number of indirect target hits. 1628system.cpu1.branchPred.indirectMisses 35574 # Number of indirect misses. 1629system.cpu1.branchPredindirectMispredicted 10610 # Number of mispredicted indirect branches. 1630system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1631system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1632system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1639system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1640system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1641system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1642system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1643system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1644system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1645system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1646system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1647system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1648system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1649system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1650system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1651system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1652system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1653system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1654system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1655system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1656system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1657system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1658system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1659system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1660system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1661system.cpu1.dtb.walker.walks 21486 # Table walker walks requested 1662system.cpu1.dtb.walker.walksShort 21486 # Table walker walks initiated with short descriptors 1663system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8656 # Level at which table walker walks with short descriptors terminate 1664system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5913 # Level at which table walker walks with short descriptors terminate 1665system.cpu1.dtb.walker.walksSquashedBefore 6917 # Table walks squashed before starting 1666system.cpu1.dtb.walker.walkWaitTime::samples 14569 # Table walker wait (enqueue to first request) latency 1667system.cpu1.dtb.walker.walkWaitTime::mean 593.417530 # Table walker wait (enqueue to first request) latency 1668system.cpu1.dtb.walker.walkWaitTime::stdev 3219.344489 # Table walker wait (enqueue to first request) latency 1669system.cpu1.dtb.walker.walkWaitTime::0-4095 13924 95.57% 95.57% # Table walker wait (enqueue to first request) latency 1670system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.90% # Table walker wait (enqueue to first request) latency 1671system.cpu1.dtb.walker.walkWaitTime::8192-12287 239 1.64% 98.54% # Table walker wait (enqueue to first request) latency 1672system.cpu1.dtb.walker.walkWaitTime::12288-16383 88 0.60% 99.15% # Table walker wait (enqueue to first request) latency 1673system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.31% # Table walker wait (enqueue to first request) latency 1674system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.11% 99.42% # Table walker wait (enqueue to first request) latency 1675system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.03% 99.46% # Table walker wait (enqueue to first request) latency 1676system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.91% # Table walker wait (enqueue to first request) latency 1677system.cpu1.dtb.walker.walkWaitTime::32768-36863 2 0.01% 99.92% # Table walker wait (enqueue to first request) latency 1678system.cpu1.dtb.walker.walkWaitTime::36864-40959 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency 1679system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1680system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1681system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1682system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1683system.cpu1.dtb.walker.walkWaitTime::total 14569 # Table walker wait (enqueue to first request) latency 1684system.cpu1.dtb.walker.walkCompletionTime::samples 5700 # Table walker service (enqueue to completion) latency 1685system.cpu1.dtb.walker.walkCompletionTime::mean 11230.789474 # Table walker service (enqueue to completion) latency 1686system.cpu1.dtb.walker.walkCompletionTime::gmean 9917.122912 # Table walker service (enqueue to completion) latency 1687system.cpu1.dtb.walker.walkCompletionTime::stdev 6183.592938 # Table walker service (enqueue to completion) latency 1688system.cpu1.dtb.walker.walkCompletionTime::0-8191 1944 34.11% 34.11% # Table walker service (enqueue to completion) latency 1689system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3149 55.25% 89.35% # Table walker service (enqueue to completion) latency 1690system.cpu1.dtb.walker.walkCompletionTime::16384-24575 398 6.98% 96.33% # Table walker service (enqueue to completion) latency 1691system.cpu1.dtb.walker.walkCompletionTime::24576-32767 155 2.72% 99.05% # Table walker service (enqueue to completion) latency 1692system.cpu1.dtb.walker.walkCompletionTime::32768-40959 22 0.39% 99.44% # Table walker service (enqueue to completion) latency 1693system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.42% 99.86% # Table walker service (enqueue to completion) latency 1694system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.95% # Table walker service (enqueue to completion) latency 1695system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency 1696system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 1697system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1698system.cpu1.dtb.walker.walkCompletionTime::total 5700 # Table walker service (enqueue to completion) latency 1699system.cpu1.dtb.walker.walksPending::samples 72594020264 # Table walker pending requests distribution 1700system.cpu1.dtb.walker.walksPending::mean 0.245062 # Table walker pending requests distribution 1701system.cpu1.dtb.walker.walksPending::stdev 0.433850 # Table walker pending requests distribution 1702system.cpu1.dtb.walker.walksPending::0-1 72572506264 99.97% 99.97% # Table walker pending requests distribution 1703system.cpu1.dtb.walker.walksPending::2-3 16659500 0.02% 99.99% # Table walker pending requests distribution 1704system.cpu1.dtb.walker.walksPending::4-5 2233500 0.00% 100.00% # Table walker pending requests distribution 1705system.cpu1.dtb.walker.walksPending::6-7 1798000 0.00% 100.00% # Table walker pending requests distribution 1706system.cpu1.dtb.walker.walksPending::8-9 337000 0.00% 100.00% # Table walker pending requests distribution 1707system.cpu1.dtb.walker.walksPending::10-11 155000 0.00% 100.00% # Table walker pending requests distribution 1708system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution 1709system.cpu1.dtb.walker.walksPending::14-15 133000 0.00% 100.00% # Table walker pending requests distribution 1710system.cpu1.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution 1711system.cpu1.dtb.walker.walksPending::total 72594020264 # Table walker pending requests distribution 1712system.cpu1.dtb.walker.walkPageSizes::4K 1956 73.89% 73.89% # Table walker page sizes translated 1713system.cpu1.dtb.walker.walkPageSizes::1M 691 26.11% 100.00% # Table walker page sizes translated 1714system.cpu1.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated 1715system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21486 # Table walker requests started/completed, data/inst 1716system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1717system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21486 # Table walker requests started/completed, data/inst 1718system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst 1719system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1720system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst 1721system.cpu1.dtb.walker.walkRequestOrigin::total 24133 # Table walker requests started/completed, data/inst 1722system.cpu1.dtb.inst_hits 0 # ITB inst hits 1723system.cpu1.dtb.inst_misses 0 # ITB inst misses 1724system.cpu1.dtb.read_hits 4198525 # DTB read hits 1725system.cpu1.dtb.read_misses 18524 # DTB read misses 1726system.cpu1.dtb.write_hits 3495808 # DTB write hits 1727system.cpu1.dtb.write_misses 2962 # DTB write misses 1728system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1729system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1730system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1731system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1732system.cpu1.dtb.flush_entries 1985 # Number of entries that have been flushed from TLB 1733system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions 1734system.cpu1.dtb.prefetch_faults 390 # Number of TLB faults due to prefetch 1735system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1736system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions 1737system.cpu1.dtb.read_accesses 4217049 # DTB read accesses 1738system.cpu1.dtb.write_accesses 3498770 # DTB write accesses 1739system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1740system.cpu1.dtb.hits 7694333 # DTB hits 1741system.cpu1.dtb.misses 21486 # DTB misses 1742system.cpu1.dtb.accesses 7715819 # DTB accesses 1743system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1744system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1748system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1749system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1750system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1751system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1752system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1753system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1754system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1755system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1756system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1757system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1758system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1759system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1760system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1761system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1762system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1763system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1764system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1765system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1766system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1767system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1768system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1769system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1770system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1771system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1772system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1773system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 1774system.cpu1.itb.walker.walks 5992 # Table walker walks requested 1775system.cpu1.itb.walker.walksShort 5992 # Table walker walks initiated with short descriptors 1776system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2735 # Level at which table walker walks with short descriptors terminate 1777system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2646 # Level at which table walker walks with short descriptors terminate 1778system.cpu1.itb.walker.walksSquashedBefore 611 # Table walks squashed before starting 1779system.cpu1.itb.walker.walkWaitTime::samples 5381 # Table walker wait (enqueue to first request) latency 1780system.cpu1.itb.walker.walkWaitTime::mean 357.461438 # Table walker wait (enqueue to first request) latency 1781system.cpu1.itb.walker.walkWaitTime::stdev 2249.604382 # Table walker wait (enqueue to first request) latency 1782system.cpu1.itb.walker.walkWaitTime::0-2047 5186 96.38% 96.38% # Table walker wait (enqueue to first request) latency 1783system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.80% 97.18% # Table walker wait (enqueue to first request) latency 1784system.cpu1.itb.walker.walkWaitTime::4096-6143 39 0.72% 97.90% # Table walker wait (enqueue to first request) latency 1785system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.39% 98.29% # Table walker wait (enqueue to first request) latency 1786system.cpu1.itb.walker.walkWaitTime::8192-10239 21 0.39% 98.68% # Table walker wait (enqueue to first request) latency 1787system.cpu1.itb.walker.walkWaitTime::10240-12287 16 0.30% 98.98% # Table walker wait (enqueue to first request) latency 1788system.cpu1.itb.walker.walkWaitTime::12288-14335 17 0.32% 99.29% # Table walker wait (enqueue to first request) latency 1789system.cpu1.itb.walker.walkWaitTime::14336-16383 9 0.17% 99.46% # Table walker wait (enqueue to first request) latency 1790system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.11% 99.57% # Table walker wait (enqueue to first request) latency 1791system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.04% 99.61% # Table walker wait (enqueue to first request) latency 1792system.cpu1.itb.walker.walkWaitTime::20480-22527 6 0.11% 99.72% # Table walker wait (enqueue to first request) latency 1793system.cpu1.itb.walker.walkWaitTime::22528-24575 3 0.06% 99.78% # Table walker wait (enqueue to first request) latency 1794system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.07% 99.85% # Table walker wait (enqueue to first request) latency 1795system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency 1796system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency 1797system.cpu1.itb.walker.walkWaitTime::30720-32767 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency 1798system.cpu1.itb.walker.walkWaitTime::total 5381 # Table walker wait (enqueue to first request) latency 1799system.cpu1.itb.walker.walkCompletionTime::samples 1781 # Table walker service (enqueue to completion) latency 1800system.cpu1.itb.walker.walkCompletionTime::mean 11779.618192 # Table walker service (enqueue to completion) latency 1801system.cpu1.itb.walker.walkCompletionTime::gmean 10714.112038 # Table walker service (enqueue to completion) latency 1802system.cpu1.itb.walker.walkCompletionTime::stdev 6875.589868 # Table walker service (enqueue to completion) latency 1803system.cpu1.itb.walker.walkCompletionTime::0-16383 1655 92.93% 92.93% # Table walker service (enqueue to completion) latency 1804system.cpu1.itb.walker.walkCompletionTime::16384-32767 93 5.22% 98.15% # Table walker service (enqueue to completion) latency 1805system.cpu1.itb.walker.walkCompletionTime::32768-49151 29 1.63% 99.78% # Table walker service (enqueue to completion) latency 1806system.cpu1.itb.walker.walkCompletionTime::49152-65535 1 0.06% 99.83% # Table walker service (enqueue to completion) latency 1807system.cpu1.itb.walker.walkCompletionTime::65536-81919 1 0.06% 99.89% # Table walker service (enqueue to completion) latency 1808system.cpu1.itb.walker.walkCompletionTime::131072-147455 2 0.11% 100.00% # Table walker service (enqueue to completion) latency 1809system.cpu1.itb.walker.walkCompletionTime::total 1781 # Table walker service (enqueue to completion) latency 1810system.cpu1.itb.walker.walksPending::samples 16739710416 # Table walker pending requests distribution 1811system.cpu1.itb.walker.walksPending::mean 0.877376 # Table walker pending requests distribution 1812system.cpu1.itb.walker.walksPending::stdev 0.328141 # Table walker pending requests distribution 1813system.cpu1.itb.walker.walksPending::0 2053443264 12.27% 12.27% # Table walker pending requests distribution 1814system.cpu1.itb.walker.walksPending::1 14685521152 87.73% 100.00% # Table walker pending requests distribution 1815system.cpu1.itb.walker.walksPending::2 746000 0.00% 100.00% # Table walker pending requests distribution 1816system.cpu1.itb.walker.walksPending::total 16739710416 # Table walker pending requests distribution 1817system.cpu1.itb.walker.walkPageSizes::4K 995 85.04% 85.04% # Table walker page sizes translated 1818system.cpu1.itb.walker.walkPageSizes::1M 175 14.96% 100.00% # Table walker page sizes translated 1819system.cpu1.itb.walker.walkPageSizes::total 1170 # Table walker page sizes translated 1820system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1821system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5992 # Table walker requests started/completed, data/inst 1822system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5992 # Table walker requests started/completed, data/inst 1823system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1824system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1170 # Table walker requests started/completed, data/inst 1825system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1170 # Table walker requests started/completed, data/inst 1826system.cpu1.itb.walker.walkRequestOrigin::total 7162 # Table walker requests started/completed, data/inst 1827system.cpu1.itb.inst_hits 8257878 # ITB inst hits 1828system.cpu1.itb.inst_misses 5992 # ITB inst misses 1829system.cpu1.itb.read_hits 0 # DTB read hits 1830system.cpu1.itb.read_misses 0 # DTB read misses 1831system.cpu1.itb.write_hits 0 # DTB write hits 1832system.cpu1.itb.write_misses 0 # DTB write misses 1833system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1834system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1835system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1836system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1837system.cpu1.itb.flush_entries 1134 # Number of entries that have been flushed from TLB 1838system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1839system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1840system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1841system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions 1842system.cpu1.itb.read_accesses 0 # DTB read accesses 1843system.cpu1.itb.write_accesses 0 # DTB write accesses 1844system.cpu1.itb.inst_accesses 8263870 # ITB inst accesses 1845system.cpu1.itb.hits 8257878 # DTB hits 1846system.cpu1.itb.misses 5992 # DTB misses 1847system.cpu1.itb.accesses 8263870 # DTB accesses 1848system.cpu1.numPwrStateTransitions 5517 # Number of power state transitions 1849system.cpu1.pwrStateClkGateDist::samples 2759 # Distribution of time spent in the clock gated state 1850system.cpu1.pwrStateClkGateDist::mean 1017941071.285973 # Distribution of time spent in the clock gated state 1851system.cpu1.pwrStateClkGateDist::stdev 25840669198.429722 # Distribution of time spent in the clock gated state 1852system.cpu1.pwrStateClkGateDist::underflows 1966 71.26% 71.26% # Distribution of time spent in the clock gated state 1853system.cpu1.pwrStateClkGateDist::1000-5e+10 787 28.52% 99.78% # Distribution of time spent in the clock gated state 1854system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state 1855system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1856system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1857system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1858system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1859system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1860system.cpu1.pwrStateClkGateDist::max_value 959984595936 # Distribution of time spent in the clock gated state 1861system.cpu1.pwrStateClkGateDist::total 2759 # Distribution of time spent in the clock gated state 1862system.cpu1.pwrStateResidencyTicks::ON 17447990322 # Cumulative time (in ticks) in various power states 1863system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808499415678 # Cumulative time (in ticks) in various power states 1864system.cpu1.numCycles 34896767 # number of cpu cycles simulated 1865system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1866system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1867system.cpu1.fetch.icacheStallCycles 8573013 # Number of cycles fetch is stalled on an Icache miss 1868system.cpu1.fetch.Insts 24834691 # Number of instructions fetch has processed 1869system.cpu1.fetch.Branches 4691512 # Number of branches that fetch encountered 1870system.cpu1.fetch.predictedBranches 2663382 # Number of branches that fetch has predicted taken 1871system.cpu1.fetch.Cycles 24575638 # Number of cycles fetch has run and was not squashing or blocked 1872system.cpu1.fetch.SquashCycles 780918 # Number of cycles fetch has spent squashing 1873system.cpu1.fetch.TlbCycles 78787 # Number of cycles fetch has spent waiting for tlb 1874system.cpu1.fetch.MiscStallCycles 29336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1875system.cpu1.fetch.PendingTrapStallCycles 166978 # Number of stall cycles due to pending traps 1876system.cpu1.fetch.PendingQuiesceStallCycles 305850 # Number of stall cycles due to pending quiesce instructions 1877system.cpu1.fetch.IcacheWaitRetryStallCycles 23292 # Number of stall cycles due to full MSHR 1878system.cpu1.fetch.CacheLines 8256698 # Number of cache lines fetched 1879system.cpu1.fetch.IcacheSquashes 107917 # Number of outstanding Icache misses that were squashed 1880system.cpu1.fetch.ItlbSquashes 2264 # Number of outstanding ITLB misses that were squashed 1881system.cpu1.fetch.rateDist::samples 34143353 # Number of instructions fetched each cycle (Total) 1882system.cpu1.fetch.rateDist::mean 0.885357 # Number of instructions fetched each cycle (Total) 1883system.cpu1.fetch.rateDist::stdev 1.219701 # Number of instructions fetched each cycle (Total) 1884system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1885system.cpu1.fetch.rateDist::0 20247760 59.30% 59.30% # Number of instructions fetched each cycle (Total) 1886system.cpu1.fetch.rateDist::1 4892921 14.33% 73.63% # Number of instructions fetched each cycle (Total) 1887system.cpu1.fetch.rateDist::2 1671892 4.90% 78.53% # Number of instructions fetched each cycle (Total) 1888system.cpu1.fetch.rateDist::3 7330780 21.47% 100.00% # Number of instructions fetched each cycle (Total) 1889system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1890system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1891system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1892system.cpu1.fetch.rateDist::total 34143353 # Number of instructions fetched each cycle (Total) 1893system.cpu1.fetch.branchRate 0.134440 # Number of branch fetches per cycle 1894system.cpu1.fetch.rate 0.711662 # Number of inst fetches per cycle 1895system.cpu1.decode.IdleCycles 7142387 # Number of cycles decode is idle 1896system.cpu1.decode.BlockedCycles 16886237 # Number of cycles decode is blocked 1897system.cpu1.decode.RunCycles 8753269 # Number of cycles decode is running 1898system.cpu1.decode.UnblockCycles 1097578 # Number of cycles decode is unblocking 1899system.cpu1.decode.SquashCycles 263882 # Number of cycles decode is squashing 1900system.cpu1.decode.BranchResolved 709919 # Number of times decode resolved a branch 1901system.cpu1.decode.BranchMispred 129188 # Number of times decode detected a branch misprediction 1902system.cpu1.decode.DecodedInsts 23442151 # Number of instructions handled by decode 1903system.cpu1.decode.SquashedInsts 1047211 # Number of squashed instructions handled by decode 1904system.cpu1.rename.SquashCycles 263882 # Number of cycles rename is squashing 1905system.cpu1.rename.IdleCycles 8565513 # Number of cycles rename is idle 1906system.cpu1.rename.BlockCycles 2371212 # Number of cycles rename is blocking 1907system.cpu1.rename.serializeStallCycles 11834998 # count of cycles rename stalled for serializing inst 1908system.cpu1.rename.RunCycles 8406528 # Number of cycles rename is running 1909system.cpu1.rename.UnblockCycles 2701220 # Number of cycles rename is unblocking 1910system.cpu1.rename.RenamedInsts 22274891 # Number of instructions processed by rename 1911system.cpu1.rename.SquashedInsts 187368 # Number of squashed instructions processed by rename 1912system.cpu1.rename.ROBFullEvents 265665 # Number of times rename has blocked due to ROB full 1913system.cpu1.rename.IQFullEvents 37047 # Number of times rename has blocked due to IQ full 1914system.cpu1.rename.LQFullEvents 14963 # Number of times rename has blocked due to LQ full 1915system.cpu1.rename.SQFullEvents 1683318 # Number of times rename has blocked due to SQ full 1916system.cpu1.rename.RenamedOperands 22278743 # Number of destination operands rename has renamed 1917system.cpu1.rename.RenameLookups 103710935 # Number of register rename lookups that rename has made 1918system.cpu1.rename.int_rename_lookups 25664622 # Number of integer rename lookups 1919system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups 1920system.cpu1.rename.CommittedMaps 19882725 # Number of HB maps that are committed 1921system.cpu1.rename.UndoneMaps 2396018 # Number of HB maps that are undone due to squashing 1922system.cpu1.rename.serializingInsts 407656 # count of serializing insts renamed 1923system.cpu1.rename.tempSerializingInsts 334437 # count of temporary serializing insts renamed 1924system.cpu1.rename.skidInsts 2896541 # count of insts added to the skid buffer 1925system.cpu1.memDep0.insertedLoads 4450446 # Number of loads inserted to the mem dependence unit. 1926system.cpu1.memDep0.insertedStores 3799896 # Number of stores inserted to the mem dependence unit. 1927system.cpu1.memDep0.conflictingLoads 626454 # Number of conflicting loads. 1928system.cpu1.memDep0.conflictingStores 628235 # Number of conflicting stores. 1929system.cpu1.iq.iqInstsAdded 21459278 # Number of instructions added to the IQ (excludes non-spec) 1930system.cpu1.iq.iqNonSpecInstsAdded 560382 # Number of non-speculative instructions added to the IQ 1931system.cpu1.iq.iqInstsIssued 21266552 # Number of instructions issued 1932system.cpu1.iq.iqSquashedInstsIssued 92050 # Number of squashed instructions issued 1933system.cpu1.iq.iqSquashedInstsExamined 2043308 # Number of squashed instructions iterated over during squash; mainly for profiling 1934system.cpu1.iq.iqSquashedOperandsExamined 4721488 # Number of squashed operands that are examined and possibly removed from graph 1935system.cpu1.iq.iqSquashedNonSpecRemoved 43321 # Number of squashed non-spec instructions that were removed 1936system.cpu1.iq.issued_per_cycle::samples 34143353 # Number of insts issued each cycle 1937system.cpu1.iq.issued_per_cycle::mean 0.622861 # Number of insts issued each cycle 1938system.cpu1.iq.issued_per_cycle::stdev 0.949388 # Number of insts issued each cycle 1939system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1940system.cpu1.iq.issued_per_cycle::0 21621380 63.33% 63.33% # Number of insts issued each cycle 1941system.cpu1.iq.issued_per_cycle::1 6152293 18.02% 81.34% # Number of insts issued each cycle 1942system.cpu1.iq.issued_per_cycle::2 4252408 12.45% 93.80% # Number of insts issued each cycle 1943system.cpu1.iq.issued_per_cycle::3 1859652 5.45% 99.25% # Number of insts issued each cycle 1944system.cpu1.iq.issued_per_cycle::4 257613 0.75% 100.00% # Number of insts issued each cycle 1945system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle 1946system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1947system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1948system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1949system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1950system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1951system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1952system.cpu1.iq.issued_per_cycle::total 34143353 # Number of insts issued each cycle 1953system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1954system.cpu1.iq.fu_full::IntAlu 1436712 29.87% 29.87% # attempts to use FU when none available 1955system.cpu1.iq.fu_full::IntMult 667 0.01% 29.88% # attempts to use FU when none available 1956system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.88% # attempts to use FU when none available 1957system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.88% # attempts to use FU when none available 1958system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.88% # attempts to use FU when none available 1959system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.88% # attempts to use FU when none available 1960system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.88% # attempts to use FU when none available 1961system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.88% # attempts to use FU when none available 1962system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.88% # attempts to use FU when none available 1963system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.88% # attempts to use FU when none available 1964system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.88% # attempts to use FU when none available 1965system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.88% # attempts to use FU when none available 1966system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.88% # attempts to use FU when none available 1967system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.88% # attempts to use FU when none available 1968system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.88% # attempts to use FU when none available 1969system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.88% # attempts to use FU when none available 1970system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.88% # attempts to use FU when none available 1971system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.88% # attempts to use FU when none available 1972system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.88% # attempts to use FU when none available 1973system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.88% # attempts to use FU when none available 1974system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.88% # attempts to use FU when none available 1975system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.88% # attempts to use FU when none available 1976system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.88% # attempts to use FU when none available 1977system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.88% # attempts to use FU when none available 1978system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.88% # attempts to use FU when none available 1979system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.88% # attempts to use FU when none available 1980system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.88% # attempts to use FU when none available 1981system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.88% # attempts to use FU when none available 1982system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.88% # attempts to use FU when none available 1983system.cpu1.iq.fu_full::MemRead 1615148 33.58% 63.46% # attempts to use FU when none available 1984system.cpu1.iq.fu_full::MemWrite 1757949 36.54% 100.00% # attempts to use FU when none available 1985system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1986system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1987system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued 1988system.cpu1.iq.FU_type_0::IntAlu 13152288 61.84% 61.85% # Type of FU issued 1989system.cpu1.iq.FU_type_0::IntMult 28200 0.13% 61.98% # Type of FU issued 1990system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued 1991system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued 1992system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued 1993system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.98% # Type of FU issued 1994system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.98% # Type of FU issued 1995system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.98% # Type of FU issued 1996system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.98% # Type of FU issued 1997system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.98% # Type of FU issued 1998system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.98% # Type of FU issued 1999system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.98% # Type of FU issued 2000system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.98% # Type of FU issued 2001system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.98% # Type of FU issued 2002system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.98% # Type of FU issued 2003system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.98% # Type of FU issued 2004system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.98% # Type of FU issued 2005system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.98% # Type of FU issued 2006system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.98% # Type of FU issued 2007system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.98% # Type of FU issued 2008system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.98% # Type of FU issued 2009system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Type of FU issued 2010system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued 2011system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued 2012system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued 2013system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.99% # Type of FU issued 2014system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued 2015system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued 2016system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued 2017system.cpu1.iq.FU_type_0::MemRead 4404606 20.71% 82.70% # Type of FU issued 2018system.cpu1.iq.FU_type_0::MemWrite 3678091 17.30% 100.00% # Type of FU issued 2019system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2020system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2021system.cpu1.iq.FU_type_0::total 21266552 # Type of FU issued 2022system.cpu1.iq.rate 0.609413 # Inst issue rate 2023system.cpu1.iq.fu_busy_cnt 4810476 # FU busy when requested 2024system.cpu1.iq.fu_busy_rate 0.226199 # FU busy rate (busy events/executed inst) 2025system.cpu1.iq.int_inst_queue_reads 81572724 # Number of integer instruction queue reads 2026system.cpu1.iq.int_inst_queue_writes 24071099 # Number of integer instruction queue writes 2027system.cpu1.iq.int_inst_queue_wakeup_accesses 20803651 # Number of integer instruction queue wakeup accesses 2028system.cpu1.iq.fp_inst_queue_reads 6259 # Number of floating instruction queue reads 2029system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes 2030system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses 2031system.cpu1.iq.int_alu_accesses 26072828 # Number of integer alu accesses 2032system.cpu1.iq.fp_alu_accesses 4134 # Number of floating point alu accesses 2033system.cpu1.iew.lsq.thread0.forwLoads 87634 # Number of loads that had data forwarded from stores 2034system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2035system.cpu1.iew.lsq.thread0.squashedLoads 411414 # Number of loads squashed 2036system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed 2037system.cpu1.iew.lsq.thread0.memOrderViolation 10207 # Number of memory ordering violations 2038system.cpu1.iew.lsq.thread0.squashedStores 255357 # Number of stores squashed 2039system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2040system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2041system.cpu1.iew.lsq.thread0.rescheduledLoads 40430 # Number of loads that were rescheduled 2042system.cpu1.iew.lsq.thread0.cacheBlocked 77958 # Number of times an access to memory failed due to the cache being blocked 2043system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2044system.cpu1.iew.iewSquashCycles 263882 # Number of cycles IEW is squashing 2045system.cpu1.iew.iewBlockCycles 544522 # Number of cycles IEW is blocking 2046system.cpu1.iew.iewUnblockCycles 96828 # Number of cycles IEW is unblocking 2047system.cpu1.iew.iewDispatchedInsts 22060743 # Number of instructions dispatched to IQ 2048system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2049system.cpu1.iew.iewDispLoadInsts 4450446 # Number of dispatched load instructions 2050system.cpu1.iew.iewDispStoreInsts 3799896 # Number of dispatched store instructions 2051system.cpu1.iew.iewDispNonSpecInsts 297241 # Number of dispatched non-speculative instructions 2052system.cpu1.iew.iewIQFullEvents 7639 # Number of times the IQ has become full, causing a stall 2053system.cpu1.iew.iewLSQFullEvents 82763 # Number of times the LSQ has become full, causing a stall 2054system.cpu1.iew.memOrderViolationEvents 10207 # Number of memory order violations 2055system.cpu1.iew.predictedTakenIncorrect 34804 # Number of branches that were predicted taken incorrectly 2056system.cpu1.iew.predictedNotTakenIncorrect 119058 # Number of branches that were predicted not taken incorrectly 2057system.cpu1.iew.branchMispredicts 153862 # Number of branch mispredicts detected at execute 2058system.cpu1.iew.iewExecutedInsts 21034955 # Number of executed instructions 2059system.cpu1.iew.iewExecLoadInsts 4309085 # Number of load instructions executed 2060system.cpu1.iew.iewExecSquashedInsts 210133 # Number of squashed instructions skipped in execute 2061system.cpu1.iew.exec_swp 0 # number of swp insts executed 2062system.cpu1.iew.exec_nop 41083 # number of nop insts executed 2063system.cpu1.iew.exec_refs 7936975 # number of memory reference insts executed 2064system.cpu1.iew.exec_branches 3061868 # Number of branches executed 2065system.cpu1.iew.exec_stores 3627890 # Number of stores executed 2066system.cpu1.iew.exec_rate 0.602777 # Inst execution rate 2067system.cpu1.iew.wb_sent 20903580 # cumulative count of insts sent to commit 2068system.cpu1.iew.wb_count 20805440 # cumulative count of insts written-back 2069system.cpu1.iew.wb_producers 10431521 # num instructions producing a value 2070system.cpu1.iew.wb_consumers 16355895 # num instructions consuming a value 2071system.cpu1.iew.wb_rate 0.596200 # insts written-back per cycle 2072system.cpu1.iew.wb_fanout 0.637784 # average fanout of values written-back 2073system.cpu1.commit.commitSquashedInsts 1829884 # The number of squashed insts skipped by commit 2074system.cpu1.commit.commitNonSpecStalls 517061 # The number of times commit has been forced to stall to communicate backwards 2075system.cpu1.commit.branchMispredicts 142735 # The number of times a branch was mispredicted 2076system.cpu1.commit.committed_per_cycle::samples 33733433 # Number of insts commited each cycle 2077system.cpu1.commit.committed_per_cycle::mean 0.593157 # Number of insts commited each cycle 2078system.cpu1.commit.committed_per_cycle::stdev 1.351929 # Number of insts commited each cycle 2079system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2080system.cpu1.commit.committed_per_cycle::0 24180502 71.68% 71.68% # Number of insts commited each cycle 2081system.cpu1.commit.committed_per_cycle::1 5607484 16.62% 88.30% # Number of insts commited each cycle 2082system.cpu1.commit.committed_per_cycle::2 1690092 5.01% 93.31% # Number of insts commited each cycle 2083system.cpu1.commit.committed_per_cycle::3 667448 1.98% 95.29% # Number of insts commited each cycle 2084system.cpu1.commit.committed_per_cycle::4 524113 1.55% 96.85% # Number of insts commited each cycle 2085system.cpu1.commit.committed_per_cycle::5 341983 1.01% 97.86% # Number of insts commited each cycle 2086system.cpu1.commit.committed_per_cycle::6 221163 0.66% 98.52% # Number of insts commited each cycle 2087system.cpu1.commit.committed_per_cycle::7 119335 0.35% 98.87% # Number of insts commited each cycle 2088system.cpu1.commit.committed_per_cycle::8 381313 1.13% 100.00% # Number of insts commited each cycle 2089system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2090system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2091system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2092system.cpu1.commit.committed_per_cycle::total 33733433 # Number of insts commited each cycle 2093system.cpu1.commit.committedInsts 16346571 # Number of instructions committed 2094system.cpu1.commit.committedOps 20009206 # Number of ops (including micro ops) committed 2095system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2096system.cpu1.commit.refs 7583571 # Number of memory references committed 2097system.cpu1.commit.loads 4039032 # Number of loads committed 2098system.cpu1.commit.membars 208429 # Number of memory barriers committed 2099system.cpu1.commit.branches 2907402 # Number of branches committed 2100system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. 2101system.cpu1.commit.int_insts 17776817 # Number of committed integer instructions. 2102system.cpu1.commit.function_calls 462681 # Number of function calls committed. 2103system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2104system.cpu1.commit.op_class_0::IntAlu 12395212 61.95% 61.95% # Class of committed instruction 2105system.cpu1.commit.op_class_0::IntMult 27122 0.14% 62.08% # Class of committed instruction 2106system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction 2107system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction 2108system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction 2109system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 62.08% # Class of committed instruction 2110system.cpu1.commit.op_class_0::FloatMult 0 0.00% 62.08% # Class of committed instruction 2111system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 62.08% # Class of committed instruction 2112system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 62.08% # Class of committed instruction 2113system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 62.08% # Class of committed instruction 2114system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 62.08% # Class of committed instruction 2115system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 62.08% # Class of committed instruction 2116system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 62.08% # Class of committed instruction 2117system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 62.08% # Class of committed instruction 2118system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 62.08% # Class of committed instruction 2119system.cpu1.commit.op_class_0::SimdMult 0 0.00% 62.08% # Class of committed instruction 2120system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 62.08% # Class of committed instruction 2121system.cpu1.commit.op_class_0::SimdShift 0 0.00% 62.08% # Class of committed instruction 2122system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 62.08% # Class of committed instruction 2123system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 62.08% # Class of committed instruction 2124system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 62.08% # Class of committed instruction 2125system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # Class of committed instruction 2126system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction 2127system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction 2128system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction 2129system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 62.10% # Class of committed instruction 2130system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction 2131system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction 2132system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction 2133system.cpu1.commit.op_class_0::MemRead 4039032 20.19% 82.29% # Class of committed instruction 2134system.cpu1.commit.op_class_0::MemWrite 3544539 17.71% 100.00% # Class of committed instruction 2135system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2136system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2137system.cpu1.commit.op_class_0::total 20009206 # Class of committed instruction 2138system.cpu1.commit.bw_lim_events 381313 # number cycles where commit BW limit reached 2139system.cpu1.rob.rob_reads 54211090 # The number of ROB reads 2140system.cpu1.rob.rob_writes 44079362 # The number of ROB writes 2141system.cpu1.timesIdled 55353 # Number of times that the entire CPU went into an idle state and unscheduled itself 2142system.cpu1.idleCycles 753414 # Total number of cycles that the CPU has spent unscheduled due to idling 2143system.cpu1.quiesceCycles 5616440201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2144system.cpu1.committedInsts 16313716 # Number of Instructions Simulated 2145system.cpu1.committedOps 19976351 # Number of Ops (including micro ops) Simulated 2146system.cpu1.cpi 2.139106 # CPI: Cycles Per Instruction 2147system.cpu1.cpi_total 2.139106 # CPI: Total CPI of All Threads 2148system.cpu1.ipc 0.467485 # IPC: Instructions Per Cycle 2149system.cpu1.ipc_total 0.467485 # IPC: Total IPC of All Threads 2150system.cpu1.int_regfile_reads 23597502 # number of integer regfile reads 2151system.cpu1.int_regfile_writes 13487852 # number of integer regfile writes 2152system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads 2153system.cpu1.fp_regfile_writes 516 # number of floating regfile writes 2154system.cpu1.cc_regfile_reads 75515975 # number of cc regfile reads 2155system.cpu1.cc_regfile_writes 6821727 # number of cc regfile writes 2156system.cpu1.misc_regfile_reads 68877879 # number of misc regfile reads 2157system.cpu1.misc_regfile_writes 387520 # number of misc regfile writes 2158system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2159system.cpu1.dcache.tags.replacements 189327 # number of replacements 2160system.cpu1.dcache.tags.tagsinuse 472.259638 # Cycle average of tags in use 2161system.cpu1.dcache.tags.total_refs 6803525 # Total number of references to valid blocks. 2162system.cpu1.dcache.tags.sampled_refs 189662 # Sample count of references to valid blocks. 2163system.cpu1.dcache.tags.avg_refs 35.871840 # Average number of references to valid blocks. 2164system.cpu1.dcache.tags.warmup_cycle 103705106000 # Cycle when the warmup percentage was hit. 2165system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.259638 # Average occupied blocks per requestor 2166system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922382 # Average percentage of cache occupancy 2167system.cpu1.dcache.tags.occ_percent::total 0.922382 # Average percentage of cache occupancy 2168system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id 2169system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id 2170system.cpu1.dcache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2171system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id 2172system.cpu1.dcache.tags.tag_accesses 15106665 # Number of tag accesses 2173system.cpu1.dcache.tags.data_accesses 15106665 # Number of data accesses 2174system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2175system.cpu1.dcache.ReadReq_hits::cpu1.data 3632818 # number of ReadReq hits 2176system.cpu1.dcache.ReadReq_hits::total 3632818 # number of ReadReq hits 2177system.cpu1.dcache.WriteReq_hits::cpu1.data 2917516 # number of WriteReq hits 2178system.cpu1.dcache.WriteReq_hits::total 2917516 # number of WriteReq hits 2179system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48925 # number of SoftPFReq hits 2180system.cpu1.dcache.SoftPFReq_hits::total 48925 # number of SoftPFReq hits 2181system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78194 # number of LoadLockedReq hits 2182system.cpu1.dcache.LoadLockedReq_hits::total 78194 # number of LoadLockedReq hits 2183system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70603 # number of StoreCondReq hits 2184system.cpu1.dcache.StoreCondReq_hits::total 70603 # number of StoreCondReq hits 2185system.cpu1.dcache.demand_hits::cpu1.data 6550334 # number of demand (read+write) hits 2186system.cpu1.dcache.demand_hits::total 6550334 # number of demand (read+write) hits 2187system.cpu1.dcache.overall_hits::cpu1.data 6599259 # number of overall hits 2188system.cpu1.dcache.overall_hits::total 6599259 # number of overall hits 2189system.cpu1.dcache.ReadReq_misses::cpu1.data 216356 # number of ReadReq misses 2190system.cpu1.dcache.ReadReq_misses::total 216356 # number of ReadReq misses 2191system.cpu1.dcache.WriteReq_misses::cpu1.data 400081 # number of WriteReq misses 2192system.cpu1.dcache.WriteReq_misses::total 400081 # number of WriteReq misses 2193system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30281 # number of SoftPFReq misses 2194system.cpu1.dcache.SoftPFReq_misses::total 30281 # number of SoftPFReq misses 2195system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18627 # number of LoadLockedReq misses 2196system.cpu1.dcache.LoadLockedReq_misses::total 18627 # number of LoadLockedReq misses 2197system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23453 # number of StoreCondReq misses 2198system.cpu1.dcache.StoreCondReq_misses::total 23453 # number of StoreCondReq misses 2199system.cpu1.dcache.demand_misses::cpu1.data 616437 # number of demand (read+write) misses 2200system.cpu1.dcache.demand_misses::total 616437 # number of demand (read+write) misses 2201system.cpu1.dcache.overall_misses::cpu1.data 646718 # number of overall misses 2202system.cpu1.dcache.overall_misses::total 646718 # number of overall misses 2203system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3492190500 # number of ReadReq miss cycles 2204system.cpu1.dcache.ReadReq_miss_latency::total 3492190500 # number of ReadReq miss cycles 2205system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10142172955 # number of WriteReq miss cycles 2206system.cpu1.dcache.WriteReq_miss_latency::total 10142172955 # number of WriteReq miss cycles 2207system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366644000 # number of LoadLockedReq miss cycles 2208system.cpu1.dcache.LoadLockedReq_miss_latency::total 366644000 # number of LoadLockedReq miss cycles 2209system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 571781000 # number of StoreCondReq miss cycles 2210system.cpu1.dcache.StoreCondReq_miss_latency::total 571781000 # number of StoreCondReq miss cycles 2211system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1485000 # number of StoreCondFailReq miss cycles 2212system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1485000 # number of StoreCondFailReq miss cycles 2213system.cpu1.dcache.demand_miss_latency::cpu1.data 13634363455 # number of demand (read+write) miss cycles 2214system.cpu1.dcache.demand_miss_latency::total 13634363455 # number of demand (read+write) miss cycles 2215system.cpu1.dcache.overall_miss_latency::cpu1.data 13634363455 # number of overall miss cycles 2216system.cpu1.dcache.overall_miss_latency::total 13634363455 # number of overall miss cycles 2217system.cpu1.dcache.ReadReq_accesses::cpu1.data 3849174 # number of ReadReq accesses(hits+misses) 2218system.cpu1.dcache.ReadReq_accesses::total 3849174 # number of ReadReq accesses(hits+misses) 2219system.cpu1.dcache.WriteReq_accesses::cpu1.data 3317597 # number of WriteReq accesses(hits+misses) 2220system.cpu1.dcache.WriteReq_accesses::total 3317597 # number of WriteReq accesses(hits+misses) 2221system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79206 # number of SoftPFReq accesses(hits+misses) 2222system.cpu1.dcache.SoftPFReq_accesses::total 79206 # number of SoftPFReq accesses(hits+misses) 2223system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96821 # number of LoadLockedReq accesses(hits+misses) 2224system.cpu1.dcache.LoadLockedReq_accesses::total 96821 # number of LoadLockedReq accesses(hits+misses) 2225system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94056 # number of StoreCondReq accesses(hits+misses) 2226system.cpu1.dcache.StoreCondReq_accesses::total 94056 # number of StoreCondReq accesses(hits+misses) 2227system.cpu1.dcache.demand_accesses::cpu1.data 7166771 # number of demand (read+write) accesses 2228system.cpu1.dcache.demand_accesses::total 7166771 # number of demand (read+write) accesses 2229system.cpu1.dcache.overall_accesses::cpu1.data 7245977 # number of overall (read+write) accesses 2230system.cpu1.dcache.overall_accesses::total 7245977 # number of overall (read+write) accesses 2231system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056208 # miss rate for ReadReq accesses 2232system.cpu1.dcache.ReadReq_miss_rate::total 0.056208 # miss rate for ReadReq accesses 2233system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120594 # miss rate for WriteReq accesses 2234system.cpu1.dcache.WriteReq_miss_rate::total 0.120594 # miss rate for WriteReq accesses 2235system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382307 # miss rate for SoftPFReq accesses 2236system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382307 # miss rate for SoftPFReq accesses 2237system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192386 # miss rate for LoadLockedReq accesses 2238system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192386 # miss rate for LoadLockedReq accesses 2239system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249351 # miss rate for StoreCondReq accesses 2240system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249351 # miss rate for StoreCondReq accesses 2241system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086013 # miss rate for demand accesses 2242system.cpu1.dcache.demand_miss_rate::total 0.086013 # miss rate for demand accesses 2243system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089252 # miss rate for overall accesses 2244system.cpu1.dcache.overall_miss_rate::total 0.089252 # miss rate for overall accesses 2245system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16140.945941 # average ReadReq miss latency 2246system.cpu1.dcache.ReadReq_avg_miss_latency::total 16140.945941 # average ReadReq miss latency 2247system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25350.298952 # average WriteReq miss latency 2248system.cpu1.dcache.WriteReq_avg_miss_latency::total 25350.298952 # average WriteReq miss latency 2249system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19683.470231 # average LoadLockedReq miss latency 2250system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19683.470231 # average LoadLockedReq miss latency 2251system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24379.866115 # average StoreCondReq miss latency 2252system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24379.866115 # average StoreCondReq miss latency 2253system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2254system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2255system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22118.016042 # average overall miss latency 2256system.cpu1.dcache.demand_avg_miss_latency::total 22118.016042 # average overall miss latency 2257system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21082.393648 # average overall miss latency 2258system.cpu1.dcache.overall_avg_miss_latency::total 21082.393648 # average overall miss latency 2259system.cpu1.dcache.blocked_cycles::no_mshrs 336 # number of cycles access was blocked 2260system.cpu1.dcache.blocked_cycles::no_targets 1512378 # number of cycles access was blocked 2261system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked 2262system.cpu1.dcache.blocked::no_targets 40281 # number of cycles access was blocked 2263system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.200000 # average number of cycles each access was blocked 2264system.cpu1.dcache.avg_blocked_cycles::no_targets 37.545692 # average number of cycles each access was blocked 2265system.cpu1.dcache.writebacks::writebacks 189327 # number of writebacks 2266system.cpu1.dcache.writebacks::total 189327 # number of writebacks 2267system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79455 # number of ReadReq MSHR hits 2268system.cpu1.dcache.ReadReq_mshr_hits::total 79455 # number of ReadReq MSHR hits 2269system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309049 # number of WriteReq MSHR hits 2270system.cpu1.dcache.WriteReq_mshr_hits::total 309049 # number of WriteReq MSHR hits 2271system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13259 # number of LoadLockedReq MSHR hits 2272system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13259 # number of LoadLockedReq MSHR hits 2273system.cpu1.dcache.demand_mshr_hits::cpu1.data 388504 # number of demand (read+write) MSHR hits 2274system.cpu1.dcache.demand_mshr_hits::total 388504 # number of demand (read+write) MSHR hits 2275system.cpu1.dcache.overall_mshr_hits::cpu1.data 388504 # number of overall MSHR hits 2276system.cpu1.dcache.overall_mshr_hits::total 388504 # number of overall MSHR hits 2277system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136901 # number of ReadReq MSHR misses 2278system.cpu1.dcache.ReadReq_mshr_misses::total 136901 # number of ReadReq MSHR misses 2279system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91032 # number of WriteReq MSHR misses 2280system.cpu1.dcache.WriteReq_mshr_misses::total 91032 # number of WriteReq MSHR misses 2281system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28913 # number of SoftPFReq MSHR misses 2282system.cpu1.dcache.SoftPFReq_mshr_misses::total 28913 # number of SoftPFReq MSHR misses 2283system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5368 # number of LoadLockedReq MSHR misses 2284system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5368 # number of LoadLockedReq MSHR misses 2285system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23453 # number of StoreCondReq MSHR misses 2286system.cpu1.dcache.StoreCondReq_mshr_misses::total 23453 # number of StoreCondReq MSHR misses 2287system.cpu1.dcache.demand_mshr_misses::cpu1.data 227933 # number of demand (read+write) MSHR misses 2288system.cpu1.dcache.demand_mshr_misses::total 227933 # number of demand (read+write) MSHR misses 2289system.cpu1.dcache.overall_mshr_misses::cpu1.data 256846 # number of overall MSHR misses 2290system.cpu1.dcache.overall_mshr_misses::total 256846 # number of overall MSHR misses 2291system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable 2292system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable 2293system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2438 # number of WriteReq MSHR uncacheable 2294system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2438 # number of WriteReq MSHR uncacheable 2295system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5519 # number of overall MSHR uncacheable misses 2296system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5519 # number of overall MSHR uncacheable misses 2297system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1914813500 # number of ReadReq MSHR miss cycles 2298system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914813500 # number of ReadReq MSHR miss cycles 2299system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2474458965 # number of WriteReq MSHR miss cycles 2300system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2474458965 # number of WriteReq MSHR miss cycles 2301system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 498834500 # number of SoftPFReq MSHR miss cycles 2302system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 498834500 # number of SoftPFReq MSHR miss cycles 2303system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96515500 # number of LoadLockedReq MSHR miss cycles 2304system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96515500 # number of LoadLockedReq MSHR miss cycles 2305system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548354000 # number of StoreCondReq MSHR miss cycles 2306system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548354000 # number of StoreCondReq MSHR miss cycles 2307system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1459000 # number of StoreCondFailReq MSHR miss cycles 2308system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1459000 # number of StoreCondFailReq MSHR miss cycles 2309system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4389272465 # number of demand (read+write) MSHR miss cycles 2310system.cpu1.dcache.demand_mshr_miss_latency::total 4389272465 # number of demand (read+write) MSHR miss cycles 2311system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4888106965 # number of overall MSHR miss cycles 2312system.cpu1.dcache.overall_mshr_miss_latency::total 4888106965 # number of overall MSHR miss cycles 2313system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442121000 # number of ReadReq MSHR uncacheable cycles 2314system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442121000 # number of ReadReq MSHR uncacheable cycles 2315system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442121000 # number of overall MSHR uncacheable cycles 2316system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442121000 # number of overall MSHR uncacheable cycles 2317system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for ReadReq accesses 2318system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035566 # mshr miss rate for ReadReq accesses 2319system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027439 # mshr miss rate for WriteReq accesses 2320system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027439 # mshr miss rate for WriteReq accesses 2321system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365035 # mshr miss rate for SoftPFReq accesses 2322system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365035 # mshr miss rate for SoftPFReq accesses 2323system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055443 # mshr miss rate for LoadLockedReq accesses 2324system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055443 # mshr miss rate for LoadLockedReq accesses 2325system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249351 # mshr miss rate for StoreCondReq accesses 2326system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249351 # mshr miss rate for StoreCondReq accesses 2327system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031804 # mshr miss rate for demand accesses 2328system.cpu1.dcache.demand_mshr_miss_rate::total 0.031804 # mshr miss rate for demand accesses 2329system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses 2330system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses 2331system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.848160 # average ReadReq mshr miss latency 2332system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.848160 # average ReadReq mshr miss latency 2333system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27182.298148 # average WriteReq mshr miss latency 2334system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27182.298148 # average WriteReq mshr miss latency 2335system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17252.948501 # average SoftPFReq mshr miss latency 2336system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17252.948501 # average SoftPFReq mshr miss latency 2337system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17979.787630 # average LoadLockedReq mshr miss latency 2338system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17979.787630 # average LoadLockedReq mshr miss latency 2339system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23380.974715 # average StoreCondReq mshr miss latency 2340system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23380.974715 # average StoreCondReq mshr miss latency 2341system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2342system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2343system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19256.853834 # average overall mshr miss latency 2344system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19256.853834 # average overall mshr miss latency 2345system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19031.275414 # average overall mshr miss latency 2346system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19031.275414 # average overall mshr miss latency 2347system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143499.188575 # average ReadReq mshr uncacheable latency 2348system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143499.188575 # average ReadReq mshr uncacheable latency 2349system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80108.896539 # average overall mshr uncacheable latency 2350system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80108.896539 # average overall mshr uncacheable latency 2351system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2352system.cpu1.icache.tags.replacements 586343 # number of replacements 2353system.cpu1.icache.tags.tagsinuse 499.448153 # Cycle average of tags in use 2354system.cpu1.icache.tags.total_refs 7647462 # Total number of references to valid blocks. 2355system.cpu1.icache.tags.sampled_refs 586855 # Sample count of references to valid blocks. 2356system.cpu1.icache.tags.avg_refs 13.031263 # Average number of references to valid blocks. 2357system.cpu1.icache.tags.warmup_cycle 79062638500 # Cycle when the warmup percentage was hit. 2358system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448153 # Average occupied blocks per requestor 2359system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy 2360system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy 2361system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2362system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2363system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2364system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2365system.cpu1.icache.tags.tag_accesses 17099739 # Number of tag accesses 2366system.cpu1.icache.tags.data_accesses 17099739 # Number of data accesses 2367system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2368system.cpu1.icache.ReadReq_hits::cpu1.inst 7647462 # number of ReadReq hits 2369system.cpu1.icache.ReadReq_hits::total 7647462 # number of ReadReq hits 2370system.cpu1.icache.demand_hits::cpu1.inst 7647462 # number of demand (read+write) hits 2371system.cpu1.icache.demand_hits::total 7647462 # number of demand (read+write) hits 2372system.cpu1.icache.overall_hits::cpu1.inst 7647462 # number of overall hits 2373system.cpu1.icache.overall_hits::total 7647462 # number of overall hits 2374system.cpu1.icache.ReadReq_misses::cpu1.inst 608974 # number of ReadReq misses 2375system.cpu1.icache.ReadReq_misses::total 608974 # number of ReadReq misses 2376system.cpu1.icache.demand_misses::cpu1.inst 608974 # number of demand (read+write) misses 2377system.cpu1.icache.demand_misses::total 608974 # number of demand (read+write) misses 2378system.cpu1.icache.overall_misses::cpu1.inst 608974 # number of overall misses 2379system.cpu1.icache.overall_misses::total 608974 # number of overall misses 2380system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5478938231 # number of ReadReq miss cycles 2381system.cpu1.icache.ReadReq_miss_latency::total 5478938231 # number of ReadReq miss cycles 2382system.cpu1.icache.demand_miss_latency::cpu1.inst 5478938231 # number of demand (read+write) miss cycles 2383system.cpu1.icache.demand_miss_latency::total 5478938231 # number of demand (read+write) miss cycles 2384system.cpu1.icache.overall_miss_latency::cpu1.inst 5478938231 # number of overall miss cycles 2385system.cpu1.icache.overall_miss_latency::total 5478938231 # number of overall miss cycles 2386system.cpu1.icache.ReadReq_accesses::cpu1.inst 8256436 # number of ReadReq accesses(hits+misses) 2387system.cpu1.icache.ReadReq_accesses::total 8256436 # number of ReadReq accesses(hits+misses) 2388system.cpu1.icache.demand_accesses::cpu1.inst 8256436 # number of demand (read+write) accesses 2389system.cpu1.icache.demand_accesses::total 8256436 # number of demand (read+write) accesses 2390system.cpu1.icache.overall_accesses::cpu1.inst 8256436 # number of overall (read+write) accesses 2391system.cpu1.icache.overall_accesses::total 8256436 # number of overall (read+write) accesses 2392system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073757 # miss rate for ReadReq accesses 2393system.cpu1.icache.ReadReq_miss_rate::total 0.073757 # miss rate for ReadReq accesses 2394system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073757 # miss rate for demand accesses 2395system.cpu1.icache.demand_miss_rate::total 0.073757 # miss rate for demand accesses 2396system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073757 # miss rate for overall accesses 2397system.cpu1.icache.overall_miss_rate::total 0.073757 # miss rate for overall accesses 2398system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8996.998609 # average ReadReq miss latency 2399system.cpu1.icache.ReadReq_avg_miss_latency::total 8996.998609 # average ReadReq miss latency 2400system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency 2401system.cpu1.icache.demand_avg_miss_latency::total 8996.998609 # average overall miss latency 2402system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency 2403system.cpu1.icache.overall_avg_miss_latency::total 8996.998609 # average overall miss latency 2404system.cpu1.icache.blocked_cycles::no_mshrs 488402 # number of cycles access was blocked 2405system.cpu1.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked 2406system.cpu1.icache.blocked::no_mshrs 41185 # number of cycles access was blocked 2407system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2408system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.858735 # average number of cycles each access was blocked 2409system.cpu1.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked 2410system.cpu1.icache.writebacks::writebacks 586343 # number of writebacks 2411system.cpu1.icache.writebacks::total 586343 # number of writebacks 2412system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22107 # number of ReadReq MSHR hits 2413system.cpu1.icache.ReadReq_mshr_hits::total 22107 # number of ReadReq MSHR hits 2414system.cpu1.icache.demand_mshr_hits::cpu1.inst 22107 # number of demand (read+write) MSHR hits 2415system.cpu1.icache.demand_mshr_hits::total 22107 # number of demand (read+write) MSHR hits 2416system.cpu1.icache.overall_mshr_hits::cpu1.inst 22107 # number of overall MSHR hits 2417system.cpu1.icache.overall_mshr_hits::total 22107 # number of overall MSHR hits 2418system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586867 # number of ReadReq MSHR misses 2419system.cpu1.icache.ReadReq_mshr_misses::total 586867 # number of ReadReq MSHR misses 2420system.cpu1.icache.demand_mshr_misses::cpu1.inst 586867 # number of demand (read+write) MSHR misses 2421system.cpu1.icache.demand_mshr_misses::total 586867 # number of demand (read+write) MSHR misses 2422system.cpu1.icache.overall_mshr_misses::cpu1.inst 586867 # number of overall MSHR misses 2423system.cpu1.icache.overall_mshr_misses::total 586867 # number of overall MSHR misses 2424system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable 2425system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable 2426system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses 2427system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses 2428system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5026245111 # number of ReadReq MSHR miss cycles 2429system.cpu1.icache.ReadReq_mshr_miss_latency::total 5026245111 # number of ReadReq MSHR miss cycles 2430system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5026245111 # number of demand (read+write) MSHR miss cycles 2431system.cpu1.icache.demand_mshr_miss_latency::total 5026245111 # number of demand (read+write) MSHR miss cycles 2432system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5026245111 # number of overall MSHR miss cycles 2433system.cpu1.icache.overall_mshr_miss_latency::total 5026245111 # number of overall MSHR miss cycles 2434system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9125500 # number of ReadReq MSHR uncacheable cycles 2435system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9125500 # number of ReadReq MSHR uncacheable cycles 2436system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9125500 # number of overall MSHR uncacheable cycles 2437system.cpu1.icache.overall_mshr_uncacheable_latency::total 9125500 # number of overall MSHR uncacheable cycles 2438system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for ReadReq accesses 2439system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071080 # mshr miss rate for ReadReq accesses 2440system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for demand accesses 2441system.cpu1.icache.demand_mshr_miss_rate::total 0.071080 # mshr miss rate for demand accesses 2442system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for overall accesses 2443system.cpu1.icache.overall_mshr_miss_rate::total 0.071080 # mshr miss rate for overall accesses 2444system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average ReadReq mshr miss latency 2445system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8564.538662 # average ReadReq mshr miss latency 2446system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency 2447system.cpu1.icache.demand_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency 2448system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency 2449system.cpu1.icache.overall_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency 2450system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average ReadReq mshr uncacheable latency 2451system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90351.485149 # average ReadReq mshr uncacheable latency 2452system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average overall mshr uncacheable latency 2453system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90351.485149 # average overall mshr uncacheable latency 2454system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2455system.cpu1.l2cache.prefetcher.num_hwpf_issued 204963 # number of hwpf issued 2456system.cpu1.l2cache.prefetcher.pfIdentified 205672 # number of prefetch candidates identified 2457system.cpu1.l2cache.prefetcher.pfBufferHit 636 # number of redundant prefetches already in prefetch queue 2458system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2459system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2460system.cpu1.l2cache.prefetcher.pfSpanPage 59720 # number of prefetches not generated due to page crossing 2461system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2462system.cpu1.l2cache.tags.replacements 51812 # number of replacements 2463system.cpu1.l2cache.tags.tagsinuse 15242.895875 # Cycle average of tags in use 2464system.cpu1.l2cache.tags.total_refs 1332238 # Total number of references to valid blocks. 2465system.cpu1.l2cache.tags.sampled_refs 66423 # Sample count of references to valid blocks. 2466system.cpu1.l2cache.tags.avg_refs 20.056878 # Average number of references to valid blocks. 2467system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2468system.cpu1.l2cache.tags.occ_blocks::writebacks 14783.108783 # Average occupied blocks per requestor 2469system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.856539 # Average occupied blocks per requestor 2470system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.176183 # Average occupied blocks per requestor 2471system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 447.754371 # Average occupied blocks per requestor 2472system.cpu1.l2cache.tags.occ_percent::writebacks 0.902289 # Average percentage of cache occupancy 2473system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000602 # Average percentage of cache occupancy 2474system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000133 # Average percentage of cache occupancy 2475system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027329 # Average percentage of cache occupancy 2476system.cpu1.l2cache.tags.occ_percent::total 0.930353 # Average percentage of cache occupancy 2477system.cpu1.l2cache.tags.occ_task_id_blocks::1022 977 # Occupied blocks per task id 2478system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id 2479system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13602 # Occupied blocks per task id 2480system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 14 # Occupied blocks per task id 2481system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 835 # Occupied blocks per task id 2482system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 128 # Occupied blocks per task id 2483system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 2484system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2485system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 2486system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id 2487system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id 2488system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4458 # Occupied blocks per task id 2489system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059631 # Percentage of cache occupancy per task id 2490system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id 2491system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.830200 # Percentage of cache occupancy per task id 2492system.cpu1.l2cache.tags.tag_accesses 26728427 # Number of tag accesses 2493system.cpu1.l2cache.tags.data_accesses 26728427 # Number of data accesses 2494system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2495system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16758 # number of ReadReq hits 2496system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6223 # number of ReadReq hits 2497system.cpu1.l2cache.ReadReq_hits::total 22981 # number of ReadReq hits 2498system.cpu1.l2cache.WritebackDirty_hits::writebacks 115160 # number of WritebackDirty hits 2499system.cpu1.l2cache.WritebackDirty_hits::total 115160 # number of WritebackDirty hits 2500system.cpu1.l2cache.WritebackClean_hits::writebacks 648098 # number of WritebackClean hits 2501system.cpu1.l2cache.WritebackClean_hits::total 648098 # number of WritebackClean hits 2502system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 2503system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 2504system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27344 # number of ReadExReq hits 2505system.cpu1.l2cache.ReadExReq_hits::total 27344 # number of ReadExReq hits 2506system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570840 # number of ReadCleanReq hits 2507system.cpu1.l2cache.ReadCleanReq_hits::total 570840 # number of ReadCleanReq hits 2508system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101859 # number of ReadSharedReq hits 2509system.cpu1.l2cache.ReadSharedReq_hits::total 101859 # number of ReadSharedReq hits 2510system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16758 # number of demand (read+write) hits 2511system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6223 # number of demand (read+write) hits 2512system.cpu1.l2cache.demand_hits::cpu1.inst 570840 # number of demand (read+write) hits 2513system.cpu1.l2cache.demand_hits::cpu1.data 129203 # number of demand (read+write) hits 2514system.cpu1.l2cache.demand_hits::total 723024 # number of demand (read+write) hits 2515system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16758 # number of overall hits 2516system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6223 # number of overall hits 2517system.cpu1.l2cache.overall_hits::cpu1.inst 570840 # number of overall hits 2518system.cpu1.l2cache.overall_hits::cpu1.data 129203 # number of overall hits 2519system.cpu1.l2cache.overall_hits::total 723024 # number of overall hits 2520system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 453 # number of ReadReq misses 2521system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 249 # number of ReadReq misses 2522system.cpu1.l2cache.ReadReq_misses::total 702 # number of ReadReq misses 2523system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29938 # number of UpgradeReq misses 2524system.cpu1.l2cache.UpgradeReq_misses::total 29938 # number of UpgradeReq misses 2525system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23451 # number of SCUpgradeReq misses 2526system.cpu1.l2cache.SCUpgradeReq_misses::total 23451 # number of SCUpgradeReq misses 2527system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 2528system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 2529system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34420 # number of ReadExReq misses 2530system.cpu1.l2cache.ReadExReq_misses::total 34420 # number of ReadExReq misses 2531system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16015 # number of ReadCleanReq misses 2532system.cpu1.l2cache.ReadCleanReq_misses::total 16015 # number of ReadCleanReq misses 2533system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69307 # number of ReadSharedReq misses 2534system.cpu1.l2cache.ReadSharedReq_misses::total 69307 # number of ReadSharedReq misses 2535system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 453 # number of demand (read+write) misses 2536system.cpu1.l2cache.demand_misses::cpu1.itb.walker 249 # number of demand (read+write) misses 2537system.cpu1.l2cache.demand_misses::cpu1.inst 16015 # number of demand (read+write) misses 2538system.cpu1.l2cache.demand_misses::cpu1.data 103727 # number of demand (read+write) misses 2539system.cpu1.l2cache.demand_misses::total 120444 # number of demand (read+write) misses 2540system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 453 # number of overall misses 2541system.cpu1.l2cache.overall_misses::cpu1.itb.walker 249 # number of overall misses 2542system.cpu1.l2cache.overall_misses::cpu1.inst 16015 # number of overall misses 2543system.cpu1.l2cache.overall_misses::cpu1.data 103727 # number of overall misses 2544system.cpu1.l2cache.overall_misses::total 120444 # number of overall misses 2545system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9914500 # number of ReadReq miss cycles 2546system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5311000 # number of ReadReq miss cycles 2547system.cpu1.l2cache.ReadReq_miss_latency::total 15225500 # number of ReadReq miss cycles 2548system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63914000 # number of UpgradeReq miss cycles 2549system.cpu1.l2cache.UpgradeReq_miss_latency::total 63914000 # number of UpgradeReq miss cycles 2550system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 34438500 # number of SCUpgradeReq miss cycles 2551system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 34438500 # number of SCUpgradeReq miss cycles 2552system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1420000 # number of SCUpgradeFailReq miss cycles 2553system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1420000 # number of SCUpgradeFailReq miss cycles 2554system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1452051999 # number of ReadExReq miss cycles 2555system.cpu1.l2cache.ReadExReq_miss_latency::total 1452051999 # number of ReadExReq miss cycles 2556system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 660407500 # number of ReadCleanReq miss cycles 2557system.cpu1.l2cache.ReadCleanReq_miss_latency::total 660407500 # number of ReadCleanReq miss cycles 2558system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1570017499 # number of ReadSharedReq miss cycles 2559system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1570017499 # number of ReadSharedReq miss cycles 2560system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9914500 # number of demand (read+write) miss cycles 2561system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5311000 # number of demand (read+write) miss cycles 2562system.cpu1.l2cache.demand_miss_latency::cpu1.inst 660407500 # number of demand (read+write) miss cycles 2563system.cpu1.l2cache.demand_miss_latency::cpu1.data 3022069498 # number of demand (read+write) miss cycles 2564system.cpu1.l2cache.demand_miss_latency::total 3697702498 # number of demand (read+write) miss cycles 2565system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9914500 # number of overall miss cycles 2566system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5311000 # number of overall miss cycles 2567system.cpu1.l2cache.overall_miss_latency::cpu1.inst 660407500 # number of overall miss cycles 2568system.cpu1.l2cache.overall_miss_latency::cpu1.data 3022069498 # number of overall miss cycles 2569system.cpu1.l2cache.overall_miss_latency::total 3697702498 # number of overall miss cycles 2570system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17211 # number of ReadReq accesses(hits+misses) 2571system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6472 # number of ReadReq accesses(hits+misses) 2572system.cpu1.l2cache.ReadReq_accesses::total 23683 # number of ReadReq accesses(hits+misses) 2573system.cpu1.l2cache.WritebackDirty_accesses::writebacks 115160 # number of WritebackDirty accesses(hits+misses) 2574system.cpu1.l2cache.WritebackDirty_accesses::total 115160 # number of WritebackDirty accesses(hits+misses) 2575system.cpu1.l2cache.WritebackClean_accesses::writebacks 648098 # number of WritebackClean accesses(hits+misses) 2576system.cpu1.l2cache.WritebackClean_accesses::total 648098 # number of WritebackClean accesses(hits+misses) 2577system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29938 # number of UpgradeReq accesses(hits+misses) 2578system.cpu1.l2cache.UpgradeReq_accesses::total 29938 # number of UpgradeReq accesses(hits+misses) 2579system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23452 # number of SCUpgradeReq accesses(hits+misses) 2580system.cpu1.l2cache.SCUpgradeReq_accesses::total 23452 # number of SCUpgradeReq accesses(hits+misses) 2581system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2582system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2583system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61764 # number of ReadExReq accesses(hits+misses) 2584system.cpu1.l2cache.ReadExReq_accesses::total 61764 # number of ReadExReq accesses(hits+misses) 2585system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 586855 # number of ReadCleanReq accesses(hits+misses) 2586system.cpu1.l2cache.ReadCleanReq_accesses::total 586855 # number of ReadCleanReq accesses(hits+misses) 2587system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171166 # number of ReadSharedReq accesses(hits+misses) 2588system.cpu1.l2cache.ReadSharedReq_accesses::total 171166 # number of ReadSharedReq accesses(hits+misses) 2589system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17211 # number of demand (read+write) accesses 2590system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6472 # number of demand (read+write) accesses 2591system.cpu1.l2cache.demand_accesses::cpu1.inst 586855 # number of demand (read+write) accesses 2592system.cpu1.l2cache.demand_accesses::cpu1.data 232930 # number of demand (read+write) accesses 2593system.cpu1.l2cache.demand_accesses::total 843468 # number of demand (read+write) accesses 2594system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17211 # number of overall (read+write) accesses 2595system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6472 # number of overall (read+write) accesses 2596system.cpu1.l2cache.overall_accesses::cpu1.inst 586855 # number of overall (read+write) accesses 2597system.cpu1.l2cache.overall_accesses::cpu1.data 232930 # number of overall (read+write) accesses 2598system.cpu1.l2cache.overall_accesses::total 843468 # number of overall (read+write) accesses 2599system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026320 # miss rate for ReadReq accesses 2600system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.038473 # miss rate for ReadReq accesses 2601system.cpu1.l2cache.ReadReq_miss_rate::total 0.029642 # miss rate for ReadReq accesses 2602system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2603system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2604system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999957 # miss rate for SCUpgradeReq accesses 2605system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999957 # miss rate for SCUpgradeReq accesses 2606system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2607system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2608system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.557283 # miss rate for ReadExReq accesses 2609system.cpu1.l2cache.ReadExReq_miss_rate::total 0.557283 # miss rate for ReadExReq accesses 2610system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027290 # miss rate for ReadCleanReq accesses 2611system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027290 # miss rate for ReadCleanReq accesses 2612system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.404911 # miss rate for ReadSharedReq accesses 2613system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.404911 # miss rate for ReadSharedReq accesses 2614system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026320 # miss rate for demand accesses 2615system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.038473 # miss rate for demand accesses 2616system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027290 # miss rate for demand accesses 2617system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.445314 # miss rate for demand accesses 2618system.cpu1.l2cache.demand_miss_rate::total 0.142796 # miss rate for demand accesses 2619system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026320 # miss rate for overall accesses 2620system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.038473 # miss rate for overall accesses 2621system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027290 # miss rate for overall accesses 2622system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.445314 # miss rate for overall accesses 2623system.cpu1.l2cache.overall_miss_rate::total 0.142796 # miss rate for overall accesses 2624system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21886.313466 # average ReadReq miss latency 2625system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21329.317269 # average ReadReq miss latency 2626system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21688.746439 # average ReadReq miss latency 2627system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2134.878749 # average UpgradeReq miss latency 2628system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2134.878749 # average UpgradeReq miss latency 2629system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1468.530127 # average SCUpgradeReq miss latency 2630system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1468.530127 # average SCUpgradeReq miss latency 2631system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1420000 # average SCUpgradeFailReq miss latency 2632system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1420000 # average SCUpgradeFailReq miss latency 2633system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42186.287013 # average ReadExReq miss latency 2634system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42186.287013 # average ReadExReq miss latency 2635system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41236.809241 # average ReadCleanReq miss latency 2636system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41236.809241 # average ReadCleanReq miss latency 2637system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22653.086975 # average ReadSharedReq miss latency 2638system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22653.086975 # average ReadSharedReq miss latency 2639system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21886.313466 # average overall miss latency 2640system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21329.317269 # average overall miss latency 2641system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41236.809241 # average overall miss latency 2642system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29134.839511 # average overall miss latency 2643system.cpu1.l2cache.demand_avg_miss_latency::total 30700.595281 # average overall miss latency 2644system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21886.313466 # average overall miss latency 2645system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21329.317269 # average overall miss latency 2646system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41236.809241 # average overall miss latency 2647system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29134.839511 # average overall miss latency 2648system.cpu1.l2cache.overall_avg_miss_latency::total 30700.595281 # average overall miss latency 2649system.cpu1.l2cache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked 2650system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2651system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 2652system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2653system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.500000 # average number of cycles each access was blocked 2654system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2655system.cpu1.l2cache.unused_prefetches 841 # number of HardPF blocks evicted w/o reference 2656system.cpu1.l2cache.writebacks::writebacks 37209 # number of writebacks 2657system.cpu1.l2cache.writebacks::total 37209 # number of writebacks 2658system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 554 # number of ReadExReq MSHR hits 2659system.cpu1.l2cache.ReadExReq_mshr_hits::total 554 # number of ReadExReq MSHR hits 2660system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2661system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 2662system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 67 # number of ReadSharedReq MSHR hits 2663system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 67 # number of ReadSharedReq MSHR hits 2664system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2665system.cpu1.l2cache.demand_mshr_hits::cpu1.data 621 # number of demand (read+write) MSHR hits 2666system.cpu1.l2cache.demand_mshr_hits::total 625 # number of demand (read+write) MSHR hits 2667system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2668system.cpu1.l2cache.overall_mshr_hits::cpu1.data 621 # number of overall MSHR hits 2669system.cpu1.l2cache.overall_mshr_hits::total 625 # number of overall MSHR hits 2670system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 453 # number of ReadReq MSHR misses 2671system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 249 # number of ReadReq MSHR misses 2672system.cpu1.l2cache.ReadReq_mshr_misses::total 702 # number of ReadReq MSHR misses 2673system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 27386 # number of HardPFReq MSHR misses 2674system.cpu1.l2cache.HardPFReq_mshr_misses::total 27386 # number of HardPFReq MSHR misses 2675system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29938 # number of UpgradeReq MSHR misses 2676system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29938 # number of UpgradeReq MSHR misses 2677system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23451 # number of SCUpgradeReq MSHR misses 2678system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23451 # number of SCUpgradeReq MSHR misses 2679system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2680system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2681system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33866 # number of ReadExReq MSHR misses 2682system.cpu1.l2cache.ReadExReq_mshr_misses::total 33866 # number of ReadExReq MSHR misses 2683system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16011 # number of ReadCleanReq MSHR misses 2684system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16011 # number of ReadCleanReq MSHR misses 2685system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69240 # number of ReadSharedReq MSHR misses 2686system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69240 # number of ReadSharedReq MSHR misses 2687system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 453 # number of demand (read+write) MSHR misses 2688system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 249 # number of demand (read+write) MSHR misses 2689system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16011 # number of demand (read+write) MSHR misses 2690system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103106 # number of demand (read+write) MSHR misses 2691system.cpu1.l2cache.demand_mshr_misses::total 119819 # number of demand (read+write) MSHR misses 2692system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 453 # number of overall MSHR misses 2693system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 249 # number of overall MSHR misses 2694system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16011 # number of overall MSHR misses 2695system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103106 # number of overall MSHR misses 2696system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 27386 # number of overall MSHR misses 2697system.cpu1.l2cache.overall_mshr_misses::total 147205 # number of overall MSHR misses 2698system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable 2699system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable 2700system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3182 # number of ReadReq MSHR uncacheable 2701system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2438 # number of WriteReq MSHR uncacheable 2702system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2438 # number of WriteReq MSHR uncacheable 2703system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses 2704system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5519 # number of overall MSHR uncacheable misses 2705system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5620 # number of overall MSHR uncacheable misses 2706system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7196500 # number of ReadReq MSHR miss cycles 2707system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3817000 # number of ReadReq MSHR miss cycles 2708system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11013500 # number of ReadReq MSHR miss cycles 2709system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1234227220 # number of HardPFReq MSHR miss cycles 2710system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1234227220 # number of HardPFReq MSHR miss cycles 2711system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 500545000 # number of UpgradeReq MSHR miss cycles 2712system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 500545000 # number of UpgradeReq MSHR miss cycles 2713system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 372231000 # number of SCUpgradeReq MSHR miss cycles 2714system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 372231000 # number of SCUpgradeReq MSHR miss cycles 2715system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1264000 # number of SCUpgradeFailReq MSHR miss cycles 2716system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1264000 # number of SCUpgradeFailReq MSHR miss cycles 2717system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1182076500 # number of ReadExReq MSHR miss cycles 2718system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1182076500 # number of ReadExReq MSHR miss cycles 2719system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 564261500 # number of ReadCleanReq MSHR miss cycles 2720system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 564261500 # number of ReadCleanReq MSHR miss cycles 2721system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1152682499 # number of ReadSharedReq MSHR miss cycles 2722system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1152682499 # number of ReadSharedReq MSHR miss cycles 2723system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7196500 # number of demand (read+write) MSHR miss cycles 2724system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3817000 # number of demand (read+write) MSHR miss cycles 2725system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 564261500 # number of demand (read+write) MSHR miss cycles 2726system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2334758999 # number of demand (read+write) MSHR miss cycles 2727system.cpu1.l2cache.demand_mshr_miss_latency::total 2910033999 # number of demand (read+write) MSHR miss cycles 2728system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7196500 # number of overall MSHR miss cycles 2729system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3817000 # number of overall MSHR miss cycles 2730system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 564261500 # number of overall MSHR miss cycles 2731system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2334758999 # number of overall MSHR miss cycles 2732system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1234227220 # number of overall MSHR miss cycles 2733system.cpu1.l2cache.overall_mshr_miss_latency::total 4144261219 # number of overall MSHR miss cycles 2734system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8368000 # number of ReadReq MSHR uncacheable cycles 2735system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417428000 # number of ReadReq MSHR uncacheable cycles 2736system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 425796000 # number of ReadReq MSHR uncacheable cycles 2737system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8368000 # number of overall MSHR uncacheable cycles 2738system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417428000 # number of overall MSHR uncacheable cycles 2739system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 425796000 # number of overall MSHR uncacheable cycles 2740system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for ReadReq accesses 2741system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for ReadReq accesses 2742system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029642 # mshr miss rate for ReadReq accesses 2743system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2744system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2745system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2746system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2747system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses 2748system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses 2749system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2750system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2751system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548313 # mshr miss rate for ReadExReq accesses 2752system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548313 # mshr miss rate for ReadExReq accesses 2753system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for ReadCleanReq accesses 2754system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027283 # mshr miss rate for ReadCleanReq accesses 2755system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404520 # mshr miss rate for ReadSharedReq accesses 2756system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404520 # mshr miss rate for ReadSharedReq accesses 2757system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for demand accesses 2758system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for demand accesses 2759system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for demand accesses 2760system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for demand accesses 2761system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142055 # mshr miss rate for demand accesses 2762system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for overall accesses 2763system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for overall accesses 2764system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for overall accesses 2765system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for overall accesses 2766system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2767system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174524 # mshr miss rate for overall accesses 2768system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average ReadReq mshr miss latency 2769system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average ReadReq mshr miss latency 2770system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15688.746439 # average ReadReq mshr miss latency 2771system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average HardPFReq mshr miss latency 2772system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45067.816403 # average HardPFReq mshr miss latency 2773system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16719.386733 # average UpgradeReq mshr miss latency 2774system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16719.386733 # average UpgradeReq mshr miss latency 2775system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15872.713317 # average SCUpgradeReq mshr miss latency 2776system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15872.713317 # average SCUpgradeReq mshr miss latency 2777system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1264000 # average SCUpgradeFailReq mshr miss latency 2778system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1264000 # average SCUpgradeFailReq mshr miss latency 2779system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34904.520758 # average ReadExReq mshr miss latency 2780system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34904.520758 # average ReadExReq mshr miss latency 2781system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average ReadCleanReq mshr miss latency 2782system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35242.114796 # average ReadCleanReq mshr miss latency 2783system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16647.638634 # average ReadSharedReq mshr miss latency 2784system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16647.638634 # average ReadSharedReq mshr miss latency 2785system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency 2786system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency 2787system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency 2788system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency 2789system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24286.916090 # average overall mshr miss latency 2790system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency 2791system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency 2792system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency 2793system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency 2794system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average overall mshr miss latency 2795system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28152.992215 # average overall mshr miss latency 2796system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average ReadReq mshr uncacheable latency 2797system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135484.582928 # average ReadReq mshr uncacheable latency 2798system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133813.953488 # average ReadReq mshr uncacheable latency 2799system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average overall mshr uncacheable latency 2800system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75634.716434 # average overall mshr uncacheable latency 2801system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75764.412811 # average overall mshr uncacheable latency 2802system.cpu1.toL2Bus.snoop_filter.tot_requests 1659506 # Total number of requests made to the snoop filter. 2803system.cpu1.toL2Bus.snoop_filter.hit_single_requests 839728 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2804system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2805system.cpu1.toL2Bus.snoop_filter.tot_snoops 183739 # Total number of snoops made to the snoop filter. 2806system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180899 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2807system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2808system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2809system.cpu1.toL2Bus.trans_dist::ReadReq 31691 # Transaction distribution 2810system.cpu1.toL2Bus.trans_dist::ReadResp 827645 # Transaction distribution 2811system.cpu1.toL2Bus.trans_dist::WriteReq 2438 # Transaction distribution 2812system.cpu1.toL2Bus.trans_dist::WriteResp 2438 # Transaction distribution 2813system.cpu1.toL2Bus.trans_dist::WritebackDirty 153507 # Transaction distribution 2814system.cpu1.toL2Bus.trans_dist::WritebackClean 660509 # Transaction distribution 2815system.cpu1.toL2Bus.trans_dist::CleanEvict 108712 # Transaction distribution 2816system.cpu1.toL2Bus.trans_dist::HardPFReq 33822 # Transaction distribution 2817system.cpu1.toL2Bus.trans_dist::UpgradeReq 71296 # Transaction distribution 2818system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41636 # Transaction distribution 2819system.cpu1.toL2Bus.trans_dist::UpgradeResp 86274 # Transaction distribution 2820system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 2821system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution 2822system.cpu1.toL2Bus.trans_dist::ReadExReq 68587 # Transaction distribution 2823system.cpu1.toL2Bus.trans_dist::ReadExResp 66399 # Transaction distribution 2824system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586867 # Transaction distribution 2825system.cpu1.toL2Bus.trans_dist::ReadSharedReq 252106 # Transaction distribution 2826system.cpu1.toL2Bus.trans_dist::InvalidateReq 259 # Transaction distribution 2827system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1760267 # Packet count per connected master and slave (bytes) 2828system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 848480 # Packet count per connected master and slave (bytes) 2829system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14499 # Packet count per connected master and slave (bytes) 2830system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37693 # Packet count per connected master and slave (bytes) 2831system.cpu1.toL2Bus.pkt_count::total 2660939 # Packet count per connected master and slave (bytes) 2832system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75086288 # Cumulative packet size per connected master and slave (bytes) 2833system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29768550 # Cumulative packet size per connected master and slave (bytes) 2834system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) 2835system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68844 # Cumulative packet size per connected master and slave (bytes) 2836system.cpu1.toL2Bus.pkt_size::total 104949570 # Cumulative packet size per connected master and slave (bytes) 2837system.cpu1.toL2Bus.snoops 408766 # Total snoops (count) 2838system.cpu1.toL2Bus.snoopTraffic 5198376 # Total snoop traffic (bytes) 2839system.cpu1.toL2Bus.snoop_fanout::samples 1235773 # Request fanout histogram 2840system.cpu1.toL2Bus.snoop_fanout::mean 0.169662 # Request fanout histogram 2841system.cpu1.toL2Bus.snoop_fanout::stdev 0.381410 # Request fanout histogram 2842system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2843system.cpu1.toL2Bus.snoop_fanout::0 1028949 83.26% 83.26% # Request fanout histogram 2844system.cpu1.toL2Bus.snoop_fanout::1 203984 16.51% 99.77% # Request fanout histogram 2845system.cpu1.toL2Bus.snoop_fanout::2 2840 0.23% 100.00% # Request fanout histogram 2846system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2847system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2848system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2849system.cpu1.toL2Bus.snoop_fanout::total 1235773 # Request fanout histogram 2850system.cpu1.toL2Bus.reqLayer0.occupancy 1618384496 # Layer occupancy (ticks) 2851system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2852system.cpu1.toL2Bus.snoopLayer0.occupancy 80334899 # Layer occupancy (ticks) 2853system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2854system.cpu1.toL2Bus.respLayer0.occupancy 880530739 # Layer occupancy (ticks) 2855system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2856system.cpu1.toL2Bus.respLayer1.occupancy 381648033 # Layer occupancy (ticks) 2857system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2858system.cpu1.toL2Bus.respLayer2.occupancy 8035982 # Layer occupancy (ticks) 2859system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2860system.cpu1.toL2Bus.respLayer3.occupancy 20499963 # Layer occupancy (ticks) 2861system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2862system.iobus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2863system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2864system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2865system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2866system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2867system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2868system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2869system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2870system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2871system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2872system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2873system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2874system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2875system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2876system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2877system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2878system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2879system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2880system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2881system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2882system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2883system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2884system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2885system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2886system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) 2887system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2888system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2889system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) 2890system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) 2891system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2892system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2893system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2894system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2895system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2896system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2897system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2898system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2899system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2900system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2901system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2902system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2903system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2904system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2905system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2906system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2907system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2908system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2909system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) 2910system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2911system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2912system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) 2913system.iobus.reqLayer0.occupancy 40384000 # Layer occupancy (ticks) 2914system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2915system.iobus.reqLayer1.occupancy 112000 # Layer occupancy (ticks) 2916system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2917system.iobus.reqLayer2.occupancy 328500 # Layer occupancy (ticks) 2918system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2919system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) 2920system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2921system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 2922system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2923system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) 2924system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2925system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) 2926system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2927system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2928system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2929system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2930system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2931system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 2932system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2933system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) 2934system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2935system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) 2936system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2937system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2938system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2939system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2940system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2941system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2942system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2943system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2944system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2945system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2946system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2947system.iobus.reqLayer23.occupancy 6095500 # Layer occupancy (ticks) 2948system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2949system.iobus.reqLayer24.occupancy 33840000 # Layer occupancy (ticks) 2950system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2951system.iobus.reqLayer25.occupancy 187690100 # Layer occupancy (ticks) 2952system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2953system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) 2954system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2955system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2956system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2957system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2958system.iocache.tags.replacements 36458 # number of replacements 2959system.iocache.tags.tagsinuse 14.555462 # Cycle average of tags in use 2960system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2961system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2962system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2963system.iocache.tags.warmup_cycle 255127474000 # Cycle when the warmup percentage was hit. 2964system.iocache.tags.occ_blocks::realview.ide 14.555462 # Average occupied blocks per requestor 2965system.iocache.tags.occ_percent::realview.ide 0.909716 # Average percentage of cache occupancy 2966system.iocache.tags.occ_percent::total 0.909716 # Average percentage of cache occupancy 2967system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2968system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2969system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2970system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2971system.iocache.tags.data_accesses 328284 # Number of data accesses 2972system.iocache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 2973system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2974system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2975system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2976system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2977system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2978system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2979system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2980system.iocache.overall_misses::total 36476 # number of overall misses 2981system.iocache.ReadReq_miss_latency::realview.ide 32581877 # number of ReadReq miss cycles 2982system.iocache.ReadReq_miss_latency::total 32581877 # number of ReadReq miss cycles 2983system.iocache.WriteLineReq_miss_latency::realview.ide 4303830223 # number of WriteLineReq miss cycles 2984system.iocache.WriteLineReq_miss_latency::total 4303830223 # number of WriteLineReq miss cycles 2985system.iocache.demand_miss_latency::realview.ide 4336412100 # number of demand (read+write) miss cycles 2986system.iocache.demand_miss_latency::total 4336412100 # number of demand (read+write) miss cycles 2987system.iocache.overall_miss_latency::realview.ide 4336412100 # number of overall miss cycles 2988system.iocache.overall_miss_latency::total 4336412100 # number of overall miss cycles 2989system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2990system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2991system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2992system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2993system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 2994system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 2995system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 2996system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 2997system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2998system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2999system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3000system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3001system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3002system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3003system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3004system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3005system.iocache.ReadReq_avg_miss_latency::realview.ide 129293.162698 # average ReadReq miss latency 3006system.iocache.ReadReq_avg_miss_latency::total 129293.162698 # average ReadReq miss latency 3007system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118811.567552 # average WriteLineReq miss latency 3008system.iocache.WriteLineReq_avg_miss_latency::total 118811.567552 # average WriteLineReq miss latency 3009system.iocache.demand_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency 3010system.iocache.demand_avg_miss_latency::total 118883.981248 # average overall miss latency 3011system.iocache.overall_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency 3012system.iocache.overall_avg_miss_latency::total 118883.981248 # average overall miss latency 3013system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked 3014system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3015system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked 3016system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3017system.iocache.avg_blocked_cycles::no_mshrs 5.333333 # average number of cycles each access was blocked 3018system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3019system.iocache.writebacks::writebacks 36206 # number of writebacks 3020system.iocache.writebacks::total 36206 # number of writebacks 3021system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3022system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3023system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3024system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3025system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 3026system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 3027system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 3028system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses 3029system.iocache.ReadReq_mshr_miss_latency::realview.ide 19981877 # number of ReadReq MSHR miss cycles 3030system.iocache.ReadReq_mshr_miss_latency::total 19981877 # number of ReadReq MSHR miss cycles 3031system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490259225 # number of WriteLineReq MSHR miss cycles 3032system.iocache.WriteLineReq_mshr_miss_latency::total 2490259225 # number of WriteLineReq MSHR miss cycles 3033system.iocache.demand_mshr_miss_latency::realview.ide 2510241102 # number of demand (read+write) MSHR miss cycles 3034system.iocache.demand_mshr_miss_latency::total 2510241102 # number of demand (read+write) MSHR miss cycles 3035system.iocache.overall_mshr_miss_latency::realview.ide 2510241102 # number of overall MSHR miss cycles 3036system.iocache.overall_mshr_miss_latency::total 2510241102 # number of overall MSHR miss cycles 3037system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3038system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3039system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3040system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3041system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3042system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3043system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3044system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3045system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79293.162698 # average ReadReq mshr miss latency 3046system.iocache.ReadReq_avg_mshr_miss_latency::total 79293.162698 # average ReadReq mshr miss latency 3047system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68746.113764 # average WriteLineReq mshr miss latency 3048system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68746.113764 # average WriteLineReq mshr miss latency 3049system.iocache.demand_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency 3050system.iocache.demand_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency 3051system.iocache.overall_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency 3052system.iocache.overall_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency 3053system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3054system.l2c.tags.replacements 132786 # number of replacements 3055system.l2c.tags.tagsinuse 63192.932289 # Cycle average of tags in use 3056system.l2c.tags.total_refs 445408 # Total number of references to valid blocks. 3057system.l2c.tags.sampled_refs 196622 # Sample count of references to valid blocks. 3058system.l2c.tags.avg_refs 2.265301 # Average number of references to valid blocks. 3059system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3060system.l2c.tags.occ_blocks::writebacks 13716.070006 # Average occupied blocks per requestor 3061system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.287927 # Average occupied blocks per requestor 3062system.l2c.tags.occ_blocks::cpu0.itb.walker 1.059977 # Average occupied blocks per requestor 3063system.l2c.tags.occ_blocks::cpu0.inst 8086.686479 # Average occupied blocks per requestor 3064system.l2c.tags.occ_blocks::cpu0.data 2783.200527 # Average occupied blocks per requestor 3065system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33654.604995 # Average occupied blocks per requestor 3066system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.598228 # Average occupied blocks per requestor 3067system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910717 # Average occupied blocks per requestor 3068system.l2c.tags.occ_blocks::cpu1.inst 1777.688460 # Average occupied blocks per requestor 3069system.l2c.tags.occ_blocks::cpu1.data 638.769137 # Average occupied blocks per requestor 3070system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2513.055836 # Average occupied blocks per requestor 3071system.l2c.tags.occ_percent::writebacks 0.209291 # Average percentage of cache occupancy 3072system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000249 # Average percentage of cache occupancy 3073system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 3074system.l2c.tags.occ_percent::cpu0.inst 0.123393 # Average percentage of cache occupancy 3075system.l2c.tags.occ_percent::cpu0.data 0.042468 # Average percentage of cache occupancy 3076system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.513529 # Average percentage of cache occupancy 3077system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000070 # Average percentage of cache occupancy 3078system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 3079system.l2c.tags.occ_percent::cpu1.inst 0.027125 # Average percentage of cache occupancy 3080system.l2c.tags.occ_percent::cpu1.data 0.009747 # Average percentage of cache occupancy 3081system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038346 # Average percentage of cache occupancy 3082system.l2c.tags.occ_percent::total 0.964248 # Average percentage of cache occupancy 3083system.l2c.tags.occ_task_id_blocks::1022 29165 # Occupied blocks per task id 3084system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 3085system.l2c.tags.occ_task_id_blocks::1024 34651 # Occupied blocks per task id 3086system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 3087system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id 3088system.l2c.tags.age_task_id_blocks_1022::3 5622 # Occupied blocks per task id 3089system.l2c.tags.age_task_id_blocks_1022::4 23349 # Occupied blocks per task id 3090system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 3091system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 3092system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 3093system.l2c.tags.age_task_id_blocks_1024::2 598 # Occupied blocks per task id 3094system.l2c.tags.age_task_id_blocks_1024::3 6765 # Occupied blocks per task id 3095system.l2c.tags.age_task_id_blocks_1024::4 27255 # Occupied blocks per task id 3096system.l2c.tags.occ_task_id_percent::1022 0.445023 # Percentage of cache occupancy per task id 3097system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id 3098system.l2c.tags.occ_task_id_percent::1024 0.528732 # Percentage of cache occupancy per task id 3099system.l2c.tags.tag_accesses 6142016 # Number of tag accesses 3100system.l2c.tags.data_accesses 6142016 # Number of data accesses 3101system.l2c.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3102system.l2c.WritebackDirty_hits::writebacks 267222 # number of WritebackDirty hits 3103system.l2c.WritebackDirty_hits::total 267222 # number of WritebackDirty hits 3104system.l2c.UpgradeReq_hits::cpu0.data 32477 # number of UpgradeReq hits 3105system.l2c.UpgradeReq_hits::cpu1.data 2702 # number of UpgradeReq hits 3106system.l2c.UpgradeReq_hits::total 35179 # number of UpgradeReq hits 3107system.l2c.SCUpgradeReq_hits::cpu0.data 2050 # number of SCUpgradeReq hits 3108system.l2c.SCUpgradeReq_hits::cpu1.data 948 # number of SCUpgradeReq hits 3109system.l2c.SCUpgradeReq_hits::total 2998 # number of SCUpgradeReq hits 3110system.l2c.ReadExReq_hits::cpu0.data 3952 # number of ReadExReq hits 3111system.l2c.ReadExReq_hits::cpu1.data 1344 # number of ReadExReq hits 3112system.l2c.ReadExReq_hits::total 5296 # number of ReadExReq hits 3113system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 189 # number of ReadSharedReq hits 3114system.l2c.ReadSharedReq_hits::cpu0.itb.walker 79 # number of ReadSharedReq hits 3115system.l2c.ReadSharedReq_hits::cpu0.inst 33758 # number of ReadSharedReq hits 3116system.l2c.ReadSharedReq_hits::cpu0.data 47203 # number of ReadSharedReq hits 3117system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46059 # number of ReadSharedReq hits 3118system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 69 # number of ReadSharedReq hits 3119system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits 3120system.l2c.ReadSharedReq_hits::cpu1.inst 13188 # number of ReadSharedReq hits 3121system.l2c.ReadSharedReq_hits::cpu1.data 9867 # number of ReadSharedReq hits 3122system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5574 # number of ReadSharedReq hits 3123system.l2c.ReadSharedReq_hits::total 156023 # number of ReadSharedReq hits 3124system.l2c.demand_hits::cpu0.dtb.walker 189 # number of demand (read+write) hits 3125system.l2c.demand_hits::cpu0.itb.walker 79 # number of demand (read+write) hits 3126system.l2c.demand_hits::cpu0.inst 33758 # number of demand (read+write) hits 3127system.l2c.demand_hits::cpu0.data 51155 # number of demand (read+write) hits 3128system.l2c.demand_hits::cpu0.l2cache.prefetcher 46059 # number of demand (read+write) hits 3129system.l2c.demand_hits::cpu1.dtb.walker 69 # number of demand (read+write) hits 3130system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits 3131system.l2c.demand_hits::cpu1.inst 13188 # number of demand (read+write) hits 3132system.l2c.demand_hits::cpu1.data 11211 # number of demand (read+write) hits 3133system.l2c.demand_hits::cpu1.l2cache.prefetcher 5574 # number of demand (read+write) hits 3134system.l2c.demand_hits::total 161319 # number of demand (read+write) hits 3135system.l2c.overall_hits::cpu0.dtb.walker 189 # number of overall hits 3136system.l2c.overall_hits::cpu0.itb.walker 79 # number of overall hits 3137system.l2c.overall_hits::cpu0.inst 33758 # number of overall hits 3138system.l2c.overall_hits::cpu0.data 51155 # number of overall hits 3139system.l2c.overall_hits::cpu0.l2cache.prefetcher 46059 # number of overall hits 3140system.l2c.overall_hits::cpu1.dtb.walker 69 # number of overall hits 3141system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits 3142system.l2c.overall_hits::cpu1.inst 13188 # number of overall hits 3143system.l2c.overall_hits::cpu1.data 11211 # number of overall hits 3144system.l2c.overall_hits::cpu1.l2cache.prefetcher 5574 # number of overall hits 3145system.l2c.overall_hits::total 161319 # number of overall hits 3146system.l2c.UpgradeReq_misses::cpu0.data 9039 # number of UpgradeReq misses 3147system.l2c.UpgradeReq_misses::cpu1.data 2774 # number of UpgradeReq misses 3148system.l2c.UpgradeReq_misses::total 11813 # number of UpgradeReq misses 3149system.l2c.SCUpgradeReq_misses::cpu0.data 653 # number of SCUpgradeReq misses 3150system.l2c.SCUpgradeReq_misses::cpu1.data 1278 # number of SCUpgradeReq misses 3151system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses 3152system.l2c.ReadExReq_misses::cpu0.data 11611 # number of ReadExReq misses 3153system.l2c.ReadExReq_misses::cpu1.data 8840 # number of ReadExReq misses 3154system.l2c.ReadExReq_misses::total 20451 # number of ReadExReq misses 3155system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses 3156system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses 3157system.l2c.ReadSharedReq_misses::cpu0.inst 19633 # number of ReadSharedReq misses 3158system.l2c.ReadSharedReq_misses::cpu0.data 9253 # number of ReadSharedReq misses 3159system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133186 # number of ReadSharedReq misses 3160system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses 3161system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2 # number of ReadSharedReq misses 3162system.l2c.ReadSharedReq_misses::cpu1.inst 2822 # number of ReadSharedReq misses 3163system.l2c.ReadSharedReq_misses::cpu1.data 1110 # number of ReadSharedReq misses 3164system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8266 # number of ReadSharedReq misses 3165system.l2c.ReadSharedReq_misses::total 174307 # number of ReadSharedReq misses 3166system.l2c.demand_misses::cpu0.dtb.walker 26 # number of demand (read+write) misses 3167system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3168system.l2c.demand_misses::cpu0.inst 19633 # number of demand (read+write) misses 3169system.l2c.demand_misses::cpu0.data 20864 # number of demand (read+write) misses 3170system.l2c.demand_misses::cpu0.l2cache.prefetcher 133186 # number of demand (read+write) misses 3171system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses 3172system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses 3173system.l2c.demand_misses::cpu1.inst 2822 # number of demand (read+write) misses 3174system.l2c.demand_misses::cpu1.data 9950 # number of demand (read+write) misses 3175system.l2c.demand_misses::cpu1.l2cache.prefetcher 8266 # number of demand (read+write) misses 3176system.l2c.demand_misses::total 194758 # number of demand (read+write) misses 3177system.l2c.overall_misses::cpu0.dtb.walker 26 # number of overall misses 3178system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3179system.l2c.overall_misses::cpu0.inst 19633 # number of overall misses 3180system.l2c.overall_misses::cpu0.data 20864 # number of overall misses 3181system.l2c.overall_misses::cpu0.l2cache.prefetcher 133186 # number of overall misses 3182system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses 3183system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses 3184system.l2c.overall_misses::cpu1.inst 2822 # number of overall misses 3185system.l2c.overall_misses::cpu1.data 9950 # number of overall misses 3186system.l2c.overall_misses::cpu1.l2cache.prefetcher 8266 # number of overall misses 3187system.l2c.overall_misses::total 194758 # number of overall misses 3188system.l2c.UpgradeReq_miss_latency::cpu0.data 9483000 # number of UpgradeReq miss cycles 3189system.l2c.UpgradeReq_miss_latency::cpu1.data 2934500 # number of UpgradeReq miss cycles 3190system.l2c.UpgradeReq_miss_latency::total 12417500 # number of UpgradeReq miss cycles 3191system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1522000 # number of SCUpgradeReq miss cycles 3192system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1065500 # number of SCUpgradeReq miss cycles 3193system.l2c.SCUpgradeReq_miss_latency::total 2587500 # number of SCUpgradeReq miss cycles 3194system.l2c.ReadExReq_miss_latency::cpu0.data 1194143500 # number of ReadExReq miss cycles 3195system.l2c.ReadExReq_miss_latency::cpu1.data 746705000 # number of ReadExReq miss cycles 3196system.l2c.ReadExReq_miss_latency::total 1940848500 # number of ReadExReq miss cycles 3197system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2594500 # number of ReadSharedReq miss cycles 3198system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 241000 # number of ReadSharedReq miss cycles 3199system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1627006500 # number of ReadSharedReq miss cycles 3200system.l2c.ReadSharedReq_miss_latency::cpu0.data 844846000 # number of ReadSharedReq miss cycles 3201system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14630340281 # number of ReadSharedReq miss cycles 3202system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 545000 # number of ReadSharedReq miss cycles 3203system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 187000 # number of ReadSharedReq miss cycles 3204system.l2c.ReadSharedReq_miss_latency::cpu1.inst 244475000 # number of ReadSharedReq miss cycles 3205system.l2c.ReadSharedReq_miss_latency::cpu1.data 105182000 # number of ReadSharedReq miss cycles 3206system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1113216216 # number of ReadSharedReq miss cycles 3207system.l2c.ReadSharedReq_miss_latency::total 18568633497 # number of ReadSharedReq miss cycles 3208system.l2c.demand_miss_latency::cpu0.dtb.walker 2594500 # number of demand (read+write) miss cycles 3209system.l2c.demand_miss_latency::cpu0.itb.walker 241000 # number of demand (read+write) miss cycles 3210system.l2c.demand_miss_latency::cpu0.inst 1627006500 # number of demand (read+write) miss cycles 3211system.l2c.demand_miss_latency::cpu0.data 2038989500 # number of demand (read+write) miss cycles 3212system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14630340281 # number of demand (read+write) miss cycles 3213system.l2c.demand_miss_latency::cpu1.dtb.walker 545000 # number of demand (read+write) miss cycles 3214system.l2c.demand_miss_latency::cpu1.itb.walker 187000 # number of demand (read+write) miss cycles 3215system.l2c.demand_miss_latency::cpu1.inst 244475000 # number of demand (read+write) miss cycles 3216system.l2c.demand_miss_latency::cpu1.data 851887000 # number of demand (read+write) miss cycles 3217system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1113216216 # number of demand (read+write) miss cycles 3218system.l2c.demand_miss_latency::total 20509481997 # number of demand (read+write) miss cycles 3219system.l2c.overall_miss_latency::cpu0.dtb.walker 2594500 # number of overall miss cycles 3220system.l2c.overall_miss_latency::cpu0.itb.walker 241000 # number of overall miss cycles 3221system.l2c.overall_miss_latency::cpu0.inst 1627006500 # number of overall miss cycles 3222system.l2c.overall_miss_latency::cpu0.data 2038989500 # number of overall miss cycles 3223system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14630340281 # number of overall miss cycles 3224system.l2c.overall_miss_latency::cpu1.dtb.walker 545000 # number of overall miss cycles 3225system.l2c.overall_miss_latency::cpu1.itb.walker 187000 # number of overall miss cycles 3226system.l2c.overall_miss_latency::cpu1.inst 244475000 # number of overall miss cycles 3227system.l2c.overall_miss_latency::cpu1.data 851887000 # number of overall miss cycles 3228system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1113216216 # number of overall miss cycles 3229system.l2c.overall_miss_latency::total 20509481997 # number of overall miss cycles 3230system.l2c.WritebackDirty_accesses::writebacks 267222 # number of WritebackDirty accesses(hits+misses) 3231system.l2c.WritebackDirty_accesses::total 267222 # number of WritebackDirty accesses(hits+misses) 3232system.l2c.UpgradeReq_accesses::cpu0.data 41516 # number of UpgradeReq accesses(hits+misses) 3233system.l2c.UpgradeReq_accesses::cpu1.data 5476 # number of UpgradeReq accesses(hits+misses) 3234system.l2c.UpgradeReq_accesses::total 46992 # number of UpgradeReq accesses(hits+misses) 3235system.l2c.SCUpgradeReq_accesses::cpu0.data 2703 # number of SCUpgradeReq accesses(hits+misses) 3236system.l2c.SCUpgradeReq_accesses::cpu1.data 2226 # number of SCUpgradeReq accesses(hits+misses) 3237system.l2c.SCUpgradeReq_accesses::total 4929 # number of SCUpgradeReq accesses(hits+misses) 3238system.l2c.ReadExReq_accesses::cpu0.data 15563 # number of ReadExReq accesses(hits+misses) 3239system.l2c.ReadExReq_accesses::cpu1.data 10184 # number of ReadExReq accesses(hits+misses) 3240system.l2c.ReadExReq_accesses::total 25747 # number of ReadExReq accesses(hits+misses) 3241system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 215 # number of ReadSharedReq accesses(hits+misses) 3242system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 82 # number of ReadSharedReq accesses(hits+misses) 3243system.l2c.ReadSharedReq_accesses::cpu0.inst 53391 # number of ReadSharedReq accesses(hits+misses) 3244system.l2c.ReadSharedReq_accesses::cpu0.data 56456 # number of ReadSharedReq accesses(hits+misses) 3245system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179245 # number of ReadSharedReq accesses(hits+misses) 3246system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 75 # number of ReadSharedReq accesses(hits+misses) 3247system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 39 # number of ReadSharedReq accesses(hits+misses) 3248system.l2c.ReadSharedReq_accesses::cpu1.inst 16010 # number of ReadSharedReq accesses(hits+misses) 3249system.l2c.ReadSharedReq_accesses::cpu1.data 10977 # number of ReadSharedReq accesses(hits+misses) 3250system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 13840 # number of ReadSharedReq accesses(hits+misses) 3251system.l2c.ReadSharedReq_accesses::total 330330 # number of ReadSharedReq accesses(hits+misses) 3252system.l2c.demand_accesses::cpu0.dtb.walker 215 # number of demand (read+write) accesses 3253system.l2c.demand_accesses::cpu0.itb.walker 82 # number of demand (read+write) accesses 3254system.l2c.demand_accesses::cpu0.inst 53391 # number of demand (read+write) accesses 3255system.l2c.demand_accesses::cpu0.data 72019 # number of demand (read+write) accesses 3256system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179245 # number of demand (read+write) accesses 3257system.l2c.demand_accesses::cpu1.dtb.walker 75 # number of demand (read+write) accesses 3258system.l2c.demand_accesses::cpu1.itb.walker 39 # number of demand (read+write) accesses 3259system.l2c.demand_accesses::cpu1.inst 16010 # number of demand (read+write) accesses 3260system.l2c.demand_accesses::cpu1.data 21161 # number of demand (read+write) accesses 3261system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13840 # number of demand (read+write) accesses 3262system.l2c.demand_accesses::total 356077 # number of demand (read+write) accesses 3263system.l2c.overall_accesses::cpu0.dtb.walker 215 # number of overall (read+write) accesses 3264system.l2c.overall_accesses::cpu0.itb.walker 82 # number of overall (read+write) accesses 3265system.l2c.overall_accesses::cpu0.inst 53391 # number of overall (read+write) accesses 3266system.l2c.overall_accesses::cpu0.data 72019 # number of overall (read+write) accesses 3267system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179245 # number of overall (read+write) accesses 3268system.l2c.overall_accesses::cpu1.dtb.walker 75 # number of overall (read+write) accesses 3269system.l2c.overall_accesses::cpu1.itb.walker 39 # number of overall (read+write) accesses 3270system.l2c.overall_accesses::cpu1.inst 16010 # number of overall (read+write) accesses 3271system.l2c.overall_accesses::cpu1.data 21161 # number of overall (read+write) accesses 3272system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13840 # number of overall (read+write) accesses 3273system.l2c.overall_accesses::total 356077 # number of overall (read+write) accesses 3274system.l2c.UpgradeReq_miss_rate::cpu0.data 0.217723 # miss rate for UpgradeReq accesses 3275system.l2c.UpgradeReq_miss_rate::cpu1.data 0.506574 # miss rate for UpgradeReq accesses 3276system.l2c.UpgradeReq_miss_rate::total 0.251383 # miss rate for UpgradeReq accesses 3277system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.241583 # miss rate for SCUpgradeReq accesses 3278system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.574124 # miss rate for SCUpgradeReq accesses 3279system.l2c.SCUpgradeReq_miss_rate::total 0.391763 # miss rate for SCUpgradeReq accesses 3280system.l2c.ReadExReq_miss_rate::cpu0.data 0.746064 # miss rate for ReadExReq accesses 3281system.l2c.ReadExReq_miss_rate::cpu1.data 0.868028 # miss rate for ReadExReq accesses 3282system.l2c.ReadExReq_miss_rate::total 0.794306 # miss rate for ReadExReq accesses 3283system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.120930 # miss rate for ReadSharedReq accesses 3284system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036585 # miss rate for ReadSharedReq accesses 3285system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367721 # miss rate for ReadSharedReq accesses 3286system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.163898 # miss rate for ReadSharedReq accesses 3287system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743039 # miss rate for ReadSharedReq accesses 3288system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.080000 # miss rate for ReadSharedReq accesses 3289system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.051282 # miss rate for ReadSharedReq accesses 3290system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176265 # miss rate for ReadSharedReq accesses 3291system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.101121 # miss rate for ReadSharedReq accesses 3292system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.597254 # miss rate for ReadSharedReq accesses 3293system.l2c.ReadSharedReq_miss_rate::total 0.527675 # miss rate for ReadSharedReq accesses 3294system.l2c.demand_miss_rate::cpu0.dtb.walker 0.120930 # miss rate for demand accesses 3295system.l2c.demand_miss_rate::cpu0.itb.walker 0.036585 # miss rate for demand accesses 3296system.l2c.demand_miss_rate::cpu0.inst 0.367721 # miss rate for demand accesses 3297system.l2c.demand_miss_rate::cpu0.data 0.289701 # miss rate for demand accesses 3298system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743039 # miss rate for demand accesses 3299system.l2c.demand_miss_rate::cpu1.dtb.walker 0.080000 # miss rate for demand accesses 3300system.l2c.demand_miss_rate::cpu1.itb.walker 0.051282 # miss rate for demand accesses 3301system.l2c.demand_miss_rate::cpu1.inst 0.176265 # miss rate for demand accesses 3302system.l2c.demand_miss_rate::cpu1.data 0.470205 # miss rate for demand accesses 3303system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.597254 # miss rate for demand accesses 3304system.l2c.demand_miss_rate::total 0.546955 # miss rate for demand accesses 3305system.l2c.overall_miss_rate::cpu0.dtb.walker 0.120930 # miss rate for overall accesses 3306system.l2c.overall_miss_rate::cpu0.itb.walker 0.036585 # miss rate for overall accesses 3307system.l2c.overall_miss_rate::cpu0.inst 0.367721 # miss rate for overall accesses 3308system.l2c.overall_miss_rate::cpu0.data 0.289701 # miss rate for overall accesses 3309system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743039 # miss rate for overall accesses 3310system.l2c.overall_miss_rate::cpu1.dtb.walker 0.080000 # miss rate for overall accesses 3311system.l2c.overall_miss_rate::cpu1.itb.walker 0.051282 # miss rate for overall accesses 3312system.l2c.overall_miss_rate::cpu1.inst 0.176265 # miss rate for overall accesses 3313system.l2c.overall_miss_rate::cpu1.data 0.470205 # miss rate for overall accesses 3314system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.597254 # miss rate for overall accesses 3315system.l2c.overall_miss_rate::total 0.546955 # miss rate for overall accesses 3316system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1049.120478 # average UpgradeReq miss latency 3317system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1057.858688 # average UpgradeReq miss latency 3318system.l2c.UpgradeReq_avg_miss_latency::total 1051.172437 # average UpgradeReq miss latency 3319system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2330.781011 # average SCUpgradeReq miss latency 3320system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 833.724570 # average SCUpgradeReq miss latency 3321system.l2c.SCUpgradeReq_avg_miss_latency::total 1339.979285 # average SCUpgradeReq miss latency 3322system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102845.878908 # average ReadExReq miss latency 3323system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84468.891403 # average ReadExReq miss latency 3324system.l2c.ReadExReq_avg_miss_latency::total 94902.376412 # average ReadExReq miss latency 3325system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99788.461538 # average ReadSharedReq miss latency 3326system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency 3327system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82871.007997 # average ReadSharedReq miss latency 3328system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91305.090241 # average ReadSharedReq miss latency 3329system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181 # average ReadSharedReq miss latency 3330system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90833.333333 # average ReadSharedReq miss latency 3331system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 93500 # average ReadSharedReq miss latency 3332system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86631.821403 # average ReadSharedReq miss latency 3333system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 94758.558559 # average ReadSharedReq miss latency 3334system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751 # average ReadSharedReq miss latency 3335system.l2c.ReadSharedReq_avg_miss_latency::total 106528.329310 # average ReadSharedReq miss latency 3336system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99788.461538 # average overall miss latency 3337system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3338system.l2c.demand_avg_miss_latency::cpu0.inst 82871.007997 # average overall miss latency 3339system.l2c.demand_avg_miss_latency::cpu0.data 97727.640913 # average overall miss latency 3340system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181 # average overall miss latency 3341system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90833.333333 # average overall miss latency 3342system.l2c.demand_avg_miss_latency::cpu1.itb.walker 93500 # average overall miss latency 3343system.l2c.demand_avg_miss_latency::cpu1.inst 86631.821403 # average overall miss latency 3344system.l2c.demand_avg_miss_latency::cpu1.data 85616.783920 # average overall miss latency 3345system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751 # average overall miss latency 3346system.l2c.demand_avg_miss_latency::total 105307.520086 # average overall miss latency 3347system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99788.461538 # average overall miss latency 3348system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3349system.l2c.overall_avg_miss_latency::cpu0.inst 82871.007997 # average overall miss latency 3350system.l2c.overall_avg_miss_latency::cpu0.data 97727.640913 # average overall miss latency 3351system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181 # average overall miss latency 3352system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90833.333333 # average overall miss latency 3353system.l2c.overall_avg_miss_latency::cpu1.itb.walker 93500 # average overall miss latency 3354system.l2c.overall_avg_miss_latency::cpu1.inst 86631.821403 # average overall miss latency 3355system.l2c.overall_avg_miss_latency::cpu1.data 85616.783920 # average overall miss latency 3356system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751 # average overall miss latency 3357system.l2c.overall_avg_miss_latency::total 105307.520086 # average overall miss latency 3358system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3359system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3360system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3361system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3362system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3363system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3364system.l2c.writebacks::writebacks 103831 # number of writebacks 3365system.l2c.writebacks::total 103831 # number of writebacks 3366system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 10 # number of ReadSharedReq MSHR hits 3367system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 16 # number of ReadSharedReq MSHR hits 3368system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits 3369system.l2c.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits 3370system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits 3371system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 3372system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 3373system.l2c.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits 3374system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits 3375system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 3376system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 3377system.l2c.overall_mshr_hits::total 27 # number of overall MSHR hits 3378system.l2c.CleanEvict_mshr_misses::writebacks 3781 # number of CleanEvict MSHR misses 3379system.l2c.CleanEvict_mshr_misses::total 3781 # number of CleanEvict MSHR misses 3380system.l2c.UpgradeReq_mshr_misses::cpu0.data 9039 # number of UpgradeReq MSHR misses 3381system.l2c.UpgradeReq_mshr_misses::cpu1.data 2774 # number of UpgradeReq MSHR misses 3382system.l2c.UpgradeReq_mshr_misses::total 11813 # number of UpgradeReq MSHR misses 3383system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 653 # number of SCUpgradeReq MSHR misses 3384system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1278 # number of SCUpgradeReq MSHR misses 3385system.l2c.SCUpgradeReq_mshr_misses::total 1931 # number of SCUpgradeReq MSHR misses 3386system.l2c.ReadExReq_mshr_misses::cpu0.data 11611 # number of ReadExReq MSHR misses 3387system.l2c.ReadExReq_mshr_misses::cpu1.data 8840 # number of ReadExReq MSHR misses 3388system.l2c.ReadExReq_mshr_misses::total 20451 # number of ReadExReq MSHR misses 3389system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 26 # number of ReadSharedReq MSHR misses 3390system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses 3391system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19623 # number of ReadSharedReq MSHR misses 3392system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9253 # number of ReadSharedReq MSHR misses 3393system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133186 # number of ReadSharedReq MSHR misses 3394system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses 3395system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2 # number of ReadSharedReq MSHR misses 3396system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2806 # number of ReadSharedReq MSHR misses 3397system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1109 # number of ReadSharedReq MSHR misses 3398system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8266 # number of ReadSharedReq MSHR misses 3399system.l2c.ReadSharedReq_mshr_misses::total 174280 # number of ReadSharedReq MSHR misses 3400system.l2c.demand_mshr_misses::cpu0.dtb.walker 26 # number of demand (read+write) MSHR misses 3401system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 3402system.l2c.demand_mshr_misses::cpu0.inst 19623 # number of demand (read+write) MSHR misses 3403system.l2c.demand_mshr_misses::cpu0.data 20864 # number of demand (read+write) MSHR misses 3404system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133186 # number of demand (read+write) MSHR misses 3405system.l2c.demand_mshr_misses::cpu1.dtb.walker 6 # number of demand (read+write) MSHR misses 3406system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses 3407system.l2c.demand_mshr_misses::cpu1.inst 2806 # number of demand (read+write) MSHR misses 3408system.l2c.demand_mshr_misses::cpu1.data 9949 # number of demand (read+write) MSHR misses 3409system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8266 # number of demand (read+write) MSHR misses 3410system.l2c.demand_mshr_misses::total 194731 # number of demand (read+write) MSHR misses 3411system.l2c.overall_mshr_misses::cpu0.dtb.walker 26 # number of overall MSHR misses 3412system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 3413system.l2c.overall_mshr_misses::cpu0.inst 19623 # number of overall MSHR misses 3414system.l2c.overall_mshr_misses::cpu0.data 20864 # number of overall MSHR misses 3415system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133186 # number of overall MSHR misses 3416system.l2c.overall_mshr_misses::cpu1.dtb.walker 6 # number of overall MSHR misses 3417system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses 3418system.l2c.overall_mshr_misses::cpu1.inst 2806 # number of overall MSHR misses 3419system.l2c.overall_mshr_misses::cpu1.data 9949 # number of overall MSHR misses 3420system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8266 # number of overall MSHR misses 3421system.l2c.overall_mshr_misses::total 194731 # number of overall MSHR misses 3422system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 3423system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31772 # number of ReadReq MSHR uncacheable 3424system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable 3425system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable 3426system.l2c.ReadReq_mshr_uncacheable::total 37954 # number of ReadReq MSHR uncacheable 3427system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28451 # number of WriteReq MSHR uncacheable 3428system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2438 # number of WriteReq MSHR uncacheable 3429system.l2c.WriteReq_mshr_uncacheable::total 30889 # number of WriteReq MSHR uncacheable 3430system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 3431system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60223 # number of overall MSHR uncacheable misses 3432system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses 3433system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5516 # number of overall MSHR uncacheable misses 3434system.l2c.overall_mshr_uncacheable_misses::total 68843 # number of overall MSHR uncacheable misses 3435system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 214811000 # number of UpgradeReq MSHR miss cycles 3436system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63023000 # number of UpgradeReq MSHR miss cycles 3437system.l2c.UpgradeReq_mshr_miss_latency::total 277834000 # number of UpgradeReq MSHR miss cycles 3438system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16846000 # number of SCUpgradeReq MSHR miss cycles 3439system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 31830500 # number of SCUpgradeReq MSHR miss cycles 3440system.l2c.SCUpgradeReq_mshr_miss_latency::total 48676500 # number of SCUpgradeReq MSHR miss cycles 3441system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1078033001 # number of ReadExReq MSHR miss cycles 3442system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 658304002 # number of ReadExReq MSHR miss cycles 3443system.l2c.ReadExReq_mshr_miss_latency::total 1736337003 # number of ReadExReq MSHR miss cycles 3444system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2334500 # number of ReadSharedReq MSHR miss cycles 3445system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 211000 # number of ReadSharedReq MSHR miss cycles 3446system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1430147005 # number of ReadSharedReq MSHR miss cycles 3447system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 752316000 # number of ReadSharedReq MSHR miss cycles 3448system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13298476788 # number of ReadSharedReq MSHR miss cycles 3449system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 485000 # number of ReadSharedReq MSHR miss cycles 3450system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 167000 # number of ReadSharedReq MSHR miss cycles 3451system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 215303006 # number of ReadSharedReq MSHR miss cycles 3452system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 94038501 # number of ReadSharedReq MSHR miss cycles 3453system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1030554221 # number of ReadSharedReq MSHR miss cycles 3454system.l2c.ReadSharedReq_mshr_miss_latency::total 16824033021 # number of ReadSharedReq MSHR miss cycles 3455system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2334500 # number of demand (read+write) MSHR miss cycles 3456system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 211000 # number of demand (read+write) MSHR miss cycles 3457system.l2c.demand_mshr_miss_latency::cpu0.inst 1430147005 # number of demand (read+write) MSHR miss cycles 3458system.l2c.demand_mshr_miss_latency::cpu0.data 1830349001 # number of demand (read+write) MSHR miss cycles 3459system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13298476788 # number of demand (read+write) MSHR miss cycles 3460system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 485000 # number of demand (read+write) MSHR miss cycles 3461system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 167000 # number of demand (read+write) MSHR miss cycles 3462system.l2c.demand_mshr_miss_latency::cpu1.inst 215303006 # number of demand (read+write) MSHR miss cycles 3463system.l2c.demand_mshr_miss_latency::cpu1.data 752342503 # number of demand (read+write) MSHR miss cycles 3464system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1030554221 # number of demand (read+write) MSHR miss cycles 3465system.l2c.demand_mshr_miss_latency::total 18560370024 # number of demand (read+write) MSHR miss cycles 3466system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2334500 # number of overall MSHR miss cycles 3467system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 211000 # number of overall MSHR miss cycles 3468system.l2c.overall_mshr_miss_latency::cpu0.inst 1430147005 # number of overall MSHR miss cycles 3469system.l2c.overall_mshr_miss_latency::cpu0.data 1830349001 # number of overall MSHR miss cycles 3470system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13298476788 # number of overall MSHR miss cycles 3471system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 485000 # number of overall MSHR miss cycles 3472system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 167000 # number of overall MSHR miss cycles 3473system.l2c.overall_mshr_miss_latency::cpu1.inst 215303006 # number of overall MSHR miss cycles 3474system.l2c.overall_mshr_miss_latency::cpu1.data 752342503 # number of overall MSHR miss cycles 3475system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1030554221 # number of overall MSHR miss cycles 3476system.l2c.overall_mshr_miss_latency::total 18560370024 # number of overall MSHR miss cycles 3477system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 192566500 # number of ReadReq MSHR uncacheable cycles 3478system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5794675500 # number of ReadReq MSHR uncacheable cycles 3479system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6549000 # number of ReadReq MSHR uncacheable cycles 3480system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 361974000 # number of ReadReq MSHR uncacheable cycles 3481system.l2c.ReadReq_mshr_uncacheable_latency::total 6355765000 # number of ReadReq MSHR uncacheable cycles 3482system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 192566500 # number of overall MSHR uncacheable cycles 3483system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5794675500 # number of overall MSHR uncacheable cycles 3484system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6549000 # number of overall MSHR uncacheable cycles 3485system.l2c.overall_mshr_uncacheable_latency::cpu1.data 361974000 # number of overall MSHR uncacheable cycles 3486system.l2c.overall_mshr_uncacheable_latency::total 6355765000 # number of overall MSHR uncacheable cycles 3487system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3488system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3489system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.217723 # mshr miss rate for UpgradeReq accesses 3490system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.506574 # mshr miss rate for UpgradeReq accesses 3491system.l2c.UpgradeReq_mshr_miss_rate::total 0.251383 # mshr miss rate for UpgradeReq accesses 3492system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.241583 # mshr miss rate for SCUpgradeReq accesses 3493system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.574124 # mshr miss rate for SCUpgradeReq accesses 3494system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.391763 # mshr miss rate for SCUpgradeReq accesses 3495system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746064 # mshr miss rate for ReadExReq accesses 3496system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.868028 # mshr miss rate for ReadExReq accesses 3497system.l2c.ReadExReq_mshr_miss_rate::total 0.794306 # mshr miss rate for ReadExReq accesses 3498system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.120930 # mshr miss rate for ReadSharedReq accesses 3499system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036585 # mshr miss rate for ReadSharedReq accesses 3500system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.367534 # mshr miss rate for ReadSharedReq accesses 3501system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.163898 # mshr miss rate for ReadSharedReq accesses 3502system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743039 # mshr miss rate for ReadSharedReq accesses 3503system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.080000 # mshr miss rate for ReadSharedReq accesses 3504system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.051282 # mshr miss rate for ReadSharedReq accesses 3505system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.175265 # mshr miss rate for ReadSharedReq accesses 3506system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.101029 # mshr miss rate for ReadSharedReq accesses 3507system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.597254 # mshr miss rate for ReadSharedReq accesses 3508system.l2c.ReadSharedReq_mshr_miss_rate::total 0.527594 # mshr miss rate for ReadSharedReq accesses 3509system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.120930 # mshr miss rate for demand accesses 3510system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036585 # mshr miss rate for demand accesses 3511system.l2c.demand_mshr_miss_rate::cpu0.inst 0.367534 # mshr miss rate for demand accesses 3512system.l2c.demand_mshr_miss_rate::cpu0.data 0.289701 # mshr miss rate for demand accesses 3513system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743039 # mshr miss rate for demand accesses 3514system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.080000 # mshr miss rate for demand accesses 3515system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.051282 # mshr miss rate for demand accesses 3516system.l2c.demand_mshr_miss_rate::cpu1.inst 0.175265 # mshr miss rate for demand accesses 3517system.l2c.demand_mshr_miss_rate::cpu1.data 0.470157 # mshr miss rate for demand accesses 3518system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.597254 # mshr miss rate for demand accesses 3519system.l2c.demand_mshr_miss_rate::total 0.546879 # mshr miss rate for demand accesses 3520system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.120930 # mshr miss rate for overall accesses 3521system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036585 # mshr miss rate for overall accesses 3522system.l2c.overall_mshr_miss_rate::cpu0.inst 0.367534 # mshr miss rate for overall accesses 3523system.l2c.overall_mshr_miss_rate::cpu0.data 0.289701 # mshr miss rate for overall accesses 3524system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743039 # mshr miss rate for overall accesses 3525system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.080000 # mshr miss rate for overall accesses 3526system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.051282 # mshr miss rate for overall accesses 3527system.l2c.overall_mshr_miss_rate::cpu1.inst 0.175265 # mshr miss rate for overall accesses 3528system.l2c.overall_mshr_miss_rate::cpu1.data 0.470157 # mshr miss rate for overall accesses 3529system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.597254 # mshr miss rate for overall accesses 3530system.l2c.overall_mshr_miss_rate::total 0.546879 # mshr miss rate for overall accesses 3531system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23764.907623 # average UpgradeReq mshr miss latency 3532system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22719.178082 # average UpgradeReq mshr miss latency 3533system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23519.343097 # average UpgradeReq mshr miss latency 3534system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25797.856049 # average SCUpgradeReq mshr miss latency 3535system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24906.494523 # average SCUpgradeReq mshr miss latency 3536system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25207.923356 # average SCUpgradeReq mshr miss latency 3537system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92845.835931 # average ReadExReq mshr miss latency 3538system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74468.778507 # average ReadExReq mshr miss latency 3539system.l2c.ReadExReq_avg_mshr_miss_latency::total 84902.303213 # average ReadExReq mshr miss latency 3540system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average ReadSharedReq mshr miss latency 3541system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency 3542system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average ReadSharedReq mshr miss latency 3543system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81305.090241 # average ReadSharedReq mshr miss latency 3544system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average ReadSharedReq mshr miss latency 3545system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average ReadSharedReq mshr miss latency 3546system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq mshr miss latency 3547system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average ReadSharedReq mshr miss latency 3548system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84795.762849 # average ReadSharedReq mshr miss latency 3549system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average ReadSharedReq mshr miss latency 3550system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96534.502071 # average ReadSharedReq mshr miss latency 3551system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency 3552system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3553system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency 3554system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency 3555system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency 3556system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency 3557system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency 3558system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency 3559system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency 3560system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency 3561system.l2c.demand_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency 3562system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency 3563system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3564system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency 3565system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency 3566system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency 3567system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency 3568system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency 3569system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency 3570system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency 3571system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency 3572system.l2c.overall_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency 3573system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency 3574system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182383.088883 # average ReadReq mshr uncacheable latency 3575system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average ReadReq mshr uncacheable latency 3576system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117600.389864 # average ReadReq mshr uncacheable latency 3577system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167459.688043 # average ReadReq mshr uncacheable latency 3578system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency 3579system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96220.306195 # average overall mshr uncacheable latency 3580system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average overall mshr uncacheable latency 3581system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65622.552574 # average overall mshr uncacheable latency 3582system.l2c.overall_avg_mshr_uncacheable_latency::total 92322.603605 # average overall mshr uncacheable latency 3583system.membus.snoop_filter.tot_requests 523570 # Total number of requests made to the snoop filter. 3584system.membus.snoop_filter.hit_single_requests 298445 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3585system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3586system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3587system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3588system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3589system.membus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3590system.membus.trans_dist::ReadReq 37954 # Transaction distribution 3591system.membus.trans_dist::ReadResp 212485 # Transaction distribution 3592system.membus.trans_dist::WriteReq 30889 # Transaction distribution 3593system.membus.trans_dist::WriteResp 30889 # Transaction distribution 3594system.membus.trans_dist::WritebackDirty 140037 # Transaction distribution 3595system.membus.trans_dist::CleanEvict 17084 # Transaction distribution 3596system.membus.trans_dist::UpgradeReq 74884 # Transaction distribution 3597system.membus.trans_dist::SCUpgradeReq 40573 # Transaction distribution 3598system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 3599system.membus.trans_dist::ReadExReq 40212 # Transaction distribution 3600system.membus.trans_dist::ReadExResp 20363 # Transaction distribution 3601system.membus.trans_dist::ReadSharedReq 174532 # Transaction distribution 3602system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3603system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) 3604system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) 3605system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13624 # Packet count per connected master and slave (bytes) 3606system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661033 # Packet count per connected master and slave (bytes) 3607system.membus.pkt_count_system.l2c.mem_side::total 782607 # Packet count per connected master and slave (bytes) 3608system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3609system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) 3610system.membus.pkt_count::total 855556 # Packet count per connected master and slave (bytes) 3611system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) 3612system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) 3613system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27248 # Cumulative packet size per connected master and slave (bytes) 3614system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19150328 # Cumulative packet size per connected master and slave (bytes) 3615system.membus.pkt_size_system.l2c.mem_side::total 19340658 # Cumulative packet size per connected master and slave (bytes) 3616system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3617system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3618system.membus.pkt_size::total 21658802 # Cumulative packet size per connected master and slave (bytes) 3619system.membus.snoops 122046 # Total snoops (count) 3620system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) 3621system.membus.snoop_fanout::samples 435271 # Request fanout histogram 3622system.membus.snoop_fanout::mean 0.011878 # Request fanout histogram 3623system.membus.snoop_fanout::stdev 0.108336 # Request fanout histogram 3624system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3625system.membus.snoop_fanout::0 430101 98.81% 98.81% # Request fanout histogram 3626system.membus.snoop_fanout::1 5170 1.19% 100.00% # Request fanout histogram 3627system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3628system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3629system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3630system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3631system.membus.snoop_fanout::total 435271 # Request fanout histogram 3632system.membus.reqLayer0.occupancy 81633500 # Layer occupancy (ticks) 3633system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3634system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3635system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3636system.membus.reqLayer2.occupancy 11523000 # Layer occupancy (ticks) 3637system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3638system.membus.reqLayer5.occupancy 1022470046 # Layer occupancy (ticks) 3639system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3640system.membus.respLayer2.occupancy 1120816043 # Layer occupancy (ticks) 3641system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3642system.membus.respLayer3.occupancy 1359381 # Layer occupancy (ticks) 3643system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3644system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3645system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3646system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3647system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3648system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3649system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3650system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3651system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3652system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3653system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3654system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3655system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3656system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3657system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3658system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3659system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3660system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3661system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3662system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3663system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3664system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3665system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3666system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3667system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3668system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3669system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3670system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3671system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3672system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3673system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3674system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3675system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3676system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3677system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3678system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3679system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3680system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3681system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3682system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3683system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3684system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3685system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3686system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3687system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3688system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3689system.realview.ethernet.droppedPackets 0 # number of packets dropped 3690system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3691system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3692system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3693system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3694system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3695system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3696system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3697system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3698system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3699system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3700system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3701system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3702system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3703system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3704system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3705system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3706system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3707system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3708system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3709system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3710system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3711system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3712system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3713system.toL2Bus.snoop_filter.tot_requests 1014149 # Total number of requests made to the snoop filter. 3714system.toL2Bus.snoop_filter.hit_single_requests 548985 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3715system.toL2Bus.snoop_filter.hit_multi_requests 155175 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3716system.toL2Bus.snoop_filter.tot_snoops 21000 # Total number of snoops made to the snoop filter. 3717system.toL2Bus.snoop_filter.hit_single_snoops 20112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3718system.toL2Bus.snoop_filter.hit_multi_snoops 888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3719system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states 3720system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution 3721system.toL2Bus.trans_dist::ReadResp 486750 # Transaction distribution 3722system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution 3723system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution 3724system.toL2Bus.trans_dist::WritebackDirty 371053 # Transaction distribution 3725system.toL2Bus.trans_dist::CleanEvict 122899 # Transaction distribution 3726system.toL2Bus.trans_dist::UpgradeReq 109975 # Transaction distribution 3727system.toL2Bus.trans_dist::SCUpgradeReq 43571 # Transaction distribution 3728system.toL2Bus.trans_dist::UpgradeResp 153546 # Transaction distribution 3729system.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution 3730system.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution 3731system.toL2Bus.trans_dist::ReadExReq 50842 # Transaction distribution 3732system.toL2Bus.trans_dist::ReadExResp 50842 # Transaction distribution 3733system.toL2Bus.trans_dist::ReadSharedReq 448796 # Transaction distribution 3734system.toL2Bus.trans_dist::InvalidateReq 4596 # Transaction distribution 3735system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1244094 # Packet count per connected master and slave (bytes) 3736system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315957 # Packet count per connected master and slave (bytes) 3737system.toL2Bus.pkt_count::total 1560051 # Packet count per connected master and slave (bytes) 3738system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34491784 # Cumulative packet size per connected master and slave (bytes) 3739system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674154 # Cumulative packet size per connected master and slave (bytes) 3740system.toL2Bus.pkt_size::total 40165938 # Cumulative packet size per connected master and slave (bytes) 3741system.toL2Bus.snoops 382861 # Total snoops (count) 3742system.toL2Bus.snoopTraffic 15835212 # Total snoop traffic (bytes) 3743system.toL2Bus.snoop_fanout::samples 859470 # Request fanout histogram 3744system.toL2Bus.snoop_fanout::mean 0.375184 # Request fanout histogram 3745system.toL2Bus.snoop_fanout::stdev 0.486300 # Request fanout histogram 3746system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3747system.toL2Bus.snoop_fanout::0 537899 62.58% 62.58% # Request fanout histogram 3748system.toL2Bus.snoop_fanout::1 320683 37.31% 99.90% # Request fanout histogram 3749system.toL2Bus.snoop_fanout::2 888 0.10% 100.00% # Request fanout histogram 3750system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3751system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3752system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3753system.toL2Bus.snoop_fanout::total 859470 # Request fanout histogram 3754system.toL2Bus.reqLayer0.occupancy 886309294 # Layer occupancy (ticks) 3755system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3756system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) 3757system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3758system.toL2Bus.respLayer0.occupancy 648979933 # Layer occupancy (ticks) 3759system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3760system.toL2Bus.respLayer1.occupancy 232794950 # Layer occupancy (ticks) 3761system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3762system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3763system.cpu0.kern.inst.quiesce 1839 # number of quiesce instructions executed 3764system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3765system.cpu1.kern.inst.quiesce 2759 # number of quiesce instructions executed 3766 3767---------- End Simulation Statistics ---------- 3768