stats.txt revision 10848:e61f847e74fd
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.625378 # Number of seconds simulated 4sim_ticks 2625378187500 # Number of ticks simulated 5final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 105357 # Simulator instruction rate (inst/s) 8host_op_rate 127837 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2300779000 # Simulator tick rate (ticks/s) 10host_mem_usage 602544 # Number of bytes of host memory used 11host_seconds 1141.08 # Real time elapsed on the host 12sim_insts 120220550 # Number of instructions simulated 13sim_ops 145872273 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1156128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1193576 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8234944 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 336832 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 657616 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 605504 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12188376 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1156128 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 336832 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1492960 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8634432 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8651996 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 20310 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 19170 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 128671 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 5329 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 10295 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 9461 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 193295 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 134913 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 139304 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 658 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 440366 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 454630 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 3136670 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 268 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 128298 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 250484 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 230635 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 4642522 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 440366 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 128298 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 568665 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3288834 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 3295524 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3288834 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 658 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 440366 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 461305 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 3136670 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 268 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 128298 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 250500 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 230635 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7938046 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 193296 # Number of read requests accepted 84system.physmem.writeReqs 175528 # Number of write requests accepted 85system.physmem.readBursts 193296 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 175528 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12362624 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue 89system.physmem.bytesWritten 9724800 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12188440 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 10970332 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 23562 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 14506 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 12287 # Per bank write bursts 96system.physmem.perBankRdBursts::1 11514 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12472 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12180 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14590 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12444 # Per bank write bursts 101system.physmem.perBankRdBursts::6 12518 # Per bank write bursts 102system.physmem.perBankRdBursts::7 12466 # Per bank write bursts 103system.physmem.perBankRdBursts::8 11679 # Per bank write bursts 104system.physmem.perBankRdBursts::9 12089 # Per bank write bursts 105system.physmem.perBankRdBursts::10 11915 # Per bank write bursts 106system.physmem.perBankRdBursts::11 11053 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11299 # Per bank write bursts 108system.physmem.perBankRdBursts::13 11450 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11880 # Per bank write bursts 110system.physmem.perBankRdBursts::15 11330 # Per bank write bursts 111system.physmem.perBankWrBursts::0 9713 # Per bank write bursts 112system.physmem.perBankWrBursts::1 9189 # Per bank write bursts 113system.physmem.perBankWrBursts::2 10054 # Per bank write bursts 114system.physmem.perBankWrBursts::3 9647 # Per bank write bursts 115system.physmem.perBankWrBursts::4 9435 # Per bank write bursts 116system.physmem.perBankWrBursts::5 9608 # Per bank write bursts 117system.physmem.perBankWrBursts::6 10036 # Per bank write bursts 118system.physmem.perBankWrBursts::7 9866 # Per bank write bursts 119system.physmem.perBankWrBursts::8 9192 # Per bank write bursts 120system.physmem.perBankWrBursts::9 9471 # Per bank write bursts 121system.physmem.perBankWrBursts::10 9539 # Per bank write bursts 122system.physmem.perBankWrBursts::11 9209 # Per bank write bursts 123system.physmem.perBankWrBursts::12 9294 # Per bank write bursts 124system.physmem.perBankWrBursts::13 9108 # Per bank write bursts 125system.physmem.perBankWrBursts::14 9699 # Per bank write bursts 126system.physmem.perBankWrBursts::15 8890 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 46 # Number of times write queue was full causing retry 129system.physmem.totGap 2625377925000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 550 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 3082 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 189636 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4391 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 171137 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 58646 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 70721 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 16311 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 12182 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 8246 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 7467 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 6266 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 5177 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 4683 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1253 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 923 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 715 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 309 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 2100 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 2340 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 3256 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 4036 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 5294 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 5941 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 6575 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 8147 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 7082 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 7445 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 9281 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 7962 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 8621 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 11356 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 9282 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 8943 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 8063 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1588 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1232 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1372 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 2519 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 2445 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 1674 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 1915 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 2563 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 1837 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 1717 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 1608 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 1995 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 1694 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 1362 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 1075 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 796 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 429 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 337 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 134 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 87477 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 252.493341 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 140.519371 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 314.341475 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 45925 52.50% 52.50% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 16983 19.41% 71.91% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 5819 6.65% 78.57% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3357 3.84% 82.40% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2775 3.17% 85.58% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1460 1.67% 87.24% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 948 1.08% 88.33% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 995 1.14% 89.47% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 9215 10.53% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 87477 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 6395 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 30.205629 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 580.308341 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 6393 99.97% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::total 6395 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 6395 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 23.760751 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.753987 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 37.694415 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-31 6028 94.26% 94.26% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::32-47 95 1.49% 95.75% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::48-63 28 0.44% 96.18% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::64-79 10 0.16% 96.34% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::80-95 24 0.38% 96.72% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::96-111 40 0.63% 97.34% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::112-127 30 0.47% 97.81% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::128-143 13 0.20% 98.01% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::144-159 18 0.28% 98.30% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::160-175 5 0.08% 98.37% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::176-191 23 0.36% 98.73% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::192-207 21 0.33% 99.06% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::208-223 7 0.11% 99.17% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::224-239 3 0.05% 99.22% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::240-255 2 0.03% 99.25% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::256-271 5 0.08% 99.33% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::272-287 3 0.05% 99.37% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::288-303 2 0.03% 99.41% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::304-319 3 0.05% 99.45% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::320-335 7 0.11% 99.56% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::336-351 6 0.09% 99.66% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::352-367 11 0.17% 99.83% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::368-383 1 0.02% 99.84% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::384-399 2 0.03% 99.87% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::512-527 2 0.03% 99.94% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::528-543 3 0.05% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::688-703 1 0.02% 100.00% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::total 6395 # Writes before turning the bus around for reads 294system.physmem.totQLat 6824061250 # Total ticks spent queuing 295system.physmem.totMemAccLat 10445923750 # Total ticks spent from burst creation until serviced by the DRAM 296system.physmem.totBusLat 965830000 # Total ticks spent in databus transfers 297system.physmem.avgQLat 35327.45 # Average queueing delay per DRAM burst 298system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 299system.physmem.avgMemAccLat 54077.45 # Average memory access latency per DRAM burst 300system.physmem.avgRdBW 4.71 # Average DRAM read bandwidth in MiByte/s 301system.physmem.avgWrBW 3.70 # Average achieved write bandwidth in MiByte/s 302system.physmem.avgRdBWSys 4.64 # Average system read bandwidth in MiByte/s 303system.physmem.avgWrBWSys 4.18 # Average system write bandwidth in MiByte/s 304system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 305system.physmem.busUtil 0.07 # Data bus utilization in percentage 306system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 307system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 308system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 309system.physmem.avgWrQLen 27.24 # Average write queue length when enqueuing 310system.physmem.readRowHits 161531 # Number of row buffer hits during reads 311system.physmem.writeRowHits 96107 # Number of row buffer hits during writes 312system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads 313system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes 314system.physmem.avgGap 7118240.48 # Average gap between requests 315system.physmem.pageHitRate 74.65 # Row buffer hit rate, read and write combined 316system.physmem_0.actEnergy 340124400 # Energy for activate commands per rank (pJ) 317system.physmem_0.preEnergy 185583750 # Energy for precharge commands per rank (pJ) 318system.physmem_0.readEnergy 783673800 # Energy for read commands per rank (pJ) 319system.physmem_0.writeEnergy 502511040 # Energy for write commands per rank (pJ) 320system.physmem_0.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) 321system.physmem_0.actBackEnergy 74898468540 # Energy for active background per rank (pJ) 322system.physmem_0.preBackEnergy 1509525073500 # Energy for precharge background per rank (pJ) 323system.physmem_0.totalEnergy 1757712204390 # Total energy per rank (pJ) 324system.physmem_0.averagePower 669.508799 # Core power per rank (mW) 325system.physmem_0.memoryStateTime::IDLE 2511124862587 # Time in different power states 326system.physmem_0.memoryStateTime::REF 87667060000 # Time in different power states 327system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 328system.physmem_0.memoryStateTime::ACT 26583898663 # Time in different power states 329system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 330system.physmem_1.actEnergy 321201720 # Energy for activate commands per rank (pJ) 331system.physmem_1.preEnergy 175258875 # Energy for precharge commands per rank (pJ) 332system.physmem_1.readEnergy 723013200 # Energy for read commands per rank (pJ) 333system.physmem_1.writeEnergy 482124960 # Energy for write commands per rank (pJ) 334system.physmem_1.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) 335system.physmem_1.actBackEnergy 74441693340 # Energy for active background per rank (pJ) 336system.physmem_1.preBackEnergy 1509925753500 # Energy for precharge background per rank (pJ) 337system.physmem_1.totalEnergy 1757545814955 # Total energy per rank (pJ) 338system.physmem_1.averagePower 669.445422 # Core power per rank (mW) 339system.physmem_1.memoryStateTime::IDLE 2511799542258 # Time in different power states 340system.physmem_1.memoryStateTime::REF 87667060000 # Time in different power states 341system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 342system.physmem_1.memoryStateTime::ACT 25911565742 # Time in different power states 343system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 344system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 350system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 351system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 353system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) 362system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 631 # Number of DMA write transactions. 368system.cpu0.branchPred.lookups 22612465 # Number of BP lookups 369system.cpu0.branchPred.condPredicted 14651481 # Number of conditional branches predicted 370system.cpu0.branchPred.condIncorrect 907853 # Number of conditional branches incorrect 371system.cpu0.branchPred.BTBLookups 13732961 # Number of BTB lookups 372system.cpu0.branchPred.BTBHits 10133003 # Number of BTB hits 373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 374system.cpu0.branchPred.BTBHitPct 73.786003 # BTB Hit Percentage 375system.cpu0.branchPred.usedRAS 3723828 # Number of times the RAS was used to get a target. 376system.cpu0.branchPred.RASInCorrect 29274 # Number of incorrect RAS predictions. 377system.cpu_clk_domain.clock 500 # Clock period in ticks 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 387system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 388system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 389system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 390system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 391system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 392system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 393system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 396system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 397system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 398system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 399system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 401system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 402system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 403system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 404system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 405system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 406system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 407system.cpu0.dtb.walker.walks 61748 # Table walker walks requested 408system.cpu0.dtb.walker.walksShort 61748 # Table walker walks initiated with short descriptors 409system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23984 # Level at which table walker walks with short descriptors terminate 410system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18764 # Level at which table walker walks with short descriptors terminate 411system.cpu0.dtb.walker.walksSquashedBefore 19000 # Table walks squashed before starting 412system.cpu0.dtb.walker.walkWaitTime::samples 42748 # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::mean 436.289417 # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkWaitTime::stdev 2694.039371 # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::0-8191 41732 97.62% 97.62% # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::8192-16383 726 1.70% 99.32% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::16384-24575 177 0.41% 99.74% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::24576-32767 77 0.18% 99.92% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.04% 99.99% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::49152-57343 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::total 42748 # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkCompletionTime::samples 15024 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::mean 8664.869276 # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::gmean 7136.607726 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::stdev 7119.581025 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::0-16383 14229 94.71% 94.71% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::16384-32767 745 4.96% 99.67% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::32768-49151 26 0.17% 99.84% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.03% 99.87% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.89% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::131072-147455 16 0.11% 99.99% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::total 15024 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walksPending::samples 87051634064 # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::mean 0.443285 # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::stdev 0.503059 # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::0-1 87007241564 99.95% 99.95% # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::2-3 33256500 0.04% 99.99% # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::4-5 5843000 0.01% 99.99% # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::6-7 2996500 0.00% 100.00% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::8-9 874000 0.00% 100.00% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::10-11 581000 0.00% 100.00% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::12-13 581000 0.00% 100.00% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::14-15 249500 0.00% 100.00% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::16-17 11000 0.00% 100.00% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::total 87051634064 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walkPageSizes::4K 5088 77.48% 77.48% # Table walker page sizes translated 451system.cpu0.dtb.walker.walkPageSizes::1M 1479 22.52% 100.00% # Table walker page sizes translated 452system.cpu0.dtb.walker.walkPageSizes::total 6567 # Table walker page sizes translated 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61748 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61748 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6567 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6567 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin::total 68315 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.inst_hits 0 # ITB inst hits 461system.cpu0.dtb.inst_misses 0 # ITB inst misses 462system.cpu0.dtb.read_hits 16748968 # DTB read hits 463system.cpu0.dtb.read_misses 52995 # DTB read misses 464system.cpu0.dtb.write_hits 13907664 # DTB write hits 465system.cpu0.dtb.write_misses 8753 # DTB write misses 466system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 467system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 468system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 469system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 470system.cpu0.dtb.flush_entries 3489 # Number of entries that have been flushed from TLB 471system.cpu0.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions 472system.cpu0.dtb.prefetch_faults 2047 # Number of TLB faults due to prefetch 473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 474system.cpu0.dtb.perms_faults 843 # Number of TLB faults due to permissions restrictions 475system.cpu0.dtb.read_accesses 16801963 # DTB read accesses 476system.cpu0.dtb.write_accesses 13916417 # DTB write accesses 477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 478system.cpu0.dtb.hits 30656632 # DTB hits 479system.cpu0.dtb.misses 61748 # DTB misses 480system.cpu0.dtb.accesses 30718380 # DTB accesses 481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 490system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 491system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 492system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 493system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 494system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 495system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 496system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 499system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 500system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 501system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 510system.cpu0.itb.walker.walks 9874 # Table walker walks requested 511system.cpu0.itb.walker.walksShort 9874 # Table walker walks initiated with short descriptors 512system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3715 # Level at which table walker walks with short descriptors terminate 513system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6056 # Level at which table walker walks with short descriptors terminate 514system.cpu0.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting 515system.cpu0.itb.walker.walkWaitTime::samples 9771 # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::mean 366.390339 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::stdev 1951.164851 # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::0-4095 9421 96.42% 96.42% # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::4096-8191 224 2.29% 98.71% # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::8192-12287 80 0.82% 99.53% # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkWaitTime::12288-16383 17 0.17% 99.70% # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.84% # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::20480-24575 5 0.05% 99.89% # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.93% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::28672-32767 6 0.06% 99.99% # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::total 9771 # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkCompletionTime::samples 2691 # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::mean 9965.812709 # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::gmean 8554.132900 # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::stdev 5681.325139 # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::0-8191 1024 38.05% 38.05% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::8192-16383 1554 57.75% 95.80% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::16384-24575 43 1.60% 97.40% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::24576-32767 63 2.34% 99.74% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::32768-40959 4 0.15% 99.89% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::total 2691 # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walksPending::samples 18106130328 # Table walker pending requests distribution 541system.cpu0.itb.walker.walksPending::mean 0.976227 # Table walker pending requests distribution 542system.cpu0.itb.walker.walksPending::stdev 0.152552 # Table walker pending requests distribution 543system.cpu0.itb.walker.walksPending::0 430953000 2.38% 2.38% # Table walker pending requests distribution 544system.cpu0.itb.walker.walksPending::1 17674714828 97.62% 100.00% # Table walker pending requests distribution 545system.cpu0.itb.walker.walksPending::2 401500 0.00% 100.00% # Table walker pending requests distribution 546system.cpu0.itb.walker.walksPending::3 61000 0.00% 100.00% # Table walker pending requests distribution 547system.cpu0.itb.walker.walksPending::total 18106130328 # Table walker pending requests distribution 548system.cpu0.itb.walker.walkPageSizes::4K 2271 87.75% 87.75% # Table walker page sizes translated 549system.cpu0.itb.walker.walkPageSizes::1M 317 12.25% 100.00% # Table walker page sizes translated 550system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 551system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 552system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9874 # Table walker requests started/completed, data/inst 553system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9874 # Table walker requests started/completed, data/inst 554system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 555system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst 556system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 557system.cpu0.itb.walker.walkRequestOrigin::total 12462 # Table walker requests started/completed, data/inst 558system.cpu0.itb.inst_hits 35678798 # ITB inst hits 559system.cpu0.itb.inst_misses 9874 # ITB inst misses 560system.cpu0.itb.read_hits 0 # DTB read hits 561system.cpu0.itb.read_misses 0 # DTB read misses 562system.cpu0.itb.write_hits 0 # DTB write hits 563system.cpu0.itb.write_misses 0 # DTB write misses 564system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 565system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 566system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 567system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 568system.cpu0.itb.flush_entries 2368 # Number of entries that have been flushed from TLB 569system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 570system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 571system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 572system.cpu0.itb.perms_faults 1932 # Number of TLB faults due to permissions restrictions 573system.cpu0.itb.read_accesses 0 # DTB read accesses 574system.cpu0.itb.write_accesses 0 # DTB write accesses 575system.cpu0.itb.inst_accesses 35688672 # ITB inst accesses 576system.cpu0.itb.hits 35678798 # DTB hits 577system.cpu0.itb.misses 9874 # DTB misses 578system.cpu0.itb.accesses 35688672 # DTB accesses 579system.cpu0.numCycles 121733824 # number of cpu cycles simulated 580system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 581system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 582system.cpu0.fetch.icacheStallCycles 17621783 # Number of cycles fetch is stalled on an Icache miss 583system.cpu0.fetch.Insts 106366119 # Number of instructions fetch has processed 584system.cpu0.fetch.Branches 22612465 # Number of branches that fetch encountered 585system.cpu0.fetch.predictedBranches 13856831 # Number of branches that fetch has predicted taken 586system.cpu0.fetch.Cycles 98711813 # Number of cycles fetch has run and was not squashing or blocked 587system.cpu0.fetch.SquashCycles 2650530 # Number of cycles fetch has spent squashing 588system.cpu0.fetch.TlbCycles 130938 # Number of cycles fetch has spent waiting for tlb 589system.cpu0.fetch.MiscStallCycles 54154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 590system.cpu0.fetch.PendingTrapStallCycles 345087 # Number of stall cycles due to pending traps 591system.cpu0.fetch.PendingQuiesceStallCycles 416739 # Number of stall cycles due to pending quiesce instructions 592system.cpu0.fetch.IcacheWaitRetryStallCycles 73296 # Number of stall cycles due to full MSHR 593system.cpu0.fetch.CacheLines 35679429 # Number of cache lines fetched 594system.cpu0.fetch.IcacheSquashes 256075 # Number of outstanding Icache misses that were squashed 595system.cpu0.fetch.ItlbSquashes 4180 # Number of outstanding ITLB misses that were squashed 596system.cpu0.fetch.rateDist::samples 118679075 # Number of instructions fetched each cycle (Total) 597system.cpu0.fetch.rateDist::mean 1.081251 # Number of instructions fetched each cycle (Total) 598system.cpu0.fetch.rateDist::stdev 1.263308 # Number of instructions fetched each cycle (Total) 599system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 600system.cpu0.fetch.rateDist::0 59721044 50.32% 50.32% # Number of instructions fetched each cycle (Total) 601system.cpu0.fetch.rateDist::1 20146281 16.98% 67.30% # Number of instructions fetched each cycle (Total) 602system.cpu0.fetch.rateDist::2 8259650 6.96% 74.26% # Number of instructions fetched each cycle (Total) 603system.cpu0.fetch.rateDist::3 30552100 25.74% 100.00% # Number of instructions fetched each cycle (Total) 604system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 605system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 606system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 607system.cpu0.fetch.rateDist::total 118679075 # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.branchRate 0.185753 # Number of branch fetches per cycle 609system.cpu0.fetch.rate 0.873760 # Number of inst fetches per cycle 610system.cpu0.decode.IdleCycles 18470879 # Number of cycles decode is idle 611system.cpu0.decode.BlockedCycles 55646585 # Number of cycles decode is blocked 612system.cpu0.decode.RunCycles 38814384 # Number of cycles decode is running 613system.cpu0.decode.UnblockCycles 4744194 # Number of cycles decode is unblocking 614system.cpu0.decode.SquashCycles 1003033 # Number of cycles decode is squashing 615system.cpu0.decode.BranchResolved 2910392 # Number of times decode resolved a branch 616system.cpu0.decode.BranchMispred 326287 # Number of times decode detected a branch misprediction 617system.cpu0.decode.DecodedInsts 104430369 # Number of instructions handled by decode 618system.cpu0.decode.SquashedInsts 3709386 # Number of squashed instructions handled by decode 619system.cpu0.rename.SquashCycles 1003033 # Number of cycles rename is squashing 620system.cpu0.rename.IdleCycles 23916141 # Number of cycles rename is idle 621system.cpu0.rename.BlockCycles 11897059 # Number of cycles rename is blocking 622system.cpu0.rename.serializeStallCycles 33727750 # count of cycles rename stalled for serializing inst 623system.cpu0.rename.RunCycles 37986661 # Number of cycles rename is running 624system.cpu0.rename.UnblockCycles 10148431 # Number of cycles rename is unblocking 625system.cpu0.rename.RenamedInsts 99624170 # Number of instructions processed by rename 626system.cpu0.rename.SquashedInsts 979348 # Number of squashed instructions processed by rename 627system.cpu0.rename.ROBFullEvents 1380369 # Number of times rename has blocked due to ROB full 628system.cpu0.rename.IQFullEvents 148421 # Number of times rename has blocked due to IQ full 629system.cpu0.rename.LQFullEvents 51935 # Number of times rename has blocked due to LQ full 630system.cpu0.rename.SQFullEvents 6127142 # Number of times rename has blocked due to SQ full 631system.cpu0.rename.RenamedOperands 103189966 # Number of destination operands rename has renamed 632system.cpu0.rename.RenameLookups 455330287 # Number of register rename lookups that rename has made 633system.cpu0.rename.int_rename_lookups 114159594 # Number of integer rename lookups 634system.cpu0.rename.fp_rename_lookups 9381 # Number of floating rename lookups 635system.cpu0.rename.CommittedMaps 92428419 # Number of HB maps that are committed 636system.cpu0.rename.UndoneMaps 10761544 # Number of HB maps that are undone due to squashing 637system.cpu0.rename.serializingInsts 1188796 # count of serializing insts renamed 638system.cpu0.rename.tempSerializingInsts 1051388 # count of temporary serializing insts renamed 639system.cpu0.rename.skidInsts 11830283 # count of insts added to the skid buffer 640system.cpu0.memDep0.insertedLoads 17680232 # Number of loads inserted to the mem dependence unit. 641system.cpu0.memDep0.insertedStores 15386939 # Number of stores inserted to the mem dependence unit. 642system.cpu0.memDep0.conflictingLoads 1636462 # Number of conflicting loads. 643system.cpu0.memDep0.conflictingStores 2175060 # Number of conflicting stores. 644system.cpu0.iq.iqInstsAdded 96814528 # Number of instructions added to the IQ (excludes non-spec) 645system.cpu0.iq.iqNonSpecInstsAdded 1636038 # Number of non-speculative instructions added to the IQ 646system.cpu0.iq.iqInstsIssued 95024919 # Number of instructions issued 647system.cpu0.iq.iqSquashedInstsIssued 451413 # Number of squashed instructions issued 648system.cpu0.iq.iqSquashedInstsExamined 8911325 # Number of squashed instructions iterated over during squash; mainly for profiling 649system.cpu0.iq.iqSquashedOperandsExamined 20849804 # Number of squashed operands that are examined and possibly removed from graph 650system.cpu0.iq.iqSquashedNonSpecRemoved 116309 # Number of squashed non-spec instructions that were removed 651system.cpu0.iq.issued_per_cycle::samples 118679075 # Number of insts issued each cycle 652system.cpu0.iq.issued_per_cycle::mean 0.800688 # Number of insts issued each cycle 653system.cpu0.iq.issued_per_cycle::stdev 1.033122 # Number of insts issued each cycle 654system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 655system.cpu0.iq.issued_per_cycle::0 65546472 55.23% 55.23% # Number of insts issued each cycle 656system.cpu0.iq.issued_per_cycle::1 22156727 18.67% 73.90% # Number of insts issued each cycle 657system.cpu0.iq.issued_per_cycle::2 21116341 17.79% 91.69% # Number of insts issued each cycle 658system.cpu0.iq.issued_per_cycle::3 8802658 7.42% 99.11% # Number of insts issued each cycle 659system.cpu0.iq.issued_per_cycle::4 1056849 0.89% 100.00% # Number of insts issued each cycle 660system.cpu0.iq.issued_per_cycle::5 28 0.00% 100.00% # Number of insts issued each cycle 661system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 662system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 663system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 664system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 665system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::total 118679075 # Number of insts issued each cycle 668system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 669system.cpu0.iq.fu_full::IntAlu 8808229 40.49% 40.49% # attempts to use FU when none available 670system.cpu0.iq.fu_full::IntMult 130 0.00% 40.49% # attempts to use FU when none available 671system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.49% # attempts to use FU when none available 672system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.49% # attempts to use FU when none available 673system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.49% # attempts to use FU when none available 674system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.49% # attempts to use FU when none available 675system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.49% # attempts to use FU when none available 676system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.49% # attempts to use FU when none available 677system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.49% # attempts to use FU when none available 678system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.49% # attempts to use FU when none available 679system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.49% # attempts to use FU when none available 680system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.49% # attempts to use FU when none available 681system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.49% # attempts to use FU when none available 682system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.49% # attempts to use FU when none available 683system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.49% # attempts to use FU when none available 684system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.49% # attempts to use FU when none available 685system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.49% # attempts to use FU when none available 686system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.49% # attempts to use FU when none available 687system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.49% # attempts to use FU when none available 688system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.49% # attempts to use FU when none available 689system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.49% # attempts to use FU when none available 690system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.49% # attempts to use FU when none available 691system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.49% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.49% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.49% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.49% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.49% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.49% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.49% # attempts to use FU when none available 698system.cpu0.iq.fu_full::MemRead 5336848 24.53% 65.02% # attempts to use FU when none available 699system.cpu0.iq.fu_full::MemWrite 7610455 34.98% 100.00% # attempts to use FU when none available 700system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 701system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 702system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued 703system.cpu0.iq.FU_type_0::IntAlu 62565826 65.84% 65.84% # Type of FU issued 704system.cpu0.iq.FU_type_0::IntMult 87588 0.09% 65.94% # Type of FU issued 705system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.94% # Type of FU issued 706system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 65.94% # Type of FU issued 707system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.94% # Type of FU issued 708system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.94% # Type of FU issued 709system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.94% # Type of FU issued 710system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.94% # Type of FU issued 711system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.94% # Type of FU issued 712system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.94% # Type of FU issued 713system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.94% # Type of FU issued 714system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.94% # Type of FU issued 715system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.94% # Type of FU issued 716system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.94% # Type of FU issued 717system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.94% # Type of FU issued 718system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.94% # Type of FU issued 719system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.94% # Type of FU issued 720system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.94% # Type of FU issued 721system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.94% # Type of FU issued 722system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.94% # Type of FU issued 723system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.94% # Type of FU issued 724system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.94% # Type of FU issued 725system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.94% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.94% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 65.94% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdFloatMisc 7159 0.01% 65.94% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.94% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.94% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.94% # Type of FU issued 732system.cpu0.iq.FU_type_0::MemRead 17417081 18.33% 84.27% # Type of FU issued 733system.cpu0.iq.FU_type_0::MemWrite 14944992 15.73% 100.00% # Type of FU issued 734system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 735system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 736system.cpu0.iq.FU_type_0::total 95024919 # Type of FU issued 737system.cpu0.iq.rate 0.780596 # Inst issue rate 738system.cpu0.iq.fu_busy_cnt 21755662 # FU busy when requested 739system.cpu0.iq.fu_busy_rate 0.228947 # FU busy rate (busy events/executed inst) 740system.cpu0.iq.int_inst_queue_reads 330903688 # Number of integer instruction queue reads 741system.cpu0.iq.int_inst_queue_writes 107369307 # Number of integer instruction queue writes 742system.cpu0.iq.int_inst_queue_wakeup_accesses 93061278 # Number of integer instruction queue wakeup accesses 743system.cpu0.iq.fp_inst_queue_reads 32300 # Number of floating instruction queue reads 744system.cpu0.iq.fp_inst_queue_writes 11278 # Number of floating instruction queue writes 745system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses 746system.cpu0.iq.int_alu_accesses 116757282 # Number of integer alu accesses 747system.cpu0.iq.fp_alu_accesses 21027 # Number of floating point alu accesses 748system.cpu0.iew.lsq.thread0.forwLoads 347087 # Number of loads that had data forwarded from stores 749system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 750system.cpu0.iew.lsq.thread0.squashedLoads 1857425 # Number of loads squashed 751system.cpu0.iew.lsq.thread0.ignoredResponses 2513 # Number of memory responses ignored because the instruction is squashed 752system.cpu0.iew.lsq.thread0.memOrderViolation 18755 # Number of memory ordering violations 753system.cpu0.iew.lsq.thread0.squashedStores 953252 # Number of stores squashed 754system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 755system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 756system.cpu0.iew.lsq.thread0.rescheduledLoads 101364 # Number of loads that were rescheduled 757system.cpu0.iew.lsq.thread0.cacheBlocked 327888 # Number of times an access to memory failed due to the cache being blocked 758system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 759system.cpu0.iew.iewSquashCycles 1003033 # Number of cycles IEW is squashing 760system.cpu0.iew.iewBlockCycles 1539075 # Number of cycles IEW is blocking 761system.cpu0.iew.iewUnblockCycles 172884 # Number of cycles IEW is unblocking 762system.cpu0.iew.iewDispatchedInsts 98621711 # Number of instructions dispatched to IQ 763system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 764system.cpu0.iew.iewDispLoadInsts 17680232 # Number of dispatched load instructions 765system.cpu0.iew.iewDispStoreInsts 15386939 # Number of dispatched store instructions 766system.cpu0.iew.iewDispNonSpecInsts 849096 # Number of dispatched non-speculative instructions 767system.cpu0.iew.iewIQFullEvents 24467 # Number of times the IQ has become full, causing a stall 768system.cpu0.iew.iewLSQFullEvents 126834 # Number of times the LSQ has become full, causing a stall 769system.cpu0.iew.memOrderViolationEvents 18755 # Number of memory order violations 770system.cpu0.iew.predictedTakenIncorrect 265533 # Number of branches that were predicted taken incorrectly 771system.cpu0.iew.predictedNotTakenIncorrect 373430 # Number of branches that were predicted not taken incorrectly 772system.cpu0.iew.branchMispredicts 638963 # Number of branch mispredicts detected at execute 773system.cpu0.iew.iewExecutedInsts 94008948 # Number of executed instructions 774system.cpu0.iew.iewExecLoadInsts 16992930 # Number of load instructions executed 775system.cpu0.iew.iewExecSquashedInsts 954343 # Number of squashed instructions skipped in execute 776system.cpu0.iew.exec_swp 0 # number of swp insts executed 777system.cpu0.iew.exec_nop 171145 # number of nop insts executed 778system.cpu0.iew.exec_refs 31760151 # number of memory reference insts executed 779system.cpu0.iew.exec_branches 15805524 # Number of branches executed 780system.cpu0.iew.exec_stores 14767221 # Number of stores executed 781system.cpu0.iew.exec_rate 0.772250 # Inst execution rate 782system.cpu0.iew.wb_sent 93501427 # cumulative count of insts sent to commit 783system.cpu0.iew.wb_count 93071002 # cumulative count of insts written-back 784system.cpu0.iew.wb_producers 48393961 # num instructions producing a value 785system.cpu0.iew.wb_consumers 79995949 # num instructions consuming a value 786system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 787system.cpu0.iew.wb_rate 0.764545 # insts written-back per cycle 788system.cpu0.iew.wb_fanout 0.604955 # average fanout of values written-back 789system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 790system.cpu0.commit.commitSquashedInsts 7948634 # The number of squashed insts skipped by commit 791system.cpu0.commit.commitNonSpecStalls 1519729 # The number of times commit has been forced to stall to communicate backwards 792system.cpu0.commit.branchMispredicts 585621 # The number of times a branch was mispredicted 793system.cpu0.commit.committed_per_cycle::samples 117035605 # Number of insts commited each cycle 794system.cpu0.commit.committed_per_cycle::mean 0.766100 # Number of insts commited each cycle 795system.cpu0.commit.committed_per_cycle::stdev 1.480781 # Number of insts commited each cycle 796system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 797system.cpu0.commit.committed_per_cycle::0 75174289 64.23% 64.23% # Number of insts commited each cycle 798system.cpu0.commit.committed_per_cycle::1 23319780 19.93% 84.16% # Number of insts commited each cycle 799system.cpu0.commit.committed_per_cycle::2 7849886 6.71% 90.86% # Number of insts commited each cycle 800system.cpu0.commit.committed_per_cycle::3 3044520 2.60% 93.47% # Number of insts commited each cycle 801system.cpu0.commit.committed_per_cycle::4 3180912 2.72% 96.18% # Number of insts commited each cycle 802system.cpu0.commit.committed_per_cycle::5 1406827 1.20% 97.39% # Number of insts commited each cycle 803system.cpu0.commit.committed_per_cycle::6 1102407 0.94% 98.33% # Number of insts commited each cycle 804system.cpu0.commit.committed_per_cycle::7 520278 0.44% 98.77% # Number of insts commited each cycle 805system.cpu0.commit.committed_per_cycle::8 1436706 1.23% 100.00% # Number of insts commited each cycle 806system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 807system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::total 117035605 # Number of insts commited each cycle 810system.cpu0.commit.committedInsts 74499569 # Number of instructions committed 811system.cpu0.commit.committedOps 89660931 # Number of ops (including micro ops) committed 812system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 813system.cpu0.commit.refs 30256494 # Number of memory references committed 814system.cpu0.commit.loads 15822807 # Number of loads committed 815system.cpu0.commit.membars 627513 # Number of memory barriers committed 816system.cpu0.commit.branches 15208996 # Number of branches committed 817system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. 818system.cpu0.commit.int_insts 77458658 # Number of committed integer instructions. 819system.cpu0.commit.function_calls 1847857 # Number of function calls committed. 820system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 821system.cpu0.commit.op_class_0::IntAlu 59311896 66.15% 66.15% # Class of committed instruction 822system.cpu0.commit.op_class_0::IntMult 85382 0.10% 66.25% # Class of committed instruction 823system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction 824system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction 825system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction 826system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction 827system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction 828system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction 829system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction 830system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction 831system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction 832system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction 833system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction 834system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction 835system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction 836system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction 837system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction 838system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction 839system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction 840system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction 841system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction 842system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdFloatMisc 7159 0.01% 66.25% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction 850system.cpu0.commit.op_class_0::MemRead 15822807 17.65% 83.90% # Class of committed instruction 851system.cpu0.commit.op_class_0::MemWrite 14433687 16.10% 100.00% # Class of committed instruction 852system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 853system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 854system.cpu0.commit.op_class_0::total 89660931 # Class of committed instruction 855system.cpu0.commit.bw_lim_events 1436706 # number cycles where commit BW limit reached 856system.cpu0.rob.rob_reads 209187674 # The number of ROB reads 857system.cpu0.rob.rob_writes 196861250 # The number of ROB writes 858system.cpu0.timesIdled 121559 # Number of times that the entire CPU went into an idle state and unscheduled itself 859system.cpu0.idleCycles 3054749 # Total number of cycles that the CPU has spent unscheduled due to idling 860system.cpu0.quiesceCycles 5129022957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 861system.cpu0.committedInsts 74377875 # Number of Instructions Simulated 862system.cpu0.committedOps 89539237 # Number of Ops (including micro ops) Simulated 863system.cpu0.cpi 1.636694 # CPI: Cycles Per Instruction 864system.cpu0.cpi_total 1.636694 # CPI: Total CPI of All Threads 865system.cpu0.ipc 0.610988 # IPC: Instructions Per Cycle 866system.cpu0.ipc_total 0.610988 # IPC: Total IPC of All Threads 867system.cpu0.int_regfile_reads 104549028 # number of integer regfile reads 868system.cpu0.int_regfile_writes 56469550 # number of integer regfile writes 869system.cpu0.fp_regfile_reads 8161 # number of floating regfile reads 870system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 871system.cpu0.cc_regfile_reads 331224109 # number of cc regfile reads 872system.cpu0.cc_regfile_writes 38421528 # number of cc regfile writes 873system.cpu0.misc_regfile_reads 233358199 # number of misc regfile reads 874system.cpu0.misc_regfile_writes 1191250 # number of misc regfile writes 875system.cpu0.dcache.tags.replacements 674914 # number of replacements 876system.cpu0.dcache.tags.tagsinuse 486.328727 # Cycle average of tags in use 877system.cpu0.dcache.tags.total_refs 27281228 # Total number of references to valid blocks. 878system.cpu0.dcache.tags.sampled_refs 675426 # Sample count of references to valid blocks. 879system.cpu0.dcache.tags.avg_refs 40.391143 # Average number of references to valid blocks. 880system.cpu0.dcache.tags.warmup_cycle 277646000 # Cycle when the warmup percentage was hit. 881system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.328727 # Average occupied blocks per requestor 882system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949861 # Average percentage of cache occupancy 883system.cpu0.dcache.tags.occ_percent::total 0.949861 # Average percentage of cache occupancy 884system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 885system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 886system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id 887system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id 888system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 889system.cpu0.dcache.tags.tag_accesses 60112887 # Number of tag accesses 890system.cpu0.dcache.tags.data_accesses 60112887 # Number of data accesses 891system.cpu0.dcache.ReadReq_hits::cpu0.data 14700771 # number of ReadReq hits 892system.cpu0.dcache.ReadReq_hits::total 14700771 # number of ReadReq hits 893system.cpu0.dcache.WriteReq_hits::cpu0.data 11392924 # number of WriteReq hits 894system.cpu0.dcache.WriteReq_hits::total 11392924 # number of WriteReq hits 895system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295732 # number of SoftPFReq hits 896system.cpu0.dcache.SoftPFReq_hits::total 295732 # number of SoftPFReq hits 897system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354072 # number of LoadLockedReq hits 898system.cpu0.dcache.LoadLockedReq_hits::total 354072 # number of LoadLockedReq hits 899system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350987 # number of StoreCondReq hits 900system.cpu0.dcache.StoreCondReq_hits::total 350987 # number of StoreCondReq hits 901system.cpu0.dcache.demand_hits::cpu0.data 26093695 # number of demand (read+write) hits 902system.cpu0.dcache.demand_hits::total 26093695 # number of demand (read+write) hits 903system.cpu0.dcache.overall_hits::cpu0.data 26389427 # number of overall hits 904system.cpu0.dcache.overall_hits::total 26389427 # number of overall hits 905system.cpu0.dcache.ReadReq_misses::cpu0.data 607182 # number of ReadReq misses 906system.cpu0.dcache.ReadReq_misses::total 607182 # number of ReadReq misses 907system.cpu0.dcache.WriteReq_misses::cpu0.data 1803068 # number of WriteReq misses 908system.cpu0.dcache.WriteReq_misses::total 1803068 # number of WriteReq misses 909system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141599 # number of SoftPFReq misses 910system.cpu0.dcache.SoftPFReq_misses::total 141599 # number of SoftPFReq misses 911system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24346 # number of LoadLockedReq misses 912system.cpu0.dcache.LoadLockedReq_misses::total 24346 # number of LoadLockedReq misses 913system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21181 # number of StoreCondReq misses 914system.cpu0.dcache.StoreCondReq_misses::total 21181 # number of StoreCondReq misses 915system.cpu0.dcache.demand_misses::cpu0.data 2410250 # number of demand (read+write) misses 916system.cpu0.dcache.demand_misses::total 2410250 # number of demand (read+write) misses 917system.cpu0.dcache.overall_misses::cpu0.data 2551849 # number of overall misses 918system.cpu0.dcache.overall_misses::total 2551849 # number of overall misses 919system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8154354688 # number of ReadReq miss cycles 920system.cpu0.dcache.ReadReq_miss_latency::total 8154354688 # number of ReadReq miss cycles 921system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26135736531 # number of WriteReq miss cycles 922system.cpu0.dcache.WriteReq_miss_latency::total 26135736531 # number of WriteReq miss cycles 923system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 384171142 # number of LoadLockedReq miss cycles 924system.cpu0.dcache.LoadLockedReq_miss_latency::total 384171142 # number of LoadLockedReq miss cycles 925system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484170513 # number of StoreCondReq miss cycles 926system.cpu0.dcache.StoreCondReq_miss_latency::total 484170513 # number of StoreCondReq miss cycles 927system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 824000 # number of StoreCondFailReq miss cycles 928system.cpu0.dcache.StoreCondFailReq_miss_latency::total 824000 # number of StoreCondFailReq miss cycles 929system.cpu0.dcache.demand_miss_latency::cpu0.data 34290091219 # number of demand (read+write) miss cycles 930system.cpu0.dcache.demand_miss_latency::total 34290091219 # number of demand (read+write) miss cycles 931system.cpu0.dcache.overall_miss_latency::cpu0.data 34290091219 # number of overall miss cycles 932system.cpu0.dcache.overall_miss_latency::total 34290091219 # number of overall miss cycles 933system.cpu0.dcache.ReadReq_accesses::cpu0.data 15307953 # number of ReadReq accesses(hits+misses) 934system.cpu0.dcache.ReadReq_accesses::total 15307953 # number of ReadReq accesses(hits+misses) 935system.cpu0.dcache.WriteReq_accesses::cpu0.data 13195992 # number of WriteReq accesses(hits+misses) 936system.cpu0.dcache.WriteReq_accesses::total 13195992 # number of WriteReq accesses(hits+misses) 937system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437331 # number of SoftPFReq accesses(hits+misses) 938system.cpu0.dcache.SoftPFReq_accesses::total 437331 # number of SoftPFReq accesses(hits+misses) 939system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378418 # number of LoadLockedReq accesses(hits+misses) 940system.cpu0.dcache.LoadLockedReq_accesses::total 378418 # number of LoadLockedReq accesses(hits+misses) 941system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372168 # number of StoreCondReq accesses(hits+misses) 942system.cpu0.dcache.StoreCondReq_accesses::total 372168 # number of StoreCondReq accesses(hits+misses) 943system.cpu0.dcache.demand_accesses::cpu0.data 28503945 # number of demand (read+write) accesses 944system.cpu0.dcache.demand_accesses::total 28503945 # number of demand (read+write) accesses 945system.cpu0.dcache.overall_accesses::cpu0.data 28941276 # number of overall (read+write) accesses 946system.cpu0.dcache.overall_accesses::total 28941276 # number of overall (read+write) accesses 947system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039664 # miss rate for ReadReq accesses 948system.cpu0.dcache.ReadReq_miss_rate::total 0.039664 # miss rate for ReadReq accesses 949system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136638 # miss rate for WriteReq accesses 950system.cpu0.dcache.WriteReq_miss_rate::total 0.136638 # miss rate for WriteReq accesses 951system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323780 # miss rate for SoftPFReq accesses 952system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323780 # miss rate for SoftPFReq accesses 953system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064336 # miss rate for LoadLockedReq accesses 954system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064336 # miss rate for LoadLockedReq accesses 955system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056912 # miss rate for StoreCondReq accesses 956system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056912 # miss rate for StoreCondReq accesses 957system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084558 # miss rate for demand accesses 958system.cpu0.dcache.demand_miss_rate::total 0.084558 # miss rate for demand accesses 959system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088173 # miss rate for overall accesses 960system.cpu0.dcache.overall_miss_rate::total 0.088173 # miss rate for overall accesses 961system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13429.836010 # average ReadReq miss latency 962system.cpu0.dcache.ReadReq_avg_miss_latency::total 13429.836010 # average ReadReq miss latency 963system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14495.147455 # average WriteReq miss latency 964system.cpu0.dcache.WriteReq_avg_miss_latency::total 14495.147455 # average WriteReq miss latency 965system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15779.641091 # average LoadLockedReq miss latency 966system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15779.641091 # average LoadLockedReq miss latency 967system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22858.718332 # average StoreCondReq miss latency 968system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22858.718332 # average StoreCondReq miss latency 969system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 970system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 971system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811 # average overall miss latency 972system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811 # average overall miss latency 973system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199 # average overall miss latency 974system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199 # average overall miss latency 975system.cpu0.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked 976system.cpu0.dcache.blocked_cycles::no_targets 3670700 # number of cycles access was blocked 977system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked 978system.cpu0.dcache.blocked::no_targets 191761 # number of cycles access was blocked 979system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.162791 # average number of cycles each access was blocked 980system.cpu0.dcache.avg_blocked_cycles::no_targets 19.142057 # average number of cycles each access was blocked 981system.cpu0.dcache.fast_writes 0 # number of fast writes performed 982system.cpu0.dcache.cache_copies 0 # number of cache copies performed 983system.cpu0.dcache.writebacks::writebacks 492000 # number of writebacks 984system.cpu0.dcache.writebacks::total 492000 # number of writebacks 985system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239081 # number of ReadReq MSHR hits 986system.cpu0.dcache.ReadReq_mshr_hits::total 239081 # number of ReadReq MSHR hits 987system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1490741 # number of WriteReq MSHR hits 988system.cpu0.dcache.WriteReq_mshr_hits::total 1490741 # number of WriteReq MSHR hits 989system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18153 # number of LoadLockedReq MSHR hits 990system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18153 # number of LoadLockedReq MSHR hits 991system.cpu0.dcache.demand_mshr_hits::cpu0.data 1729822 # number of demand (read+write) MSHR hits 992system.cpu0.dcache.demand_mshr_hits::total 1729822 # number of demand (read+write) MSHR hits 993system.cpu0.dcache.overall_mshr_hits::cpu0.data 1729822 # number of overall MSHR hits 994system.cpu0.dcache.overall_mshr_hits::total 1729822 # number of overall MSHR hits 995system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368101 # number of ReadReq MSHR misses 996system.cpu0.dcache.ReadReq_mshr_misses::total 368101 # number of ReadReq MSHR misses 997system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312327 # number of WriteReq MSHR misses 998system.cpu0.dcache.WriteReq_mshr_misses::total 312327 # number of WriteReq MSHR misses 999system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98325 # number of SoftPFReq MSHR misses 1000system.cpu0.dcache.SoftPFReq_mshr_misses::total 98325 # number of SoftPFReq MSHR misses 1001system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses 1002system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6193 # number of LoadLockedReq MSHR misses 1003system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21181 # number of StoreCondReq MSHR misses 1004system.cpu0.dcache.StoreCondReq_mshr_misses::total 21181 # number of StoreCondReq MSHR misses 1005system.cpu0.dcache.demand_mshr_misses::cpu0.data 680428 # number of demand (read+write) MSHR misses 1006system.cpu0.dcache.demand_mshr_misses::total 680428 # number of demand (read+write) MSHR misses 1007system.cpu0.dcache.overall_mshr_misses::cpu0.data 778753 # number of overall MSHR misses 1008system.cpu0.dcache.overall_mshr_misses::total 778753 # number of overall MSHR misses 1009system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable 1010system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17965 # number of ReadReq MSHR uncacheable 1011system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable 1012system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable 1013system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses 1014system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34679 # number of overall MSHR uncacheable misses 1015system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4128121038 # number of ReadReq MSHR miss cycles 1016system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4128121038 # number of ReadReq MSHR miss cycles 1017system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5207818329 # number of WriteReq MSHR miss cycles 1018system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5207818329 # number of WriteReq MSHR miss cycles 1019system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570971031 # number of SoftPFReq MSHR miss cycles 1020system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570971031 # number of SoftPFReq MSHR miss cycles 1021system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91940502 # number of LoadLockedReq MSHR miss cycles 1022system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91940502 # number of LoadLockedReq MSHR miss cycles 1023system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 451443987 # number of StoreCondReq MSHR miss cycles 1024system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 451443987 # number of StoreCondReq MSHR miss cycles 1025system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 794000 # number of StoreCondFailReq MSHR miss cycles 1026system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 794000 # number of StoreCondFailReq MSHR miss cycles 1027system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335939367 # number of demand (read+write) MSHR miss cycles 1028system.cpu0.dcache.demand_mshr_miss_latency::total 9335939367 # number of demand (read+write) MSHR miss cycles 1029system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10906910398 # number of overall MSHR miss cycles 1030system.cpu0.dcache.overall_mshr_miss_latency::total 10906910398 # number of overall MSHR miss cycles 1031system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3693380750 # number of ReadReq MSHR uncacheable cycles 1032system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3693380750 # number of ReadReq MSHR uncacheable cycles 1033system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2688166013 # number of WriteReq MSHR uncacheable cycles 1034system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2688166013 # number of WriteReq MSHR uncacheable cycles 1035system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6381546763 # number of overall MSHR uncacheable cycles 1036system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6381546763 # number of overall MSHR uncacheable cycles 1037system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses 1038system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses 1039system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023668 # mshr miss rate for WriteReq accesses 1040system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023668 # mshr miss rate for WriteReq accesses 1041system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224830 # mshr miss rate for SoftPFReq accesses 1042system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224830 # mshr miss rate for SoftPFReq accesses 1043system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016366 # mshr miss rate for LoadLockedReq accesses 1044system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016366 # mshr miss rate for LoadLockedReq accesses 1045system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056912 # mshr miss rate for StoreCondReq accesses 1046system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056912 # mshr miss rate for StoreCondReq accesses 1047system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023871 # mshr miss rate for demand accesses 1048system.cpu0.dcache.demand_mshr_miss_rate::total 0.023871 # mshr miss rate for demand accesses 1049system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026908 # mshr miss rate for overall accesses 1050system.cpu0.dcache.overall_mshr_miss_rate::total 0.026908 # mshr miss rate for overall accesses 1051system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280 # average ReadReq mshr miss latency 1052system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280 # average ReadReq mshr miss latency 1053system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517 # average WriteReq mshr miss latency 1054system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517 # average WriteReq mshr miss latency 1055system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598 # average SoftPFReq mshr miss latency 1056system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598 # average SoftPFReq mshr miss latency 1057system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697 # average LoadLockedReq mshr miss latency 1058system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697 # average LoadLockedReq mshr miss latency 1059system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526 # average StoreCondReq mshr miss latency 1060system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526 # average StoreCondReq mshr miss latency 1061system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1062system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1063system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637 # average overall mshr miss latency 1064system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637 # average overall mshr miss latency 1065system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478 # average overall mshr miss latency 1066system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478 # average overall mshr miss latency 1067system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059 # average ReadReq mshr uncacheable latency 1068system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059 # average ReadReq mshr uncacheable latency 1069system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508 # average WriteReq mshr uncacheable latency 1070system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508 # average WriteReq mshr uncacheable latency 1071system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898 # average overall mshr uncacheable latency 1072system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898 # average overall mshr uncacheable latency 1073system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1074system.cpu0.icache.tags.replacements 1200530 # number of replacements 1075system.cpu0.icache.tags.tagsinuse 511.748320 # Cycle average of tags in use 1076system.cpu0.icache.tags.total_refs 34431245 # Total number of references to valid blocks. 1077system.cpu0.icache.tags.sampled_refs 1201042 # Sample count of references to valid blocks. 1078system.cpu0.icache.tags.avg_refs 28.667811 # Average number of references to valid blocks. 1079system.cpu0.icache.tags.warmup_cycle 6414143250 # Cycle when the warmup percentage was hit. 1080system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748320 # Average occupied blocks per requestor 1081system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy 1082system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy 1083system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1084system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 1085system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 1086system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id 1087system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1088system.cpu0.icache.tags.tag_accesses 72552920 # Number of tag accesses 1089system.cpu0.icache.tags.data_accesses 72552920 # Number of data accesses 1090system.cpu0.icache.ReadReq_hits::cpu0.inst 34431245 # number of ReadReq hits 1091system.cpu0.icache.ReadReq_hits::total 34431245 # number of ReadReq hits 1092system.cpu0.icache.demand_hits::cpu0.inst 34431245 # number of demand (read+write) hits 1093system.cpu0.icache.demand_hits::total 34431245 # number of demand (read+write) hits 1094system.cpu0.icache.overall_hits::cpu0.inst 34431245 # number of overall hits 1095system.cpu0.icache.overall_hits::total 34431245 # number of overall hits 1096system.cpu0.icache.ReadReq_misses::cpu0.inst 1244682 # number of ReadReq misses 1097system.cpu0.icache.ReadReq_misses::total 1244682 # number of ReadReq misses 1098system.cpu0.icache.demand_misses::cpu0.inst 1244682 # number of demand (read+write) misses 1099system.cpu0.icache.demand_misses::total 1244682 # number of demand (read+write) misses 1100system.cpu0.icache.overall_misses::cpu0.inst 1244682 # number of overall misses 1101system.cpu0.icache.overall_misses::total 1244682 # number of overall misses 1102system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12221339030 # number of ReadReq miss cycles 1103system.cpu0.icache.ReadReq_miss_latency::total 12221339030 # number of ReadReq miss cycles 1104system.cpu0.icache.demand_miss_latency::cpu0.inst 12221339030 # number of demand (read+write) miss cycles 1105system.cpu0.icache.demand_miss_latency::total 12221339030 # number of demand (read+write) miss cycles 1106system.cpu0.icache.overall_miss_latency::cpu0.inst 12221339030 # number of overall miss cycles 1107system.cpu0.icache.overall_miss_latency::total 12221339030 # number of overall miss cycles 1108system.cpu0.icache.ReadReq_accesses::cpu0.inst 35675927 # number of ReadReq accesses(hits+misses) 1109system.cpu0.icache.ReadReq_accesses::total 35675927 # number of ReadReq accesses(hits+misses) 1110system.cpu0.icache.demand_accesses::cpu0.inst 35675927 # number of demand (read+write) accesses 1111system.cpu0.icache.demand_accesses::total 35675927 # number of demand (read+write) accesses 1112system.cpu0.icache.overall_accesses::cpu0.inst 35675927 # number of overall (read+write) accesses 1113system.cpu0.icache.overall_accesses::total 35675927 # number of overall (read+write) accesses 1114system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034889 # miss rate for ReadReq accesses 1115system.cpu0.icache.ReadReq_miss_rate::total 0.034889 # miss rate for ReadReq accesses 1116system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034889 # miss rate for demand accesses 1117system.cpu0.icache.demand_miss_rate::total 0.034889 # miss rate for demand accesses 1118system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034889 # miss rate for overall accesses 1119system.cpu0.icache.overall_miss_rate::total 0.034889 # miss rate for overall accesses 1120system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9818.844516 # average ReadReq miss latency 1121system.cpu0.icache.ReadReq_avg_miss_latency::total 9818.844516 # average ReadReq miss latency 1122system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency 1123system.cpu0.icache.demand_avg_miss_latency::total 9818.844516 # average overall miss latency 1124system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency 1125system.cpu0.icache.overall_avg_miss_latency::total 9818.844516 # average overall miss latency 1126system.cpu0.icache.blocked_cycles::no_mshrs 1349229 # number of cycles access was blocked 1127system.cpu0.icache.blocked_cycles::no_targets 432 # number of cycles access was blocked 1128system.cpu0.icache.blocked::no_mshrs 105227 # number of cycles access was blocked 1129system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked 1130system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.822080 # average number of cycles each access was blocked 1131system.cpu0.icache.avg_blocked_cycles::no_targets 39.272727 # average number of cycles each access was blocked 1132system.cpu0.icache.fast_writes 0 # number of fast writes performed 1133system.cpu0.icache.cache_copies 0 # number of cache copies performed 1134system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43614 # number of ReadReq MSHR hits 1135system.cpu0.icache.ReadReq_mshr_hits::total 43614 # number of ReadReq MSHR hits 1136system.cpu0.icache.demand_mshr_hits::cpu0.inst 43614 # number of demand (read+write) MSHR hits 1137system.cpu0.icache.demand_mshr_hits::total 43614 # number of demand (read+write) MSHR hits 1138system.cpu0.icache.overall_mshr_hits::cpu0.inst 43614 # number of overall MSHR hits 1139system.cpu0.icache.overall_mshr_hits::total 43614 # number of overall MSHR hits 1140system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201068 # number of ReadReq MSHR misses 1141system.cpu0.icache.ReadReq_mshr_misses::total 1201068 # number of ReadReq MSHR misses 1142system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201068 # number of demand (read+write) MSHR misses 1143system.cpu0.icache.demand_mshr_misses::total 1201068 # number of demand (read+write) MSHR misses 1144system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201068 # number of overall MSHR misses 1145system.cpu0.icache.overall_mshr_misses::total 1201068 # number of overall MSHR misses 1146system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable 1147system.cpu0.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable 1148system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses 1149system.cpu0.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses 1150system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10504795288 # number of ReadReq MSHR miss cycles 1151system.cpu0.icache.ReadReq_mshr_miss_latency::total 10504795288 # number of ReadReq MSHR miss cycles 1152system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10504795288 # number of demand (read+write) MSHR miss cycles 1153system.cpu0.icache.demand_mshr_miss_latency::total 10504795288 # number of demand (read+write) MSHR miss cycles 1154system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10504795288 # number of overall MSHR miss cycles 1155system.cpu0.icache.overall_mshr_miss_latency::total 10504795288 # number of overall MSHR miss cycles 1156system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265434748 # number of ReadReq MSHR uncacheable cycles 1157system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles 1158system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles 1159system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles 1160system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for ReadReq accesses 1161system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033666 # mshr miss rate for ReadReq accesses 1162system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for demand accesses 1163system.cpu0.icache.demand_mshr_miss_rate::total 0.033666 # mshr miss rate for demand accesses 1164system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for overall accesses 1165system.cpu0.icache.overall_mshr_miss_rate::total 0.033666 # mshr miss rate for overall accesses 1166system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average ReadReq mshr miss latency 1167system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8746.211945 # average ReadReq mshr miss latency 1168system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency 1169system.cpu0.icache.demand_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency 1170system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency 1171system.cpu0.icache.overall_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency 1172system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average ReadReq mshr uncacheable latency 1173system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88419.303131 # average ReadReq mshr uncacheable latency 1174system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average overall mshr uncacheable latency 1175system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88419.303131 # average overall mshr uncacheable latency 1176system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1177system.cpu0.l2cache.prefetcher.num_hwpf_issued 1764126 # number of hwpf issued 1178system.cpu0.l2cache.prefetcher.pfIdentified 1768652 # number of prefetch candidates identified 1179system.cpu0.l2cache.prefetcher.pfBufferHit 4013 # number of redundant prefetches already in prefetch queue 1180system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1181system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1182system.cpu0.l2cache.prefetcher.pfSpanPage 220332 # number of prefetches not generated due to page crossing 1183system.cpu0.l2cache.tags.replacements 264213 # number of replacements 1184system.cpu0.l2cache.tags.tagsinuse 16022.712569 # Cycle average of tags in use 1185system.cpu0.l2cache.tags.total_refs 2093032 # Total number of references to valid blocks. 1186system.cpu0.l2cache.tags.sampled_refs 280442 # Sample count of references to valid blocks. 1187system.cpu0.l2cache.tags.avg_refs 7.463333 # Average number of references to valid blocks. 1188system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1189system.cpu0.l2cache.tags.occ_blocks::writebacks 9357.549400 # Average occupied blocks per requestor 1190system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.830885 # Average occupied blocks per requestor 1191system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.990255 # Average occupied blocks per requestor 1192system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3887.194071 # Average occupied blocks per requestor 1193system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1642.708300 # Average occupied blocks per requestor 1194system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1121.439658 # Average occupied blocks per requestor 1195system.cpu0.l2cache.tags.occ_percent::writebacks 0.571139 # Average percentage of cache occupancy 1196system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy 1197system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy 1198system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.237255 # Average percentage of cache occupancy 1199system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100263 # Average percentage of cache occupancy 1200system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068447 # Average percentage of cache occupancy 1201system.cpu0.l2cache.tags.occ_percent::total 0.977949 # Average percentage of cache occupancy 1202system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id 1203system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 1204system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15194 # Occupied blocks per task id 1205system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id 1206system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id 1207system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 426 # Occupied blocks per task id 1208system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id 1209system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1210system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1211system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 1212system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 450 # Occupied blocks per task id 1213system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7327 # Occupied blocks per task id 1215system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2684 # Occupied blocks per task id 1216system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id 1217system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 1218system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927368 # Percentage of cache occupancy per task id 1219system.cpu0.l2cache.tags.tag_accesses 41624222 # Number of tag accesses 1220system.cpu0.l2cache.tags.data_accesses 41624222 # Number of data accesses 1221system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49855 # number of ReadReq hits 1222system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11685 # number of ReadReq hits 1223system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1152127 # number of ReadReq hits 1224system.cpu0.l2cache.ReadReq_hits::cpu0.data 374018 # number of ReadReq hits 1225system.cpu0.l2cache.ReadReq_hits::total 1587685 # number of ReadReq hits 1226system.cpu0.l2cache.Writeback_hits::writebacks 491993 # number of Writeback hits 1227system.cpu0.l2cache.Writeback_hits::total 491993 # number of Writeback hits 1228system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28477 # number of UpgradeReq hits 1229system.cpu0.l2cache.UpgradeReq_hits::total 28477 # number of UpgradeReq hits 1230system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1602 # number of SCUpgradeReq hits 1231system.cpu0.l2cache.SCUpgradeReq_hits::total 1602 # number of SCUpgradeReq hits 1232system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210193 # number of ReadExReq hits 1233system.cpu0.l2cache.ReadExReq_hits::total 210193 # number of ReadExReq hits 1234system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49855 # number of demand (read+write) hits 1235system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11685 # number of demand (read+write) hits 1236system.cpu0.l2cache.demand_hits::cpu0.inst 1152127 # number of demand (read+write) hits 1237system.cpu0.l2cache.demand_hits::cpu0.data 584211 # number of demand (read+write) hits 1238system.cpu0.l2cache.demand_hits::total 1797878 # number of demand (read+write) hits 1239system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49855 # number of overall hits 1240system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11685 # number of overall hits 1241system.cpu0.l2cache.overall_hits::cpu0.inst 1152127 # number of overall hits 1242system.cpu0.l2cache.overall_hits::cpu0.data 584211 # number of overall hits 1243system.cpu0.l2cache.overall_hits::total 1797878 # number of overall hits 1244system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 397 # number of ReadReq misses 1245system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 143 # number of ReadReq misses 1246system.cpu0.l2cache.ReadReq_misses::cpu0.inst 48926 # number of ReadReq misses 1247system.cpu0.l2cache.ReadReq_misses::cpu0.data 98504 # number of ReadReq misses 1248system.cpu0.l2cache.ReadReq_misses::total 147970 # number of ReadReq misses 1249system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses 1250system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses 1251system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27483 # number of UpgradeReq misses 1252system.cpu0.l2cache.UpgradeReq_misses::total 27483 # number of UpgradeReq misses 1253system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19577 # number of SCUpgradeReq misses 1254system.cpu0.l2cache.SCUpgradeReq_misses::total 19577 # number of SCUpgradeReq misses 1255system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 1256system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1257system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46426 # number of ReadExReq misses 1258system.cpu0.l2cache.ReadExReq_misses::total 46426 # number of ReadExReq misses 1259system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 397 # number of demand (read+write) misses 1260system.cpu0.l2cache.demand_misses::cpu0.itb.walker 143 # number of demand (read+write) misses 1261system.cpu0.l2cache.demand_misses::cpu0.inst 48926 # number of demand (read+write) misses 1262system.cpu0.l2cache.demand_misses::cpu0.data 144930 # number of demand (read+write) misses 1263system.cpu0.l2cache.demand_misses::total 194396 # number of demand (read+write) misses 1264system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 397 # number of overall misses 1265system.cpu0.l2cache.overall_misses::cpu0.itb.walker 143 # number of overall misses 1266system.cpu0.l2cache.overall_misses::cpu0.inst 48926 # number of overall misses 1267system.cpu0.l2cache.overall_misses::cpu0.data 144930 # number of overall misses 1268system.cpu0.l2cache.overall_misses::total 194396 # number of overall misses 1269system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10907493 # number of ReadReq miss cycles 1270system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3478500 # number of ReadReq miss cycles 1271system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2401346947 # number of ReadReq miss cycles 1272system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2853426397 # number of ReadReq miss cycles 1273system.cpu0.l2cache.ReadReq_miss_latency::total 5269159337 # number of ReadReq miss cycles 1274system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 505786782 # number of UpgradeReq miss cycles 1275system.cpu0.l2cache.UpgradeReq_miss_latency::total 505786782 # number of UpgradeReq miss cycles 1276system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 394596383 # number of SCUpgradeReq miss cycles 1277system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 394596383 # number of SCUpgradeReq miss cycles 1278system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 773499 # number of SCUpgradeFailReq miss cycles 1279system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 773499 # number of SCUpgradeFailReq miss cycles 1280system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2617489063 # number of ReadExReq miss cycles 1281system.cpu0.l2cache.ReadExReq_miss_latency::total 2617489063 # number of ReadExReq miss cycles 1282system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10907493 # number of demand (read+write) miss cycles 1283system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3478500 # number of demand (read+write) miss cycles 1284system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2401346947 # number of demand (read+write) miss cycles 1285system.cpu0.l2cache.demand_miss_latency::cpu0.data 5470915460 # number of demand (read+write) miss cycles 1286system.cpu0.l2cache.demand_miss_latency::total 7886648400 # number of demand (read+write) miss cycles 1287system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10907493 # number of overall miss cycles 1288system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3478500 # number of overall miss cycles 1289system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2401346947 # number of overall miss cycles 1290system.cpu0.l2cache.overall_miss_latency::cpu0.data 5470915460 # number of overall miss cycles 1291system.cpu0.l2cache.overall_miss_latency::total 7886648400 # number of overall miss cycles 1292system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50252 # number of ReadReq accesses(hits+misses) 1293system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 11828 # number of ReadReq accesses(hits+misses) 1294system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1201053 # number of ReadReq accesses(hits+misses) 1295system.cpu0.l2cache.ReadReq_accesses::cpu0.data 472522 # number of ReadReq accesses(hits+misses) 1296system.cpu0.l2cache.ReadReq_accesses::total 1735655 # number of ReadReq accesses(hits+misses) 1297system.cpu0.l2cache.Writeback_accesses::writebacks 491995 # number of Writeback accesses(hits+misses) 1298system.cpu0.l2cache.Writeback_accesses::total 491995 # number of Writeback accesses(hits+misses) 1299system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55960 # number of UpgradeReq accesses(hits+misses) 1300system.cpu0.l2cache.UpgradeReq_accesses::total 55960 # number of UpgradeReq accesses(hits+misses) 1301system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21179 # number of SCUpgradeReq accesses(hits+misses) 1302system.cpu0.l2cache.SCUpgradeReq_accesses::total 21179 # number of SCUpgradeReq accesses(hits+misses) 1303system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1304system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1305system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256619 # number of ReadExReq accesses(hits+misses) 1306system.cpu0.l2cache.ReadExReq_accesses::total 256619 # number of ReadExReq accesses(hits+misses) 1307system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50252 # number of demand (read+write) accesses 1308system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 11828 # number of demand (read+write) accesses 1309system.cpu0.l2cache.demand_accesses::cpu0.inst 1201053 # number of demand (read+write) accesses 1310system.cpu0.l2cache.demand_accesses::cpu0.data 729141 # number of demand (read+write) accesses 1311system.cpu0.l2cache.demand_accesses::total 1992274 # number of demand (read+write) accesses 1312system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50252 # number of overall (read+write) accesses 1313system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 11828 # number of overall (read+write) accesses 1314system.cpu0.l2cache.overall_accesses::cpu0.inst 1201053 # number of overall (read+write) accesses 1315system.cpu0.l2cache.overall_accesses::cpu0.data 729141 # number of overall (read+write) accesses 1316system.cpu0.l2cache.overall_accesses::total 1992274 # number of overall (read+write) accesses 1317system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for ReadReq accesses 1318system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012090 # miss rate for ReadReq accesses 1319system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040736 # miss rate for ReadReq accesses 1320system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.208464 # miss rate for ReadReq accesses 1321system.cpu0.l2cache.ReadReq_miss_rate::total 0.085253 # miss rate for ReadReq accesses 1322system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses 1323system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses 1324system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.491119 # miss rate for UpgradeReq accesses 1325system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.491119 # miss rate for UpgradeReq accesses 1326system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924359 # miss rate for SCUpgradeReq accesses 1327system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924359 # miss rate for SCUpgradeReq accesses 1328system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1329system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1330system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180914 # miss rate for ReadExReq accesses 1331system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180914 # miss rate for ReadExReq accesses 1332system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for demand accesses 1333system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012090 # miss rate for demand accesses 1334system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040736 # miss rate for demand accesses 1335system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198768 # miss rate for demand accesses 1336system.cpu0.l2cache.demand_miss_rate::total 0.097575 # miss rate for demand accesses 1337system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for overall accesses 1338system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012090 # miss rate for overall accesses 1339system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040736 # miss rate for overall accesses 1340system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198768 # miss rate for overall accesses 1341system.cpu0.l2cache.overall_miss_rate::total 0.097575 # miss rate for overall accesses 1342system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average ReadReq miss latency 1343system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24325.174825 # average ReadReq miss latency 1344system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49081.203184 # average ReadReq miss latency 1345system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28967.619559 # average ReadReq miss latency 1346system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35609.646124 # average ReadReq miss latency 1347system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18403.623404 # average UpgradeReq miss latency 1348system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18403.623404 # average UpgradeReq miss latency 1349system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20156.121112 # average SCUpgradeReq miss latency 1350system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20156.121112 # average SCUpgradeReq miss latency 1351system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 386749.500000 # average SCUpgradeFailReq miss latency 1352system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 386749.500000 # average SCUpgradeFailReq miss latency 1353system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56379.810085 # average ReadExReq miss latency 1354system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56379.810085 # average ReadExReq miss latency 1355system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency 1356system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency 1357system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency 1358system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency 1359system.cpu0.l2cache.demand_avg_miss_latency::total 40570.013786 # average overall miss latency 1360system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency 1361system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency 1362system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency 1363system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency 1364system.cpu0.l2cache.overall_avg_miss_latency::total 40570.013786 # average overall miss latency 1365system.cpu0.l2cache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked 1366system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1367system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked 1368system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1369system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.428571 # average number of cycles each access was blocked 1370system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1371system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1372system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1373system.cpu0.l2cache.writebacks::writebacks 192333 # number of writebacks 1374system.cpu0.l2cache.writebacks::total 192333 # number of writebacks 1375system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1376system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1377system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits 1378system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 734 # number of ReadReq MSHR hits 1379system.cpu0.l2cache.ReadReq_mshr_hits::total 766 # number of ReadReq MSHR hits 1380system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5918 # number of ReadExReq MSHR hits 1381system.cpu0.l2cache.ReadExReq_mshr_hits::total 5918 # number of ReadExReq MSHR hits 1382system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1383system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1384system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits 1385system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6652 # number of demand (read+write) MSHR hits 1386system.cpu0.l2cache.demand_mshr_hits::total 6684 # number of demand (read+write) MSHR hits 1387system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1388system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1389system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits 1390system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6652 # number of overall MSHR hits 1391system.cpu0.l2cache.overall_mshr_hits::total 6684 # number of overall MSHR hits 1392system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 396 # number of ReadReq MSHR misses 1393system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 142 # number of ReadReq MSHR misses 1394system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 48896 # number of ReadReq MSHR misses 1395system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97770 # number of ReadReq MSHR misses 1396system.cpu0.l2cache.ReadReq_mshr_misses::total 147204 # number of ReadReq MSHR misses 1397system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses 1398system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses 1399system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of HardPFReq MSHR misses 1400system.cpu0.l2cache.HardPFReq_mshr_misses::total 231819 # number of HardPFReq MSHR misses 1401system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27483 # number of UpgradeReq MSHR misses 1402system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27483 # number of UpgradeReq MSHR misses 1403system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19577 # number of SCUpgradeReq MSHR misses 1404system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19577 # number of SCUpgradeReq MSHR misses 1405system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1406system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1407system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40508 # number of ReadExReq MSHR misses 1408system.cpu0.l2cache.ReadExReq_mshr_misses::total 40508 # number of ReadExReq MSHR misses 1409system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 396 # number of demand (read+write) MSHR misses 1410system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 142 # number of demand (read+write) MSHR misses 1411system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48896 # number of demand (read+write) MSHR misses 1412system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138278 # number of demand (read+write) MSHR misses 1413system.cpu0.l2cache.demand_mshr_misses::total 187712 # number of demand (read+write) MSHR misses 1414system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 396 # number of overall MSHR misses 1415system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 142 # number of overall MSHR misses 1416system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48896 # number of overall MSHR misses 1417system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138278 # number of overall MSHR misses 1418system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of overall MSHR misses 1419system.cpu0.l2cache.overall_mshr_misses::total 419531 # number of overall MSHR misses 1420system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable 1421system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable 1422system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20967 # number of ReadReq MSHR uncacheable 1423system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable 1424system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable 1425system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses 1426system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses 1427system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37681 # 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number of UpgradeReq MSHR miss cycles 1437system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292472580 # number of SCUpgradeReq MSHR miss cycles 1438system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292472580 # number of SCUpgradeReq MSHR miss cycles 1439system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 643499 # number of SCUpgradeFailReq MSHR miss cycles 1440system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 643499 # number of SCUpgradeFailReq MSHR miss cycles 1441system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1596975176 # number of ReadExReq MSHR miss cycles 1442system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1596975176 # number of ReadExReq MSHR miss cycles 1443system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of demand (read+write) MSHR miss cycles 1444system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2542000 # number of demand (read+write) MSHR miss cycles 1445system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2076482303 # number of demand (read+write) MSHR miss cycles 1446system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3772966126 # number of demand (read+write) MSHR miss cycles 1447system.cpu0.l2cache.demand_mshr_miss_latency::total 5860294928 # number of demand (read+write) MSHR miss cycles 1448system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of overall MSHR miss cycles 1449system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2542000 # number of overall MSHR miss cycles 1450system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2076482303 # number of overall MSHR miss cycles 1451system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3772966126 # number of overall MSHR miss cycles 1452system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of overall MSHR miss cycles 1453system.cpu0.l2cache.overall_mshr_miss_latency::total 20890949936 # number of overall MSHR miss cycles 1454system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 241524750 # number of ReadReq MSHR uncacheable cycles 1455system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3549350250 # number of ReadReq MSHR uncacheable cycles 1456system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3790875000 # number of ReadReq MSHR uncacheable cycles 1457system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2559965955 # number of WriteReq MSHR uncacheable cycles 1458system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2559965955 # number of WriteReq MSHR uncacheable cycles 1459system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles 1460system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6109316205 # number of overall MSHR uncacheable cycles 1461system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6350840955 # number of overall MSHR uncacheable cycles 1462system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for ReadReq accesses 1463system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for ReadReq accesses 1464system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for ReadReq accesses 1465system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.206911 # mshr miss rate for ReadReq accesses 1466system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.084812 # mshr miss rate for ReadReq accesses 1467system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses 1468system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses 1469system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1470system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1471system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.491119 # mshr miss rate for UpgradeReq accesses 1472system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.491119 # mshr miss rate for UpgradeReq accesses 1473system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924359 # mshr miss rate for SCUpgradeReq accesses 1474system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924359 # mshr miss rate for SCUpgradeReq accesses 1475system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1476system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1477system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157853 # mshr miss rate for ReadExReq accesses 1478system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157853 # mshr miss rate for ReadExReq accesses 1479system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for demand accesses 1480system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for demand accesses 1481system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for demand accesses 1482system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for demand accesses 1483system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094220 # mshr miss rate for demand accesses 1484system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for overall accesses 1485system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for overall accesses 1486system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for overall accesses 1487system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for overall accesses 1488system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1489system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210579 # mshr miss rate for overall accesses 1490system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average ReadReq mshr miss latency 1491system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average ReadReq mshr miss latency 1492system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average ReadReq mshr miss latency 1493system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279 # average ReadReq mshr miss latency 1494system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044 # average ReadReq mshr miss latency 1495system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average HardPFReq mshr miss latency 1496system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803 # average HardPFReq mshr miss latency 1497system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163 # average UpgradeReq mshr miss latency 1498system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163 # average UpgradeReq mshr miss latency 1499system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573 # average SCUpgradeReq mshr miss latency 1500system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573 # average SCUpgradeReq mshr miss latency 1501system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000 # average SCUpgradeFailReq mshr miss latency 1502system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000 # average SCUpgradeFailReq mshr miss latency 1503system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430 # average ReadExReq mshr miss latency 1504system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430 # average ReadExReq mshr miss latency 1505system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency 1506system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency 1507system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency 1508system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency 1509system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313 # average overall mshr miss latency 1510system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency 1511system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency 1512system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency 1513system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency 1514system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average overall mshr miss latency 1515system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482 # average overall mshr miss latency 1516system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average ReadReq mshr uncacheable latency 1517system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452 # average ReadReq mshr uncacheable latency 1518system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531 # average ReadReq mshr uncacheable latency 1519system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453 # average WriteReq mshr uncacheable latency 1520system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453 # average WriteReq mshr uncacheable latency 1521system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average overall mshr uncacheable latency 1522system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133 # average overall mshr uncacheable latency 1523system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485 # average overall mshr uncacheable latency 1524system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1525system.cpu0.toL2Bus.trans_dist::ReadReq 1907833 # Transaction distribution 1526system.cpu0.toL2Bus.trans_dist::ReadResp 1820754 # Transaction distribution 1527system.cpu0.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution 1528system.cpu0.toL2Bus.trans_dist::WriteResp 16714 # Transaction distribution 1529system.cpu0.toL2Bus.trans_dist::Writeback 491995 # Transaction distribution 1530system.cpu0.toL2Bus.trans_dist::HardPFReq 299768 # Transaction distribution 1531system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution 1532system.cpu0.toL2Bus.trans_dist::UpgradeReq 92116 # Transaction distribution 1533system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43624 # Transaction distribution 1534system.cpu0.toL2Bus.trans_dist::UpgradeResp 114864 # Transaction distribution 1535system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution 1536system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution 1537system.cpu0.toL2Bus.trans_dist::ReadExReq 284068 # Transaction distribution 1538system.cpu0.toL2Bus.trans_dist::ReadExResp 270286 # Transaction distribution 1539system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2408123 # Packet count per connected master and slave (bytes) 1540system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2274201 # Packet count per connected master and slave (bytes) 1541system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27655 # Packet count per connected master and slave (bytes) 1542system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 111764 # Packet count per connected master and slave (bytes) 1543system.cpu0.toL2Bus.pkt_count::total 4821743 # Packet count per connected master and slave (bytes) 1544system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76915296 # Cumulative packet size per connected master and slave (bytes) 1545system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82255660 # Cumulative packet size per connected master and slave (bytes) 1546system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 47312 # Cumulative packet size per connected master and slave (bytes) 1547system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 201008 # Cumulative packet size per connected master and slave (bytes) 1548system.cpu0.toL2Bus.pkt_size::total 159419276 # Cumulative packet size per connected master and slave (bytes) 1549system.cpu0.toL2Bus.snoops 687931 # Total snoops (count) 1550system.cpu0.toL2Bus.snoop_fanout::samples 3186793 # Request fanout histogram 1551system.cpu0.toL2Bus.snoop_fanout::mean 1.203876 # Request fanout histogram 1552system.cpu0.toL2Bus.snoop_fanout::stdev 0.402878 # Request fanout histogram 1553system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1554system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1555system.cpu0.toL2Bus.snoop_fanout::1 2537081 79.61% 79.61% # Request fanout histogram 1556system.cpu0.toL2Bus.snoop_fanout::2 649712 20.39% 100.00% # Request fanout histogram 1557system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1558system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1559system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1560system.cpu0.toL2Bus.snoop_fanout::total 3186793 # Request fanout histogram 1561system.cpu0.toL2Bus.reqLayer0.occupancy 1807599924 # Layer occupancy (ticks) 1562system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1563system.cpu0.toL2Bus.snoopLayer0.occupancy 112679999 # Layer occupancy (ticks) 1564system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1565system.cpu0.toL2Bus.respLayer0.occupancy 1808718407 # Layer occupancy (ticks) 1566system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1567system.cpu0.toL2Bus.respLayer1.occupancy 1166698241 # Layer occupancy (ticks) 1568system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1569system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # Layer occupancy (ticks) 1570system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1571system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks) 1572system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1573system.cpu1.branchPred.lookups 35319894 # Number of BP lookups 1574system.cpu1.branchPred.condPredicted 12619407 # Number of conditional branches predicted 1575system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect 1576system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups 1577system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits 1578system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1579system.cpu1.branchPred.BTBHitPct 79.617709 # BTB Hit Percentage 1580system.cpu1.branchPred.usedRAS 12648833 # Number of times the RAS was used to get a target. 1581system.cpu1.branchPred.RASInCorrect 10709 # Number of incorrect RAS predictions. 1582system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1583system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1584system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1585system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1586system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1587system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1588system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1589system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1590system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1591system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1592system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1593system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1594system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1595system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1596system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1597system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1598system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1599system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1600system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1601system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1602system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1603system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1604system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1605system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1606system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1607system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1608system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1609system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1610system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1611system.cpu1.dtb.walker.walks 24259 # Table walker walks requested 1612system.cpu1.dtb.walker.walksShort 24259 # Table walker walks initiated with short descriptors 1613system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11332 # Level at which table walker walks with short descriptors terminate 1614system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6025 # Level at which table walker walks with short descriptors terminate 1615system.cpu1.dtb.walker.walksSquashedBefore 6902 # Table walks squashed before starting 1616system.cpu1.dtb.walker.walkWaitTime::samples 17357 # Table walker wait (enqueue to first request) latency 1617system.cpu1.dtb.walker.walkWaitTime::mean 400.040330 # Table walker wait (enqueue to first request) latency 1618system.cpu1.dtb.walker.walkWaitTime::stdev 2564.899375 # Table walker wait (enqueue to first request) latency 1619system.cpu1.dtb.walker.walkWaitTime::0-4095 16829 96.96% 96.96% # Table walker wait (enqueue to first request) latency 1620system.cpu1.dtb.walker.walkWaitTime::4096-8191 181 1.04% 98.00% # Table walker wait (enqueue to first request) latency 1621system.cpu1.dtb.walker.walkWaitTime::8192-12287 173 1.00% 99.00% # Table walker wait (enqueue to first request) latency 1622system.cpu1.dtb.walker.walkWaitTime::12288-16383 71 0.41% 99.41% # Table walker wait (enqueue to first request) latency 1623system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.16% 99.57% # Table walker wait (enqueue to first request) latency 1624system.cpu1.dtb.walker.walkWaitTime::20480-24575 5 0.03% 99.60% # Table walker wait (enqueue to first request) latency 1625system.cpu1.dtb.walker.walkWaitTime::24576-28671 45 0.26% 99.86% # Table walker wait (enqueue to first request) latency 1626system.cpu1.dtb.walker.walkWaitTime::28672-32767 6 0.03% 99.89% # Table walker wait (enqueue to first request) latency 1627system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.97% # Table walker wait (enqueue to first request) latency 1628system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1629system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1630system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1631system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1632system.cpu1.dtb.walker.walkWaitTime::total 17357 # Table walker wait (enqueue to first request) latency 1633system.cpu1.dtb.walker.walkCompletionTime::samples 5295 # Table walker service (enqueue to completion) latency 1634system.cpu1.dtb.walker.walkCompletionTime::mean 9383.568650 # Table walker service (enqueue to completion) latency 1635system.cpu1.dtb.walker.walkCompletionTime::gmean 7860.112601 # Table walker service (enqueue to completion) latency 1636system.cpu1.dtb.walker.walkCompletionTime::stdev 8293.617199 # Table walker service (enqueue to completion) latency 1637system.cpu1.dtb.walker.walkCompletionTime::0-32767 5259 99.32% 99.32% # Table walker service (enqueue to completion) latency 1638system.cpu1.dtb.walker.walkCompletionTime::32768-65535 29 0.55% 99.87% # Table walker service (enqueue to completion) latency 1639system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.06% 99.92% # Table walker service (enqueue to completion) latency 1640system.cpu1.dtb.walker.walkCompletionTime::163840-196607 3 0.06% 99.98% # Table walker service (enqueue to completion) latency 1641system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1642system.cpu1.dtb.walker.walkCompletionTime::total 5295 # Table walker service (enqueue to completion) latency 1643system.cpu1.dtb.walker.walksPending::samples 69596834880 # Table walker pending requests distribution 1644system.cpu1.dtb.walker.walksPending::mean 0.389063 # Table walker pending requests distribution 1645system.cpu1.dtb.walker.walksPending::stdev 0.490087 # Table walker pending requests distribution 1646system.cpu1.dtb.walker.walksPending::0 42554298056 61.14% 61.14% # Table walker pending requests distribution 1647system.cpu1.dtb.walker.walksPending::1 27024786824 38.83% 99.97% # Table walker pending requests distribution 1648system.cpu1.dtb.walker.walksPending::2 11219000 0.02% 99.99% # Table walker pending requests distribution 1649system.cpu1.dtb.walker.walksPending::3 3252000 0.00% 100.00% # Table walker pending requests distribution 1650system.cpu1.dtb.walker.walksPending::4 913000 0.00% 100.00% # Table walker pending requests distribution 1651system.cpu1.dtb.walker.walksPending::5 701500 0.00% 100.00% # Table walker pending requests distribution 1652system.cpu1.dtb.walker.walksPending::6 719000 0.00% 100.00% # Table walker pending requests distribution 1653system.cpu1.dtb.walker.walksPending::7 299000 0.00% 100.00% # Table walker pending requests distribution 1654system.cpu1.dtb.walker.walksPending::8 99500 0.00% 100.00% # Table walker pending requests distribution 1655system.cpu1.dtb.walker.walksPending::9 182000 0.00% 100.00% # Table walker pending requests distribution 1656system.cpu1.dtb.walker.walksPending::10 50000 0.00% 100.00% # Table walker pending requests distribution 1657system.cpu1.dtb.walker.walksPending::11 63500 0.00% 100.00% # Table walker pending requests distribution 1658system.cpu1.dtb.walker.walksPending::12 106500 0.00% 100.00% # Table walker pending requests distribution 1659system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution 1660system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution 1661system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution 1662system.cpu1.dtb.walker.walksPending::total 69596834880 # Table walker pending requests distribution 1663system.cpu1.dtb.walker.walkPageSizes::4K 1939 74.63% 74.63% # Table walker page sizes translated 1664system.cpu1.dtb.walker.walkPageSizes::1M 659 25.37% 100.00% # Table walker page sizes translated 1665system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated 1666system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24259 # Table walker requests started/completed, data/inst 1667system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1668system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24259 # Table walker requests started/completed, data/inst 1669system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst 1670system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1671system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst 1672system.cpu1.dtb.walker.walkRequestOrigin::total 26857 # Table walker requests started/completed, data/inst 1673system.cpu1.dtb.inst_hits 0 # ITB inst hits 1674system.cpu1.dtb.inst_misses 0 # ITB inst misses 1675system.cpu1.dtb.read_hits 11166498 # DTB read hits 1676system.cpu1.dtb.read_misses 21069 # DTB read misses 1677system.cpu1.dtb.write_hits 7306223 # DTB write hits 1678system.cpu1.dtb.write_misses 3190 # DTB write misses 1679system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1680system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1681system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1682system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1683system.cpu1.dtb.flush_entries 2022 # Number of entries that have been flushed from TLB 1684system.cpu1.dtb.align_faults 70 # Number of TLB faults due to alignment restrictions 1685system.cpu1.dtb.prefetch_faults 623 # Number of TLB faults due to prefetch 1686system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1687system.cpu1.dtb.perms_faults 374 # Number of TLB faults due to permissions restrictions 1688system.cpu1.dtb.read_accesses 11187567 # DTB read accesses 1689system.cpu1.dtb.write_accesses 7309413 # DTB write accesses 1690system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1691system.cpu1.dtb.hits 18472721 # DTB hits 1692system.cpu1.dtb.misses 24259 # DTB misses 1693system.cpu1.dtb.accesses 18496980 # DTB accesses 1694system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1695system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1696system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1697system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1698system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1699system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1700system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1701system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1702system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1703system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1704system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1705system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1706system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1707system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1708system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1709system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1710system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1711system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1712system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1713system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1714system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1715system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1716system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1717system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1718system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1719system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1720system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1721system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1722system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1723system.cpu1.itb.walker.walks 6817 # Table walker walks requested 1724system.cpu1.itb.walker.walksShort 6817 # Table walker walks initiated with short descriptors 1725system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4075 # Level at which table walker walks with short descriptors terminate 1726system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2679 # Level at which table walker walks with short descriptors terminate 1727system.cpu1.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting 1728system.cpu1.itb.walker.walkWaitTime::samples 6754 # Table walker wait (enqueue to first request) latency 1729system.cpu1.itb.walker.walkWaitTime::mean 138.510512 # Table walker wait (enqueue to first request) latency 1730system.cpu1.itb.walker.walkWaitTime::stdev 1194.021921 # Table walker wait (enqueue to first request) latency 1731system.cpu1.itb.walker.walkWaitTime::0-2047 6631 98.18% 98.18% # Table walker wait (enqueue to first request) latency 1732system.cpu1.itb.walker.walkWaitTime::2048-4095 35 0.52% 98.70% # Table walker wait (enqueue to first request) latency 1733system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 99.11% # Table walker wait (enqueue to first request) latency 1734system.cpu1.itb.walker.walkWaitTime::6144-8191 28 0.41% 99.53% # Table walker wait (enqueue to first request) latency 1735system.cpu1.itb.walker.walkWaitTime::8192-10239 11 0.16% 99.69% # Table walker wait (enqueue to first request) latency 1736system.cpu1.itb.walker.walkWaitTime::10240-12287 8 0.12% 99.81% # Table walker wait (enqueue to first request) latency 1737system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.87% # Table walker wait (enqueue to first request) latency 1738system.cpu1.itb.walker.walkWaitTime::14336-16383 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency 1739system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency 1740system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency 1741system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency 1742system.cpu1.itb.walker.walkWaitTime::26624-28671 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1743system.cpu1.itb.walker.walkWaitTime::total 6754 # Table walker wait (enqueue to first request) latency 1744system.cpu1.itb.walker.walkCompletionTime::samples 1229 # Table walker service (enqueue to completion) latency 1745system.cpu1.itb.walker.walkCompletionTime::mean 9949.958503 # Table walker service (enqueue to completion) latency 1746system.cpu1.itb.walker.walkCompletionTime::gmean 8666.714001 # Table walker service (enqueue to completion) latency 1747system.cpu1.itb.walker.walkCompletionTime::stdev 5833.930601 # Table walker service (enqueue to completion) latency 1748system.cpu1.itb.walker.walkCompletionTime::0-4095 208 16.92% 16.92% # Table walker service (enqueue to completion) latency 1749system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.24% 31.16% # Table walker service (enqueue to completion) latency 1750system.cpu1.itb.walker.walkCompletionTime::8192-12287 520 42.31% 73.47% # Table walker service (enqueue to completion) latency 1751system.cpu1.itb.walker.walkCompletionTime::12288-16383 258 20.99% 94.47% # Table walker service (enqueue to completion) latency 1752system.cpu1.itb.walker.walkCompletionTime::16384-20479 10 0.81% 95.28% # Table walker service (enqueue to completion) latency 1753system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.24% 95.52% # Table walker service (enqueue to completion) latency 1754system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.44% 97.97% # Table walker service (enqueue to completion) latency 1755system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.30% 99.27% # Table walker service (enqueue to completion) latency 1756system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.16% 99.43% # Table walker service (enqueue to completion) latency 1757system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.41% 99.84% # Table walker service (enqueue to completion) latency 1758system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency 1759system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency 1760system.cpu1.itb.walker.walkCompletionTime::total 1229 # Table walker service (enqueue to completion) latency 1761system.cpu1.itb.walker.walksPending::samples 18026373328 # Table walker pending requests distribution 1762system.cpu1.itb.walker.walksPending::mean 0.989122 # Table walker pending requests distribution 1763system.cpu1.itb.walker.walksPending::stdev 0.103762 # Table walker pending requests distribution 1764system.cpu1.itb.walker.walksPending::0 196149764 1.09% 1.09% # Table walker pending requests distribution 1765system.cpu1.itb.walker.walksPending::1 17830158064 98.91% 100.00% # Table walker pending requests distribution 1766system.cpu1.itb.walker.walksPending::2 65500 0.00% 100.00% # Table walker pending requests distribution 1767system.cpu1.itb.walker.walksPending::total 18026373328 # Table walker pending requests distribution 1768system.cpu1.itb.walker.walkPageSizes::4K 995 85.33% 85.33% # Table walker page sizes translated 1769system.cpu1.itb.walker.walkPageSizes::1M 171 14.67% 100.00% # Table walker page sizes translated 1770system.cpu1.itb.walker.walkPageSizes::total 1166 # Table walker page sizes translated 1771system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1772system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6817 # Table walker requests started/completed, data/inst 1773system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6817 # Table walker requests started/completed, data/inst 1774system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1775system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1166 # Table walker requests started/completed, data/inst 1776system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1166 # Table walker requests started/completed, data/inst 1777system.cpu1.itb.walker.walkRequestOrigin::total 7983 # Table walker requests started/completed, data/inst 1778system.cpu1.itb.inst_hits 45723303 # ITB inst hits 1779system.cpu1.itb.inst_misses 6817 # ITB inst misses 1780system.cpu1.itb.read_hits 0 # DTB read hits 1781system.cpu1.itb.read_misses 0 # DTB read misses 1782system.cpu1.itb.write_hits 0 # DTB write hits 1783system.cpu1.itb.write_misses 0 # DTB write misses 1784system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1785system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1786system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1787system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1788system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB 1789system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1790system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1791system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1792system.cpu1.itb.perms_faults 537 # Number of TLB faults due to permissions restrictions 1793system.cpu1.itb.read_accesses 0 # DTB read accesses 1794system.cpu1.itb.write_accesses 0 # DTB write accesses 1795system.cpu1.itb.inst_accesses 45730120 # ITB inst accesses 1796system.cpu1.itb.hits 45723303 # DTB hits 1797system.cpu1.itb.misses 6817 # DTB misses 1798system.cpu1.itb.accesses 45730120 # DTB accesses 1799system.cpu1.numCycles 113567718 # number of cpu cycles simulated 1800system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1801system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1802system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss 1803system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed 1804system.cpu1.fetch.Branches 35319894 # Number of branches that fetch encountered 1805system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken 1806system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked 1807system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing 1808system.cpu1.fetch.TlbCycles 84431 # Number of cycles fetch has spent waiting for tlb 1809system.cpu1.fetch.MiscStallCycles 39920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1810system.cpu1.fetch.PendingTrapStallCycles 219438 # Number of stall cycles due to pending traps 1811system.cpu1.fetch.PendingQuiesceStallCycles 325443 # Number of stall cycles due to pending quiesce instructions 1812system.cpu1.fetch.IcacheWaitRetryStallCycles 27387 # Number of stall cycles due to full MSHR 1813system.cpu1.fetch.CacheLines 45722696 # Number of cache lines fetched 1814system.cpu1.fetch.IcacheSquashes 133886 # Number of outstanding Icache misses that were squashed 1815system.cpu1.fetch.ItlbSquashes 2307 # Number of outstanding ITLB misses that were squashed 1816system.cpu1.fetch.rateDist::samples 112589057 # Number of instructions fetched each cycle (Total) 1817system.cpu1.fetch.rateDist::mean 1.268755 # Number of instructions fetched each cycle (Total) 1818system.cpu1.fetch.rateDist::stdev 1.334526 # Number of instructions fetched each cycle (Total) 1819system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1820system.cpu1.fetch.rateDist::0 52059388 46.24% 46.24% # Number of instructions fetched each cycle (Total) 1821system.cpu1.fetch.rateDist::1 15346880 13.63% 59.87% # Number of instructions fetched each cycle (Total) 1822system.cpu1.fetch.rateDist::2 8047278 7.15% 67.02% # Number of instructions fetched each cycle (Total) 1823system.cpu1.fetch.rateDist::3 37135511 32.98% 100.00% # Number of instructions fetched each cycle (Total) 1824system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1825system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1826system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1827system.cpu1.fetch.rateDist::total 112589057 # Number of instructions fetched each cycle (Total) 1828system.cpu1.fetch.branchRate 0.311003 # Number of branch fetches per cycle 1829system.cpu1.fetch.rate 1.016533 # Number of inst fetches per cycle 1830system.cpu1.decode.IdleCycles 14201102 # Number of cycles decode is idle 1831system.cpu1.decode.BlockedCycles 65884249 # Number of cycles decode is blocked 1832system.cpu1.decode.RunCycles 29361473 # Number of cycles decode is running 1833system.cpu1.decode.UnblockCycles 1323272 # Number of cycles decode is unblocking 1834system.cpu1.decode.SquashCycles 1818961 # Number of cycles decode is squashing 1835system.cpu1.decode.BranchResolved 906595 # Number of times decode resolved a branch 1836system.cpu1.decode.BranchMispred 159892 # Number of times decode detected a branch misprediction 1837system.cpu1.decode.DecodedInsts 74422628 # Number of instructions handled by decode 1838system.cpu1.decode.SquashedInsts 1448245 # Number of squashed instructions handled by decode 1839system.cpu1.rename.SquashCycles 1818961 # Number of cycles rename is squashing 1840system.cpu1.rename.IdleCycles 18946447 # Number of cycles rename is idle 1841system.cpu1.rename.BlockCycles 2582249 # Number of cycles rename is blocking 1842system.cpu1.rename.serializeStallCycles 60294532 # count of cycles rename stalled for serializing inst 1843system.cpu1.rename.RunCycles 25904145 # Number of cycles rename is running 1844system.cpu1.rename.UnblockCycles 3042723 # Number of cycles rename is unblocking 1845system.cpu1.rename.RenamedInsts 61245605 # Number of instructions processed by rename 1846system.cpu1.rename.SquashedInsts 312742 # Number of squashed instructions processed by rename 1847system.cpu1.rename.ROBFullEvents 326990 # Number of times rename has blocked due to ROB full 1848system.cpu1.rename.IQFullEvents 51393 # Number of times rename has blocked due to IQ full 1849system.cpu1.rename.LQFullEvents 18938 # Number of times rename has blocked due to LQ full 1850system.cpu1.rename.SQFullEvents 1837973 # Number of times rename has blocked due to SQ full 1851system.cpu1.rename.RenamedOperands 61569183 # Number of destination operands rename has renamed 1852system.cpu1.rename.RenameLookups 287884146 # Number of register rename lookups that rename has made 1853system.cpu1.rename.int_rename_lookups 65513638 # Number of integer rename lookups 1854system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups 1855system.cpu1.rename.CommittedMaps 58022651 # Number of HB maps that are committed 1856system.cpu1.rename.UndoneMaps 3546532 # Number of HB maps that are undone due to squashing 1857system.cpu1.rename.serializingInsts 1914472 # count of serializing insts renamed 1858system.cpu1.rename.tempSerializingInsts 1838523 # count of temporary serializing insts renamed 1859system.cpu1.rename.skidInsts 13613893 # count of insts added to the skid buffer 1860system.cpu1.memDep0.insertedLoads 11512865 # Number of loads inserted to the mem dependence unit. 1861system.cpu1.memDep0.insertedStores 7756589 # Number of stores inserted to the mem dependence unit. 1862system.cpu1.memDep0.conflictingLoads 697877 # Number of conflicting loads. 1863system.cpu1.memDep0.conflictingStores 945772 # Number of conflicting stores. 1864system.cpu1.iq.iqInstsAdded 60208856 # Number of instructions added to the IQ (excludes non-spec) 1865system.cpu1.iq.iqNonSpecInstsAdded 646860 # Number of non-speculative instructions added to the IQ 1866system.cpu1.iq.iqInstsIssued 59677362 # Number of instructions issued 1867system.cpu1.iq.iqSquashedInstsIssued 148586 # Number of squashed instructions issued 1868system.cpu1.iq.iqSquashedInstsExamined 4522679 # Number of squashed instructions iterated over during squash; mainly for profiling 1869system.cpu1.iq.iqSquashedOperandsExamined 7282133 # Number of squashed operands that are examined and possibly removed from graph 1870system.cpu1.iq.iqSquashedNonSpecRemoved 53722 # Number of squashed non-spec instructions that were removed 1871system.cpu1.iq.issued_per_cycle::samples 112589057 # Number of insts issued each cycle 1872system.cpu1.iq.issued_per_cycle::mean 0.530046 # Number of insts issued each cycle 1873system.cpu1.iq.issued_per_cycle::stdev 0.866401 # Number of insts issued each cycle 1874system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1875system.cpu1.iq.issued_per_cycle::0 76211299 67.69% 67.69% # Number of insts issued each cycle 1876system.cpu1.iq.issued_per_cycle::1 17665370 15.69% 83.38% # Number of insts issued each cycle 1877system.cpu1.iq.issued_per_cycle::2 14473056 12.85% 96.23% # Number of insts issued each cycle 1878system.cpu1.iq.issued_per_cycle::3 3891466 3.46% 99.69% # Number of insts issued each cycle 1879system.cpu1.iq.issued_per_cycle::4 347848 0.31% 100.00% # Number of insts issued each cycle 1880system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle 1881system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1882system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1883system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1884system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1885system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1886system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1887system.cpu1.iq.issued_per_cycle::total 112589057 # Number of insts issued each cycle 1888system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1889system.cpu1.iq.fu_full::IntAlu 3478019 44.85% 44.85% # attempts to use FU when none available 1890system.cpu1.iq.fu_full::IntMult 614 0.01% 44.86% # attempts to use FU when none available 1891system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.86% # attempts to use FU when none available 1892system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.86% # attempts to use FU when none available 1893system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.86% # attempts to use FU when none available 1894system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.86% # attempts to use FU when none available 1895system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.86% # attempts to use FU when none available 1896system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.86% # attempts to use FU when none available 1897system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.86% # attempts to use FU when none available 1898system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.86% # attempts to use FU when none available 1899system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.86% # attempts to use FU when none available 1900system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.86% # attempts to use FU when none available 1901system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.86% # attempts to use FU when none available 1902system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.86% # attempts to use FU when none available 1903system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.86% # attempts to use FU when none available 1904system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.86% # attempts to use FU when none available 1905system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.86% # attempts to use FU when none available 1906system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.86% # attempts to use FU when none available 1907system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.86% # attempts to use FU when none available 1908system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.86% # attempts to use FU when none available 1909system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.86% # attempts to use FU when none available 1910system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.86% # attempts to use FU when none available 1911system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.86% # attempts to use FU when none available 1912system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.86% # attempts to use FU when none available 1913system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.86% # attempts to use FU when none available 1914system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.86% # attempts to use FU when none available 1915system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.86% # attempts to use FU when none available 1916system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.86% # attempts to use FU when none available 1917system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.86% # attempts to use FU when none available 1918system.cpu1.iq.fu_full::MemRead 1940620 25.03% 69.89% # attempts to use FU when none available 1919system.cpu1.iq.fu_full::MemWrite 2334930 30.11% 100.00% # attempts to use FU when none available 1920system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1921system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1922system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued 1923system.cpu1.iq.FU_type_0::IntAlu 40635841 68.09% 68.09% # Type of FU issued 1924system.cpu1.iq.FU_type_0::IntMult 52797 0.09% 68.18% # Type of FU issued 1925system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued 1926system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued 1927system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.18% # Type of FU issued 1928system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued 1929system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued 1930system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued 1931system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.18% # Type of FU issued 1932system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.18% # Type of FU issued 1933system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.18% # Type of FU issued 1934system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.18% # Type of FU issued 1935system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.18% # Type of FU issued 1936system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.18% # Type of FU issued 1937system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.18% # Type of FU issued 1938system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.18% # Type of FU issued 1939system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.18% # Type of FU issued 1940system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.18% # Type of FU issued 1941system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.18% # Type of FU issued 1942system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.18% # Type of FU issued 1943system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.18% # Type of FU issued 1944system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.18% # Type of FU issued 1945system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.18% # Type of FU issued 1946system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.18% # Type of FU issued 1947system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.18% # Type of FU issued 1948system.cpu1.iq.FU_type_0::SimdFloatMisc 4119 0.01% 68.19% # Type of FU issued 1949system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued 1950system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued 1951system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued 1952system.cpu1.iq.FU_type_0::MemRead 11419177 19.13% 87.32% # Type of FU issued 1953system.cpu1.iq.FU_type_0::MemWrite 7565361 12.68% 100.00% # Type of FU issued 1954system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1955system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1956system.cpu1.iq.FU_type_0::total 59677362 # Type of FU issued 1957system.cpu1.iq.rate 0.525478 # Inst issue rate 1958system.cpu1.iq.fu_busy_cnt 7754183 # FU busy when requested 1959system.cpu1.iq.fu_busy_rate 0.129935 # FU busy rate (busy events/executed inst) 1960system.cpu1.iq.int_inst_queue_reads 239840869 # Number of integer instruction queue reads 1961system.cpu1.iq.int_inst_queue_writes 65386915 # Number of integer instruction queue writes 1962system.cpu1.iq.int_inst_queue_wakeup_accesses 57545759 # Number of integer instruction queue wakeup accesses 1963system.cpu1.iq.fp_inst_queue_reads 5681 # Number of floating instruction queue reads 1964system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes 1965system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses 1966system.cpu1.iq.int_alu_accesses 67427880 # Number of integer alu accesses 1967system.cpu1.iq.fp_alu_accesses 3598 # Number of floating point alu accesses 1968system.cpu1.iew.lsq.thread0.forwLoads 109848 # Number of loads that had data forwarded from stores 1969system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1970system.cpu1.iew.lsq.thread0.squashedLoads 624171 # Number of loads squashed 1971system.cpu1.iew.lsq.thread0.ignoredResponses 851 # Number of memory responses ignored because the instruction is squashed 1972system.cpu1.iew.lsq.thread0.memOrderViolation 10604 # Number of memory ordering violations 1973system.cpu1.iew.lsq.thread0.squashedStores 419293 # Number of stores squashed 1974system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1975system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1976system.cpu1.iew.lsq.thread0.rescheduledLoads 57328 # Number of loads that were rescheduled 1977system.cpu1.iew.lsq.thread0.cacheBlocked 95447 # Number of times an access to memory failed due to the cache being blocked 1978system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1979system.cpu1.iew.iewSquashCycles 1818961 # Number of cycles IEW is squashing 1980system.cpu1.iew.iewBlockCycles 659321 # Number of cycles IEW is blocking 1981system.cpu1.iew.iewUnblockCycles 119824 # Number of cycles IEW is unblocking 1982system.cpu1.iew.iewDispatchedInsts 60910908 # Number of instructions dispatched to IQ 1983system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 1984system.cpu1.iew.iewDispLoadInsts 11512865 # Number of dispatched load instructions 1985system.cpu1.iew.iewDispStoreInsts 7756589 # Number of dispatched store instructions 1986system.cpu1.iew.iewDispNonSpecInsts 325462 # Number of dispatched non-speculative instructions 1987system.cpu1.iew.iewIQFullEvents 12815 # Number of times the IQ has become full, causing a stall 1988system.cpu1.iew.iewLSQFullEvents 97459 # Number of times the LSQ has become full, causing a stall 1989system.cpu1.iew.memOrderViolationEvents 10604 # Number of memory order violations 1990system.cpu1.iew.predictedTakenIncorrect 81282 # Number of branches that were predicted taken incorrectly 1991system.cpu1.iew.predictedNotTakenIncorrect 152799 # Number of branches that were predicted not taken incorrectly 1992system.cpu1.iew.branchMispredicts 234081 # Number of branch mispredicts detected at execute 1993system.cpu1.iew.iewExecutedInsts 59327650 # Number of executed instructions 1994system.cpu1.iew.iewExecLoadInsts 11286961 # Number of load instructions executed 1995system.cpu1.iew.iewExecSquashedInsts 325473 # Number of squashed instructions skipped in execute 1996system.cpu1.iew.exec_swp 0 # number of swp insts executed 1997system.cpu1.iew.exec_nop 55192 # number of nop insts executed 1998system.cpu1.iew.exec_refs 18774109 # number of memory reference insts executed 1999system.cpu1.iew.exec_branches 12866831 # Number of branches executed 2000system.cpu1.iew.exec_stores 7487148 # Number of stores executed 2001system.cpu1.iew.exec_rate 0.522399 # Inst execution rate 2002system.cpu1.iew.wb_sent 59146208 # cumulative count of insts sent to commit 2003system.cpu1.iew.wb_count 57547543 # cumulative count of insts written-back 2004system.cpu1.iew.wb_producers 28211344 # num instructions producing a value 2005system.cpu1.iew.wb_consumers 43350974 # num instructions consuming a value 2006system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2007system.cpu1.iew.wb_rate 0.506724 # insts written-back per cycle 2008system.cpu1.iew.wb_fanout 0.650766 # average fanout of values written-back 2009system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2010system.cpu1.commit.commitSquashedInsts 4198450 # The number of squashed insts skipped by commit 2011system.cpu1.commit.commitNonSpecStalls 593138 # The number of times commit has been forced to stall to communicate backwards 2012system.cpu1.commit.branchMispredicts 217301 # The number of times a branch was mispredicted 2013system.cpu1.commit.committed_per_cycle::samples 110549070 # Number of insts commited each cycle 2014system.cpu1.commit.committed_per_cycle::mean 0.509875 # Number of insts commited each cycle 2015system.cpu1.commit.committed_per_cycle::stdev 1.177384 # Number of insts commited each cycle 2016system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2017system.cpu1.commit.committed_per_cycle::0 82464476 74.60% 74.60% # Number of insts commited each cycle 2018system.cpu1.commit.committed_per_cycle::1 15679600 14.18% 88.78% # Number of insts commited each cycle 2019system.cpu1.commit.committed_per_cycle::2 6499039 5.88% 94.66% # Number of insts commited each cycle 2020system.cpu1.commit.committed_per_cycle::3 896756 0.81% 95.47% # Number of insts commited each cycle 2021system.cpu1.commit.committed_per_cycle::4 2234307 2.02% 97.49% # Number of insts commited each cycle 2022system.cpu1.commit.committed_per_cycle::5 1661965 1.50% 98.99% # Number of insts commited each cycle 2023system.cpu1.commit.committed_per_cycle::6 498497 0.45% 99.44% # Number of insts commited each cycle 2024system.cpu1.commit.committed_per_cycle::7 155172 0.14% 99.58% # Number of insts commited each cycle 2025system.cpu1.commit.committed_per_cycle::8 459258 0.42% 100.00% # Number of insts commited each cycle 2026system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2027system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2028system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2029system.cpu1.commit.committed_per_cycle::total 110549070 # Number of insts commited each cycle 2030system.cpu1.commit.committedInsts 45875888 # Number of instructions committed 2031system.cpu1.commit.committedOps 56366249 # Number of ops (including micro ops) committed 2032system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2033system.cpu1.commit.refs 18225990 # Number of memory references committed 2034system.cpu1.commit.loads 10888694 # Number of loads committed 2035system.cpu1.commit.membars 231720 # Number of memory barriers committed 2036system.cpu1.commit.branches 12659864 # Number of branches committed 2037system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. 2038system.cpu1.commit.int_insts 50354679 # Number of committed integer instructions. 2039system.cpu1.commit.function_calls 3453612 # Number of function calls committed. 2040system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2041system.cpu1.commit.op_class_0::IntAlu 38084418 67.57% 67.57% # Class of committed instruction 2042system.cpu1.commit.op_class_0::IntMult 51722 0.09% 67.66% # Class of committed instruction 2043system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.66% # Class of committed instruction 2044system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.66% # Class of committed instruction 2045system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.66% # Class of committed instruction 2046system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.66% # Class of committed instruction 2047system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.66% # Class of committed instruction 2048system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.66% # Class of committed instruction 2049system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.66% # Class of committed instruction 2050system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.66% # Class of committed instruction 2051system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.66% # Class of committed instruction 2052system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.66% # Class of committed instruction 2053system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.66% # Class of committed instruction 2054system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.66% # Class of committed instruction 2055system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.66% # Class of committed instruction 2056system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.66% # Class of committed instruction 2057system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.66% # Class of committed instruction 2058system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.66% # Class of committed instruction 2059system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.66% # Class of committed instruction 2060system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.66% # Class of committed instruction 2061system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.66% # Class of committed instruction 2062system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.66% # Class of committed instruction 2063system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.66% # Class of committed instruction 2064system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.66% # Class of committed instruction 2065system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.66% # Class of committed instruction 2066system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.67% # Class of committed instruction 2067system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.67% # Class of committed instruction 2068system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.67% # Class of committed instruction 2069system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.67% # Class of committed instruction 2070system.cpu1.commit.op_class_0::MemRead 10888694 19.32% 86.98% # Class of committed instruction 2071system.cpu1.commit.op_class_0::MemWrite 7337296 13.02% 100.00% # Class of committed instruction 2072system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2073system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2074system.cpu1.commit.op_class_0::total 56366249 # Class of committed instruction 2075system.cpu1.commit.bw_lim_events 459258 # number cycles where commit BW limit reached 2076system.cpu1.rob.rob_reads 150434096 # The number of ROB reads 2077system.cpu1.rob.rob_writes 123166009 # The number of ROB writes 2078system.cpu1.timesIdled 67345 # Number of times that the entire CPU went into an idle state and unscheduled itself 2079system.cpu1.idleCycles 978661 # Total number of cycles that the CPU has spent unscheduled due to idling 2080system.cpu1.quiesceCycles 5136638072 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2081system.cpu1.committedInsts 45842675 # Number of Instructions Simulated 2082system.cpu1.committedOps 56333036 # Number of Ops (including micro ops) Simulated 2083system.cpu1.cpi 2.477336 # CPI: Cycles Per Instruction 2084system.cpu1.cpi_total 2.477336 # CPI: Total CPI of All Threads 2085system.cpu1.ipc 0.403659 # IPC: Instructions Per Cycle 2086system.cpu1.ipc_total 0.403659 # IPC: Total IPC of All Threads 2087system.cpu1.int_regfile_reads 62490093 # number of integer regfile reads 2088system.cpu1.int_regfile_writes 39068646 # number of integer regfile writes 2089system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads 2090system.cpu1.fp_regfile_writes 516 # number of floating regfile writes 2091system.cpu1.cc_regfile_reads 211116899 # number of cc regfile reads 2092system.cpu1.cc_regfile_writes 18233735 # number of cc regfile writes 2093system.cpu1.misc_regfile_reads 220514092 # number of misc regfile reads 2094system.cpu1.misc_regfile_writes 421035 # number of misc regfile writes 2095system.cpu1.dcache.tags.replacements 227457 # number of replacements 2096system.cpu1.dcache.tags.tagsinuse 483.345523 # Cycle average of tags in use 2097system.cpu1.dcache.tags.total_refs 17322126 # Total number of references to valid blocks. 2098system.cpu1.dcache.tags.sampled_refs 227768 # Sample count of references to valid blocks. 2099system.cpu1.dcache.tags.avg_refs 76.051623 # Average number of references to valid blocks. 2100system.cpu1.dcache.tags.warmup_cycle 89024511500 # Cycle when the warmup percentage was hit. 2101system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.345523 # Average occupied blocks per requestor 2102system.cpu1.dcache.tags.occ_percent::cpu1.data 0.944034 # Average percentage of cache occupancy 2103system.cpu1.dcache.tags.occ_percent::total 0.944034 # Average percentage of cache occupancy 2104system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id 2105system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 2106system.cpu1.dcache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id 2107system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id 2108system.cpu1.dcache.tags.tag_accesses 36423981 # Number of tag accesses 2109system.cpu1.dcache.tags.data_accesses 36423981 # Number of data accesses 2110system.cpu1.dcache.ReadReq_hits::cpu1.data 10467087 # number of ReadReq hits 2111system.cpu1.dcache.ReadReq_hits::total 10467087 # number of ReadReq hits 2112system.cpu1.dcache.WriteReq_hits::cpu1.data 6561195 # number of WriteReq hits 2113system.cpu1.dcache.WriteReq_hits::total 6561195 # number of WriteReq hits 2114system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65021 # number of SoftPFReq hits 2115system.cpu1.dcache.SoftPFReq_hits::total 65021 # number of SoftPFReq hits 2116system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88659 # number of LoadLockedReq hits 2117system.cpu1.dcache.LoadLockedReq_hits::total 88659 # number of LoadLockedReq hits 2118system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80691 # number of StoreCondReq hits 2119system.cpu1.dcache.StoreCondReq_hits::total 80691 # number of StoreCondReq hits 2120system.cpu1.dcache.demand_hits::cpu1.data 17028282 # number of demand (read+write) hits 2121system.cpu1.dcache.demand_hits::total 17028282 # number of demand (read+write) hits 2122system.cpu1.dcache.overall_hits::cpu1.data 17093303 # number of overall hits 2123system.cpu1.dcache.overall_hits::total 17093303 # number of overall hits 2124system.cpu1.dcache.ReadReq_misses::cpu1.data 254533 # number of ReadReq misses 2125system.cpu1.dcache.ReadReq_misses::total 254533 # number of ReadReq misses 2126system.cpu1.dcache.WriteReq_misses::cpu1.data 479063 # number of WriteReq misses 2127system.cpu1.dcache.WriteReq_misses::total 479063 # number of WriteReq misses 2128system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35844 # number of SoftPFReq misses 2129system.cpu1.dcache.SoftPFReq_misses::total 35844 # number of SoftPFReq misses 2130system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19098 # number of LoadLockedReq misses 2131system.cpu1.dcache.LoadLockedReq_misses::total 19098 # number of LoadLockedReq misses 2132system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23509 # number of StoreCondReq misses 2133system.cpu1.dcache.StoreCondReq_misses::total 23509 # number of StoreCondReq misses 2134system.cpu1.dcache.demand_misses::cpu1.data 733596 # number of demand (read+write) misses 2135system.cpu1.dcache.demand_misses::total 733596 # number of demand (read+write) misses 2136system.cpu1.dcache.overall_misses::cpu1.data 769440 # number of overall misses 2137system.cpu1.dcache.overall_misses::total 769440 # number of overall misses 2138system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3958996431 # number of ReadReq miss cycles 2139system.cpu1.dcache.ReadReq_miss_latency::total 3958996431 # number of ReadReq miss cycles 2140system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10579018157 # number of WriteReq miss cycles 2141system.cpu1.dcache.WriteReq_miss_latency::total 10579018157 # number of WriteReq miss cycles 2142system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 370185734 # number of LoadLockedReq miss cycles 2143system.cpu1.dcache.LoadLockedReq_miss_latency::total 370185734 # number of LoadLockedReq miss cycles 2144system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549251321 # number of StoreCondReq miss cycles 2145system.cpu1.dcache.StoreCondReq_miss_latency::total 549251321 # number of StoreCondReq miss cycles 2146system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 798500 # number of StoreCondFailReq miss cycles 2147system.cpu1.dcache.StoreCondFailReq_miss_latency::total 798500 # number of StoreCondFailReq miss cycles 2148system.cpu1.dcache.demand_miss_latency::cpu1.data 14538014588 # number of demand (read+write) miss cycles 2149system.cpu1.dcache.demand_miss_latency::total 14538014588 # number of demand (read+write) miss cycles 2150system.cpu1.dcache.overall_miss_latency::cpu1.data 14538014588 # number of overall miss cycles 2151system.cpu1.dcache.overall_miss_latency::total 14538014588 # number of overall miss cycles 2152system.cpu1.dcache.ReadReq_accesses::cpu1.data 10721620 # number of ReadReq accesses(hits+misses) 2153system.cpu1.dcache.ReadReq_accesses::total 10721620 # number of ReadReq accesses(hits+misses) 2154system.cpu1.dcache.WriteReq_accesses::cpu1.data 7040258 # number of WriteReq accesses(hits+misses) 2155system.cpu1.dcache.WriteReq_accesses::total 7040258 # number of WriteReq accesses(hits+misses) 2156system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100865 # number of SoftPFReq accesses(hits+misses) 2157system.cpu1.dcache.SoftPFReq_accesses::total 100865 # number of SoftPFReq accesses(hits+misses) 2158system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107757 # number of LoadLockedReq accesses(hits+misses) 2159system.cpu1.dcache.LoadLockedReq_accesses::total 107757 # number of LoadLockedReq accesses(hits+misses) 2160system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104200 # number of StoreCondReq accesses(hits+misses) 2161system.cpu1.dcache.StoreCondReq_accesses::total 104200 # number of StoreCondReq accesses(hits+misses) 2162system.cpu1.dcache.demand_accesses::cpu1.data 17761878 # number of demand (read+write) accesses 2163system.cpu1.dcache.demand_accesses::total 17761878 # number of demand (read+write) accesses 2164system.cpu1.dcache.overall_accesses::cpu1.data 17862743 # number of overall (read+write) accesses 2165system.cpu1.dcache.overall_accesses::total 17862743 # number of overall (read+write) accesses 2166system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023740 # miss rate for ReadReq accesses 2167system.cpu1.dcache.ReadReq_miss_rate::total 0.023740 # miss rate for ReadReq accesses 2168system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.068046 # miss rate for WriteReq accesses 2169system.cpu1.dcache.WriteReq_miss_rate::total 0.068046 # miss rate for WriteReq accesses 2170system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.355366 # miss rate for SoftPFReq accesses 2171system.cpu1.dcache.SoftPFReq_miss_rate::total 0.355366 # miss rate for SoftPFReq accesses 2172system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177232 # miss rate for LoadLockedReq accesses 2173system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177232 # miss rate for LoadLockedReq accesses 2174system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225614 # miss rate for StoreCondReq accesses 2175system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225614 # miss rate for StoreCondReq accesses 2176system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041302 # miss rate for demand accesses 2177system.cpu1.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses 2178system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043075 # miss rate for overall accesses 2179system.cpu1.dcache.overall_miss_rate::total 0.043075 # miss rate for overall accesses 2180system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15553.961298 # average ReadReq miss latency 2181system.cpu1.dcache.ReadReq_avg_miss_latency::total 15553.961298 # average ReadReq miss latency 2182system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22082.728487 # average WriteReq miss latency 2183system.cpu1.dcache.WriteReq_avg_miss_latency::total 22082.728487 # average WriteReq miss latency 2184system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19383.481726 # average LoadLockedReq miss latency 2185system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19383.481726 # average LoadLockedReq miss latency 2186system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23363.448934 # average StoreCondReq miss latency 2187system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23363.448934 # average StoreCondReq miss latency 2188system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2189system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2190system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19817.467091 # average overall miss latency 2191system.cpu1.dcache.demand_avg_miss_latency::total 19817.467091 # average overall miss latency 2192system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18894.279720 # average overall miss latency 2193system.cpu1.dcache.overall_avg_miss_latency::total 18894.279720 # average overall miss latency 2194system.cpu1.dcache.blocked_cycles::no_mshrs 393 # number of cycles access was blocked 2195system.cpu1.dcache.blocked_cycles::no_targets 1480475 # number of cycles access was blocked 2196system.cpu1.dcache.blocked::no_mshrs 42 # number of cycles access was blocked 2197system.cpu1.dcache.blocked::no_targets 48784 # number of cycles access was blocked 2198system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.357143 # average number of cycles each access was blocked 2199system.cpu1.dcache.avg_blocked_cycles::no_targets 30.347552 # average number of cycles each access was blocked 2200system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2201system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2202system.cpu1.dcache.writebacks::writebacks 138868 # number of writebacks 2203system.cpu1.dcache.writebacks::total 138868 # number of writebacks 2204system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91268 # number of ReadReq MSHR hits 2205system.cpu1.dcache.ReadReq_mshr_hits::total 91268 # number of ReadReq MSHR hits 2206system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375164 # number of WriteReq MSHR hits 2207system.cpu1.dcache.WriteReq_mshr_hits::total 375164 # number of WriteReq MSHR hits 2208system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13545 # number of LoadLockedReq MSHR hits 2209system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13545 # number of LoadLockedReq MSHR hits 2210system.cpu1.dcache.demand_mshr_hits::cpu1.data 466432 # number of demand (read+write) MSHR hits 2211system.cpu1.dcache.demand_mshr_hits::total 466432 # number of demand (read+write) MSHR hits 2212system.cpu1.dcache.overall_mshr_hits::cpu1.data 466432 # number of overall MSHR hits 2213system.cpu1.dcache.overall_mshr_hits::total 466432 # number of overall MSHR hits 2214system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163265 # number of ReadReq MSHR misses 2215system.cpu1.dcache.ReadReq_mshr_misses::total 163265 # number of ReadReq MSHR misses 2216system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103899 # number of WriteReq MSHR misses 2217system.cpu1.dcache.WriteReq_mshr_misses::total 103899 # number of WriteReq MSHR misses 2218system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32275 # number of SoftPFReq MSHR misses 2219system.cpu1.dcache.SoftPFReq_mshr_misses::total 32275 # number of SoftPFReq MSHR misses 2220system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5553 # number of LoadLockedReq MSHR misses 2221system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5553 # number of LoadLockedReq MSHR misses 2222system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23509 # number of StoreCondReq MSHR misses 2223system.cpu1.dcache.StoreCondReq_mshr_misses::total 23509 # number of StoreCondReq MSHR misses 2224system.cpu1.dcache.demand_mshr_misses::cpu1.data 267164 # number of demand (read+write) MSHR misses 2225system.cpu1.dcache.demand_mshr_misses::total 267164 # number of demand (read+write) MSHR misses 2226system.cpu1.dcache.overall_mshr_misses::cpu1.data 299439 # number of overall MSHR misses 2227system.cpu1.dcache.overall_mshr_misses::total 299439 # number of overall MSHR misses 2228system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable 2229system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17059 # number of ReadReq MSHR uncacheable 2230system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable 2231system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable 2232system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses 2233system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31400 # number of overall MSHR uncacheable misses 2234system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2133861458 # number of ReadReq MSHR miss cycles 2235system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2133861458 # number of ReadReq MSHR miss cycles 2236system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2484196176 # number of WriteReq MSHR miss cycles 2237system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2484196176 # number of WriteReq MSHR miss cycles 2238system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 503074190 # number of SoftPFReq MSHR miss cycles 2239system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 503074190 # number of SoftPFReq MSHR miss cycles 2240system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95947255 # number of LoadLockedReq MSHR miss cycles 2241system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95947255 # number of LoadLockedReq MSHR miss cycles 2242system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 512832179 # number of StoreCondReq MSHR miss cycles 2243system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 512832179 # number of StoreCondReq MSHR miss cycles 2244system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 777500 # number of StoreCondFailReq MSHR miss cycles 2245system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 777500 # number of StoreCondFailReq MSHR miss cycles 2246system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4618057634 # number of demand (read+write) MSHR miss cycles 2247system.cpu1.dcache.demand_mshr_miss_latency::total 4618057634 # number of demand (read+write) MSHR miss cycles 2248system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5121131824 # number of overall MSHR miss cycles 2249system.cpu1.dcache.overall_mshr_miss_latency::total 5121131824 # number of overall MSHR miss cycles 2250system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2900210250 # number of ReadReq MSHR uncacheable cycles 2251system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2900210250 # number of ReadReq MSHR uncacheable cycles 2252system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2419067503 # number of WriteReq MSHR uncacheable cycles 2253system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2419067503 # number of WriteReq MSHR uncacheable cycles 2254system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5319277753 # number of overall MSHR uncacheable cycles 2255system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5319277753 # number of overall MSHR uncacheable cycles 2256system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015228 # mshr miss rate for ReadReq accesses 2257system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015228 # mshr miss rate for ReadReq accesses 2258system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014758 # mshr miss rate for WriteReq accesses 2259system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014758 # mshr miss rate for WriteReq accesses 2260system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319982 # mshr miss rate for SoftPFReq accesses 2261system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319982 # mshr miss rate for SoftPFReq accesses 2262system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051533 # mshr miss rate for LoadLockedReq accesses 2263system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051533 # mshr miss rate for LoadLockedReq accesses 2264system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225614 # mshr miss rate for StoreCondReq accesses 2265system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225614 # mshr miss rate for StoreCondReq accesses 2266system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015041 # mshr miss rate for demand accesses 2267system.cpu1.dcache.demand_mshr_miss_rate::total 0.015041 # mshr miss rate for demand accesses 2268system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016763 # mshr miss rate for overall accesses 2269system.cpu1.dcache.overall_mshr_miss_rate::total 0.016763 # mshr miss rate for overall accesses 2270system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13069.925936 # average ReadReq mshr miss latency 2271system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13069.925936 # average ReadReq mshr miss latency 2272system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23909.721711 # average WriteReq mshr miss latency 2273system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23909.721711 # average WriteReq mshr miss latency 2274system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15587.116654 # average SoftPFReq mshr miss latency 2275system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15587.116654 # average SoftPFReq mshr miss latency 2276system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17278.453989 # average LoadLockedReq mshr miss latency 2277system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17278.453989 # average LoadLockedReq mshr miss latency 2278system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21814.291505 # average StoreCondReq mshr miss latency 2279system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21814.291505 # average StoreCondReq mshr miss latency 2280system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2281system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2282system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17285.478710 # average overall mshr miss latency 2283system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17285.478710 # average overall mshr miss latency 2284system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17102.420940 # average overall mshr miss latency 2285system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17102.420940 # average overall mshr miss latency 2286system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170010.566270 # average ReadReq mshr uncacheable latency 2287system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170010.566270 # average ReadReq mshr uncacheable latency 2288system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168681.926156 # average WriteReq mshr uncacheable latency 2289system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168681.926156 # average WriteReq mshr uncacheable latency 2290system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169403.750096 # average overall mshr uncacheable latency 2291system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169403.750096 # average overall mshr uncacheable latency 2292system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2293system.cpu1.icache.tags.replacements 671809 # number of replacements 2294system.cpu1.icache.tags.tagsinuse 498.529348 # Cycle average of tags in use 2295system.cpu1.icache.tags.total_refs 45027049 # Total number of references to valid blocks. 2296system.cpu1.icache.tags.sampled_refs 672321 # Sample count of references to valid blocks. 2297system.cpu1.icache.tags.avg_refs 66.972546 # Average number of references to valid blocks. 2298system.cpu1.icache.tags.warmup_cycle 78856865000 # Cycle when the warmup percentage was hit. 2299system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.529348 # Average occupied blocks per requestor 2300system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973690 # Average percentage of cache occupancy 2301system.cpu1.icache.tags.occ_percent::total 0.973690 # Average percentage of cache occupancy 2302system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2303system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2304system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2305system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2306system.cpu1.icache.tags.tag_accesses 92117192 # Number of tag accesses 2307system.cpu1.icache.tags.data_accesses 92117192 # Number of data accesses 2308system.cpu1.icache.ReadReq_hits::cpu1.inst 45027049 # number of ReadReq hits 2309system.cpu1.icache.ReadReq_hits::total 45027049 # number of ReadReq hits 2310system.cpu1.icache.demand_hits::cpu1.inst 45027049 # number of demand (read+write) hits 2311system.cpu1.icache.demand_hits::total 45027049 # number of demand (read+write) hits 2312system.cpu1.icache.overall_hits::cpu1.inst 45027049 # number of overall hits 2313system.cpu1.icache.overall_hits::total 45027049 # number of overall hits 2314system.cpu1.icache.ReadReq_misses::cpu1.inst 695384 # number of ReadReq misses 2315system.cpu1.icache.ReadReq_misses::total 695384 # number of ReadReq misses 2316system.cpu1.icache.demand_misses::cpu1.inst 695384 # number of demand (read+write) misses 2317system.cpu1.icache.demand_misses::total 695384 # number of demand (read+write) misses 2318system.cpu1.icache.overall_misses::cpu1.inst 695384 # number of overall misses 2319system.cpu1.icache.overall_misses::total 695384 # number of overall misses 2320system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6371214084 # number of ReadReq miss cycles 2321system.cpu1.icache.ReadReq_miss_latency::total 6371214084 # number of ReadReq miss cycles 2322system.cpu1.icache.demand_miss_latency::cpu1.inst 6371214084 # number of demand (read+write) miss cycles 2323system.cpu1.icache.demand_miss_latency::total 6371214084 # number of demand (read+write) miss cycles 2324system.cpu1.icache.overall_miss_latency::cpu1.inst 6371214084 # number of overall miss cycles 2325system.cpu1.icache.overall_miss_latency::total 6371214084 # number of overall miss cycles 2326system.cpu1.icache.ReadReq_accesses::cpu1.inst 45722433 # number of ReadReq accesses(hits+misses) 2327system.cpu1.icache.ReadReq_accesses::total 45722433 # number of ReadReq accesses(hits+misses) 2328system.cpu1.icache.demand_accesses::cpu1.inst 45722433 # number of demand (read+write) accesses 2329system.cpu1.icache.demand_accesses::total 45722433 # number of demand (read+write) accesses 2330system.cpu1.icache.overall_accesses::cpu1.inst 45722433 # number of overall (read+write) accesses 2331system.cpu1.icache.overall_accesses::total 45722433 # number of overall (read+write) accesses 2332system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015209 # miss rate for ReadReq accesses 2333system.cpu1.icache.ReadReq_miss_rate::total 0.015209 # miss rate for ReadReq accesses 2334system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015209 # miss rate for demand accesses 2335system.cpu1.icache.demand_miss_rate::total 0.015209 # miss rate for demand accesses 2336system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015209 # miss rate for overall accesses 2337system.cpu1.icache.overall_miss_rate::total 0.015209 # miss rate for overall accesses 2338system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9162.152255 # average ReadReq miss latency 2339system.cpu1.icache.ReadReq_avg_miss_latency::total 9162.152255 # average ReadReq miss latency 2340system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency 2341system.cpu1.icache.demand_avg_miss_latency::total 9162.152255 # average overall miss latency 2342system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency 2343system.cpu1.icache.overall_avg_miss_latency::total 9162.152255 # average overall miss latency 2344system.cpu1.icache.blocked_cycles::no_mshrs 596666 # number of cycles access was blocked 2345system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked 2346system.cpu1.icache.blocked::no_mshrs 49414 # number of cycles access was blocked 2347system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 2348system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.074837 # average number of cycles each access was blocked 2349system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked 2350system.cpu1.icache.fast_writes 0 # number of fast writes performed 2351system.cpu1.icache.cache_copies 0 # number of cache copies performed 2352system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23058 # number of ReadReq MSHR hits 2353system.cpu1.icache.ReadReq_mshr_hits::total 23058 # number of ReadReq MSHR hits 2354system.cpu1.icache.demand_mshr_hits::cpu1.inst 23058 # number of demand (read+write) MSHR hits 2355system.cpu1.icache.demand_mshr_hits::total 23058 # number of demand (read+write) MSHR hits 2356system.cpu1.icache.overall_mshr_hits::cpu1.inst 23058 # number of overall MSHR hits 2357system.cpu1.icache.overall_mshr_hits::total 23058 # number of overall MSHR hits 2358system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672326 # number of ReadReq MSHR misses 2359system.cpu1.icache.ReadReq_mshr_misses::total 672326 # number of ReadReq MSHR misses 2360system.cpu1.icache.demand_mshr_misses::cpu1.inst 672326 # number of demand (read+write) MSHR misses 2361system.cpu1.icache.demand_mshr_misses::total 672326 # number of demand (read+write) MSHR misses 2362system.cpu1.icache.overall_mshr_misses::cpu1.inst 672326 # number of overall MSHR misses 2363system.cpu1.icache.overall_mshr_misses::total 672326 # number of overall MSHR misses 2364system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable 2365system.cpu1.icache.ReadReq_mshr_uncacheable::total 100 # number of ReadReq MSHR uncacheable 2366system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses 2367system.cpu1.icache.overall_mshr_uncacheable_misses::total 100 # number of overall MSHR uncacheable misses 2368system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5482686465 # number of ReadReq MSHR miss cycles 2369system.cpu1.icache.ReadReq_mshr_miss_latency::total 5482686465 # number of ReadReq MSHR miss cycles 2370system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5482686465 # number of demand (read+write) MSHR miss cycles 2371system.cpu1.icache.demand_mshr_miss_latency::total 5482686465 # number of demand (read+write) MSHR miss cycles 2372system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5482686465 # number of overall MSHR miss cycles 2373system.cpu1.icache.overall_mshr_miss_latency::total 5482686465 # number of overall MSHR miss cycles 2374system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8677000 # number of ReadReq MSHR uncacheable cycles 2375system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8677000 # number of ReadReq MSHR uncacheable cycles 2376system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8677000 # number of overall MSHR uncacheable cycles 2377system.cpu1.icache.overall_mshr_uncacheable_latency::total 8677000 # number of overall MSHR uncacheable cycles 2378system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for ReadReq accesses 2379system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014705 # mshr miss rate for ReadReq accesses 2380system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for demand accesses 2381system.cpu1.icache.demand_mshr_miss_rate::total 0.014705 # mshr miss rate for demand accesses 2382system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for overall accesses 2383system.cpu1.icache.overall_mshr_miss_rate::total 0.014705 # mshr miss rate for overall accesses 2384system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average ReadReq mshr miss latency 2385system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8154.803570 # average ReadReq mshr miss latency 2386system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency 2387system.cpu1.icache.demand_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency 2388system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency 2389system.cpu1.icache.overall_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency 2390system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average ReadReq mshr uncacheable latency 2391system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86770 # average ReadReq mshr uncacheable latency 2392system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average overall mshr uncacheable latency 2393system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86770 # average overall mshr uncacheable latency 2394system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2395system.cpu1.l2cache.prefetcher.num_hwpf_issued 264317 # number of hwpf issued 2396system.cpu1.l2cache.prefetcher.pfIdentified 265106 # number of prefetch candidates identified 2397system.cpu1.l2cache.prefetcher.pfBufferHit 699 # number of redundant prefetches already in prefetch queue 2398system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2399system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2400system.cpu1.l2cache.prefetcher.pfSpanPage 68110 # number of prefetches not generated due to page crossing 2401system.cpu1.l2cache.tags.replacements 61852 # number of replacements 2402system.cpu1.l2cache.tags.tagsinuse 15537.791452 # Cycle average of tags in use 2403system.cpu1.l2cache.tags.total_refs 937119 # Total number of references to valid blocks. 2404system.cpu1.l2cache.tags.sampled_refs 76426 # Sample count of references to valid blocks. 2405system.cpu1.l2cache.tags.avg_refs 12.261783 # Average number of references to valid blocks. 2406system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2407system.cpu1.l2cache.tags.occ_blocks::writebacks 6612.049075 # Average occupied blocks per requestor 2408system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.719968 # Average occupied blocks per requestor 2409system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.202712 # Average occupied blocks per requestor 2410system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4939.798550 # Average occupied blocks per requestor 2411system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2550.027939 # Average occupied blocks per requestor 2412system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1417.993208 # Average occupied blocks per requestor 2413system.cpu1.l2cache.tags.occ_percent::writebacks 0.403567 # Average percentage of cache occupancy 2414system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000959 # Average percentage of cache occupancy 2415system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000134 # Average percentage of cache occupancy 2416system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301501 # Average percentage of cache occupancy 2417system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.155641 # Average percentage of cache occupancy 2418system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086547 # Average percentage of cache occupancy 2419system.cpu1.l2cache.tags.occ_percent::total 0.948352 # Average percentage of cache occupancy 2420system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1249 # Occupied blocks per task id 2421system.cpu1.l2cache.tags.occ_task_id_blocks::1023 36 # Occupied blocks per task id 2422system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13289 # Occupied blocks per task id 2423system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 16 # Occupied blocks per task id 2424system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 878 # Occupied blocks per task id 2425system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 355 # Occupied blocks per task id 2426system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 2427system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id 2428system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 2429system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 2430system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8497 # Occupied blocks per task id 2431system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4330 # Occupied blocks per task id 2432system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076233 # Percentage of cache occupancy per task id 2433system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002197 # Percentage of cache occupancy per task id 2434system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811096 # Percentage of cache occupancy per task id 2435system.cpu1.l2cache.tags.tag_accesses 18910778 # Number of tag accesses 2436system.cpu1.l2cache.tags.data_accesses 18910778 # Number of data accesses 2437system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19107 # number of ReadReq hits 2438system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7219 # number of ReadReq hits 2439system.cpu1.l2cache.ReadReq_hits::cpu1.inst 650283 # number of ReadReq hits 2440system.cpu1.l2cache.ReadReq_hits::cpu1.data 128648 # number of ReadReq hits 2441system.cpu1.l2cache.ReadReq_hits::total 805257 # number of ReadReq hits 2442system.cpu1.l2cache.Writeback_hits::writebacks 138868 # number of Writeback hits 2443system.cpu1.l2cache.Writeback_hits::total 138868 # number of Writeback hits 2444system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1925 # number of UpgradeReq hits 2445system.cpu1.l2cache.UpgradeReq_hits::total 1925 # number of UpgradeReq hits 2446system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1050 # number of SCUpgradeReq hits 2447system.cpu1.l2cache.SCUpgradeReq_hits::total 1050 # number of SCUpgradeReq hits 2448system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38271 # number of ReadExReq hits 2449system.cpu1.l2cache.ReadExReq_hits::total 38271 # number of ReadExReq hits 2450system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19107 # number of demand (read+write) hits 2451system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7219 # number of demand (read+write) hits 2452system.cpu1.l2cache.demand_hits::cpu1.inst 650283 # number of demand (read+write) hits 2453system.cpu1.l2cache.demand_hits::cpu1.data 166919 # number of demand (read+write) hits 2454system.cpu1.l2cache.demand_hits::total 843528 # number of demand (read+write) hits 2455system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19107 # number of overall hits 2456system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7219 # number of overall hits 2457system.cpu1.l2cache.overall_hits::cpu1.inst 650283 # number of overall hits 2458system.cpu1.l2cache.overall_hits::cpu1.data 166919 # number of overall hits 2459system.cpu1.l2cache.overall_hits::total 843528 # number of overall hits 2460system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 427 # number of ReadReq misses 2461system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses 2462system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22038 # number of ReadReq misses 2463system.cpu1.l2cache.ReadReq_misses::cpu1.data 72420 # number of ReadReq misses 2464system.cpu1.l2cache.ReadReq_misses::total 95161 # number of ReadReq misses 2465system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29112 # number of UpgradeReq misses 2466system.cpu1.l2cache.UpgradeReq_misses::total 29112 # number of UpgradeReq misses 2467system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22458 # number of SCUpgradeReq misses 2468system.cpu1.l2cache.SCUpgradeReq_misses::total 22458 # number of SCUpgradeReq misses 2469system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 2470system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 2471system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35228 # number of ReadExReq misses 2472system.cpu1.l2cache.ReadExReq_misses::total 35228 # number of ReadExReq misses 2473system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 427 # number of demand (read+write) misses 2474system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses 2475system.cpu1.l2cache.demand_misses::cpu1.inst 22038 # number of demand (read+write) misses 2476system.cpu1.l2cache.demand_misses::cpu1.data 107648 # number of demand (read+write) misses 2477system.cpu1.l2cache.demand_misses::total 130389 # number of demand (read+write) misses 2478system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 427 # number of overall misses 2479system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses 2480system.cpu1.l2cache.overall_misses::cpu1.inst 22038 # number of overall misses 2481system.cpu1.l2cache.overall_misses::cpu1.data 107648 # number of overall misses 2482system.cpu1.l2cache.overall_misses::total 130389 # number of overall misses 2483system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9785994 # number of ReadReq miss cycles 2484system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5538750 # number of ReadReq miss cycles 2485system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 913296236 # number of ReadReq miss cycles 2486system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1683125409 # number of ReadReq miss cycles 2487system.cpu1.l2cache.ReadReq_miss_latency::total 2611746389 # number of ReadReq miss cycles 2488system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 548231087 # number of UpgradeReq miss cycles 2489system.cpu1.l2cache.UpgradeReq_miss_latency::total 548231087 # number of UpgradeReq miss cycles 2490system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449027944 # number of SCUpgradeReq miss cycles 2491system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449027944 # number of SCUpgradeReq miss cycles 2492system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 763500 # number of SCUpgradeFailReq miss cycles 2493system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 763500 # number of SCUpgradeFailReq miss cycles 2494system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429440182 # number of ReadExReq miss cycles 2495system.cpu1.l2cache.ReadExReq_miss_latency::total 1429440182 # number of ReadExReq miss cycles 2496system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9785994 # number of demand (read+write) miss cycles 2497system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5538750 # number of demand (read+write) miss cycles 2498system.cpu1.l2cache.demand_miss_latency::cpu1.inst 913296236 # number of demand (read+write) miss cycles 2499system.cpu1.l2cache.demand_miss_latency::cpu1.data 3112565591 # number of demand (read+write) miss cycles 2500system.cpu1.l2cache.demand_miss_latency::total 4041186571 # number of demand (read+write) miss cycles 2501system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9785994 # number of overall miss cycles 2502system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5538750 # number of overall miss cycles 2503system.cpu1.l2cache.overall_miss_latency::cpu1.inst 913296236 # number of overall miss cycles 2504system.cpu1.l2cache.overall_miss_latency::cpu1.data 3112565591 # number of overall miss cycles 2505system.cpu1.l2cache.overall_miss_latency::total 4041186571 # number of overall miss cycles 2506system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19534 # number of ReadReq accesses(hits+misses) 2507system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7495 # number of ReadReq accesses(hits+misses) 2508system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 672321 # number of ReadReq accesses(hits+misses) 2509system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201068 # number of ReadReq accesses(hits+misses) 2510system.cpu1.l2cache.ReadReq_accesses::total 900418 # number of ReadReq accesses(hits+misses) 2511system.cpu1.l2cache.Writeback_accesses::writebacks 138868 # number of Writeback accesses(hits+misses) 2512system.cpu1.l2cache.Writeback_accesses::total 138868 # number of Writeback accesses(hits+misses) 2513system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31037 # number of UpgradeReq accesses(hits+misses) 2514system.cpu1.l2cache.UpgradeReq_accesses::total 31037 # number of UpgradeReq accesses(hits+misses) 2515system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23508 # number of SCUpgradeReq accesses(hits+misses) 2516system.cpu1.l2cache.SCUpgradeReq_accesses::total 23508 # number of SCUpgradeReq accesses(hits+misses) 2517system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2518system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2519system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73499 # number of ReadExReq accesses(hits+misses) 2520system.cpu1.l2cache.ReadExReq_accesses::total 73499 # number of ReadExReq accesses(hits+misses) 2521system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19534 # number of demand (read+write) accesses 2522system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7495 # number of demand (read+write) accesses 2523system.cpu1.l2cache.demand_accesses::cpu1.inst 672321 # number of demand (read+write) accesses 2524system.cpu1.l2cache.demand_accesses::cpu1.data 274567 # number of demand (read+write) accesses 2525system.cpu1.l2cache.demand_accesses::total 973917 # number of demand (read+write) accesses 2526system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19534 # number of overall (read+write) accesses 2527system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7495 # number of overall (read+write) accesses 2528system.cpu1.l2cache.overall_accesses::cpu1.inst 672321 # number of overall (read+write) accesses 2529system.cpu1.l2cache.overall_accesses::cpu1.data 274567 # number of overall (read+write) accesses 2530system.cpu1.l2cache.overall_accesses::total 973917 # number of overall (read+write) accesses 2531system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for ReadReq accesses 2532system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036825 # miss rate for ReadReq accesses 2533system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.032779 # miss rate for ReadReq accesses 2534system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.360177 # miss rate for ReadReq accesses 2535system.cpu1.l2cache.ReadReq_miss_rate::total 0.105685 # miss rate for ReadReq accesses 2536system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.937977 # miss rate for UpgradeReq accesses 2537system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937977 # miss rate for UpgradeReq accesses 2538system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955334 # miss rate for SCUpgradeReq accesses 2539system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955334 # miss rate for SCUpgradeReq accesses 2540system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2541system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2542system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.479299 # miss rate for ReadExReq accesses 2543system.cpu1.l2cache.ReadExReq_miss_rate::total 0.479299 # miss rate for ReadExReq accesses 2544system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for demand accesses 2545system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036825 # miss rate for demand accesses 2546system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032779 # miss rate for demand accesses 2547system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392065 # miss rate for demand accesses 2548system.cpu1.l2cache.demand_miss_rate::total 0.133881 # miss rate for demand accesses 2549system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for overall accesses 2550system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036825 # miss rate for overall accesses 2551system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032779 # miss rate for overall accesses 2552system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392065 # miss rate for overall accesses 2553system.cpu1.l2cache.overall_miss_rate::total 0.133881 # miss rate for overall accesses 2554system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average ReadReq miss latency 2555system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20067.934783 # average ReadReq miss latency 2556system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 41441.883837 # average ReadReq miss latency 2557system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23241.168310 # average ReadReq miss latency 2558system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27445.554261 # average ReadReq miss latency 2559system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18831.790567 # average UpgradeReq miss latency 2560system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18831.790567 # average UpgradeReq miss latency 2561system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19994.119868 # average SCUpgradeReq miss latency 2562system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19994.119868 # average SCUpgradeReq miss latency 2563system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 763500 # average SCUpgradeFailReq miss latency 2564system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 763500 # average SCUpgradeFailReq miss latency 2565system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40576.819064 # average ReadExReq miss latency 2566system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40576.819064 # average ReadExReq miss latency 2567system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency 2568system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency 2569system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency 2570system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency 2571system.cpu1.l2cache.demand_avg_miss_latency::total 30993.309029 # average overall miss latency 2572system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency 2573system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency 2574system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency 2575system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency 2576system.cpu1.l2cache.overall_avg_miss_latency::total 30993.309029 # average overall miss latency 2577system.cpu1.l2cache.blocked_cycles::no_mshrs 61 # number of cycles access was blocked 2578system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2579system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked 2580system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2581system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 12.200000 # average number of cycles each access was blocked 2582system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2583system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2584system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2585system.cpu1.l2cache.writebacks::writebacks 35144 # number of writebacks 2586system.cpu1.l2cache.writebacks::total 35144 # number of writebacks 2587system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2588system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits 2589system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 2590system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 141 # number of ReadReq MSHR hits 2591system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits 2592system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 736 # number of ReadExReq MSHR hits 2593system.cpu1.l2cache.ReadExReq_mshr_hits::total 736 # number of ReadExReq MSHR hits 2594system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2595system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits 2596system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 2597system.cpu1.l2cache.demand_mshr_hits::cpu1.data 877 # number of demand (read+write) MSHR hits 2598system.cpu1.l2cache.demand_mshr_hits::total 907 # number of demand (read+write) MSHR hits 2599system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2600system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits 2601system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 2602system.cpu1.l2cache.overall_mshr_hits::cpu1.data 877 # number of overall MSHR hits 2603system.cpu1.l2cache.overall_mshr_hits::total 907 # number of overall MSHR hits 2604system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 426 # number of ReadReq MSHR misses 2605system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 263 # number of ReadReq MSHR misses 2606system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22022 # number of ReadReq MSHR misses 2607system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72279 # number of ReadReq MSHR misses 2608system.cpu1.l2cache.ReadReq_mshr_misses::total 94990 # number of ReadReq MSHR misses 2609system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of HardPFReq MSHR misses 2610system.cpu1.l2cache.HardPFReq_mshr_misses::total 36425 # number of HardPFReq MSHR misses 2611system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29112 # number of UpgradeReq MSHR misses 2612system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29112 # number of UpgradeReq MSHR misses 2613system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22458 # number of SCUpgradeReq MSHR misses 2614system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22458 # number of SCUpgradeReq MSHR misses 2615system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2616system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2617system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34492 # number of ReadExReq MSHR misses 2618system.cpu1.l2cache.ReadExReq_mshr_misses::total 34492 # number of ReadExReq MSHR misses 2619system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 426 # number of demand (read+write) MSHR misses 2620system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 263 # number of demand (read+write) MSHR misses 2621system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22022 # number of demand (read+write) MSHR misses 2622system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106771 # number of demand (read+write) MSHR misses 2623system.cpu1.l2cache.demand_mshr_misses::total 129482 # number of demand (read+write) MSHR misses 2624system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 426 # number of overall MSHR misses 2625system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 263 # number of overall MSHR misses 2626system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22022 # number of overall MSHR misses 2627system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106771 # number of overall MSHR misses 2628system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of overall MSHR misses 2629system.cpu1.l2cache.overall_mshr_misses::total 165907 # number of overall MSHR misses 2630system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable 2631system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable 2632system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17159 # number of ReadReq MSHR uncacheable 2633system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable 2634system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable 2635system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses 2636system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses 2637system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31500 # number of overall MSHR uncacheable misses 2638system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of ReadReq MSHR miss cycles 2639system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3664750 # number of ReadReq MSHR miss cycles 2640system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 767719764 # number of ReadReq MSHR miss cycles 2641system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1208019590 # number of ReadReq MSHR miss cycles 2642system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1986398104 # number of ReadReq MSHR miss cycles 2643system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of HardPFReq MSHR miss cycles 2644system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1404338548 # number of HardPFReq MSHR miss cycles 2645system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484116716 # number of UpgradeReq MSHR miss cycles 2646system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484116716 # number of UpgradeReq MSHR miss cycles 2647system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 336604833 # number of SCUpgradeReq MSHR miss cycles 2648system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 336604833 # number of SCUpgradeReq MSHR miss cycles 2649system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 672500 # number of SCUpgradeFailReq MSHR miss cycles 2650system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 672500 # number of SCUpgradeFailReq MSHR miss cycles 2651system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121552915 # number of ReadExReq MSHR miss cycles 2652system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121552915 # number of ReadExReq MSHR miss cycles 2653system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of demand (read+write) MSHR miss cycles 2654system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3664750 # number of demand (read+write) MSHR miss cycles 2655system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 767719764 # number of demand (read+write) MSHR miss cycles 2656system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2329572505 # number of demand (read+write) MSHR miss cycles 2657system.cpu1.l2cache.demand_mshr_miss_latency::total 3107951019 # number of demand (read+write) MSHR miss cycles 2658system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of overall MSHR miss cycles 2659system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3664750 # number of overall MSHR miss cycles 2660system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 767719764 # number of overall MSHR miss cycles 2661system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2329572505 # number of overall MSHR miss cycles 2662system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of overall MSHR miss cycles 2663system.cpu1.l2cache.overall_mshr_miss_latency::total 4512289567 # number of overall MSHR miss cycles 2664system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7885000 # number of ReadReq MSHR uncacheable cycles 2665system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2763450750 # number of ReadReq MSHR uncacheable cycles 2666system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2771335750 # number of ReadReq MSHR uncacheable cycles 2667system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2311397498 # number of WriteReq MSHR uncacheable cycles 2668system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2311397498 # number of WriteReq MSHR uncacheable cycles 2669system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7885000 # number of overall MSHR uncacheable cycles 2670system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5074848248 # number of overall MSHR uncacheable cycles 2671system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5082733248 # number of overall MSHR uncacheable cycles 2672system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for ReadReq accesses 2673system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for ReadReq accesses 2674system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for ReadReq accesses 2675system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.359475 # mshr miss rate for ReadReq accesses 2676system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.105495 # mshr miss rate for ReadReq accesses 2677system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2678system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2679system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.937977 # mshr miss rate for UpgradeReq accesses 2680system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937977 # mshr miss rate for UpgradeReq accesses 2681system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955334 # mshr miss rate for SCUpgradeReq accesses 2682system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955334 # mshr miss rate for SCUpgradeReq accesses 2683system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2684system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2685system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.469285 # mshr miss rate for ReadExReq accesses 2686system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.469285 # mshr miss rate for ReadExReq accesses 2687system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for demand accesses 2688system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for demand accesses 2689system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for demand accesses 2690system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for demand accesses 2691system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132950 # mshr miss rate for demand accesses 2692system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for overall accesses 2693system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for overall accesses 2694system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for overall accesses 2695system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for overall accesses 2696system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2697system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses 2698system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average ReadReq mshr miss latency 2699system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average ReadReq mshr miss latency 2700system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average ReadReq mshr miss latency 2701system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16713.285878 # average ReadReq mshr miss latency 2702system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20911.654953 # average ReadReq mshr miss latency 2703system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average HardPFReq mshr miss latency 2704system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38554.249774 # average HardPFReq mshr miss latency 2705system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16629.455757 # average UpgradeReq mshr miss latency 2706system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757 # average UpgradeReq mshr miss latency 2707system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14988.192760 # average SCUpgradeReq mshr miss latency 2708system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14988.192760 # average SCUpgradeReq mshr miss latency 2709system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 672500 # average SCUpgradeFailReq mshr miss latency 2710system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672500 # average SCUpgradeFailReq mshr miss latency 2711system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32516.320161 # average ReadExReq mshr miss latency 2712system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32516.320161 # average ReadExReq mshr miss latency 2713system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency 2714system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency 2715system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency 2716system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency 2717system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24002.958087 # average overall mshr miss latency 2718system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency 2719system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency 2720system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency 2721system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency 2722system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average overall mshr miss latency 2723system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27197.704539 # average overall mshr miss latency 2724system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average ReadReq mshr uncacheable latency 2725system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161993.712996 # average ReadReq mshr uncacheable latency 2726system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161509.164287 # average ReadReq mshr uncacheable latency 2727system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161174.081166 # average WriteReq mshr uncacheable latency 2728system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161174.081166 # average WriteReq mshr uncacheable latency 2729system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average overall mshr uncacheable latency 2730system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161619.370955 # average overall mshr uncacheable latency 2731system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048 # average overall mshr uncacheable latency 2732system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2733system.cpu1.toL2Bus.trans_dist::ReadReq 1277963 # Transaction distribution 2734system.cpu1.toL2Bus.trans_dist::ReadResp 964810 # Transaction distribution 2735system.cpu1.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution 2736system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution 2737system.cpu1.toL2Bus.trans_dist::Writeback 138868 # Transaction distribution 2738system.cpu1.toL2Bus.trans_dist::HardPFReq 45574 # Transaction distribution 2739system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2740system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution 2741system.cpu1.toL2Bus.trans_dist::UpgradeReq 76215 # Transaction distribution 2742system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43067 # Transaction distribution 2743system.cpu1.toL2Bus.trans_dist::UpgradeResp 89621 # Transaction distribution 2744system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution 2745system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution 2746system.cpu1.toL2Bus.trans_dist::ReadExReq 96319 # Transaction distribution 2747system.cpu1.toL2Bus.trans_dist::ReadExResp 79290 # Transaction distribution 2748system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1344847 # Packet count per connected master and slave (bytes) 2749system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 942237 # Packet count per connected master and slave (bytes) 2750system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16928 # Packet count per connected master and slave (bytes) 2751system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42916 # Packet count per connected master and slave (bytes) 2752system.cpu1.toL2Bus.pkt_count::total 2346928 # Packet count per connected master and slave (bytes) 2753system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43030144 # Cumulative packet size per connected master and slave (bytes) 2754system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29597157 # Cumulative packet size per connected master and slave (bytes) 2755system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29980 # Cumulative packet size per connected master and slave (bytes) 2756system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78136 # Cumulative packet size per connected master and slave (bytes) 2757system.cpu1.toL2Bus.pkt_size::total 72735417 # Cumulative packet size per connected master and slave (bytes) 2758system.cpu1.toL2Bus.snoops 628857 # Total snoops (count) 2759system.cpu1.toL2Bus.snoop_fanout::samples 1745350 # Request fanout histogram 2760system.cpu1.toL2Bus.snoop_fanout::mean 1.328609 # Request fanout histogram 2761system.cpu1.toL2Bus.snoop_fanout::stdev 0.469708 # Request fanout histogram 2762system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2763system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2764system.cpu1.toL2Bus.snoop_fanout::1 1171812 67.14% 67.14% # Request fanout histogram 2765system.cpu1.toL2Bus.snoop_fanout::2 573538 32.86% 100.00% # Request fanout histogram 2766system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2767system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2768system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2769system.cpu1.toL2Bus.snoop_fanout::total 1745350 # Request fanout histogram 2770system.cpu1.toL2Bus.reqLayer0.occupancy 748369465 # Layer occupancy (ticks) 2771system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2772system.cpu1.toL2Bus.snoopLayer0.occupancy 88425999 # Layer occupancy (ticks) 2773system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2774system.cpu1.toL2Bus.respLayer0.occupancy 1009581341 # Layer occupancy (ticks) 2775system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2776system.cpu1.toL2Bus.respLayer1.occupancy 468876167 # Layer occupancy (ticks) 2777system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2778system.cpu1.toL2Bus.respLayer2.occupancy 9538553 # Layer occupancy (ticks) 2779system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2780system.cpu1.toL2Bus.respLayer3.occupancy 23419937 # Layer occupancy (ticks) 2781system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2782system.iobus.trans_dist::ReadReq 31011 # Transaction distribution 2783system.iobus.trans_dist::ReadResp 31011 # Transaction distribution 2784system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2785system.iobus.trans_dist::WriteResp 23197 # Transaction distribution 2786system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2787system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2788system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2789system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2790system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2791system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2792system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes) 2793system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2794system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2795system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2796system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2797system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2798system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2799system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2800system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2801system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2802system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2803system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2804system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2805system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2806system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2807system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2808system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) 2809system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2810system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2811system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) 2812system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) 2813system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2814system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2815system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2816system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2817system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes) 2818system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2819system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2820system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2821system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2822system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2823system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2824system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2825system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2826system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2827system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2828system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2829system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2830system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2831system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2832system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2833system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes) 2834system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2835system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2836system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes) 2837system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks) 2838system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2839system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2840system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2841system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2842system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2843system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2844system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2845system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2846system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2847system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks) 2848system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2849system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2850system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2851system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2852system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2853system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2854system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2855system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2856system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2857system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2858system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2859system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2860system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2861system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2862system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2863system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2864system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2865system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2866system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2867system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2868system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2869system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2870system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2871system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2872system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2873system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2874system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2875system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2876system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2877system.iobus.reqLayer27.occupancy 198987475 # Layer occupancy (ticks) 2878system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2879system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2880system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2881system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks) 2882system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2883system.iobus.respLayer3.occupancy 36777012 # Layer occupancy (ticks) 2884system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2885system.iocache.tags.replacements 36458 # number of replacements 2886system.iocache.tags.tagsinuse 14.446991 # Cycle average of tags in use 2887system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2888system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2889system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2890system.iocache.tags.warmup_cycle 254817991000 # Cycle when the warmup percentage was hit. 2891system.iocache.tags.occ_blocks::realview.ide 14.446991 # Average occupied blocks per requestor 2892system.iocache.tags.occ_percent::realview.ide 0.902937 # Average percentage of cache occupancy 2893system.iocache.tags.occ_percent::total 0.902937 # Average percentage of cache occupancy 2894system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2895system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2896system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2897system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2898system.iocache.tags.data_accesses 328284 # Number of data accesses 2899system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2900system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2901system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2902system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2903system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 2904system.iocache.demand_misses::total 252 # number of demand (read+write) misses 2905system.iocache.overall_misses::realview.ide 252 # number of overall misses 2906system.iocache.overall_misses::total 252 # number of overall misses 2907system.iocache.ReadReq_miss_latency::realview.ide 32304877 # number of ReadReq miss cycles 2908system.iocache.ReadReq_miss_latency::total 32304877 # number of ReadReq miss cycles 2909system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652654586 # number of WriteInvalidateReq miss cycles 2910system.iocache.WriteInvalidateReq_miss_latency::total 6652654586 # number of WriteInvalidateReq miss cycles 2911system.iocache.demand_miss_latency::realview.ide 32304877 # number of demand (read+write) miss cycles 2912system.iocache.demand_miss_latency::total 32304877 # number of demand (read+write) miss cycles 2913system.iocache.overall_miss_latency::realview.ide 32304877 # number of overall miss cycles 2914system.iocache.overall_miss_latency::total 32304877 # number of overall miss cycles 2915system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2916system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2917system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2918system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2919system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 2920system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 2921system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 2922system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 2923system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2924system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2925system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2926system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2927system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2928system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2929system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2930system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2931system.iocache.ReadReq_avg_miss_latency::realview.ide 128193.956349 # average ReadReq miss latency 2932system.iocache.ReadReq_avg_miss_latency::total 128193.956349 # average ReadReq miss latency 2933system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183653.229516 # average WriteInvalidateReq miss latency 2934system.iocache.WriteInvalidateReq_avg_miss_latency::total 183653.229516 # average WriteInvalidateReq miss latency 2935system.iocache.demand_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency 2936system.iocache.demand_avg_miss_latency::total 128193.956349 # average overall miss latency 2937system.iocache.overall_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency 2938system.iocache.overall_avg_miss_latency::total 128193.956349 # average overall miss latency 2939system.iocache.blocked_cycles::no_mshrs 22817 # number of cycles access was blocked 2940system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2941system.iocache.blocked::no_mshrs 3477 # number of cycles access was blocked 2942system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2943system.iocache.avg_blocked_cycles::no_mshrs 6.562266 # average number of cycles each access was blocked 2944system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2945system.iocache.fast_writes 0 # number of fast writes performed 2946system.iocache.cache_copies 0 # number of cache copies performed 2947system.iocache.writebacks::writebacks 36206 # number of writebacks 2948system.iocache.writebacks::total 36206 # number of writebacks 2949system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 2950system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 2951system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2952system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2953system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses 2954system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses 2955system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses 2956system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses 2957system.iocache.ReadReq_mshr_miss_latency::realview.ide 19198877 # number of ReadReq MSHR miss cycles 2958system.iocache.ReadReq_mshr_miss_latency::total 19198877 # number of ReadReq MSHR miss cycles 2959system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768982610 # number of WriteInvalidateReq MSHR miss cycles 2960system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768982610 # number of WriteInvalidateReq MSHR miss cycles 2961system.iocache.demand_mshr_miss_latency::realview.ide 19198877 # number of demand (read+write) MSHR miss cycles 2962system.iocache.demand_mshr_miss_latency::total 19198877 # number of demand (read+write) MSHR miss cycles 2963system.iocache.overall_mshr_miss_latency::realview.ide 19198877 # number of overall MSHR miss cycles 2964system.iocache.overall_mshr_miss_latency::total 19198877 # number of overall MSHR miss cycles 2965system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2966system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2967system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2968system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2969system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2970system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2971system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2972system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2973system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76186.019841 # average ReadReq mshr miss latency 2974system.iocache.ReadReq_avg_mshr_miss_latency::total 76186.019841 # average ReadReq mshr miss latency 2975system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131652.567635 # average WriteInvalidateReq mshr miss latency 2976system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131652.567635 # average WriteInvalidateReq mshr miss latency 2977system.iocache.demand_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency 2978system.iocache.demand_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency 2979system.iocache.overall_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency 2980system.iocache.overall_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency 2981system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2982system.l2c.tags.replacements 130801 # number of replacements 2983system.l2c.tags.tagsinuse 64048.619051 # Cycle average of tags in use 2984system.l2c.tags.total_refs 351623 # Total number of references to valid blocks. 2985system.l2c.tags.sampled_refs 195125 # Sample count of references to valid blocks. 2986system.l2c.tags.avg_refs 1.802040 # Average number of references to valid blocks. 2987system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2988system.l2c.tags.occ_blocks::writebacks 12682.907006 # Average occupied blocks per requestor 2989system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.525676 # Average occupied blocks per requestor 2990system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048604 # Average occupied blocks per requestor 2991system.l2c.tags.occ_blocks::cpu0.inst 5727.667382 # Average occupied blocks per requestor 2992system.l2c.tags.occ_blocks::cpu0.data 1961.871644 # Average occupied blocks per requestor 2993system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34750.097208 # Average occupied blocks per requestor 2994system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.787095 # Average occupied blocks per requestor 2995system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903255 # Average occupied blocks per requestor 2996system.l2c.tags.occ_blocks::cpu1.inst 3571.469043 # Average occupied blocks per requestor 2997system.l2c.tags.occ_blocks::cpu1.data 1470.884658 # Average occupied blocks per requestor 2998system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3857.457480 # Average occupied blocks per requestor 2999system.l2c.tags.occ_percent::writebacks 0.193526 # Average percentage of cache occupancy 3000system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy 3001system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy 3002system.l2c.tags.occ_percent::cpu0.inst 0.087397 # Average percentage of cache occupancy 3003system.l2c.tags.occ_percent::cpu0.data 0.029936 # Average percentage of cache occupancy 3004system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.530244 # Average percentage of cache occupancy 3005system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy 3006system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 3007system.l2c.tags.occ_percent::cpu1.inst 0.054496 # Average percentage of cache occupancy 3008system.l2c.tags.occ_percent::cpu1.data 0.022444 # Average percentage of cache occupancy 3009system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058860 # Average percentage of cache occupancy 3010system.l2c.tags.occ_percent::total 0.977304 # Average percentage of cache occupancy 3011system.l2c.tags.occ_task_id_blocks::1022 31466 # Occupied blocks per task id 3012system.l2c.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id 3013system.l2c.tags.occ_task_id_blocks::1024 32827 # Occupied blocks per task id 3014system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id 3015system.l2c.tags.age_task_id_blocks_1022::3 6139 # Occupied blocks per task id 3016system.l2c.tags.age_task_id_blocks_1022::4 25208 # Occupied blocks per task id 3017system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 3018system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id 3019system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 3020system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 3021system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 3022system.l2c.tags.age_task_id_blocks_1024::3 4937 # Occupied blocks per task id 3023system.l2c.tags.age_task_id_blocks_1024::4 27395 # Occupied blocks per task id 3024system.l2c.tags.occ_task_id_percent::1022 0.480133 # Percentage of cache occupancy per task id 3025system.l2c.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id 3026system.l2c.tags.occ_task_id_percent::1024 0.500900 # Percentage of cache occupancy per task id 3027system.l2c.tags.tag_accesses 5006121 # Number of tag accesses 3028system.l2c.tags.data_accesses 5006121 # Number of data accesses 3029system.l2c.ReadReq_hits::cpu0.dtb.walker 169 # number of ReadReq hits 3030system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits 3031system.l2c.ReadReq_hits::cpu0.inst 31569 # number of ReadReq hits 3032system.l2c.ReadReq_hits::cpu0.data 45303 # number of ReadReq hits 3033system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 43197 # number of ReadReq hits 3034system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits 3035system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits 3036system.l2c.ReadReq_hits::cpu1.inst 16772 # number of ReadReq hits 3037system.l2c.ReadReq_hits::cpu1.data 11005 # number of ReadReq hits 3038system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7251 # number of ReadReq hits 3039system.l2c.ReadReq_hits::total 155435 # number of ReadReq hits 3040system.l2c.Writeback_hits::writebacks 227479 # number of Writeback hits 3041system.l2c.Writeback_hits::total 227479 # number of Writeback hits 3042system.l2c.UpgradeReq_hits::cpu0.data 2575 # number of UpgradeReq hits 3043system.l2c.UpgradeReq_hits::cpu1.data 820 # number of UpgradeReq hits 3044system.l2c.UpgradeReq_hits::total 3395 # number of UpgradeReq hits 3045system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits 3046system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits 3047system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits 3048system.l2c.ReadExReq_hits::cpu0.data 3872 # number of ReadExReq hits 3049system.l2c.ReadExReq_hits::cpu1.data 2196 # number of ReadExReq hits 3050system.l2c.ReadExReq_hits::total 6068 # number of ReadExReq hits 3051system.l2c.demand_hits::cpu0.dtb.walker 169 # number of demand (read+write) hits 3052system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits 3053system.l2c.demand_hits::cpu0.inst 31569 # number of demand (read+write) hits 3054system.l2c.demand_hits::cpu0.data 49175 # number of demand (read+write) hits 3055system.l2c.demand_hits::cpu0.l2cache.prefetcher 43197 # number of demand (read+write) hits 3056system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits 3057system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits 3058system.l2c.demand_hits::cpu1.inst 16772 # number of demand (read+write) hits 3059system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits 3060system.l2c.demand_hits::cpu1.l2cache.prefetcher 7251 # number of demand (read+write) hits 3061system.l2c.demand_hits::total 161503 # number of demand (read+write) hits 3062system.l2c.overall_hits::cpu0.dtb.walker 169 # number of overall hits 3063system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits 3064system.l2c.overall_hits::cpu0.inst 31569 # number of overall hits 3065system.l2c.overall_hits::cpu0.data 49175 # number of overall hits 3066system.l2c.overall_hits::cpu0.l2cache.prefetcher 43197 # number of overall hits 3067system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits 3068system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits 3069system.l2c.overall_hits::cpu1.inst 16772 # number of overall hits 3070system.l2c.overall_hits::cpu1.data 13201 # number of overall hits 3071system.l2c.overall_hits::cpu1.l2cache.prefetcher 7251 # number of overall hits 3072system.l2c.overall_hits::total 161503 # number of overall hits 3073system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses 3074system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses 3075system.l2c.ReadReq_misses::cpu0.inst 17327 # number of ReadReq misses 3076system.l2c.ReadReq_misses::cpu0.data 8118 # number of ReadReq misses 3077system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq misses 3078system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses 3079system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 3080system.l2c.ReadReq_misses::cpu1.inst 5250 # number of ReadReq misses 3081system.l2c.ReadReq_misses::cpu1.data 2138 # number of ReadReq misses 3082system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq misses 3083system.l2c.ReadReq_misses::total 171166 # number of ReadReq misses 3084system.l2c.UpgradeReq_misses::cpu0.data 8455 # number of UpgradeReq misses 3085system.l2c.UpgradeReq_misses::cpu1.data 3870 # number of UpgradeReq misses 3086system.l2c.UpgradeReq_misses::total 12325 # number of UpgradeReq misses 3087system.l2c.SCUpgradeReq_misses::cpu0.data 920 # number of SCUpgradeReq misses 3088system.l2c.SCUpgradeReq_misses::cpu1.data 1168 # number of SCUpgradeReq misses 3089system.l2c.SCUpgradeReq_misses::total 2088 # number of SCUpgradeReq misses 3090system.l2c.ReadExReq_misses::cpu0.data 10724 # number of ReadExReq misses 3091system.l2c.ReadExReq_misses::cpu1.data 8176 # number of ReadExReq misses 3092system.l2c.ReadExReq_misses::total 18900 # number of ReadExReq misses 3093system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses 3094system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses 3095system.l2c.demand_misses::cpu0.inst 17327 # number of demand (read+write) misses 3096system.l2c.demand_misses::cpu0.data 18842 # number of demand (read+write) misses 3097system.l2c.demand_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) misses 3098system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses 3099system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3100system.l2c.demand_misses::cpu1.inst 5250 # number of demand (read+write) misses 3101system.l2c.demand_misses::cpu1.data 10314 # number of demand (read+write) misses 3102system.l2c.demand_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) misses 3103system.l2c.demand_misses::total 190066 # number of demand (read+write) misses 3104system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses 3105system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses 3106system.l2c.overall_misses::cpu0.inst 17327 # number of overall misses 3107system.l2c.overall_misses::cpu0.data 18842 # number of overall misses 3108system.l2c.overall_misses::cpu0.l2cache.prefetcher 128828 # number of overall misses 3109system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses 3110system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3111system.l2c.overall_misses::cpu1.inst 5250 # number of overall misses 3112system.l2c.overall_misses::cpu1.data 10314 # number of overall misses 3113system.l2c.overall_misses::cpu1.l2cache.prefetcher 9461 # number of overall misses 3114system.l2c.overall_misses::total 190066 # number of overall misses 3115system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2599500 # number of ReadReq miss cycles 3116system.l2c.ReadReq_miss_latency::cpu0.itb.walker 443500 # number of ReadReq miss cycles 3117system.l2c.ReadReq_miss_latency::cpu0.inst 1426835542 # number of ReadReq miss cycles 3118system.l2c.ReadReq_miss_latency::cpu0.data 735252946 # number of ReadReq miss cycles 3119system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of ReadReq miss cycles 3120system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1206000 # number of ReadReq miss cycles 3121system.l2c.ReadReq_miss_latency::cpu1.itb.walker 97250 # number of ReadReq miss cycles 3122system.l2c.ReadReq_miss_latency::cpu1.inst 448103000 # number of ReadReq miss cycles 3123system.l2c.ReadReq_miss_latency::cpu1.data 186224591 # number of ReadReq miss cycles 3124system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of ReadReq miss cycles 3125system.l2c.ReadReq_miss_latency::total 18394990666 # number of ReadReq miss cycles 3126system.l2c.UpgradeReq_miss_latency::cpu0.data 7116778 # number of UpgradeReq miss cycles 3127system.l2c.UpgradeReq_miss_latency::cpu1.data 2985907 # number of UpgradeReq miss cycles 3128system.l2c.UpgradeReq_miss_latency::total 10102685 # number of UpgradeReq miss cycles 3129system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1350463 # number of SCUpgradeReq miss cycles 3130system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1030967 # number of SCUpgradeReq miss cycles 3131system.l2c.SCUpgradeReq_miss_latency::total 2381430 # number of SCUpgradeReq miss cycles 3132system.l2c.ReadExReq_miss_latency::cpu0.data 1037256751 # number of ReadExReq miss cycles 3133system.l2c.ReadExReq_miss_latency::cpu1.data 678589231 # number of ReadExReq miss cycles 3134system.l2c.ReadExReq_miss_latency::total 1715845982 # number of ReadExReq miss cycles 3135system.l2c.demand_miss_latency::cpu0.dtb.walker 2599500 # number of demand (read+write) miss cycles 3136system.l2c.demand_miss_latency::cpu0.itb.walker 443500 # number of demand (read+write) miss cycles 3137system.l2c.demand_miss_latency::cpu0.inst 1426835542 # number of demand (read+write) miss cycles 3138system.l2c.demand_miss_latency::cpu0.data 1772509697 # number of demand (read+write) miss cycles 3139system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of demand (read+write) miss cycles 3140system.l2c.demand_miss_latency::cpu1.dtb.walker 1206000 # number of demand (read+write) miss cycles 3141system.l2c.demand_miss_latency::cpu1.itb.walker 97250 # number of demand (read+write) miss cycles 3142system.l2c.demand_miss_latency::cpu1.inst 448103000 # number of demand (read+write) miss cycles 3143system.l2c.demand_miss_latency::cpu1.data 864813822 # number of demand (read+write) miss cycles 3144system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of demand (read+write) miss cycles 3145system.l2c.demand_miss_latency::total 20110836648 # number of demand (read+write) miss cycles 3146system.l2c.overall_miss_latency::cpu0.dtb.walker 2599500 # number of overall miss cycles 3147system.l2c.overall_miss_latency::cpu0.itb.walker 443500 # number of overall miss cycles 3148system.l2c.overall_miss_latency::cpu0.inst 1426835542 # number of overall miss cycles 3149system.l2c.overall_miss_latency::cpu0.data 1772509697 # number of overall miss cycles 3150system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of overall miss cycles 3151system.l2c.overall_miss_latency::cpu1.dtb.walker 1206000 # number of overall miss cycles 3152system.l2c.overall_miss_latency::cpu1.itb.walker 97250 # number of overall miss cycles 3153system.l2c.overall_miss_latency::cpu1.inst 448103000 # number of overall miss cycles 3154system.l2c.overall_miss_latency::cpu1.data 864813822 # number of overall miss cycles 3155system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of overall miss cycles 3156system.l2c.overall_miss_latency::total 20110836648 # number of overall miss cycles 3157system.l2c.ReadReq_accesses::cpu0.dtb.walker 196 # number of ReadReq accesses(hits+misses) 3158system.l2c.ReadReq_accesses::cpu0.itb.walker 73 # number of ReadReq accesses(hits+misses) 3159system.l2c.ReadReq_accesses::cpu0.inst 48896 # number of ReadReq accesses(hits+misses) 3160system.l2c.ReadReq_accesses::cpu0.data 53421 # number of ReadReq accesses(hits+misses) 3161system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 172025 # number of ReadReq accesses(hits+misses) 3162system.l2c.ReadReq_accesses::cpu1.dtb.walker 79 # number of ReadReq accesses(hits+misses) 3163system.l2c.ReadReq_accesses::cpu1.itb.walker 34 # number of ReadReq accesses(hits+misses) 3164system.l2c.ReadReq_accesses::cpu1.inst 22022 # number of ReadReq accesses(hits+misses) 3165system.l2c.ReadReq_accesses::cpu1.data 13143 # number of ReadReq accesses(hits+misses) 3166system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 16712 # number of ReadReq accesses(hits+misses) 3167system.l2c.ReadReq_accesses::total 326601 # number of ReadReq accesses(hits+misses) 3168system.l2c.Writeback_accesses::writebacks 227479 # number of Writeback accesses(hits+misses) 3169system.l2c.Writeback_accesses::total 227479 # number of Writeback accesses(hits+misses) 3170system.l2c.UpgradeReq_accesses::cpu0.data 11030 # number of UpgradeReq accesses(hits+misses) 3171system.l2c.UpgradeReq_accesses::cpu1.data 4690 # number of UpgradeReq accesses(hits+misses) 3172system.l2c.UpgradeReq_accesses::total 15720 # number of UpgradeReq accesses(hits+misses) 3173system.l2c.SCUpgradeReq_accesses::cpu0.data 1175 # number of SCUpgradeReq accesses(hits+misses) 3174system.l2c.SCUpgradeReq_accesses::cpu1.data 1266 # number of SCUpgradeReq accesses(hits+misses) 3175system.l2c.SCUpgradeReq_accesses::total 2441 # number of SCUpgradeReq accesses(hits+misses) 3176system.l2c.ReadExReq_accesses::cpu0.data 14596 # number of ReadExReq accesses(hits+misses) 3177system.l2c.ReadExReq_accesses::cpu1.data 10372 # number of ReadExReq accesses(hits+misses) 3178system.l2c.ReadExReq_accesses::total 24968 # number of ReadExReq accesses(hits+misses) 3179system.l2c.demand_accesses::cpu0.dtb.walker 196 # number of demand (read+write) accesses 3180system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses 3181system.l2c.demand_accesses::cpu0.inst 48896 # number of demand (read+write) accesses 3182system.l2c.demand_accesses::cpu0.data 68017 # number of demand (read+write) accesses 3183system.l2c.demand_accesses::cpu0.l2cache.prefetcher 172025 # number of demand (read+write) accesses 3184system.l2c.demand_accesses::cpu1.dtb.walker 79 # number of demand (read+write) accesses 3185system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses 3186system.l2c.demand_accesses::cpu1.inst 22022 # number of demand (read+write) accesses 3187system.l2c.demand_accesses::cpu1.data 23515 # number of demand (read+write) accesses 3188system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16712 # number of demand (read+write) accesses 3189system.l2c.demand_accesses::total 351569 # number of demand (read+write) accesses 3190system.l2c.overall_accesses::cpu0.dtb.walker 196 # number of overall (read+write) accesses 3191system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses 3192system.l2c.overall_accesses::cpu0.inst 48896 # number of overall (read+write) accesses 3193system.l2c.overall_accesses::cpu0.data 68017 # number of overall (read+write) accesses 3194system.l2c.overall_accesses::cpu0.l2cache.prefetcher 172025 # number of overall (read+write) accesses 3195system.l2c.overall_accesses::cpu1.dtb.walker 79 # number of overall (read+write) accesses 3196system.l2c.overall_accesses::cpu1.itb.walker 34 # number of overall (read+write) accesses 3197system.l2c.overall_accesses::cpu1.inst 22022 # number of overall (read+write) accesses 3198system.l2c.overall_accesses::cpu1.data 23515 # number of overall (read+write) accesses 3199system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16712 # number of overall (read+write) accesses 3200system.l2c.overall_accesses::total 351569 # number of overall (read+write) accesses 3201system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for ReadReq accesses 3202system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.068493 # miss rate for ReadReq accesses 3203system.l2c.ReadReq_miss_rate::cpu0.inst 0.354364 # miss rate for ReadReq accesses 3204system.l2c.ReadReq_miss_rate::cpu0.data 0.151963 # miss rate for ReadReq accesses 3205system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for ReadReq accesses 3206system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for ReadReq accesses 3207system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.029412 # miss rate for ReadReq accesses 3208system.l2c.ReadReq_miss_rate::cpu1.inst 0.238398 # miss rate for ReadReq accesses 3209system.l2c.ReadReq_miss_rate::cpu1.data 0.162672 # miss rate for ReadReq accesses 3210system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for ReadReq accesses 3211system.l2c.ReadReq_miss_rate::total 0.524083 # miss rate for ReadReq accesses 3212system.l2c.UpgradeReq_miss_rate::cpu0.data 0.766546 # miss rate for UpgradeReq accesses 3213system.l2c.UpgradeReq_miss_rate::cpu1.data 0.825160 # miss rate for UpgradeReq accesses 3214system.l2c.UpgradeReq_miss_rate::total 0.784033 # miss rate for UpgradeReq accesses 3215system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.782979 # miss rate for SCUpgradeReq accesses 3216system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.922591 # miss rate for SCUpgradeReq accesses 3217system.l2c.SCUpgradeReq_miss_rate::total 0.855387 # miss rate for SCUpgradeReq accesses 3218system.l2c.ReadExReq_miss_rate::cpu0.data 0.734722 # miss rate for ReadExReq accesses 3219system.l2c.ReadExReq_miss_rate::cpu1.data 0.788276 # miss rate for ReadExReq accesses 3220system.l2c.ReadExReq_miss_rate::total 0.756969 # miss rate for ReadExReq accesses 3221system.l2c.demand_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for demand accesses 3222system.l2c.demand_miss_rate::cpu0.itb.walker 0.068493 # miss rate for demand accesses 3223system.l2c.demand_miss_rate::cpu0.inst 0.354364 # miss rate for demand accesses 3224system.l2c.demand_miss_rate::cpu0.data 0.277019 # miss rate for demand accesses 3225system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for demand accesses 3226system.l2c.demand_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for demand accesses 3227system.l2c.demand_miss_rate::cpu1.itb.walker 0.029412 # miss rate for demand accesses 3228system.l2c.demand_miss_rate::cpu1.inst 0.238398 # miss rate for demand accesses 3229system.l2c.demand_miss_rate::cpu1.data 0.438614 # miss rate for demand accesses 3230system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for demand accesses 3231system.l2c.demand_miss_rate::total 0.540622 # miss rate for demand accesses 3232system.l2c.overall_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for overall accesses 3233system.l2c.overall_miss_rate::cpu0.itb.walker 0.068493 # miss rate for overall accesses 3234system.l2c.overall_miss_rate::cpu0.inst 0.354364 # miss rate for overall accesses 3235system.l2c.overall_miss_rate::cpu0.data 0.277019 # miss rate for overall accesses 3236system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for overall accesses 3237system.l2c.overall_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for overall accesses 3238system.l2c.overall_miss_rate::cpu1.itb.walker 0.029412 # miss rate for overall accesses 3239system.l2c.overall_miss_rate::cpu1.inst 0.238398 # miss rate for overall accesses 3240system.l2c.overall_miss_rate::cpu1.data 0.438614 # miss rate for overall accesses 3241system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for overall accesses 3242system.l2c.overall_miss_rate::total 0.540622 # miss rate for overall accesses 3243system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average ReadReq miss latency 3244system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88700 # average ReadReq miss latency 3245system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82347.523634 # average ReadReq miss latency 3246system.l2c.ReadReq_avg_miss_latency::cpu0.data 90570.700419 # average ReadReq miss latency 3247system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average ReadReq miss latency 3248system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average ReadReq miss latency 3249system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 97250 # average ReadReq miss latency 3250system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85352.952381 # average ReadReq miss latency 3251system.l2c.ReadReq_avg_miss_latency::cpu1.data 87102.240879 # average ReadReq miss latency 3252system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average ReadReq miss latency 3253system.l2c.ReadReq_avg_miss_latency::total 107468.718472 # average ReadReq miss latency 3254system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 841.724187 # average UpgradeReq miss latency 3255system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 771.552196 # average UpgradeReq miss latency 3256system.l2c.UpgradeReq_avg_miss_latency::total 819.690467 # average UpgradeReq miss latency 3257system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1467.894565 # average SCUpgradeReq miss latency 3258system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 882.677226 # average SCUpgradeReq miss latency 3259system.l2c.SCUpgradeReq_avg_miss_latency::total 1140.531609 # average SCUpgradeReq miss latency 3260system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96722.934633 # average ReadExReq miss latency 3261system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82997.704379 # average ReadExReq miss latency 3262system.l2c.ReadExReq_avg_miss_latency::total 90785.501693 # average ReadExReq miss latency 3263system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency 3264system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency 3265system.l2c.demand_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency 3266system.l2c.demand_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency 3267system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency 3268system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency 3269system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency 3270system.l2c.demand_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency 3271system.l2c.demand_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency 3272system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency 3273system.l2c.demand_avg_miss_latency::total 105809.753707 # average overall miss latency 3274system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency 3275system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency 3276system.l2c.overall_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency 3277system.l2c.overall_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency 3278system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency 3279system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency 3280system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency 3281system.l2c.overall_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency 3282system.l2c.overall_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency 3283system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency 3284system.l2c.overall_avg_miss_latency::total 105809.753707 # average overall miss latency 3285system.l2c.blocked_cycles::no_mshrs 234 # number of cycles access was blocked 3286system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3287system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked 3288system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3289system.l2c.avg_blocked_cycles::no_mshrs 117 # average number of cycles each access was blocked 3290system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3291system.l2c.fast_writes 0 # number of fast writes performed 3292system.l2c.cache_copies 0 # number of cache copies performed 3293system.l2c.writebacks::writebacks 98707 # number of writebacks 3294system.l2c.writebacks::total 98707 # number of writebacks 3295system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits 3296system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits 3297system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 3298system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 3299system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits 3300system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 3301system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 3302system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits 3303system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits 3304system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses 3305system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses 3306system.l2c.ReadReq_mshr_misses::cpu0.inst 17319 # number of ReadReq MSHR misses 3307system.l2c.ReadReq_mshr_misses::cpu0.data 8118 # number of ReadReq MSHR misses 3308system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq MSHR misses 3309system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses 3310system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 3311system.l2c.ReadReq_mshr_misses::cpu1.inst 5241 # number of ReadReq MSHR misses 3312system.l2c.ReadReq_mshr_misses::cpu1.data 2138 # number of ReadReq MSHR misses 3313system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq MSHR misses 3314system.l2c.ReadReq_mshr_misses::total 171149 # number of ReadReq MSHR misses 3315system.l2c.UpgradeReq_mshr_misses::cpu0.data 8455 # number of UpgradeReq MSHR misses 3316system.l2c.UpgradeReq_mshr_misses::cpu1.data 3870 # number of UpgradeReq MSHR misses 3317system.l2c.UpgradeReq_mshr_misses::total 12325 # number of UpgradeReq MSHR misses 3318system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 920 # number of SCUpgradeReq MSHR misses 3319system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1168 # number of SCUpgradeReq MSHR misses 3320system.l2c.SCUpgradeReq_mshr_misses::total 2088 # number of SCUpgradeReq MSHR misses 3321system.l2c.ReadExReq_mshr_misses::cpu0.data 10724 # number of ReadExReq MSHR misses 3322system.l2c.ReadExReq_mshr_misses::cpu1.data 8176 # number of ReadExReq MSHR misses 3323system.l2c.ReadExReq_mshr_misses::total 18900 # number of ReadExReq MSHR misses 3324system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses 3325system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses 3326system.l2c.demand_mshr_misses::cpu0.inst 17319 # number of demand (read+write) MSHR misses 3327system.l2c.demand_mshr_misses::cpu0.data 18842 # number of demand (read+write) MSHR misses 3328system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) MSHR misses 3329system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses 3330system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3331system.l2c.demand_mshr_misses::cpu1.inst 5241 # number of demand (read+write) MSHR misses 3332system.l2c.demand_mshr_misses::cpu1.data 10314 # number of demand (read+write) MSHR misses 3333system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) MSHR misses 3334system.l2c.demand_mshr_misses::total 190049 # number of demand (read+write) MSHR misses 3335system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses 3336system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses 3337system.l2c.overall_mshr_misses::cpu0.inst 17319 # number of overall MSHR misses 3338system.l2c.overall_mshr_misses::cpu0.data 18842 # number of overall MSHR misses 3339system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of overall MSHR misses 3340system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses 3341system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3342system.l2c.overall_mshr_misses::cpu1.inst 5241 # number of overall MSHR misses 3343system.l2c.overall_mshr_misses::cpu1.data 10314 # number of overall MSHR misses 3344system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of overall MSHR misses 3345system.l2c.overall_mshr_misses::total 190049 # number of overall MSHR misses 3346system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable 3347system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable 3348system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable 3349system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17055 # number of ReadReq MSHR uncacheable 3350system.l2c.ReadReq_mshr_uncacheable::total 38122 # number of ReadReq MSHR uncacheable 3351system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable 3352system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable 3353system.l2c.WriteReq_mshr_uncacheable::total 31055 # number of WriteReq MSHR uncacheable 3354system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses 3355system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses 3356system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses 3357system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31396 # number of overall MSHR uncacheable misses 3358system.l2c.overall_mshr_uncacheable_misses::total 69177 # number of overall MSHR uncacheable misses 3359system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of ReadReq MSHR miss cycles 3360system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 380000 # number of ReadReq MSHR miss cycles 3361system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1209530708 # number of ReadReq MSHR miss cycles 3362system.l2c.ReadReq_mshr_miss_latency::cpu0.data 633945550 # number of ReadReq MSHR miss cycles 3363system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of ReadReq MSHR miss cycles 3364system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of ReadReq MSHR miss cycles 3365system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 84250 # number of ReadReq MSHR miss cycles 3366system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 381902000 # number of ReadReq MSHR miss cycles 3367system.l2c.ReadReq_mshr_miss_latency::cpu1.data 159442409 # number of ReadReq MSHR miss cycles 3368system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of ReadReq MSHR miss cycles 3369system.l2c.ReadReq_mshr_miss_latency::total 16282699204 # number of ReadReq MSHR miss cycles 3370system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 150732427 # number of UpgradeReq MSHR miss cycles 3371system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 68800353 # number of UpgradeReq MSHR miss cycles 3372system.l2c.UpgradeReq_mshr_miss_latency::total 219532780 # number of UpgradeReq MSHR miss cycles 3373system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16443920 # number of SCUpgradeReq MSHR miss cycles 3374system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20736167 # number of SCUpgradeReq MSHR miss cycles 3375system.l2c.SCUpgradeReq_mshr_miss_latency::total 37180087 # number of SCUpgradeReq MSHR miss cycles 3376system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 905183749 # number of ReadExReq MSHR miss cycles 3377system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 576557769 # number of ReadExReq MSHR miss cycles 3378system.l2c.ReadExReq_mshr_miss_latency::total 1481741518 # number of ReadExReq MSHR miss cycles 3379system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of demand (read+write) MSHR miss cycles 3380system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 380000 # number of demand (read+write) MSHR miss cycles 3381system.l2c.demand_mshr_miss_latency::cpu0.inst 1209530708 # number of demand (read+write) MSHR miss cycles 3382system.l2c.demand_mshr_miss_latency::cpu0.data 1539129299 # number of demand (read+write) MSHR miss cycles 3383system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of demand (read+write) MSHR miss cycles 3384system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of demand (read+write) MSHR miss cycles 3385system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 84250 # number of demand (read+write) MSHR miss cycles 3386system.l2c.demand_mshr_miss_latency::cpu1.inst 381902000 # number of demand (read+write) MSHR miss cycles 3387system.l2c.demand_mshr_miss_latency::cpu1.data 736000178 # number of demand (read+write) MSHR miss cycles 3388system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of demand (read+write) MSHR miss cycles 3389system.l2c.demand_mshr_miss_latency::total 17764440722 # number of demand (read+write) MSHR miss cycles 3390system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of overall MSHR miss cycles 3391system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 380000 # number of overall MSHR miss cycles 3392system.l2c.overall_mshr_miss_latency::cpu0.inst 1209530708 # number of overall MSHR miss cycles 3393system.l2c.overall_mshr_miss_latency::cpu0.data 1539129299 # number of overall MSHR miss cycles 3394system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of overall MSHR miss cycles 3395system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of overall MSHR miss cycles 3396system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 84250 # number of overall MSHR miss cycles 3397system.l2c.overall_mshr_miss_latency::cpu1.inst 381902000 # number of overall MSHR miss cycles 3398system.l2c.overall_mshr_miss_latency::cpu1.data 736000178 # number of overall MSHR miss cycles 3399system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of overall MSHR miss cycles 3400system.l2c.overall_mshr_miss_latency::total 17764440722 # number of overall MSHR miss cycles 3401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 181479250 # number of ReadReq MSHR uncacheable cycles 3402system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3198370250 # number of ReadReq MSHR uncacheable cycles 3403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5885000 # number of ReadReq MSHR uncacheable cycles 3404system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430251250 # number of ReadReq MSHR uncacheable cycles 3405system.l2c.ReadReq_mshr_uncacheable_latency::total 5815985750 # number of ReadReq MSHR uncacheable cycles 3406system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2250411545 # number of WriteReq MSHR uncacheable cycles 3407system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2045879002 # number of WriteReq MSHR uncacheable cycles 3408system.l2c.WriteReq_mshr_uncacheable_latency::total 4296290547 # number of WriteReq MSHR uncacheable cycles 3409system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles 3410system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5448781795 # number of overall MSHR uncacheable cycles 3411system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5885000 # number of overall MSHR uncacheable cycles 3412system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4476130252 # number of overall MSHR uncacheable cycles 3413system.l2c.overall_mshr_uncacheable_latency::total 10112276297 # number of overall MSHR uncacheable cycles 3414system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for ReadReq accesses 3415system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for ReadReq accesses 3416system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for ReadReq accesses 3417system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.151963 # mshr miss rate for ReadReq accesses 3418system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for ReadReq accesses 3419system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for ReadReq accesses 3420system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for ReadReq accesses 3421system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for ReadReq accesses 3422system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.162672 # mshr miss rate for ReadReq accesses 3423system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for ReadReq accesses 3424system.l2c.ReadReq_mshr_miss_rate::total 0.524031 # mshr miss rate for ReadReq accesses 3425system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.766546 # mshr miss rate for UpgradeReq accesses 3426system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.825160 # mshr miss rate for UpgradeReq accesses 3427system.l2c.UpgradeReq_mshr_miss_rate::total 0.784033 # mshr miss rate for UpgradeReq accesses 3428system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.782979 # mshr miss rate for SCUpgradeReq accesses 3429system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.922591 # mshr miss rate for SCUpgradeReq accesses 3430system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855387 # mshr miss rate for SCUpgradeReq accesses 3431system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.734722 # mshr miss rate for ReadExReq accesses 3432system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.788276 # mshr miss rate for ReadExReq accesses 3433system.l2c.ReadExReq_mshr_miss_rate::total 0.756969 # mshr miss rate for ReadExReq accesses 3434system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for demand accesses 3435system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for demand accesses 3436system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for demand accesses 3437system.l2c.demand_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for demand accesses 3438system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for demand accesses 3439system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for demand accesses 3440system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for demand accesses 3441system.l2c.demand_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for demand accesses 3442system.l2c.demand_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for demand accesses 3443system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for demand accesses 3444system.l2c.demand_mshr_miss_rate::total 0.540574 # mshr miss rate for demand accesses 3445system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for overall accesses 3446system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for overall accesses 3447system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for overall accesses 3448system.l2c.overall_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for overall accesses 3449system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for overall accesses 3450system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for overall accesses 3451system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for overall accesses 3452system.l2c.overall_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for overall accesses 3453system.l2c.overall_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for overall accesses 3454system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for overall accesses 3455system.l2c.overall_mshr_miss_rate::total 0.540574 # mshr miss rate for overall accesses 3456system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average ReadReq mshr miss latency 3457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average ReadReq mshr miss latency 3458system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average ReadReq mshr miss latency 3459system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78091.346391 # average ReadReq mshr miss latency 3460system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average ReadReq mshr miss latency 3461system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average ReadReq mshr miss latency 3462system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average ReadReq mshr miss latency 3463system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average ReadReq mshr miss latency 3464system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74575.495323 # average ReadReq mshr miss latency 3465system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average ReadReq mshr miss latency 3466system.l2c.ReadReq_avg_mshr_miss_latency::total 95137.565536 # average ReadReq mshr miss latency 3467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17827.608161 # average UpgradeReq mshr miss latency 3468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.868992 # average UpgradeReq mshr miss latency 3469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.990264 # average UpgradeReq mshr miss latency 3470system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17873.826087 # average SCUpgradeReq mshr miss latency 3471system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17753.567637 # average SCUpgradeReq mshr miss latency 3472system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17806.555077 # average SCUpgradeReq mshr miss latency 3473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84407.287300 # average ReadExReq mshr miss latency 3474system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70518.318126 # average ReadExReq mshr miss latency 3475system.l2c.ReadExReq_avg_mshr_miss_latency::total 78399.022116 # average ReadExReq mshr miss latency 3476system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency 3477system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency 3478system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency 3479system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency 3480system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency 3481system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency 3482system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency 3483system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency 3484system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency 3485system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency 3486system.l2c.demand_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency 3487system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency 3488system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency 3489system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency 3490system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency 3491system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency 3492system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency 3493system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency 3494system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency 3495system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency 3496system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency 3497system.l2c.overall_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency 3498system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average ReadReq mshr uncacheable latency 3499system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190 # average ReadReq mshr uncacheable latency 3500system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average ReadReq mshr uncacheable latency 3501system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832 # average ReadReq mshr uncacheable latency 3502system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816 # average ReadReq mshr uncacheable latency 3503system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544 # average WriteReq mshr uncacheable latency 3504system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114 # average WriteReq mshr uncacheable latency 3505system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606 # average WriteReq mshr uncacheable latency 3506system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average overall mshr uncacheable latency 3507system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294 # average overall mshr uncacheable latency 3508system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average overall mshr uncacheable latency 3509system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647 # average overall mshr uncacheable latency 3510system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115 # average overall mshr uncacheable latency 3511system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3512system.membus.trans_dist::ReadReq 209523 # Transaction distribution 3513system.membus.trans_dist::ReadResp 209522 # Transaction distribution 3514system.membus.trans_dist::WriteReq 31055 # Transaction distribution 3515system.membus.trans_dist::WriteResp 31055 # Transaction distribution 3516system.membus.trans_dist::Writeback 134913 # Transaction distribution 3517system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 3518system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 3519system.membus.trans_dist::UpgradeReq 78034 # Transaction distribution 3520system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution 3521system.membus.trans_dist::UpgradeResp 14508 # Transaction distribution 3522system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 3523system.membus.trans_dist::ReadExReq 38508 # Transaction distribution 3524system.membus.trans_dist::ReadExResp 18805 # Transaction distribution 3525system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) 3526system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 3527system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14300 # Packet count per connected master and slave (bytes) 3528system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648289 # Packet count per connected master and slave (bytes) 3529system.membus.pkt_count_system.l2c.mem_side::total 770541 # Packet count per connected master and slave (bytes) 3530system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) 3531system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) 3532system.membus.pkt_count::total 879462 # Packet count per connected master and slave (bytes) 3533system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) 3534system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 3535system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28600 # Cumulative packet size per connected master and slave (bytes) 3536system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18522228 # Cumulative packet size per connected master and slave (bytes) 3537system.membus.pkt_size_system.l2c.mem_side::total 18713941 # Cumulative packet size per connected master and slave (bytes) 3538system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) 3539system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) 3540system.membus.pkt_size::total 23350421 # Cumulative packet size per connected master and slave (bytes) 3541system.membus.snoops 125464 # Total snoops (count) 3542system.membus.snoop_fanout::samples 569969 # Request fanout histogram 3543system.membus.snoop_fanout::mean 1 # Request fanout histogram 3544system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3545system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3546system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3547system.membus.snoop_fanout::1 569969 100.00% 100.00% # Request fanout histogram 3548system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3549system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3550system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3551system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3552system.membus.snoop_fanout::total 569969 # Request fanout histogram 3553system.membus.reqLayer0.occupancy 81685500 # Layer occupancy (ticks) 3554system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3555system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks) 3556system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3557system.membus.reqLayer2.occupancy 12047488 # Layer occupancy (ticks) 3558system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3559system.membus.reqLayer5.occupancy 1135057072 # Layer occupancy (ticks) 3560system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3561system.membus.respLayer2.occupancy 1127535962 # Layer occupancy (ticks) 3562system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3563system.membus.respLayer3.occupancy 37496988 # Layer occupancy (ticks) 3564system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3565system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3566system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3567system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3568system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3569system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3570system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3571system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3572system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3573system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3574system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3575system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3576system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3577system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3578system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3579system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3580system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3581system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3582system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3583system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3584system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3585system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3586system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3587system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3588system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3589system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3590system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3591system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3592system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3593system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3594system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3595system.realview.ethernet.droppedPackets 0 # number of packets dropped 3596system.toL2Bus.trans_dist::ReadReq 490298 # Transaction distribution 3597system.toL2Bus.trans_dist::ReadResp 490282 # Transaction distribution 3598system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution 3599system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution 3600system.toL2Bus.trans_dist::Writeback 227479 # Transaction distribution 3601system.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution 3602system.toL2Bus.trans_dist::UpgradeReq 81334 # Transaction distribution 3603system.toL2Bus.trans_dist::SCUpgradeReq 42004 # Transaction distribution 3604system.toL2Bus.trans_dist::UpgradeResp 123338 # Transaction distribution 3605system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution 3606system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution 3607system.toL2Bus.trans_dist::ReadExReq 50269 # Transaction distribution 3608system.toL2Bus.trans_dist::ReadExResp 50269 # Transaction distribution 3609system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 990291 # Packet count per connected master and slave (bytes) 3610system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 371073 # Packet count per connected master and slave (bytes) 3611system.toL2Bus.pkt_count::total 1361364 # Packet count per connected master and slave (bytes) 3612system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 30980096 # Cumulative packet size per connected master and slave (bytes) 3613system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6355093 # Cumulative packet size per connected master and slave (bytes) 3614system.toL2Bus.pkt_size::total 37335189 # Cumulative packet size per connected master and slave (bytes) 3615system.toL2Bus.snoops 292587 # Total snoops (count) 3616system.toL2Bus.snoop_fanout::samples 958737 # Request fanout histogram 3617system.toL2Bus.snoop_fanout::mean 1.038087 # Request fanout histogram 3618system.toL2Bus.snoop_fanout::stdev 0.191405 # Request fanout histogram 3619system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3620system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3621system.toL2Bus.snoop_fanout::1 922222 96.19% 96.19% # Request fanout histogram 3622system.toL2Bus.snoop_fanout::2 36515 3.81% 100.00% # Request fanout histogram 3623system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3624system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3625system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3626system.toL2Bus.snoop_fanout::total 958737 # Request fanout histogram 3627system.toL2Bus.reqLayer0.occupancy 763418418 # Layer occupancy (ticks) 3628system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3629system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) 3630system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3631system.toL2Bus.respLayer0.occupancy 618495385 # Layer occupancy (ticks) 3632system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3633system.toL2Bus.respLayer1.occupancy 276060555 # Layer occupancy (ticks) 3634system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3635system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3636system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed 3637system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3638system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed 3639 3640---------- End Simulation Statistics ---------- 3641