stats.txt revision 10517:ba51f8572571
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.824341 # Number of seconds simulated 4sim_ticks 2824340874000 # Number of ticks simulated 5final_tick 2824340874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 96866 # Simulator instruction rate (inst/s) 8host_op_rate 117519 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2277239721 # Simulator tick rate (ticks/s) 10host_mem_usage 609056 # Number of bytes of host memory used 11host_seconds 1240.25 # Real time elapsed on the host 12sim_insts 120137719 # Number of instructions simulated 13sim_ops 145752951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 286816 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1046908 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 10513536 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 549344 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 1344384 # Number of bytes read from this memory 27system.physmem.bytes_read::total 13777356 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 286816 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 318768 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 7262336 # Number of bytes written to this memory 32system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 35system.physmem.bytes_written::total 9598416 # Number of bytes written to this memory 36system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.inst 6727 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.data 16883 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu0.l2cache.prefetcher 164274 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.data 8607 # Number of read requests responded to by this memory 46system.physmem.num_reads::cpu1.l2cache.prefetcher 21006 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 218132 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 113474 # Number of write requests responded to by this memory 49system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 51system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 52system.physmem.num_writes::total 154134 # Number of write requests responded to by this memory 53system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.itb.walker 181 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.inst 101551 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.data 370673 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu0.l2cache.prefetcher 3722474 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.inst 11313 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.data 194503 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu1.l2cache.prefetcher 475999 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 4878078 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 101551 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 11313 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 112865 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2571338 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::realview.ide 820841 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 72system.physmem.bw_write::total 3398462 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2571338 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 821181 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.inst 101551 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.data 376942 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.l2cache.prefetcher 3722474 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.inst 11313 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.data 194518 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.l2cache.prefetcher 475999 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 8276541 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 218132 # Number of read requests accepted 87system.physmem.writeReqs 154134 # Number of write requests accepted 88system.physmem.readBursts 218132 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 154134 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13944832 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue 92system.physmem.bytesWritten 9612032 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 13777356 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 9598416 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue 96system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one 97system.physmem.neitherReadNorWriteReqs 13729 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 13731 # Per bank write bursts 99system.physmem.perBankRdBursts::1 13637 # Per bank write bursts 100system.physmem.perBankRdBursts::2 14382 # Per bank write bursts 101system.physmem.perBankRdBursts::3 14282 # Per bank write bursts 102system.physmem.perBankRdBursts::4 15946 # Per bank write bursts 103system.physmem.perBankRdBursts::5 13017 # Per bank write bursts 104system.physmem.perBankRdBursts::6 13909 # Per bank write bursts 105system.physmem.perBankRdBursts::7 13917 # Per bank write bursts 106system.physmem.perBankRdBursts::8 13612 # Per bank write bursts 107system.physmem.perBankRdBursts::9 13371 # Per bank write bursts 108system.physmem.perBankRdBursts::10 12787 # Per bank write bursts 109system.physmem.perBankRdBursts::11 11726 # Per bank write bursts 110system.physmem.perBankRdBursts::12 13349 # Per bank write bursts 111system.physmem.perBankRdBursts::13 14174 # Per bank write bursts 112system.physmem.perBankRdBursts::14 13344 # Per bank write bursts 113system.physmem.perBankRdBursts::15 12704 # Per bank write bursts 114system.physmem.perBankWrBursts::0 9692 # Per bank write bursts 115system.physmem.perBankWrBursts::1 9790 # Per bank write bursts 116system.physmem.perBankWrBursts::2 10299 # Per bank write bursts 117system.physmem.perBankWrBursts::3 9942 # Per bank write bursts 118system.physmem.perBankWrBursts::4 9060 # Per bank write bursts 119system.physmem.perBankWrBursts::5 9040 # Per bank write bursts 120system.physmem.perBankWrBursts::6 9465 # Per bank write bursts 121system.physmem.perBankWrBursts::7 9428 # Per bank write bursts 122system.physmem.perBankWrBursts::8 9418 # Per bank write bursts 123system.physmem.perBankWrBursts::9 9301 # Per bank write bursts 124system.physmem.perBankWrBursts::10 9150 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8663 # Per bank write bursts 126system.physmem.perBankWrBursts::12 9463 # Per bank write bursts 127system.physmem.perBankWrBursts::13 9594 # Per bank write bursts 128system.physmem.perBankWrBursts::14 9165 # Per bank write bursts 129system.physmem.perBankWrBursts::15 8718 # Per bank write bursts 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 131system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 132system.physmem.totGap 2824339295000 # Total gap between requests 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 559 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 3083 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) 139system.physmem.readPktSize::6 214462 # Read request sizes (log2) 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) 146system.physmem.writePktSize::6 149698 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 53523 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 76682 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 20695 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 15255 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 11067 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 9733 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 8849 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 8196 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 7196 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 2474 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 1465 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 1103 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 647 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 481 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 305 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 208 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 179system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::15 2920 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3538 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4134 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 5600 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 6932 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7778 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8822 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9717 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10984 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 10866 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 10869 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 10841 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 11416 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 9280 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 9219 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 8573 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 815 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 368 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 234 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 92801 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 253.842782 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 143.815283 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 308.388546 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 46919 50.56% 50.56% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 18870 20.33% 70.89% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6768 7.29% 78.19% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3705 3.99% 82.18% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3168 3.41% 85.59% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 2103 2.27% 87.86% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1242 1.34% 89.20% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1089 1.17% 90.37% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 92801 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 7531 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 28.931483 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 528.461754 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 7530 99.99% 99.99% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 7531 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 7531 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 19.942637 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.618581 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 11.035986 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 6139 81.52% 81.52% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 568 7.54% 89.06% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 91 1.21% 90.27% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 228 3.03% 93.29% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 184 2.44% 95.74% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 18 0.24% 95.98% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 26 0.35% 96.32% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 11 0.15% 96.47% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 33 0.44% 96.91% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 5 0.07% 96.97% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 10 0.13% 97.11% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 1 0.01% 97.12% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 156 2.07% 99.19% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 9 0.12% 99.31% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 1 0.01% 99.38% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 13 0.17% 99.55% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::88-91 3 0.04% 99.60% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 4 0.05% 99.65% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 1 0.01% 99.67% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 2 0.03% 99.73% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 4 0.05% 99.79% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 4 0.05% 99.84% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 6 0.08% 99.95% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::136-139 2 0.03% 99.97% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 7531 # Writes before turning the bus around for reads 299system.physmem.totQLat 8907181250 # Total ticks spent queuing 300system.physmem.totMemAccLat 12992581250 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 1089440000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 40879.63 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 59629.63 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 3.40 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.07 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 21.20 # Average write queue length when enqueuing 315system.physmem.readRowHits 185267 # Number of row buffer hits during reads 316system.physmem.writeRowHits 90008 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 85.03 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 59.92 # Row buffer hit rate for writes 319system.physmem.avgGap 7586884.90 # Average gap between requests 320system.physmem.pageHitRate 74.78 # Row buffer hit rate, read and write combined 321system.physmem.memoryStateTime::IDLE 2697410352000 # Time in different power states 322system.physmem.memoryStateTime::REF 94310840000 # Time in different power states 323system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 324system.physmem.memoryStateTime::ACT 32616675500 # Time in different power states 325system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 326system.physmem.actEnergy::0 364754880 # Energy for activate commands per rank (pJ) 327system.physmem.actEnergy::1 336820680 # Energy for activate commands per rank (pJ) 328system.physmem.preEnergy::0 199023000 # Energy for precharge commands per rank (pJ) 329system.physmem.preEnergy::1 183781125 # Energy for precharge commands per rank (pJ) 330system.physmem.readEnergy::0 880003800 # Energy for read commands per rank (pJ) 331system.physmem.readEnergy::1 819522600 # Energy for read commands per rank (pJ) 332system.physmem.writeEnergy::0 497119680 # Energy for write commands per rank (pJ) 333system.physmem.writeEnergy::1 476098560 # Energy for write commands per rank (pJ) 334system.physmem.refreshEnergy::0 184472003040 # Energy for refresh commands per rank (pJ) 335system.physmem.refreshEnergy::1 184472003040 # Energy for refresh commands per rank (pJ) 336system.physmem.actBackEnergy::0 78880301865 # Energy for active background per rank (pJ) 337system.physmem.actBackEnergy::1 78435436815 # Energy for active background per rank (pJ) 338system.physmem.preBackEnergy::0 1625409465000 # Energy for precharge background per rank (pJ) 339system.physmem.preBackEnergy::1 1625799697500 # Energy for precharge background per rank (pJ) 340system.physmem.totalEnergy::0 1890702671265 # Total energy per rank (pJ) 341system.physmem.totalEnergy::1 1890523360320 # Total energy per rank (pJ) 342system.physmem.averagePower::0 669.432189 # Core power per rank (mW) 343system.physmem.averagePower::1 669.368701 # Core power per rank (mW) 344system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory 350system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 351system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 353system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) 362system.membus.trans_dist::ReadReq 237823 # Transaction distribution 363system.membus.trans_dist::ReadResp 237823 # Transaction distribution 364system.membus.trans_dist::WriteReq 30977 # Transaction distribution 365system.membus.trans_dist::WriteResp 30977 # Transaction distribution 366system.membus.trans_dist::Writeback 113474 # Transaction distribution 367system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 368system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 369system.membus.trans_dist::UpgradeReq 79489 # Transaction distribution 370system.membus.trans_dist::SCUpgradeReq 40661 # Transaction distribution 371system.membus.trans_dist::UpgradeResp 13729 # Transaction distribution 372system.membus.trans_dist::ReadExReq 31194 # Transaction distribution 373system.membus.trans_dist::ReadExResp 14874 # Transaction distribution 374system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) 375system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 376system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13738 # Packet count per connected master and slave (bytes) 377system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708779 # Packet count per connected master and slave (bytes) 378system.membus.pkt_count_system.l2c.mem_side::total 830527 # Packet count per connected master and slave (bytes) 379system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) 380system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) 381system.membus.pkt_count::total 903237 # Packet count per connected master and slave (bytes) 382system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) 383system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) 384system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27476 # Cumulative packet size per connected master and slave (bytes) 385system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21056476 # Cumulative packet size per connected master and slave (bytes) 386system.membus.pkt_size_system.l2c.mem_side::total 21247122 # Cumulative packet size per connected master and slave (bytes) 387system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 388system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 389system.membus.pkt_size::total 23566418 # Cumulative packet size per connected master and slave (bytes) 390system.membus.snoops 122973 # Total snoops (count) 391system.membus.snoop_fanout::samples 500866 # Request fanout histogram 392system.membus.snoop_fanout::mean 1 # Request fanout histogram 393system.membus.snoop_fanout::stdev 0 # Request fanout histogram 394system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 395system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 396system.membus.snoop_fanout::1 500866 100.00% 100.00% # Request fanout histogram 397system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 398system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 399system.membus.snoop_fanout::min_value 1 # Request fanout histogram 400system.membus.snoop_fanout::max_value 1 # Request fanout histogram 401system.membus.snoop_fanout::total 500866 # Request fanout histogram 402system.membus.reqLayer0.occupancy 81235490 # Layer occupancy (ticks) 403system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 404system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) 405system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 406system.membus.reqLayer2.occupancy 11626497 # Layer occupancy (ticks) 407system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 408system.membus.reqLayer5.occupancy 1642596998 # Layer occupancy (ticks) 409system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 410system.membus.respLayer2.occupancy 2113984385 # Layer occupancy (ticks) 411system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 412system.membus.respLayer3.occupancy 38546403 # Layer occupancy (ticks) 413system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 414system.cpu_clk_domain.clock 500 # Clock period in ticks 415system.l2c.tags.replacements 153419 # number of replacements 416system.l2c.tags.tagsinuse 64440.075057 # Cycle average of tags in use 417system.l2c.tags.total_refs 521049 # Total number of references to valid blocks. 418system.l2c.tags.sampled_refs 218085 # Sample count of references to valid blocks. 419system.l2c.tags.avg_refs 2.389201 # Average number of references to valid blocks. 420system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 421system.l2c.tags.occ_blocks::writebacks 14106.989110 # Average occupied blocks per requestor 422system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.481706 # Average occupied blocks per requestor 423system.l2c.tags.occ_blocks::cpu0.itb.walker 2.879098 # Average occupied blocks per requestor 424system.l2c.tags.occ_blocks::cpu0.inst 1413.448081 # Average occupied blocks per requestor 425system.l2c.tags.occ_blocks::cpu0.data 2144.570039 # Average occupied blocks per requestor 426system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39278.457251 # Average occupied blocks per requestor 427system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.502209 # Average occupied blocks per requestor 428system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002709 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu1.inst 292.869735 # Average occupied blocks per requestor 430system.l2c.tags.occ_blocks::cpu1.data 885.757521 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6295.117598 # Average occupied blocks per requestor 432system.l2c.tags.occ_percent::writebacks 0.215256 # Average percentage of cache occupancy 433system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy 434system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy 435system.l2c.tags.occ_percent::cpu0.inst 0.021568 # Average percentage of cache occupancy 436system.l2c.tags.occ_percent::cpu0.data 0.032724 # Average percentage of cache occupancy 437system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599342 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy 439system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 440system.l2c.tags.occ_percent::cpu1.inst 0.004469 # Average percentage of cache occupancy 441system.l2c.tags.occ_percent::cpu1.data 0.013516 # Average percentage of cache occupancy 442system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096056 # Average percentage of cache occupancy 443system.l2c.tags.occ_percent::total 0.983278 # Average percentage of cache occupancy 444system.l2c.tags.occ_task_id_blocks::1022 44367 # Occupied blocks per task id 445system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 446system.l2c.tags.occ_task_id_blocks::1024 20280 # Occupied blocks per task id 447system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id 448system.l2c.tags.age_task_id_blocks_1022::3 7792 # Occupied blocks per task id 449system.l2c.tags.age_task_id_blocks_1022::4 36164 # Occupied blocks per task id 450system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 451system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 452system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 453system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 454system.l2c.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id 455system.l2c.tags.age_task_id_blocks_1024::3 4621 # Occupied blocks per task id 456system.l2c.tags.age_task_id_blocks_1024::4 15296 # Occupied blocks per task id 457system.l2c.tags.occ_task_id_percent::1022 0.676987 # Percentage of cache occupancy per task id 458system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id 459system.l2c.tags.occ_task_id_percent::1024 0.309448 # Percentage of cache occupancy per task id 460system.l2c.tags.tag_accesses 6602520 # Number of tag accesses 461system.l2c.tags.data_accesses 6602520 # Number of data accesses 462system.l2c.ReadReq_hits::cpu0.dtb.walker 282 # number of ReadReq hits 463system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits 464system.l2c.ReadReq_hits::cpu0.inst 12559 # number of ReadReq hits 465system.l2c.ReadReq_hits::cpu0.data 39006 # number of ReadReq hits 466system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182592 # number of ReadReq hits 467system.l2c.ReadReq_hits::cpu1.dtb.walker 97 # number of ReadReq hits 468system.l2c.ReadReq_hits::cpu1.itb.walker 55 # number of ReadReq hits 469system.l2c.ReadReq_hits::cpu1.inst 4109 # number of ReadReq hits 470system.l2c.ReadReq_hits::cpu1.data 11553 # number of ReadReq hits 471system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44326 # number of ReadReq hits 472system.l2c.ReadReq_hits::total 294701 # number of ReadReq hits 473system.l2c.Writeback_hits::writebacks 252802 # number of Writeback hits 474system.l2c.Writeback_hits::total 252802 # number of Writeback hits 475system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits 476system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits 477system.l2c.UpgradeReq_hits::total 12432 # number of UpgradeReq hits 478system.l2c.SCUpgradeReq_hits::cpu0.data 184 # number of SCUpgradeReq hits 479system.l2c.SCUpgradeReq_hits::cpu1.data 173 # number of SCUpgradeReq hits 480system.l2c.SCUpgradeReq_hits::total 357 # number of SCUpgradeReq hits 481system.l2c.ReadExReq_hits::cpu0.data 3642 # number of ReadExReq hits 482system.l2c.ReadExReq_hits::cpu1.data 1229 # number of ReadExReq hits 483system.l2c.ReadExReq_hits::total 4871 # number of ReadExReq hits 484system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits 485system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits 486system.l2c.demand_hits::cpu0.inst 12559 # number of demand (read+write) hits 487system.l2c.demand_hits::cpu0.data 42648 # number of demand (read+write) hits 488system.l2c.demand_hits::cpu0.l2cache.prefetcher 182592 # number of demand (read+write) hits 489system.l2c.demand_hits::cpu1.dtb.walker 97 # number of demand (read+write) hits 490system.l2c.demand_hits::cpu1.itb.walker 55 # number of demand (read+write) hits 491system.l2c.demand_hits::cpu1.inst 4109 # number of demand (read+write) hits 492system.l2c.demand_hits::cpu1.data 12782 # number of demand (read+write) hits 493system.l2c.demand_hits::cpu1.l2cache.prefetcher 44326 # number of demand (read+write) hits 494system.l2c.demand_hits::total 299572 # number of demand (read+write) hits 495system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits 496system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits 497system.l2c.overall_hits::cpu0.inst 12559 # number of overall hits 498system.l2c.overall_hits::cpu0.data 42648 # number of overall hits 499system.l2c.overall_hits::cpu0.l2cache.prefetcher 182592 # number of overall hits 500system.l2c.overall_hits::cpu1.dtb.walker 97 # number of overall hits 501system.l2c.overall_hits::cpu1.itb.walker 55 # number of overall hits 502system.l2c.overall_hits::cpu1.inst 4109 # number of overall hits 503system.l2c.overall_hits::cpu1.data 12782 # number of overall hits 504system.l2c.overall_hits::cpu1.l2cache.prefetcher 44326 # number of overall hits 505system.l2c.overall_hits::total 299572 # number of overall hits 506system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses 507system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses 508system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses 509system.l2c.ReadReq_misses::cpu0.data 8647 # number of ReadReq misses 510system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164277 # number of ReadReq misses 511system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses 512system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses 513system.l2c.ReadReq_misses::cpu1.inst 479 # number of ReadReq misses 514system.l2c.ReadReq_misses::cpu1.data 1383 # number of ReadReq misses 515system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21024 # number of ReadReq misses 516system.l2c.ReadReq_misses::total 199597 # number of ReadReq misses 517system.l2c.UpgradeReq_misses::cpu0.data 8851 # number of UpgradeReq misses 518system.l2c.UpgradeReq_misses::cpu1.data 2828 # number of UpgradeReq misses 519system.l2c.UpgradeReq_misses::total 11679 # number of UpgradeReq misses 520system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses 521system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses 522system.l2c.SCUpgradeReq_misses::total 1952 # number of SCUpgradeReq misses 523system.l2c.ReadExReq_misses::cpu0.data 7757 # number of ReadExReq misses 524system.l2c.ReadExReq_misses::cpu1.data 7215 # number of ReadExReq misses 525system.l2c.ReadExReq_misses::total 14972 # number of ReadExReq misses 526system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses 527system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses 528system.l2c.demand_misses::cpu0.inst 3733 # number of demand (read+write) misses 529system.l2c.demand_misses::cpu0.data 16404 # number of demand (read+write) misses 530system.l2c.demand_misses::cpu0.l2cache.prefetcher 164277 # number of demand (read+write) misses 531system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 532system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses 533system.l2c.demand_misses::cpu1.inst 479 # number of demand (read+write) misses 534system.l2c.demand_misses::cpu1.data 8598 # number of demand (read+write) misses 535system.l2c.demand_misses::cpu1.l2cache.prefetcher 21024 # number of demand (read+write) misses 536system.l2c.demand_misses::total 214569 # number of demand (read+write) misses 537system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses 538system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses 539system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses 540system.l2c.overall_misses::cpu0.data 16404 # number of overall misses 541system.l2c.overall_misses::cpu0.l2cache.prefetcher 164277 # number of overall misses 542system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 543system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses 544system.l2c.overall_misses::cpu1.inst 479 # number of overall misses 545system.l2c.overall_misses::cpu1.data 8598 # number of overall misses 546system.l2c.overall_misses::cpu1.l2cache.prefetcher 21024 # number of overall misses 547system.l2c.overall_misses::total 214569 # number of overall misses 548system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2727250 # number of ReadReq miss cycles 549system.l2c.ReadReq_miss_latency::cpu0.itb.walker 613750 # number of ReadReq miss cycles 550system.l2c.ReadReq_miss_latency::cpu0.inst 350075996 # number of ReadReq miss cycles 551system.l2c.ReadReq_miss_latency::cpu0.data 761569744 # number of ReadReq miss cycles 552system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of ReadReq miss cycles 553system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 768250 # number of ReadReq miss cycles 554system.l2c.ReadReq_miss_latency::cpu1.itb.walker 150000 # number of ReadReq miss cycles 555system.l2c.ReadReq_miss_latency::cpu1.inst 47537750 # number of ReadReq miss cycles 556system.l2c.ReadReq_miss_latency::cpu1.data 122331750 # number of ReadReq miss cycles 557system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of ReadReq miss cycles 558system.l2c.ReadReq_miss_latency::total 22797831231 # number of ReadReq miss cycles 559system.l2c.UpgradeReq_miss_latency::cpu0.data 6376742 # number of UpgradeReq miss cycles 560system.l2c.UpgradeReq_miss_latency::cpu1.data 2877882 # number of UpgradeReq miss cycles 561system.l2c.UpgradeReq_miss_latency::total 9254624 # number of UpgradeReq miss cycles 562system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147452 # number of SCUpgradeReq miss cycles 563system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1135953 # number of SCUpgradeReq miss cycles 564system.l2c.SCUpgradeReq_miss_latency::total 2283405 # number of SCUpgradeReq miss cycles 565system.l2c.ReadExReq_miss_latency::cpu0.data 711214419 # number of ReadExReq miss cycles 566system.l2c.ReadExReq_miss_latency::cpu1.data 562948982 # number of ReadExReq miss cycles 567system.l2c.ReadExReq_miss_latency::total 1274163401 # number of ReadExReq miss cycles 568system.l2c.demand_miss_latency::cpu0.dtb.walker 2727250 # number of demand (read+write) miss cycles 569system.l2c.demand_miss_latency::cpu0.itb.walker 613750 # number of demand (read+write) miss cycles 570system.l2c.demand_miss_latency::cpu0.inst 350075996 # number of demand (read+write) miss cycles 571system.l2c.demand_miss_latency::cpu0.data 1472784163 # number of demand (read+write) miss cycles 572system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of demand (read+write) miss cycles 573system.l2c.demand_miss_latency::cpu1.dtb.walker 768250 # number of demand (read+write) miss cycles 574system.l2c.demand_miss_latency::cpu1.itb.walker 150000 # number of demand (read+write) miss cycles 575system.l2c.demand_miss_latency::cpu1.inst 47537750 # number of demand (read+write) miss cycles 576system.l2c.demand_miss_latency::cpu1.data 685280732 # number of demand (read+write) miss cycles 577system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of demand (read+write) miss cycles 578system.l2c.demand_miss_latency::total 24071994632 # number of demand (read+write) miss cycles 579system.l2c.overall_miss_latency::cpu0.dtb.walker 2727250 # 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number of ReadReq accesses(hits+misses) 591system.l2c.ReadReq_accesses::cpu0.itb.walker 130 # number of ReadReq accesses(hits+misses) 592system.l2c.ReadReq_accesses::cpu0.inst 16292 # number of ReadReq accesses(hits+misses) 593system.l2c.ReadReq_accesses::cpu0.data 47653 # number of ReadReq accesses(hits+misses) 594system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346869 # number of ReadReq accesses(hits+misses) 595system.l2c.ReadReq_accesses::cpu1.dtb.walker 107 # number of ReadReq accesses(hits+misses) 596system.l2c.ReadReq_accesses::cpu1.itb.walker 57 # number of ReadReq accesses(hits+misses) 597system.l2c.ReadReq_accesses::cpu1.inst 4588 # number of ReadReq accesses(hits+misses) 598system.l2c.ReadReq_accesses::cpu1.data 12936 # number of ReadReq accesses(hits+misses) 599system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65350 # number of ReadReq accesses(hits+misses) 600system.l2c.ReadReq_accesses::total 494298 # number of ReadReq accesses(hits+misses) 601system.l2c.Writeback_accesses::writebacks 252802 # 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miss rate for demand accesses 659system.l2c.demand_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for demand accesses 660system.l2c.demand_miss_rate::cpu1.itb.walker 0.035088 # miss rate for demand accesses 661system.l2c.demand_miss_rate::cpu1.inst 0.104403 # miss rate for demand accesses 662system.l2c.demand_miss_rate::cpu1.data 0.402152 # miss rate for demand accesses 663system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for demand accesses 664system.l2c.demand_miss_rate::total 0.417335 # miss rate for demand accesses 665system.l2c.overall_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for overall accesses 666system.l2c.overall_miss_rate::cpu0.itb.walker 0.061538 # miss rate for overall accesses 667system.l2c.overall_miss_rate::cpu0.inst 0.229131 # miss rate for overall accesses 668system.l2c.overall_miss_rate::cpu0.data 0.277789 # miss rate for overall accesses 669system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for overall accesses 670system.l2c.overall_miss_rate::cpu1.dtb.walker 0.093458 # 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number of ReadReq MSHR miss cycles 787system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 303960496 # number of ReadReq MSHR miss cycles 788system.l2c.ReadReq_mshr_miss_latency::cpu0.data 654157744 # number of ReadReq MSHR miss cycles 789system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of ReadReq MSHR miss cycles 790system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 643750 # number of ReadReq MSHR miss cycles 791system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 125000 # number of ReadReq MSHR miss cycles 792system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 41455250 # number of ReadReq MSHR miss cycles 793system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105134250 # number of ReadReq MSHR miss cycles 794system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of ReadReq MSHR miss cycles 795system.l2c.ReadReq_mshr_miss_latency::total 20343291231 # number of ReadReq MSHR miss cycles 796system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 89616766 # number of UpgradeReq MSHR miss cycles 797system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28576308 # number of UpgradeReq MSHR miss cycles 798system.l2c.UpgradeReq_mshr_miss_latency::total 118193074 # number of UpgradeReq MSHR miss cycles 799system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7674203 # number of SCUpgradeReq MSHR miss cycles 800system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12103692 # number of SCUpgradeReq MSHR miss cycles 801system.l2c.SCUpgradeReq_mshr_miss_latency::total 19777895 # number of SCUpgradeReq MSHR miss cycles 802system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 615195579 # number of ReadExReq MSHR miss cycles 803system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 471924516 # number of ReadExReq MSHR miss cycles 804system.l2c.ReadExReq_mshr_miss_latency::total 1087120095 # number of ReadExReq MSHR miss cycles 805system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of demand (read+write) MSHR miss cycles 806system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 513750 # number of demand (read+write) MSHR miss cycles 807system.l2c.demand_mshr_miss_latency::cpu0.inst 303960496 # number of demand (read+write) MSHR miss cycles 808system.l2c.demand_mshr_miss_latency::cpu0.data 1269353323 # number of demand (read+write) MSHR miss cycles 809system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of demand (read+write) MSHR miss cycles 810system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 643750 # number of demand (read+write) MSHR miss cycles 811system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 812system.l2c.demand_mshr_miss_latency::cpu1.inst 41455250 # number of demand (read+write) MSHR miss cycles 813system.l2c.demand_mshr_miss_latency::cpu1.data 577058766 # number of demand (read+write) MSHR miss cycles 814system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of demand (read+write) MSHR miss cycles 815system.l2c.demand_mshr_miss_latency::total 21430411326 # number of demand (read+write) MSHR miss cycles 816system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles 817system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 513750 # number of overall MSHR miss cycles 818system.l2c.overall_mshr_miss_latency::cpu0.inst 303960496 # number of overall MSHR miss cycles 819system.l2c.overall_mshr_miss_latency::cpu0.data 1269353323 # number of overall MSHR miss cycles 820system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of overall MSHR miss cycles 821system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 643750 # number of overall MSHR miss cycles 822system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 125000 # number of overall MSHR miss cycles 823system.l2c.overall_mshr_miss_latency::cpu1.inst 41455250 # number of overall MSHR miss cycles 824system.l2c.overall_mshr_miss_latency::cpu1.data 577058766 # number of overall MSHR miss cycles 825system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of overall MSHR miss cycles 826system.l2c.overall_mshr_miss_latency::total 21430411326 # number of overall MSHR miss cycles 827system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles 828system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686341747 # number of ReadReq MSHR uncacheable cycles 829system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles 830system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919844500 # number of ReadReq MSHR uncacheable cycles 831system.l2c.ReadReq_mshr_uncacheable_latency::total 5770618747 # number of ReadReq MSHR uncacheable cycles 832system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713885499 # number of WriteReq MSHR uncacheable cycles 833system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535420500 # number of WriteReq MSHR uncacheable cycles 834system.l2c.WriteReq_mshr_uncacheable_latency::total 4249305999 # number of WriteReq MSHR uncacheable cycles 835system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles 836system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400227246 # number of overall MSHR uncacheable cycles 837system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles 838system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455265000 # number of overall MSHR uncacheable cycles 839system.l2c.overall_mshr_uncacheable_latency::total 10019924746 # number of overall MSHR uncacheable cycles 840system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for ReadReq accesses 841system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for ReadReq accesses 842system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for ReadReq accesses 843system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181437 # mshr miss rate for ReadReq accesses 844system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for ReadReq accesses 845system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for ReadReq accesses 846system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for ReadReq accesses 847system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for ReadReq accesses 848system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.106911 # mshr miss rate for ReadReq accesses 849system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for ReadReq accesses 850system.l2c.ReadReq_mshr_miss_rate::total 0.403750 # mshr miss rate for ReadReq accesses 851system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430580 # mshr miss rate for UpgradeReq accesses 852system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795499 # mshr miss rate for UpgradeReq accesses 853system.l2c.UpgradeReq_mshr_miss_rate::total 0.484385 # mshr miss rate for UpgradeReq accesses 854system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.802787 # mshr miss rate for SCUpgradeReq accesses 855system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.874273 # mshr miss rate for SCUpgradeReq accesses 856system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845388 # mshr miss rate for SCUpgradeReq accesses 857system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.680498 # mshr miss rate for ReadExReq accesses 858system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854453 # mshr miss rate for ReadExReq accesses 859system.l2c.ReadExReq_mshr_miss_rate::total 0.754523 # mshr miss rate for ReadExReq accesses 860system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for demand accesses 861system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for demand accesses 862system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for demand accesses 863system.l2c.demand_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for demand accesses 864system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for demand accesses 865system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for demand accesses 866system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for demand accesses 867system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for demand accesses 868system.l2c.demand_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for demand accesses 869system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for demand accesses 870system.l2c.demand_mshr_miss_rate::total 0.417288 # mshr miss rate for demand accesses 871system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for overall accesses 872system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for overall accesses 873system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for overall accesses 874system.l2c.overall_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for overall accesses 875system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for overall accesses 876system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for overall accesses 877system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for overall accesses 878system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for overall accesses 879system.l2c.overall_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for overall accesses 880system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for overall accesses 881system.l2c.overall_mshr_miss_rate::total 0.417288 # mshr miss rate for overall accesses 882system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency 883system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average ReadReq mshr miss latency 884system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average ReadReq mshr miss latency 885system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75660.160074 # average ReadReq mshr miss latency 886system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average ReadReq mshr miss latency 887system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average ReadReq mshr miss latency 888system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 889system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average ReadReq mshr miss latency 890system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76018.980477 # average ReadReq mshr miss latency 891system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average ReadReq mshr miss latency 892system.l2c.ReadReq_avg_mshr_miss_latency::total 101934.085427 # average ReadReq mshr miss latency 893system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10125.044176 # average UpgradeReq mshr miss latency 894system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.776521 # average UpgradeReq mshr miss latency 895system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.136484 # average UpgradeReq mshr miss latency 896system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10245.931909 # average SCUpgradeReq mshr miss latency 897system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10061.256858 # average SCUpgradeReq mshr miss latency 898system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10132.118340 # average SCUpgradeReq mshr miss latency 899system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79308.441279 # average ReadExReq mshr miss latency 900system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65408.803326 # average ReadExReq mshr miss latency 901system.l2c.ReadExReq_avg_mshr_miss_latency::total 72610.212063 # average ReadExReq mshr miss latency 902system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency 903system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency 904system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency 905system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency 906system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency 907system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency 908system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 909system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency 910system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency 911system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency 912system.l2c.demand_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency 913system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency 914system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency 915system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency 916system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency 917system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency 918system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency 919system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 920system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency 921system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency 922system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency 923system.l2c.overall_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency 924system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 925system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 926system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 927system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 928system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 929system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 930system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 931system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 933system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 934system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 935system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 936system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 937system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 938system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 939system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 940system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 941system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 942system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 943system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 944system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 945system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 946system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 947system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 948system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 949system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 950system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 951system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 952system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 953system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 954system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 955system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 956system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 957system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 958system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 959system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 960system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 961system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 962system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 963system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 964system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 965system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 966system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 967system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 968system.realview.ethernet.droppedPackets 0 # number of packets dropped 969system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 970system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 971system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 972system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 973system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 974system.cf0.dma_write_txs 631 # Number of DMA write transactions. 975system.toL2Bus.trans_dist::ReadReq 660487 # Transaction distribution 976system.toL2Bus.trans_dist::ReadResp 660472 # Transaction distribution 977system.toL2Bus.trans_dist::WriteReq 30977 # Transaction distribution 978system.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution 979system.toL2Bus.trans_dist::Writeback 252802 # Transaction distribution 980system.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution 981system.toL2Bus.trans_dist::UpgradeReq 91823 # Transaction distribution 982system.toL2Bus.trans_dist::SCUpgradeReq 41018 # Transaction distribution 983system.toL2Bus.trans_dist::UpgradeResp 132841 # Transaction distribution 984system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution 985system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 986system.toL2Bus.trans_dist::ReadExReq 40090 # Transaction distribution 987system.toL2Bus.trans_dist::ReadExResp 40090 # Transaction distribution 988system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1299997 # Packet count per connected master and slave (bytes) 989system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426747 # Packet count per connected master and slave (bytes) 990system.toL2Bus.pkt_count::total 1726744 # Packet count per connected master and slave (bytes) 991system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40789878 # Cumulative packet size per connected master and slave (bytes) 992system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8569500 # Cumulative packet size per connected master and slave (bytes) 993system.toL2Bus.pkt_size::total 49359378 # Cumulative packet size per connected master and slave (bytes) 994system.toL2Bus.snoops 291335 # Total snoops (count) 995system.toL2Bus.snoop_fanout::samples 1084475 # Request fanout histogram 996system.toL2Bus.snoop_fanout::mean 1.033634 # Request fanout histogram 997system.toL2Bus.snoop_fanout::stdev 0.180285 # Request fanout histogram 998system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 999system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1000system.toL2Bus.snoop_fanout::1 1048000 96.64% 96.64% # Request fanout histogram 1001system.toL2Bus.snoop_fanout::2 36475 3.36% 100.00% # Request fanout histogram 1002system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1003system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1004system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1005system.toL2Bus.snoop_fanout::total 1084475 # Request fanout histogram 1006system.toL2Bus.reqLayer0.occupancy 1587731325 # Layer occupancy (ticks) 1007system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1008system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) 1009system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1010system.toL2Bus.respLayer0.occupancy 2275347621 # Layer occupancy (ticks) 1011system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1012system.toL2Bus.respLayer1.occupancy 846816900 # Layer occupancy (ticks) 1013system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1014system.iobus.trans_dist::ReadReq 31016 # Transaction distribution 1015system.iobus.trans_dist::ReadResp 31016 # Transaction distribution 1016system.iobus.trans_dist::WriteReq 59425 # Transaction distribution 1017system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1018system.iobus.trans_dist::WriteInvalidateReq 15 # Transaction distribution 1019system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1020system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1021system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1022system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1024system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1025system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1026system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1027system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1028system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1029system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1030system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1031system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1032system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1033system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1034system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1035system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1036system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1037system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1038system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1039system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1040system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) 1041system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) 1042system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) 1043system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes) 1044system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 1045system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1052system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1053system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1054system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1055system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1056system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1057system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1058system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1059system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1060system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1061system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1062system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1063system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1064system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1065system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) 1066system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) 1067system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) 1068system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes) 1069system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 1070system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1071system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1072system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1073system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1074system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1075system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1076system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1077system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1078system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1079system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1080system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1081system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1082system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1083system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1084system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1085system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1086system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1087system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1088system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1090system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1092system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1093system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1094system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1096system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1097system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1098system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1099system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1100system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1101system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1102system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1103system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1104system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1105system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1106system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1107system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1108system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1109system.iobus.reqLayer27.occupancy 326640327 # Layer occupancy (ticks) 1110system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1111system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1112system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1113system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 1114system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1115system.iobus.respLayer3.occupancy 36831597 # Layer occupancy (ticks) 1116system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1117system.cpu0.branchPred.lookups 24028098 # Number of BP lookups 1118system.cpu0.branchPred.condPredicted 15717962 # Number of conditional branches predicted 1119system.cpu0.branchPred.condIncorrect 977131 # Number of conditional branches incorrect 1120system.cpu0.branchPred.BTBLookups 14655901 # Number of BTB lookups 1121system.cpu0.branchPred.BTBHits 10773369 # Number of BTB hits 1122system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1123system.cpu0.branchPred.BTBHitPct 73.508746 # BTB Hit Percentage 1124system.cpu0.branchPred.usedRAS 3877913 # Number of times the RAS was used to get a target. 1125system.cpu0.branchPred.RASInCorrect 32441 # Number of incorrect RAS predictions. 1126system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1127system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1128system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1129system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1130system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1131system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1132system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1133system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1134system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1135system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1136system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1137system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1138system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1139system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1140system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1141system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1142system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1143system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1144system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1145system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1146system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1147system.cpu0.dtb.inst_hits 0 # ITB inst hits 1148system.cpu0.dtb.inst_misses 0 # ITB inst misses 1149system.cpu0.dtb.read_hits 17721911 # DTB read hits 1150system.cpu0.dtb.read_misses 56434 # DTB read misses 1151system.cpu0.dtb.write_hits 14647364 # DTB write hits 1152system.cpu0.dtb.write_misses 8710 # DTB write misses 1153system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1154system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1155system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1156system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1157system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB 1158system.cpu0.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions 1159system.cpu0.dtb.prefetch_faults 2358 # Number of TLB faults due to prefetch 1160system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1161system.cpu0.dtb.perms_faults 855 # Number of TLB faults due to permissions restrictions 1162system.cpu0.dtb.read_accesses 17778345 # DTB read accesses 1163system.cpu0.dtb.write_accesses 14656074 # DTB write accesses 1164system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1165system.cpu0.dtb.hits 32369275 # DTB hits 1166system.cpu0.dtb.misses 65144 # DTB misses 1167system.cpu0.dtb.accesses 32434419 # DTB accesses 1168system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1169system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1170system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1171system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1172system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1173system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1174system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1175system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1176system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1177system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1178system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1179system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1180system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1181system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1182system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1183system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1184system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1185system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1186system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1187system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1188system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1189system.cpu0.itb.inst_hits 37749203 # ITB inst hits 1190system.cpu0.itb.inst_misses 10291 # ITB inst misses 1191system.cpu0.itb.read_hits 0 # DTB read hits 1192system.cpu0.itb.read_misses 0 # DTB read misses 1193system.cpu0.itb.write_hits 0 # DTB write hits 1194system.cpu0.itb.write_misses 0 # DTB write misses 1195system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1196system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1197system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1198system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1199system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB 1200system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1201system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1202system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1203system.cpu0.itb.perms_faults 1952 # Number of TLB faults due to permissions restrictions 1204system.cpu0.itb.read_accesses 0 # DTB read accesses 1205system.cpu0.itb.write_accesses 0 # DTB write accesses 1206system.cpu0.itb.inst_accesses 37759494 # ITB inst accesses 1207system.cpu0.itb.hits 37749203 # DTB hits 1208system.cpu0.itb.misses 10291 # DTB misses 1209system.cpu0.itb.accesses 37759494 # DTB accesses 1210system.cpu0.numCycles 126930318 # number of cpu cycles simulated 1211system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1212system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1213system.cpu0.fetch.icacheStallCycles 18136746 # Number of cycles fetch is stalled on an Icache miss 1214system.cpu0.fetch.Insts 112711782 # Number of instructions fetch has processed 1215system.cpu0.fetch.Branches 24028098 # Number of branches that fetch encountered 1216system.cpu0.fetch.predictedBranches 14651282 # Number of branches that fetch has predicted taken 1217system.cpu0.fetch.Cycles 104771989 # Number of cycles fetch has run and was not squashing or blocked 1218system.cpu0.fetch.SquashCycles 2822564 # Number of cycles fetch has spent squashing 1219system.cpu0.fetch.TlbCycles 133376 # Number of cycles fetch has spent waiting for tlb 1220system.cpu0.fetch.MiscStallCycles 38789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1221system.cpu0.fetch.PendingTrapStallCycles 365072 # Number of stall cycles due to pending traps 1222system.cpu0.fetch.PendingQuiesceStallCycles 429907 # Number of stall cycles due to pending quiesce instructions 1223system.cpu0.fetch.IcacheWaitRetryStallCycles 37570 # Number of stall cycles due to full MSHR 1224system.cpu0.fetch.CacheLines 37749815 # Number of cache lines fetched 1225system.cpu0.fetch.IcacheSquashes 265004 # Number of outstanding Icache misses that were squashed 1226system.cpu0.fetch.ItlbSquashes 3918 # Number of outstanding ITLB misses that were squashed 1227system.cpu0.fetch.rateDist::samples 125324731 # Number of instructions fetched each cycle (Total) 1228system.cpu0.fetch.rateDist::mean 1.084977 # Number of instructions fetched each cycle (Total) 1229system.cpu0.fetch.rateDist::stdev 1.263079 # Number of instructions fetched each cycle (Total) 1230system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1231system.cpu0.fetch.rateDist::0 62770441 50.09% 50.09% # Number of instructions fetched each cycle (Total) 1232system.cpu0.fetch.rateDist::1 21460959 17.12% 67.21% # Number of instructions fetched each cycle (Total) 1233system.cpu0.fetch.rateDist::2 8766539 7.00% 74.21% # Number of instructions fetched each cycle (Total) 1234system.cpu0.fetch.rateDist::3 32326792 25.79% 100.00% # Number of instructions fetched each cycle (Total) 1235system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1236system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1237system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1238system.cpu0.fetch.rateDist::total 125324731 # Number of instructions fetched each cycle (Total) 1239system.cpu0.fetch.branchRate 0.189301 # Number of branch fetches per cycle 1240system.cpu0.fetch.rate 0.887982 # Number of inst fetches per cycle 1241system.cpu0.decode.IdleCycles 19209269 # Number of cycles decode is idle 1242system.cpu0.decode.BlockedCycles 58676701 # Number of cycles decode is blocked 1243system.cpu0.decode.RunCycles 41413260 # Number of cycles decode is running 1244system.cpu0.decode.UnblockCycles 4958284 # Number of cycles decode is unblocking 1245system.cpu0.decode.SquashCycles 1067217 # Number of cycles decode is squashing 1246system.cpu0.decode.BranchResolved 3055385 # Number of times decode resolved a branch 1247system.cpu0.decode.BranchMispred 348256 # Number of times decode detected a branch misprediction 1248system.cpu0.decode.DecodedInsts 110724808 # Number of instructions handled by decode 1249system.cpu0.decode.SquashedInsts 3997323 # Number of squashed instructions handled by decode 1250system.cpu0.rename.SquashCycles 1067217 # Number of cycles rename is squashing 1251system.cpu0.rename.IdleCycles 24959463 # Number of cycles rename is idle 1252system.cpu0.rename.BlockCycles 12008700 # Number of cycles rename is blocking 1253system.cpu0.rename.serializeStallCycles 36549302 # count of cycles rename stalled for serializing inst 1254system.cpu0.rename.RunCycles 40482992 # Number of cycles rename is running 1255system.cpu0.rename.UnblockCycles 10257057 # Number of cycles rename is unblocking 1256system.cpu0.rename.RenamedInsts 105644030 # Number of instructions processed by rename 1257system.cpu0.rename.SquashedInsts 1060860 # Number of squashed instructions processed by rename 1258system.cpu0.rename.ROBFullEvents 1434602 # Number of times rename has blocked due to ROB full 1259system.cpu0.rename.IQFullEvents 161076 # Number of times rename has blocked due to IQ full 1260system.cpu0.rename.LQFullEvents 61450 # Number of times rename has blocked due to LQ full 1261system.cpu0.rename.SQFullEvents 6058216 # Number of times rename has blocked due to SQ full 1262system.cpu0.rename.RenamedOperands 109726611 # Number of destination operands rename has renamed 1263system.cpu0.rename.RenameLookups 482367040 # Number of register rename lookups that rename has made 1264system.cpu0.rename.int_rename_lookups 120917485 # Number of integer rename lookups 1265system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups 1266system.cpu0.rename.CommittedMaps 98135067 # Number of HB maps that are committed 1267system.cpu0.rename.UndoneMaps 11591541 # Number of HB maps that are undone due to squashing 1268system.cpu0.rename.serializingInsts 1228775 # count of serializing insts renamed 1269system.cpu0.rename.tempSerializingInsts 1087468 # count of temporary serializing insts renamed 1270system.cpu0.rename.skidInsts 12318365 # count of insts added to the skid buffer 1271system.cpu0.memDep0.insertedLoads 18735262 # Number of loads inserted to the mem dependence unit. 1272system.cpu0.memDep0.insertedStores 16202067 # Number of stores inserted to the mem dependence unit. 1273system.cpu0.memDep0.conflictingLoads 1700806 # Number of conflicting loads. 1274system.cpu0.memDep0.conflictingStores 2287265 # Number of conflicting stores. 1275system.cpu0.iq.iqInstsAdded 102683814 # Number of instructions added to the IQ (excludes non-spec) 1276system.cpu0.iq.iqNonSpecInstsAdded 1694438 # Number of non-speculative instructions added to the IQ 1277system.cpu0.iq.iqInstsIssued 100667981 # Number of instructions issued 1278system.cpu0.iq.iqSquashedInstsIssued 483835 # Number of squashed instructions issued 1279system.cpu0.iq.iqSquashedInstsExamined 9019913 # Number of squashed instructions iterated over during squash; mainly for profiling 1280system.cpu0.iq.iqSquashedOperandsExamined 22488132 # Number of squashed operands that are examined and possibly removed from graph 1281system.cpu0.iq.iqSquashedNonSpecRemoved 122848 # Number of squashed non-spec instructions that were removed 1282system.cpu0.iq.issued_per_cycle::samples 125324731 # Number of insts issued each cycle 1283system.cpu0.iq.issued_per_cycle::mean 0.803257 # Number of insts issued each cycle 1284system.cpu0.iq.issued_per_cycle::stdev 1.034844 # Number of insts issued each cycle 1285system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1286system.cpu0.iq.issued_per_cycle::0 69182553 55.20% 55.20% # Number of insts issued each cycle 1287system.cpu0.iq.issued_per_cycle::1 23178514 18.49% 73.70% # Number of insts issued each cycle 1288system.cpu0.iq.issued_per_cycle::2 22516011 17.97% 91.66% # Number of insts issued each cycle 1289system.cpu0.iq.issued_per_cycle::3 9333204 7.45% 99.11% # Number of insts issued each cycle 1290system.cpu0.iq.issued_per_cycle::4 1114412 0.89% 100.00% # Number of insts issued each cycle 1291system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle 1292system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1293system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1294system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1295system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1296system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1297system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1298system.cpu0.iq.issued_per_cycle::total 125324731 # Number of insts issued each cycle 1299system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1300system.cpu0.iq.fu_full::IntAlu 9379454 40.76% 40.76% # attempts to use FU when none available 1301system.cpu0.iq.fu_full::IntMult 82 0.00% 40.76% # attempts to use FU when none available 1302system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available 1303system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available 1304system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available 1305system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available 1306system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available 1307system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available 1308system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available 1309system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available 1310system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available 1311system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available 1312system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available 1313system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available 1314system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available 1315system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available 1316system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available 1317system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available 1318system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available 1319system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available 1320system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available 1321system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available 1322system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available 1323system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available 1324system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available 1325system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available 1326system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available 1327system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available 1328system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available 1329system.cpu0.iq.fu_full::MemRead 5581640 24.26% 65.02% # attempts to use FU when none available 1330system.cpu0.iq.fu_full::MemWrite 8050330 34.98% 100.00% # attempts to use FU when none available 1331system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1332system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1333system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued 1334system.cpu0.iq.FU_type_0::IntAlu 66408183 65.97% 65.97% # Type of FU issued 1335system.cpu0.iq.FU_type_0::IntMult 93140 0.09% 66.06% # Type of FU issued 1336system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued 1337system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued 1338system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 1339system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 1340system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 1341system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 1342system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 1343system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued 1344system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued 1345system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued 1346system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued 1347system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued 1348system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued 1349system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued 1350system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued 1351system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 1352system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 1353system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 1354system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 1355system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 1356system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 1357system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 1358system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued 1359system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued 1360system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued 1361system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued 1362system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued 1363system.cpu0.iq.FU_type_0::MemRead 18430252 18.31% 84.38% # Type of FU issued 1364system.cpu0.iq.FU_type_0::MemWrite 15726021 15.62% 100.00% # Type of FU issued 1365system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1366system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1367system.cpu0.iq.FU_type_0::total 100667981 # Type of FU issued 1368system.cpu0.iq.rate 0.793096 # Inst issue rate 1369system.cpu0.iq.fu_busy_cnt 23011506 # FU busy when requested 1370system.cpu0.iq.fu_busy_rate 0.228588 # FU busy rate (busy events/executed inst) 1371system.cpu0.iq.int_inst_queue_reads 350124170 # Number of integer instruction queue reads 1372system.cpu0.iq.int_inst_queue_writes 113406012 # Number of integer instruction queue writes 1373system.cpu0.iq.int_inst_queue_wakeup_accesses 98579580 # Number of integer instruction queue wakeup accesses 1374system.cpu0.iq.fp_inst_queue_reads 31864 # Number of floating instruction queue reads 1375system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes 1376system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses 1377system.cpu0.iq.int_alu_accesses 123656622 # Number of integer alu accesses 1378system.cpu0.iq.fp_alu_accesses 20592 # Number of floating point alu accesses 1379system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores 1380system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1381system.cpu0.iew.lsq.thread0.squashedLoads 2006492 # Number of loads squashed 1382system.cpu0.iew.lsq.thread0.ignoredResponses 2605 # Number of memory responses ignored because the instruction is squashed 1383system.cpu0.iew.lsq.thread0.memOrderViolation 19209 # Number of memory ordering violations 1384system.cpu0.iew.lsq.thread0.squashedStores 1022192 # Number of stores squashed 1385system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1386system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1387system.cpu0.iew.lsq.thread0.rescheduledLoads 106472 # Number of loads that were rescheduled 1388system.cpu0.iew.lsq.thread0.cacheBlocked 336634 # Number of times an access to memory failed due to the cache being blocked 1389system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1390system.cpu0.iew.iewSquashCycles 1067217 # Number of cycles IEW is squashing 1391system.cpu0.iew.iewBlockCycles 1619268 # Number of cycles IEW is blocking 1392system.cpu0.iew.iewUnblockCycles 191305 # Number of cycles IEW is unblocking 1393system.cpu0.iew.iewDispatchedInsts 104552982 # Number of instructions dispatched to IQ 1394system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 1395system.cpu0.iew.iewDispLoadInsts 18735262 # Number of dispatched load instructions 1396system.cpu0.iew.iewDispStoreInsts 16202067 # Number of dispatched store instructions 1397system.cpu0.iew.iewDispNonSpecInsts 876141 # Number of dispatched non-speculative instructions 1398system.cpu0.iew.iewIQFullEvents 27204 # Number of times the IQ has become full, causing a stall 1399system.cpu0.iew.iewLSQFullEvents 140421 # Number of times the LSQ has become full, causing a stall 1400system.cpu0.iew.memOrderViolationEvents 19209 # Number of memory order violations 1401system.cpu0.iew.predictedTakenIncorrect 291739 # Number of branches that were predicted taken incorrectly 1402system.cpu0.iew.predictedNotTakenIncorrect 400527 # Number of branches that were predicted not taken incorrectly 1403system.cpu0.iew.branchMispredicts 692266 # Number of branch mispredicts detected at execute 1404system.cpu0.iew.iewExecutedInsts 99570429 # Number of executed instructions 1405system.cpu0.iew.iewExecLoadInsts 17973451 # Number of load instructions executed 1406system.cpu0.iew.iewExecSquashedInsts 1032544 # Number of squashed instructions skipped in execute 1407system.cpu0.iew.exec_swp 0 # number of swp insts executed 1408system.cpu0.iew.exec_nop 174730 # number of nop insts executed 1409system.cpu0.iew.exec_refs 33508210 # number of memory reference insts executed 1410system.cpu0.iew.exec_branches 16843179 # Number of branches executed 1411system.cpu0.iew.exec_stores 15534759 # Number of stores executed 1412system.cpu0.iew.exec_rate 0.784450 # Inst execution rate 1413system.cpu0.iew.wb_sent 99039643 # cumulative count of insts sent to commit 1414system.cpu0.iew.wb_count 98589303 # cumulative count of insts written-back 1415system.cpu0.iew.wb_producers 51320532 # num instructions producing a value 1416system.cpu0.iew.wb_consumers 84799978 # num instructions consuming a value 1417system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1418system.cpu0.iew.wb_rate 0.776720 # insts written-back per cycle 1419system.cpu0.iew.wb_fanout 0.605195 # average fanout of values written-back 1420system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1421system.cpu0.commit.commitSquashedInsts 8525678 # The number of squashed insts skipped by commit 1422system.cpu0.commit.commitNonSpecStalls 1571590 # The number of times commit has been forced to stall to communicate backwards 1423system.cpu0.commit.branchMispredicts 633066 # The number of times a branch was mispredicted 1424system.cpu0.commit.committed_per_cycle::samples 123570875 # Number of insts commited each cycle 1425system.cpu0.commit.committed_per_cycle::mean 0.768216 # Number of insts commited each cycle 1426system.cpu0.commit.committed_per_cycle::stdev 1.481246 # Number of insts commited each cycle 1427system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1428system.cpu0.commit.committed_per_cycle::0 79246760 64.13% 64.13% # Number of insts commited each cycle 1429system.cpu0.commit.committed_per_cycle::1 24711613 20.00% 84.13% # Number of insts commited each cycle 1430system.cpu0.commit.committed_per_cycle::2 8248135 6.67% 90.80% # Number of insts commited each cycle 1431system.cpu0.commit.committed_per_cycle::3 3213746 2.60% 93.40% # Number of insts commited each cycle 1432system.cpu0.commit.committed_per_cycle::4 3439781 2.78% 96.19% # Number of insts commited each cycle 1433system.cpu0.commit.committed_per_cycle::5 1516341 1.23% 97.41% # Number of insts commited each cycle 1434system.cpu0.commit.committed_per_cycle::6 1141391 0.92% 98.34% # Number of insts commited each cycle 1435system.cpu0.commit.committed_per_cycle::7 534018 0.43% 98.77% # Number of insts commited each cycle 1436system.cpu0.commit.committed_per_cycle::8 1519090 1.23% 100.00% # Number of insts commited each cycle 1437system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1438system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1439system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1440system.cpu0.commit.committed_per_cycle::total 123570875 # Number of insts commited each cycle 1441system.cpu0.commit.committedInsts 78899754 # Number of instructions committed 1442system.cpu0.commit.committedOps 94929142 # Number of ops (including micro ops) committed 1443system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1444system.cpu0.commit.refs 31908645 # Number of memory references committed 1445system.cpu0.commit.loads 16728770 # Number of loads committed 1446system.cpu0.commit.membars 647107 # Number of memory barriers committed 1447system.cpu0.commit.branches 16205360 # Number of branches committed 1448system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. 1449system.cpu0.commit.int_insts 81878721 # Number of committed integer instructions. 1450system.cpu0.commit.function_calls 1929507 # Number of function calls committed. 1451system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1452system.cpu0.commit.op_class_0::IntAlu 62921673 66.28% 66.28% # Class of committed instruction 1453system.cpu0.commit.op_class_0::IntMult 90715 0.10% 66.38% # Class of committed instruction 1454system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction 1455system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction 1456system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction 1457system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction 1458system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction 1459system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction 1460system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction 1461system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction 1462system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction 1463system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction 1464system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction 1465system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction 1466system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction 1467system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction 1468system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction 1469system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction 1470system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction 1471system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction 1472system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction 1473system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction 1474system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction 1475system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction 1476system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction 1477system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction 1478system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction 1479system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction 1480system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction 1481system.cpu0.commit.op_class_0::MemRead 16728770 17.62% 84.01% # Class of committed instruction 1482system.cpu0.commit.op_class_0::MemWrite 15179875 15.99% 100.00% # Class of committed instruction 1483system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1484system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1485system.cpu0.commit.op_class_0::total 94929142 # Class of committed instruction 1486system.cpu0.commit.bw_lim_events 1519090 # number cycles where commit BW limit reached 1487system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1488system.cpu0.rob.rob_reads 221323955 # The number of ROB reads 1489system.cpu0.rob.rob_writes 208662740 # The number of ROB writes 1490system.cpu0.timesIdled 109422 # Number of times that the entire CPU went into an idle state and unscheduled itself 1491system.cpu0.idleCycles 1605587 # Total number of cycles that the CPU has spent unscheduled due to idling 1492system.cpu0.quiesceCycles 5521751456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1493system.cpu0.committedInsts 78777703 # Number of Instructions Simulated 1494system.cpu0.committedOps 94807091 # Number of Ops (including micro ops) Simulated 1495system.cpu0.cpi 1.611247 # CPI: Cycles Per Instruction 1496system.cpu0.cpi_total 1.611247 # CPI: Total CPI of All Threads 1497system.cpu0.ipc 0.620637 # IPC: Instructions Per Cycle 1498system.cpu0.ipc_total 0.620637 # IPC: Total IPC of All Threads 1499system.cpu0.int_regfile_reads 110612001 # number of integer regfile reads 1500system.cpu0.int_regfile_writes 59736021 # number of integer regfile writes 1501system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads 1502system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes 1503system.cpu0.cc_regfile_reads 350763374 # number of cc regfile reads 1504system.cpu0.cc_regfile_writes 41072426 # number of cc regfile writes 1505system.cpu0.misc_regfile_reads 246706358 # number of misc regfile reads 1506system.cpu0.misc_regfile_writes 1224463 # number of misc regfile writes 1507system.cpu0.toL2Bus.trans_dist::ReadReq 2021709 # Transaction distribution 1508system.cpu0.toL2Bus.trans_dist::ReadResp 1920443 # Transaction distribution 1509system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution 1510system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution 1511system.cpu0.toL2Bus.trans_dist::Writeback 512971 # Transaction distribution 1512system.cpu0.toL2Bus.trans_dist::HardPFReq 647722 # Transaction distribution 1513system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution 1514system.cpu0.toL2Bus.trans_dist::UpgradeReq 80908 # Transaction distribution 1515system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43157 # Transaction distribution 1516system.cpu0.toL2Bus.trans_dist::UpgradeResp 104918 # Transaction distribution 1517system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 1518system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 1519system.cpu0.toL2Bus.trans_dist::ReadExReq 291878 # Transaction distribution 1520system.cpu0.toL2Bus.trans_dist::ReadExResp 281134 # Transaction distribution 1521system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2533809 # Packet count per connected master and slave (bytes) 1522system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360432 # Packet count per connected master and slave (bytes) 1523system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28914 # Packet count per connected master and slave (bytes) 1524system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120703 # Packet count per connected master and slave (bytes) 1525system.cpu0.toL2Bus.pkt_count::total 5043858 # Packet count per connected master and slave (bytes) 1526system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80936864 # Cumulative packet size per connected master and slave (bytes) 1527system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86195670 # Cumulative packet size per connected master and slave (bytes) 1528system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50328 # Cumulative packet size per connected master and slave (bytes) 1529system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 219428 # Cumulative packet size per connected master and slave (bytes) 1530system.cpu0.toL2Bus.pkt_size::total 167402290 # Cumulative packet size per connected master and slave (bytes) 1531system.cpu0.toL2Bus.snoops 1041040 # Total snoops (count) 1532system.cpu0.toL2Bus.snoop_fanout::samples 3611543 # Request fanout histogram 1533system.cpu0.toL2Bus.snoop_fanout::mean 5.254928 # Request fanout histogram 1534system.cpu0.toL2Bus.snoop_fanout::stdev 0.435821 # Request fanout histogram 1535system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1536system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1537system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1538system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1539system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1540system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1541system.cpu0.toL2Bus.snoop_fanout::5 2690859 74.51% 74.51% # Request fanout histogram 1542system.cpu0.toL2Bus.snoop_fanout::6 920684 25.49% 100.00% # Request fanout histogram 1543system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1544system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1545system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1546system.cpu0.toL2Bus.snoop_fanout::total 3611543 # Request fanout histogram 1547system.cpu0.toL2Bus.reqLayer0.occupancy 1890112247 # Layer occupancy (ticks) 1548system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1549system.cpu0.toL2Bus.snoopLayer0.occupancy 117326747 # Layer occupancy (ticks) 1550system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1551system.cpu0.toL2Bus.respLayer0.occupancy 1900909092 # Layer occupancy (ticks) 1552system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1553system.cpu0.toL2Bus.respLayer1.occupancy 1220029643 # Layer occupancy (ticks) 1554system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1555system.cpu0.toL2Bus.respLayer2.occupancy 16342731 # Layer occupancy (ticks) 1556system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1557system.cpu0.toL2Bus.respLayer3.occupancy 65878690 # Layer occupancy (ticks) 1558system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1559system.cpu0.icache.tags.replacements 1263367 # number of replacements 1560system.cpu0.icache.tags.tagsinuse 511.774258 # Cycle average of tags in use 1561system.cpu0.icache.tags.total_refs 36446077 # Total number of references to valid blocks. 1562system.cpu0.icache.tags.sampled_refs 1263879 # Sample count of references to valid blocks. 1563system.cpu0.icache.tags.avg_refs 28.836682 # Average number of references to valid blocks. 1564system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. 1565system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774258 # Average occupied blocks per requestor 1566system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy 1567system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy 1568system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1569system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 1570system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 1571system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id 1572system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1573system.cpu0.icache.tags.tag_accesses 76757150 # Number of tag accesses 1574system.cpu0.icache.tags.data_accesses 76757150 # Number of data accesses 1575system.cpu0.icache.ReadReq_hits::cpu0.inst 36446077 # number of ReadReq hits 1576system.cpu0.icache.ReadReq_hits::total 36446077 # number of ReadReq hits 1577system.cpu0.icache.demand_hits::cpu0.inst 36446077 # number of demand (read+write) hits 1578system.cpu0.icache.demand_hits::total 36446077 # number of demand (read+write) hits 1579system.cpu0.icache.overall_hits::cpu0.inst 36446077 # number of overall hits 1580system.cpu0.icache.overall_hits::total 36446077 # number of overall hits 1581system.cpu0.icache.ReadReq_misses::cpu0.inst 1300540 # number of ReadReq misses 1582system.cpu0.icache.ReadReq_misses::total 1300540 # number of ReadReq misses 1583system.cpu0.icache.demand_misses::cpu0.inst 1300540 # number of demand (read+write) misses 1584system.cpu0.icache.demand_misses::total 1300540 # number of demand (read+write) misses 1585system.cpu0.icache.overall_misses::cpu0.inst 1300540 # number of overall misses 1586system.cpu0.icache.overall_misses::total 1300540 # number of overall misses 1587system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11011983856 # number of ReadReq miss cycles 1588system.cpu0.icache.ReadReq_miss_latency::total 11011983856 # number of ReadReq miss cycles 1589system.cpu0.icache.demand_miss_latency::cpu0.inst 11011983856 # number of demand (read+write) miss cycles 1590system.cpu0.icache.demand_miss_latency::total 11011983856 # number of demand (read+write) miss cycles 1591system.cpu0.icache.overall_miss_latency::cpu0.inst 11011983856 # number of overall miss cycles 1592system.cpu0.icache.overall_miss_latency::total 11011983856 # number of overall miss cycles 1593system.cpu0.icache.ReadReq_accesses::cpu0.inst 37746617 # number of ReadReq accesses(hits+misses) 1594system.cpu0.icache.ReadReq_accesses::total 37746617 # number of ReadReq accesses(hits+misses) 1595system.cpu0.icache.demand_accesses::cpu0.inst 37746617 # number of demand (read+write) accesses 1596system.cpu0.icache.demand_accesses::total 37746617 # number of demand (read+write) accesses 1597system.cpu0.icache.overall_accesses::cpu0.inst 37746617 # number of overall (read+write) accesses 1598system.cpu0.icache.overall_accesses::total 37746617 # number of overall (read+write) accesses 1599system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034454 # miss rate for ReadReq accesses 1600system.cpu0.icache.ReadReq_miss_rate::total 0.034454 # miss rate for ReadReq accesses 1601system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034454 # miss rate for demand accesses 1602system.cpu0.icache.demand_miss_rate::total 0.034454 # miss rate for demand accesses 1603system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034454 # miss rate for overall accesses 1604system.cpu0.icache.overall_miss_rate::total 0.034454 # miss rate for overall accesses 1605system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8467.239651 # average ReadReq miss latency 1606system.cpu0.icache.ReadReq_avg_miss_latency::total 8467.239651 # average ReadReq miss latency 1607system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency 1608system.cpu0.icache.demand_avg_miss_latency::total 8467.239651 # average overall miss latency 1609system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency 1610system.cpu0.icache.overall_avg_miss_latency::total 8467.239651 # average overall miss latency 1611system.cpu0.icache.blocked_cycles::no_mshrs 724812 # number of cycles access was blocked 1612system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked 1613system.cpu0.icache.blocked::no_mshrs 96016 # number of cycles access was blocked 1614system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked 1615system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.548867 # average number of cycles each access was blocked 1616system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked 1617system.cpu0.icache.fast_writes 0 # number of fast writes performed 1618system.cpu0.icache.cache_copies 0 # number of cache copies performed 1619system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36623 # number of ReadReq MSHR hits 1620system.cpu0.icache.ReadReq_mshr_hits::total 36623 # number of ReadReq MSHR hits 1621system.cpu0.icache.demand_mshr_hits::cpu0.inst 36623 # number of demand (read+write) MSHR hits 1622system.cpu0.icache.demand_mshr_hits::total 36623 # number of demand (read+write) MSHR hits 1623system.cpu0.icache.overall_mshr_hits::cpu0.inst 36623 # number of overall MSHR hits 1624system.cpu0.icache.overall_mshr_hits::total 36623 # number of overall MSHR hits 1625system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1263917 # number of ReadReq MSHR misses 1626system.cpu0.icache.ReadReq_mshr_misses::total 1263917 # number of ReadReq MSHR misses 1627system.cpu0.icache.demand_mshr_misses::cpu0.inst 1263917 # number of demand (read+write) MSHR misses 1628system.cpu0.icache.demand_mshr_misses::total 1263917 # number of demand (read+write) MSHR misses 1629system.cpu0.icache.overall_mshr_misses::cpu0.inst 1263917 # number of overall MSHR misses 1630system.cpu0.icache.overall_mshr_misses::total 1263917 # number of overall MSHR misses 1631system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8916921322 # number of ReadReq MSHR miss cycles 1632system.cpu0.icache.ReadReq_mshr_miss_latency::total 8916921322 # number of ReadReq MSHR miss cycles 1633system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8916921322 # number of demand (read+write) MSHR miss cycles 1634system.cpu0.icache.demand_mshr_miss_latency::total 8916921322 # number of demand (read+write) MSHR miss cycles 1635system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8916921322 # number of overall MSHR miss cycles 1636system.cpu0.icache.overall_mshr_miss_latency::total 8916921322 # number of overall MSHR miss cycles 1637system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles 1638system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles 1639system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles 1640system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles 1641system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for ReadReq accesses 1642system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033484 # mshr miss rate for ReadReq accesses 1643system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for demand accesses 1644system.cpu0.icache.demand_mshr_miss_rate::total 0.033484 # mshr miss rate for demand accesses 1645system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for overall accesses 1646system.cpu0.icache.overall_mshr_miss_rate::total 0.033484 # mshr miss rate for overall accesses 1647system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average ReadReq mshr miss latency 1648system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.989625 # average ReadReq mshr miss latency 1649system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency 1650system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency 1651system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency 1652system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency 1653system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1654system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1655system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1656system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1657system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1658system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11566475 # number of hwpf identified 1659system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 526266 # number of hwpf that were already in mshr 1660system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10413579 # number of hwpf that were already in the cache 1661system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118534 # number of hwpf that were already in the prefetch queue 1662system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1663system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25521 # number of hwpf removed because MSHR allocated 1664system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 482570 # number of hwpf issued 1665system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881997 # number of hwpf spanning a virtual page 1666system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1667system.cpu0.l2cache.tags.replacements 397205 # number of replacements 1668system.cpu0.l2cache.tags.tagsinuse 16210.584505 # Cycle average of tags in use 1669system.cpu0.l2cache.tags.total_refs 2245016 # Total number of references to valid blocks. 1670system.cpu0.l2cache.tags.sampled_refs 413453 # Sample count of references to valid blocks. 1671system.cpu0.l2cache.tags.avg_refs 5.429918 # Average number of references to valid blocks. 1672system.cpu0.l2cache.tags.warmup_cycle 2809067534500 # Cycle when the warmup percentage was hit. 1673system.cpu0.l2cache.tags.occ_blocks::writebacks 4582.280464 # Average occupied blocks per requestor 1674system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 7.704235 # Average occupied blocks per requestor 1675system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.810288 # Average occupied blocks per requestor 1676system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 954.063900 # Average occupied blocks per requestor 1677system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1415.763715 # Average occupied blocks per requestor 1678system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9248.961904 # Average occupied blocks per requestor 1679system.cpu0.l2cache.tags.occ_percent::writebacks 0.279680 # Average percentage of cache occupancy 1680system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000470 # Average percentage of cache occupancy 1681system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy 1682system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.058231 # Average percentage of cache occupancy 1683system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086411 # Average percentage of cache occupancy 1684system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.564512 # Average percentage of cache occupancy 1685system.cpu0.l2cache.tags.occ_percent::total 0.989416 # Average percentage of cache occupancy 1686system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8114 # Occupied blocks per task id 1687system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 1688system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8126 # Occupied blocks per task id 1689system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id 1690system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 255 # Occupied blocks per task id 1691system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3376 # Occupied blocks per task id 1692system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3995 # Occupied blocks per task id 1693system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id 1694system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 1695system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 1696system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 500 # Occupied blocks per task id 1697system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id 1698system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3570 # Occupied blocks per task id 1699system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 262 # Occupied blocks per task id 1700system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.495239 # Percentage of cache occupancy per task id 1701system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 1702system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.495972 # Percentage of cache occupancy per task id 1703system.cpu0.l2cache.tags.tag_accesses 43582923 # Number of tag accesses 1704system.cpu0.l2cache.tags.data_accesses 43582923 # Number of data accesses 1705system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54301 # number of ReadReq hits 1706system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12378 # number of ReadReq hits 1707system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242064 # number of ReadReq hits 1708system.cpu0.l2cache.ReadReq_hits::cpu0.data 407333 # number of ReadReq hits 1709system.cpu0.l2cache.ReadReq_hits::total 1716076 # number of ReadReq hits 1710system.cpu0.l2cache.Writeback_hits::writebacks 512970 # number of Writeback hits 1711system.cpu0.l2cache.Writeback_hits::total 512970 # number of Writeback hits 1712system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15323 # number of UpgradeReq hits 1713system.cpu0.l2cache.UpgradeReq_hits::total 15323 # number of UpgradeReq hits 1714system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2128 # number of SCUpgradeReq hits 1715system.cpu0.l2cache.SCUpgradeReq_hits::total 2128 # number of SCUpgradeReq hits 1716system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216744 # number of ReadExReq hits 1717system.cpu0.l2cache.ReadExReq_hits::total 216744 # number of ReadExReq hits 1718system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54301 # number of demand (read+write) hits 1719system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12378 # number of demand (read+write) hits 1720system.cpu0.l2cache.demand_hits::cpu0.inst 1242064 # number of demand (read+write) hits 1721system.cpu0.l2cache.demand_hits::cpu0.data 624077 # number of demand (read+write) hits 1722system.cpu0.l2cache.demand_hits::total 1932820 # number of demand (read+write) hits 1723system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54301 # number of overall hits 1724system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12378 # number of overall hits 1725system.cpu0.l2cache.overall_hits::cpu0.inst 1242064 # number of overall hits 1726system.cpu0.l2cache.overall_hits::cpu0.data 624077 # number of overall hits 1727system.cpu0.l2cache.overall_hits::total 1932820 # number of overall hits 1728system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 556 # number of ReadReq misses 1729system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 204 # number of ReadReq misses 1730system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21825 # number of ReadReq misses 1731system.cpu0.l2cache.ReadReq_misses::cpu0.data 90809 # number of ReadReq misses 1732system.cpu0.l2cache.ReadReq_misses::total 113394 # number of ReadReq misses 1733system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1734system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 1735system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27941 # number of UpgradeReq misses 1736system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses 1737system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses 1738system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses 1739system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52711 # number of ReadExReq misses 1740system.cpu0.l2cache.ReadExReq_misses::total 52711 # number of ReadExReq misses 1741system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 556 # number of demand (read+write) misses 1742system.cpu0.l2cache.demand_misses::cpu0.itb.walker 204 # number of demand (read+write) misses 1743system.cpu0.l2cache.demand_misses::cpu0.inst 21825 # number of demand (read+write) misses 1744system.cpu0.l2cache.demand_misses::cpu0.data 143520 # number of demand (read+write) misses 1745system.cpu0.l2cache.demand_misses::total 166105 # number of demand (read+write) misses 1746system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 556 # number of overall misses 1747system.cpu0.l2cache.overall_misses::cpu0.itb.walker 204 # number of overall misses 1748system.cpu0.l2cache.overall_misses::cpu0.inst 21825 # number of overall misses 1749system.cpu0.l2cache.overall_misses::cpu0.data 143520 # number of overall misses 1750system.cpu0.l2cache.overall_misses::total 166105 # number of overall misses 1751system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14566249 # number of ReadReq miss cycles 1752system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5056249 # number of ReadReq miss cycles 1753system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 811526688 # number of ReadReq miss cycles 1754system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694555362 # number of ReadReq miss cycles 1755system.cpu0.l2cache.ReadReq_miss_latency::total 3525704548 # number of ReadReq miss cycles 1756system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501364439 # number of UpgradeReq miss cycles 1757system.cpu0.l2cache.UpgradeReq_miss_latency::total 501364439 # number of UpgradeReq miss cycles 1758system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362083288 # number of SCUpgradeReq miss cycles 1759system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362083288 # number of SCUpgradeReq miss cycles 1760system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 361000 # number of SCUpgradeFailReq miss cycles 1761system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 361000 # number of SCUpgradeFailReq miss cycles 1762system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2596231534 # number of ReadExReq miss cycles 1763system.cpu0.l2cache.ReadExReq_miss_latency::total 2596231534 # number of ReadExReq miss cycles 1764system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14566249 # number of demand (read+write) miss cycles 1765system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5056249 # number of demand (read+write) miss cycles 1766system.cpu0.l2cache.demand_miss_latency::cpu0.inst 811526688 # number of demand (read+write) miss cycles 1767system.cpu0.l2cache.demand_miss_latency::cpu0.data 5290786896 # number of demand (read+write) miss cycles 1768system.cpu0.l2cache.demand_miss_latency::total 6121936082 # number of demand (read+write) miss cycles 1769system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14566249 # number of overall miss cycles 1770system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5056249 # number of overall miss cycles 1771system.cpu0.l2cache.overall_miss_latency::cpu0.inst 811526688 # number of overall miss cycles 1772system.cpu0.l2cache.overall_miss_latency::cpu0.data 5290786896 # number of overall miss cycles 1773system.cpu0.l2cache.overall_miss_latency::total 6121936082 # number of overall miss cycles 1774system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54857 # number of ReadReq accesses(hits+misses) 1775system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12582 # number of ReadReq accesses(hits+misses) 1776system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1263889 # number of ReadReq accesses(hits+misses) 1777system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498142 # number of ReadReq accesses(hits+misses) 1778system.cpu0.l2cache.ReadReq_accesses::total 1829470 # number of ReadReq accesses(hits+misses) 1779system.cpu0.l2cache.Writeback_accesses::writebacks 512971 # number of Writeback accesses(hits+misses) 1780system.cpu0.l2cache.Writeback_accesses::total 512971 # number of Writeback accesses(hits+misses) 1781system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43264 # number of UpgradeReq accesses(hits+misses) 1782system.cpu0.l2cache.UpgradeReq_accesses::total 43264 # number of UpgradeReq accesses(hits+misses) 1783system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20607 # number of SCUpgradeReq accesses(hits+misses) 1784system.cpu0.l2cache.SCUpgradeReq_accesses::total 20607 # number of SCUpgradeReq accesses(hits+misses) 1785system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269455 # number of ReadExReq accesses(hits+misses) 1786system.cpu0.l2cache.ReadExReq_accesses::total 269455 # number of ReadExReq accesses(hits+misses) 1787system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54857 # number of demand (read+write) accesses 1788system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12582 # number of demand (read+write) accesses 1789system.cpu0.l2cache.demand_accesses::cpu0.inst 1263889 # number of demand (read+write) accesses 1790system.cpu0.l2cache.demand_accesses::cpu0.data 767597 # number of demand (read+write) accesses 1791system.cpu0.l2cache.demand_accesses::total 2098925 # number of demand (read+write) accesses 1792system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54857 # number of overall (read+write) accesses 1793system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12582 # number of overall (read+write) accesses 1794system.cpu0.l2cache.overall_accesses::cpu0.inst 1263889 # number of overall (read+write) accesses 1795system.cpu0.l2cache.overall_accesses::cpu0.data 767597 # number of overall (read+write) accesses 1796system.cpu0.l2cache.overall_accesses::total 2098925 # number of overall (read+write) accesses 1797system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for ReadReq accesses 1798system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016214 # miss rate for ReadReq accesses 1799system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017268 # miss rate for ReadReq accesses 1800system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182295 # miss rate for ReadReq accesses 1801system.cpu0.l2cache.ReadReq_miss_rate::total 0.061982 # miss rate for ReadReq accesses 1802system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses 1803system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses 1804system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645826 # miss rate for UpgradeReq accesses 1805system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645826 # miss rate for UpgradeReq accesses 1806system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.896734 # miss rate for SCUpgradeReq accesses 1807system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.896734 # miss rate for SCUpgradeReq accesses 1808system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195621 # miss rate for ReadExReq accesses 1809system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195621 # miss rate for ReadExReq accesses 1810system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for demand accesses 1811system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016214 # miss rate for demand accesses 1812system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017268 # miss rate for demand accesses 1813system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186973 # miss rate for demand accesses 1814system.cpu0.l2cache.demand_miss_rate::total 0.079138 # miss rate for demand accesses 1815system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for overall accesses 1816system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016214 # miss rate for overall accesses 1817system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017268 # miss rate for overall accesses 1818system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186973 # miss rate for overall accesses 1819system.cpu0.l2cache.overall_miss_rate::total 0.079138 # miss rate for overall accesses 1820system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average ReadReq miss latency 1821system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24785.534314 # average ReadReq miss latency 1822system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.353402 # average ReadReq miss latency 1823system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29672.778711 # average ReadReq miss latency 1824system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31092.514137 # average ReadReq miss latency 1825system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17943.682724 # average UpgradeReq miss latency 1826system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17943.682724 # average UpgradeReq miss latency 1827system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19594.311813 # average SCUpgradeReq miss latency 1828system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19594.311813 # average SCUpgradeReq miss latency 1829system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1830system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1831system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49254.074747 # average ReadExReq miss latency 1832system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49254.074747 # average ReadExReq miss latency 1833system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency 1834system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency 1835system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency 1836system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency 1837system.cpu0.l2cache.demand_avg_miss_latency::total 36855.820607 # average overall miss latency 1838system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency 1839system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency 1840system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency 1841system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency 1842system.cpu0.l2cache.overall_avg_miss_latency::total 36855.820607 # average overall miss latency 1843system.cpu0.l2cache.blocked_cycles::no_mshrs 65022 # number of cycles access was blocked 1844system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1845system.cpu0.l2cache.blocked::no_mshrs 1467 # number of cycles access was blocked 1846system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1847system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.323108 # average number of cycles each access was blocked 1848system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1849system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1850system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1851system.cpu0.l2cache.writebacks::writebacks 212015 # number of writebacks 1852system.cpu0.l2cache.writebacks::total 212015 # number of writebacks 1853system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1854system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5576 # number of ReadReq MSHR hits 1855system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3180 # number of ReadReq MSHR hits 1856system.cpu0.l2cache.ReadReq_mshr_hits::total 8757 # number of ReadReq MSHR hits 1857system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8826 # number of ReadExReq MSHR hits 1858system.cpu0.l2cache.ReadExReq_mshr_hits::total 8826 # number of ReadExReq MSHR hits 1859system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1860system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5576 # number of demand (read+write) MSHR hits 1861system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12006 # number of demand (read+write) MSHR hits 1862system.cpu0.l2cache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits 1863system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1864system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5576 # number of overall MSHR hits 1865system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12006 # number of overall MSHR hits 1866system.cpu0.l2cache.overall_mshr_hits::total 17583 # number of overall MSHR hits 1867system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 556 # number of ReadReq MSHR misses 1868system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 203 # number of ReadReq MSHR misses 1869system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16249 # number of ReadReq MSHR misses 1870system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87629 # number of ReadReq MSHR misses 1871system.cpu0.l2cache.ReadReq_mshr_misses::total 104637 # number of ReadReq MSHR misses 1872system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1873system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1874system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of HardPFReq MSHR misses 1875system.cpu0.l2cache.HardPFReq_mshr_misses::total 482567 # number of HardPFReq MSHR misses 1876system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27941 # number of UpgradeReq MSHR misses 1877system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses 1878system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18479 # number of SCUpgradeReq MSHR misses 1879system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18479 # number of SCUpgradeReq MSHR misses 1880system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43885 # number of ReadExReq MSHR misses 1881system.cpu0.l2cache.ReadExReq_mshr_misses::total 43885 # number of ReadExReq MSHR misses 1882system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 556 # number of demand (read+write) MSHR misses 1883system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 203 # number of demand (read+write) MSHR misses 1884system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16249 # number of demand (read+write) MSHR misses 1885system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131514 # number of demand (read+write) MSHR misses 1886system.cpu0.l2cache.demand_mshr_misses::total 148522 # number of demand (read+write) MSHR misses 1887system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 556 # number of overall MSHR misses 1888system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 203 # number of overall MSHR misses 1889system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16249 # number of overall MSHR misses 1890system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131514 # number of overall MSHR misses 1891system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of overall MSHR misses 1892system.cpu0.l2cache.overall_mshr_misses::total 631089 # number of overall MSHR misses 1893system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of ReadReq MSHR miss cycles 1894system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3620751 # number of ReadReq MSHR miss cycles 1895system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 587001511 # number of ReadReq MSHR miss cycles 1896system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2007365947 # number of ReadReq MSHR miss cycles 1897system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2608656960 # number of ReadReq MSHR miss cycles 1898system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of HardPFReq MSHR miss cycles 1899system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21948496416 # number of HardPFReq MSHR miss cycles 1900system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 481784375 # number of UpgradeReq MSHR miss cycles 1901system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481784375 # number of UpgradeReq MSHR miss cycles 1902system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249254743 # number of SCUpgradeReq MSHR miss cycles 1903system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249254743 # number of SCUpgradeReq MSHR miss cycles 1904system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 284000 # number of SCUpgradeFailReq MSHR miss cycles 1905system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 284000 # number of SCUpgradeFailReq MSHR miss cycles 1906system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315803854 # number of ReadExReq MSHR miss cycles 1907system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315803854 # number of ReadExReq MSHR miss cycles 1908system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of demand (read+write) MSHR miss cycles 1909system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3620751 # number of demand (read+write) MSHR miss cycles 1910system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 587001511 # number of demand (read+write) MSHR miss cycles 1911system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3323169801 # number of demand (read+write) MSHR miss cycles 1912system.cpu0.l2cache.demand_mshr_miss_latency::total 3924460814 # number of demand (read+write) MSHR miss cycles 1913system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of overall MSHR miss cycles 1914system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3620751 # number of overall MSHR miss cycles 1915system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 587001511 # number of overall MSHR miss cycles 1916system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3323169801 # number of overall MSHR miss cycles 1917system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of overall MSHR miss cycles 1918system.cpu0.l2cache.overall_mshr_miss_latency::total 25872957230 # number of overall MSHR miss cycles 1919system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles 1920system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053946738 # number of ReadReq MSHR uncacheable cycles 1921system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272660488 # number of ReadReq MSHR uncacheable cycles 1922system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040262957 # number of WriteReq MSHR uncacheable cycles 1923system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040262957 # number of WriteReq MSHR uncacheable cycles 1924system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles 1925system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7094209695 # number of overall MSHR uncacheable cycles 1926system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312923445 # number of overall MSHR uncacheable cycles 1927system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for ReadReq accesses 1928system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for ReadReq accesses 1929system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for ReadReq accesses 1930system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175912 # mshr miss rate for ReadReq accesses 1931system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057195 # mshr miss rate for ReadReq accesses 1932system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses 1933system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses 1934system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1935system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1936system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645826 # mshr miss rate for UpgradeReq accesses 1937system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645826 # mshr miss rate for UpgradeReq accesses 1938system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896734 # mshr miss rate for SCUpgradeReq accesses 1939system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896734 # mshr miss rate for SCUpgradeReq accesses 1940system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162866 # mshr miss rate for ReadExReq accesses 1941system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162866 # mshr miss rate for ReadExReq accesses 1942system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for demand accesses 1943system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for demand accesses 1944system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for demand accesses 1945system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for demand accesses 1946system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070761 # mshr miss rate for demand accesses 1947system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for overall accesses 1948system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for overall accesses 1949system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for overall accesses 1950system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for overall accesses 1951system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1952system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300672 # mshr miss rate for overall accesses 1953system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average ReadReq mshr miss latency 1954system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average ReadReq mshr miss latency 1955system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average ReadReq mshr miss latency 1956system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22907.552831 # average ReadReq mshr miss latency 1957system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24930.540440 # average ReadReq mshr miss latency 1958system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average HardPFReq mshr miss latency 1959system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45482.795997 # average HardPFReq mshr miss latency 1960system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17242.918113 # average UpgradeReq mshr miss latency 1961system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17242.918113 # average UpgradeReq mshr miss latency 1962system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13488.540668 # average SCUpgradeReq mshr miss latency 1963system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13488.540668 # average SCUpgradeReq mshr miss latency 1964system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1965system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1966system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29982.997699 # average ReadExReq mshr miss latency 1967system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29982.997699 # average ReadExReq mshr miss latency 1968system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency 1969system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency 1970system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency 1971system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency 1972system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26423.430966 # average overall mshr miss latency 1973system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency 1974system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency 1975system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency 1976system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency 1977system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average overall mshr miss latency 1978system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40997.319285 # average overall mshr miss latency 1979system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1980system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1981system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1982system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1983system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1984system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1985system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1986system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1987system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1988system.cpu0.dcache.tags.replacements 712829 # number of replacements 1989system.cpu0.dcache.tags.tagsinuse 493.082766 # Cycle average of tags in use 1990system.cpu0.dcache.tags.total_refs 28841671 # Total number of references to valid blocks. 1991system.cpu0.dcache.tags.sampled_refs 713341 # Sample count of references to valid blocks. 1992system.cpu0.dcache.tags.avg_refs 40.431815 # Average number of references to valid blocks. 1993system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. 1994system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082766 # Average occupied blocks per requestor 1995system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy 1996system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy 1997system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1998system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id 1999system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id 2000system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 2001system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2002system.cpu0.dcache.tags.tag_accesses 63481444 # Number of tag accesses 2003system.cpu0.dcache.tags.data_accesses 63481444 # Number of data accesses 2004system.cpu0.dcache.ReadReq_hits::cpu0.data 15588806 # number of ReadReq hits 2005system.cpu0.dcache.ReadReq_hits::total 15588806 # number of ReadReq hits 2006system.cpu0.dcache.WriteReq_hits::cpu0.data 12071580 # number of WriteReq hits 2007system.cpu0.dcache.WriteReq_hits::total 12071580 # number of WriteReq hits 2008system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311031 # number of SoftPFReq hits 2009system.cpu0.dcache.SoftPFReq_hits::total 311031 # number of SoftPFReq hits 2010system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363190 # number of LoadLockedReq hits 2011system.cpu0.dcache.LoadLockedReq_hits::total 363190 # number of LoadLockedReq hits 2012system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360636 # number of StoreCondReq hits 2013system.cpu0.dcache.StoreCondReq_hits::total 360636 # number of StoreCondReq hits 2014system.cpu0.dcache.demand_hits::cpu0.data 27660386 # number of demand (read+write) hits 2015system.cpu0.dcache.demand_hits::total 27660386 # number of demand (read+write) hits 2016system.cpu0.dcache.overall_hits::cpu0.data 27971417 # number of overall hits 2017system.cpu0.dcache.overall_hits::total 27971417 # number of overall hits 2018system.cpu0.dcache.ReadReq_misses::cpu0.data 638107 # number of ReadReq misses 2019system.cpu0.dcache.ReadReq_misses::total 638107 # number of ReadReq misses 2020system.cpu0.dcache.WriteReq_misses::cpu0.data 1831928 # number of WriteReq misses 2021system.cpu0.dcache.WriteReq_misses::total 1831928 # number of WriteReq misses 2022system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146057 # number of SoftPFReq misses 2023system.cpu0.dcache.SoftPFReq_misses::total 146057 # number of SoftPFReq misses 2024system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses 2025system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses 2026system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20607 # number of StoreCondReq misses 2027system.cpu0.dcache.StoreCondReq_misses::total 20607 # number of StoreCondReq misses 2028system.cpu0.dcache.demand_misses::cpu0.data 2470035 # number of demand (read+write) misses 2029system.cpu0.dcache.demand_misses::total 2470035 # number of demand (read+write) misses 2030system.cpu0.dcache.overall_misses::cpu0.data 2616092 # number of overall misses 2031system.cpu0.dcache.overall_misses::total 2616092 # number of overall misses 2032system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8089240805 # number of ReadReq miss cycles 2033system.cpu0.dcache.ReadReq_miss_latency::total 8089240805 # number of ReadReq miss cycles 2034system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24966494558 # number of WriteReq miss cycles 2035system.cpu0.dcache.WriteReq_miss_latency::total 24966494558 # number of WriteReq miss cycles 2036system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395038253 # number of LoadLockedReq miss cycles 2037system.cpu0.dcache.LoadLockedReq_miss_latency::total 395038253 # number of LoadLockedReq miss cycles 2038system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453870788 # number of StoreCondReq miss cycles 2039system.cpu0.dcache.StoreCondReq_miss_latency::total 453870788 # number of StoreCondReq miss cycles 2040system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 394000 # number of StoreCondFailReq miss cycles 2041system.cpu0.dcache.StoreCondFailReq_miss_latency::total 394000 # number of StoreCondFailReq miss cycles 2042system.cpu0.dcache.demand_miss_latency::cpu0.data 33055735363 # number of demand (read+write) miss cycles 2043system.cpu0.dcache.demand_miss_latency::total 33055735363 # number of demand (read+write) miss cycles 2044system.cpu0.dcache.overall_miss_latency::cpu0.data 33055735363 # number of overall miss cycles 2045system.cpu0.dcache.overall_miss_latency::total 33055735363 # number of overall miss cycles 2046system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226913 # number of ReadReq accesses(hits+misses) 2047system.cpu0.dcache.ReadReq_accesses::total 16226913 # number of ReadReq accesses(hits+misses) 2048system.cpu0.dcache.WriteReq_accesses::cpu0.data 13903508 # number of WriteReq accesses(hits+misses) 2049system.cpu0.dcache.WriteReq_accesses::total 13903508 # number of WriteReq accesses(hits+misses) 2050system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457088 # number of SoftPFReq accesses(hits+misses) 2051system.cpu0.dcache.SoftPFReq_accesses::total 457088 # number of SoftPFReq accesses(hits+misses) 2052system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388166 # number of LoadLockedReq accesses(hits+misses) 2053system.cpu0.dcache.LoadLockedReq_accesses::total 388166 # number of LoadLockedReq accesses(hits+misses) 2054system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381243 # number of StoreCondReq accesses(hits+misses) 2055system.cpu0.dcache.StoreCondReq_accesses::total 381243 # number of StoreCondReq accesses(hits+misses) 2056system.cpu0.dcache.demand_accesses::cpu0.data 30130421 # number of demand (read+write) accesses 2057system.cpu0.dcache.demand_accesses::total 30130421 # number of demand (read+write) accesses 2058system.cpu0.dcache.overall_accesses::cpu0.data 30587509 # number of overall (read+write) accesses 2059system.cpu0.dcache.overall_accesses::total 30587509 # number of overall (read+write) accesses 2060system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039324 # miss rate for ReadReq accesses 2061system.cpu0.dcache.ReadReq_miss_rate::total 0.039324 # miss rate for ReadReq accesses 2062system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131760 # miss rate for WriteReq accesses 2063system.cpu0.dcache.WriteReq_miss_rate::total 0.131760 # miss rate for WriteReq accesses 2064system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319538 # miss rate for SoftPFReq accesses 2065system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319538 # miss rate for SoftPFReq accesses 2066system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064344 # miss rate for LoadLockedReq accesses 2067system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064344 # miss rate for LoadLockedReq accesses 2068system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054052 # miss rate for StoreCondReq accesses 2069system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054052 # miss rate for StoreCondReq accesses 2070system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081978 # miss rate for demand accesses 2071system.cpu0.dcache.demand_miss_rate::total 0.081978 # miss rate for demand accesses 2072system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085528 # miss rate for overall accesses 2073system.cpu0.dcache.overall_miss_rate::total 0.085528 # miss rate for overall accesses 2074system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12676.934754 # average ReadReq miss latency 2075system.cpu0.dcache.ReadReq_avg_miss_latency::total 12676.934754 # average ReadReq miss latency 2076system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13628.534832 # average WriteReq miss latency 2077system.cpu0.dcache.WriteReq_avg_miss_latency::total 13628.534832 # average WriteReq miss latency 2078system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.714166 # average LoadLockedReq miss latency 2079system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.714166 # average LoadLockedReq miss latency 2080system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22025.078274 # average StoreCondReq miss latency 2081system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22025.078274 # average StoreCondReq miss latency 2082system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 2083system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2084system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13382.699178 # average overall miss latency 2085system.cpu0.dcache.demand_avg_miss_latency::total 13382.699178 # average overall miss latency 2086system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12635.540097 # average overall miss latency 2087system.cpu0.dcache.overall_avg_miss_latency::total 12635.540097 # average overall miss latency 2088system.cpu0.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked 2089system.cpu0.dcache.blocked_cycles::no_targets 3370028 # number of cycles access was blocked 2090system.cpu0.dcache.blocked::no_mshrs 68 # number of cycles access was blocked 2091system.cpu0.dcache.blocked::no_targets 191306 # number of cycles access was blocked 2092system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.602941 # average number of cycles each access was blocked 2093system.cpu0.dcache.avg_blocked_cycles::no_targets 17.615903 # average number of cycles each access was blocked 2094system.cpu0.dcache.fast_writes 0 # number of fast writes performed 2095system.cpu0.dcache.cache_copies 0 # number of cache copies performed 2096system.cpu0.dcache.writebacks::writebacks 512971 # number of writebacks 2097system.cpu0.dcache.writebacks::total 512971 # number of writebacks 2098system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 247929 # number of ReadReq MSHR hits 2099system.cpu0.dcache.ReadReq_mshr_hits::total 247929 # number of ReadReq MSHR hits 2100system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519381 # number of WriteReq MSHR hits 2101system.cpu0.dcache.WriteReq_mshr_hits::total 1519381 # number of WriteReq MSHR hits 2102system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18420 # number of LoadLockedReq MSHR hits 2103system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18420 # number of LoadLockedReq MSHR hits 2104system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767310 # number of demand (read+write) MSHR hits 2105system.cpu0.dcache.demand_mshr_hits::total 1767310 # number of demand (read+write) MSHR hits 2106system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767310 # number of overall MSHR hits 2107system.cpu0.dcache.overall_mshr_hits::total 1767310 # number of overall MSHR hits 2108system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390178 # number of ReadReq MSHR misses 2109system.cpu0.dcache.ReadReq_mshr_misses::total 390178 # number of ReadReq MSHR misses 2110system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312547 # number of WriteReq MSHR misses 2111system.cpu0.dcache.WriteReq_mshr_misses::total 312547 # number of WriteReq MSHR misses 2112system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101517 # number of SoftPFReq MSHR misses 2113system.cpu0.dcache.SoftPFReq_mshr_misses::total 101517 # number of SoftPFReq MSHR misses 2114system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses 2115system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses 2116system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20607 # number of StoreCondReq MSHR misses 2117system.cpu0.dcache.StoreCondReq_mshr_misses::total 20607 # number of StoreCondReq MSHR misses 2118system.cpu0.dcache.demand_mshr_misses::cpu0.data 702725 # number of demand (read+write) MSHR misses 2119system.cpu0.dcache.demand_mshr_misses::total 702725 # number of demand (read+write) MSHR misses 2120system.cpu0.dcache.overall_mshr_misses::cpu0.data 804242 # number of overall MSHR misses 2121system.cpu0.dcache.overall_mshr_misses::total 804242 # number of overall MSHR misses 2122system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170870238 # number of ReadReq MSHR miss cycles 2123system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170870238 # number of ReadReq MSHR miss cycles 2124system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4998082086 # number of WriteReq MSHR miss cycles 2125system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4998082086 # number of WriteReq MSHR miss cycles 2126system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1413907491 # number of SoftPFReq MSHR miss cycles 2127system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1413907491 # number of SoftPFReq MSHR miss cycles 2128system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97710498 # number of LoadLockedReq MSHR miss cycles 2129system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97710498 # number of LoadLockedReq MSHR miss cycles 2130system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411958212 # number of StoreCondReq MSHR miss cycles 2131system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411958212 # number of StoreCondReq MSHR miss cycles 2132system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 372000 # number of StoreCondFailReq MSHR miss cycles 2133system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 372000 # number of StoreCondFailReq MSHR miss cycles 2134system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9168952324 # number of demand (read+write) MSHR miss cycles 2135system.cpu0.dcache.demand_mshr_miss_latency::total 9168952324 # number of demand (read+write) MSHR miss cycles 2136system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10582859815 # number of overall MSHR miss cycles 2137system.cpu0.dcache.overall_mshr_miss_latency::total 10582859815 # number of overall MSHR miss cycles 2138system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217153741 # number of ReadReq MSHR uncacheable cycles 2139system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217153741 # number of ReadReq MSHR uncacheable cycles 2140system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187052487 # number of WriteReq MSHR uncacheable cycles 2141system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187052487 # number of WriteReq MSHR uncacheable cycles 2142system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404206228 # number of overall MSHR uncacheable cycles 2143system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404206228 # number of overall MSHR uncacheable cycles 2144system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses 2145system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses 2146system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022480 # mshr miss rate for WriteReq accesses 2147system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022480 # mshr miss rate for WriteReq accesses 2148system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222095 # mshr miss rate for SoftPFReq accesses 2149system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222095 # mshr miss rate for SoftPFReq accesses 2150system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016890 # mshr miss rate for LoadLockedReq accesses 2151system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016890 # mshr miss rate for LoadLockedReq accesses 2152system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054052 # mshr miss rate for StoreCondReq accesses 2153system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054052 # mshr miss rate for StoreCondReq accesses 2154system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023323 # mshr miss rate for demand accesses 2155system.cpu0.dcache.demand_mshr_miss_rate::total 0.023323 # mshr miss rate for demand accesses 2156system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026293 # mshr miss rate for overall accesses 2157system.cpu0.dcache.overall_mshr_miss_rate::total 0.026293 # mshr miss rate for overall accesses 2158system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10689.660201 # average ReadReq mshr miss latency 2159system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10689.660201 # average ReadReq mshr miss latency 2160system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15991.457560 # average WriteReq mshr miss latency 2161system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15991.457560 # average WriteReq mshr miss latency 2162system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13927.790331 # average SoftPFReq mshr miss latency 2163system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13927.790331 # average SoftPFReq mshr miss latency 2164system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14903.980781 # average LoadLockedReq mshr miss latency 2165system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14903.980781 # average LoadLockedReq mshr miss latency 2166system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19991.178337 # average StoreCondReq mshr miss latency 2167system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19991.178337 # average StoreCondReq mshr miss latency 2168system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 2169system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2170system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13047.710447 # average overall mshr miss latency 2171system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13047.710447 # average overall mshr miss latency 2172system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13158.800231 # average overall mshr miss latency 2173system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13158.800231 # average overall mshr miss latency 2174system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2175system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2176system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2177system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2178system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2179system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2180system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2181system.cpu1.branchPred.lookups 33910931 # Number of BP lookups 2182system.cpu1.branchPred.condPredicted 11562938 # Number of conditional branches predicted 2183system.cpu1.branchPred.condIncorrect 305104 # Number of conditional branches incorrect 2184system.cpu1.branchPred.BTBLookups 18756149 # Number of BTB lookups 2185system.cpu1.branchPred.BTBHits 14959197 # Number of BTB hits 2186system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2187system.cpu1.branchPred.BTBHitPct 79.756228 # BTB Hit Percentage 2188system.cpu1.branchPred.usedRAS 12490116 # Number of times the RAS was used to get a target. 2189system.cpu1.branchPred.RASInCorrect 7241 # Number of incorrect RAS predictions. 2190system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2191system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2192system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2193system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2194system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2195system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2196system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2197system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2198system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2199system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2200system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 2201system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 2202system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 2203system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2204system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2205system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2206system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2207system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2208system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2209system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2210system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2211system.cpu1.dtb.inst_hits 0 # ITB inst hits 2212system.cpu1.dtb.inst_misses 0 # ITB inst misses 2213system.cpu1.dtb.read_hits 10163466 # DTB read hits 2214system.cpu1.dtb.read_misses 18799 # DTB read misses 2215system.cpu1.dtb.write_hits 6542146 # DTB write hits 2216system.cpu1.dtb.write_misses 2834 # DTB write misses 2217system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 2218system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 2219system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2220system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2221system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB 2222system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions 2223system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch 2224system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2225system.cpu1.dtb.perms_faults 406 # Number of TLB faults due to permissions restrictions 2226system.cpu1.dtb.read_accesses 10182265 # DTB read accesses 2227system.cpu1.dtb.write_accesses 6544980 # DTB write accesses 2228system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 2229system.cpu1.dtb.hits 16705612 # DTB hits 2230system.cpu1.dtb.misses 21633 # DTB misses 2231system.cpu1.dtb.accesses 16727245 # DTB accesses 2232system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 2233system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2234system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 2235system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 2236system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 2237system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2238system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2239system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2240system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2241system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2242system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 2243system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 2244system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 2245system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2246system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2247system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2248system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2249system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2250system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 2251system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 2252system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2253system.cpu1.itb.inst_hits 43642051 # ITB inst hits 2254system.cpu1.itb.inst_misses 6989 # ITB inst misses 2255system.cpu1.itb.read_hits 0 # DTB read hits 2256system.cpu1.itb.read_misses 0 # DTB read misses 2257system.cpu1.itb.write_hits 0 # DTB write hits 2258system.cpu1.itb.write_misses 0 # DTB write misses 2259system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 2260system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 2261system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2262system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2263system.cpu1.itb.flush_entries 1203 # Number of entries that have been flushed from TLB 2264system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2265system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2266system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2267system.cpu1.itb.perms_faults 541 # Number of TLB faults due to permissions restrictions 2268system.cpu1.itb.read_accesses 0 # DTB read accesses 2269system.cpu1.itb.write_accesses 0 # DTB write accesses 2270system.cpu1.itb.inst_accesses 43649040 # ITB inst accesses 2271system.cpu1.itb.hits 43642051 # DTB hits 2272system.cpu1.itb.misses 6989 # DTB misses 2273system.cpu1.itb.accesses 43649040 # DTB accesses 2274system.cpu1.numCycles 104614253 # number of cpu cycles simulated 2275system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2276system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 2277system.cpu1.fetch.icacheStallCycles 9984991 # Number of cycles fetch is stalled on an Icache miss 2278system.cpu1.fetch.Insts 109167147 # Number of instructions fetch has processed 2279system.cpu1.fetch.Branches 33910931 # Number of branches that fetch encountered 2280system.cpu1.fetch.predictedBranches 27449313 # Number of branches that fetch has predicted taken 2281system.cpu1.fetch.Cycles 91788694 # Number of cycles fetch has run and was not squashing or blocked 2282system.cpu1.fetch.SquashCycles 3775566 # Number of cycles fetch has spent squashing 2283system.cpu1.fetch.TlbCycles 78493 # Number of cycles fetch has spent waiting for tlb 2284system.cpu1.fetch.MiscStallCycles 31389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2285system.cpu1.fetch.PendingTrapStallCycles 199715 # Number of stall cycles due to pending traps 2286system.cpu1.fetch.PendingQuiesceStallCycles 294230 # Number of stall cycles due to pending quiesce instructions 2287system.cpu1.fetch.IcacheWaitRetryStallCycles 7403 # Number of stall cycles due to full MSHR 2288system.cpu1.fetch.CacheLines 43641443 # Number of cache lines fetched 2289system.cpu1.fetch.IcacheSquashes 116254 # Number of outstanding Icache misses that were squashed 2290system.cpu1.fetch.ItlbSquashes 2254 # Number of outstanding ITLB misses that were squashed 2291system.cpu1.fetch.rateDist::samples 104272698 # Number of instructions fetched each cycle (Total) 2292system.cpu1.fetch.rateDist::mean 1.296959 # Number of instructions fetched each cycle (Total) 2293system.cpu1.fetch.rateDist::stdev 1.339784 # Number of instructions fetched each cycle (Total) 2294system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2295system.cpu1.fetch.rateDist::0 47324573 45.39% 45.39% # Number of instructions fetched each cycle (Total) 2296system.cpu1.fetch.rateDist::1 14035291 13.46% 58.85% # Number of instructions fetched each cycle (Total) 2297system.cpu1.fetch.rateDist::2 7536357 7.23% 66.07% # Number of instructions fetched each cycle (Total) 2298system.cpu1.fetch.rateDist::3 35376477 33.93% 100.00% # Number of instructions fetched each cycle (Total) 2299system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2300system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2301system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 2302system.cpu1.fetch.rateDist::total 104272698 # Number of instructions fetched each cycle (Total) 2303system.cpu1.fetch.branchRate 0.324152 # Number of branch fetches per cycle 2304system.cpu1.fetch.rate 1.043521 # Number of inst fetches per cycle 2305system.cpu1.decode.IdleCycles 13017206 # Number of cycles decode is idle 2306system.cpu1.decode.BlockedCycles 61665780 # Number of cycles decode is blocked 2307system.cpu1.decode.RunCycles 26725185 # Number of cycles decode is running 2308system.cpu1.decode.UnblockCycles 1111466 # Number of cycles decode is unblocking 2309system.cpu1.decode.SquashCycles 1753061 # Number of cycles decode is squashing 2310system.cpu1.decode.BranchResolved 754244 # Number of times decode resolved a branch 2311system.cpu1.decode.BranchMispred 137628 # Number of times decode detected a branch misprediction 2312system.cpu1.decode.DecodedInsts 68061507 # Number of instructions handled by decode 2313system.cpu1.decode.SquashedInsts 1169291 # Number of squashed instructions handled by decode 2314system.cpu1.rename.SquashCycles 1753061 # Number of cycles rename is squashing 2315system.cpu1.rename.IdleCycles 17449719 # Number of cycles rename is idle 2316system.cpu1.rename.BlockCycles 2249370 # Number of cycles rename is blocking 2317system.cpu1.rename.serializeStallCycles 56981821 # count of cycles rename stalled for serializing inst 2318system.cpu1.rename.RunCycles 23380432 # Number of cycles rename is running 2319system.cpu1.rename.UnblockCycles 2458295 # Number of cycles rename is unblocking 2320system.cpu1.rename.RenamedInsts 55156803 # Number of instructions processed by rename 2321system.cpu1.rename.SquashedInsts 230618 # Number of squashed instructions processed by rename 2322system.cpu1.rename.ROBFullEvents 263094 # Number of times rename has blocked due to ROB full 2323system.cpu1.rename.IQFullEvents 35438 # Number of times rename has blocked due to IQ full 2324system.cpu1.rename.LQFullEvents 18102 # Number of times rename has blocked due to LQ full 2325system.cpu1.rename.SQFullEvents 1431236 # Number of times rename has blocked due to SQ full 2326system.cpu1.rename.RenamedOperands 55002903 # Number of destination operands rename has renamed 2327system.cpu1.rename.RenameLookups 260522537 # Number of register rename lookups that rename has made 2328system.cpu1.rename.int_rename_lookups 58680311 # Number of integer rename lookups 2329system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups 2330system.cpu1.rename.CommittedMaps 52222762 # Number of HB maps that are committed 2331system.cpu1.rename.UndoneMaps 2780141 # Number of HB maps that are undone due to squashing 2332system.cpu1.rename.serializingInsts 1878015 # count of serializing insts renamed 2333system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed 2334system.cpu1.rename.skidInsts 13100914 # count of insts added to the skid buffer 2335system.cpu1.memDep0.insertedLoads 10457203 # Number of loads inserted to the mem dependence unit. 2336system.cpu1.memDep0.insertedStores 6914095 # Number of stores inserted to the mem dependence unit. 2337system.cpu1.memDep0.conflictingLoads 629486 # Number of conflicting loads. 2338system.cpu1.memDep0.conflictingStores 832023 # Number of conflicting stores. 2339system.cpu1.iq.iqInstsAdded 54264845 # Number of instructions added to the IQ (excludes non-spec) 2340system.cpu1.iq.iqNonSpecInstsAdded 589076 # Number of non-speculative instructions added to the IQ 2341system.cpu1.iq.iqInstsIssued 53908335 # Number of instructions issued 2342system.cpu1.iq.iqSquashedInstsIssued 111707 # Number of squashed instructions issued 2343system.cpu1.iq.iqSquashedInstsExamined 2293120 # Number of squashed instructions iterated over during squash; mainly for profiling 2344system.cpu1.iq.iqSquashedOperandsExamined 5811368 # Number of squashed operands that are examined and possibly removed from graph 2345system.cpu1.iq.iqSquashedNonSpecRemoved 48776 # Number of squashed non-spec instructions that were removed 2346system.cpu1.iq.issued_per_cycle::samples 104272698 # Number of insts issued each cycle 2347system.cpu1.iq.issued_per_cycle::mean 0.516994 # Number of insts issued each cycle 2348system.cpu1.iq.issued_per_cycle::stdev 0.852584 # Number of insts issued each cycle 2349system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2350system.cpu1.iq.issued_per_cycle::0 71021448 68.11% 68.11% # Number of insts issued each cycle 2351system.cpu1.iq.issued_per_cycle::1 16528398 15.85% 83.96% # Number of insts issued each cycle 2352system.cpu1.iq.issued_per_cycle::2 13076148 12.54% 96.50% # Number of insts issued each cycle 2353system.cpu1.iq.issued_per_cycle::3 3359187 3.22% 99.72% # Number of insts issued each cycle 2354system.cpu1.iq.issued_per_cycle::4 287505 0.28% 100.00% # Number of insts issued each cycle 2355system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle 2356system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2357system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2358system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2359system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2360system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2361system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2362system.cpu1.iq.issued_per_cycle::total 104272698 # Number of insts issued each cycle 2363system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2364system.cpu1.iq.fu_full::IntAlu 2925111 45.11% 45.11% # attempts to use FU when none available 2365system.cpu1.iq.fu_full::IntMult 678 0.01% 45.12% # attempts to use FU when none available 2366system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.12% # attempts to use FU when none available 2367system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.12% # attempts to use FU when none available 2368system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.12% # attempts to use FU when none available 2369system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.12% # attempts to use FU when none available 2370system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.12% # attempts to use FU when none available 2371system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.12% # attempts to use FU when none available 2372system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.12% # attempts to use FU when none available 2373system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.12% # attempts to use FU when none available 2374system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.12% # attempts to use FU when none available 2375system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.12% # attempts to use FU when none available 2376system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.12% # attempts to use FU when none available 2377system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.12% # attempts to use FU when none available 2378system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.12% # attempts to use FU when none available 2379system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.12% # attempts to use FU when none available 2380system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.12% # attempts to use FU when none available 2381system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.12% # attempts to use FU when none available 2382system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.12% # attempts to use FU when none available 2383system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.12% # attempts to use FU when none available 2384system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.12% # attempts to use FU when none available 2385system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.12% # attempts to use FU when none available 2386system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.12% # attempts to use FU when none available 2387system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.12% # attempts to use FU when none available 2388system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.12% # attempts to use FU when none available 2389system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.12% # attempts to use FU when none available 2390system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.12% # attempts to use FU when none available 2391system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.12% # attempts to use FU when none available 2392system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.12% # attempts to use FU when none available 2393system.cpu1.iq.fu_full::MemRead 1673253 25.80% 70.93% # attempts to use FU when none available 2394system.cpu1.iq.fu_full::MemWrite 1885198 29.07% 100.00% # attempts to use FU when none available 2395system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2396system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2397system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued 2398system.cpu1.iq.FU_type_0::IntAlu 36727070 68.13% 68.13% # Type of FU issued 2399system.cpu1.iq.FU_type_0::IntMult 46542 0.09% 68.22% # Type of FU issued 2400system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued 2401system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued 2402system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued 2403system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued 2404system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued 2405system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued 2406system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued 2407system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued 2408system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued 2409system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued 2410system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued 2411system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued 2412system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.22% # Type of FU issued 2413system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued 2414system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued 2415system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.22% # Type of FU issued 2416system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued 2417system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued 2418system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued 2419system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued 2420system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued 2421system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued 2422system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued 2423system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued 2424system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 2425system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 2426system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued 2427system.cpu1.iq.FU_type_0::MemRead 10379930 19.25% 87.48% # Type of FU issued 2428system.cpu1.iq.FU_type_0::MemWrite 6751385 12.52% 100.00% # Type of FU issued 2429system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2430system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2431system.cpu1.iq.FU_type_0::total 53908335 # Type of FU issued 2432system.cpu1.iq.rate 0.515306 # Inst issue rate 2433system.cpu1.iq.fu_busy_cnt 6484240 # FU busy when requested 2434system.cpu1.iq.fu_busy_rate 0.120283 # FU busy rate (busy events/executed inst) 2435system.cpu1.iq.int_inst_queue_reads 218679535 # Number of integer instruction queue reads 2436system.cpu1.iq.int_inst_queue_writes 57155155 # Number of integer instruction queue writes 2437system.cpu1.iq.int_inst_queue_wakeup_accesses 51920155 # Number of integer instruction queue wakeup accesses 2438system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads 2439system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes 2440system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses 2441system.cpu1.iq.int_alu_accesses 60388817 # Number of integer alu accesses 2442system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses 2443system.cpu1.iew.lsq.thread0.forwLoads 91403 # Number of loads that had data forwarded from stores 2444system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2445system.cpu1.iew.lsq.thread0.squashedLoads 490692 # Number of loads squashed 2446system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed 2447system.cpu1.iew.lsq.thread0.memOrderViolation 10198 # Number of memory ordering violations 2448system.cpu1.iew.lsq.thread0.squashedStores 355978 # Number of stores squashed 2449system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2450system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2451system.cpu1.iew.lsq.thread0.rescheduledLoads 51963 # Number of loads that were rescheduled 2452system.cpu1.iew.lsq.thread0.cacheBlocked 70332 # Number of times an access to memory failed due to the cache being blocked 2453system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2454system.cpu1.iew.iewSquashCycles 1753061 # Number of cycles IEW is squashing 2455system.cpu1.iew.iewBlockCycles 546569 # Number of cycles IEW is blocking 2456system.cpu1.iew.iewUnblockCycles 114085 # Number of cycles IEW is unblocking 2457system.cpu1.iew.iewDispatchedInsts 54906076 # Number of instructions dispatched to IQ 2458system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2459system.cpu1.iew.iewDispLoadInsts 10457203 # Number of dispatched load instructions 2460system.cpu1.iew.iewDispStoreInsts 6914095 # Number of dispatched store instructions 2461system.cpu1.iew.iewDispNonSpecInsts 301562 # Number of dispatched non-speculative instructions 2462system.cpu1.iew.iewIQFullEvents 9838 # Number of times the IQ has become full, causing a stall 2463system.cpu1.iew.iewLSQFullEvents 96727 # Number of times the LSQ has become full, causing a stall 2464system.cpu1.iew.memOrderViolationEvents 10198 # Number of memory order violations 2465system.cpu1.iew.predictedTakenIncorrect 54956 # Number of branches that were predicted taken incorrectly 2466system.cpu1.iew.predictedNotTakenIncorrect 127310 # Number of branches that were predicted not taken incorrectly 2467system.cpu1.iew.branchMispredicts 182266 # Number of branch mispredicts detected at execute 2468system.cpu1.iew.iewExecutedInsts 53638370 # Number of executed instructions 2469system.cpu1.iew.iewExecLoadInsts 10277968 # Number of load instructions executed 2470system.cpu1.iew.iewExecSquashedInsts 248350 # Number of squashed instructions skipped in execute 2471system.cpu1.iew.exec_swp 0 # number of swp insts executed 2472system.cpu1.iew.exec_nop 52155 # number of nop insts executed 2473system.cpu1.iew.exec_refs 16965083 # number of memory reference insts executed 2474system.cpu1.iew.exec_branches 11807834 # Number of branches executed 2475system.cpu1.iew.exec_stores 6687115 # Number of stores executed 2476system.cpu1.iew.exec_rate 0.512725 # Inst execution rate 2477system.cpu1.iew.wb_sent 53497576 # cumulative count of insts sent to commit 2478system.cpu1.iew.wb_count 51921941 # cumulative count of insts written-back 2479system.cpu1.iew.wb_producers 25229731 # num instructions producing a value 2480system.cpu1.iew.wb_consumers 38490253 # num instructions consuming a value 2481system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2482system.cpu1.iew.wb_rate 0.496318 # insts written-back per cycle 2483system.cpu1.iew.wb_fanout 0.655484 # average fanout of values written-back 2484system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2485system.cpu1.commit.commitSquashedInsts 3658728 # The number of squashed insts skipped by commit 2486system.cpu1.commit.commitNonSpecStalls 540300 # The number of times commit has been forced to stall to communicate backwards 2487system.cpu1.commit.branchMispredicts 170382 # The number of times a branch was mispredicted 2488system.cpu1.commit.committed_per_cycle::samples 102340769 # Number of insts commited each cycle 2489system.cpu1.commit.committed_per_cycle::mean 0.498127 # Number of insts commited each cycle 2490system.cpu1.commit.committed_per_cycle::stdev 1.159192 # Number of insts commited each cycle 2491system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2492system.cpu1.commit.committed_per_cycle::0 76762339 75.01% 75.01% # Number of insts commited each cycle 2493system.cpu1.commit.committed_per_cycle::1 14287767 13.96% 88.97% # Number of insts commited each cycle 2494system.cpu1.commit.committed_per_cycle::2 6080575 5.94% 94.91% # Number of insts commited each cycle 2495system.cpu1.commit.committed_per_cycle::3 703802 0.69% 95.60% # Number of insts commited each cycle 2496system.cpu1.commit.committed_per_cycle::4 1980023 1.93% 97.53% # Number of insts commited each cycle 2497system.cpu1.commit.committed_per_cycle::5 1565125 1.53% 99.06% # Number of insts commited each cycle 2498system.cpu1.commit.committed_per_cycle::6 446359 0.44% 99.50% # Number of insts commited each cycle 2499system.cpu1.commit.committed_per_cycle::7 123712 0.12% 99.62% # Number of insts commited each cycle 2500system.cpu1.commit.committed_per_cycle::8 391067 0.38% 100.00% # Number of insts commited each cycle 2501system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2502system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2503system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2504system.cpu1.commit.committed_per_cycle::total 102340769 # Number of insts commited each cycle 2505system.cpu1.commit.committedInsts 41392870 # Number of instructions committed 2506system.cpu1.commit.committedOps 50978714 # Number of ops (including micro ops) committed 2507system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2508system.cpu1.commit.refs 16524628 # Number of memory references committed 2509system.cpu1.commit.loads 9966511 # Number of loads committed 2510system.cpu1.commit.membars 209715 # Number of memory barriers committed 2511system.cpu1.commit.branches 11639820 # Number of branches committed 2512system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. 2513system.cpu1.commit.int_insts 45828641 # Number of committed integer instructions. 2514system.cpu1.commit.function_calls 3366594 # Number of function calls committed. 2515system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2516system.cpu1.commit.op_class_0::IntAlu 34405110 67.49% 67.49% # Class of committed instruction 2517system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction 2518system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction 2519system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction 2520system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction 2521system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction 2522system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction 2523system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction 2524system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction 2525system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction 2526system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.58% # Class of committed instruction 2527system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.58% # Class of committed instruction 2528system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.58% # Class of committed instruction 2529system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.58% # Class of committed instruction 2530system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.58% # Class of committed instruction 2531system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.58% # Class of committed instruction 2532system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.58% # Class of committed instruction 2533system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.58% # Class of committed instruction 2534system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.58% # Class of committed instruction 2535system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.58% # Class of committed instruction 2536system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.58% # Class of committed instruction 2537system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction 2538system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction 2539system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction 2540system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction 2541system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction 2542system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction 2543system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction 2544system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction 2545system.cpu1.commit.op_class_0::MemRead 9966511 19.55% 87.14% # Class of committed instruction 2546system.cpu1.commit.op_class_0::MemWrite 6558117 12.86% 100.00% # Class of committed instruction 2547system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2548system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2549system.cpu1.commit.op_class_0::total 50978714 # Class of committed instruction 2550system.cpu1.commit.bw_lim_events 391067 # number cycles where commit BW limit reached 2551system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 2552system.cpu1.rob.rob_reads 136550879 # The number of ROB reads 2553system.cpu1.rob.rob_writes 111203214 # The number of ROB writes 2554system.cpu1.timesIdled 53373 # Number of times that the entire CPU went into an idle state and unscheduled itself 2555system.cpu1.idleCycles 341555 # Total number of cycles that the CPU has spent unscheduled due to idling 2556system.cpu1.quiesceCycles 5543525682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2557system.cpu1.committedInsts 41360016 # Number of Instructions Simulated 2558system.cpu1.committedOps 50945860 # Number of Ops (including micro ops) Simulated 2559system.cpu1.cpi 2.529357 # CPI: Cycles Per Instruction 2560system.cpu1.cpi_total 2.529357 # CPI: Total CPI of All Threads 2561system.cpu1.ipc 0.395357 # IPC: Instructions Per Cycle 2562system.cpu1.ipc_total 0.395357 # IPC: Total IPC of All Threads 2563system.cpu1.int_regfile_reads 56284604 # number of integer regfile reads 2564system.cpu1.int_regfile_writes 35740768 # number of integer regfile writes 2565system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads 2566system.cpu1.fp_regfile_writes 520 # number of floating regfile writes 2567system.cpu1.cc_regfile_reads 191160889 # number of cc regfile reads 2568system.cpu1.cc_regfile_writes 15560745 # number of cc regfile writes 2569system.cpu1.misc_regfile_reads 205861724 # number of misc regfile reads 2570system.cpu1.misc_regfile_writes 388836 # number of misc regfile writes 2571system.cpu1.toL2Bus.trans_dist::ReadReq 1295167 # Transaction distribution 2572system.cpu1.toL2Bus.trans_dist::ReadResp 865146 # Transaction distribution 2573system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution 2574system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution 2575system.cpu1.toL2Bus.trans_dist::Writeback 117435 # Transaction distribution 2576system.cpu1.toL2Bus.trans_dist::HardPFReq 157667 # Transaction distribution 2577system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution 2578system.cpu1.toL2Bus.trans_dist::UpgradeReq 84819 # Transaction distribution 2579system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41863 # Transaction distribution 2580system.cpu1.toL2Bus.trans_dist::UpgradeResp 87089 # Transaction distribution 2581system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2582system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 2583system.cpu1.toL2Bus.trans_dist::ReadExReq 79490 # Transaction distribution 2584system.cpu1.toL2Bus.trans_dist::ReadExResp 66369 # Transaction distribution 2585system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215695 # Packet count per connected master and slave (bytes) 2586system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 824924 # Packet count per connected master and slave (bytes) 2587system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17344 # Packet count per connected master and slave (bytes) 2588system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37959 # Packet count per connected master and slave (bytes) 2589system.cpu1.toL2Bus.pkt_count::total 2095922 # Packet count per connected master and slave (bytes) 2590system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897296 # Cumulative packet size per connected master and slave (bytes) 2591system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25431436 # Cumulative packet size per connected master and slave (bytes) 2592system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30740 # Cumulative packet size per connected master and slave (bytes) 2593system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67228 # Cumulative packet size per connected master and slave (bytes) 2594system.cpu1.toL2Bus.pkt_size::total 64426700 # Cumulative packet size per connected master and slave (bytes) 2595system.cpu1.toL2Bus.snoops 835314 # Total snoops (count) 2596system.cpu1.toL2Bus.snoop_fanout::samples 1798151 # Request fanout histogram 2597system.cpu1.toL2Bus.snoop_fanout::mean 5.418656 # Request fanout histogram 2598system.cpu1.toL2Bus.snoop_fanout::stdev 0.493339 # Request fanout histogram 2599system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2600system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2601system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2602system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2603system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2604system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2605system.cpu1.toL2Bus.snoop_fanout::5 1045344 58.13% 58.13% # Request fanout histogram 2606system.cpu1.toL2Bus.snoop_fanout::6 752807 41.87% 100.00% # Request fanout histogram 2607system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2608system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2609system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2610system.cpu1.toL2Bus.snoop_fanout::total 1798151 # Request fanout histogram 2611system.cpu1.toL2Bus.reqLayer0.occupancy 659597923 # Layer occupancy (ticks) 2612system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2613system.cpu1.toL2Bus.snoopLayer0.occupancy 81215248 # Layer occupancy (ticks) 2614system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2615system.cpu1.toL2Bus.respLayer0.occupancy 913005612 # Layer occupancy (ticks) 2616system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2617system.cpu1.toL2Bus.respLayer1.occupancy 403790804 # Layer occupancy (ticks) 2618system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2619system.cpu1.toL2Bus.respLayer2.occupancy 9801715 # Layer occupancy (ticks) 2620system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2621system.cpu1.toL2Bus.respLayer3.occupancy 21218619 # Layer occupancy (ticks) 2622system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2623system.cpu1.icache.tags.replacements 607233 # number of replacements 2624system.cpu1.icache.tags.tagsinuse 499.524677 # Cycle average of tags in use 2625system.cpu1.icache.tags.total_refs 43016935 # Total number of references to valid blocks. 2626system.cpu1.icache.tags.sampled_refs 607745 # Sample count of references to valid blocks. 2627system.cpu1.icache.tags.avg_refs 70.781224 # Average number of references to valid blocks. 2628system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit. 2629system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524677 # Average occupied blocks per requestor 2630system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975634 # Average percentage of cache occupancy 2631system.cpu1.icache.tags.occ_percent::total 0.975634 # Average percentage of cache occupancy 2632system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2633system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2634system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2635system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2636system.cpu1.icache.tags.tag_accesses 87890334 # Number of tag accesses 2637system.cpu1.icache.tags.data_accesses 87890334 # Number of data accesses 2638system.cpu1.icache.ReadReq_hits::cpu1.inst 43016935 # number of ReadReq hits 2639system.cpu1.icache.ReadReq_hits::total 43016935 # number of ReadReq hits 2640system.cpu1.icache.demand_hits::cpu1.inst 43016935 # number of demand (read+write) hits 2641system.cpu1.icache.demand_hits::total 43016935 # number of demand (read+write) hits 2642system.cpu1.icache.overall_hits::cpu1.inst 43016935 # number of overall hits 2643system.cpu1.icache.overall_hits::total 43016935 # number of overall hits 2644system.cpu1.icache.ReadReq_misses::cpu1.inst 624358 # number of ReadReq misses 2645system.cpu1.icache.ReadReq_misses::total 624358 # number of ReadReq misses 2646system.cpu1.icache.demand_misses::cpu1.inst 624358 # number of demand (read+write) misses 2647system.cpu1.icache.demand_misses::total 624358 # number of demand (read+write) misses 2648system.cpu1.icache.overall_misses::cpu1.inst 624358 # number of overall misses 2649system.cpu1.icache.overall_misses::total 624358 # number of overall misses 2650system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5094140300 # number of ReadReq miss cycles 2651system.cpu1.icache.ReadReq_miss_latency::total 5094140300 # number of ReadReq miss cycles 2652system.cpu1.icache.demand_miss_latency::cpu1.inst 5094140300 # number of demand (read+write) miss cycles 2653system.cpu1.icache.demand_miss_latency::total 5094140300 # number of demand (read+write) miss cycles 2654system.cpu1.icache.overall_miss_latency::cpu1.inst 5094140300 # number of overall miss cycles 2655system.cpu1.icache.overall_miss_latency::total 5094140300 # number of overall miss cycles 2656system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641293 # number of ReadReq accesses(hits+misses) 2657system.cpu1.icache.ReadReq_accesses::total 43641293 # number of ReadReq accesses(hits+misses) 2658system.cpu1.icache.demand_accesses::cpu1.inst 43641293 # number of demand (read+write) accesses 2659system.cpu1.icache.demand_accesses::total 43641293 # number of demand (read+write) accesses 2660system.cpu1.icache.overall_accesses::cpu1.inst 43641293 # number of overall (read+write) accesses 2661system.cpu1.icache.overall_accesses::total 43641293 # number of overall (read+write) accesses 2662system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014307 # miss rate for ReadReq accesses 2663system.cpu1.icache.ReadReq_miss_rate::total 0.014307 # miss rate for ReadReq accesses 2664system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014307 # miss rate for demand accesses 2665system.cpu1.icache.demand_miss_rate::total 0.014307 # miss rate for demand accesses 2666system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014307 # miss rate for overall accesses 2667system.cpu1.icache.overall_miss_rate::total 0.014307 # miss rate for overall accesses 2668system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8159.005410 # average ReadReq miss latency 2669system.cpu1.icache.ReadReq_avg_miss_latency::total 8159.005410 # average ReadReq miss latency 2670system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency 2671system.cpu1.icache.demand_avg_miss_latency::total 8159.005410 # average overall miss latency 2672system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency 2673system.cpu1.icache.overall_avg_miss_latency::total 8159.005410 # average overall miss latency 2674system.cpu1.icache.blocked_cycles::no_mshrs 274240 # number of cycles access was blocked 2675system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2676system.cpu1.icache.blocked::no_mshrs 36121 # number of cycles access was blocked 2677system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2678system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.592259 # average number of cycles each access was blocked 2679system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2680system.cpu1.icache.fast_writes 0 # number of fast writes performed 2681system.cpu1.icache.cache_copies 0 # number of cache copies performed 2682system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16610 # number of ReadReq MSHR hits 2683system.cpu1.icache.ReadReq_mshr_hits::total 16610 # number of ReadReq MSHR hits 2684system.cpu1.icache.demand_mshr_hits::cpu1.inst 16610 # number of demand (read+write) MSHR hits 2685system.cpu1.icache.demand_mshr_hits::total 16610 # number of demand (read+write) MSHR hits 2686system.cpu1.icache.overall_mshr_hits::cpu1.inst 16610 # number of overall MSHR hits 2687system.cpu1.icache.overall_mshr_hits::total 16610 # number of overall MSHR hits 2688system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607748 # number of ReadReq MSHR misses 2689system.cpu1.icache.ReadReq_mshr_misses::total 607748 # number of ReadReq MSHR misses 2690system.cpu1.icache.demand_mshr_misses::cpu1.inst 607748 # number of demand (read+write) MSHR misses 2691system.cpu1.icache.demand_mshr_misses::total 607748 # number of demand (read+write) MSHR misses 2692system.cpu1.icache.overall_mshr_misses::cpu1.inst 607748 # number of overall MSHR misses 2693system.cpu1.icache.overall_mshr_misses::total 607748 # number of overall MSHR misses 2694system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4102836710 # number of ReadReq MSHR miss cycles 2695system.cpu1.icache.ReadReq_mshr_miss_latency::total 4102836710 # number of ReadReq MSHR miss cycles 2696system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4102836710 # number of demand (read+write) MSHR miss cycles 2697system.cpu1.icache.demand_mshr_miss_latency::total 4102836710 # number of demand (read+write) MSHR miss cycles 2698system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4102836710 # number of overall MSHR miss cycles 2699system.cpu1.icache.overall_mshr_miss_latency::total 4102836710 # number of overall MSHR miss cycles 2700system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles 2701system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles 2702system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles 2703system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles 2704system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses 2705system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses 2706system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses 2707system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses 2708system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses 2709system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses 2710system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average ReadReq mshr miss latency 2711system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6750.884758 # average ReadReq mshr miss latency 2712system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency 2713system.cpu1.icache.demand_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency 2714system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency 2715system.cpu1.icache.overall_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency 2716system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2717system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2718system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2719system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2720system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2721system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841881 # number of hwpf identified 2722system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43251 # number of hwpf that were already in mshr 2723system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4640074 # number of hwpf that were already in the cache 2724system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42977 # number of hwpf that were already in the prefetch queue 2725system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 2726system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6024 # number of hwpf removed because MSHR allocated 2727system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109555 # number of hwpf issued 2728system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564023 # number of hwpf spanning a virtual page 2729system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 2730system.cpu1.l2cache.tags.replacements 85866 # number of replacements 2731system.cpu1.l2cache.tags.tagsinuse 15600.635673 # Cycle average of tags in use 2732system.cpu1.l2cache.tags.total_refs 846675 # Total number of references to valid blocks. 2733system.cpu1.l2cache.tags.sampled_refs 100980 # Sample count of references to valid blocks. 2734system.cpu1.l2cache.tags.avg_refs 8.384581 # Average number of references to valid blocks. 2735system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2736system.cpu1.l2cache.tags.occ_blocks::writebacks 6012.739780 # Average occupied blocks per requestor 2737system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.101116 # Average occupied blocks per requestor 2738system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.182282 # Average occupied blocks per requestor 2739system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 726.495477 # Average occupied blocks per requestor 2740system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1966.711133 # Average occupied blocks per requestor 2741system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.405886 # Average occupied blocks per requestor 2742system.cpu1.l2cache.tags.occ_percent::writebacks 0.366989 # Average percentage of cache occupancy 2743system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000555 # Average percentage of cache occupancy 2744system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000072 # Average percentage of cache occupancy 2745system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.044342 # Average percentage of cache occupancy 2746system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.120039 # Average percentage of cache occupancy 2747system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.420191 # Average percentage of cache occupancy 2748system.cpu1.l2cache.tags.occ_percent::total 0.952187 # Average percentage of cache occupancy 2749system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9526 # Occupied blocks per task id 2750system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id 2751system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5563 # Occupied blocks per task id 2752system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id 2753system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8131 # Occupied blocks per task id 2754system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1089 # Occupied blocks per task id 2755system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 2756system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 2757system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 2758system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 415 # Occupied blocks per task id 2759system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4194 # Occupied blocks per task id 2760system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 954 # Occupied blocks per task id 2761system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.581421 # Percentage of cache occupancy per task id 2762system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id 2763system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.339539 # Percentage of cache occupancy per task id 2764system.cpu1.l2cache.tags.tag_accesses 16877479 # Number of tag accesses 2765system.cpu1.l2cache.tags.data_accesses 16877479 # Number of data accesses 2766system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16335 # number of ReadReq hits 2767system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7409 # number of ReadReq hits 2768system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601802 # number of ReadReq hits 2769system.cpu1.l2cache.ReadReq_hits::cpu1.data 101305 # number of ReadReq hits 2770system.cpu1.l2cache.ReadReq_hits::total 726851 # number of ReadReq hits 2771system.cpu1.l2cache.Writeback_hits::writebacks 117435 # number of Writeback hits 2772system.cpu1.l2cache.Writeback_hits::total 117435 # number of Writeback hits 2773system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2252 # number of UpgradeReq hits 2774system.cpu1.l2cache.UpgradeReq_hits::total 2252 # number of UpgradeReq hits 2775system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 837 # number of SCUpgradeReq hits 2776system.cpu1.l2cache.SCUpgradeReq_hits::total 837 # number of SCUpgradeReq hits 2777system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28910 # number of ReadExReq hits 2778system.cpu1.l2cache.ReadExReq_hits::total 28910 # number of ReadExReq hits 2779system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16335 # number of demand (read+write) hits 2780system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7409 # number of demand (read+write) hits 2781system.cpu1.l2cache.demand_hits::cpu1.inst 601802 # number of demand (read+write) hits 2782system.cpu1.l2cache.demand_hits::cpu1.data 130215 # number of demand (read+write) hits 2783system.cpu1.l2cache.demand_hits::total 755761 # number of demand (read+write) hits 2784system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16335 # number of overall hits 2785system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7409 # number of overall hits 2786system.cpu1.l2cache.overall_hits::cpu1.inst 601802 # number of overall hits 2787system.cpu1.l2cache.overall_hits::cpu1.data 130215 # number of overall hits 2788system.cpu1.l2cache.overall_hits::total 755761 # number of overall hits 2789system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses 2790system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses 2791system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5943 # number of ReadReq misses 2792system.cpu1.l2cache.ReadReq_misses::cpu1.data 72078 # number of ReadReq misses 2793system.cpu1.l2cache.ReadReq_misses::total 78769 # number of ReadReq misses 2794system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28388 # number of UpgradeReq misses 2795system.cpu1.l2cache.UpgradeReq_misses::total 28388 # number of UpgradeReq misses 2796system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22558 # number of SCUpgradeReq misses 2797system.cpu1.l2cache.SCUpgradeReq_misses::total 22558 # number of SCUpgradeReq misses 2798system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2799system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 2800system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32913 # number of ReadExReq misses 2801system.cpu1.l2cache.ReadExReq_misses::total 32913 # number of ReadExReq misses 2802system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses 2803system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses 2804system.cpu1.l2cache.demand_misses::cpu1.inst 5943 # number of demand (read+write) misses 2805system.cpu1.l2cache.demand_misses::cpu1.data 104991 # number of demand (read+write) misses 2806system.cpu1.l2cache.demand_misses::total 111682 # number of demand (read+write) misses 2807system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses 2808system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses 2809system.cpu1.l2cache.overall_misses::cpu1.inst 5943 # number of overall misses 2810system.cpu1.l2cache.overall_misses::cpu1.data 104991 # number of overall misses 2811system.cpu1.l2cache.overall_misses::total 111682 # number of overall misses 2812system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10433249 # number of ReadReq miss cycles 2813system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5666498 # number of ReadReq miss cycles 2814system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 181785702 # number of ReadReq miss cycles 2815system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1611031625 # number of ReadReq miss cycles 2816system.cpu1.l2cache.ReadReq_miss_latency::total 1808917074 # number of ReadReq miss cycles 2817system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536972883 # number of UpgradeReq miss cycles 2818system.cpu1.l2cache.UpgradeReq_miss_latency::total 536972883 # number of UpgradeReq miss cycles 2819system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442531028 # number of SCUpgradeReq miss cycles 2820system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442531028 # number of SCUpgradeReq miss cycles 2821system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 437999 # number of SCUpgradeFailReq miss cycles 2822system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 437999 # number of SCUpgradeFailReq miss cycles 2823system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1278690285 # number of ReadExReq miss cycles 2824system.cpu1.l2cache.ReadExReq_miss_latency::total 1278690285 # number of ReadExReq miss cycles 2825system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10433249 # number of demand (read+write) miss cycles 2826system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5666498 # number of demand (read+write) miss cycles 2827system.cpu1.l2cache.demand_miss_latency::cpu1.inst 181785702 # number of demand (read+write) miss cycles 2828system.cpu1.l2cache.demand_miss_latency::cpu1.data 2889721910 # number of demand (read+write) miss cycles 2829system.cpu1.l2cache.demand_miss_latency::total 3087607359 # number of demand (read+write) miss cycles 2830system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10433249 # number of overall miss cycles 2831system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5666498 # number of overall miss cycles 2832system.cpu1.l2cache.overall_miss_latency::cpu1.inst 181785702 # number of overall miss cycles 2833system.cpu1.l2cache.overall_miss_latency::cpu1.data 2889721910 # number of overall miss cycles 2834system.cpu1.l2cache.overall_miss_latency::total 3087607359 # number of overall miss cycles 2835system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16807 # number of ReadReq accesses(hits+misses) 2836system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7685 # number of ReadReq accesses(hits+misses) 2837system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607745 # number of ReadReq accesses(hits+misses) 2838system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173383 # number of ReadReq accesses(hits+misses) 2839system.cpu1.l2cache.ReadReq_accesses::total 805620 # number of ReadReq accesses(hits+misses) 2840system.cpu1.l2cache.Writeback_accesses::writebacks 117435 # number of Writeback accesses(hits+misses) 2841system.cpu1.l2cache.Writeback_accesses::total 117435 # number of Writeback accesses(hits+misses) 2842system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30640 # number of UpgradeReq accesses(hits+misses) 2843system.cpu1.l2cache.UpgradeReq_accesses::total 30640 # number of UpgradeReq accesses(hits+misses) 2844system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23395 # number of SCUpgradeReq accesses(hits+misses) 2845system.cpu1.l2cache.SCUpgradeReq_accesses::total 23395 # number of SCUpgradeReq accesses(hits+misses) 2846system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2847system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 2848system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61823 # number of ReadExReq accesses(hits+misses) 2849system.cpu1.l2cache.ReadExReq_accesses::total 61823 # number of ReadExReq accesses(hits+misses) 2850system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16807 # number of demand (read+write) accesses 2851system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7685 # number of demand (read+write) accesses 2852system.cpu1.l2cache.demand_accesses::cpu1.inst 607745 # number of demand (read+write) accesses 2853system.cpu1.l2cache.demand_accesses::cpu1.data 235206 # number of demand (read+write) accesses 2854system.cpu1.l2cache.demand_accesses::total 867443 # number of demand (read+write) accesses 2855system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16807 # number of overall (read+write) accesses 2856system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7685 # number of overall (read+write) accesses 2857system.cpu1.l2cache.overall_accesses::cpu1.inst 607745 # number of overall (read+write) accesses 2858system.cpu1.l2cache.overall_accesses::cpu1.data 235206 # number of overall (read+write) accesses 2859system.cpu1.l2cache.overall_accesses::total 867443 # number of overall (read+write) accesses 2860system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for ReadReq accesses 2861system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035914 # miss rate for ReadReq accesses 2862system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009779 # miss rate for ReadReq accesses 2863system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415715 # miss rate for ReadReq accesses 2864system.cpu1.l2cache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses 2865system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926501 # miss rate for UpgradeReq accesses 2866system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926501 # miss rate for UpgradeReq accesses 2867system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964223 # miss rate for SCUpgradeReq accesses 2868system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964223 # miss rate for SCUpgradeReq accesses 2869system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2870system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2871system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532375 # miss rate for ReadExReq accesses 2872system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532375 # miss rate for ReadExReq accesses 2873system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for demand accesses 2874system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035914 # miss rate for demand accesses 2875system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009779 # miss rate for demand accesses 2876system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446379 # miss rate for demand accesses 2877system.cpu1.l2cache.demand_miss_rate::total 0.128749 # miss rate for demand accesses 2878system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for overall accesses 2879system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035914 # miss rate for overall accesses 2880system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009779 # miss rate for overall accesses 2881system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446379 # miss rate for overall accesses 2882system.cpu1.l2cache.overall_miss_rate::total 0.128749 # miss rate for overall accesses 2883system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average ReadReq miss latency 2884system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20530.789855 # average ReadReq miss latency 2885system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30588.204947 # average ReadReq miss latency 2886system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22351.225409 # average ReadReq miss latency 2887system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22964.834821 # average ReadReq miss latency 2888system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18915.488340 # average UpgradeReq miss latency 2889system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18915.488340 # average UpgradeReq miss latency 2890system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19617.476195 # average SCUpgradeReq miss latency 2891system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.476195 # average SCUpgradeReq miss latency 2892system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 218999.500000 # average SCUpgradeFailReq miss latency 2893system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 218999.500000 # average SCUpgradeFailReq miss latency 2894system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38850.614803 # average ReadExReq miss latency 2895system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38850.614803 # average ReadExReq miss latency 2896system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency 2897system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency 2898system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency 2899system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency 2900system.cpu1.l2cache.demand_avg_miss_latency::total 27646.418931 # average overall miss latency 2901system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency 2902system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency 2903system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency 2904system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency 2905system.cpu1.l2cache.overall_avg_miss_latency::total 27646.418931 # average overall miss latency 2906system.cpu1.l2cache.blocked_cycles::no_mshrs 22060 # number of cycles access was blocked 2907system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2908system.cpu1.l2cache.blocked::no_mshrs 480 # number of cycles access was blocked 2909system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2910system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.958333 # average number of cycles each access was blocked 2911system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2912system.cpu1.l2cache.fast_writes 0 # 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number of demand (read+write) MSHR hits 2925system.cpu1.l2cache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits 2926system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits 2927system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1367 # number of overall MSHR hits 2928system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1321 # number of overall MSHR hits 2929system.cpu1.l2cache.overall_mshr_hits::total 2702 # number of overall MSHR hits 2930system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 472 # number of ReadReq MSHR misses 2931system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses 2932system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4576 # number of ReadReq MSHR misses 2933system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71994 # number of ReadReq MSHR misses 2934system.cpu1.l2cache.ReadReq_mshr_misses::total 77304 # number of ReadReq MSHR misses 2935system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of HardPFReq MSHR misses 2936system.cpu1.l2cache.HardPFReq_mshr_misses::total 109552 # number of HardPFReq MSHR misses 2937system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28388 # number of UpgradeReq MSHR misses 2938system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28388 # number of UpgradeReq MSHR misses 2939system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22558 # number of SCUpgradeReq MSHR misses 2940system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22558 # number of SCUpgradeReq MSHR misses 2941system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2942system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2943system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31676 # number of ReadExReq MSHR misses 2944system.cpu1.l2cache.ReadExReq_mshr_misses::total 31676 # number of ReadExReq MSHR misses 2945system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 472 # number of demand (read+write) MSHR misses 2946system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses 2947system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4576 # number of demand (read+write) MSHR misses 2948system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103670 # number of demand (read+write) MSHR misses 2949system.cpu1.l2cache.demand_mshr_misses::total 108980 # number of demand (read+write) MSHR misses 2950system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 472 # number of overall MSHR misses 2951system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses 2952system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4576 # number of overall MSHR misses 2953system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103670 # number of overall MSHR misses 2954system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of overall MSHR misses 2955system.cpu1.l2cache.overall_mshr_misses::total 218532 # number of overall MSHR misses 2956system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of ReadReq MSHR miss cycles 2957system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3660000 # number of ReadReq MSHR miss cycles 2958system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 123437534 # number of ReadReq MSHR miss cycles 2959system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105460943 # number of ReadReq MSHR miss cycles 2960system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1239685228 # number of ReadReq MSHR miss cycles 2961system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of HardPFReq MSHR miss cycles 2962system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3461172800 # number of HardPFReq MSHR miss cycles 2963system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 416881074 # number of UpgradeReq MSHR miss cycles 2964system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 416881074 # number of UpgradeReq MSHR miss cycles 2965system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308366284 # number of SCUpgradeReq MSHR miss cycles 2966system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308366284 # number of SCUpgradeReq MSHR miss cycles 2967system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 367999 # number of SCUpgradeFailReq MSHR miss cycles 2968system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 367999 # number of SCUpgradeFailReq MSHR miss cycles 2969system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944446910 # number of ReadExReq MSHR miss cycles 2970system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944446910 # number of ReadExReq MSHR miss cycles 2971system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of demand (read+write) MSHR miss cycles 2972system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3660000 # number of demand (read+write) MSHR miss cycles 2973system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 123437534 # number of demand (read+write) MSHR miss cycles 2974system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2049907853 # number of demand (read+write) MSHR miss cycles 2975system.cpu1.l2cache.demand_mshr_miss_latency::total 2184132138 # number of demand (read+write) MSHR miss cycles 2976system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of overall MSHR miss cycles 2977system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3660000 # number of overall MSHR miss cycles 2978system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 123437534 # number of overall MSHR miss cycles 2979system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2049907853 # number of overall MSHR miss cycles 2980system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of overall MSHR miss cycles 2981system.cpu1.l2cache.overall_mshr_miss_latency::total 5645304938 # number of overall MSHR miss cycles 2982system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles 2983system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182190507 # number of ReadReq MSHR uncacheable cycles 2984system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189531257 # number of ReadReq MSHR uncacheable cycles 2985system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737661499 # number of WriteReq MSHR uncacheable cycles 2986system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737661499 # number of WriteReq MSHR uncacheable cycles 2987system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles 2988system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919852006 # number of overall MSHR uncacheable cycles 2989system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927192756 # number of overall MSHR uncacheable cycles 2990system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for ReadReq accesses 2991system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for ReadReq accesses 2992system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for ReadReq accesses 2993system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415231 # mshr miss rate for ReadReq accesses 2994system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.095956 # mshr miss rate for ReadReq accesses 2995system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2996system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2997system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926501 # mshr miss rate for UpgradeReq accesses 2998system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926501 # mshr miss rate for UpgradeReq accesses 2999system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964223 # mshr miss rate for SCUpgradeReq accesses 3000system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964223 # mshr miss rate for SCUpgradeReq accesses 3001system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 3002system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 3003system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512366 # mshr miss rate for ReadExReq accesses 3004system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512366 # mshr miss rate for ReadExReq accesses 3005system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for demand accesses 3006system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for demand accesses 3007system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for demand accesses 3008system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for demand accesses 3009system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125634 # mshr miss rate for demand accesses 3010system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for overall accesses 3011system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for overall accesses 3012system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for overall accesses 3013system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for overall accesses 3014system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 3015system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251927 # mshr miss rate for overall accesses 3016system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average ReadReq mshr miss latency 3017system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average ReadReq mshr miss latency 3018system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average ReadReq mshr miss latency 3019system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15354.903784 # average ReadReq mshr miss latency 3020system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.495240 # average ReadReq mshr miss latency 3021system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average HardPFReq mshr miss latency 3022system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31593.880532 # average HardPFReq mshr miss latency 3023system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14685.116035 # average UpgradeReq mshr miss latency 3024system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14685.116035 # average UpgradeReq mshr miss latency 3025system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.930136 # average SCUpgradeReq mshr miss latency 3026system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.930136 # average SCUpgradeReq mshr miss latency 3027system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183999.500000 # average SCUpgradeFailReq mshr miss latency 3028system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183999.500000 # average SCUpgradeFailReq mshr miss latency 3029system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29815.851433 # average ReadExReq mshr miss latency 3030system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29815.851433 # average ReadExReq mshr miss latency 3031system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency 3032system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency 3033system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency 3034system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency 3035system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20041.586878 # average overall mshr miss latency 3036system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency 3037system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency 3038system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency 3039system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency 3040system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average overall mshr miss latency 3041system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25832.852571 # average overall mshr miss latency 3042system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3043system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3044system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3045system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3046system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3047system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3048system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3049system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3050system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3051system.cpu1.dcache.tags.replacements 191071 # number of replacements 3052system.cpu1.dcache.tags.tagsinuse 472.558673 # Cycle average of tags in use 3053system.cpu1.dcache.tags.total_refs 15741841 # Total number of references to valid blocks. 3054system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. 3055system.cpu1.dcache.tags.avg_refs 82.247922 # Average number of references to valid blocks. 3056system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. 3057system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558673 # Average occupied blocks per requestor 3058system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy 3059system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy 3060system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id 3061system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 3062system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 3063system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id 3064system.cpu1.dcache.tags.tag_accesses 32983753 # Number of tag accesses 3065system.cpu1.dcache.tags.data_accesses 32983753 # Number of data accesses 3066system.cpu1.dcache.ReadReq_hits::cpu1.data 9574420 # number of ReadReq hits 3067system.cpu1.dcache.ReadReq_hits::total 9574420 # number of ReadReq hits 3068system.cpu1.dcache.WriteReq_hits::cpu1.data 5910665 # number of WriteReq hits 3069system.cpu1.dcache.WriteReq_hits::total 5910665 # number of WriteReq hits 3070system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49536 # number of SoftPFReq hits 3071system.cpu1.dcache.SoftPFReq_hits::total 49536 # number of SoftPFReq hits 3072system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79144 # number of LoadLockedReq hits 3073system.cpu1.dcache.LoadLockedReq_hits::total 79144 # number of LoadLockedReq hits 3074system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71002 # number of StoreCondReq hits 3075system.cpu1.dcache.StoreCondReq_hits::total 71002 # number of StoreCondReq hits 3076system.cpu1.dcache.demand_hits::cpu1.data 15485085 # number of demand (read+write) hits 3077system.cpu1.dcache.demand_hits::total 15485085 # number of demand (read+write) hits 3078system.cpu1.dcache.overall_hits::cpu1.data 15534621 # number of overall hits 3079system.cpu1.dcache.overall_hits::total 15534621 # number of overall hits 3080system.cpu1.dcache.ReadReq_misses::cpu1.data 219558 # number of ReadReq misses 3081system.cpu1.dcache.ReadReq_misses::total 219558 # number of ReadReq misses 3082system.cpu1.dcache.WriteReq_misses::cpu1.data 398300 # number of WriteReq misses 3083system.cpu1.dcache.WriteReq_misses::total 398300 # number of WriteReq misses 3084system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30127 # number of SoftPFReq misses 3085system.cpu1.dcache.SoftPFReq_misses::total 30127 # number of SoftPFReq misses 3086system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18119 # number of LoadLockedReq misses 3087system.cpu1.dcache.LoadLockedReq_misses::total 18119 # number of LoadLockedReq misses 3088system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23397 # number of StoreCondReq misses 3089system.cpu1.dcache.StoreCondReq_misses::total 23397 # number of StoreCondReq misses 3090system.cpu1.dcache.demand_misses::cpu1.data 617858 # number of demand (read+write) misses 3091system.cpu1.dcache.demand_misses::total 617858 # number of demand (read+write) misses 3092system.cpu1.dcache.overall_misses::cpu1.data 647985 # number of overall misses 3093system.cpu1.dcache.overall_misses::total 647985 # number of overall misses 3094system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453411003 # number of ReadReq miss cycles 3095system.cpu1.dcache.ReadReq_miss_latency::total 3453411003 # number of ReadReq miss cycles 3096system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8719629262 # number of WriteReq miss cycles 3097system.cpu1.dcache.WriteReq_miss_latency::total 8719629262 # number of WriteReq miss cycles 3098system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362936751 # number of LoadLockedReq miss cycles 3099system.cpu1.dcache.LoadLockedReq_miss_latency::total 362936751 # number of LoadLockedReq miss cycles 3100system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542268315 # number of StoreCondReq miss cycles 3101system.cpu1.dcache.StoreCondReq_miss_latency::total 542268315 # number of StoreCondReq miss cycles 3102system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 468000 # number of StoreCondFailReq miss cycles 3103system.cpu1.dcache.StoreCondFailReq_miss_latency::total 468000 # number of StoreCondFailReq miss cycles 3104system.cpu1.dcache.demand_miss_latency::cpu1.data 12173040265 # number of demand (read+write) miss cycles 3105system.cpu1.dcache.demand_miss_latency::total 12173040265 # number of demand (read+write) miss cycles 3106system.cpu1.dcache.overall_miss_latency::cpu1.data 12173040265 # number of overall miss cycles 3107system.cpu1.dcache.overall_miss_latency::total 12173040265 # number of overall miss cycles 3108system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793978 # number of ReadReq accesses(hits+misses) 3109system.cpu1.dcache.ReadReq_accesses::total 9793978 # number of ReadReq accesses(hits+misses) 3110system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308965 # number of WriteReq accesses(hits+misses) 3111system.cpu1.dcache.WriteReq_accesses::total 6308965 # number of WriteReq accesses(hits+misses) 3112system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79663 # number of SoftPFReq accesses(hits+misses) 3113system.cpu1.dcache.SoftPFReq_accesses::total 79663 # number of SoftPFReq accesses(hits+misses) 3114system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97263 # number of LoadLockedReq accesses(hits+misses) 3115system.cpu1.dcache.LoadLockedReq_accesses::total 97263 # number of LoadLockedReq accesses(hits+misses) 3116system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94399 # number of StoreCondReq accesses(hits+misses) 3117system.cpu1.dcache.StoreCondReq_accesses::total 94399 # number of StoreCondReq accesses(hits+misses) 3118system.cpu1.dcache.demand_accesses::cpu1.data 16102943 # number of demand (read+write) accesses 3119system.cpu1.dcache.demand_accesses::total 16102943 # number of demand (read+write) accesses 3120system.cpu1.dcache.overall_accesses::cpu1.data 16182606 # number of overall (read+write) accesses 3121system.cpu1.dcache.overall_accesses::total 16182606 # number of overall (read+write) accesses 3122system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022418 # miss rate for ReadReq accesses 3123system.cpu1.dcache.ReadReq_miss_rate::total 0.022418 # miss rate for ReadReq accesses 3124system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063132 # miss rate for WriteReq accesses 3125system.cpu1.dcache.WriteReq_miss_rate::total 0.063132 # miss rate for WriteReq accesses 3126system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378181 # miss rate for SoftPFReq accesses 3127system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378181 # miss rate for SoftPFReq accesses 3128system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186289 # miss rate for LoadLockedReq accesses 3129system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186289 # miss rate for LoadLockedReq accesses 3130system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247852 # miss rate for StoreCondReq accesses 3131system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247852 # miss rate for StoreCondReq accesses 3132system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038369 # miss rate for demand accesses 3133system.cpu1.dcache.demand_miss_rate::total 0.038369 # miss rate for demand accesses 3134system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040042 # miss rate for overall accesses 3135system.cpu1.dcache.overall_miss_rate::total 0.040042 # miss rate for overall accesses 3136system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15728.923578 # average ReadReq miss latency 3137system.cpu1.dcache.ReadReq_avg_miss_latency::total 15728.923578 # average ReadReq miss latency 3138system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21892.114642 # average WriteReq miss latency 3139system.cpu1.dcache.WriteReq_avg_miss_latency::total 21892.114642 # average WriteReq miss latency 3140system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.727468 # average LoadLockedReq miss latency 3141system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.727468 # average LoadLockedReq miss latency 3142system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23176.831004 # average StoreCondReq miss latency 3143system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23176.831004 # average StoreCondReq miss latency 3144system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 3145system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 3146system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19702.003154 # average overall miss latency 3147system.cpu1.dcache.demand_avg_miss_latency::total 19702.003154 # average overall miss latency 3148system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18785.990825 # average overall miss latency 3149system.cpu1.dcache.overall_avg_miss_latency::total 18785.990825 # average overall miss latency 3150system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked 3151system.cpu1.dcache.blocked_cycles::no_targets 1110000 # number of cycles access was blocked 3152system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked 3153system.cpu1.dcache.blocked::no_targets 39631 # number of cycles access was blocked 3154system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked 3155system.cpu1.dcache.avg_blocked_cycles::no_targets 28.008377 # average number of cycles each access was blocked 3156system.cpu1.dcache.fast_writes 0 # number of fast writes performed 3157system.cpu1.dcache.cache_copies 0 # number of cache copies performed 3158system.cpu1.dcache.writebacks::writebacks 117436 # number of writebacks 3159system.cpu1.dcache.writebacks::total 117436 # number of writebacks 3160system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79714 # number of ReadReq MSHR hits 3161system.cpu1.dcache.ReadReq_mshr_hits::total 79714 # number of ReadReq MSHR hits 3162system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306518 # number of WriteReq MSHR hits 3163system.cpu1.dcache.WriteReq_mshr_hits::total 306518 # number of WriteReq MSHR hits 3164system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits 3165system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits 3166system.cpu1.dcache.demand_mshr_hits::cpu1.data 386232 # number of demand (read+write) MSHR hits 3167system.cpu1.dcache.demand_mshr_hits::total 386232 # number of demand (read+write) MSHR hits 3168system.cpu1.dcache.overall_mshr_hits::cpu1.data 386232 # number of overall MSHR hits 3169system.cpu1.dcache.overall_mshr_hits::total 386232 # number of overall MSHR hits 3170system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139844 # number of ReadReq MSHR misses 3171system.cpu1.dcache.ReadReq_mshr_misses::total 139844 # number of ReadReq MSHR misses 3172system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91782 # number of WriteReq MSHR misses 3173system.cpu1.dcache.WriteReq_mshr_misses::total 91782 # number of WriteReq MSHR misses 3174system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28626 # number of SoftPFReq MSHR misses 3175system.cpu1.dcache.SoftPFReq_mshr_misses::total 28626 # number of SoftPFReq MSHR misses 3176system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4932 # number of LoadLockedReq MSHR misses 3177system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4932 # number of LoadLockedReq MSHR misses 3178system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23397 # number of StoreCondReq MSHR misses 3179system.cpu1.dcache.StoreCondReq_mshr_misses::total 23397 # number of StoreCondReq MSHR misses 3180system.cpu1.dcache.demand_mshr_misses::cpu1.data 231626 # number of demand (read+write) MSHR misses 3181system.cpu1.dcache.demand_mshr_misses::total 231626 # number of demand (read+write) MSHR misses 3182system.cpu1.dcache.overall_mshr_misses::cpu1.data 260252 # number of overall MSHR misses 3183system.cpu1.dcache.overall_mshr_misses::total 260252 # number of overall MSHR misses 3184system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827153559 # number of ReadReq MSHR miss cycles 3185system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827153559 # number of ReadReq MSHR miss cycles 3186system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2193887187 # number of WriteReq MSHR miss cycles 3187system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2193887187 # number of WriteReq MSHR miss cycles 3188system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494621242 # number of SoftPFReq MSHR miss cycles 3189system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494621242 # number of SoftPFReq MSHR miss cycles 3190system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939750 # number of LoadLockedReq MSHR miss cycles 3191system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939750 # number of LoadLockedReq MSHR miss cycles 3192system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494306685 # number of StoreCondReq MSHR miss cycles 3193system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494306685 # number of StoreCondReq MSHR miss cycles 3194system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 448000 # number of StoreCondFailReq MSHR miss cycles 3195system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 448000 # number of StoreCondFailReq MSHR miss cycles 3196system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4021040746 # number of demand (read+write) MSHR miss cycles 3197system.cpu1.dcache.demand_mshr_miss_latency::total 4021040746 # number of demand (read+write) MSHR miss cycles 3198system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4515661988 # number of overall MSHR miss cycles 3199system.cpu1.dcache.overall_mshr_miss_latency::total 4515661988 # number of overall MSHR miss cycles 3200system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298831492 # number of ReadReq MSHR uncacheable cycles 3201system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298831492 # number of ReadReq MSHR uncacheable cycles 3202system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826840995 # number of WriteReq MSHR uncacheable cycles 3203system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826840995 # number of WriteReq MSHR uncacheable cycles 3204system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125672487 # number of overall MSHR uncacheable cycles 3205system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125672487 # number of overall MSHR uncacheable cycles 3206system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses 3207system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses 3208system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014548 # mshr miss rate for WriteReq accesses 3209system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014548 # mshr miss rate for WriteReq accesses 3210system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359339 # mshr miss rate for SoftPFReq accesses 3211system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359339 # mshr miss rate for SoftPFReq accesses 3212system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050708 # mshr miss rate for LoadLockedReq accesses 3213system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050708 # mshr miss rate for LoadLockedReq accesses 3214system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247852 # mshr miss rate for StoreCondReq accesses 3215system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247852 # mshr miss rate for StoreCondReq accesses 3216system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014384 # mshr miss rate for demand accesses 3217system.cpu1.dcache.demand_mshr_miss_rate::total 0.014384 # mshr miss rate for demand accesses 3218system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016082 # mshr miss rate for overall accesses 3219system.cpu1.dcache.overall_mshr_miss_rate::total 0.016082 # mshr miss rate for overall accesses 3220system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13065.655724 # average ReadReq mshr miss latency 3221system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13065.655724 # average ReadReq mshr miss latency 3222system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23903.240145 # average WriteReq mshr miss latency 3223system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23903.240145 # average WriteReq mshr miss latency 3224system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17278.741075 # average SoftPFReq mshr miss latency 3225system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17278.741075 # average SoftPFReq mshr miss latency 3226system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17627.686537 # average LoadLockedReq mshr miss latency 3227system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17627.686537 # average LoadLockedReq mshr miss latency 3228system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21126.925888 # average StoreCondReq mshr miss latency 3229system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21126.925888 # average StoreCondReq mshr miss latency 3230system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 3231system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 3232system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17360.057791 # average overall mshr miss latency 3233system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17360.057791 # average overall mshr miss latency 3234system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17351.113490 # average overall mshr miss latency 3235system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17351.113490 # average overall mshr miss latency 3236system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3237system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3238system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3239system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3240system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3241system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3242system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3243system.iocache.tags.replacements 36453 # number of replacements 3244system.iocache.tags.tagsinuse 14.560234 # Cycle average of tags in use 3245system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3246system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. 3247system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 3248system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit. 3249system.iocache.tags.occ_blocks::realview.ide 14.560234 # Average occupied blocks per requestor 3250system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy 3251system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy 3252system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3253system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3254system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3255system.iocache.tags.tag_accesses 328359 # Number of tag accesses 3256system.iocache.tags.data_accesses 328359 # Number of data accesses 3257system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 3258system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 3259system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses 3260system.iocache.ReadReq_misses::total 247 # number of ReadReq misses 3261system.iocache.WriteInvalidateReq_misses::realview.ide 15 # number of WriteInvalidateReq misses 3262system.iocache.WriteInvalidateReq_misses::total 15 # number of WriteInvalidateReq misses 3263system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses 3264system.iocache.demand_misses::total 247 # number of demand (read+write) misses 3265system.iocache.overall_misses::realview.ide 247 # number of overall misses 3266system.iocache.overall_misses::total 247 # number of overall misses 3267system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles 3268system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles 3269system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles 3270system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles 3271system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles 3272system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles 3273system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) 3274system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) 3275system.iocache.WriteInvalidateReq_accesses::realview.ide 36239 # number of WriteInvalidateReq accesses(hits+misses) 3276system.iocache.WriteInvalidateReq_accesses::total 36239 # number of WriteInvalidateReq accesses(hits+misses) 3277system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses 3278system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses 3279system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses 3280system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses 3281system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3282system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3283system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000414 # miss rate for WriteInvalidateReq accesses 3284system.iocache.WriteInvalidateReq_miss_rate::total 0.000414 # miss rate for WriteInvalidateReq accesses 3285system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3286system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3287system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3288system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3289system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency 3290system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency 3291system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency 3292system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency 3293system.iocache.overall_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency 3294system.iocache.overall_avg_miss_latency::total 124827.437247 # average overall miss latency 3295system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3296system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3297system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 3298system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3299system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3300system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3301system.iocache.fast_writes 36224 # number of fast writes performed 3302system.iocache.cache_copies 0 # number of cache copies performed 3303system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses 3304system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses 3305system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses 3306system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses 3307system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses 3308system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses 3309system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles 3310system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles 3311system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2254879547 # number of WriteInvalidateReq MSHR miss cycles 3312system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2254879547 # number of WriteInvalidateReq MSHR miss cycles 3313system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles 3314system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles 3315system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles 3316system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles 3317system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3318system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3319system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3320system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3321system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3322system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3323system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency 3324system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency 3325system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 3326system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 3327system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 3328system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency 3329system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency 3330system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency 3331system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3332system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3333system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed 3334system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3335system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed 3336 3337---------- End Simulation Statistics ---------- 3338