stats.txt revision 10220:9eab5efc02e8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.605644 # Number of seconds simulated 4sim_ticks 2605643988500 # Number of ticks simulated 5final_tick 2605643988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 56388 # Simulator instruction rate (inst/s) 8host_op_rate 72604 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2339801960 # Simulator tick rate (ticks/s) 10host_mem_usage 475216 # Number of bytes of host memory used 11host_seconds 1113.62 # Real time elapsed on the host 12sim_insts 62794806 # Number of instructions simulated 13sim_ops 80853196 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 394240 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 4377212 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 429184 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 5246712 # Number of bytes read from this memory 24system.physmem.bytes_read::total 131559796 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 394240 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 429184 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 823424 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 4275584 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 31system.physmem.bytes_written::total 7304720 # Number of bytes written to this memory 32system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 6160 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 68468 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 6706 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 82008 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15302188 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 66806 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 824090 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46480075 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 151302 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 1679896 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 164713 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 2013595 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50490319 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 151302 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 164713 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 316016 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 1640893 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::total 2803422 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 1640893 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::realview.clcd 46480075 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.inst 151302 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 1686421 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 164713 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 3169600 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 53293741 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 15302188 # Number of read requests accepted 72system.physmem.writeReqs 824090 # Number of write requests accepted 73system.physmem.readBursts 15302188 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 824090 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 974626176 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 4713856 # Total number of bytes read from write queue 77system.physmem.bytesWritten 7328128 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 131559796 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 7304720 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 73654 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 709569 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 14159 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 956238 # Per bank write bursts 84system.physmem.perBankRdBursts::1 951013 # Per bank write bursts 85system.physmem.perBankRdBursts::2 950196 # Per bank write bursts 86system.physmem.perBankRdBursts::3 950464 # Per bank write bursts 87system.physmem.perBankRdBursts::4 956634 # Per bank write bursts 88system.physmem.perBankRdBursts::5 950822 # Per bank write bursts 89system.physmem.perBankRdBursts::6 949869 # Per bank write bursts 90system.physmem.perBankRdBursts::7 949811 # Per bank write bursts 91system.physmem.perBankRdBursts::8 956681 # Per bank write bursts 92system.physmem.perBankRdBursts::9 951277 # Per bank write bursts 93system.physmem.perBankRdBursts::10 949961 # Per bank write bursts 94system.physmem.perBankRdBursts::11 949024 # Per bank write bursts 95system.physmem.perBankRdBursts::12 956331 # Per bank write bursts 96system.physmem.perBankRdBursts::13 950586 # Per bank write bursts 97system.physmem.perBankRdBursts::14 950041 # Per bank write bursts 98system.physmem.perBankRdBursts::15 949586 # Per bank write bursts 99system.physmem.perBankWrBursts::0 7062 # Per bank write bursts 100system.physmem.perBankWrBursts::1 6963 # Per bank write bursts 101system.physmem.perBankWrBursts::2 7126 # Per bank write bursts 102system.physmem.perBankWrBursts::3 7116 # Per bank write bursts 103system.physmem.perBankWrBursts::4 7811 # Per bank write bursts 104system.physmem.perBankWrBursts::5 7409 # Per bank write bursts 105system.physmem.perBankWrBursts::6 7013 # Per bank write bursts 106system.physmem.perBankWrBursts::7 7004 # Per bank write bursts 107system.physmem.perBankWrBursts::8 7458 # Per bank write bursts 108system.physmem.perBankWrBursts::9 7561 # Per bank write bursts 109system.physmem.perBankWrBursts::10 6914 # Per bank write bursts 110system.physmem.perBankWrBursts::11 6583 # Per bank write bursts 111system.physmem.perBankWrBursts::12 7179 # Per bank write bursts 112system.physmem.perBankWrBursts::13 7101 # Per bank write bursts 113system.physmem.perBankWrBursts::14 7219 # Per bank write bursts 114system.physmem.perBankWrBursts::15 6983 # Per bank write bursts 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 117system.physmem.totGap 2605642823000 # Total gap between requests 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 109 # Read request sizes (log2) 121system.physmem.readPktSize::3 15138816 # Read request sizes (log2) 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) 124system.physmem.readPktSize::6 163263 # Read request sizes (log2) 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 757284 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) 131system.physmem.writePktSize::6 66806 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 1074226 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 1009957 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 967065 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 1078396 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 970167 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 1034458 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 2664402 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 2566961 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 3342237 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 136100 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 116220 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 107345 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 103465 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 19833 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 18840 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 18525 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 164system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::15 2784 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 3035 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 4735 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 6745 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 6909 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 6865 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 6844 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 6920 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 6907 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 6964 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 6810 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 6824 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 6992 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::34 96 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 228system.physmem.bytesPerActivate::samples 1012463 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::mean 969.866853 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::gmean 900.909804 # Bytes accessed per row activation 231system.physmem.bytesPerActivate::stdev 207.662919 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::0-127 24967 2.47% 2.47% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::128-255 21104 2.08% 4.55% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::256-383 8681 0.86% 5.41% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::384-511 2506 0.25% 5.66% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::512-639 2720 0.27% 5.92% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::640-767 2029 0.20% 6.12% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::768-895 8638 0.85% 6.98% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::896-1023 1014 0.10% 7.08% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1024-1151 940804 92.92% 100.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::total 1012463 # Bytes accessed per row activation 242system.physmem.rdPerTurnAround::samples 6706 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::mean 2270.880853 # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::stdev 84552.226363 # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::0-262143 6700 99.91% 99.91% # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.97% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06 1 0.01% 99.99% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06 1 0.01% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6706 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6706 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 17.074560 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 17.020748 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 1.396636 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16 3829 57.10% 57.10% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::17 48 0.72% 57.81% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::18 1779 26.53% 84.34% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::19 878 13.09% 97.44% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::20 53 0.79% 98.23% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::21 31 0.46% 98.69% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::22 34 0.51% 99.19% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::23 40 0.60% 99.79% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::24 12 0.18% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 6706 # Writes before turning the bus around for reads 269system.physmem.totQLat 395588666000 # Total ticks spent queuing 270system.physmem.totMemAccLat 681123678500 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 76142670000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 25976.81 # Average queueing delay per DRAM burst 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 274system.physmem.avgMemAccLat 44726.81 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 374.04 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 280system.physmem.busUtil 2.94 # Data bus utilization in percentage 281system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads 282system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 283system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing 284system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing 285system.physmem.readRowHits 14234195 # Number of row buffer hits during reads 286system.physmem.writeRowHits 96378 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 84.16 # Row buffer hit rate for writes 289system.physmem.avgGap 161577.45 # Average gap between requests 290system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined 291system.physmem.memoryStateTime::IDLE 2260536385250 # Time in different power states 292system.physmem.memoryStateTime::REF 87007960000 # Time in different power states 293system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 294system.physmem.memoryStateTime::ACT 258093332250 # Time in different power states 295system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 296system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 297system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 298system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 299system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 300system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 301system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 302system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 303system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 304system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 305system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) 306system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 307system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) 308system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) 309system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 310system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) 311system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) 312system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 313system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) 314system.membus.throughput 54224369 # Throughput (bytes/s) 315system.membus.trans_dist::ReadReq 16352672 # Transaction distribution 316system.membus.trans_dist::ReadResp 16352672 # Transaction distribution 317system.membus.trans_dist::WriteReq 769183 # Transaction distribution 318system.membus.trans_dist::WriteResp 769183 # Transaction distribution 319system.membus.trans_dist::Writeback 66806 # Transaction distribution 320system.membus.trans_dist::UpgradeReq 35949 # Transaction distribution 321system.membus.trans_dist::SCUpgradeReq 18292 # Transaction distribution 322system.membus.trans_dist::UpgradeResp 14159 # Transaction distribution 323system.membus.trans_dist::ReadExReq 138125 # Transaction distribution 324system.membus.trans_dist::ReadExResp 137746 # Transaction distribution 325system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976897 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.l2c.mem_side::total 4377155 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 334system.membus.pkt_count::total 34654787 # Packet count per connected master and slave (bytes) 335system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) 336system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 337system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes) 338system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 339system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) 340system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17753988 # Cumulative packet size per connected master and slave (bytes) 341system.membus.tot_pkt_size_system.l2c.mem_side::total 20178873 # Cumulative packet size per connected master and slave (bytes) 342system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 343system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 344system.membus.tot_pkt_size::total 141289401 # Cumulative packet size per connected master and slave (bytes) 345system.membus.data_through_bus 141289401 # Total data (bytes) 346system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 347system.membus.reqLayer0.occupancy 1487962500 # Layer occupancy (ticks) 348system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 349system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) 350system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 351system.membus.reqLayer2.occupancy 11808000 # Layer occupancy (ticks) 352system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 353system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 354system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 355system.membus.reqLayer5.occupancy 1796000 # Layer occupancy (ticks) 356system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 357system.membus.reqLayer6.occupancy 17659548997 # Layer occupancy (ticks) 358system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 359system.membus.respLayer1.occupancy 4847870095 # Layer occupancy (ticks) 360system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 361system.membus.respLayer2.occupancy 37379122644 # Layer occupancy (ticks) 362system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 363system.cpu_clk_domain.clock 500 # Clock period in ticks 364system.l2c.tags.replacements 72974 # number of replacements 365system.l2c.tags.tagsinuse 53023.948009 # Cycle average of tags in use 366system.l2c.tags.total_refs 1873330 # Total number of references to valid blocks. 367system.l2c.tags.sampled_refs 138152 # Sample count of references to valid blocks. 368system.l2c.tags.avg_refs 13.559920 # Average number of references to valid blocks. 369system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 370system.l2c.tags.occ_blocks::writebacks 37706.296895 # Average occupied blocks per requestor 371system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.412172 # Average occupied blocks per requestor 372system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000364 # Average occupied blocks per requestor 373system.l2c.tags.occ_blocks::cpu0.inst 4169.126027 # Average occupied blocks per requestor 374system.l2c.tags.occ_blocks::cpu0.data 2962.597547 # Average occupied blocks per requestor 375system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.621110 # Average occupied blocks per requestor 376system.l2c.tags.occ_blocks::cpu1.inst 4061.748879 # Average occupied blocks per requestor 377system.l2c.tags.occ_blocks::cpu1.data 4107.145016 # Average occupied blocks per requestor 378system.l2c.tags.occ_percent::writebacks 0.575352 # Average percentage of cache occupancy 379system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy 380system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 381system.l2c.tags.occ_percent::cpu0.inst 0.063616 # Average percentage of cache occupancy 382system.l2c.tags.occ_percent::cpu0.data 0.045206 # Average percentage of cache occupancy 383system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000177 # Average percentage of cache occupancy 384system.l2c.tags.occ_percent::cpu1.inst 0.061977 # Average percentage of cache occupancy 385system.l2c.tags.occ_percent::cpu1.data 0.062670 # Average percentage of cache occupancy 386system.l2c.tags.occ_percent::total 0.809081 # Average percentage of cache occupancy 387system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 388system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id 389system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 390system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 391system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id 392system.l2c.tags.age_task_id_blocks_1024::2 3154 # Occupied blocks per task id 393system.l2c.tags.age_task_id_blocks_1024::3 9081 # Occupied blocks per task id 394system.l2c.tags.age_task_id_blocks_1024::4 52631 # Occupied blocks per task id 395system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 396system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id 397system.l2c.tags.tag_accesses 18850449 # Number of tag accesses 398system.l2c.tags.data_accesses 18850449 # Number of data accesses 399system.l2c.ReadReq_hits::cpu0.dtb.walker 22712 # number of ReadReq hits 400system.l2c.ReadReq_hits::cpu0.itb.walker 4441 # number of ReadReq hits 401system.l2c.ReadReq_hits::cpu0.inst 393676 # number of ReadReq hits 402system.l2c.ReadReq_hits::cpu0.data 165723 # number of ReadReq hits 403system.l2c.ReadReq_hits::cpu1.dtb.walker 33196 # number of ReadReq hits 404system.l2c.ReadReq_hits::cpu1.itb.walker 5802 # number of ReadReq hits 405system.l2c.ReadReq_hits::cpu1.inst 607870 # number of ReadReq hits 406system.l2c.ReadReq_hits::cpu1.data 201576 # number of ReadReq hits 407system.l2c.ReadReq_hits::total 1434996 # number of ReadReq hits 408system.l2c.Writeback_hits::writebacks 583128 # number of Writeback hits 409system.l2c.Writeback_hits::total 583128 # number of Writeback hits 410system.l2c.UpgradeReq_hits::cpu0.data 1123 # number of UpgradeReq hits 411system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits 412system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits 413system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits 414system.l2c.SCUpgradeReq_hits::cpu1.data 158 # number of SCUpgradeReq hits 415system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits 416system.l2c.ReadExReq_hits::cpu0.data 47567 # number of ReadExReq hits 417system.l2c.ReadExReq_hits::cpu1.data 59393 # number of ReadExReq hits 418system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits 419system.l2c.demand_hits::cpu0.dtb.walker 22712 # number of demand (read+write) hits 420system.l2c.demand_hits::cpu0.itb.walker 4441 # number of demand (read+write) hits 421system.l2c.demand_hits::cpu0.inst 393676 # number of demand (read+write) hits 422system.l2c.demand_hits::cpu0.data 213290 # number of demand (read+write) hits 423system.l2c.demand_hits::cpu1.dtb.walker 33196 # number of demand (read+write) hits 424system.l2c.demand_hits::cpu1.itb.walker 5802 # number of demand (read+write) hits 425system.l2c.demand_hits::cpu1.inst 607870 # number of demand (read+write) hits 426system.l2c.demand_hits::cpu1.data 260969 # number of demand (read+write) hits 427system.l2c.demand_hits::total 1541956 # number of demand (read+write) hits 428system.l2c.overall_hits::cpu0.dtb.walker 22712 # number of overall hits 429system.l2c.overall_hits::cpu0.itb.walker 4441 # number of overall hits 430system.l2c.overall_hits::cpu0.inst 393676 # number of overall hits 431system.l2c.overall_hits::cpu0.data 213290 # number of overall hits 432system.l2c.overall_hits::cpu1.dtb.walker 33196 # number of overall hits 433system.l2c.overall_hits::cpu1.itb.walker 5802 # number of overall hits 434system.l2c.overall_hits::cpu1.inst 607870 # number of overall hits 435system.l2c.overall_hits::cpu1.data 260969 # number of overall hits 436system.l2c.overall_hits::total 1541956 # number of overall hits 437system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses 438system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 439system.l2c.ReadReq_misses::cpu0.inst 6041 # number of ReadReq misses 440system.l2c.ReadReq_misses::cpu0.data 6321 # number of ReadReq misses 441system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses 442system.l2c.ReadReq_misses::cpu1.inst 6670 # number of ReadReq misses 443system.l2c.ReadReq_misses::cpu1.data 6363 # number of ReadReq misses 444system.l2c.ReadReq_misses::total 25425 # number of ReadReq misses 445system.l2c.UpgradeReq_misses::cpu0.data 5691 # number of UpgradeReq misses 446system.l2c.UpgradeReq_misses::cpu1.data 4436 # number of UpgradeReq misses 447system.l2c.UpgradeReq_misses::total 10127 # number of UpgradeReq misses 448system.l2c.SCUpgradeReq_misses::cpu0.data 767 # number of SCUpgradeReq misses 449system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses 450system.l2c.SCUpgradeReq_misses::total 1356 # number of SCUpgradeReq misses 451system.l2c.ReadExReq_misses::cpu0.data 63545 # number of ReadExReq misses 452system.l2c.ReadExReq_misses::cpu1.data 76877 # number of ReadExReq misses 453system.l2c.ReadExReq_misses::total 140422 # number of ReadExReq misses 454system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses 455system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 456system.l2c.demand_misses::cpu0.inst 6041 # number of demand (read+write) misses 457system.l2c.demand_misses::cpu0.data 69866 # number of demand (read+write) misses 458system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses 459system.l2c.demand_misses::cpu1.inst 6670 # number of demand (read+write) misses 460system.l2c.demand_misses::cpu1.data 83240 # number of demand (read+write) misses 461system.l2c.demand_misses::total 165847 # number of demand (read+write) misses 462system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses 463system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 464system.l2c.overall_misses::cpu0.inst 6041 # number of overall misses 465system.l2c.overall_misses::cpu0.data 69866 # number of overall misses 466system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses 467system.l2c.overall_misses::cpu1.inst 6670 # number of overall misses 468system.l2c.overall_misses::cpu1.data 83240 # number of overall misses 469system.l2c.overall_misses::total 165847 # number of overall misses 470system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1149750 # number of ReadReq miss cycles 471system.l2c.ReadReq_miss_latency::cpu0.itb.walker 368000 # number of ReadReq miss cycles 472system.l2c.ReadReq_miss_latency::cpu0.inst 435967250 # number of ReadReq miss cycles 473system.l2c.ReadReq_miss_latency::cpu0.data 468270999 # number of ReadReq miss cycles 474system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1231000 # number of ReadReq miss cycles 475system.l2c.ReadReq_miss_latency::cpu1.inst 485141500 # number of ReadReq miss cycles 476system.l2c.ReadReq_miss_latency::cpu1.data 483349999 # number of ReadReq miss cycles 477system.l2c.ReadReq_miss_latency::total 1875478498 # number of ReadReq miss cycles 478system.l2c.UpgradeReq_miss_latency::cpu0.data 9144593 # number of UpgradeReq miss cycles 479system.l2c.UpgradeReq_miss_latency::cpu1.data 12320478 # number of UpgradeReq miss cycles 480system.l2c.UpgradeReq_miss_latency::total 21465071 # number of UpgradeReq miss cycles 481system.l2c.SCUpgradeReq_miss_latency::cpu0.data 441981 # number of SCUpgradeReq miss cycles 482system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3192363 # number of SCUpgradeReq miss cycles 483system.l2c.SCUpgradeReq_miss_latency::total 3634344 # number of SCUpgradeReq miss cycles 484system.l2c.ReadExReq_miss_latency::cpu0.data 4462150559 # number of ReadExReq miss cycles 485system.l2c.ReadExReq_miss_latency::cpu1.data 6003353008 # number of ReadExReq miss cycles 486system.l2c.ReadExReq_miss_latency::total 10465503567 # number of ReadExReq miss cycles 487system.l2c.demand_miss_latency::cpu0.dtb.walker 1149750 # number of demand (read+write) miss cycles 488system.l2c.demand_miss_latency::cpu0.itb.walker 368000 # number of demand (read+write) miss cycles 489system.l2c.demand_miss_latency::cpu0.inst 435967250 # number of demand (read+write) miss cycles 490system.l2c.demand_miss_latency::cpu0.data 4930421558 # number of demand (read+write) miss cycles 491system.l2c.demand_miss_latency::cpu1.dtb.walker 1231000 # number of demand (read+write) miss cycles 492system.l2c.demand_miss_latency::cpu1.inst 485141500 # number of demand (read+write) miss cycles 493system.l2c.demand_miss_latency::cpu1.data 6486703007 # number of demand (read+write) miss cycles 494system.l2c.demand_miss_latency::total 12340982065 # number of demand (read+write) miss cycles 495system.l2c.overall_miss_latency::cpu0.dtb.walker 1149750 # number of overall miss cycles 496system.l2c.overall_miss_latency::cpu0.itb.walker 368000 # number of overall miss cycles 497system.l2c.overall_miss_latency::cpu0.inst 435967250 # number of overall miss cycles 498system.l2c.overall_miss_latency::cpu0.data 4930421558 # number of overall miss cycles 499system.l2c.overall_miss_latency::cpu1.dtb.walker 1231000 # number of overall miss cycles 500system.l2c.overall_miss_latency::cpu1.inst 485141500 # number of overall miss cycles 501system.l2c.overall_miss_latency::cpu1.data 6486703007 # number of overall miss cycles 502system.l2c.overall_miss_latency::total 12340982065 # number of overall miss cycles 503system.l2c.ReadReq_accesses::cpu0.dtb.walker 22724 # number of ReadReq accesses(hits+misses) 504system.l2c.ReadReq_accesses::cpu0.itb.walker 4443 # number of ReadReq accesses(hits+misses) 505system.l2c.ReadReq_accesses::cpu0.inst 399717 # number of ReadReq accesses(hits+misses) 506system.l2c.ReadReq_accesses::cpu0.data 172044 # number of ReadReq accesses(hits+misses) 507system.l2c.ReadReq_accesses::cpu1.dtb.walker 33212 # number of ReadReq accesses(hits+misses) 508system.l2c.ReadReq_accesses::cpu1.itb.walker 5802 # number of ReadReq accesses(hits+misses) 509system.l2c.ReadReq_accesses::cpu1.inst 614540 # number of ReadReq accesses(hits+misses) 510system.l2c.ReadReq_accesses::cpu1.data 207939 # number of ReadReq accesses(hits+misses) 511system.l2c.ReadReq_accesses::total 1460421 # number of ReadReq accesses(hits+misses) 512system.l2c.Writeback_accesses::writebacks 583128 # number of Writeback accesses(hits+misses) 513system.l2c.Writeback_accesses::total 583128 # number of Writeback accesses(hits+misses) 514system.l2c.UpgradeReq_accesses::cpu0.data 6814 # number of UpgradeReq accesses(hits+misses) 515system.l2c.UpgradeReq_accesses::cpu1.data 5163 # number of UpgradeReq accesses(hits+misses) 516system.l2c.UpgradeReq_accesses::total 11977 # number of UpgradeReq accesses(hits+misses) 517system.l2c.SCUpgradeReq_accesses::cpu0.data 974 # number of SCUpgradeReq accesses(hits+misses) 518system.l2c.SCUpgradeReq_accesses::cpu1.data 747 # number of SCUpgradeReq accesses(hits+misses) 519system.l2c.SCUpgradeReq_accesses::total 1721 # number of SCUpgradeReq accesses(hits+misses) 520system.l2c.ReadExReq_accesses::cpu0.data 111112 # number of ReadExReq accesses(hits+misses) 521system.l2c.ReadExReq_accesses::cpu1.data 136270 # number of ReadExReq accesses(hits+misses) 522system.l2c.ReadExReq_accesses::total 247382 # number of ReadExReq accesses(hits+misses) 523system.l2c.demand_accesses::cpu0.dtb.walker 22724 # number of demand (read+write) accesses 524system.l2c.demand_accesses::cpu0.itb.walker 4443 # number of demand (read+write) accesses 525system.l2c.demand_accesses::cpu0.inst 399717 # number of demand (read+write) accesses 526system.l2c.demand_accesses::cpu0.data 283156 # number of demand (read+write) accesses 527system.l2c.demand_accesses::cpu1.dtb.walker 33212 # number of demand (read+write) accesses 528system.l2c.demand_accesses::cpu1.itb.walker 5802 # number of demand (read+write) accesses 529system.l2c.demand_accesses::cpu1.inst 614540 # number of demand (read+write) accesses 530system.l2c.demand_accesses::cpu1.data 344209 # number of demand (read+write) accesses 531system.l2c.demand_accesses::total 1707803 # number of demand (read+write) accesses 532system.l2c.overall_accesses::cpu0.dtb.walker 22724 # number of overall (read+write) accesses 533system.l2c.overall_accesses::cpu0.itb.walker 4443 # number of overall (read+write) accesses 534system.l2c.overall_accesses::cpu0.inst 399717 # number of overall (read+write) accesses 535system.l2c.overall_accesses::cpu0.data 283156 # number of overall (read+write) accesses 536system.l2c.overall_accesses::cpu1.dtb.walker 33212 # number of overall (read+write) accesses 537system.l2c.overall_accesses::cpu1.itb.walker 5802 # number of overall (read+write) accesses 538system.l2c.overall_accesses::cpu1.inst 614540 # number of overall (read+write) accesses 539system.l2c.overall_accesses::cpu1.data 344209 # number of overall (read+write) accesses 540system.l2c.overall_accesses::total 1707803 # number of overall (read+write) accesses 541system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for ReadReq accesses 542system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000450 # miss rate for ReadReq accesses 543system.l2c.ReadReq_miss_rate::cpu0.inst 0.015113 # miss rate for ReadReq accesses 544system.l2c.ReadReq_miss_rate::cpu0.data 0.036741 # miss rate for ReadReq accesses 545system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for ReadReq accesses 546system.l2c.ReadReq_miss_rate::cpu1.inst 0.010854 # miss rate for ReadReq accesses 547system.l2c.ReadReq_miss_rate::cpu1.data 0.030600 # miss rate for ReadReq accesses 548system.l2c.ReadReq_miss_rate::total 0.017409 # miss rate for ReadReq accesses 549system.l2c.UpgradeReq_miss_rate::cpu0.data 0.835192 # miss rate for UpgradeReq accesses 550system.l2c.UpgradeReq_miss_rate::cpu1.data 0.859190 # miss rate for UpgradeReq accesses 551system.l2c.UpgradeReq_miss_rate::total 0.845537 # miss rate for UpgradeReq accesses 552system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787474 # miss rate for SCUpgradeReq accesses 553system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.788487 # miss rate for SCUpgradeReq accesses 554system.l2c.SCUpgradeReq_miss_rate::total 0.787914 # miss rate for SCUpgradeReq accesses 555system.l2c.ReadExReq_miss_rate::cpu0.data 0.571900 # miss rate for ReadExReq accesses 556system.l2c.ReadExReq_miss_rate::cpu1.data 0.564152 # miss rate for ReadExReq accesses 557system.l2c.ReadExReq_miss_rate::total 0.567632 # miss rate for ReadExReq accesses 558system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for demand accesses 559system.l2c.demand_miss_rate::cpu0.itb.walker 0.000450 # miss rate for demand accesses 560system.l2c.demand_miss_rate::cpu0.inst 0.015113 # miss rate for demand accesses 561system.l2c.demand_miss_rate::cpu0.data 0.246740 # miss rate for demand accesses 562system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for demand accesses 563system.l2c.demand_miss_rate::cpu1.inst 0.010854 # miss rate for demand accesses 564system.l2c.demand_miss_rate::cpu1.data 0.241830 # miss rate for demand accesses 565system.l2c.demand_miss_rate::total 0.097111 # miss rate for demand accesses 566system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for overall accesses 567system.l2c.overall_miss_rate::cpu0.itb.walker 0.000450 # miss rate for overall accesses 568system.l2c.overall_miss_rate::cpu0.inst 0.015113 # miss rate for overall accesses 569system.l2c.overall_miss_rate::cpu0.data 0.246740 # miss rate for overall accesses 570system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for overall accesses 571system.l2c.overall_miss_rate::cpu1.inst 0.010854 # miss rate for overall accesses 572system.l2c.overall_miss_rate::cpu1.data 0.241830 # miss rate for overall accesses 573system.l2c.overall_miss_rate::total 0.097111 # miss rate for overall accesses 574system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average ReadReq miss latency 575system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 184000 # average ReadReq miss latency 576system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72168.059924 # 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average overall miss latency 599system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average overall miss latency 600system.l2c.overall_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency 601system.l2c.overall_avg_miss_latency::cpu0.inst 72168.059924 # average overall miss latency 602system.l2c.overall_avg_miss_latency::cpu0.data 70569.684224 # average overall miss latency 603system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76937.500000 # average overall miss latency 604system.l2c.overall_avg_miss_latency::cpu1.inst 72734.857571 # average overall miss latency 605system.l2c.overall_avg_miss_latency::cpu1.data 77927.715125 # average overall miss latency 606system.l2c.overall_avg_miss_latency::total 74411.849868 # average overall miss latency 607system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 608system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 609system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 610system.l2c.blocked::no_targets 0 # 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number of ReadReq MSHR uncacheable cycles 702system.l2c.ReadReq_mshr_uncacheable_latency::total 167226422467 # number of ReadReq MSHR uncacheable cycles 703system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1073382998 # number of WriteReq MSHR uncacheable cycles 704system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16528122341 # number of WriteReq MSHR uncacheable cycles 705system.l2c.WriteReq_mshr_uncacheable_latency::total 17601505339 # number of WriteReq MSHR uncacheable cycles 706system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6890749 # number of overall MSHR uncacheable cycles 707system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13408755986 # number of overall MSHR uncacheable cycles 708system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2843750 # number of overall MSHR uncacheable cycles 709system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171409437321 # number of overall MSHR uncacheable cycles 710system.l2c.overall_mshr_uncacheable_latency::total 184827927806 # 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average UpgradeReq mshr miss latency 754system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.668510 # average UpgradeReq mshr miss latency 755system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10014.033898 # average SCUpgradeReq mshr miss latency 756system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.541596 # average SCUpgradeReq mshr miss latency 757system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10009.476401 # average SCUpgradeReq mshr miss latency 758system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57729.104367 # average ReadExReq mshr miss latency 759system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65666.928730 # average ReadExReq mshr miss latency 760system.l2c.ReadExReq_avg_mshr_miss_latency::total 62074.834549 # average ReadExReq mshr miss latency 761system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency 762system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency 763system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency 764system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency 765system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency 766system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency 767system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency 768system.l2c.demand_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency 769system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency 770system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency 771system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency 772system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency 773system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency 774system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency 775system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency 776system.l2c.overall_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency 777system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 778system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 779system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 780system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 781system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 782system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 783system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 784system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 785system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 786system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 787system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 788system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 789system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 790system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 791system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 792system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 793system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 794system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 795system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 796system.cf0.dma_write_txs 0 # Number of DMA write transactions. 797system.toL2Bus.throughput 58718575 # Throughput (bytes/s) 798system.toL2Bus.trans_dist::ReadReq 2740966 # Transaction distribution 799system.toL2Bus.trans_dist::ReadResp 2740965 # Transaction distribution 800system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution 801system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution 802system.toL2Bus.trans_dist::Writeback 583128 # Transaction distribution 803system.toL2Bus.trans_dist::UpgradeReq 35123 # Transaction distribution 804system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution 805system.toL2Bus.trans_dist::UpgradeResp 53780 # Transaction distribution 806system.toL2Bus.trans_dist::ReadExReq 259272 # Transaction distribution 807system.toL2Bus.trans_dist::ReadExResp 259272 # Transaction distribution 808system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800244 # Packet count per connected master and slave (bytes) 809system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073141 # Packet count per connected master and slave (bytes) 810system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13760 # Packet count per connected master and slave (bytes) 811system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56807 # Packet count per connected master and slave (bytes) 812system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1229764 # Packet count per connected master and slave (bytes) 813system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820581 # Packet count per connected master and slave (bytes) 814system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15635 # Packet count per connected master and slave (bytes) 815system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75586 # Packet count per connected master and slave (bytes) 816system.toL2Bus.pkt_count::total 8085518 # Packet count per connected master and slave (bytes) 817system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25589824 # Cumulative packet size per connected master and slave (bytes) 818system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34686241 # Cumulative packet size per connected master and slave (bytes) 819system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17772 # Cumulative packet size per connected master and slave (bytes) 820system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90896 # Cumulative packet size per connected master and slave (bytes) 821system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39333696 # Cumulative packet size per connected master and slave (bytes) 822system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48239320 # Cumulative packet size per connected master and slave (bytes) 823system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23208 # Cumulative packet size per connected master and slave (bytes) 824system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132848 # Cumulative packet size per connected master and slave (bytes) 825system.toL2Bus.tot_pkt_size::total 148113805 # Cumulative packet size per connected master and slave (bytes) 826system.toL2Bus.data_through_bus 148113805 # Total data (bytes) 827system.toL2Bus.snoop_data_through_bus 4885896 # Total snoop data (bytes) 828system.toL2Bus.reqLayer0.occupancy 4921313376 # Layer occupancy (ticks) 829system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 830system.toL2Bus.respLayer0.occupancy 1803473389 # Layer occupancy (ticks) 831system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 832system.toL2Bus.respLayer1.occupancy 1514355955 # Layer occupancy (ticks) 833system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 834system.toL2Bus.respLayer2.occupancy 9338456 # Layer occupancy (ticks) 835system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 836system.toL2Bus.respLayer3.occupancy 34226949 # Layer occupancy (ticks) 837system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 838system.toL2Bus.respLayer6.occupancy 2770248418 # Layer occupancy (ticks) 839system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) 840system.toL2Bus.respLayer7.occupancy 3257977460 # Layer occupancy (ticks) 841system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) 842system.toL2Bus.respLayer8.occupancy 9851958 # Layer occupancy (ticks) 843system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 844system.toL2Bus.respLayer9.occupancy 42643941 # Layer occupancy (ticks) 845system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 846system.iobus.throughput 47398342 # Throughput (bytes/s) 847system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution 848system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution 849system.iobus.trans_dist::WriteReq 8083 # Transaction distribution 850system.iobus.trans_dist::WriteResp 8083 # Transaction distribution 851system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) 852system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8836 # Packet count per connected master and slave (bytes) 853system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 854system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) 855system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 856system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 857system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) 858system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 859system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 860system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 861system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 862system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 863system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 864system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 865system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 866system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 867system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 868system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 869system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 871system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 872system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 873system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 874system.iobus.pkt_count_system.bridge.master::total 2384364 # Packet count per connected master and slave (bytes) 875system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 876system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 877system.iobus.pkt_count::total 32661996 # Packet count per connected master and slave (bytes) 878system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) 879system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17672 # Cumulative packet size per connected master and slave (bytes) 880system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 881system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) 882system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 883system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 884system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) 885system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 886system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 887system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 888system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 889system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 890system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 891system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 892system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 893system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 894system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 895system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 898system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 900system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 901system.iobus.tot_pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.tot_pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) 905system.iobus.data_through_bus 123503205 # Total data (bytes) 906system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) 907system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 908system.iobus.reqLayer1.occupancy 4424000 # Layer occupancy (ticks) 909system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 910system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 911system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 912system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) 913system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 914system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 915system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 916system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 917system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 918system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) 919system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 920system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 921system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 922system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 923system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 924system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 925system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 926system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 927system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 928system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 929system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 930system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 931system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 932system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 933system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 934system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 935system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 936system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 937system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 938system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 939system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 940system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 941system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 942system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 943system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 944system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 945system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 946system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 947system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 948system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 949system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 950system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 951system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 952system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 953system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 954system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks) 955system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 956system.iobus.respLayer1.occupancy 38174483356 # Layer occupancy (ticks) 957system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 958system.cpu0.branchPred.lookups 6117114 # Number of BP lookups 959system.cpu0.branchPred.condPredicted 4670626 # Number of conditional branches predicted 960system.cpu0.branchPred.condIncorrect 296157 # Number of conditional branches incorrect 961system.cpu0.branchPred.BTBLookups 3842728 # Number of BTB lookups 962system.cpu0.branchPred.BTBHits 2949969 # Number of BTB hits 963system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 964system.cpu0.branchPred.BTBHitPct 76.767572 # BTB Hit Percentage 965system.cpu0.branchPred.usedRAS 683314 # Number of times the RAS was used to get a target. 966system.cpu0.branchPred.RASInCorrect 28361 # Number of incorrect RAS predictions. 967system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 968system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 969system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 970system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 971system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 972system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 973system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 974system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 975system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 976system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 977system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 978system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 979system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 980system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 981system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 982system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 983system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 984system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 985system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 986system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 987system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 988system.cpu0.dtb.inst_hits 0 # ITB inst hits 989system.cpu0.dtb.inst_misses 0 # ITB inst misses 990system.cpu0.dtb.read_hits 8969403 # DTB read hits 991system.cpu0.dtb.read_misses 29343 # DTB read misses 992system.cpu0.dtb.write_hits 5210557 # DTB write hits 993system.cpu0.dtb.write_misses 5731 # DTB write misses 994system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 995system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 996system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 997system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 998system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB 999system.cpu0.dtb.align_faults 1050 # Number of TLB faults due to alignment restrictions 1000system.cpu0.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch 1001system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1002system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions 1003system.cpu0.dtb.read_accesses 8998746 # DTB read accesses 1004system.cpu0.dtb.write_accesses 5216288 # DTB write accesses 1005system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1006system.cpu0.dtb.hits 14179960 # DTB hits 1007system.cpu0.dtb.misses 35074 # DTB misses 1008system.cpu0.dtb.accesses 14215034 # DTB accesses 1009system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1010system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1011system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1012system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1013system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1014system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1015system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1016system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1017system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1018system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1019system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1020system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1021system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1022system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1023system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1024system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1025system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1026system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1027system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1028system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1029system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1030system.cpu0.itb.inst_hits 4277605 # ITB inst hits 1031system.cpu0.itb.inst_misses 5145 # ITB inst misses 1032system.cpu0.itb.read_hits 0 # DTB read hits 1033system.cpu0.itb.read_misses 0 # DTB read misses 1034system.cpu0.itb.write_hits 0 # DTB write hits 1035system.cpu0.itb.write_misses 0 # DTB write misses 1036system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1037system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1038system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1039system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1040system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB 1041system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1042system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1043system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1044system.cpu0.itb.perms_faults 1426 # Number of TLB faults due to permissions restrictions 1045system.cpu0.itb.read_accesses 0 # DTB read accesses 1046system.cpu0.itb.write_accesses 0 # DTB write accesses 1047system.cpu0.itb.inst_accesses 4282750 # ITB inst accesses 1048system.cpu0.itb.hits 4277605 # DTB hits 1049system.cpu0.itb.misses 5145 # DTB misses 1050system.cpu0.itb.accesses 4282750 # DTB accesses 1051system.cpu0.numCycles 70248238 # number of cpu cycles simulated 1052system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1053system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1054system.cpu0.fetch.icacheStallCycles 11931842 # Number of cycles fetch is stalled on an Icache miss 1055system.cpu0.fetch.Insts 32451975 # Number of instructions fetch has processed 1056system.cpu0.fetch.Branches 6117114 # Number of branches that fetch encountered 1057system.cpu0.fetch.predictedBranches 3633283 # Number of branches that fetch has predicted taken 1058system.cpu0.fetch.Cycles 7612739 # Number of cycles fetch has run and was not squashing or blocked 1059system.cpu0.fetch.SquashCycles 1460869 # Number of cycles fetch has spent squashing 1060system.cpu0.fetch.TlbCycles 60951 # Number of cycles fetch has spent waiting for tlb 1061system.cpu0.fetch.BlockedCycles 20309232 # Number of cycles fetch has spent blocked 1062system.cpu0.fetch.MiscStallCycles 6063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1063system.cpu0.fetch.PendingTrapStallCycles 46682 # Number of stall cycles due to pending traps 1064system.cpu0.fetch.PendingQuiesceStallCycles 1377400 # Number of stall cycles due to pending quiesce instructions 1065system.cpu0.fetch.IcacheWaitRetryStallCycles 299 # Number of stall cycles due to full MSHR 1066system.cpu0.fetch.CacheLines 4276074 # Number of cache lines fetched 1067system.cpu0.fetch.IcacheSquashes 156796 # Number of outstanding Icache misses that were squashed 1068system.cpu0.fetch.ItlbSquashes 2089 # Number of outstanding ITLB misses that were squashed 1069system.cpu0.fetch.rateDist::samples 42393450 # Number of instructions fetched each cycle (Total) 1070system.cpu0.fetch.rateDist::mean 0.988978 # Number of instructions fetched each cycle (Total) 1071system.cpu0.fetch.rateDist::stdev 2.370199 # Number of instructions fetched each cycle (Total) 1072system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1073system.cpu0.fetch.rateDist::0 34788183 82.06% 82.06% # Number of instructions fetched each cycle (Total) 1074system.cpu0.fetch.rateDist::1 572054 1.35% 83.41% # Number of instructions fetched each cycle (Total) 1075system.cpu0.fetch.rateDist::2 825907 1.95% 85.36% # Number of instructions fetched each cycle (Total) 1076system.cpu0.fetch.rateDist::3 686377 1.62% 86.98% # Number of instructions fetched each cycle (Total) 1077system.cpu0.fetch.rateDist::4 779180 1.84% 88.81% # Number of instructions fetched each cycle (Total) 1078system.cpu0.fetch.rateDist::5 565083 1.33% 90.15% # Number of instructions fetched each cycle (Total) 1079system.cpu0.fetch.rateDist::6 677221 1.60% 91.75% # Number of instructions fetched each cycle (Total) 1080system.cpu0.fetch.rateDist::7 357838 0.84% 92.59% # Number of instructions fetched each cycle (Total) 1081system.cpu0.fetch.rateDist::8 3141607 7.41% 100.00% # Number of instructions fetched each cycle (Total) 1082system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1083system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1084system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1085system.cpu0.fetch.rateDist::total 42393450 # Number of instructions fetched each cycle (Total) 1086system.cpu0.fetch.branchRate 0.087079 # Number of branch fetches per cycle 1087system.cpu0.fetch.rate 0.461961 # Number of inst fetches per cycle 1088system.cpu0.decode.IdleCycles 12487890 # Number of cycles decode is idle 1089system.cpu0.decode.BlockedCycles 21493629 # Number of cycles decode is blocked 1090system.cpu0.decode.RunCycles 6874468 # Number of cycles decode is running 1091system.cpu0.decode.UnblockCycles 552722 # Number of cycles decode is unblocking 1092system.cpu0.decode.SquashCycles 984741 # Number of cycles decode is squashing 1093system.cpu0.decode.BranchResolved 950951 # Number of times decode resolved a branch 1094system.cpu0.decode.BranchMispred 64626 # Number of times decode detected a branch misprediction 1095system.cpu0.decode.DecodedInsts 40558878 # Number of instructions handled by decode 1096system.cpu0.decode.SquashedInsts 212020 # Number of squashed instructions handled by decode 1097system.cpu0.rename.SquashCycles 984741 # Number of cycles rename is squashing 1098system.cpu0.rename.IdleCycles 13064503 # Number of cycles rename is idle 1099system.cpu0.rename.BlockCycles 5883311 # Number of cycles rename is blocking 1100system.cpu0.rename.serializeStallCycles 13498743 # count of cycles rename stalled for serializing inst 1101system.cpu0.rename.RunCycles 6804692 # Number of cycles rename is running 1102system.cpu0.rename.UnblockCycles 2157460 # Number of cycles rename is unblocking 1103system.cpu0.rename.RenamedInsts 39446559 # Number of instructions processed by rename 1104system.cpu0.rename.ROBFullEvents 311 # Number of times rename has blocked due to ROB full 1105system.cpu0.rename.IQFullEvents 442642 # Number of times rename has blocked due to IQ full 1106system.cpu0.rename.LSQFullEvents 1180293 # Number of times rename has blocked due to LSQ full 1107system.cpu0.rename.FullRegisterEvents 145 # Number of times there has been no free registers 1108system.cpu0.rename.RenamedOperands 39856275 # Number of destination operands rename has renamed 1109system.cpu0.rename.RenameLookups 180582545 # Number of register rename lookups that rename has made 1110system.cpu0.rename.int_rename_lookups 163877057 # Number of integer rename lookups 1111system.cpu0.rename.fp_rename_lookups 4135 # Number of floating rename lookups 1112system.cpu0.rename.CommittedMaps 31488132 # Number of HB maps that are committed 1113system.cpu0.rename.UndoneMaps 8368142 # Number of HB maps that are undone due to squashing 1114system.cpu0.rename.serializingInsts 460013 # count of serializing insts renamed 1115system.cpu0.rename.tempSerializingInsts 416638 # count of temporary serializing insts renamed 1116system.cpu0.rename.skidInsts 5509006 # count of insts added to the skid buffer 1117system.cpu0.memDep0.insertedLoads 7758217 # Number of loads inserted to the mem dependence unit. 1118system.cpu0.memDep0.insertedStores 5771757 # Number of stores inserted to the mem dependence unit. 1119system.cpu0.memDep0.conflictingLoads 1123661 # Number of conflicting loads. 1120system.cpu0.memDep0.conflictingStores 1193308 # Number of conflicting stores. 1121system.cpu0.iq.iqInstsAdded 37348678 # Number of instructions added to the IQ (excludes non-spec) 1122system.cpu0.iq.iqNonSpecInstsAdded 906063 # Number of non-speculative instructions added to the IQ 1123system.cpu0.iq.iqInstsIssued 37718806 # Number of instructions issued 1124system.cpu0.iq.iqSquashedInstsIssued 82800 # Number of squashed instructions issued 1125system.cpu0.iq.iqSquashedInstsExamined 6312476 # Number of squashed instructions iterated over during squash; mainly for profiling 1126system.cpu0.iq.iqSquashedOperandsExamined 13233696 # Number of squashed operands that are examined and possibly removed from graph 1127system.cpu0.iq.iqSquashedNonSpecRemoved 257258 # Number of squashed non-spec instructions that were removed 1128system.cpu0.iq.issued_per_cycle::samples 42393450 # Number of insts issued each cycle 1129system.cpu0.iq.issued_per_cycle::mean 0.889732 # Number of insts issued each cycle 1130system.cpu0.iq.issued_per_cycle::stdev 1.506737 # Number of insts issued each cycle 1131system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1132system.cpu0.iq.issued_per_cycle::0 27027469 63.75% 63.75% # Number of insts issued each cycle 1133system.cpu0.iq.issued_per_cycle::1 5904750 13.93% 77.68% # Number of insts issued each cycle 1134system.cpu0.iq.issued_per_cycle::2 3167008 7.47% 85.15% # Number of insts issued each cycle 1135system.cpu0.iq.issued_per_cycle::3 2470651 5.83% 90.98% # Number of insts issued each cycle 1136system.cpu0.iq.issued_per_cycle::4 2117188 4.99% 95.97% # Number of insts issued each cycle 1137system.cpu0.iq.issued_per_cycle::5 941206 2.22% 98.20% # Number of insts issued each cycle 1138system.cpu0.iq.issued_per_cycle::6 520081 1.23% 99.42% # Number of insts issued each cycle 1139system.cpu0.iq.issued_per_cycle::7 187957 0.44% 99.87% # Number of insts issued each cycle 1140system.cpu0.iq.issued_per_cycle::8 57140 0.13% 100.00% # Number of insts issued each cycle 1141system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1142system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1143system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1144system.cpu0.iq.issued_per_cycle::total 42393450 # Number of insts issued each cycle 1145system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1146system.cpu0.iq.fu_full::IntAlu 26875 2.51% 2.51% # attempts to use FU when none available 1147system.cpu0.iq.fu_full::IntMult 458 0.04% 2.55% # attempts to use FU when none available 1148system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.55% # attempts to use FU when none available 1149system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.55% # attempts to use FU when none available 1150system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.55% # attempts to use FU when none available 1151system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.55% # attempts to use FU when none available 1152system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.55% # attempts to use FU when none available 1153system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.55% # attempts to use FU when none available 1154system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.55% # attempts to use FU when none available 1155system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.55% # attempts to use FU when none available 1156system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.55% # attempts to use FU when none available 1157system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.55% # attempts to use FU when none available 1158system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.55% # attempts to use FU when none available 1159system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.55% # attempts to use FU when none available 1160system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.55% # attempts to use FU when none available 1161system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.55% # attempts to use FU when none available 1162system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.55% # attempts to use FU when none available 1163system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.55% # attempts to use FU when none available 1164system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.55% # attempts to use FU when none available 1165system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.55% # attempts to use FU when none available 1166system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.55% # attempts to use FU when none available 1167system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.55% # attempts to use FU when none available 1168system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.55% # attempts to use FU when none available 1169system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.55% # attempts to use FU when none available 1170system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.55% # attempts to use FU when none available 1171system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.55% # attempts to use FU when none available 1172system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.55% # attempts to use FU when none available 1173system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.55% # attempts to use FU when none available 1174system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.55% # attempts to use FU when none available 1175system.cpu0.iq.fu_full::MemRead 836202 77.98% 80.53% # attempts to use FU when none available 1176system.cpu0.iq.fu_full::MemWrite 208765 19.47% 100.00% # attempts to use FU when none available 1177system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1178system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1179system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued 1180system.cpu0.iq.FU_type_0::IntAlu 22694630 60.17% 60.21% # Type of FU issued 1181system.cpu0.iq.FU_type_0::IntMult 47979 0.13% 60.33% # Type of FU issued 1182system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued 1183system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued 1184system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued 1185system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued 1186system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued 1187system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued 1188system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued 1189system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued 1190system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued 1191system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued 1192system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued 1193system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued 1194system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.33% # Type of FU issued 1195system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued 1196system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued 1197system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued 1198system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.33% # Type of FU issued 1199system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued 1200system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued 1201system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued 1202system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued 1203system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued 1204system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued 1205system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued 1206system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued 1207system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued 1208system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued 1209system.cpu0.iq.FU_type_0::MemRead 9430195 25.00% 85.34% # Type of FU issued 1210system.cpu0.iq.FU_type_0::MemWrite 5530734 14.66% 100.00% # Type of FU issued 1211system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1212system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1213system.cpu0.iq.FU_type_0::total 37718806 # Type of FU issued 1214system.cpu0.iq.rate 0.536936 # Inst issue rate 1215system.cpu0.iq.fu_busy_cnt 1072300 # FU busy when requested 1216system.cpu0.iq.fu_busy_rate 0.028429 # FU busy rate (busy events/executed inst) 1217system.cpu0.iq.int_inst_queue_reads 119012569 # Number of integer instruction queue reads 1218system.cpu0.iq.int_inst_queue_writes 44575137 # Number of integer instruction queue writes 1219system.cpu0.iq.int_inst_queue_wakeup_accesses 34852276 # Number of integer instruction queue wakeup accesses 1220system.cpu0.iq.fp_inst_queue_reads 8350 # Number of floating instruction queue reads 1221system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes 1222system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses 1223system.cpu0.iq.int_alu_accesses 38772197 # Number of integer alu accesses 1224system.cpu0.iq.fp_alu_accesses 4358 # Number of floating point alu accesses 1225system.cpu0.iew.lsq.thread0.forwLoads 316382 # Number of loads that had data forwarded from stores 1226system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1227system.cpu0.iew.lsq.thread0.squashedLoads 1375838 # Number of loads squashed 1228system.cpu0.iew.lsq.thread0.ignoredResponses 2694 # Number of memory responses ignored because the instruction is squashed 1229system.cpu0.iew.lsq.thread0.memOrderViolation 13105 # Number of memory ordering violations 1230system.cpu0.iew.lsq.thread0.squashedStores 538991 # Number of stores squashed 1231system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1232system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1233system.cpu0.iew.lsq.thread0.rescheduledLoads 2149907 # Number of loads that were rescheduled 1234system.cpu0.iew.lsq.thread0.cacheBlocked 5937 # Number of times an access to memory failed due to the cache being blocked 1235system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1236system.cpu0.iew.iewSquashCycles 984741 # Number of cycles IEW is squashing 1237system.cpu0.iew.iewBlockCycles 4273547 # Number of cycles IEW is blocking 1238system.cpu0.iew.iewUnblockCycles 99764 # Number of cycles IEW is unblocking 1239system.cpu0.iew.iewDispatchedInsts 38372810 # Number of instructions dispatched to IQ 1240system.cpu0.iew.iewDispSquashedInsts 83727 # Number of squashed instructions skipped by dispatch 1241system.cpu0.iew.iewDispLoadInsts 7758217 # Number of dispatched load instructions 1242system.cpu0.iew.iewDispStoreInsts 5771757 # Number of dispatched store instructions 1243system.cpu0.iew.iewDispNonSpecInsts 578717 # Number of dispatched non-speculative instructions 1244system.cpu0.iew.iewIQFullEvents 40350 # Number of times the IQ has become full, causing a stall 1245system.cpu0.iew.iewLSQFullEvents 3282 # Number of times the LSQ has become full, causing a stall 1246system.cpu0.iew.memOrderViolationEvents 13105 # Number of memory order violations 1247system.cpu0.iew.predictedTakenIncorrect 151036 # Number of branches that were predicted taken incorrectly 1248system.cpu0.iew.predictedNotTakenIncorrect 117828 # Number of branches that were predicted not taken incorrectly 1249system.cpu0.iew.branchMispredicts 268864 # Number of branch mispredicts detected at execute 1250system.cpu0.iew.iewExecutedInsts 37337135 # Number of executed instructions 1251system.cpu0.iew.iewExecLoadInsts 9286340 # Number of load instructions executed 1252system.cpu0.iew.iewExecSquashedInsts 381671 # Number of squashed instructions skipped in execute 1253system.cpu0.iew.exec_swp 0 # number of swp insts executed 1254system.cpu0.iew.exec_nop 118069 # number of nop insts executed 1255system.cpu0.iew.exec_refs 14769450 # number of memory reference insts executed 1256system.cpu0.iew.exec_branches 4962843 # Number of branches executed 1257system.cpu0.iew.exec_stores 5483110 # Number of stores executed 1258system.cpu0.iew.exec_rate 0.531503 # Inst execution rate 1259system.cpu0.iew.wb_sent 37142523 # cumulative count of insts sent to commit 1260system.cpu0.iew.wb_count 34856145 # cumulative count of insts written-back 1261system.cpu0.iew.wb_producers 18592748 # num instructions producing a value 1262system.cpu0.iew.wb_consumers 35683758 # num instructions consuming a value 1263system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1264system.cpu0.iew.wb_rate 0.496185 # insts written-back per cycle 1265system.cpu0.iew.wb_fanout 0.521042 # average fanout of values written-back 1266system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1267system.cpu0.commit.commitSquashedInsts 6125993 # The number of squashed insts skipped by commit 1268system.cpu0.commit.commitNonSpecStalls 648805 # The number of times commit has been forced to stall to communicate backwards 1269system.cpu0.commit.branchMispredicts 232656 # The number of times a branch was mispredicted 1270system.cpu0.commit.committed_per_cycle::samples 41408709 # Number of insts commited each cycle 1271system.cpu0.commit.committed_per_cycle::mean 0.767702 # Number of insts commited each cycle 1272system.cpu0.commit.committed_per_cycle::stdev 1.726975 # Number of insts commited each cycle 1273system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1274system.cpu0.commit.committed_per_cycle::0 29445863 71.11% 71.11% # Number of insts commited each cycle 1275system.cpu0.commit.committed_per_cycle::1 5939620 14.34% 85.45% # Number of insts commited each cycle 1276system.cpu0.commit.committed_per_cycle::2 1940870 4.69% 90.14% # Number of insts commited each cycle 1277system.cpu0.commit.committed_per_cycle::3 1013361 2.45% 92.59% # Number of insts commited each cycle 1278system.cpu0.commit.committed_per_cycle::4 759448 1.83% 94.42% # Number of insts commited each cycle 1279system.cpu0.commit.committed_per_cycle::5 515426 1.24% 95.67% # Number of insts commited each cycle 1280system.cpu0.commit.committed_per_cycle::6 408347 0.99% 96.65% # Number of insts commited each cycle 1281system.cpu0.commit.committed_per_cycle::7 223076 0.54% 97.19% # Number of insts commited each cycle 1282system.cpu0.commit.committed_per_cycle::8 1162698 2.81% 100.00% # Number of insts commited each cycle 1283system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1284system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1285system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1286system.cpu0.commit.committed_per_cycle::total 41408709 # Number of insts commited each cycle 1287system.cpu0.commit.committedInsts 24071577 # Number of instructions committed 1288system.cpu0.commit.committedOps 31789563 # Number of ops (including micro ops) committed 1289system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1290system.cpu0.commit.refs 11615145 # Number of memory references committed 1291system.cpu0.commit.loads 6382379 # Number of loads committed 1292system.cpu0.commit.membars 231812 # Number of memory barriers committed 1293system.cpu0.commit.branches 4351457 # Number of branches committed 1294system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 1295system.cpu0.commit.int_insts 28135168 # Number of committed integer instructions. 1296system.cpu0.commit.function_calls 498959 # Number of function calls committed. 1297system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1298system.cpu0.commit.op_class_0::IntAlu 20133954 63.34% 63.34% # Class of committed instruction 1299system.cpu0.commit.op_class_0::IntMult 39784 0.13% 63.46% # Class of committed instruction 1300system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.46% # Class of committed instruction 1301system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.46% # Class of committed instruction 1302system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.46% # Class of committed instruction 1303system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.46% # Class of committed instruction 1304system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.46% # Class of committed instruction 1305system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.46% # Class of committed instruction 1306system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.46% # Class of committed instruction 1307system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.46% # Class of committed instruction 1308system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.46% # Class of committed instruction 1309system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.46% # Class of committed instruction 1310system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.46% # Class of committed instruction 1311system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.46% # Class of committed instruction 1312system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.46% # Class of committed instruction 1313system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.46% # Class of committed instruction 1314system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.46% # Class of committed instruction 1315system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.46% # Class of committed instruction 1316system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.46% # Class of committed instruction 1317system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.46% # Class of committed instruction 1318system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.46% # Class of committed instruction 1319system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.46% # Class of committed instruction 1320system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.46% # Class of committed instruction 1321system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.46% # Class of committed instruction 1322system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.46% # Class of committed instruction 1323system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.46% # Class of committed instruction 1324system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 1325system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 1326system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 1327system.cpu0.commit.op_class_0::MemRead 6382379 20.08% 83.54% # Class of committed instruction 1328system.cpu0.commit.op_class_0::MemWrite 5232766 16.46% 100.00% # Class of committed instruction 1329system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1330system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1331system.cpu0.commit.op_class_0::total 31789563 # Class of committed instruction 1332system.cpu0.commit.bw_lim_events 1162698 # number cycles where commit BW limit reached 1333system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1334system.cpu0.rob.rob_reads 77292791 # The number of ROB reads 1335system.cpu0.rob.rob_writes 76817595 # The number of ROB writes 1336system.cpu0.timesIdled 365665 # Number of times that the entire CPU went into an idle state and unscheduled itself 1337system.cpu0.idleCycles 27854788 # Total number of cycles that the CPU has spent unscheduled due to idling 1338system.cpu0.quiesceCycles 5140997105 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1339system.cpu0.committedInsts 23990835 # Number of Instructions Simulated 1340system.cpu0.committedOps 31708821 # Number of Ops (including micro ops) Simulated 1341system.cpu0.committedInsts_total 23990835 # Number of Instructions Simulated 1342system.cpu0.cpi 2.928128 # CPI: Cycles Per Instruction 1343system.cpu0.cpi_total 2.928128 # CPI: Total CPI of All Threads 1344system.cpu0.ipc 0.341515 # IPC: Instructions Per Cycle 1345system.cpu0.ipc_total 0.341515 # IPC: Total IPC of All Threads 1346system.cpu0.int_regfile_reads 174285855 # number of integer regfile reads 1347system.cpu0.int_regfile_writes 34604955 # number of integer regfile writes 1348system.cpu0.fp_regfile_reads 3294 # number of floating regfile reads 1349system.cpu0.fp_regfile_writes 912 # number of floating regfile writes 1350system.cpu0.misc_regfile_reads 79299010 # number of misc regfile reads 1351system.cpu0.misc_regfile_writes 500883 # number of misc regfile writes 1352system.cpu0.icache.tags.replacements 399739 # number of replacements 1353system.cpu0.icache.tags.tagsinuse 511.543627 # Cycle average of tags in use 1354system.cpu0.icache.tags.total_refs 3844274 # Total number of references to valid blocks. 1355system.cpu0.icache.tags.sampled_refs 400251 # Sample count of references to valid blocks. 1356system.cpu0.icache.tags.avg_refs 9.604658 # Average number of references to valid blocks. 1357system.cpu0.icache.tags.warmup_cycle 7097393250 # Cycle when the warmup percentage was hit. 1358system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.543627 # Average occupied blocks per requestor 1359system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999109 # Average percentage of cache occupancy 1360system.cpu0.icache.tags.occ_percent::total 0.999109 # Average percentage of cache occupancy 1361system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1362system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id 1363system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 1364system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id 1365system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 1366system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1367system.cpu0.icache.tags.tag_accesses 4676219 # Number of tag accesses 1368system.cpu0.icache.tags.data_accesses 4676219 # Number of data accesses 1369system.cpu0.icache.ReadReq_hits::cpu0.inst 3844274 # number of ReadReq hits 1370system.cpu0.icache.ReadReq_hits::total 3844274 # number of ReadReq hits 1371system.cpu0.icache.demand_hits::cpu0.inst 3844274 # number of demand (read+write) hits 1372system.cpu0.icache.demand_hits::total 3844274 # number of demand (read+write) hits 1373system.cpu0.icache.overall_hits::cpu0.inst 3844274 # number of overall hits 1374system.cpu0.icache.overall_hits::total 3844274 # number of overall hits 1375system.cpu0.icache.ReadReq_misses::cpu0.inst 431668 # number of ReadReq misses 1376system.cpu0.icache.ReadReq_misses::total 431668 # number of ReadReq misses 1377system.cpu0.icache.demand_misses::cpu0.inst 431668 # number of demand (read+write) misses 1378system.cpu0.icache.demand_misses::total 431668 # number of demand (read+write) misses 1379system.cpu0.icache.overall_misses::cpu0.inst 431668 # number of overall misses 1380system.cpu0.icache.overall_misses::total 431668 # number of overall misses 1381system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5966691765 # number of ReadReq miss cycles 1382system.cpu0.icache.ReadReq_miss_latency::total 5966691765 # number of ReadReq miss cycles 1383system.cpu0.icache.demand_miss_latency::cpu0.inst 5966691765 # number of demand (read+write) miss cycles 1384system.cpu0.icache.demand_miss_latency::total 5966691765 # number of demand (read+write) miss cycles 1385system.cpu0.icache.overall_miss_latency::cpu0.inst 5966691765 # number of overall miss cycles 1386system.cpu0.icache.overall_miss_latency::total 5966691765 # number of overall miss cycles 1387system.cpu0.icache.ReadReq_accesses::cpu0.inst 4275942 # number of ReadReq accesses(hits+misses) 1388system.cpu0.icache.ReadReq_accesses::total 4275942 # number of ReadReq accesses(hits+misses) 1389system.cpu0.icache.demand_accesses::cpu0.inst 4275942 # number of demand (read+write) accesses 1390system.cpu0.icache.demand_accesses::total 4275942 # number of demand (read+write) accesses 1391system.cpu0.icache.overall_accesses::cpu0.inst 4275942 # number of overall (read+write) accesses 1392system.cpu0.icache.overall_accesses::total 4275942 # number of overall (read+write) accesses 1393system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100953 # miss rate for ReadReq accesses 1394system.cpu0.icache.ReadReq_miss_rate::total 0.100953 # miss rate for ReadReq accesses 1395system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100953 # miss rate for demand accesses 1396system.cpu0.icache.demand_miss_rate::total 0.100953 # miss rate for demand accesses 1397system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100953 # miss rate for overall accesses 1398system.cpu0.icache.overall_miss_rate::total 0.100953 # miss rate for overall accesses 1399system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271 # average ReadReq miss latency 1400system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271 # average ReadReq miss latency 1401system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency 1402system.cpu0.icache.demand_avg_miss_latency::total 13822.409271 # average overall miss latency 1403system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency 1404system.cpu0.icache.overall_avg_miss_latency::total 13822.409271 # average overall miss latency 1405system.cpu0.icache.blocked_cycles::no_mshrs 4149 # number of cycles access was blocked 1406system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1407system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked 1408system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1409system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.122093 # average number of cycles each access was blocked 1410system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1411system.cpu0.icache.fast_writes 0 # number of fast writes performed 1412system.cpu0.icache.cache_copies 0 # number of cache copies performed 1413system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31390 # number of ReadReq MSHR hits 1414system.cpu0.icache.ReadReq_mshr_hits::total 31390 # number of ReadReq MSHR hits 1415system.cpu0.icache.demand_mshr_hits::cpu0.inst 31390 # number of demand (read+write) MSHR hits 1416system.cpu0.icache.demand_mshr_hits::total 31390 # number of demand (read+write) MSHR hits 1417system.cpu0.icache.overall_mshr_hits::cpu0.inst 31390 # number of overall MSHR hits 1418system.cpu0.icache.overall_mshr_hits::total 31390 # number of overall MSHR hits 1419system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400278 # number of ReadReq MSHR misses 1420system.cpu0.icache.ReadReq_mshr_misses::total 400278 # number of ReadReq MSHR misses 1421system.cpu0.icache.demand_mshr_misses::cpu0.inst 400278 # number of demand (read+write) MSHR misses 1422system.cpu0.icache.demand_mshr_misses::total 400278 # number of demand (read+write) MSHR misses 1423system.cpu0.icache.overall_mshr_misses::cpu0.inst 400278 # number of overall MSHR misses 1424system.cpu0.icache.overall_mshr_misses::total 400278 # number of overall MSHR misses 1425system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859637603 # number of ReadReq MSHR miss cycles 1426system.cpu0.icache.ReadReq_mshr_miss_latency::total 4859637603 # number of ReadReq MSHR miss cycles 1427system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859637603 # number of demand (read+write) MSHR miss cycles 1428system.cpu0.icache.demand_mshr_miss_latency::total 4859637603 # number of demand (read+write) MSHR miss cycles 1429system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859637603 # number of overall MSHR miss cycles 1430system.cpu0.icache.overall_mshr_miss_latency::total 4859637603 # number of overall MSHR miss cycles 1431system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9490000 # number of ReadReq MSHR uncacheable cycles 1432system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9490000 # number of ReadReq MSHR uncacheable cycles 1433system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9490000 # number of overall MSHR uncacheable cycles 1434system.cpu0.icache.overall_mshr_uncacheable_latency::total 9490000 # number of overall MSHR uncacheable cycles 1435system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for ReadReq accesses 1436system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093612 # mshr miss rate for ReadReq accesses 1437system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for demand accesses 1438system.cpu0.icache.demand_mshr_miss_rate::total 0.093612 # mshr miss rate for demand accesses 1439system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for overall accesses 1440system.cpu0.icache.overall_mshr_miss_rate::total 0.093612 # mshr miss rate for overall accesses 1441system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average ReadReq mshr miss latency 1442system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12140.656251 # average ReadReq mshr miss latency 1443system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency 1444system.cpu0.icache.demand_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency 1445system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency 1446system.cpu0.icache.overall_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency 1447system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1448system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1449system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1450system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1451system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1452system.cpu0.dcache.tags.replacements 275002 # number of replacements 1453system.cpu0.dcache.tags.tagsinuse 479.873805 # Cycle average of tags in use 1454system.cpu0.dcache.tags.total_refs 9429051 # Total number of references to valid blocks. 1455system.cpu0.dcache.tags.sampled_refs 275514 # Sample count of references to valid blocks. 1456system.cpu0.dcache.tags.avg_refs 34.223491 # Average number of references to valid blocks. 1457system.cpu0.dcache.tags.warmup_cycle 43985250 # Cycle when the warmup percentage was hit. 1458system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.873805 # Average occupied blocks per requestor 1459system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937254 # Average percentage of cache occupancy 1460system.cpu0.dcache.tags.occ_percent::total 0.937254 # Average percentage of cache occupancy 1461system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1462system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 1463system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 1464system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 1465system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1466system.cpu0.dcache.tags.tag_accesses 45805638 # Number of tag accesses 1467system.cpu0.dcache.tags.data_accesses 45805638 # Number of data accesses 1468system.cpu0.dcache.ReadReq_hits::cpu0.data 5875796 # number of ReadReq hits 1469system.cpu0.dcache.ReadReq_hits::total 5875796 # number of ReadReq hits 1470system.cpu0.dcache.WriteReq_hits::cpu0.data 3229179 # number of WriteReq hits 1471system.cpu0.dcache.WriteReq_hits::total 3229179 # number of WriteReq hits 1472system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139566 # number of LoadLockedReq hits 1473system.cpu0.dcache.LoadLockedReq_hits::total 139566 # number of LoadLockedReq hits 1474system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137212 # number of StoreCondReq hits 1475system.cpu0.dcache.StoreCondReq_hits::total 137212 # number of StoreCondReq hits 1476system.cpu0.dcache.demand_hits::cpu0.data 9104975 # number of demand (read+write) hits 1477system.cpu0.dcache.demand_hits::total 9104975 # number of demand (read+write) hits 1478system.cpu0.dcache.overall_hits::cpu0.data 9104975 # number of overall hits 1479system.cpu0.dcache.overall_hits::total 9104975 # number of overall hits 1480system.cpu0.dcache.ReadReq_misses::cpu0.data 392540 # number of ReadReq misses 1481system.cpu0.dcache.ReadReq_misses::total 392540 # number of ReadReq misses 1482system.cpu0.dcache.WriteReq_misses::cpu0.data 1582550 # number of WriteReq misses 1483system.cpu0.dcache.WriteReq_misses::total 1582550 # number of WriteReq misses 1484system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8878 # number of LoadLockedReq misses 1485system.cpu0.dcache.LoadLockedReq_misses::total 8878 # number of LoadLockedReq misses 1486system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7747 # number of StoreCondReq misses 1487system.cpu0.dcache.StoreCondReq_misses::total 7747 # number of StoreCondReq misses 1488system.cpu0.dcache.demand_misses::cpu0.data 1975090 # number of demand (read+write) misses 1489system.cpu0.dcache.demand_misses::total 1975090 # number of demand (read+write) misses 1490system.cpu0.dcache.overall_misses::cpu0.data 1975090 # number of overall misses 1491system.cpu0.dcache.overall_misses::total 1975090 # number of overall misses 1492system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5503316358 # number of ReadReq miss cycles 1493system.cpu0.dcache.ReadReq_miss_latency::total 5503316358 # number of ReadReq miss cycles 1494system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80403947306 # number of WriteReq miss cycles 1495system.cpu0.dcache.WriteReq_miss_latency::total 80403947306 # number of WriteReq miss cycles 1496system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91149731 # number of LoadLockedReq miss cycles 1497system.cpu0.dcache.LoadLockedReq_miss_latency::total 91149731 # number of LoadLockedReq miss cycles 1498system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49845761 # number of StoreCondReq miss cycles 1499system.cpu0.dcache.StoreCondReq_miss_latency::total 49845761 # number of StoreCondReq miss cycles 1500system.cpu0.dcache.demand_miss_latency::cpu0.data 85907263664 # number of demand (read+write) miss cycles 1501system.cpu0.dcache.demand_miss_latency::total 85907263664 # number of demand (read+write) miss cycles 1502system.cpu0.dcache.overall_miss_latency::cpu0.data 85907263664 # number of overall miss cycles 1503system.cpu0.dcache.overall_miss_latency::total 85907263664 # number of overall miss cycles 1504system.cpu0.dcache.ReadReq_accesses::cpu0.data 6268336 # number of ReadReq accesses(hits+misses) 1505system.cpu0.dcache.ReadReq_accesses::total 6268336 # number of ReadReq accesses(hits+misses) 1506system.cpu0.dcache.WriteReq_accesses::cpu0.data 4811729 # number of WriteReq accesses(hits+misses) 1507system.cpu0.dcache.WriteReq_accesses::total 4811729 # number of WriteReq accesses(hits+misses) 1508system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148444 # number of LoadLockedReq accesses(hits+misses) 1509system.cpu0.dcache.LoadLockedReq_accesses::total 148444 # number of LoadLockedReq accesses(hits+misses) 1510system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144959 # number of StoreCondReq accesses(hits+misses) 1511system.cpu0.dcache.StoreCondReq_accesses::total 144959 # number of StoreCondReq accesses(hits+misses) 1512system.cpu0.dcache.demand_accesses::cpu0.data 11080065 # number of demand (read+write) accesses 1513system.cpu0.dcache.demand_accesses::total 11080065 # number of demand (read+write) accesses 1514system.cpu0.dcache.overall_accesses::cpu0.data 11080065 # number of overall (read+write) accesses 1515system.cpu0.dcache.overall_accesses::total 11080065 # number of overall (read+write) accesses 1516system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062623 # miss rate for ReadReq accesses 1517system.cpu0.dcache.ReadReq_miss_rate::total 0.062623 # miss rate for ReadReq accesses 1518system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328894 # miss rate for WriteReq accesses 1519system.cpu0.dcache.WriteReq_miss_rate::total 0.328894 # miss rate for WriteReq accesses 1520system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059807 # miss rate for LoadLockedReq accesses 1521system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059807 # miss rate for LoadLockedReq accesses 1522system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053443 # miss rate for StoreCondReq accesses 1523system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053443 # miss rate for StoreCondReq accesses 1524system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178256 # miss rate for demand accesses 1525system.cpu0.dcache.demand_miss_rate::total 0.178256 # miss rate for demand accesses 1526system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178256 # miss rate for overall accesses 1527system.cpu0.dcache.overall_miss_rate::total 0.178256 # miss rate for overall accesses 1528system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14019.759408 # average ReadReq miss latency 1529system.cpu0.dcache.ReadReq_avg_miss_latency::total 14019.759408 # average ReadReq miss latency 1530system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289 # average WriteReq miss latency 1531system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289 # average WriteReq miss latency 1532system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717 # average LoadLockedReq miss latency 1533system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717 # average LoadLockedReq miss latency 1534system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6434.201756 # average StoreCondReq miss latency 1535system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6434.201756 # average StoreCondReq miss latency 1536system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency 1537system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623 # average overall miss latency 1538system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency 1539system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623 # average overall miss latency 1540system.cpu0.dcache.blocked_cycles::no_mshrs 9513 # number of cycles access was blocked 1541system.cpu0.dcache.blocked_cycles::no_targets 7748 # number of cycles access was blocked 1542system.cpu0.dcache.blocked::no_mshrs 587 # number of cycles access was blocked 1543system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked 1544system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.206133 # average number of cycles each access was blocked 1545system.cpu0.dcache.avg_blocked_cycles::no_targets 56.970588 # average number of cycles each access was blocked 1546system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1547system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1548system.cpu0.dcache.writebacks::writebacks 255347 # number of writebacks 1549system.cpu0.dcache.writebacks::total 255347 # number of writebacks 1550system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203411 # number of ReadReq MSHR hits 1551system.cpu0.dcache.ReadReq_mshr_hits::total 203411 # number of ReadReq MSHR hits 1552system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451593 # number of WriteReq MSHR hits 1553system.cpu0.dcache.WriteReq_mshr_hits::total 1451593 # number of WriteReq MSHR hits 1554system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits 1555system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits 1556system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655004 # number of demand (read+write) MSHR hits 1557system.cpu0.dcache.demand_mshr_hits::total 1655004 # number of demand (read+write) MSHR hits 1558system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655004 # number of overall MSHR hits 1559system.cpu0.dcache.overall_mshr_hits::total 1655004 # number of overall MSHR hits 1560system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189129 # number of ReadReq MSHR misses 1561system.cpu0.dcache.ReadReq_mshr_misses::total 189129 # number of ReadReq MSHR misses 1562system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130957 # number of WriteReq MSHR misses 1563system.cpu0.dcache.WriteReq_mshr_misses::total 130957 # number of WriteReq MSHR misses 1564system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8410 # number of LoadLockedReq MSHR misses 1565system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses 1566system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7747 # number of StoreCondReq MSHR misses 1567system.cpu0.dcache.StoreCondReq_mshr_misses::total 7747 # number of StoreCondReq MSHR misses 1568system.cpu0.dcache.demand_mshr_misses::cpu0.data 320086 # number of demand (read+write) MSHR misses 1569system.cpu0.dcache.demand_mshr_misses::total 320086 # number of demand (read+write) MSHR misses 1570system.cpu0.dcache.overall_mshr_misses::cpu0.data 320086 # number of overall MSHR misses 1571system.cpu0.dcache.overall_mshr_misses::total 320086 # number of overall MSHR misses 1572system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2397985131 # number of ReadReq MSHR miss cycles 1573system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2397985131 # number of ReadReq MSHR miss cycles 1574system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338215866 # number of WriteReq MSHR miss cycles 1575system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338215866 # number of WriteReq MSHR miss cycles 1576system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69513767 # number of LoadLockedReq MSHR miss cycles 1577system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69513767 # number of LoadLockedReq MSHR miss cycles 1578system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34349239 # number of StoreCondReq MSHR miss cycles 1579system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34349239 # number of StoreCondReq MSHR miss cycles 1580system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1581system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1582system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7736200997 # number of demand (read+write) MSHR miss cycles 1583system.cpu0.dcache.demand_mshr_miss_latency::total 7736200997 # number of demand (read+write) MSHR miss cycles 1584system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7736200997 # number of overall MSHR miss cycles 1585system.cpu0.dcache.overall_mshr_miss_latency::total 7736200997 # number of overall MSHR miss cycles 1586system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434640527 # number of ReadReq MSHR uncacheable cycles 1587system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434640527 # number of ReadReq MSHR uncacheable cycles 1588system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206086382 # number of WriteReq MSHR uncacheable cycles 1589system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206086382 # number of WriteReq MSHR uncacheable cycles 1590system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640726909 # number of overall MSHR uncacheable cycles 1591system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640726909 # number of overall MSHR uncacheable cycles 1592system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030172 # mshr miss rate for ReadReq accesses 1593system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030172 # mshr miss rate for ReadReq accesses 1594system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027216 # mshr miss rate for WriteReq accesses 1595system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027216 # mshr miss rate for WriteReq accesses 1596system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056654 # mshr miss rate for LoadLockedReq accesses 1597system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056654 # mshr miss rate for LoadLockedReq accesses 1598system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053443 # mshr miss rate for StoreCondReq accesses 1599system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053443 # mshr miss rate for StoreCondReq accesses 1600system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for demand accesses 1601system.cpu0.dcache.demand_mshr_miss_rate::total 0.028888 # mshr miss rate for demand accesses 1602system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for overall accesses 1603system.cpu0.dcache.overall_mshr_miss_rate::total 0.028888 # mshr miss rate for overall accesses 1604system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028 # average ReadReq mshr miss latency 1605system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028 # average ReadReq mshr miss latency 1606system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696 # average WriteReq mshr miss latency 1607system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696 # average WriteReq mshr miss latency 1608system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8265.608442 # average LoadLockedReq mshr miss latency 1609system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8265.608442 # average LoadLockedReq mshr miss latency 1610system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4433.876210 # average StoreCondReq mshr miss latency 1611system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4433.876210 # average StoreCondReq mshr miss latency 1612system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1613system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1614system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency 1615system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency 1616system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency 1617system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency 1618system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1619system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1620system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1621system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1622system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1623system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1624system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1625system.cpu1.branchPred.lookups 9293378 # Number of BP lookups 1626system.cpu1.branchPred.condPredicted 7631598 # Number of conditional branches predicted 1627system.cpu1.branchPred.condIncorrect 415998 # Number of conditional branches incorrect 1628system.cpu1.branchPred.BTBLookups 5889507 # Number of BTB lookups 1629system.cpu1.branchPred.BTBHits 5046361 # Number of BTB hits 1630system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1631system.cpu1.branchPred.BTBHitPct 85.683929 # BTB Hit Percentage 1632system.cpu1.branchPred.usedRAS 797302 # Number of times the RAS was used to get a target. 1633system.cpu1.branchPred.RASInCorrect 43622 # Number of incorrect RAS predictions. 1634system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1635system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1636system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1637system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1638system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1639system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1640system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1641system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1642system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1643system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1644system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1645system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1646system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1647system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1648system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1649system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1650system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1651system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1652system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1653system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1654system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1655system.cpu1.dtb.inst_hits 0 # ITB inst hits 1656system.cpu1.dtb.inst_misses 0 # ITB inst misses 1657system.cpu1.dtb.read_hits 42971422 # DTB read hits 1658system.cpu1.dtb.read_misses 37905 # DTB read misses 1659system.cpu1.dtb.write_hits 6976449 # DTB write hits 1660system.cpu1.dtb.write_misses 10883 # DTB write misses 1661system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1662system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1663system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1664system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1665system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB 1666system.cpu1.dtb.align_faults 2893 # Number of TLB faults due to alignment restrictions 1667system.cpu1.dtb.prefetch_faults 296 # Number of TLB faults due to prefetch 1668system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1669system.cpu1.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions 1670system.cpu1.dtb.read_accesses 43009327 # DTB read accesses 1671system.cpu1.dtb.write_accesses 6987332 # DTB write accesses 1672system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1673system.cpu1.dtb.hits 49947871 # DTB hits 1674system.cpu1.dtb.misses 48788 # DTB misses 1675system.cpu1.dtb.accesses 49996659 # DTB accesses 1676system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1677system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1678system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1679system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1680system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1681system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1682system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1683system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1684system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1685system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1686system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1687system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1688system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1689system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1690system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1691system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1692system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1693system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1694system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1695system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1696system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1697system.cpu1.itb.inst_hits 7719787 # ITB inst hits 1698system.cpu1.itb.inst_misses 5634 # ITB inst misses 1699system.cpu1.itb.read_hits 0 # DTB read hits 1700system.cpu1.itb.read_misses 0 # DTB read misses 1701system.cpu1.itb.write_hits 0 # DTB write hits 1702system.cpu1.itb.write_misses 0 # DTB write misses 1703system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1704system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1705system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1706system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1707system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB 1708system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1709system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1710system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1711system.cpu1.itb.perms_faults 1538 # Number of TLB faults due to permissions restrictions 1712system.cpu1.itb.read_accesses 0 # DTB read accesses 1713system.cpu1.itb.write_accesses 0 # DTB write accesses 1714system.cpu1.itb.inst_accesses 7725421 # ITB inst accesses 1715system.cpu1.itb.hits 7719787 # DTB hits 1716system.cpu1.itb.misses 5634 # DTB misses 1717system.cpu1.itb.accesses 7725421 # DTB accesses 1718system.cpu1.numCycles 413693823 # number of cpu cycles simulated 1719system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1720system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1721system.cpu1.fetch.icacheStallCycles 19372544 # Number of cycles fetch is stalled on an Icache miss 1722system.cpu1.fetch.Insts 61318271 # Number of instructions fetch has processed 1723system.cpu1.fetch.Branches 9293378 # Number of branches that fetch encountered 1724system.cpu1.fetch.predictedBranches 5843663 # Number of branches that fetch has predicted taken 1725system.cpu1.fetch.Cycles 13362487 # Number of cycles fetch has run and was not squashing or blocked 1726system.cpu1.fetch.SquashCycles 3346253 # Number of cycles fetch has spent squashing 1727system.cpu1.fetch.TlbCycles 69736 # Number of cycles fetch has spent waiting for tlb 1728system.cpu1.fetch.BlockedCycles 80999073 # Number of cycles fetch has spent blocked 1729system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1730system.cpu1.fetch.PendingTrapStallCycles 42062 # Number of stall cycles due to pending traps 1731system.cpu1.fetch.PendingQuiesceStallCycles 1494344 # Number of stall cycles due to pending quiesce instructions 1732system.cpu1.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR 1733system.cpu1.fetch.CacheLines 7717920 # Number of cache lines fetched 1734system.cpu1.fetch.IcacheSquashes 551887 # Number of outstanding Icache misses that were squashed 1735system.cpu1.fetch.ItlbSquashes 2996 # Number of outstanding ITLB misses that were squashed 1736system.cpu1.fetch.rateDist::samples 117635394 # Number of instructions fetched each cycle (Total) 1737system.cpu1.fetch.rateDist::mean 0.638004 # Number of instructions fetched each cycle (Total) 1738system.cpu1.fetch.rateDist::stdev 1.959630 # Number of instructions fetched each cycle (Total) 1739system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1740system.cpu1.fetch.rateDist::0 104280280 88.65% 88.65% # Number of instructions fetched each cycle (Total) 1741system.cpu1.fetch.rateDist::1 814710 0.69% 89.34% # Number of instructions fetched each cycle (Total) 1742system.cpu1.fetch.rateDist::2 961160 0.82% 90.16% # Number of instructions fetched each cycle (Total) 1743system.cpu1.fetch.rateDist::3 1713171 1.46% 91.61% # Number of instructions fetched each cycle (Total) 1744system.cpu1.fetch.rateDist::4 1415249 1.20% 92.82% # Number of instructions fetched each cycle (Total) 1745system.cpu1.fetch.rateDist::5 586962 0.50% 93.32% # Number of instructions fetched each cycle (Total) 1746system.cpu1.fetch.rateDist::6 1954597 1.66% 94.98% # Number of instructions fetched each cycle (Total) 1747system.cpu1.fetch.rateDist::7 422243 0.36% 95.34% # Number of instructions fetched each cycle (Total) 1748system.cpu1.fetch.rateDist::8 5487022 4.66% 100.00% # Number of instructions fetched each cycle (Total) 1749system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1750system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1751system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1752system.cpu1.fetch.rateDist::total 117635394 # Number of instructions fetched each cycle (Total) 1753system.cpu1.fetch.branchRate 0.022464 # Number of branch fetches per cycle 1754system.cpu1.fetch.rate 0.148221 # Number of inst fetches per cycle 1755system.cpu1.decode.IdleCycles 20963679 # Number of cycles decode is idle 1756system.cpu1.decode.BlockedCycles 81759193 # Number of cycles decode is blocked 1757system.cpu1.decode.RunCycles 11913295 # Number of cycles decode is running 1758system.cpu1.decode.UnblockCycles 809519 # Number of cycles decode is unblocking 1759system.cpu1.decode.SquashCycles 2189708 # Number of cycles decode is squashing 1760system.cpu1.decode.BranchResolved 1137363 # Number of times decode resolved a branch 1761system.cpu1.decode.BranchMispred 100954 # Number of times decode detected a branch misprediction 1762system.cpu1.decode.DecodedInsts 71089276 # Number of instructions handled by decode 1763system.cpu1.decode.SquashedInsts 336011 # Number of squashed instructions handled by decode 1764system.cpu1.rename.SquashCycles 2189708 # Number of cycles rename is squashing 1765system.cpu1.rename.IdleCycles 22156707 # Number of cycles rename is idle 1766system.cpu1.rename.BlockCycles 33902507 # Number of cycles rename is blocking 1767system.cpu1.rename.serializeStallCycles 43325786 # count of cycles rename stalled for serializing inst 1768system.cpu1.rename.RunCycles 11473545 # Number of cycles rename is running 1769system.cpu1.rename.UnblockCycles 4587141 # Number of cycles rename is unblocking 1770system.cpu1.rename.RenamedInsts 67137864 # Number of instructions processed by rename 1771system.cpu1.rename.ROBFullEvents 137 # Number of times rename has blocked due to ROB full 1772system.cpu1.rename.IQFullEvents 682095 # Number of times rename has blocked due to IQ full 1773system.cpu1.rename.LSQFullEvents 3075433 # Number of times rename has blocked due to LSQ full 1774system.cpu1.rename.FullRegisterEvents 1010 # Number of times there has been no free registers 1775system.cpu1.rename.RenamedOperands 70763032 # Number of destination operands rename has renamed 1776system.cpu1.rename.RenameLookups 313108743 # Number of register rename lookups that rename has made 1777system.cpu1.rename.int_rename_lookups 286757803 # Number of integer rename lookups 1778system.cpu1.rename.fp_rename_lookups 6623 # Number of floating rename lookups 1779system.cpu1.rename.CommittedMaps 50416422 # Number of HB maps that are committed 1780system.cpu1.rename.UndoneMaps 20346610 # Number of HB maps that are undone due to squashing 1781system.cpu1.rename.serializingInsts 765987 # count of serializing insts renamed 1782system.cpu1.rename.tempSerializingInsts 705836 # count of temporary serializing insts renamed 1783system.cpu1.rename.skidInsts 8420477 # count of insts added to the skid buffer 1784system.cpu1.memDep0.insertedLoads 12843204 # Number of loads inserted to the mem dependence unit. 1785system.cpu1.memDep0.insertedStores 8115826 # Number of stores inserted to the mem dependence unit. 1786system.cpu1.memDep0.conflictingLoads 1055497 # Number of conflicting loads. 1787system.cpu1.memDep0.conflictingStores 1512633 # Number of conflicting stores. 1788system.cpu1.iq.iqInstsAdded 61850161 # Number of instructions added to the IQ (excludes non-spec) 1789system.cpu1.iq.iqNonSpecInstsAdded 1179252 # Number of non-speculative instructions added to the IQ 1790system.cpu1.iq.iqInstsIssued 88896986 # Number of instructions issued 1791system.cpu1.iq.iqSquashedInstsIssued 93979 # Number of squashed instructions issued 1792system.cpu1.iq.iqSquashedInstsExamined 13548762 # Number of squashed instructions iterated over during squash; mainly for profiling 1793system.cpu1.iq.iqSquashedOperandsExamined 36246660 # Number of squashed operands that are examined and possibly removed from graph 1794system.cpu1.iq.iqSquashedNonSpecRemoved 279849 # Number of squashed non-spec instructions that were removed 1795system.cpu1.iq.issued_per_cycle::samples 117635394 # Number of insts issued each cycle 1796system.cpu1.iq.issued_per_cycle::mean 0.755699 # Number of insts issued each cycle 1797system.cpu1.iq.issued_per_cycle::stdev 1.498688 # Number of insts issued each cycle 1798system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1799system.cpu1.iq.issued_per_cycle::0 86772303 73.76% 73.76% # Number of insts issued each cycle 1800system.cpu1.iq.issued_per_cycle::1 9298113 7.90% 81.67% # Number of insts issued each cycle 1801system.cpu1.iq.issued_per_cycle::2 4175598 3.55% 85.22% # Number of insts issued each cycle 1802system.cpu1.iq.issued_per_cycle::3 3594840 3.06% 88.27% # Number of insts issued each cycle 1803system.cpu1.iq.issued_per_cycle::4 10374006 8.82% 97.09% # Number of insts issued each cycle 1804system.cpu1.iq.issued_per_cycle::5 1994938 1.70% 98.79% # Number of insts issued each cycle 1805system.cpu1.iq.issued_per_cycle::6 1065613 0.91% 99.69% # Number of insts issued each cycle 1806system.cpu1.iq.issued_per_cycle::7 281099 0.24% 99.93% # Number of insts issued each cycle 1807system.cpu1.iq.issued_per_cycle::8 78884 0.07% 100.00% # Number of insts issued each cycle 1808system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1809system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1810system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1811system.cpu1.iq.issued_per_cycle::total 117635394 # Number of insts issued each cycle 1812system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1813system.cpu1.iq.fu_full::IntAlu 32152 0.41% 0.41% # attempts to use FU when none available 1814system.cpu1.iq.fu_full::IntMult 986 0.01% 0.42% # attempts to use FU when none available 1815system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available 1816system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available 1817system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1818system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1819system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available 1820system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1821system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 1822system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available 1823system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available 1824system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available 1825system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available 1826system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available 1827system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available 1828system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available 1829system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available 1830system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available 1831system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available 1832system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available 1833system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available 1834system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available 1835system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available 1836system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available 1837system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available 1838system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available 1839system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available 1840system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available 1841system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available 1842system.cpu1.iq.fu_full::MemRead 7573471 95.70% 96.12% # attempts to use FU when none available 1843system.cpu1.iq.fu_full::MemWrite 306947 3.88% 100.00% # attempts to use FU when none available 1844system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1845system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1846system.cpu1.iq.FU_type_0::No_OpClass 14268 0.02% 0.02% # Type of FU issued 1847system.cpu1.iq.FU_type_0::IntAlu 37614404 42.31% 42.33% # Type of FU issued 1848system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.40% # Type of FU issued 1849system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued 1850system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued 1851system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued 1852system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued 1853system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued 1854system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued 1855system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued 1856system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued 1857system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued 1858system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued 1859system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued 1860system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued 1861system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.40% # Type of FU issued 1862system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued 1863system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued 1864system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued 1865system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued 1866system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued 1867system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued 1868system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued 1869system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued 1870system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued 1871system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued 1872system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.40% # Type of FU issued 1873system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued 1874system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 42.40% # Type of FU issued 1875system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued 1876system.cpu1.iq.FU_type_0::MemRead 43858329 49.34% 91.74% # Type of FU issued 1877system.cpu1.iq.FU_type_0::MemWrite 7347048 8.26% 100.00% # Type of FU issued 1878system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1879system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1880system.cpu1.iq.FU_type_0::total 88896986 # Type of FU issued 1881system.cpu1.iq.rate 0.214886 # Inst issue rate 1882system.cpu1.iq.fu_busy_cnt 7913556 # FU busy when requested 1883system.cpu1.iq.fu_busy_rate 0.089019 # FU busy rate (busy events/executed inst) 1884system.cpu1.iq.int_inst_queue_reads 303469985 # Number of integer instruction queue reads 1885system.cpu1.iq.int_inst_queue_writes 76586992 # Number of integer instruction queue writes 1886system.cpu1.iq.int_inst_queue_wakeup_accesses 54255274 # Number of integer instruction queue wakeup accesses 1887system.cpu1.iq.fp_inst_queue_reads 15534 # Number of floating instruction queue reads 1888system.cpu1.iq.fp_inst_queue_writes 8108 # Number of floating instruction queue writes 1889system.cpu1.iq.fp_inst_queue_wakeup_accesses 6874 # Number of floating instruction queue wakeup accesses 1890system.cpu1.iq.int_alu_accesses 96788024 # Number of integer alu accesses 1891system.cpu1.iq.fp_alu_accesses 8250 # Number of floating point alu accesses 1892system.cpu1.iew.lsq.thread0.forwLoads 355713 # Number of loads that had data forwarded from stores 1893system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1894system.cpu1.iew.lsq.thread0.squashedLoads 2862172 # Number of loads squashed 1895system.cpu1.iew.lsq.thread0.ignoredResponses 4122 # Number of memory responses ignored because the instruction is squashed 1896system.cpu1.iew.lsq.thread0.memOrderViolation 17485 # Number of memory ordering violations 1897system.cpu1.iew.lsq.thread0.squashedStores 1111950 # Number of stores squashed 1898system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1899system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1900system.cpu1.iew.lsq.thread0.rescheduledLoads 31965671 # Number of loads that were rescheduled 1901system.cpu1.iew.lsq.thread0.cacheBlocked 675853 # Number of times an access to memory failed due to the cache being blocked 1902system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1903system.cpu1.iew.iewSquashCycles 2189708 # Number of cycles IEW is squashing 1904system.cpu1.iew.iewBlockCycles 26386476 # Number of cycles IEW is blocking 1905system.cpu1.iew.iewUnblockCycles 363440 # Number of cycles IEW is unblocking 1906system.cpu1.iew.iewDispatchedInsts 63133555 # Number of instructions dispatched to IQ 1907system.cpu1.iew.iewDispSquashedInsts 115239 # Number of squashed instructions skipped by dispatch 1908system.cpu1.iew.iewDispLoadInsts 12843204 # Number of dispatched load instructions 1909system.cpu1.iew.iewDispStoreInsts 8115826 # Number of dispatched store instructions 1910system.cpu1.iew.iewDispNonSpecInsts 883054 # Number of dispatched non-speculative instructions 1911system.cpu1.iew.iewIQFullEvents 66097 # Number of times the IQ has become full, causing a stall 1912system.cpu1.iew.iewLSQFullEvents 4286 # Number of times the LSQ has become full, causing a stall 1913system.cpu1.iew.memOrderViolationEvents 17485 # Number of memory order violations 1914system.cpu1.iew.predictedTakenIncorrect 204520 # Number of branches that were predicted taken incorrectly 1915system.cpu1.iew.predictedNotTakenIncorrect 158639 # Number of branches that were predicted not taken incorrectly 1916system.cpu1.iew.branchMispredicts 363159 # Number of branch mispredicts detected at execute 1917system.cpu1.iew.iewExecutedInsts 87164207 # Number of executed instructions 1918system.cpu1.iew.iewExecLoadInsts 43354058 # Number of load instructions executed 1919system.cpu1.iew.iewExecSquashedInsts 1732779 # Number of squashed instructions skipped in execute 1920system.cpu1.iew.exec_swp 0 # number of swp insts executed 1921system.cpu1.iew.exec_nop 104142 # number of nop insts executed 1922system.cpu1.iew.exec_refs 50636612 # number of memory reference insts executed 1923system.cpu1.iew.exec_branches 7376811 # Number of branches executed 1924system.cpu1.iew.exec_stores 7282554 # Number of stores executed 1925system.cpu1.iew.exec_rate 0.210697 # Inst execution rate 1926system.cpu1.iew.wb_sent 86400335 # cumulative count of insts sent to commit 1927system.cpu1.iew.wb_count 54262148 # cumulative count of insts written-back 1928system.cpu1.iew.wb_producers 30287291 # num instructions producing a value 1929system.cpu1.iew.wb_consumers 53873069 # num instructions consuming a value 1930system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1931system.cpu1.iew.wb_rate 0.131165 # insts written-back per cycle 1932system.cpu1.iew.wb_fanout 0.562197 # average fanout of values written-back 1933system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1934system.cpu1.commit.commitSquashedInsts 13443206 # The number of squashed insts skipped by commit 1935system.cpu1.commit.commitNonSpecStalls 899403 # The number of times commit has been forced to stall to communicate backwards 1936system.cpu1.commit.branchMispredicts 316783 # The number of times a branch was mispredicted 1937system.cpu1.commit.committed_per_cycle::samples 115445686 # Number of insts commited each cycle 1938system.cpu1.commit.committed_per_cycle::mean 0.426296 # Number of insts commited each cycle 1939system.cpu1.commit.committed_per_cycle::stdev 1.378874 # Number of insts commited each cycle 1940system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1941system.cpu1.commit.committed_per_cycle::0 97421932 84.39% 84.39% # Number of insts commited each cycle 1942system.cpu1.commit.committed_per_cycle::1 9594899 8.31% 92.70% # Number of insts commited each cycle 1943system.cpu1.commit.committed_per_cycle::2 2172227 1.88% 94.58% # Number of insts commited each cycle 1944system.cpu1.commit.committed_per_cycle::3 1301741 1.13% 95.71% # Number of insts commited each cycle 1945system.cpu1.commit.committed_per_cycle::4 988993 0.86% 96.56% # Number of insts commited each cycle 1946system.cpu1.commit.committed_per_cycle::5 587152 0.51% 97.07% # Number of insts commited each cycle 1947system.cpu1.commit.committed_per_cycle::6 1008803 0.87% 97.95% # Number of insts commited each cycle 1948system.cpu1.commit.committed_per_cycle::7 534624 0.46% 98.41% # Number of insts commited each cycle 1949system.cpu1.commit.committed_per_cycle::8 1835315 1.59% 100.00% # Number of insts commited each cycle 1950system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1951system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1952system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1953system.cpu1.commit.committed_per_cycle::total 115445686 # Number of insts commited each cycle 1954system.cpu1.commit.committedInsts 38873610 # Number of instructions committed 1955system.cpu1.commit.committedOps 49214014 # Number of ops (including micro ops) committed 1956system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1957system.cpu1.commit.refs 16984908 # Number of memory references committed 1958system.cpu1.commit.loads 9981032 # Number of loads committed 1959system.cpu1.commit.membars 195536 # Number of memory barriers committed 1960system.cpu1.commit.branches 6424997 # Number of branches committed 1961system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. 1962system.cpu1.commit.int_insts 43926362 # Number of committed integer instructions. 1963system.cpu1.commit.function_calls 553376 # Number of function calls committed. 1964system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 1965system.cpu1.commit.op_class_0::IntAlu 32169137 65.37% 65.37% # Class of committed instruction 1966system.cpu1.commit.op_class_0::IntMult 58263 0.12% 65.48% # Class of committed instruction 1967system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.48% # Class of committed instruction 1968system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.48% # Class of committed instruction 1969system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.48% # Class of committed instruction 1970system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.48% # Class of committed instruction 1971system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.48% # Class of committed instruction 1972system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.48% # Class of committed instruction 1973system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.48% # Class of committed instruction 1974system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.48% # Class of committed instruction 1975system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.48% # Class of committed instruction 1976system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.48% # Class of committed instruction 1977system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.48% # Class of committed instruction 1978system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.48% # Class of committed instruction 1979system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.48% # Class of committed instruction 1980system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.48% # Class of committed instruction 1981system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.48% # Class of committed instruction 1982system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.48% # Class of committed instruction 1983system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.48% # Class of committed instruction 1984system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.48% # Class of committed instruction 1985system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.48% # Class of committed instruction 1986system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.48% # Class of committed instruction 1987system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.48% # Class of committed instruction 1988system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.48% # Class of committed instruction 1989system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.48% # Class of committed instruction 1990system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction 1991system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction 1992system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction 1993system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction 1994system.cpu1.commit.op_class_0::MemRead 9981032 20.28% 85.77% # Class of committed instruction 1995system.cpu1.commit.op_class_0::MemWrite 7003876 14.23% 100.00% # Class of committed instruction 1996system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1997system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1998system.cpu1.commit.op_class_0::total 49214014 # Class of committed instruction 1999system.cpu1.commit.bw_lim_events 1835315 # number cycles where commit BW limit reached 2000system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 2001system.cpu1.rob.rob_reads 175201017 # The number of ROB reads 2002system.cpu1.rob.rob_writes 127586843 # The number of ROB writes 2003system.cpu1.timesIdled 1428644 # Number of times that the entire CPU went into an idle state and unscheduled itself 2004system.cpu1.idleCycles 296058429 # Total number of cycles that the CPU has spent unscheduled due to idling 2005system.cpu1.quiesceCycles 4796946974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2006system.cpu1.committedInsts 38803971 # Number of Instructions Simulated 2007system.cpu1.committedOps 49144375 # Number of Ops (including micro ops) Simulated 2008system.cpu1.committedInsts_total 38803971 # Number of Instructions Simulated 2009system.cpu1.cpi 10.661121 # CPI: Cycles Per Instruction 2010system.cpu1.cpi_total 10.661121 # CPI: Total CPI of All Threads 2011system.cpu1.ipc 0.093799 # IPC: Instructions Per Cycle 2012system.cpu1.ipc_total 0.093799 # IPC: Total IPC of All Threads 2013system.cpu1.int_regfile_reads 391634066 # number of integer regfile reads 2014system.cpu1.int_regfile_writes 56368159 # number of integer regfile writes 2015system.cpu1.fp_regfile_reads 5144 # number of floating regfile reads 2016system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes 2017system.cpu1.misc_regfile_reads 202762353 # number of misc regfile reads 2018system.cpu1.misc_regfile_writes 723009 # number of misc regfile writes 2019system.cpu1.icache.tags.replacements 614589 # number of replacements 2020system.cpu1.icache.tags.tagsinuse 498.738252 # Cycle average of tags in use 2021system.cpu1.icache.tags.total_refs 7056364 # Total number of references to valid blocks. 2022system.cpu1.icache.tags.sampled_refs 615101 # Sample count of references to valid blocks. 2023system.cpu1.icache.tags.avg_refs 11.471879 # Average number of references to valid blocks. 2024system.cpu1.icache.tags.warmup_cycle 74953244500 # Cycle when the warmup percentage was hit. 2025system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.738252 # Average occupied blocks per requestor 2026system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974098 # Average percentage of cache occupancy 2027system.cpu1.icache.tags.occ_percent::total 0.974098 # Average percentage of cache occupancy 2028system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2029system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 2030system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2031system.cpu1.icache.tags.tag_accesses 8332995 # Number of tag accesses 2032system.cpu1.icache.tags.data_accesses 8332995 # Number of data accesses 2033system.cpu1.icache.ReadReq_hits::cpu1.inst 7056364 # number of ReadReq hits 2034system.cpu1.icache.ReadReq_hits::total 7056364 # number of ReadReq hits 2035system.cpu1.icache.demand_hits::cpu1.inst 7056364 # number of demand (read+write) hits 2036system.cpu1.icache.demand_hits::total 7056364 # number of demand (read+write) hits 2037system.cpu1.icache.overall_hits::cpu1.inst 7056364 # number of overall hits 2038system.cpu1.icache.overall_hits::total 7056364 # number of overall hits 2039system.cpu1.icache.ReadReq_misses::cpu1.inst 661505 # number of ReadReq misses 2040system.cpu1.icache.ReadReq_misses::total 661505 # number of ReadReq misses 2041system.cpu1.icache.demand_misses::cpu1.inst 661505 # number of demand (read+write) misses 2042system.cpu1.icache.demand_misses::total 661505 # number of demand (read+write) misses 2043system.cpu1.icache.overall_misses::cpu1.inst 661505 # number of overall misses 2044system.cpu1.icache.overall_misses::total 661505 # number of overall misses 2045system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8964922762 # number of ReadReq miss cycles 2046system.cpu1.icache.ReadReq_miss_latency::total 8964922762 # number of ReadReq miss cycles 2047system.cpu1.icache.demand_miss_latency::cpu1.inst 8964922762 # number of demand (read+write) miss cycles 2048system.cpu1.icache.demand_miss_latency::total 8964922762 # number of demand (read+write) miss cycles 2049system.cpu1.icache.overall_miss_latency::cpu1.inst 8964922762 # number of overall miss cycles 2050system.cpu1.icache.overall_miss_latency::total 8964922762 # number of overall miss cycles 2051system.cpu1.icache.ReadReq_accesses::cpu1.inst 7717869 # number of ReadReq accesses(hits+misses) 2052system.cpu1.icache.ReadReq_accesses::total 7717869 # number of ReadReq accesses(hits+misses) 2053system.cpu1.icache.demand_accesses::cpu1.inst 7717869 # number of demand (read+write) accesses 2054system.cpu1.icache.demand_accesses::total 7717869 # number of demand (read+write) accesses 2055system.cpu1.icache.overall_accesses::cpu1.inst 7717869 # number of overall (read+write) accesses 2056system.cpu1.icache.overall_accesses::total 7717869 # number of overall (read+write) accesses 2057system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085711 # miss rate for ReadReq accesses 2058system.cpu1.icache.ReadReq_miss_rate::total 0.085711 # miss rate for ReadReq accesses 2059system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085711 # miss rate for demand accesses 2060system.cpu1.icache.demand_miss_rate::total 0.085711 # miss rate for demand accesses 2061system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085711 # miss rate for overall accesses 2062system.cpu1.icache.overall_miss_rate::total 0.085711 # miss rate for overall accesses 2063system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926 # average ReadReq miss latency 2064system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926 # average ReadReq miss latency 2065system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency 2066system.cpu1.icache.demand_avg_miss_latency::total 13552.312926 # average overall miss latency 2067system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency 2068system.cpu1.icache.overall_avg_miss_latency::total 13552.312926 # average overall miss latency 2069system.cpu1.icache.blocked_cycles::no_mshrs 3582 # number of cycles access was blocked 2070system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2071system.cpu1.icache.blocked::no_mshrs 212 # number of cycles access was blocked 2072system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2073system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.896226 # average number of cycles each access was blocked 2074system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2075system.cpu1.icache.fast_writes 0 # number of fast writes performed 2076system.cpu1.icache.cache_copies 0 # number of cache copies performed 2077system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46379 # number of ReadReq MSHR hits 2078system.cpu1.icache.ReadReq_mshr_hits::total 46379 # number of ReadReq MSHR hits 2079system.cpu1.icache.demand_mshr_hits::cpu1.inst 46379 # number of demand (read+write) MSHR hits 2080system.cpu1.icache.demand_mshr_hits::total 46379 # number of demand (read+write) MSHR hits 2081system.cpu1.icache.overall_mshr_hits::cpu1.inst 46379 # number of overall MSHR hits 2082system.cpu1.icache.overall_mshr_hits::total 46379 # number of overall MSHR hits 2083system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615126 # number of ReadReq MSHR misses 2084system.cpu1.icache.ReadReq_mshr_misses::total 615126 # number of ReadReq MSHR misses 2085system.cpu1.icache.demand_mshr_misses::cpu1.inst 615126 # number of demand (read+write) MSHR misses 2086system.cpu1.icache.demand_mshr_misses::total 615126 # number of demand (read+write) MSHR misses 2087system.cpu1.icache.overall_mshr_misses::cpu1.inst 615126 # number of overall MSHR misses 2088system.cpu1.icache.overall_mshr_misses::total 615126 # number of overall MSHR misses 2089system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7320744820 # number of ReadReq MSHR miss cycles 2090system.cpu1.icache.ReadReq_mshr_miss_latency::total 7320744820 # number of ReadReq MSHR miss cycles 2091system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7320744820 # number of demand (read+write) MSHR miss cycles 2092system.cpu1.icache.demand_mshr_miss_latency::total 7320744820 # number of demand (read+write) MSHR miss cycles 2093system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7320744820 # number of overall MSHR miss cycles 2094system.cpu1.icache.overall_mshr_miss_latency::total 7320744820 # number of overall MSHR miss cycles 2095system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3847250 # number of ReadReq MSHR uncacheable cycles 2096system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3847250 # number of ReadReq MSHR uncacheable cycles 2097system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3847250 # number of overall MSHR uncacheable cycles 2098system.cpu1.icache.overall_mshr_uncacheable_latency::total 3847250 # number of overall MSHR uncacheable cycles 2099system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for ReadReq accesses 2100system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079702 # mshr miss rate for ReadReq accesses 2101system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for demand accesses 2102system.cpu1.icache.demand_mshr_miss_rate::total 0.079702 # mshr miss rate for demand accesses 2103system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for overall accesses 2104system.cpu1.icache.overall_mshr_miss_rate::total 0.079702 # mshr miss rate for overall accesses 2105system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average ReadReq mshr miss latency 2106system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11901.211817 # average ReadReq mshr miss latency 2107system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency 2108system.cpu1.icache.demand_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency 2109system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency 2110system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency 2111system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2112system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2113system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2114system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2115system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2116system.cpu1.dcache.tags.replacements 363297 # number of replacements 2117system.cpu1.dcache.tags.tagsinuse 486.117445 # Cycle average of tags in use 2118system.cpu1.dcache.tags.total_refs 13019165 # Total number of references to valid blocks. 2119system.cpu1.dcache.tags.sampled_refs 363645 # Sample count of references to valid blocks. 2120system.cpu1.dcache.tags.avg_refs 35.801853 # Average number of references to valid blocks. 2121system.cpu1.dcache.tags.warmup_cycle 71011321250 # Cycle when the warmup percentage was hit. 2122system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.117445 # Average occupied blocks per requestor 2123system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949448 # Average percentage of cache occupancy 2124system.cpu1.dcache.tags.occ_percent::total 0.949448 # Average percentage of cache occupancy 2125system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 2126system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id 2127system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id 2128system.cpu1.dcache.tags.tag_accesses 60291027 # Number of tag accesses 2129system.cpu1.dcache.tags.data_accesses 60291027 # Number of data accesses 2130system.cpu1.dcache.ReadReq_hits::cpu1.data 8513196 # number of ReadReq hits 2131system.cpu1.dcache.ReadReq_hits::total 8513196 # number of ReadReq hits 2132system.cpu1.dcache.WriteReq_hits::cpu1.data 4271027 # number of WriteReq hits 2133system.cpu1.dcache.WriteReq_hits::total 4271027 # number of WriteReq hits 2134system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99804 # number of LoadLockedReq hits 2135system.cpu1.dcache.LoadLockedReq_hits::total 99804 # number of LoadLockedReq hits 2136system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97081 # number of StoreCondReq hits 2137system.cpu1.dcache.StoreCondReq_hits::total 97081 # number of StoreCondReq hits 2138system.cpu1.dcache.demand_hits::cpu1.data 12784223 # number of demand (read+write) hits 2139system.cpu1.dcache.demand_hits::total 12784223 # number of demand (read+write) hits 2140system.cpu1.dcache.overall_hits::cpu1.data 12784223 # number of overall hits 2141system.cpu1.dcache.overall_hits::total 12784223 # number of overall hits 2142system.cpu1.dcache.ReadReq_misses::cpu1.data 403038 # number of ReadReq misses 2143system.cpu1.dcache.ReadReq_misses::total 403038 # number of ReadReq misses 2144system.cpu1.dcache.WriteReq_misses::cpu1.data 1566274 # number of WriteReq misses 2145system.cpu1.dcache.WriteReq_misses::total 1566274 # number of WriteReq misses 2146system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14187 # number of LoadLockedReq misses 2147system.cpu1.dcache.LoadLockedReq_misses::total 14187 # number of LoadLockedReq misses 2148system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10911 # number of StoreCondReq misses 2149system.cpu1.dcache.StoreCondReq_misses::total 10911 # number of StoreCondReq misses 2150system.cpu1.dcache.demand_misses::cpu1.data 1969312 # number of demand (read+write) misses 2151system.cpu1.dcache.demand_misses::total 1969312 # number of demand (read+write) misses 2152system.cpu1.dcache.overall_misses::cpu1.data 1969312 # number of overall misses 2153system.cpu1.dcache.overall_misses::total 1969312 # number of overall misses 2154system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6108097691 # number of ReadReq miss cycles 2155system.cpu1.dcache.ReadReq_miss_latency::total 6108097691 # number of ReadReq miss cycles 2156system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 77891341203 # number of WriteReq miss cycles 2157system.cpu1.dcache.WriteReq_miss_latency::total 77891341203 # number of WriteReq miss cycles 2158system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131130743 # number of LoadLockedReq miss cycles 2159system.cpu1.dcache.LoadLockedReq_miss_latency::total 131130743 # number of LoadLockedReq miss cycles 2160system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58206088 # number of StoreCondReq miss cycles 2161system.cpu1.dcache.StoreCondReq_miss_latency::total 58206088 # number of StoreCondReq miss cycles 2162system.cpu1.dcache.demand_miss_latency::cpu1.data 83999438894 # number of demand (read+write) miss cycles 2163system.cpu1.dcache.demand_miss_latency::total 83999438894 # number of demand (read+write) miss cycles 2164system.cpu1.dcache.overall_miss_latency::cpu1.data 83999438894 # number of overall miss cycles 2165system.cpu1.dcache.overall_miss_latency::total 83999438894 # number of overall miss cycles 2166system.cpu1.dcache.ReadReq_accesses::cpu1.data 8916234 # number of ReadReq accesses(hits+misses) 2167system.cpu1.dcache.ReadReq_accesses::total 8916234 # number of ReadReq accesses(hits+misses) 2168system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837301 # number of WriteReq accesses(hits+misses) 2169system.cpu1.dcache.WriteReq_accesses::total 5837301 # number of WriteReq accesses(hits+misses) 2170system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113991 # number of LoadLockedReq accesses(hits+misses) 2171system.cpu1.dcache.LoadLockedReq_accesses::total 113991 # number of LoadLockedReq accesses(hits+misses) 2172system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107992 # number of StoreCondReq accesses(hits+misses) 2173system.cpu1.dcache.StoreCondReq_accesses::total 107992 # number of StoreCondReq accesses(hits+misses) 2174system.cpu1.dcache.demand_accesses::cpu1.data 14753535 # number of demand (read+write) accesses 2175system.cpu1.dcache.demand_accesses::total 14753535 # number of demand (read+write) accesses 2176system.cpu1.dcache.overall_accesses::cpu1.data 14753535 # number of overall (read+write) accesses 2177system.cpu1.dcache.overall_accesses::total 14753535 # number of overall (read+write) accesses 2178system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045203 # miss rate for ReadReq accesses 2179system.cpu1.dcache.ReadReq_miss_rate::total 0.045203 # miss rate for ReadReq accesses 2180system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268322 # miss rate for WriteReq accesses 2181system.cpu1.dcache.WriteReq_miss_rate::total 0.268322 # miss rate for WriteReq accesses 2182system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124457 # miss rate for LoadLockedReq accesses 2183system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124457 # miss rate for LoadLockedReq accesses 2184system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101035 # miss rate for StoreCondReq accesses 2185system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101035 # miss rate for StoreCondReq accesses 2186system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133481 # miss rate for demand accesses 2187system.cpu1.dcache.demand_miss_rate::total 0.133481 # miss rate for demand accesses 2188system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133481 # miss rate for overall accesses 2189system.cpu1.dcache.overall_miss_rate::total 0.133481 # miss rate for overall accesses 2190system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932 # average ReadReq miss latency 2191system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932 # average ReadReq miss latency 2192system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692 # average WriteReq miss latency 2193system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692 # average WriteReq miss latency 2194system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9243.021287 # average LoadLockedReq miss latency 2195system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9243.021287 # average LoadLockedReq miss latency 2196system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.624507 # average StoreCondReq miss latency 2197system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.624507 # average StoreCondReq miss latency 2198system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency 2199system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577 # average overall miss latency 2200system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency 2201system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577 # average overall miss latency 2202system.cpu1.dcache.blocked_cycles::no_mshrs 29593 # number of cycles access was blocked 2203system.cpu1.dcache.blocked_cycles::no_targets 18156 # number of cycles access was blocked 2204system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked 2205system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked 2206system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.003042 # average number of cycles each access was blocked 2207system.cpu1.dcache.avg_blocked_cycles::no_targets 103.748571 # average number of cycles each access was blocked 2208system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2209system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2210system.cpu1.dcache.writebacks::writebacks 327781 # number of writebacks 2211system.cpu1.dcache.writebacks::total 327781 # number of writebacks 2212system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171674 # number of ReadReq MSHR hits 2213system.cpu1.dcache.ReadReq_mshr_hits::total 171674 # number of ReadReq MSHR hits 2214system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1403027 # number of WriteReq MSHR hits 2215system.cpu1.dcache.WriteReq_mshr_hits::total 1403027 # number of WriteReq MSHR hits 2216system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1467 # number of LoadLockedReq MSHR hits 2217system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1467 # number of LoadLockedReq MSHR hits 2218system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574701 # number of demand (read+write) MSHR hits 2219system.cpu1.dcache.demand_mshr_hits::total 1574701 # number of demand (read+write) MSHR hits 2220system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574701 # number of overall MSHR hits 2221system.cpu1.dcache.overall_mshr_hits::total 1574701 # number of overall MSHR hits 2222system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231364 # number of ReadReq MSHR misses 2223system.cpu1.dcache.ReadReq_mshr_misses::total 231364 # number of ReadReq MSHR misses 2224system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163247 # number of WriteReq MSHR misses 2225system.cpu1.dcache.WriteReq_mshr_misses::total 163247 # number of WriteReq MSHR misses 2226system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses 2227system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses 2228system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10911 # number of StoreCondReq MSHR misses 2229system.cpu1.dcache.StoreCondReq_mshr_misses::total 10911 # number of StoreCondReq MSHR misses 2230system.cpu1.dcache.demand_mshr_misses::cpu1.data 394611 # number of demand (read+write) MSHR misses 2231system.cpu1.dcache.demand_mshr_misses::total 394611 # number of demand (read+write) MSHR misses 2232system.cpu1.dcache.overall_mshr_misses::cpu1.data 394611 # number of overall MSHR misses 2233system.cpu1.dcache.overall_mshr_misses::total 394611 # number of overall MSHR misses 2234system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2878773157 # number of ReadReq MSHR miss cycles 2235system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2878773157 # number of ReadReq MSHR miss cycles 2236system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7001686259 # number of WriteReq MSHR miss cycles 2237system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7001686259 # number of WriteReq MSHR miss cycles 2238system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89753005 # number of LoadLockedReq MSHR miss cycles 2239system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89753005 # number of LoadLockedReq MSHR miss cycles 2240system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36382912 # number of StoreCondReq MSHR miss cycles 2241system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36382912 # number of StoreCondReq MSHR miss cycles 2242system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9880459416 # number of demand (read+write) MSHR miss cycles 2243system.cpu1.dcache.demand_mshr_miss_latency::total 9880459416 # number of demand (read+write) MSHR miss cycles 2244system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9880459416 # number of overall MSHR miss cycles 2245system.cpu1.dcache.overall_mshr_miss_latency::total 9880459416 # number of overall MSHR miss cycles 2246system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012 # number of ReadReq MSHR uncacheable cycles 2247system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012 # number of ReadReq MSHR uncacheable cycles 2248system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25869959988 # number of WriteReq MSHR uncacheable cycles 2249system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25869959988 # number of WriteReq MSHR uncacheable cycles 2250system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000 # number of overall MSHR uncacheable cycles 2251system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000 # number of overall MSHR uncacheable cycles 2252system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025949 # mshr miss rate for ReadReq accesses 2253system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025949 # mshr miss rate for ReadReq accesses 2254system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027966 # mshr miss rate for WriteReq accesses 2255system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027966 # mshr miss rate for WriteReq accesses 2256system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111588 # mshr miss rate for LoadLockedReq accesses 2257system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111588 # mshr miss rate for LoadLockedReq accesses 2258system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101035 # mshr miss rate for StoreCondReq accesses 2259system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101035 # mshr miss rate for StoreCondReq accesses 2260system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for demand accesses 2261system.cpu1.dcache.demand_mshr_miss_rate::total 0.026747 # mshr miss rate for demand accesses 2262system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for overall accesses 2263system.cpu1.dcache.overall_mshr_miss_rate::total 0.026747 # mshr miss rate for overall accesses 2264system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914 # average ReadReq mshr miss latency 2265system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914 # average ReadReq mshr miss latency 2266system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393 # average WriteReq mshr miss latency 2267system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393 # average WriteReq mshr miss latency 2268system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7056.053852 # average LoadLockedReq mshr miss latency 2269system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7056.053852 # average LoadLockedReq mshr miss latency 2270system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3334.516726 # average StoreCondReq mshr miss latency 2271system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3334.516726 # average StoreCondReq mshr miss latency 2272system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency 2273system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency 2274system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency 2275system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency 2276system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2277system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2278system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2279system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2280system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2281system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2282system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2283system.iocache.tags.replacements 0 # number of replacements 2284system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 2285system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2286system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2287system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2288system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2289system.iocache.tags.tag_accesses 0 # Number of tag accesses 2290system.iocache.tags.data_accesses 0 # Number of data accesses 2291system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2292system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2293system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2294system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2295system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2296system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2297system.iocache.fast_writes 0 # number of fast writes performed 2298system.iocache.cache_copies 0 # number of cache copies performed 2299system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of ReadReq MSHR uncacheable cycles 2300system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356 # number of ReadReq MSHR uncacheable cycles 2301system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of overall MSHR uncacheable cycles 2302system.iocache.overall_mshr_uncacheable_latency::total 1735350782356 # number of overall MSHR uncacheable cycles 2303system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2304system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2305system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2306system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2307system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2308system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2309system.cpu0.kern.inst.quiesce 42636 # number of quiesce instructions executed 2310system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2311system.cpu1.kern.inst.quiesce 50408 # number of quiesce instructions executed 2312 2313---------- End Simulation Statistics ---------- 2314