config.ini revision 9449
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/gem5/dist/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename= 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0 22kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem system.realview.nvmem 28multi_proc=true 29num_work_ids=16 30readfile=tests/halt.sh 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clock=1000 44delay=50000 45ranges=268435456:520093695 1073741824:1610612735 46req_size=16 47resp_size=16 48master=system.iobus.slave[0] 49slave=system.membus.master[0] 50 51[system.cf0] 52type=IdeDisk 53children=image 54delay=1000000 55driveID=master 56image=system.cf0.image 57 58[system.cf0.image] 59type=CowDiskImage 60children=child 61child=system.cf0.image.child 62image_file= 63read_only=false 64table_size=65536 65 66[system.cf0.image.child] 67type=RawDiskImage 68image_file=/gem5/dist/disks/linux-arm-ael.img 69read_only=true 70 71[system.cpu0] 72type=DerivO3CPU 73children=dcache dtb fuPool icache interrupts isa itb tracer 74BTBEntries=4096 75BTBTagSize=16 76LFSTSize=1024 77LQEntries=32 78LSQCheckLoads=true 79LSQDepCheckShift=4 80RASSize=16 81SQEntries=32 82SSITSize=1024 83activity=0 84backComSize=5 85cachePorts=200 86checker=Null 87choiceCtrBits=2 88choicePredictorSize=8192 89clock=500 90commitToDecodeDelay=1 91commitToFetchDelay=1 92commitToIEWDelay=1 93commitToRenameDelay=1 94commitWidth=8 95cpu_id=0 96decodeToFetchDelay=1 97decodeToRenameDelay=1 98decodeWidth=8 99dispatchWidth=8 100do_checkpoint_insts=true 101do_quiesce=true 102do_statistics_insts=true 103dtb=system.cpu0.dtb 104fetchToDecodeDelay=1 105fetchTrapLatency=1 106fetchWidth=8 107forwardComSize=5 108fuPool=system.cpu0.fuPool 109function_trace=false 110function_trace_start=0 111globalCtrBits=2 112globalHistoryBits=13 113globalPredictorSize=8192 114iewToCommitDelay=1 115iewToDecodeDelay=1 116iewToFetchDelay=1 117iewToRenameDelay=1 118instShiftAmt=2 119interrupts=system.cpu0.interrupts 120isa=system.cpu0.isa 121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu0.itb 124localCtrBits=2 125localHistoryBits=11 126localHistoryTableSize=2048 127localPredictorSize=2048 128max_insts_all_threads=0 129max_insts_any_thread=0 130max_loads_all_threads=0 131max_loads_any_thread=0 132needsTSO=false 133numIQEntries=64 134numPhysFloatRegs=256 135numPhysIntRegs=256 136numROBEntries=192 137numRobs=1 138numThreads=1 139predType=tournament 140profile=0 141progress_interval=0 142renameToDecodeDelay=1 143renameToFetchDelay=1 144renameToIEWDelay=2 145renameToROBDelay=1 146renameWidth=8 147smtCommitPolicy=RoundRobin 148smtFetchPolicy=SingleThread 149smtIQPolicy=Partitioned 150smtIQThreshold=100 151smtLSQPolicy=Partitioned 152smtLSQThreshold=100 153smtNumFetchingThreads=1 154smtROBPolicy=Partitioned 155smtROBThreshold=100 156squashWidth=8 157store_set_clear_period=250000 158switched_out=false 159system=system 160tracer=system.cpu0.tracer 161trapLatency=13 162wbDepth=1 163wbWidth=8 164workload= 165dcache_port=system.cpu0.dcache.cpu_side 166icache_port=system.cpu0.icache.cpu_side 167 168[system.cpu0.dcache] 169type=BaseCache 170addr_ranges=0:18446744073709551615 171assoc=4 172block_size=64 173clock=500 174forward_snoops=true 175hit_latency=2 176is_top_level=true 177max_miss_count=0 178mshrs=4 179prefetch_on_access=false 180prefetcher=Null 181response_latency=2 182size=32768 183system=system 184tgts_per_mshr=20 185two_queue=false 186write_buffers=8 187cpu_side=system.cpu0.dcache_port 188mem_side=system.toL2Bus.slave[1] 189 190[system.cpu0.dtb] 191type=ArmTLB 192children=walker 193size=64 194walker=system.cpu0.dtb.walker 195 196[system.cpu0.dtb.walker] 197type=ArmTableWalker 198clock=500 199num_squash_per_cycle=2 200sys=system 201port=system.toL2Bus.slave[3] 202 203[system.cpu0.fuPool] 204type=FUPool 205children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 206FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 207 208[system.cpu0.fuPool.FUList0] 209type=FUDesc 210children=opList 211count=6 212opList=system.cpu0.fuPool.FUList0.opList 213 214[system.cpu0.fuPool.FUList0.opList] 215type=OpDesc 216issueLat=1 217opClass=IntAlu 218opLat=1 219 220[system.cpu0.fuPool.FUList1] 221type=FUDesc 222children=opList0 opList1 223count=2 224opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 225 226[system.cpu0.fuPool.FUList1.opList0] 227type=OpDesc 228issueLat=1 229opClass=IntMult 230opLat=3 231 232[system.cpu0.fuPool.FUList1.opList1] 233type=OpDesc 234issueLat=19 235opClass=IntDiv 236opLat=20 237 238[system.cpu0.fuPool.FUList2] 239type=FUDesc 240children=opList0 opList1 opList2 241count=4 242opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 243 244[system.cpu0.fuPool.FUList2.opList0] 245type=OpDesc 246issueLat=1 247opClass=FloatAdd 248opLat=2 249 250[system.cpu0.fuPool.FUList2.opList1] 251type=OpDesc 252issueLat=1 253opClass=FloatCmp 254opLat=2 255 256[system.cpu0.fuPool.FUList2.opList2] 257type=OpDesc 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu0.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 267 268[system.cpu0.fuPool.FUList3.opList0] 269type=OpDesc 270issueLat=1 271opClass=FloatMult 272opLat=4 273 274[system.cpu0.fuPool.FUList3.opList1] 275type=OpDesc 276issueLat=12 277opClass=FloatDiv 278opLat=12 279 280[system.cpu0.fuPool.FUList3.opList2] 281type=OpDesc 282issueLat=24 283opClass=FloatSqrt 284opLat=24 285 286[system.cpu0.fuPool.FUList4] 287type=FUDesc 288children=opList 289count=0 290opList=system.cpu0.fuPool.FUList4.opList 291 292[system.cpu0.fuPool.FUList4.opList] 293type=OpDesc 294issueLat=1 295opClass=MemRead 296opLat=1 297 298[system.cpu0.fuPool.FUList5] 299type=FUDesc 300children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 301count=4 302opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 303 304[system.cpu0.fuPool.FUList5.opList00] 305type=OpDesc 306issueLat=1 307opClass=SimdAdd 308opLat=1 309 310[system.cpu0.fuPool.FUList5.opList01] 311type=OpDesc 312issueLat=1 313opClass=SimdAddAcc 314opLat=1 315 316[system.cpu0.fuPool.FUList5.opList02] 317type=OpDesc 318issueLat=1 319opClass=SimdAlu 320opLat=1 321 322[system.cpu0.fuPool.FUList5.opList03] 323type=OpDesc 324issueLat=1 325opClass=SimdCmp 326opLat=1 327 328[system.cpu0.fuPool.FUList5.opList04] 329type=OpDesc 330issueLat=1 331opClass=SimdCvt 332opLat=1 333 334[system.cpu0.fuPool.FUList5.opList05] 335type=OpDesc 336issueLat=1 337opClass=SimdMisc 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList06] 341type=OpDesc 342issueLat=1 343opClass=SimdMult 344opLat=1 345 346[system.cpu0.fuPool.FUList5.opList07] 347type=OpDesc 348issueLat=1 349opClass=SimdMultAcc 350opLat=1 351 352[system.cpu0.fuPool.FUList5.opList08] 353type=OpDesc 354issueLat=1 355opClass=SimdShift 356opLat=1 357 358[system.cpu0.fuPool.FUList5.opList09] 359type=OpDesc 360issueLat=1 361opClass=SimdShiftAcc 362opLat=1 363 364[system.cpu0.fuPool.FUList5.opList10] 365type=OpDesc 366issueLat=1 367opClass=SimdSqrt 368opLat=1 369 370[system.cpu0.fuPool.FUList5.opList11] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatAdd 374opLat=1 375 376[system.cpu0.fuPool.FUList5.opList12] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatAlu 380opLat=1 381 382[system.cpu0.fuPool.FUList5.opList13] 383type=OpDesc 384issueLat=1 385opClass=SimdFloatCmp 386opLat=1 387 388[system.cpu0.fuPool.FUList5.opList14] 389type=OpDesc 390issueLat=1 391opClass=SimdFloatCvt 392opLat=1 393 394[system.cpu0.fuPool.FUList5.opList15] 395type=OpDesc 396issueLat=1 397opClass=SimdFloatDiv 398opLat=1 399 400[system.cpu0.fuPool.FUList5.opList16] 401type=OpDesc 402issueLat=1 403opClass=SimdFloatMisc 404opLat=1 405 406[system.cpu0.fuPool.FUList5.opList17] 407type=OpDesc 408issueLat=1 409opClass=SimdFloatMult 410opLat=1 411 412[system.cpu0.fuPool.FUList5.opList18] 413type=OpDesc 414issueLat=1 415opClass=SimdFloatMultAcc 416opLat=1 417 418[system.cpu0.fuPool.FUList5.opList19] 419type=OpDesc 420issueLat=1 421opClass=SimdFloatSqrt 422opLat=1 423 424[system.cpu0.fuPool.FUList6] 425type=FUDesc 426children=opList 427count=0 428opList=system.cpu0.fuPool.FUList6.opList 429 430[system.cpu0.fuPool.FUList6.opList] 431type=OpDesc 432issueLat=1 433opClass=MemWrite 434opLat=1 435 436[system.cpu0.fuPool.FUList7] 437type=FUDesc 438children=opList0 opList1 439count=4 440opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 441 442[system.cpu0.fuPool.FUList7.opList0] 443type=OpDesc 444issueLat=1 445opClass=MemRead 446opLat=1 447 448[system.cpu0.fuPool.FUList7.opList1] 449type=OpDesc 450issueLat=1 451opClass=MemWrite 452opLat=1 453 454[system.cpu0.fuPool.FUList8] 455type=FUDesc 456children=opList 457count=1 458opList=system.cpu0.fuPool.FUList8.opList 459 460[system.cpu0.fuPool.FUList8.opList] 461type=OpDesc 462issueLat=3 463opClass=IprAccess 464opLat=3 465 466[system.cpu0.icache] 467type=BaseCache 468addr_ranges=0:18446744073709551615 469assoc=1 470block_size=64 471clock=500 472forward_snoops=true 473hit_latency=2 474is_top_level=true 475max_miss_count=0 476mshrs=4 477prefetch_on_access=false 478prefetcher=Null 479response_latency=2 480size=32768 481system=system 482tgts_per_mshr=20 483two_queue=false 484write_buffers=8 485cpu_side=system.cpu0.icache_port 486mem_side=system.toL2Bus.slave[0] 487 488[system.cpu0.interrupts] 489type=ArmInterrupts 490 491[system.cpu0.isa] 492type=ArmISA 493fpsid=1090793632 494id_isar0=34607377 495id_isar1=34677009 496id_isar2=555950401 497id_isar3=17899825 498id_isar4=268501314 499id_isar5=0 500id_mmfr0=3 501id_mmfr1=0 502id_mmfr2=19070976 503id_mmfr3=4027589137 504id_pfr0=49 505id_pfr1=1 506midr=890224640 507 508[system.cpu0.itb] 509type=ArmTLB 510children=walker 511size=64 512walker=system.cpu0.itb.walker 513 514[system.cpu0.itb.walker] 515type=ArmTableWalker 516clock=500 517num_squash_per_cycle=2 518sys=system 519port=system.toL2Bus.slave[2] 520 521[system.cpu0.tracer] 522type=ExeTracer 523 524[system.cpu1] 525type=DerivO3CPU 526children=dcache dtb fuPool icache interrupts isa itb tracer 527BTBEntries=4096 528BTBTagSize=16 529LFSTSize=1024 530LQEntries=32 531LSQCheckLoads=true 532LSQDepCheckShift=4 533RASSize=16 534SQEntries=32 535SSITSize=1024 536activity=0 537backComSize=5 538cachePorts=200 539checker=Null 540choiceCtrBits=2 541choicePredictorSize=8192 542clock=500 543commitToDecodeDelay=1 544commitToFetchDelay=1 545commitToIEWDelay=1 546commitToRenameDelay=1 547commitWidth=8 548cpu_id=1 549decodeToFetchDelay=1 550decodeToRenameDelay=1 551decodeWidth=8 552dispatchWidth=8 553do_checkpoint_insts=true 554do_quiesce=true 555do_statistics_insts=true 556dtb=system.cpu1.dtb 557fetchToDecodeDelay=1 558fetchTrapLatency=1 559fetchWidth=8 560forwardComSize=5 561fuPool=system.cpu1.fuPool 562function_trace=false 563function_trace_start=0 564globalCtrBits=2 565globalHistoryBits=13 566globalPredictorSize=8192 567iewToCommitDelay=1 568iewToDecodeDelay=1 569iewToFetchDelay=1 570iewToRenameDelay=1 571instShiftAmt=2 572interrupts=system.cpu1.interrupts 573isa=system.cpu1.isa 574issueToExecuteDelay=1 575issueWidth=8 576itb=system.cpu1.itb 577localCtrBits=2 578localHistoryBits=11 579localHistoryTableSize=2048 580localPredictorSize=2048 581max_insts_all_threads=0 582max_insts_any_thread=0 583max_loads_all_threads=0 584max_loads_any_thread=0 585needsTSO=false 586numIQEntries=64 587numPhysFloatRegs=256 588numPhysIntRegs=256 589numROBEntries=192 590numRobs=1 591numThreads=1 592predType=tournament 593profile=0 594progress_interval=0 595renameToDecodeDelay=1 596renameToFetchDelay=1 597renameToIEWDelay=2 598renameToROBDelay=1 599renameWidth=8 600smtCommitPolicy=RoundRobin 601smtFetchPolicy=SingleThread 602smtIQPolicy=Partitioned 603smtIQThreshold=100 604smtLSQPolicy=Partitioned 605smtLSQThreshold=100 606smtNumFetchingThreads=1 607smtROBPolicy=Partitioned 608smtROBThreshold=100 609squashWidth=8 610store_set_clear_period=250000 611switched_out=false 612system=system 613tracer=system.cpu1.tracer 614trapLatency=13 615wbDepth=1 616wbWidth=8 617workload= 618dcache_port=system.cpu1.dcache.cpu_side 619icache_port=system.cpu1.icache.cpu_side 620 621[system.cpu1.dcache] 622type=BaseCache 623addr_ranges=0:18446744073709551615 624assoc=4 625block_size=64 626clock=500 627forward_snoops=true 628hit_latency=2 629is_top_level=true 630max_miss_count=0 631mshrs=4 632prefetch_on_access=false 633prefetcher=Null 634response_latency=2 635size=32768 636system=system 637tgts_per_mshr=20 638two_queue=false 639write_buffers=8 640cpu_side=system.cpu1.dcache_port 641mem_side=system.toL2Bus.slave[5] 642 643[system.cpu1.dtb] 644type=ArmTLB 645children=walker 646size=64 647walker=system.cpu1.dtb.walker 648 649[system.cpu1.dtb.walker] 650type=ArmTableWalker 651clock=500 652num_squash_per_cycle=2 653sys=system 654port=system.toL2Bus.slave[7] 655 656[system.cpu1.fuPool] 657type=FUPool 658children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 659FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 660 661[system.cpu1.fuPool.FUList0] 662type=FUDesc 663children=opList 664count=6 665opList=system.cpu1.fuPool.FUList0.opList 666 667[system.cpu1.fuPool.FUList0.opList] 668type=OpDesc 669issueLat=1 670opClass=IntAlu 671opLat=1 672 673[system.cpu1.fuPool.FUList1] 674type=FUDesc 675children=opList0 opList1 676count=2 677opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 678 679[system.cpu1.fuPool.FUList1.opList0] 680type=OpDesc 681issueLat=1 682opClass=IntMult 683opLat=3 684 685[system.cpu1.fuPool.FUList1.opList1] 686type=OpDesc 687issueLat=19 688opClass=IntDiv 689opLat=20 690 691[system.cpu1.fuPool.FUList2] 692type=FUDesc 693children=opList0 opList1 opList2 694count=4 695opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 696 697[system.cpu1.fuPool.FUList2.opList0] 698type=OpDesc 699issueLat=1 700opClass=FloatAdd 701opLat=2 702 703[system.cpu1.fuPool.FUList2.opList1] 704type=OpDesc 705issueLat=1 706opClass=FloatCmp 707opLat=2 708 709[system.cpu1.fuPool.FUList2.opList2] 710type=OpDesc 711issueLat=1 712opClass=FloatCvt 713opLat=2 714 715[system.cpu1.fuPool.FUList3] 716type=FUDesc 717children=opList0 opList1 opList2 718count=2 719opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 720 721[system.cpu1.fuPool.FUList3.opList0] 722type=OpDesc 723issueLat=1 724opClass=FloatMult 725opLat=4 726 727[system.cpu1.fuPool.FUList3.opList1] 728type=OpDesc 729issueLat=12 730opClass=FloatDiv 731opLat=12 732 733[system.cpu1.fuPool.FUList3.opList2] 734type=OpDesc 735issueLat=24 736opClass=FloatSqrt 737opLat=24 738 739[system.cpu1.fuPool.FUList4] 740type=FUDesc 741children=opList 742count=0 743opList=system.cpu1.fuPool.FUList4.opList 744 745[system.cpu1.fuPool.FUList4.opList] 746type=OpDesc 747issueLat=1 748opClass=MemRead 749opLat=1 750 751[system.cpu1.fuPool.FUList5] 752type=FUDesc 753children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 754count=4 755opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 756 757[system.cpu1.fuPool.FUList5.opList00] 758type=OpDesc 759issueLat=1 760opClass=SimdAdd 761opLat=1 762 763[system.cpu1.fuPool.FUList5.opList01] 764type=OpDesc 765issueLat=1 766opClass=SimdAddAcc 767opLat=1 768 769[system.cpu1.fuPool.FUList5.opList02] 770type=OpDesc 771issueLat=1 772opClass=SimdAlu 773opLat=1 774 775[system.cpu1.fuPool.FUList5.opList03] 776type=OpDesc 777issueLat=1 778opClass=SimdCmp 779opLat=1 780 781[system.cpu1.fuPool.FUList5.opList04] 782type=OpDesc 783issueLat=1 784opClass=SimdCvt 785opLat=1 786 787[system.cpu1.fuPool.FUList5.opList05] 788type=OpDesc 789issueLat=1 790opClass=SimdMisc 791opLat=1 792 793[system.cpu1.fuPool.FUList5.opList06] 794type=OpDesc 795issueLat=1 796opClass=SimdMult 797opLat=1 798 799[system.cpu1.fuPool.FUList5.opList07] 800type=OpDesc 801issueLat=1 802opClass=SimdMultAcc 803opLat=1 804 805[system.cpu1.fuPool.FUList5.opList08] 806type=OpDesc 807issueLat=1 808opClass=SimdShift 809opLat=1 810 811[system.cpu1.fuPool.FUList5.opList09] 812type=OpDesc 813issueLat=1 814opClass=SimdShiftAcc 815opLat=1 816 817[system.cpu1.fuPool.FUList5.opList10] 818type=OpDesc 819issueLat=1 820opClass=SimdSqrt 821opLat=1 822 823[system.cpu1.fuPool.FUList5.opList11] 824type=OpDesc 825issueLat=1 826opClass=SimdFloatAdd 827opLat=1 828 829[system.cpu1.fuPool.FUList5.opList12] 830type=OpDesc 831issueLat=1 832opClass=SimdFloatAlu 833opLat=1 834 835[system.cpu1.fuPool.FUList5.opList13] 836type=OpDesc 837issueLat=1 838opClass=SimdFloatCmp 839opLat=1 840 841[system.cpu1.fuPool.FUList5.opList14] 842type=OpDesc 843issueLat=1 844opClass=SimdFloatCvt 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList15] 848type=OpDesc 849issueLat=1 850opClass=SimdFloatDiv 851opLat=1 852 853[system.cpu1.fuPool.FUList5.opList16] 854type=OpDesc 855issueLat=1 856opClass=SimdFloatMisc 857opLat=1 858 859[system.cpu1.fuPool.FUList5.opList17] 860type=OpDesc 861issueLat=1 862opClass=SimdFloatMult 863opLat=1 864 865[system.cpu1.fuPool.FUList5.opList18] 866type=OpDesc 867issueLat=1 868opClass=SimdFloatMultAcc 869opLat=1 870 871[system.cpu1.fuPool.FUList5.opList19] 872type=OpDesc 873issueLat=1 874opClass=SimdFloatSqrt 875opLat=1 876 877[system.cpu1.fuPool.FUList6] 878type=FUDesc 879children=opList 880count=0 881opList=system.cpu1.fuPool.FUList6.opList 882 883[system.cpu1.fuPool.FUList6.opList] 884type=OpDesc 885issueLat=1 886opClass=MemWrite 887opLat=1 888 889[system.cpu1.fuPool.FUList7] 890type=FUDesc 891children=opList0 opList1 892count=4 893opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 894 895[system.cpu1.fuPool.FUList7.opList0] 896type=OpDesc 897issueLat=1 898opClass=MemRead 899opLat=1 900 901[system.cpu1.fuPool.FUList7.opList1] 902type=OpDesc 903issueLat=1 904opClass=MemWrite 905opLat=1 906 907[system.cpu1.fuPool.FUList8] 908type=FUDesc 909children=opList 910count=1 911opList=system.cpu1.fuPool.FUList8.opList 912 913[system.cpu1.fuPool.FUList8.opList] 914type=OpDesc 915issueLat=3 916opClass=IprAccess 917opLat=3 918 919[system.cpu1.icache] 920type=BaseCache 921addr_ranges=0:18446744073709551615 922assoc=1 923block_size=64 924clock=500 925forward_snoops=true 926hit_latency=2 927is_top_level=true 928max_miss_count=0 929mshrs=4 930prefetch_on_access=false 931prefetcher=Null 932response_latency=2 933size=32768 934system=system 935tgts_per_mshr=20 936two_queue=false 937write_buffers=8 938cpu_side=system.cpu1.icache_port 939mem_side=system.toL2Bus.slave[4] 940 941[system.cpu1.interrupts] 942type=ArmInterrupts 943 944[system.cpu1.isa] 945type=ArmISA 946fpsid=1090793632 947id_isar0=34607377 948id_isar1=34677009 949id_isar2=555950401 950id_isar3=17899825 951id_isar4=268501314 952id_isar5=0 953id_mmfr0=3 954id_mmfr1=0 955id_mmfr2=19070976 956id_mmfr3=4027589137 957id_pfr0=49 958id_pfr1=1 959midr=890224640 960 961[system.cpu1.itb] 962type=ArmTLB 963children=walker 964size=64 965walker=system.cpu1.itb.walker 966 967[system.cpu1.itb.walker] 968type=ArmTableWalker 969clock=500 970num_squash_per_cycle=2 971sys=system 972port=system.toL2Bus.slave[6] 973 974[system.cpu1.tracer] 975type=ExeTracer 976 977[system.intrctrl] 978type=IntrControl 979sys=system 980 981[system.iobus] 982type=NoncoherentBus 983block_size=64 984clock=1000 985header_cycles=1 986use_default_range=false 987width=8 988master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 989slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 990 991[system.iocache] 992type=BaseCache 993addr_ranges=0:134217727 994assoc=8 995block_size=64 996clock=1000 997forward_snoops=false 998hit_latency=50 999is_top_level=true 1000max_miss_count=0 1001mshrs=20 1002prefetch_on_access=false 1003prefetcher=Null 1004response_latency=50 1005size=1024 1006system=system 1007tgts_per_mshr=12 1008two_queue=false 1009write_buffers=8 1010cpu_side=system.iobus.master[25] 1011mem_side=system.membus.slave[2] 1012 1013[system.l2c] 1014type=BaseCache 1015addr_ranges=0:18446744073709551615 1016assoc=8 1017block_size=64 1018clock=500 1019forward_snoops=true 1020hit_latency=20 1021is_top_level=false 1022max_miss_count=0 1023mshrs=20 1024prefetch_on_access=false 1025prefetcher=Null 1026response_latency=20 1027size=4194304 1028system=system 1029tgts_per_mshr=12 1030two_queue=false 1031write_buffers=8 1032cpu_side=system.toL2Bus.master[0] 1033mem_side=system.membus.slave[1] 1034 1035[system.membus] 1036type=CoherentBus 1037children=badaddr_responder 1038block_size=64 1039clock=1000 1040header_cycles=1 1041use_default_range=false 1042width=8 1043default=system.membus.badaddr_responder.pio 1044master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 1045slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1046 1047[system.membus.badaddr_responder] 1048type=IsaFake 1049clock=1000 1050fake_mem=false 1051pio_addr=0 1052pio_latency=100000 1053pio_size=8 1054ret_bad_addr=true 1055ret_data16=65535 1056ret_data32=4294967295 1057ret_data64=18446744073709551615 1058ret_data8=255 1059system=system 1060update_data=false 1061warn_access=warn 1062pio=system.membus.default 1063 1064[system.physmem] 1065type=SimpleDRAM 1066addr_mapping=openmap 1067banks_per_rank=8 1068clock=1000 1069conf_table_reported=true 1070in_addr_map=true 1071lines_per_rowbuffer=64 1072mem_sched_policy=fcfs 1073null=false 1074page_policy=open 1075range=0:134217727 1076ranks_per_channel=2 1077read_buffer_size=32 1078tBURST=4000 1079tCL=14000 1080tRCD=14000 1081tREFI=7800000 1082tRFC=300000 1083tRP=14000 1084tWTR=1000 1085write_buffer_size=32 1086write_thresh_perc=70 1087zero=false 1088port=system.membus.master[2] 1089 1090[system.realview] 1091type=RealView 1092children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1093intrctrl=system.intrctrl 1094max_mem_size=268435456 1095mem_start_addr=0 1096pci_cfg_base=0 1097system=system 1098 1099[system.realview.a9scu] 1100type=A9SCU 1101clock=1000 1102pio_addr=520093696 1103pio_latency=100000 1104system=system 1105pio=system.membus.master[5] 1106 1107[system.realview.aaci_fake] 1108type=AmbaFake 1109amba_id=0 1110clock=1000 1111ignore_access=false 1112pio_addr=268451840 1113pio_latency=100000 1114system=system 1115pio=system.iobus.master[21] 1116 1117[system.realview.cf_ctrl] 1118type=IdeController 1119BAR0=402653184 1120BAR0LegacyIO=true 1121BAR0Size=16 1122BAR1=402653440 1123BAR1LegacyIO=true 1124BAR1Size=1 1125BAR2=1 1126BAR2LegacyIO=false 1127BAR2Size=8 1128BAR3=1 1129BAR3LegacyIO=false 1130BAR3Size=4 1131BAR4=1 1132BAR4LegacyIO=false 1133BAR4Size=16 1134BAR5=1 1135BAR5LegacyIO=false 1136BAR5Size=0 1137BIST=0 1138CacheLineSize=0 1139CardbusCIS=0 1140ClassCode=1 1141Command=1 1142DeviceID=28945 1143ExpansionROM=0 1144HeaderType=0 1145InterruptLine=31 1146InterruptPin=1 1147LatencyTimer=0 1148MaximumLatency=0 1149MinimumGrant=0 1150ProgIF=133 1151Revision=0 1152Status=640 1153SubClassCode=1 1154SubsystemID=0 1155SubsystemVendorID=0 1156VendorID=32902 1157clock=1000 1158config_latency=20000 1159ctrl_offset=2 1160disks=system.cf0 1161io_shift=1 1162pci_bus=2 1163pci_dev=7 1164pci_func=0 1165pio_latency=30000 1166platform=system.realview 1167system=system 1168config=system.iobus.master[8] 1169dma=system.iobus.slave[2] 1170pio=system.iobus.master[7] 1171 1172[system.realview.clcd] 1173type=Pl111 1174amba_id=1315089 1175clock=1000 1176gic=system.realview.gic 1177int_num=55 1178pio_addr=268566528 1179pio_latency=10000 1180pixel_clock=41667 1181system=system 1182vnc=system.vncserver 1183dma=system.iobus.slave[1] 1184pio=system.iobus.master[4] 1185 1186[system.realview.dmac_fake] 1187type=AmbaFake 1188amba_id=0 1189clock=1000 1190ignore_access=false 1191pio_addr=268632064 1192pio_latency=100000 1193system=system 1194pio=system.iobus.master[9] 1195 1196[system.realview.flash_fake] 1197type=IsaFake 1198clock=1000 1199fake_mem=true 1200pio_addr=1073741824 1201pio_latency=100000 1202pio_size=536870912 1203ret_bad_addr=false 1204ret_data16=65535 1205ret_data32=4294967295 1206ret_data64=18446744073709551615 1207ret_data8=255 1208system=system 1209update_data=false 1210warn_access= 1211pio=system.iobus.master[24] 1212 1213[system.realview.gic] 1214type=Gic 1215clock=1000 1216cpu_addr=520093952 1217cpu_pio_delay=10000 1218dist_addr=520097792 1219dist_pio_delay=10000 1220int_latency=10000 1221it_lines=128 1222platform=system.realview 1223system=system 1224pio=system.membus.master[3] 1225 1226[system.realview.gpio0_fake] 1227type=AmbaFake 1228amba_id=0 1229clock=1000 1230ignore_access=false 1231pio_addr=268513280 1232pio_latency=100000 1233system=system 1234pio=system.iobus.master[16] 1235 1236[system.realview.gpio1_fake] 1237type=AmbaFake 1238amba_id=0 1239clock=1000 1240ignore_access=false 1241pio_addr=268517376 1242pio_latency=100000 1243system=system 1244pio=system.iobus.master[17] 1245 1246[system.realview.gpio2_fake] 1247type=AmbaFake 1248amba_id=0 1249clock=1000 1250ignore_access=false 1251pio_addr=268521472 1252pio_latency=100000 1253system=system 1254pio=system.iobus.master[18] 1255 1256[system.realview.kmi0] 1257type=Pl050 1258amba_id=1314896 1259clock=1000 1260gic=system.realview.gic 1261int_delay=1000000 1262int_num=52 1263is_mouse=false 1264pio_addr=268460032 1265pio_latency=100000 1266system=system 1267vnc=system.vncserver 1268pio=system.iobus.master[5] 1269 1270[system.realview.kmi1] 1271type=Pl050 1272amba_id=1314896 1273clock=1000 1274gic=system.realview.gic 1275int_delay=1000000 1276int_num=53 1277is_mouse=true 1278pio_addr=268464128 1279pio_latency=100000 1280system=system 1281vnc=system.vncserver 1282pio=system.iobus.master[6] 1283 1284[system.realview.l2x0_fake] 1285type=IsaFake 1286clock=1000 1287fake_mem=false 1288pio_addr=520101888 1289pio_latency=100000 1290pio_size=4095 1291ret_bad_addr=false 1292ret_data16=65535 1293ret_data32=4294967295 1294ret_data64=18446744073709551615 1295ret_data8=255 1296system=system 1297update_data=false 1298warn_access= 1299pio=system.membus.master[4] 1300 1301[system.realview.local_cpu_timer] 1302type=CpuLocalTimer 1303clock=1000 1304gic=system.realview.gic 1305int_num_timer=29 1306int_num_watchdog=30 1307pio_addr=520095232 1308pio_latency=100000 1309system=system 1310pio=system.membus.master[6] 1311 1312[system.realview.mmc_fake] 1313type=AmbaFake 1314amba_id=0 1315clock=1000 1316ignore_access=false 1317pio_addr=268455936 1318pio_latency=100000 1319system=system 1320pio=system.iobus.master[22] 1321 1322[system.realview.nvmem] 1323type=SimpleMemory 1324bandwidth=73.000000 1325clock=1000 1326conf_table_reported=false 1327in_addr_map=true 1328latency=30000 1329latency_var=0 1330null=false 1331range=2147483648:2214592511 1332zero=true 1333port=system.membus.master[1] 1334 1335[system.realview.realview_io] 1336type=RealViewCtrl 1337clock=1000 1338idreg=0 1339pio_addr=268435456 1340pio_latency=100000 1341proc_id0=201326592 1342proc_id1=201327138 1343system=system 1344pio=system.iobus.master[1] 1345 1346[system.realview.rtc] 1347type=PL031 1348amba_id=3412017 1349clock=1000 1350gic=system.realview.gic 1351int_delay=100000 1352int_num=42 1353pio_addr=268529664 1354pio_latency=100000 1355system=system 1356time=Thu Jan 1 00:00:00 2009 1357pio=system.iobus.master[23] 1358 1359[system.realview.sci_fake] 1360type=AmbaFake 1361amba_id=0 1362clock=1000 1363ignore_access=false 1364pio_addr=268492800 1365pio_latency=100000 1366system=system 1367pio=system.iobus.master[20] 1368 1369[system.realview.smc_fake] 1370type=AmbaFake 1371amba_id=0 1372clock=1000 1373ignore_access=false 1374pio_addr=269357056 1375pio_latency=100000 1376system=system 1377pio=system.iobus.master[13] 1378 1379[system.realview.sp810_fake] 1380type=AmbaFake 1381amba_id=0 1382clock=1000 1383ignore_access=true 1384pio_addr=268439552 1385pio_latency=100000 1386system=system 1387pio=system.iobus.master[14] 1388 1389[system.realview.ssp_fake] 1390type=AmbaFake 1391amba_id=0 1392clock=1000 1393ignore_access=false 1394pio_addr=268488704 1395pio_latency=100000 1396system=system 1397pio=system.iobus.master[19] 1398 1399[system.realview.timer0] 1400type=Sp804 1401amba_id=1316868 1402clock=1000 1403clock0=1000000 1404clock1=1000000 1405gic=system.realview.gic 1406int_num0=36 1407int_num1=36 1408pio_addr=268505088 1409pio_latency=100000 1410system=system 1411pio=system.iobus.master[2] 1412 1413[system.realview.timer1] 1414type=Sp804 1415amba_id=1316868 1416clock=1000 1417clock0=1000000 1418clock1=1000000 1419gic=system.realview.gic 1420int_num0=37 1421int_num1=37 1422pio_addr=268509184 1423pio_latency=100000 1424system=system 1425pio=system.iobus.master[3] 1426 1427[system.realview.uart] 1428type=Pl011 1429clock=1000 1430end_on_eot=false 1431gic=system.realview.gic 1432int_delay=100000 1433int_num=44 1434pio_addr=268472320 1435pio_latency=100000 1436platform=system.realview 1437system=system 1438terminal=system.terminal 1439pio=system.iobus.master[0] 1440 1441[system.realview.uart1_fake] 1442type=AmbaFake 1443amba_id=0 1444clock=1000 1445ignore_access=false 1446pio_addr=268476416 1447pio_latency=100000 1448system=system 1449pio=system.iobus.master[10] 1450 1451[system.realview.uart2_fake] 1452type=AmbaFake 1453amba_id=0 1454clock=1000 1455ignore_access=false 1456pio_addr=268480512 1457pio_latency=100000 1458system=system 1459pio=system.iobus.master[11] 1460 1461[system.realview.uart3_fake] 1462type=AmbaFake 1463amba_id=0 1464clock=1000 1465ignore_access=false 1466pio_addr=268484608 1467pio_latency=100000 1468system=system 1469pio=system.iobus.master[12] 1470 1471[system.realview.watchdog_fake] 1472type=AmbaFake 1473amba_id=0 1474clock=1000 1475ignore_access=false 1476pio_addr=268500992 1477pio_latency=100000 1478system=system 1479pio=system.iobus.master[15] 1480 1481[system.terminal] 1482type=Terminal 1483intr_control=system.intrctrl 1484number=0 1485output=true 1486port=3456 1487 1488[system.toL2Bus] 1489type=CoherentBus 1490block_size=64 1491clock=500 1492header_cycles=1 1493use_default_range=false 1494width=8 1495master=system.l2c.cpu_side 1496slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1497 1498[system.vncserver] 1499type=VncServer 1500frame_capture=false 1501number=0 1502port=5900 1503 1504