config.ini revision 9348:44d31345e360
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/projects/pd/randd/dist/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename= 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0 22kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing 26memories=system.physmem system.realview.nvmem 27multi_proc=true 28num_work_ids=16 29readfile=tests/halt.sh 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[0] 39 40[system.bridge] 41type=Bridge 42clock=1000 43delay=50000 44ranges=268435456:520093695 1073741824:1610612735 45req_size=16 46resp_size=16 47master=system.iobus.slave[0] 48slave=system.membus.master[0] 49 50[system.cf0] 51type=IdeDisk 52children=image 53delay=1000000 54driveID=master 55image=system.cf0.image 56 57[system.cf0.image] 58type=CowDiskImage 59children=child 60child=system.cf0.image.child 61image_file= 62read_only=false 63table_size=65536 64 65[system.cf0.image.child] 66type=RawDiskImage 67image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img 68read_only=true 69 70[system.cpu0] 71type=DerivO3CPU 72children=dcache dtb fuPool icache interrupts isa itb tracer 73BTBEntries=4096 74BTBTagSize=16 75LFSTSize=1024 76LQEntries=32 77LSQCheckLoads=true 78LSQDepCheckShift=4 79RASSize=16 80SQEntries=32 81SSITSize=1024 82activity=0 83backComSize=5 84cachePorts=200 85checker=Null 86choiceCtrBits=2 87choicePredictorSize=8192 88clock=500 89commitToDecodeDelay=1 90commitToFetchDelay=1 91commitToIEWDelay=1 92commitToRenameDelay=1 93commitWidth=8 94cpu_id=0 95decodeToFetchDelay=1 96decodeToRenameDelay=1 97decodeWidth=8 98defer_registration=false 99dispatchWidth=8 100do_checkpoint_insts=true 101do_quiesce=true 102do_statistics_insts=true 103dtb=system.cpu0.dtb 104fetchToDecodeDelay=1 105fetchTrapLatency=1 106fetchWidth=8 107forwardComSize=5 108fuPool=system.cpu0.fuPool 109function_trace=false 110function_trace_start=0 111globalCtrBits=2 112globalHistoryBits=13 113globalPredictorSize=8192 114iewToCommitDelay=1 115iewToDecodeDelay=1 116iewToFetchDelay=1 117iewToRenameDelay=1 118instShiftAmt=2 119interrupts=system.cpu0.interrupts 120isa=system.cpu0.isa 121issueToExecuteDelay=1 122issueWidth=8 123itb=system.cpu0.itb 124localCtrBits=2 125localHistoryBits=11 126localHistoryTableSize=2048 127localPredictorSize=2048 128max_insts_all_threads=0 129max_insts_any_thread=0 130max_loads_all_threads=0 131max_loads_any_thread=0 132needsTSO=false 133numIQEntries=64 134numPhysFloatRegs=256 135numPhysIntRegs=256 136numROBEntries=192 137numRobs=1 138numThreads=1 139predType=tournament 140profile=0 141progress_interval=0 142renameToDecodeDelay=1 143renameToFetchDelay=1 144renameToIEWDelay=2 145renameToROBDelay=1 146renameWidth=8 147smtCommitPolicy=RoundRobin 148smtFetchPolicy=SingleThread 149smtIQPolicy=Partitioned 150smtIQThreshold=100 151smtLSQPolicy=Partitioned 152smtLSQThreshold=100 153smtNumFetchingThreads=1 154smtROBPolicy=Partitioned 155smtROBThreshold=100 156squashWidth=8 157store_set_clear_period=250000 158system=system 159tracer=system.cpu0.tracer 160trapLatency=13 161wbDepth=1 162wbWidth=8 163workload= 164dcache_port=system.cpu0.dcache.cpu_side 165icache_port=system.cpu0.icache.cpu_side 166 167[system.cpu0.dcache] 168type=BaseCache 169addr_ranges=0:18446744073709551615 170assoc=4 171block_size=64 172clock=500 173forward_snoops=true 174hash_delay=1 175hit_latency=2 176is_top_level=true 177max_miss_count=0 178mshrs=4 179prefetch_on_access=false 180prefetcher=Null 181prioritizeRequests=false 182repl=Null 183response_latency=2 184size=32768 185subblock_size=0 186system=system 187tgts_per_mshr=20 188trace_addr=0 189two_queue=false 190write_buffers=8 191cpu_side=system.cpu0.dcache_port 192mem_side=system.toL2Bus.slave[1] 193 194[system.cpu0.dtb] 195type=ArmTLB 196children=walker 197size=64 198walker=system.cpu0.dtb.walker 199 200[system.cpu0.dtb.walker] 201type=ArmTableWalker 202clock=500 203num_squash_per_cycle=2 204sys=system 205port=system.toL2Bus.slave[3] 206 207[system.cpu0.fuPool] 208type=FUPool 209children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 210FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 211 212[system.cpu0.fuPool.FUList0] 213type=FUDesc 214children=opList 215count=6 216opList=system.cpu0.fuPool.FUList0.opList 217 218[system.cpu0.fuPool.FUList0.opList] 219type=OpDesc 220issueLat=1 221opClass=IntAlu 222opLat=1 223 224[system.cpu0.fuPool.FUList1] 225type=FUDesc 226children=opList0 opList1 227count=2 228opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 229 230[system.cpu0.fuPool.FUList1.opList0] 231type=OpDesc 232issueLat=1 233opClass=IntMult 234opLat=3 235 236[system.cpu0.fuPool.FUList1.opList1] 237type=OpDesc 238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu0.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4 246opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 247 248[system.cpu0.fuPool.FUList2.opList0] 249type=OpDesc 250issueLat=1 251opClass=FloatAdd 252opLat=2 253 254[system.cpu0.fuPool.FUList2.opList1] 255type=OpDesc 256issueLat=1 257opClass=FloatCmp 258opLat=2 259 260[system.cpu0.fuPool.FUList2.opList2] 261type=OpDesc 262issueLat=1 263opClass=FloatCvt 264opLat=2 265 266[system.cpu0.fuPool.FUList3] 267type=FUDesc 268children=opList0 opList1 opList2 269count=2 270opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 271 272[system.cpu0.fuPool.FUList3.opList0] 273type=OpDesc 274issueLat=1 275opClass=FloatMult 276opLat=4 277 278[system.cpu0.fuPool.FUList3.opList1] 279type=OpDesc 280issueLat=12 281opClass=FloatDiv 282opLat=12 283 284[system.cpu0.fuPool.FUList3.opList2] 285type=OpDesc 286issueLat=24 287opClass=FloatSqrt 288opLat=24 289 290[system.cpu0.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294opList=system.cpu0.fuPool.FUList4.opList 295 296[system.cpu0.fuPool.FUList4.opList] 297type=OpDesc 298issueLat=1 299opClass=MemRead 300opLat=1 301 302[system.cpu0.fuPool.FUList5] 303type=FUDesc 304children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 305count=4 306opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 307 308[system.cpu0.fuPool.FUList5.opList00] 309type=OpDesc 310issueLat=1 311opClass=SimdAdd 312opLat=1 313 314[system.cpu0.fuPool.FUList5.opList01] 315type=OpDesc 316issueLat=1 317opClass=SimdAddAcc 318opLat=1 319 320[system.cpu0.fuPool.FUList5.opList02] 321type=OpDesc 322issueLat=1 323opClass=SimdAlu 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList03] 327type=OpDesc 328issueLat=1 329opClass=SimdCmp 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList04] 333type=OpDesc 334issueLat=1 335opClass=SimdCvt 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList05] 339type=OpDesc 340issueLat=1 341opClass=SimdMisc 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList06] 345type=OpDesc 346issueLat=1 347opClass=SimdMult 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList07] 351type=OpDesc 352issueLat=1 353opClass=SimdMultAcc 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList08] 357type=OpDesc 358issueLat=1 359opClass=SimdShift 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList09] 363type=OpDesc 364issueLat=1 365opClass=SimdShiftAcc 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList10] 369type=OpDesc 370issueLat=1 371opClass=SimdSqrt 372opLat=1 373 374[system.cpu0.fuPool.FUList5.opList11] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatAdd 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList12] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatAlu 384opLat=1 385 386[system.cpu0.fuPool.FUList5.opList13] 387type=OpDesc 388issueLat=1 389opClass=SimdFloatCmp 390opLat=1 391 392[system.cpu0.fuPool.FUList5.opList14] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatCvt 396opLat=1 397 398[system.cpu0.fuPool.FUList5.opList15] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatDiv 402opLat=1 403 404[system.cpu0.fuPool.FUList5.opList16] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatMisc 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList17] 411type=OpDesc 412issueLat=1 413opClass=SimdFloatMult 414opLat=1 415 416[system.cpu0.fuPool.FUList5.opList18] 417type=OpDesc 418issueLat=1 419opClass=SimdFloatMultAcc 420opLat=1 421 422[system.cpu0.fuPool.FUList5.opList19] 423type=OpDesc 424issueLat=1 425opClass=SimdFloatSqrt 426opLat=1 427 428[system.cpu0.fuPool.FUList6] 429type=FUDesc 430children=opList 431count=0 432opList=system.cpu0.fuPool.FUList6.opList 433 434[system.cpu0.fuPool.FUList6.opList] 435type=OpDesc 436issueLat=1 437opClass=MemWrite 438opLat=1 439 440[system.cpu0.fuPool.FUList7] 441type=FUDesc 442children=opList0 opList1 443count=4 444opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 445 446[system.cpu0.fuPool.FUList7.opList0] 447type=OpDesc 448issueLat=1 449opClass=MemRead 450opLat=1 451 452[system.cpu0.fuPool.FUList7.opList1] 453type=OpDesc 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu0.fuPool.FUList8] 459type=FUDesc 460children=opList 461count=1 462opList=system.cpu0.fuPool.FUList8.opList 463 464[system.cpu0.fuPool.FUList8.opList] 465type=OpDesc 466issueLat=3 467opClass=IprAccess 468opLat=3 469 470[system.cpu0.icache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=1 474block_size=64 475clock=500 476forward_snoops=true 477hash_delay=1 478hit_latency=2 479is_top_level=true 480max_miss_count=0 481mshrs=4 482prefetch_on_access=false 483prefetcher=Null 484prioritizeRequests=false 485repl=Null 486response_latency=2 487size=32768 488subblock_size=0 489system=system 490tgts_per_mshr=20 491trace_addr=0 492two_queue=false 493write_buffers=8 494cpu_side=system.cpu0.icache_port 495mem_side=system.toL2Bus.slave[0] 496 497[system.cpu0.interrupts] 498type=ArmInterrupts 499 500[system.cpu0.isa] 501type=ArmISA 502fpsid=1090793632 503id_isar0=34607377 504id_isar1=34677009 505id_isar2=555950401 506id_isar3=17899825 507id_isar4=268501314 508id_isar5=0 509id_mmfr0=3 510id_mmfr1=0 511id_mmfr2=19070976 512id_mmfr3=4027589137 513id_pfr0=49 514id_pfr1=1 515midr=890224640 516 517[system.cpu0.itb] 518type=ArmTLB 519children=walker 520size=64 521walker=system.cpu0.itb.walker 522 523[system.cpu0.itb.walker] 524type=ArmTableWalker 525clock=500 526num_squash_per_cycle=2 527sys=system 528port=system.toL2Bus.slave[2] 529 530[system.cpu0.tracer] 531type=ExeTracer 532 533[system.cpu1] 534type=DerivO3CPU 535children=dcache dtb fuPool icache interrupts isa itb tracer 536BTBEntries=4096 537BTBTagSize=16 538LFSTSize=1024 539LQEntries=32 540LSQCheckLoads=true 541LSQDepCheckShift=4 542RASSize=16 543SQEntries=32 544SSITSize=1024 545activity=0 546backComSize=5 547cachePorts=200 548checker=Null 549choiceCtrBits=2 550choicePredictorSize=8192 551clock=500 552commitToDecodeDelay=1 553commitToFetchDelay=1 554commitToIEWDelay=1 555commitToRenameDelay=1 556commitWidth=8 557cpu_id=1 558decodeToFetchDelay=1 559decodeToRenameDelay=1 560decodeWidth=8 561defer_registration=false 562dispatchWidth=8 563do_checkpoint_insts=true 564do_quiesce=true 565do_statistics_insts=true 566dtb=system.cpu1.dtb 567fetchToDecodeDelay=1 568fetchTrapLatency=1 569fetchWidth=8 570forwardComSize=5 571fuPool=system.cpu1.fuPool 572function_trace=false 573function_trace_start=0 574globalCtrBits=2 575globalHistoryBits=13 576globalPredictorSize=8192 577iewToCommitDelay=1 578iewToDecodeDelay=1 579iewToFetchDelay=1 580iewToRenameDelay=1 581instShiftAmt=2 582interrupts=system.cpu1.interrupts 583isa=system.cpu1.isa 584issueToExecuteDelay=1 585issueWidth=8 586itb=system.cpu1.itb 587localCtrBits=2 588localHistoryBits=11 589localHistoryTableSize=2048 590localPredictorSize=2048 591max_insts_all_threads=0 592max_insts_any_thread=0 593max_loads_all_threads=0 594max_loads_any_thread=0 595needsTSO=false 596numIQEntries=64 597numPhysFloatRegs=256 598numPhysIntRegs=256 599numROBEntries=192 600numRobs=1 601numThreads=1 602predType=tournament 603profile=0 604progress_interval=0 605renameToDecodeDelay=1 606renameToFetchDelay=1 607renameToIEWDelay=2 608renameToROBDelay=1 609renameWidth=8 610smtCommitPolicy=RoundRobin 611smtFetchPolicy=SingleThread 612smtIQPolicy=Partitioned 613smtIQThreshold=100 614smtLSQPolicy=Partitioned 615smtLSQThreshold=100 616smtNumFetchingThreads=1 617smtROBPolicy=Partitioned 618smtROBThreshold=100 619squashWidth=8 620store_set_clear_period=250000 621system=system 622tracer=system.cpu1.tracer 623trapLatency=13 624wbDepth=1 625wbWidth=8 626workload= 627dcache_port=system.cpu1.dcache.cpu_side 628icache_port=system.cpu1.icache.cpu_side 629 630[system.cpu1.dcache] 631type=BaseCache 632addr_ranges=0:18446744073709551615 633assoc=4 634block_size=64 635clock=500 636forward_snoops=true 637hash_delay=1 638hit_latency=2 639is_top_level=true 640max_miss_count=0 641mshrs=4 642prefetch_on_access=false 643prefetcher=Null 644prioritizeRequests=false 645repl=Null 646response_latency=2 647size=32768 648subblock_size=0 649system=system 650tgts_per_mshr=20 651trace_addr=0 652two_queue=false 653write_buffers=8 654cpu_side=system.cpu1.dcache_port 655mem_side=system.toL2Bus.slave[5] 656 657[system.cpu1.dtb] 658type=ArmTLB 659children=walker 660size=64 661walker=system.cpu1.dtb.walker 662 663[system.cpu1.dtb.walker] 664type=ArmTableWalker 665clock=500 666num_squash_per_cycle=2 667sys=system 668port=system.toL2Bus.slave[7] 669 670[system.cpu1.fuPool] 671type=FUPool 672children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 673FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 674 675[system.cpu1.fuPool.FUList0] 676type=FUDesc 677children=opList 678count=6 679opList=system.cpu1.fuPool.FUList0.opList 680 681[system.cpu1.fuPool.FUList0.opList] 682type=OpDesc 683issueLat=1 684opClass=IntAlu 685opLat=1 686 687[system.cpu1.fuPool.FUList1] 688type=FUDesc 689children=opList0 opList1 690count=2 691opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 692 693[system.cpu1.fuPool.FUList1.opList0] 694type=OpDesc 695issueLat=1 696opClass=IntMult 697opLat=3 698 699[system.cpu1.fuPool.FUList1.opList1] 700type=OpDesc 701issueLat=19 702opClass=IntDiv 703opLat=20 704 705[system.cpu1.fuPool.FUList2] 706type=FUDesc 707children=opList0 opList1 opList2 708count=4 709opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 710 711[system.cpu1.fuPool.FUList2.opList0] 712type=OpDesc 713issueLat=1 714opClass=FloatAdd 715opLat=2 716 717[system.cpu1.fuPool.FUList2.opList1] 718type=OpDesc 719issueLat=1 720opClass=FloatCmp 721opLat=2 722 723[system.cpu1.fuPool.FUList2.opList2] 724type=OpDesc 725issueLat=1 726opClass=FloatCvt 727opLat=2 728 729[system.cpu1.fuPool.FUList3] 730type=FUDesc 731children=opList0 opList1 opList2 732count=2 733opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 734 735[system.cpu1.fuPool.FUList3.opList0] 736type=OpDesc 737issueLat=1 738opClass=FloatMult 739opLat=4 740 741[system.cpu1.fuPool.FUList3.opList1] 742type=OpDesc 743issueLat=12 744opClass=FloatDiv 745opLat=12 746 747[system.cpu1.fuPool.FUList3.opList2] 748type=OpDesc 749issueLat=24 750opClass=FloatSqrt 751opLat=24 752 753[system.cpu1.fuPool.FUList4] 754type=FUDesc 755children=opList 756count=0 757opList=system.cpu1.fuPool.FUList4.opList 758 759[system.cpu1.fuPool.FUList4.opList] 760type=OpDesc 761issueLat=1 762opClass=MemRead 763opLat=1 764 765[system.cpu1.fuPool.FUList5] 766type=FUDesc 767children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 768count=4 769opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 770 771[system.cpu1.fuPool.FUList5.opList00] 772type=OpDesc 773issueLat=1 774opClass=SimdAdd 775opLat=1 776 777[system.cpu1.fuPool.FUList5.opList01] 778type=OpDesc 779issueLat=1 780opClass=SimdAddAcc 781opLat=1 782 783[system.cpu1.fuPool.FUList5.opList02] 784type=OpDesc 785issueLat=1 786opClass=SimdAlu 787opLat=1 788 789[system.cpu1.fuPool.FUList5.opList03] 790type=OpDesc 791issueLat=1 792opClass=SimdCmp 793opLat=1 794 795[system.cpu1.fuPool.FUList5.opList04] 796type=OpDesc 797issueLat=1 798opClass=SimdCvt 799opLat=1 800 801[system.cpu1.fuPool.FUList5.opList05] 802type=OpDesc 803issueLat=1 804opClass=SimdMisc 805opLat=1 806 807[system.cpu1.fuPool.FUList5.opList06] 808type=OpDesc 809issueLat=1 810opClass=SimdMult 811opLat=1 812 813[system.cpu1.fuPool.FUList5.opList07] 814type=OpDesc 815issueLat=1 816opClass=SimdMultAcc 817opLat=1 818 819[system.cpu1.fuPool.FUList5.opList08] 820type=OpDesc 821issueLat=1 822opClass=SimdShift 823opLat=1 824 825[system.cpu1.fuPool.FUList5.opList09] 826type=OpDesc 827issueLat=1 828opClass=SimdShiftAcc 829opLat=1 830 831[system.cpu1.fuPool.FUList5.opList10] 832type=OpDesc 833issueLat=1 834opClass=SimdSqrt 835opLat=1 836 837[system.cpu1.fuPool.FUList5.opList11] 838type=OpDesc 839issueLat=1 840opClass=SimdFloatAdd 841opLat=1 842 843[system.cpu1.fuPool.FUList5.opList12] 844type=OpDesc 845issueLat=1 846opClass=SimdFloatAlu 847opLat=1 848 849[system.cpu1.fuPool.FUList5.opList13] 850type=OpDesc 851issueLat=1 852opClass=SimdFloatCmp 853opLat=1 854 855[system.cpu1.fuPool.FUList5.opList14] 856type=OpDesc 857issueLat=1 858opClass=SimdFloatCvt 859opLat=1 860 861[system.cpu1.fuPool.FUList5.opList15] 862type=OpDesc 863issueLat=1 864opClass=SimdFloatDiv 865opLat=1 866 867[system.cpu1.fuPool.FUList5.opList16] 868type=OpDesc 869issueLat=1 870opClass=SimdFloatMisc 871opLat=1 872 873[system.cpu1.fuPool.FUList5.opList17] 874type=OpDesc 875issueLat=1 876opClass=SimdFloatMult 877opLat=1 878 879[system.cpu1.fuPool.FUList5.opList18] 880type=OpDesc 881issueLat=1 882opClass=SimdFloatMultAcc 883opLat=1 884 885[system.cpu1.fuPool.FUList5.opList19] 886type=OpDesc 887issueLat=1 888opClass=SimdFloatSqrt 889opLat=1 890 891[system.cpu1.fuPool.FUList6] 892type=FUDesc 893children=opList 894count=0 895opList=system.cpu1.fuPool.FUList6.opList 896 897[system.cpu1.fuPool.FUList6.opList] 898type=OpDesc 899issueLat=1 900opClass=MemWrite 901opLat=1 902 903[system.cpu1.fuPool.FUList7] 904type=FUDesc 905children=opList0 opList1 906count=4 907opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 908 909[system.cpu1.fuPool.FUList7.opList0] 910type=OpDesc 911issueLat=1 912opClass=MemRead 913opLat=1 914 915[system.cpu1.fuPool.FUList7.opList1] 916type=OpDesc 917issueLat=1 918opClass=MemWrite 919opLat=1 920 921[system.cpu1.fuPool.FUList8] 922type=FUDesc 923children=opList 924count=1 925opList=system.cpu1.fuPool.FUList8.opList 926 927[system.cpu1.fuPool.FUList8.opList] 928type=OpDesc 929issueLat=3 930opClass=IprAccess 931opLat=3 932 933[system.cpu1.icache] 934type=BaseCache 935addr_ranges=0:18446744073709551615 936assoc=1 937block_size=64 938clock=500 939forward_snoops=true 940hash_delay=1 941hit_latency=2 942is_top_level=true 943max_miss_count=0 944mshrs=4 945prefetch_on_access=false 946prefetcher=Null 947prioritizeRequests=false 948repl=Null 949response_latency=2 950size=32768 951subblock_size=0 952system=system 953tgts_per_mshr=20 954trace_addr=0 955two_queue=false 956write_buffers=8 957cpu_side=system.cpu1.icache_port 958mem_side=system.toL2Bus.slave[4] 959 960[system.cpu1.interrupts] 961type=ArmInterrupts 962 963[system.cpu1.isa] 964type=ArmISA 965fpsid=1090793632 966id_isar0=34607377 967id_isar1=34677009 968id_isar2=555950401 969id_isar3=17899825 970id_isar4=268501314 971id_isar5=0 972id_mmfr0=3 973id_mmfr1=0 974id_mmfr2=19070976 975id_mmfr3=4027589137 976id_pfr0=49 977id_pfr1=1 978midr=890224640 979 980[system.cpu1.itb] 981type=ArmTLB 982children=walker 983size=64 984walker=system.cpu1.itb.walker 985 986[system.cpu1.itb.walker] 987type=ArmTableWalker 988clock=500 989num_squash_per_cycle=2 990sys=system 991port=system.toL2Bus.slave[6] 992 993[system.cpu1.tracer] 994type=ExeTracer 995 996[system.intrctrl] 997type=IntrControl 998sys=system 999 1000[system.iobus] 1001type=NoncoherentBus 1002block_size=64 1003clock=1000 1004header_cycles=1 1005use_default_range=false 1006width=8 1007master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1008slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1009 1010[system.iocache] 1011type=BaseCache 1012addr_ranges=0:268435455 1013assoc=8 1014block_size=64 1015clock=1000 1016forward_snoops=false 1017hash_delay=1 1018hit_latency=50 1019is_top_level=true 1020max_miss_count=0 1021mshrs=20 1022prefetch_on_access=false 1023prefetcher=Null 1024prioritizeRequests=false 1025repl=Null 1026response_latency=50 1027size=1024 1028subblock_size=0 1029system=system 1030tgts_per_mshr=12 1031trace_addr=0 1032two_queue=false 1033write_buffers=8 1034cpu_side=system.iobus.master[25] 1035mem_side=system.membus.slave[1] 1036 1037[system.l2c] 1038type=BaseCache 1039addr_ranges=0:18446744073709551615 1040assoc=8 1041block_size=64 1042clock=500 1043forward_snoops=true 1044hash_delay=1 1045hit_latency=20 1046is_top_level=false 1047max_miss_count=0 1048mshrs=20 1049prefetch_on_access=false 1050prefetcher=Null 1051prioritizeRequests=false 1052repl=Null 1053response_latency=20 1054size=4194304 1055subblock_size=0 1056system=system 1057tgts_per_mshr=12 1058trace_addr=0 1059two_queue=false 1060write_buffers=8 1061cpu_side=system.toL2Bus.master[0] 1062mem_side=system.membus.slave[2] 1063 1064[system.membus] 1065type=CoherentBus 1066children=badaddr_responder 1067block_size=64 1068clock=1000 1069header_cycles=1 1070use_default_range=false 1071width=8 1072default=system.membus.badaddr_responder.pio 1073master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 1074slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1075 1076[system.membus.badaddr_responder] 1077type=IsaFake 1078clock=1000 1079fake_mem=false 1080pio_addr=0 1081pio_latency=100000 1082pio_size=8 1083ret_bad_addr=true 1084ret_data16=65535 1085ret_data32=4294967295 1086ret_data64=18446744073709551615 1087ret_data8=255 1088system=system 1089update_data=false 1090warn_access=warn 1091pio=system.membus.default 1092 1093[system.physmem] 1094type=SimpleDRAM 1095addr_mapping=openmap 1096banks_per_rank=8 1097clock=1000 1098conf_table_reported=true 1099in_addr_map=true 1100lines_per_rowbuffer=64 1101mem_sched_policy=fcfs 1102null=false 1103page_policy=open 1104range=0:134217727 1105ranks_per_channel=2 1106read_buffer_size=32 1107tBURST=4000 1108tCL=14000 1109tRCD=14000 1110tREFI=7800000 1111tRFC=300000 1112tRP=14000 1113tWTR=1000 1114write_buffer_size=32 1115write_thresh_perc=70 1116zero=false 1117port=system.membus.master[2] 1118 1119[system.realview] 1120type=RealView 1121children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1122intrctrl=system.intrctrl 1123max_mem_size=268435456 1124mem_start_addr=0 1125pci_cfg_base=0 1126system=system 1127 1128[system.realview.a9scu] 1129type=A9SCU 1130clock=1000 1131pio_addr=520093696 1132pio_latency=100000 1133system=system 1134pio=system.membus.master[5] 1135 1136[system.realview.aaci_fake] 1137type=AmbaFake 1138amba_id=0 1139clock=1000 1140ignore_access=false 1141pio_addr=268451840 1142pio_latency=100000 1143system=system 1144pio=system.iobus.master[21] 1145 1146[system.realview.cf_ctrl] 1147type=IdeController 1148BAR0=402653184 1149BAR0LegacyIO=true 1150BAR0Size=16 1151BAR1=402653440 1152BAR1LegacyIO=true 1153BAR1Size=1 1154BAR2=1 1155BAR2LegacyIO=false 1156BAR2Size=8 1157BAR3=1 1158BAR3LegacyIO=false 1159BAR3Size=4 1160BAR4=1 1161BAR4LegacyIO=false 1162BAR4Size=16 1163BAR5=1 1164BAR5LegacyIO=false 1165BAR5Size=0 1166BIST=0 1167CacheLineSize=0 1168CardbusCIS=0 1169ClassCode=1 1170Command=1 1171DeviceID=28945 1172ExpansionROM=0 1173HeaderType=0 1174InterruptLine=31 1175InterruptPin=1 1176LatencyTimer=0 1177MaximumLatency=0 1178MinimumGrant=0 1179ProgIF=133 1180Revision=0 1181Status=640 1182SubClassCode=1 1183SubsystemID=0 1184SubsystemVendorID=0 1185VendorID=32902 1186clock=1000 1187config_latency=20000 1188ctrl_offset=2 1189disks=system.cf0 1190io_shift=1 1191pci_bus=2 1192pci_dev=7 1193pci_func=0 1194pio_latency=30000 1195platform=system.realview 1196system=system 1197config=system.iobus.master[8] 1198dma=system.iobus.slave[2] 1199pio=system.iobus.master[7] 1200 1201[system.realview.clcd] 1202type=Pl111 1203amba_id=1315089 1204clock=41667 1205gic=system.realview.gic 1206int_num=55 1207pio_addr=268566528 1208pio_latency=10000 1209system=system 1210vnc=system.vncserver 1211dma=system.iobus.slave[1] 1212pio=system.iobus.master[4] 1213 1214[system.realview.dmac_fake] 1215type=AmbaFake 1216amba_id=0 1217clock=1000 1218ignore_access=false 1219pio_addr=268632064 1220pio_latency=100000 1221system=system 1222pio=system.iobus.master[9] 1223 1224[system.realview.flash_fake] 1225type=IsaFake 1226clock=1000 1227fake_mem=true 1228pio_addr=1073741824 1229pio_latency=100000 1230pio_size=536870912 1231ret_bad_addr=false 1232ret_data16=65535 1233ret_data32=4294967295 1234ret_data64=18446744073709551615 1235ret_data8=255 1236system=system 1237update_data=false 1238warn_access= 1239pio=system.iobus.master[24] 1240 1241[system.realview.gic] 1242type=Gic 1243clock=1000 1244cpu_addr=520093952 1245cpu_pio_delay=10000 1246dist_addr=520097792 1247dist_pio_delay=10000 1248int_latency=10000 1249it_lines=128 1250platform=system.realview 1251system=system 1252pio=system.membus.master[3] 1253 1254[system.realview.gpio0_fake] 1255type=AmbaFake 1256amba_id=0 1257clock=1000 1258ignore_access=false 1259pio_addr=268513280 1260pio_latency=100000 1261system=system 1262pio=system.iobus.master[16] 1263 1264[system.realview.gpio1_fake] 1265type=AmbaFake 1266amba_id=0 1267clock=1000 1268ignore_access=false 1269pio_addr=268517376 1270pio_latency=100000 1271system=system 1272pio=system.iobus.master[17] 1273 1274[system.realview.gpio2_fake] 1275type=AmbaFake 1276amba_id=0 1277clock=1000 1278ignore_access=false 1279pio_addr=268521472 1280pio_latency=100000 1281system=system 1282pio=system.iobus.master[18] 1283 1284[system.realview.kmi0] 1285type=Pl050 1286amba_id=1314896 1287clock=1000 1288gic=system.realview.gic 1289int_delay=1000000 1290int_num=52 1291is_mouse=false 1292pio_addr=268460032 1293pio_latency=100000 1294system=system 1295vnc=system.vncserver 1296pio=system.iobus.master[5] 1297 1298[system.realview.kmi1] 1299type=Pl050 1300amba_id=1314896 1301clock=1000 1302gic=system.realview.gic 1303int_delay=1000000 1304int_num=53 1305is_mouse=true 1306pio_addr=268464128 1307pio_latency=100000 1308system=system 1309vnc=system.vncserver 1310pio=system.iobus.master[6] 1311 1312[system.realview.l2x0_fake] 1313type=IsaFake 1314clock=1000 1315fake_mem=false 1316pio_addr=520101888 1317pio_latency=100000 1318pio_size=4095 1319ret_bad_addr=false 1320ret_data16=65535 1321ret_data32=4294967295 1322ret_data64=18446744073709551615 1323ret_data8=255 1324system=system 1325update_data=false 1326warn_access= 1327pio=system.membus.master[4] 1328 1329[system.realview.local_cpu_timer] 1330type=CpuLocalTimer 1331clock=1000 1332gic=system.realview.gic 1333int_num_timer=29 1334int_num_watchdog=30 1335pio_addr=520095232 1336pio_latency=100000 1337system=system 1338pio=system.membus.master[6] 1339 1340[system.realview.mmc_fake] 1341type=AmbaFake 1342amba_id=0 1343clock=1000 1344ignore_access=false 1345pio_addr=268455936 1346pio_latency=100000 1347system=system 1348pio=system.iobus.master[22] 1349 1350[system.realview.nvmem] 1351type=SimpleMemory 1352bandwidth=73.000000 1353clock=1000 1354conf_table_reported=false 1355in_addr_map=true 1356latency=30000 1357latency_var=0 1358null=false 1359range=2147483648:2214592511 1360zero=true 1361port=system.membus.master[1] 1362 1363[system.realview.realview_io] 1364type=RealViewCtrl 1365clock=1000 1366idreg=0 1367pio_addr=268435456 1368pio_latency=100000 1369proc_id0=201326592 1370proc_id1=201327138 1371system=system 1372pio=system.iobus.master[1] 1373 1374[system.realview.rtc] 1375type=PL031 1376amba_id=3412017 1377clock=1000 1378gic=system.realview.gic 1379int_delay=100000 1380int_num=42 1381pio_addr=268529664 1382pio_latency=100000 1383system=system 1384time=Thu Jan 1 00:00:00 2009 1385pio=system.iobus.master[23] 1386 1387[system.realview.sci_fake] 1388type=AmbaFake 1389amba_id=0 1390clock=1000 1391ignore_access=false 1392pio_addr=268492800 1393pio_latency=100000 1394system=system 1395pio=system.iobus.master[20] 1396 1397[system.realview.smc_fake] 1398type=AmbaFake 1399amba_id=0 1400clock=1000 1401ignore_access=false 1402pio_addr=269357056 1403pio_latency=100000 1404system=system 1405pio=system.iobus.master[13] 1406 1407[system.realview.sp810_fake] 1408type=AmbaFake 1409amba_id=0 1410clock=1000 1411ignore_access=true 1412pio_addr=268439552 1413pio_latency=100000 1414system=system 1415pio=system.iobus.master[14] 1416 1417[system.realview.ssp_fake] 1418type=AmbaFake 1419amba_id=0 1420clock=1000 1421ignore_access=false 1422pio_addr=268488704 1423pio_latency=100000 1424system=system 1425pio=system.iobus.master[19] 1426 1427[system.realview.timer0] 1428type=Sp804 1429amba_id=1316868 1430clock=1000 1431clock0=1000000 1432clock1=1000000 1433gic=system.realview.gic 1434int_num0=36 1435int_num1=36 1436pio_addr=268505088 1437pio_latency=100000 1438system=system 1439pio=system.iobus.master[2] 1440 1441[system.realview.timer1] 1442type=Sp804 1443amba_id=1316868 1444clock=1000 1445clock0=1000000 1446clock1=1000000 1447gic=system.realview.gic 1448int_num0=37 1449int_num1=37 1450pio_addr=268509184 1451pio_latency=100000 1452system=system 1453pio=system.iobus.master[3] 1454 1455[system.realview.uart] 1456type=Pl011 1457clock=1000 1458end_on_eot=false 1459gic=system.realview.gic 1460int_delay=100000 1461int_num=44 1462pio_addr=268472320 1463pio_latency=100000 1464platform=system.realview 1465system=system 1466terminal=system.terminal 1467pio=system.iobus.master[0] 1468 1469[system.realview.uart1_fake] 1470type=AmbaFake 1471amba_id=0 1472clock=1000 1473ignore_access=false 1474pio_addr=268476416 1475pio_latency=100000 1476system=system 1477pio=system.iobus.master[10] 1478 1479[system.realview.uart2_fake] 1480type=AmbaFake 1481amba_id=0 1482clock=1000 1483ignore_access=false 1484pio_addr=268480512 1485pio_latency=100000 1486system=system 1487pio=system.iobus.master[11] 1488 1489[system.realview.uart3_fake] 1490type=AmbaFake 1491amba_id=0 1492clock=1000 1493ignore_access=false 1494pio_addr=268484608 1495pio_latency=100000 1496system=system 1497pio=system.iobus.master[12] 1498 1499[system.realview.watchdog_fake] 1500type=AmbaFake 1501amba_id=0 1502clock=1000 1503ignore_access=false 1504pio_addr=268500992 1505pio_latency=100000 1506system=system 1507pio=system.iobus.master[15] 1508 1509[system.terminal] 1510type=Terminal 1511intr_control=system.intrctrl 1512number=0 1513output=true 1514port=3456 1515 1516[system.toL2Bus] 1517type=CoherentBus 1518block_size=64 1519clock=500 1520header_cycles=1 1521use_default_range=false 1522width=8 1523master=system.l2c.cpu_side 1524slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1525 1526[system.vncserver] 1527type=VncServer 1528frame_capture=false 1529number=0 1530port=5900 1531 1532