config.ini revision 9134:275232ad377d
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15early_kernel_symbols=false 16flags_addr=268435504 17gic_cpu_addr=520093952 18init_param=0 19kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 20load_addr_mask=268435455 21machine_type=RealView_PBX 22mem_mode=timing 23memories=system.physmem system.realview.nvmem 24midr_regval=890224640 25multi_proc=true 26num_work_ids=16 27readfile=tests/halt.sh 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.bridge] 39type=Bridge 40delay=50000 41nack_delay=4000 42ranges=268435456:520093695 1073741824:1610612735 43req_size=16 44resp_size=16 45write_ack=false 46master=system.iobus.slave[0] 47slave=system.membus.master[0] 48 49[system.cf0] 50type=IdeDisk 51children=image 52delay=1000000 53driveID=master 54image=system.cf0.image 55 56[system.cf0.image] 57type=CowDiskImage 58children=child 59child=system.cf0.image.child 60image_file= 61read_only=false 62table_size=65536 63 64[system.cf0.image.child] 65type=RawDiskImage 66image_file=/dist/m5/system/disks/linux-arm-ael.img 67read_only=true 68 69[system.cpu0] 70type=DerivO3CPU 71children=dcache dtb fuPool icache interrupts itb tracer 72BTBEntries=4096 73BTBTagSize=16 74LFSTSize=1024 75LQEntries=32 76LSQCheckLoads=true 77LSQDepCheckShift=4 78RASSize=16 79SQEntries=32 80SSITSize=1024 81activity=0 82backComSize=5 83cachePorts=200 84checker=Null 85choiceCtrBits=2 86choicePredictorSize=8192 87clock=500 88commitToDecodeDelay=1 89commitToFetchDelay=1 90commitToIEWDelay=1 91commitToRenameDelay=1 92commitWidth=8 93cpu_id=0 94decodeToFetchDelay=1 95decodeToRenameDelay=1 96decodeWidth=8 97defer_registration=false 98dispatchWidth=8 99do_checkpoint_insts=true 100do_quiesce=true 101do_statistics_insts=true 102dtb=system.cpu0.dtb 103fetchToDecodeDelay=1 104fetchTrapLatency=1 105fetchWidth=8 106forwardComSize=5 107fuPool=system.cpu0.fuPool 108function_trace=false 109function_trace_start=0 110globalCtrBits=2 111globalHistoryBits=13 112globalPredictorSize=8192 113iewToCommitDelay=1 114iewToDecodeDelay=1 115iewToFetchDelay=1 116iewToRenameDelay=1 117instShiftAmt=2 118interrupts=system.cpu0.interrupts 119issueToExecuteDelay=1 120issueWidth=8 121itb=system.cpu0.itb 122localCtrBits=2 123localHistoryBits=11 124localHistoryTableSize=2048 125localPredictorSize=2048 126max_insts_all_threads=0 127max_insts_any_thread=0 128max_loads_all_threads=0 129max_loads_any_thread=0 130needsTSO=false 131numIQEntries=64 132numPhysFloatRegs=256 133numPhysIntRegs=256 134numROBEntries=192 135numRobs=1 136numThreads=1 137phase=0 138predType=tournament 139profile=0 140progress_interval=0 141renameToDecodeDelay=1 142renameToFetchDelay=1 143renameToIEWDelay=2 144renameToROBDelay=1 145renameWidth=8 146smtCommitPolicy=RoundRobin 147smtFetchPolicy=SingleThread 148smtIQPolicy=Partitioned 149smtIQThreshold=100 150smtLSQPolicy=Partitioned 151smtLSQThreshold=100 152smtNumFetchingThreads=1 153smtROBPolicy=Partitioned 154smtROBThreshold=100 155squashWidth=8 156store_set_clear_period=250000 157system=system 158tracer=system.cpu0.tracer 159trapLatency=13 160wbDepth=1 161wbWidth=8 162workload= 163dcache_port=system.cpu0.dcache.cpu_side 164icache_port=system.cpu0.icache.cpu_side 165 166[system.cpu0.dcache] 167type=BaseCache 168addr_ranges=0:18446744073709551615 169assoc=4 170block_size=64 171forward_snoops=true 172hash_delay=1 173is_top_level=true 174latency=1000 175max_miss_count=0 176mshrs=4 177prefetch_on_access=false 178prefetcher=Null 179prioritizeRequests=false 180repl=Null 181size=32768 182subblock_size=0 183system=system 184tgts_per_mshr=20 185trace_addr=0 186two_queue=false 187write_buffers=8 188cpu_side=system.cpu0.dcache_port 189mem_side=system.toL2Bus.slave[1] 190 191[system.cpu0.dtb] 192type=ArmTLB 193children=walker 194size=64 195walker=system.cpu0.dtb.walker 196 197[system.cpu0.dtb.walker] 198type=ArmTableWalker 199max_backoff=100000 200min_backoff=0 201sys=system 202port=system.toL2Bus.slave[3] 203 204[system.cpu0.fuPool] 205type=FUPool 206children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 207FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 208 209[system.cpu0.fuPool.FUList0] 210type=FUDesc 211children=opList 212count=6 213opList=system.cpu0.fuPool.FUList0.opList 214 215[system.cpu0.fuPool.FUList0.opList] 216type=OpDesc 217issueLat=1 218opClass=IntAlu 219opLat=1 220 221[system.cpu0.fuPool.FUList1] 222type=FUDesc 223children=opList0 opList1 224count=2 225opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 226 227[system.cpu0.fuPool.FUList1.opList0] 228type=OpDesc 229issueLat=1 230opClass=IntMult 231opLat=3 232 233[system.cpu0.fuPool.FUList1.opList1] 234type=OpDesc 235issueLat=19 236opClass=IntDiv 237opLat=20 238 239[system.cpu0.fuPool.FUList2] 240type=FUDesc 241children=opList0 opList1 opList2 242count=4 243opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 244 245[system.cpu0.fuPool.FUList2.opList0] 246type=OpDesc 247issueLat=1 248opClass=FloatAdd 249opLat=2 250 251[system.cpu0.fuPool.FUList2.opList1] 252type=OpDesc 253issueLat=1 254opClass=FloatCmp 255opLat=2 256 257[system.cpu0.fuPool.FUList2.opList2] 258type=OpDesc 259issueLat=1 260opClass=FloatCvt 261opLat=2 262 263[system.cpu0.fuPool.FUList3] 264type=FUDesc 265children=opList0 opList1 opList2 266count=2 267opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 268 269[system.cpu0.fuPool.FUList3.opList0] 270type=OpDesc 271issueLat=1 272opClass=FloatMult 273opLat=4 274 275[system.cpu0.fuPool.FUList3.opList1] 276type=OpDesc 277issueLat=12 278opClass=FloatDiv 279opLat=12 280 281[system.cpu0.fuPool.FUList3.opList2] 282type=OpDesc 283issueLat=24 284opClass=FloatSqrt 285opLat=24 286 287[system.cpu0.fuPool.FUList4] 288type=FUDesc 289children=opList 290count=0 291opList=system.cpu0.fuPool.FUList4.opList 292 293[system.cpu0.fuPool.FUList4.opList] 294type=OpDesc 295issueLat=1 296opClass=MemRead 297opLat=1 298 299[system.cpu0.fuPool.FUList5] 300type=FUDesc 301children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 302count=4 303opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 304 305[system.cpu0.fuPool.FUList5.opList00] 306type=OpDesc 307issueLat=1 308opClass=SimdAdd 309opLat=1 310 311[system.cpu0.fuPool.FUList5.opList01] 312type=OpDesc 313issueLat=1 314opClass=SimdAddAcc 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList02] 318type=OpDesc 319issueLat=1 320opClass=SimdAlu 321opLat=1 322 323[system.cpu0.fuPool.FUList5.opList03] 324type=OpDesc 325issueLat=1 326opClass=SimdCmp 327opLat=1 328 329[system.cpu0.fuPool.FUList5.opList04] 330type=OpDesc 331issueLat=1 332opClass=SimdCvt 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList05] 336type=OpDesc 337issueLat=1 338opClass=SimdMisc 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList06] 342type=OpDesc 343issueLat=1 344opClass=SimdMult 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList07] 348type=OpDesc 349issueLat=1 350opClass=SimdMultAcc 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList08] 354type=OpDesc 355issueLat=1 356opClass=SimdShift 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList09] 360type=OpDesc 361issueLat=1 362opClass=SimdShiftAcc 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList10] 366type=OpDesc 367issueLat=1 368opClass=SimdSqrt 369opLat=1 370 371[system.cpu0.fuPool.FUList5.opList11] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatAdd 375opLat=1 376 377[system.cpu0.fuPool.FUList5.opList12] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatAlu 381opLat=1 382 383[system.cpu0.fuPool.FUList5.opList13] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatCmp 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList14] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatCvt 393opLat=1 394 395[system.cpu0.fuPool.FUList5.opList15] 396type=OpDesc 397issueLat=1 398opClass=SimdFloatDiv 399opLat=1 400 401[system.cpu0.fuPool.FUList5.opList16] 402type=OpDesc 403issueLat=1 404opClass=SimdFloatMisc 405opLat=1 406 407[system.cpu0.fuPool.FUList5.opList17] 408type=OpDesc 409issueLat=1 410opClass=SimdFloatMult 411opLat=1 412 413[system.cpu0.fuPool.FUList5.opList18] 414type=OpDesc 415issueLat=1 416opClass=SimdFloatMultAcc 417opLat=1 418 419[system.cpu0.fuPool.FUList5.opList19] 420type=OpDesc 421issueLat=1 422opClass=SimdFloatSqrt 423opLat=1 424 425[system.cpu0.fuPool.FUList6] 426type=FUDesc 427children=opList 428count=0 429opList=system.cpu0.fuPool.FUList6.opList 430 431[system.cpu0.fuPool.FUList6.opList] 432type=OpDesc 433issueLat=1 434opClass=MemWrite 435opLat=1 436 437[system.cpu0.fuPool.FUList7] 438type=FUDesc 439children=opList0 opList1 440count=4 441opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 442 443[system.cpu0.fuPool.FUList7.opList0] 444type=OpDesc 445issueLat=1 446opClass=MemRead 447opLat=1 448 449[system.cpu0.fuPool.FUList7.opList1] 450type=OpDesc 451issueLat=1 452opClass=MemWrite 453opLat=1 454 455[system.cpu0.fuPool.FUList8] 456type=FUDesc 457children=opList 458count=1 459opList=system.cpu0.fuPool.FUList8.opList 460 461[system.cpu0.fuPool.FUList8.opList] 462type=OpDesc 463issueLat=3 464opClass=IprAccess 465opLat=3 466 467[system.cpu0.icache] 468type=BaseCache 469addr_ranges=0:18446744073709551615 470assoc=1 471block_size=64 472forward_snoops=true 473hash_delay=1 474is_top_level=true 475latency=1000 476max_miss_count=0 477mshrs=4 478prefetch_on_access=false 479prefetcher=Null 480prioritizeRequests=false 481repl=Null 482size=32768 483subblock_size=0 484system=system 485tgts_per_mshr=20 486trace_addr=0 487two_queue=false 488write_buffers=8 489cpu_side=system.cpu0.icache_port 490mem_side=system.toL2Bus.slave[0] 491 492[system.cpu0.interrupts] 493type=ArmInterrupts 494 495[system.cpu0.itb] 496type=ArmTLB 497children=walker 498size=64 499walker=system.cpu0.itb.walker 500 501[system.cpu0.itb.walker] 502type=ArmTableWalker 503max_backoff=100000 504min_backoff=0 505sys=system 506port=system.toL2Bus.slave[2] 507 508[system.cpu0.tracer] 509type=ExeTracer 510 511[system.cpu1] 512type=DerivO3CPU 513children=dcache dtb fuPool icache interrupts itb tracer 514BTBEntries=4096 515BTBTagSize=16 516LFSTSize=1024 517LQEntries=32 518LSQCheckLoads=true 519LSQDepCheckShift=4 520RASSize=16 521SQEntries=32 522SSITSize=1024 523activity=0 524backComSize=5 525cachePorts=200 526checker=Null 527choiceCtrBits=2 528choicePredictorSize=8192 529clock=500 530commitToDecodeDelay=1 531commitToFetchDelay=1 532commitToIEWDelay=1 533commitToRenameDelay=1 534commitWidth=8 535cpu_id=1 536decodeToFetchDelay=1 537decodeToRenameDelay=1 538decodeWidth=8 539defer_registration=false 540dispatchWidth=8 541do_checkpoint_insts=true 542do_quiesce=true 543do_statistics_insts=true 544dtb=system.cpu1.dtb 545fetchToDecodeDelay=1 546fetchTrapLatency=1 547fetchWidth=8 548forwardComSize=5 549fuPool=system.cpu1.fuPool 550function_trace=false 551function_trace_start=0 552globalCtrBits=2 553globalHistoryBits=13 554globalPredictorSize=8192 555iewToCommitDelay=1 556iewToDecodeDelay=1 557iewToFetchDelay=1 558iewToRenameDelay=1 559instShiftAmt=2 560interrupts=system.cpu1.interrupts 561issueToExecuteDelay=1 562issueWidth=8 563itb=system.cpu1.itb 564localCtrBits=2 565localHistoryBits=11 566localHistoryTableSize=2048 567localPredictorSize=2048 568max_insts_all_threads=0 569max_insts_any_thread=0 570max_loads_all_threads=0 571max_loads_any_thread=0 572needsTSO=false 573numIQEntries=64 574numPhysFloatRegs=256 575numPhysIntRegs=256 576numROBEntries=192 577numRobs=1 578numThreads=1 579phase=0 580predType=tournament 581profile=0 582progress_interval=0 583renameToDecodeDelay=1 584renameToFetchDelay=1 585renameToIEWDelay=2 586renameToROBDelay=1 587renameWidth=8 588smtCommitPolicy=RoundRobin 589smtFetchPolicy=SingleThread 590smtIQPolicy=Partitioned 591smtIQThreshold=100 592smtLSQPolicy=Partitioned 593smtLSQThreshold=100 594smtNumFetchingThreads=1 595smtROBPolicy=Partitioned 596smtROBThreshold=100 597squashWidth=8 598store_set_clear_period=250000 599system=system 600tracer=system.cpu1.tracer 601trapLatency=13 602wbDepth=1 603wbWidth=8 604workload= 605dcache_port=system.cpu1.dcache.cpu_side 606icache_port=system.cpu1.icache.cpu_side 607 608[system.cpu1.dcache] 609type=BaseCache 610addr_ranges=0:18446744073709551615 611assoc=4 612block_size=64 613forward_snoops=true 614hash_delay=1 615is_top_level=true 616latency=1000 617max_miss_count=0 618mshrs=4 619prefetch_on_access=false 620prefetcher=Null 621prioritizeRequests=false 622repl=Null 623size=32768 624subblock_size=0 625system=system 626tgts_per_mshr=20 627trace_addr=0 628two_queue=false 629write_buffers=8 630cpu_side=system.cpu1.dcache_port 631mem_side=system.toL2Bus.slave[5] 632 633[system.cpu1.dtb] 634type=ArmTLB 635children=walker 636size=64 637walker=system.cpu1.dtb.walker 638 639[system.cpu1.dtb.walker] 640type=ArmTableWalker 641max_backoff=100000 642min_backoff=0 643sys=system 644port=system.toL2Bus.slave[7] 645 646[system.cpu1.fuPool] 647type=FUPool 648children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 649FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 650 651[system.cpu1.fuPool.FUList0] 652type=FUDesc 653children=opList 654count=6 655opList=system.cpu1.fuPool.FUList0.opList 656 657[system.cpu1.fuPool.FUList0.opList] 658type=OpDesc 659issueLat=1 660opClass=IntAlu 661opLat=1 662 663[system.cpu1.fuPool.FUList1] 664type=FUDesc 665children=opList0 opList1 666count=2 667opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 668 669[system.cpu1.fuPool.FUList1.opList0] 670type=OpDesc 671issueLat=1 672opClass=IntMult 673opLat=3 674 675[system.cpu1.fuPool.FUList1.opList1] 676type=OpDesc 677issueLat=19 678opClass=IntDiv 679opLat=20 680 681[system.cpu1.fuPool.FUList2] 682type=FUDesc 683children=opList0 opList1 opList2 684count=4 685opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 686 687[system.cpu1.fuPool.FUList2.opList0] 688type=OpDesc 689issueLat=1 690opClass=FloatAdd 691opLat=2 692 693[system.cpu1.fuPool.FUList2.opList1] 694type=OpDesc 695issueLat=1 696opClass=FloatCmp 697opLat=2 698 699[system.cpu1.fuPool.FUList2.opList2] 700type=OpDesc 701issueLat=1 702opClass=FloatCvt 703opLat=2 704 705[system.cpu1.fuPool.FUList3] 706type=FUDesc 707children=opList0 opList1 opList2 708count=2 709opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 710 711[system.cpu1.fuPool.FUList3.opList0] 712type=OpDesc 713issueLat=1 714opClass=FloatMult 715opLat=4 716 717[system.cpu1.fuPool.FUList3.opList1] 718type=OpDesc 719issueLat=12 720opClass=FloatDiv 721opLat=12 722 723[system.cpu1.fuPool.FUList3.opList2] 724type=OpDesc 725issueLat=24 726opClass=FloatSqrt 727opLat=24 728 729[system.cpu1.fuPool.FUList4] 730type=FUDesc 731children=opList 732count=0 733opList=system.cpu1.fuPool.FUList4.opList 734 735[system.cpu1.fuPool.FUList4.opList] 736type=OpDesc 737issueLat=1 738opClass=MemRead 739opLat=1 740 741[system.cpu1.fuPool.FUList5] 742type=FUDesc 743children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 744count=4 745opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 746 747[system.cpu1.fuPool.FUList5.opList00] 748type=OpDesc 749issueLat=1 750opClass=SimdAdd 751opLat=1 752 753[system.cpu1.fuPool.FUList5.opList01] 754type=OpDesc 755issueLat=1 756opClass=SimdAddAcc 757opLat=1 758 759[system.cpu1.fuPool.FUList5.opList02] 760type=OpDesc 761issueLat=1 762opClass=SimdAlu 763opLat=1 764 765[system.cpu1.fuPool.FUList5.opList03] 766type=OpDesc 767issueLat=1 768opClass=SimdCmp 769opLat=1 770 771[system.cpu1.fuPool.FUList5.opList04] 772type=OpDesc 773issueLat=1 774opClass=SimdCvt 775opLat=1 776 777[system.cpu1.fuPool.FUList5.opList05] 778type=OpDesc 779issueLat=1 780opClass=SimdMisc 781opLat=1 782 783[system.cpu1.fuPool.FUList5.opList06] 784type=OpDesc 785issueLat=1 786opClass=SimdMult 787opLat=1 788 789[system.cpu1.fuPool.FUList5.opList07] 790type=OpDesc 791issueLat=1 792opClass=SimdMultAcc 793opLat=1 794 795[system.cpu1.fuPool.FUList5.opList08] 796type=OpDesc 797issueLat=1 798opClass=SimdShift 799opLat=1 800 801[system.cpu1.fuPool.FUList5.opList09] 802type=OpDesc 803issueLat=1 804opClass=SimdShiftAcc 805opLat=1 806 807[system.cpu1.fuPool.FUList5.opList10] 808type=OpDesc 809issueLat=1 810opClass=SimdSqrt 811opLat=1 812 813[system.cpu1.fuPool.FUList5.opList11] 814type=OpDesc 815issueLat=1 816opClass=SimdFloatAdd 817opLat=1 818 819[system.cpu1.fuPool.FUList5.opList12] 820type=OpDesc 821issueLat=1 822opClass=SimdFloatAlu 823opLat=1 824 825[system.cpu1.fuPool.FUList5.opList13] 826type=OpDesc 827issueLat=1 828opClass=SimdFloatCmp 829opLat=1 830 831[system.cpu1.fuPool.FUList5.opList14] 832type=OpDesc 833issueLat=1 834opClass=SimdFloatCvt 835opLat=1 836 837[system.cpu1.fuPool.FUList5.opList15] 838type=OpDesc 839issueLat=1 840opClass=SimdFloatDiv 841opLat=1 842 843[system.cpu1.fuPool.FUList5.opList16] 844type=OpDesc 845issueLat=1 846opClass=SimdFloatMisc 847opLat=1 848 849[system.cpu1.fuPool.FUList5.opList17] 850type=OpDesc 851issueLat=1 852opClass=SimdFloatMult 853opLat=1 854 855[system.cpu1.fuPool.FUList5.opList18] 856type=OpDesc 857issueLat=1 858opClass=SimdFloatMultAcc 859opLat=1 860 861[system.cpu1.fuPool.FUList5.opList19] 862type=OpDesc 863issueLat=1 864opClass=SimdFloatSqrt 865opLat=1 866 867[system.cpu1.fuPool.FUList6] 868type=FUDesc 869children=opList 870count=0 871opList=system.cpu1.fuPool.FUList6.opList 872 873[system.cpu1.fuPool.FUList6.opList] 874type=OpDesc 875issueLat=1 876opClass=MemWrite 877opLat=1 878 879[system.cpu1.fuPool.FUList7] 880type=FUDesc 881children=opList0 opList1 882count=4 883opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 884 885[system.cpu1.fuPool.FUList7.opList0] 886type=OpDesc 887issueLat=1 888opClass=MemRead 889opLat=1 890 891[system.cpu1.fuPool.FUList7.opList1] 892type=OpDesc 893issueLat=1 894opClass=MemWrite 895opLat=1 896 897[system.cpu1.fuPool.FUList8] 898type=FUDesc 899children=opList 900count=1 901opList=system.cpu1.fuPool.FUList8.opList 902 903[system.cpu1.fuPool.FUList8.opList] 904type=OpDesc 905issueLat=3 906opClass=IprAccess 907opLat=3 908 909[system.cpu1.icache] 910type=BaseCache 911addr_ranges=0:18446744073709551615 912assoc=1 913block_size=64 914forward_snoops=true 915hash_delay=1 916is_top_level=true 917latency=1000 918max_miss_count=0 919mshrs=4 920prefetch_on_access=false 921prefetcher=Null 922prioritizeRequests=false 923repl=Null 924size=32768 925subblock_size=0 926system=system 927tgts_per_mshr=20 928trace_addr=0 929two_queue=false 930write_buffers=8 931cpu_side=system.cpu1.icache_port 932mem_side=system.toL2Bus.slave[4] 933 934[system.cpu1.interrupts] 935type=ArmInterrupts 936 937[system.cpu1.itb] 938type=ArmTLB 939children=walker 940size=64 941walker=system.cpu1.itb.walker 942 943[system.cpu1.itb.walker] 944type=ArmTableWalker 945max_backoff=100000 946min_backoff=0 947sys=system 948port=system.toL2Bus.slave[6] 949 950[system.cpu1.tracer] 951type=ExeTracer 952 953[system.intrctrl] 954type=IntrControl 955sys=system 956 957[system.iobus] 958type=NoncoherentBus 959block_size=64 960clock=1000 961header_cycles=1 962use_default_range=false 963width=8 964master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 965slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 966 967[system.iocache] 968type=BaseCache 969addr_ranges=0:268435455 970assoc=8 971block_size=64 972forward_snoops=false 973hash_delay=1 974is_top_level=false 975latency=50000 976max_miss_count=0 977mshrs=20 978prefetch_on_access=false 979prefetcher=Null 980prioritizeRequests=false 981repl=Null 982size=1024 983subblock_size=0 984system=system 985tgts_per_mshr=12 986trace_addr=0 987two_queue=false 988write_buffers=8 989cpu_side=system.iobus.master[25] 990mem_side=system.membus.slave[1] 991 992[system.l2c] 993type=BaseCache 994addr_ranges=0:18446744073709551615 995assoc=8 996block_size=64 997forward_snoops=true 998hash_delay=1 999is_top_level=false 1000latency=10000 1001max_miss_count=0 1002mshrs=92 1003prefetch_on_access=false 1004prefetcher=Null 1005prioritizeRequests=false 1006repl=Null 1007size=4194304 1008subblock_size=0 1009system=system 1010tgts_per_mshr=16 1011trace_addr=0 1012two_queue=false 1013write_buffers=8 1014cpu_side=system.toL2Bus.master[0] 1015mem_side=system.membus.slave[2] 1016 1017[system.membus] 1018type=CoherentBus 1019children=badaddr_responder 1020block_size=64 1021clock=1000 1022header_cycles=1 1023use_default_range=false 1024width=8 1025default=system.membus.badaddr_responder.pio 1026master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 1027slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1028 1029[system.membus.badaddr_responder] 1030type=IsaFake 1031fake_mem=false 1032pio_addr=0 1033pio_latency=1000 1034pio_size=8 1035ret_bad_addr=true 1036ret_data16=65535 1037ret_data32=4294967295 1038ret_data64=18446744073709551615 1039ret_data8=255 1040system=system 1041update_data=false 1042warn_access=warn 1043pio=system.membus.default 1044 1045[system.physmem] 1046type=SimpleMemory 1047conf_table_reported=true 1048file= 1049in_addr_map=true 1050latency=30000 1051latency_var=0 1052null=false 1053range=0:134217727 1054zero=false 1055port=system.membus.master[2] 1056 1057[system.realview] 1058type=RealView 1059children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1060intrctrl=system.intrctrl 1061max_mem_size=268435456 1062mem_start_addr=0 1063pci_cfg_base=0 1064system=system 1065 1066[system.realview.a9scu] 1067type=A9SCU 1068pio_addr=520093696 1069pio_latency=1000 1070system=system 1071pio=system.membus.master[5] 1072 1073[system.realview.aaci_fake] 1074type=AmbaFake 1075amba_id=0 1076ignore_access=false 1077pio_addr=268451840 1078pio_latency=1000 1079system=system 1080pio=system.iobus.master[21] 1081 1082[system.realview.cf_ctrl] 1083type=IdeController 1084BAR0=402653184 1085BAR0LegacyIO=true 1086BAR0Size=16 1087BAR1=402653440 1088BAR1LegacyIO=true 1089BAR1Size=1 1090BAR2=1 1091BAR2LegacyIO=false 1092BAR2Size=8 1093BAR3=1 1094BAR3LegacyIO=false 1095BAR3Size=4 1096BAR4=1 1097BAR4LegacyIO=false 1098BAR4Size=16 1099BAR5=1 1100BAR5LegacyIO=false 1101BAR5Size=0 1102BIST=0 1103CacheLineSize=0 1104CardbusCIS=0 1105ClassCode=1 1106Command=1 1107DeviceID=28945 1108ExpansionROM=0 1109HeaderType=0 1110InterruptLine=31 1111InterruptPin=1 1112LatencyTimer=0 1113MaximumLatency=0 1114MinimumGrant=0 1115ProgIF=133 1116Revision=0 1117Status=640 1118SubClassCode=1 1119SubsystemID=0 1120SubsystemVendorID=0 1121VendorID=32902 1122config_latency=20000 1123ctrl_offset=2 1124disks=system.cf0 1125io_shift=1 1126max_backoff_delay=10000000 1127min_backoff_delay=4000 1128pci_bus=2 1129pci_dev=7 1130pci_func=0 1131pio_latency=1000 1132platform=system.realview 1133system=system 1134config=system.iobus.master[8] 1135dma=system.iobus.slave[2] 1136pio=system.iobus.master[7] 1137 1138[system.realview.clcd] 1139type=Pl111 1140amba_id=1315089 1141clock=41667 1142gic=system.realview.gic 1143int_num=55 1144max_backoff_delay=10000000 1145min_backoff_delay=4000 1146pio_addr=268566528 1147pio_latency=10000 1148system=system 1149vnc=system.vncserver 1150dma=system.iobus.slave[1] 1151pio=system.iobus.master[4] 1152 1153[system.realview.dmac_fake] 1154type=AmbaFake 1155amba_id=0 1156ignore_access=false 1157pio_addr=268632064 1158pio_latency=1000 1159system=system 1160pio=system.iobus.master[9] 1161 1162[system.realview.flash_fake] 1163type=IsaFake 1164fake_mem=true 1165pio_addr=1073741824 1166pio_latency=1000 1167pio_size=536870912 1168ret_bad_addr=false 1169ret_data16=65535 1170ret_data32=4294967295 1171ret_data64=18446744073709551615 1172ret_data8=255 1173system=system 1174update_data=false 1175warn_access= 1176pio=system.iobus.master[24] 1177 1178[system.realview.gic] 1179type=Gic 1180cpu_addr=520093952 1181cpu_pio_delay=10000 1182dist_addr=520097792 1183dist_pio_delay=10000 1184int_latency=10000 1185it_lines=128 1186platform=system.realview 1187system=system 1188pio=system.membus.master[3] 1189 1190[system.realview.gpio0_fake] 1191type=AmbaFake 1192amba_id=0 1193ignore_access=false 1194pio_addr=268513280 1195pio_latency=1000 1196system=system 1197pio=system.iobus.master[16] 1198 1199[system.realview.gpio1_fake] 1200type=AmbaFake 1201amba_id=0 1202ignore_access=false 1203pio_addr=268517376 1204pio_latency=1000 1205system=system 1206pio=system.iobus.master[17] 1207 1208[system.realview.gpio2_fake] 1209type=AmbaFake 1210amba_id=0 1211ignore_access=false 1212pio_addr=268521472 1213pio_latency=1000 1214system=system 1215pio=system.iobus.master[18] 1216 1217[system.realview.kmi0] 1218type=Pl050 1219amba_id=1314896 1220gic=system.realview.gic 1221int_delay=1000000 1222int_num=52 1223is_mouse=false 1224pio_addr=268460032 1225pio_latency=1000 1226system=system 1227vnc=system.vncserver 1228pio=system.iobus.master[5] 1229 1230[system.realview.kmi1] 1231type=Pl050 1232amba_id=1314896 1233gic=system.realview.gic 1234int_delay=1000000 1235int_num=53 1236is_mouse=true 1237pio_addr=268464128 1238pio_latency=1000 1239system=system 1240vnc=system.vncserver 1241pio=system.iobus.master[6] 1242 1243[system.realview.l2x0_fake] 1244type=IsaFake 1245fake_mem=false 1246pio_addr=520101888 1247pio_latency=1000 1248pio_size=4095 1249ret_bad_addr=false 1250ret_data16=65535 1251ret_data32=4294967295 1252ret_data64=18446744073709551615 1253ret_data8=255 1254system=system 1255update_data=false 1256warn_access= 1257pio=system.membus.master[4] 1258 1259[system.realview.local_cpu_timer] 1260type=CpuLocalTimer 1261clock=1000 1262gic=system.realview.gic 1263int_num_timer=29 1264int_num_watchdog=30 1265pio_addr=520095232 1266pio_latency=1000 1267system=system 1268pio=system.membus.master[6] 1269 1270[system.realview.mmc_fake] 1271type=AmbaFake 1272amba_id=0 1273ignore_access=false 1274pio_addr=268455936 1275pio_latency=1000 1276system=system 1277pio=system.iobus.master[22] 1278 1279[system.realview.nvmem] 1280type=SimpleMemory 1281conf_table_reported=false 1282file= 1283in_addr_map=true 1284latency=30000 1285latency_var=0 1286null=false 1287range=2147483648:2214592511 1288zero=true 1289port=system.membus.master[1] 1290 1291[system.realview.realview_io] 1292type=RealViewCtrl 1293idreg=0 1294pio_addr=268435456 1295pio_latency=1000 1296proc_id0=201326592 1297proc_id1=201327138 1298system=system 1299pio=system.iobus.master[1] 1300 1301[system.realview.rtc] 1302type=PL031 1303amba_id=3412017 1304gic=system.realview.gic 1305int_delay=100000 1306int_num=42 1307pio_addr=268529664 1308pio_latency=1000 1309system=system 1310time=Thu Jan 1 00:00:00 2009 1311pio=system.iobus.master[23] 1312 1313[system.realview.sci_fake] 1314type=AmbaFake 1315amba_id=0 1316ignore_access=false 1317pio_addr=268492800 1318pio_latency=1000 1319system=system 1320pio=system.iobus.master[20] 1321 1322[system.realview.smc_fake] 1323type=AmbaFake 1324amba_id=0 1325ignore_access=false 1326pio_addr=269357056 1327pio_latency=1000 1328system=system 1329pio=system.iobus.master[13] 1330 1331[system.realview.sp810_fake] 1332type=AmbaFake 1333amba_id=0 1334ignore_access=true 1335pio_addr=268439552 1336pio_latency=1000 1337system=system 1338pio=system.iobus.master[14] 1339 1340[system.realview.ssp_fake] 1341type=AmbaFake 1342amba_id=0 1343ignore_access=false 1344pio_addr=268488704 1345pio_latency=1000 1346system=system 1347pio=system.iobus.master[19] 1348 1349[system.realview.timer0] 1350type=Sp804 1351amba_id=1316868 1352clock0=1000000 1353clock1=1000000 1354gic=system.realview.gic 1355int_num0=36 1356int_num1=36 1357pio_addr=268505088 1358pio_latency=1000 1359system=system 1360pio=system.iobus.master[2] 1361 1362[system.realview.timer1] 1363type=Sp804 1364amba_id=1316868 1365clock0=1000000 1366clock1=1000000 1367gic=system.realview.gic 1368int_num0=37 1369int_num1=37 1370pio_addr=268509184 1371pio_latency=1000 1372system=system 1373pio=system.iobus.master[3] 1374 1375[system.realview.uart] 1376type=Pl011 1377end_on_eot=false 1378gic=system.realview.gic 1379int_delay=100000 1380int_num=44 1381pio_addr=268472320 1382pio_latency=1000 1383platform=system.realview 1384system=system 1385terminal=system.terminal 1386pio=system.iobus.master[0] 1387 1388[system.realview.uart1_fake] 1389type=AmbaFake 1390amba_id=0 1391ignore_access=false 1392pio_addr=268476416 1393pio_latency=1000 1394system=system 1395pio=system.iobus.master[10] 1396 1397[system.realview.uart2_fake] 1398type=AmbaFake 1399amba_id=0 1400ignore_access=false 1401pio_addr=268480512 1402pio_latency=1000 1403system=system 1404pio=system.iobus.master[11] 1405 1406[system.realview.uart3_fake] 1407type=AmbaFake 1408amba_id=0 1409ignore_access=false 1410pio_addr=268484608 1411pio_latency=1000 1412system=system 1413pio=system.iobus.master[12] 1414 1415[system.realview.watchdog_fake] 1416type=AmbaFake 1417amba_id=0 1418ignore_access=false 1419pio_addr=268500992 1420pio_latency=1000 1421system=system 1422pio=system.iobus.master[15] 1423 1424[system.terminal] 1425type=Terminal 1426intr_control=system.intrctrl 1427number=0 1428output=true 1429port=3456 1430 1431[system.toL2Bus] 1432type=CoherentBus 1433block_size=64 1434clock=1000 1435header_cycles=1 1436use_default_range=false 1437width=8 1438master=system.l2c.cpu_side 1439slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1440 1441[system.vncserver] 1442type=VncServer 1443frame_capture=false 1444number=0 1445port=5900 1446 1447