config.ini revision 9055:38f1926fb599
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15early_kernel_symbols=false 16flags_addr=268435504 17gic_cpu_addr=520093952 18init_param=0 19kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 20load_addr_mask=268435455 21machine_type=RealView_PBX 22mem_mode=timing 23memories=system.physmem system.realview.nvmem 24midr_regval=890224640 25num_work_ids=16 26readfile=tests/halt.sh 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39delay=50000 40nack_delay=4000 41ranges=268435456:520093695 1073741824:1610612735 42req_size=16 43resp_size=16 44write_ack=false 45master=system.iobus.slave[0] 46slave=system.membus.master[0] 47 48[system.cf0] 49type=IdeDisk 50children=image 51delay=1000000 52driveID=master 53image=system.cf0.image 54 55[system.cf0.image] 56type=CowDiskImage 57children=child 58child=system.cf0.image.child 59image_file= 60read_only=false 61table_size=65536 62 63[system.cf0.image.child] 64type=RawDiskImage 65image_file=/dist/m5/system/disks/linux-arm-ael.img 66read_only=true 67 68[system.cpu0] 69type=DerivO3CPU 70children=dcache dtb fuPool icache interrupts itb tracer 71BTBEntries=4096 72BTBTagSize=16 73LFSTSize=1024 74LQEntries=32 75LSQCheckLoads=true 76LSQDepCheckShift=4 77RASSize=16 78SQEntries=32 79SSITSize=1024 80activity=0 81backComSize=5 82cachePorts=200 83checker=Null 84choiceCtrBits=2 85choicePredictorSize=8192 86clock=500 87commitToDecodeDelay=1 88commitToFetchDelay=1 89commitToIEWDelay=1 90commitToRenameDelay=1 91commitWidth=8 92cpu_id=0 93decodeToFetchDelay=1 94decodeToRenameDelay=1 95decodeWidth=8 96defer_registration=false 97dispatchWidth=8 98do_checkpoint_insts=true 99do_quiesce=true 100do_statistics_insts=true 101dtb=system.cpu0.dtb 102fetchToDecodeDelay=1 103fetchTrapLatency=1 104fetchWidth=8 105forwardComSize=5 106fuPool=system.cpu0.fuPool 107function_trace=false 108function_trace_start=0 109globalCtrBits=2 110globalHistoryBits=13 111globalPredictorSize=8192 112iewToCommitDelay=1 113iewToDecodeDelay=1 114iewToFetchDelay=1 115iewToRenameDelay=1 116instShiftAmt=2 117interrupts=system.cpu0.interrupts 118issueToExecuteDelay=1 119issueWidth=8 120itb=system.cpu0.itb 121localCtrBits=2 122localHistoryBits=11 123localHistoryTableSize=2048 124localPredictorSize=2048 125max_insts_all_threads=0 126max_insts_any_thread=0 127max_loads_all_threads=0 128max_loads_any_thread=0 129needsTSO=false 130numIQEntries=64 131numPhysFloatRegs=256 132numPhysIntRegs=256 133numROBEntries=192 134numRobs=1 135numThreads=1 136phase=0 137predType=tournament 138profile=0 139progress_interval=0 140renameToDecodeDelay=1 141renameToFetchDelay=1 142renameToIEWDelay=2 143renameToROBDelay=1 144renameWidth=8 145smtCommitPolicy=RoundRobin 146smtFetchPolicy=SingleThread 147smtIQPolicy=Partitioned 148smtIQThreshold=100 149smtLSQPolicy=Partitioned 150smtLSQThreshold=100 151smtNumFetchingThreads=1 152smtROBPolicy=Partitioned 153smtROBThreshold=100 154squashWidth=8 155store_set_clear_period=250000 156system=system 157tracer=system.cpu0.tracer 158trapLatency=13 159wbDepth=1 160wbWidth=8 161workload= 162dcache_port=system.cpu0.dcache.cpu_side 163icache_port=system.cpu0.icache.cpu_side 164 165[system.cpu0.dcache] 166type=BaseCache 167addr_ranges=0:18446744073709551615 168assoc=4 169block_size=64 170forward_snoops=true 171hash_delay=1 172is_top_level=true 173latency=1000 174max_miss_count=0 175mshrs=4 176prefetch_on_access=false 177prefetcher=Null 178prioritizeRequests=false 179repl=Null 180size=32768 181subblock_size=0 182system=system 183tgts_per_mshr=20 184trace_addr=0 185two_queue=false 186write_buffers=8 187cpu_side=system.cpu0.dcache_port 188mem_side=system.toL2Bus.slave[1] 189 190[system.cpu0.dtb] 191type=ArmTLB 192children=walker 193size=64 194walker=system.cpu0.dtb.walker 195 196[system.cpu0.dtb.walker] 197type=ArmTableWalker 198max_backoff=100000 199min_backoff=0 200sys=system 201port=system.toL2Bus.slave[3] 202 203[system.cpu0.fuPool] 204type=FUPool 205children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 206FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 207 208[system.cpu0.fuPool.FUList0] 209type=FUDesc 210children=opList 211count=6 212opList=system.cpu0.fuPool.FUList0.opList 213 214[system.cpu0.fuPool.FUList0.opList] 215type=OpDesc 216issueLat=1 217opClass=IntAlu 218opLat=1 219 220[system.cpu0.fuPool.FUList1] 221type=FUDesc 222children=opList0 opList1 223count=2 224opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 225 226[system.cpu0.fuPool.FUList1.opList0] 227type=OpDesc 228issueLat=1 229opClass=IntMult 230opLat=3 231 232[system.cpu0.fuPool.FUList1.opList1] 233type=OpDesc 234issueLat=19 235opClass=IntDiv 236opLat=20 237 238[system.cpu0.fuPool.FUList2] 239type=FUDesc 240children=opList0 opList1 opList2 241count=4 242opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 243 244[system.cpu0.fuPool.FUList2.opList0] 245type=OpDesc 246issueLat=1 247opClass=FloatAdd 248opLat=2 249 250[system.cpu0.fuPool.FUList2.opList1] 251type=OpDesc 252issueLat=1 253opClass=FloatCmp 254opLat=2 255 256[system.cpu0.fuPool.FUList2.opList2] 257type=OpDesc 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu0.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 267 268[system.cpu0.fuPool.FUList3.opList0] 269type=OpDesc 270issueLat=1 271opClass=FloatMult 272opLat=4 273 274[system.cpu0.fuPool.FUList3.opList1] 275type=OpDesc 276issueLat=12 277opClass=FloatDiv 278opLat=12 279 280[system.cpu0.fuPool.FUList3.opList2] 281type=OpDesc 282issueLat=24 283opClass=FloatSqrt 284opLat=24 285 286[system.cpu0.fuPool.FUList4] 287type=FUDesc 288children=opList 289count=0 290opList=system.cpu0.fuPool.FUList4.opList 291 292[system.cpu0.fuPool.FUList4.opList] 293type=OpDesc 294issueLat=1 295opClass=MemRead 296opLat=1 297 298[system.cpu0.fuPool.FUList5] 299type=FUDesc 300children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 301count=4 302opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 303 304[system.cpu0.fuPool.FUList5.opList00] 305type=OpDesc 306issueLat=1 307opClass=SimdAdd 308opLat=1 309 310[system.cpu0.fuPool.FUList5.opList01] 311type=OpDesc 312issueLat=1 313opClass=SimdAddAcc 314opLat=1 315 316[system.cpu0.fuPool.FUList5.opList02] 317type=OpDesc 318issueLat=1 319opClass=SimdAlu 320opLat=1 321 322[system.cpu0.fuPool.FUList5.opList03] 323type=OpDesc 324issueLat=1 325opClass=SimdCmp 326opLat=1 327 328[system.cpu0.fuPool.FUList5.opList04] 329type=OpDesc 330issueLat=1 331opClass=SimdCvt 332opLat=1 333 334[system.cpu0.fuPool.FUList5.opList05] 335type=OpDesc 336issueLat=1 337opClass=SimdMisc 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList06] 341type=OpDesc 342issueLat=1 343opClass=SimdMult 344opLat=1 345 346[system.cpu0.fuPool.FUList5.opList07] 347type=OpDesc 348issueLat=1 349opClass=SimdMultAcc 350opLat=1 351 352[system.cpu0.fuPool.FUList5.opList08] 353type=OpDesc 354issueLat=1 355opClass=SimdShift 356opLat=1 357 358[system.cpu0.fuPool.FUList5.opList09] 359type=OpDesc 360issueLat=1 361opClass=SimdShiftAcc 362opLat=1 363 364[system.cpu0.fuPool.FUList5.opList10] 365type=OpDesc 366issueLat=1 367opClass=SimdSqrt 368opLat=1 369 370[system.cpu0.fuPool.FUList5.opList11] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatAdd 374opLat=1 375 376[system.cpu0.fuPool.FUList5.opList12] 377type=OpDesc 378issueLat=1 379opClass=SimdFloatAlu 380opLat=1 381 382[system.cpu0.fuPool.FUList5.opList13] 383type=OpDesc 384issueLat=1 385opClass=SimdFloatCmp 386opLat=1 387 388[system.cpu0.fuPool.FUList5.opList14] 389type=OpDesc 390issueLat=1 391opClass=SimdFloatCvt 392opLat=1 393 394[system.cpu0.fuPool.FUList5.opList15] 395type=OpDesc 396issueLat=1 397opClass=SimdFloatDiv 398opLat=1 399 400[system.cpu0.fuPool.FUList5.opList16] 401type=OpDesc 402issueLat=1 403opClass=SimdFloatMisc 404opLat=1 405 406[system.cpu0.fuPool.FUList5.opList17] 407type=OpDesc 408issueLat=1 409opClass=SimdFloatMult 410opLat=1 411 412[system.cpu0.fuPool.FUList5.opList18] 413type=OpDesc 414issueLat=1 415opClass=SimdFloatMultAcc 416opLat=1 417 418[system.cpu0.fuPool.FUList5.opList19] 419type=OpDesc 420issueLat=1 421opClass=SimdFloatSqrt 422opLat=1 423 424[system.cpu0.fuPool.FUList6] 425type=FUDesc 426children=opList 427count=0 428opList=system.cpu0.fuPool.FUList6.opList 429 430[system.cpu0.fuPool.FUList6.opList] 431type=OpDesc 432issueLat=1 433opClass=MemWrite 434opLat=1 435 436[system.cpu0.fuPool.FUList7] 437type=FUDesc 438children=opList0 opList1 439count=4 440opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 441 442[system.cpu0.fuPool.FUList7.opList0] 443type=OpDesc 444issueLat=1 445opClass=MemRead 446opLat=1 447 448[system.cpu0.fuPool.FUList7.opList1] 449type=OpDesc 450issueLat=1 451opClass=MemWrite 452opLat=1 453 454[system.cpu0.fuPool.FUList8] 455type=FUDesc 456children=opList 457count=1 458opList=system.cpu0.fuPool.FUList8.opList 459 460[system.cpu0.fuPool.FUList8.opList] 461type=OpDesc 462issueLat=3 463opClass=IprAccess 464opLat=3 465 466[system.cpu0.icache] 467type=BaseCache 468addr_ranges=0:18446744073709551615 469assoc=1 470block_size=64 471forward_snoops=true 472hash_delay=1 473is_top_level=true 474latency=1000 475max_miss_count=0 476mshrs=4 477prefetch_on_access=false 478prefetcher=Null 479prioritizeRequests=false 480repl=Null 481size=32768 482subblock_size=0 483system=system 484tgts_per_mshr=20 485trace_addr=0 486two_queue=false 487write_buffers=8 488cpu_side=system.cpu0.icache_port 489mem_side=system.toL2Bus.slave[0] 490 491[system.cpu0.interrupts] 492type=ArmInterrupts 493 494[system.cpu0.itb] 495type=ArmTLB 496children=walker 497size=64 498walker=system.cpu0.itb.walker 499 500[system.cpu0.itb.walker] 501type=ArmTableWalker 502max_backoff=100000 503min_backoff=0 504sys=system 505port=system.toL2Bus.slave[2] 506 507[system.cpu0.tracer] 508type=ExeTracer 509 510[system.cpu1] 511type=DerivO3CPU 512children=dcache dtb fuPool icache interrupts itb tracer 513BTBEntries=4096 514BTBTagSize=16 515LFSTSize=1024 516LQEntries=32 517LSQCheckLoads=true 518LSQDepCheckShift=4 519RASSize=16 520SQEntries=32 521SSITSize=1024 522activity=0 523backComSize=5 524cachePorts=200 525checker=Null 526choiceCtrBits=2 527choicePredictorSize=8192 528clock=500 529commitToDecodeDelay=1 530commitToFetchDelay=1 531commitToIEWDelay=1 532commitToRenameDelay=1 533commitWidth=8 534cpu_id=1 535decodeToFetchDelay=1 536decodeToRenameDelay=1 537decodeWidth=8 538defer_registration=false 539dispatchWidth=8 540do_checkpoint_insts=true 541do_quiesce=true 542do_statistics_insts=true 543dtb=system.cpu1.dtb 544fetchToDecodeDelay=1 545fetchTrapLatency=1 546fetchWidth=8 547forwardComSize=5 548fuPool=system.cpu1.fuPool 549function_trace=false 550function_trace_start=0 551globalCtrBits=2 552globalHistoryBits=13 553globalPredictorSize=8192 554iewToCommitDelay=1 555iewToDecodeDelay=1 556iewToFetchDelay=1 557iewToRenameDelay=1 558instShiftAmt=2 559interrupts=system.cpu1.interrupts 560issueToExecuteDelay=1 561issueWidth=8 562itb=system.cpu1.itb 563localCtrBits=2 564localHistoryBits=11 565localHistoryTableSize=2048 566localPredictorSize=2048 567max_insts_all_threads=0 568max_insts_any_thread=0 569max_loads_all_threads=0 570max_loads_any_thread=0 571needsTSO=false 572numIQEntries=64 573numPhysFloatRegs=256 574numPhysIntRegs=256 575numROBEntries=192 576numRobs=1 577numThreads=1 578phase=0 579predType=tournament 580profile=0 581progress_interval=0 582renameToDecodeDelay=1 583renameToFetchDelay=1 584renameToIEWDelay=2 585renameToROBDelay=1 586renameWidth=8 587smtCommitPolicy=RoundRobin 588smtFetchPolicy=SingleThread 589smtIQPolicy=Partitioned 590smtIQThreshold=100 591smtLSQPolicy=Partitioned 592smtLSQThreshold=100 593smtNumFetchingThreads=1 594smtROBPolicy=Partitioned 595smtROBThreshold=100 596squashWidth=8 597store_set_clear_period=250000 598system=system 599tracer=system.cpu1.tracer 600trapLatency=13 601wbDepth=1 602wbWidth=8 603workload= 604dcache_port=system.cpu1.dcache.cpu_side 605icache_port=system.cpu1.icache.cpu_side 606 607[system.cpu1.dcache] 608type=BaseCache 609addr_ranges=0:18446744073709551615 610assoc=4 611block_size=64 612forward_snoops=true 613hash_delay=1 614is_top_level=true 615latency=1000 616max_miss_count=0 617mshrs=4 618prefetch_on_access=false 619prefetcher=Null 620prioritizeRequests=false 621repl=Null 622size=32768 623subblock_size=0 624system=system 625tgts_per_mshr=20 626trace_addr=0 627two_queue=false 628write_buffers=8 629cpu_side=system.cpu1.dcache_port 630mem_side=system.toL2Bus.slave[5] 631 632[system.cpu1.dtb] 633type=ArmTLB 634children=walker 635size=64 636walker=system.cpu1.dtb.walker 637 638[system.cpu1.dtb.walker] 639type=ArmTableWalker 640max_backoff=100000 641min_backoff=0 642sys=system 643port=system.toL2Bus.slave[7] 644 645[system.cpu1.fuPool] 646type=FUPool 647children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 648FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 649 650[system.cpu1.fuPool.FUList0] 651type=FUDesc 652children=opList 653count=6 654opList=system.cpu1.fuPool.FUList0.opList 655 656[system.cpu1.fuPool.FUList0.opList] 657type=OpDesc 658issueLat=1 659opClass=IntAlu 660opLat=1 661 662[system.cpu1.fuPool.FUList1] 663type=FUDesc 664children=opList0 opList1 665count=2 666opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 667 668[system.cpu1.fuPool.FUList1.opList0] 669type=OpDesc 670issueLat=1 671opClass=IntMult 672opLat=3 673 674[system.cpu1.fuPool.FUList1.opList1] 675type=OpDesc 676issueLat=19 677opClass=IntDiv 678opLat=20 679 680[system.cpu1.fuPool.FUList2] 681type=FUDesc 682children=opList0 opList1 opList2 683count=4 684opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 685 686[system.cpu1.fuPool.FUList2.opList0] 687type=OpDesc 688issueLat=1 689opClass=FloatAdd 690opLat=2 691 692[system.cpu1.fuPool.FUList2.opList1] 693type=OpDesc 694issueLat=1 695opClass=FloatCmp 696opLat=2 697 698[system.cpu1.fuPool.FUList2.opList2] 699type=OpDesc 700issueLat=1 701opClass=FloatCvt 702opLat=2 703 704[system.cpu1.fuPool.FUList3] 705type=FUDesc 706children=opList0 opList1 opList2 707count=2 708opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 709 710[system.cpu1.fuPool.FUList3.opList0] 711type=OpDesc 712issueLat=1 713opClass=FloatMult 714opLat=4 715 716[system.cpu1.fuPool.FUList3.opList1] 717type=OpDesc 718issueLat=12 719opClass=FloatDiv 720opLat=12 721 722[system.cpu1.fuPool.FUList3.opList2] 723type=OpDesc 724issueLat=24 725opClass=FloatSqrt 726opLat=24 727 728[system.cpu1.fuPool.FUList4] 729type=FUDesc 730children=opList 731count=0 732opList=system.cpu1.fuPool.FUList4.opList 733 734[system.cpu1.fuPool.FUList4.opList] 735type=OpDesc 736issueLat=1 737opClass=MemRead 738opLat=1 739 740[system.cpu1.fuPool.FUList5] 741type=FUDesc 742children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 743count=4 744opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 745 746[system.cpu1.fuPool.FUList5.opList00] 747type=OpDesc 748issueLat=1 749opClass=SimdAdd 750opLat=1 751 752[system.cpu1.fuPool.FUList5.opList01] 753type=OpDesc 754issueLat=1 755opClass=SimdAddAcc 756opLat=1 757 758[system.cpu1.fuPool.FUList5.opList02] 759type=OpDesc 760issueLat=1 761opClass=SimdAlu 762opLat=1 763 764[system.cpu1.fuPool.FUList5.opList03] 765type=OpDesc 766issueLat=1 767opClass=SimdCmp 768opLat=1 769 770[system.cpu1.fuPool.FUList5.opList04] 771type=OpDesc 772issueLat=1 773opClass=SimdCvt 774opLat=1 775 776[system.cpu1.fuPool.FUList5.opList05] 777type=OpDesc 778issueLat=1 779opClass=SimdMisc 780opLat=1 781 782[system.cpu1.fuPool.FUList5.opList06] 783type=OpDesc 784issueLat=1 785opClass=SimdMult 786opLat=1 787 788[system.cpu1.fuPool.FUList5.opList07] 789type=OpDesc 790issueLat=1 791opClass=SimdMultAcc 792opLat=1 793 794[system.cpu1.fuPool.FUList5.opList08] 795type=OpDesc 796issueLat=1 797opClass=SimdShift 798opLat=1 799 800[system.cpu1.fuPool.FUList5.opList09] 801type=OpDesc 802issueLat=1 803opClass=SimdShiftAcc 804opLat=1 805 806[system.cpu1.fuPool.FUList5.opList10] 807type=OpDesc 808issueLat=1 809opClass=SimdSqrt 810opLat=1 811 812[system.cpu1.fuPool.FUList5.opList11] 813type=OpDesc 814issueLat=1 815opClass=SimdFloatAdd 816opLat=1 817 818[system.cpu1.fuPool.FUList5.opList12] 819type=OpDesc 820issueLat=1 821opClass=SimdFloatAlu 822opLat=1 823 824[system.cpu1.fuPool.FUList5.opList13] 825type=OpDesc 826issueLat=1 827opClass=SimdFloatCmp 828opLat=1 829 830[system.cpu1.fuPool.FUList5.opList14] 831type=OpDesc 832issueLat=1 833opClass=SimdFloatCvt 834opLat=1 835 836[system.cpu1.fuPool.FUList5.opList15] 837type=OpDesc 838issueLat=1 839opClass=SimdFloatDiv 840opLat=1 841 842[system.cpu1.fuPool.FUList5.opList16] 843type=OpDesc 844issueLat=1 845opClass=SimdFloatMisc 846opLat=1 847 848[system.cpu1.fuPool.FUList5.opList17] 849type=OpDesc 850issueLat=1 851opClass=SimdFloatMult 852opLat=1 853 854[system.cpu1.fuPool.FUList5.opList18] 855type=OpDesc 856issueLat=1 857opClass=SimdFloatMultAcc 858opLat=1 859 860[system.cpu1.fuPool.FUList5.opList19] 861type=OpDesc 862issueLat=1 863opClass=SimdFloatSqrt 864opLat=1 865 866[system.cpu1.fuPool.FUList6] 867type=FUDesc 868children=opList 869count=0 870opList=system.cpu1.fuPool.FUList6.opList 871 872[system.cpu1.fuPool.FUList6.opList] 873type=OpDesc 874issueLat=1 875opClass=MemWrite 876opLat=1 877 878[system.cpu1.fuPool.FUList7] 879type=FUDesc 880children=opList0 opList1 881count=4 882opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 883 884[system.cpu1.fuPool.FUList7.opList0] 885type=OpDesc 886issueLat=1 887opClass=MemRead 888opLat=1 889 890[system.cpu1.fuPool.FUList7.opList1] 891type=OpDesc 892issueLat=1 893opClass=MemWrite 894opLat=1 895 896[system.cpu1.fuPool.FUList8] 897type=FUDesc 898children=opList 899count=1 900opList=system.cpu1.fuPool.FUList8.opList 901 902[system.cpu1.fuPool.FUList8.opList] 903type=OpDesc 904issueLat=3 905opClass=IprAccess 906opLat=3 907 908[system.cpu1.icache] 909type=BaseCache 910addr_ranges=0:18446744073709551615 911assoc=1 912block_size=64 913forward_snoops=true 914hash_delay=1 915is_top_level=true 916latency=1000 917max_miss_count=0 918mshrs=4 919prefetch_on_access=false 920prefetcher=Null 921prioritizeRequests=false 922repl=Null 923size=32768 924subblock_size=0 925system=system 926tgts_per_mshr=20 927trace_addr=0 928two_queue=false 929write_buffers=8 930cpu_side=system.cpu1.icache_port 931mem_side=system.toL2Bus.slave[4] 932 933[system.cpu1.interrupts] 934type=ArmInterrupts 935 936[system.cpu1.itb] 937type=ArmTLB 938children=walker 939size=64 940walker=system.cpu1.itb.walker 941 942[system.cpu1.itb.walker] 943type=ArmTableWalker 944max_backoff=100000 945min_backoff=0 946sys=system 947port=system.toL2Bus.slave[6] 948 949[system.cpu1.tracer] 950type=ExeTracer 951 952[system.intrctrl] 953type=IntrControl 954sys=system 955 956[system.iobus] 957type=NoncoherentBus 958block_size=64 959clock=1000 960header_cycles=1 961use_default_range=false 962width=64 963master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 964slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 965 966[system.iocache] 967type=BaseCache 968addr_ranges=0:268435455 969assoc=8 970block_size=64 971forward_snoops=false 972hash_delay=1 973is_top_level=false 974latency=50000 975max_miss_count=0 976mshrs=20 977prefetch_on_access=false 978prefetcher=Null 979prioritizeRequests=false 980repl=Null 981size=1024 982subblock_size=0 983system=system 984tgts_per_mshr=12 985trace_addr=0 986two_queue=false 987write_buffers=8 988cpu_side=system.iobus.master[25] 989mem_side=system.membus.slave[1] 990 991[system.l2c] 992type=BaseCache 993addr_ranges=0:18446744073709551615 994assoc=8 995block_size=64 996forward_snoops=true 997hash_delay=1 998is_top_level=false 999latency=10000 1000max_miss_count=0 1001mshrs=92 1002prefetch_on_access=false 1003prefetcher=Null 1004prioritizeRequests=false 1005repl=Null 1006size=4194304 1007subblock_size=0 1008system=system 1009tgts_per_mshr=16 1010trace_addr=0 1011two_queue=false 1012write_buffers=8 1013cpu_side=system.toL2Bus.master[0] 1014mem_side=system.membus.slave[2] 1015 1016[system.membus] 1017type=CoherentBus 1018children=badaddr_responder 1019block_size=64 1020clock=1000 1021header_cycles=1 1022use_default_range=false 1023width=64 1024default=system.membus.badaddr_responder.pio 1025master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 1026slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1027 1028[system.membus.badaddr_responder] 1029type=IsaFake 1030fake_mem=false 1031pio_addr=0 1032pio_latency=1000 1033pio_size=8 1034ret_bad_addr=true 1035ret_data16=65535 1036ret_data32=4294967295 1037ret_data64=18446744073709551615 1038ret_data8=255 1039system=system 1040update_data=false 1041warn_access=warn 1042pio=system.membus.default 1043 1044[system.physmem] 1045type=SimpleMemory 1046conf_table_reported=true 1047file= 1048in_addr_map=true 1049latency=30000 1050latency_var=0 1051null=false 1052range=0:134217727 1053zero=false 1054port=system.membus.master[2] 1055 1056[system.realview] 1057type=RealView 1058children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1059intrctrl=system.intrctrl 1060max_mem_size=268435456 1061mem_start_addr=0 1062pci_cfg_base=0 1063system=system 1064 1065[system.realview.a9scu] 1066type=A9SCU 1067pio_addr=520093696 1068pio_latency=1000 1069system=system 1070pio=system.membus.master[5] 1071 1072[system.realview.aaci_fake] 1073type=AmbaFake 1074amba_id=0 1075ignore_access=false 1076pio_addr=268451840 1077pio_latency=1000 1078system=system 1079pio=system.iobus.master[21] 1080 1081[system.realview.cf_ctrl] 1082type=IdeController 1083BAR0=402653184 1084BAR0LegacyIO=true 1085BAR0Size=16 1086BAR1=402653440 1087BAR1LegacyIO=true 1088BAR1Size=1 1089BAR2=1 1090BAR2LegacyIO=false 1091BAR2Size=8 1092BAR3=1 1093BAR3LegacyIO=false 1094BAR3Size=4 1095BAR4=1 1096BAR4LegacyIO=false 1097BAR4Size=16 1098BAR5=1 1099BAR5LegacyIO=false 1100BAR5Size=0 1101BIST=0 1102CacheLineSize=0 1103CardbusCIS=0 1104ClassCode=1 1105Command=1 1106DeviceID=28945 1107ExpansionROM=0 1108HeaderType=0 1109InterruptLine=31 1110InterruptPin=1 1111LatencyTimer=0 1112MaximumLatency=0 1113MinimumGrant=0 1114ProgIF=133 1115Revision=0 1116Status=640 1117SubClassCode=1 1118SubsystemID=0 1119SubsystemVendorID=0 1120VendorID=32902 1121config_latency=20000 1122ctrl_offset=2 1123disks=system.cf0 1124io_shift=1 1125max_backoff_delay=10000000 1126min_backoff_delay=4000 1127pci_bus=2 1128pci_dev=7 1129pci_func=0 1130pio_latency=1000 1131platform=system.realview 1132system=system 1133config=system.iobus.master[8] 1134dma=system.iobus.slave[2] 1135pio=system.iobus.master[7] 1136 1137[system.realview.clcd] 1138type=Pl111 1139amba_id=1315089 1140clock=41667 1141gic=system.realview.gic 1142int_num=55 1143max_backoff_delay=10000000 1144min_backoff_delay=4000 1145pio_addr=268566528 1146pio_latency=10000 1147system=system 1148vnc=system.vncserver 1149dma=system.iobus.slave[1] 1150pio=system.iobus.master[4] 1151 1152[system.realview.dmac_fake] 1153type=AmbaFake 1154amba_id=0 1155ignore_access=false 1156pio_addr=268632064 1157pio_latency=1000 1158system=system 1159pio=system.iobus.master[9] 1160 1161[system.realview.flash_fake] 1162type=IsaFake 1163fake_mem=true 1164pio_addr=1073741824 1165pio_latency=1000 1166pio_size=536870912 1167ret_bad_addr=false 1168ret_data16=65535 1169ret_data32=4294967295 1170ret_data64=18446744073709551615 1171ret_data8=255 1172system=system 1173update_data=false 1174warn_access= 1175pio=system.iobus.master[24] 1176 1177[system.realview.gic] 1178type=Gic 1179cpu_addr=520093952 1180cpu_pio_delay=10000 1181dist_addr=520097792 1182dist_pio_delay=10000 1183int_latency=10000 1184it_lines=128 1185platform=system.realview 1186system=system 1187pio=system.membus.master[3] 1188 1189[system.realview.gpio0_fake] 1190type=AmbaFake 1191amba_id=0 1192ignore_access=false 1193pio_addr=268513280 1194pio_latency=1000 1195system=system 1196pio=system.iobus.master[16] 1197 1198[system.realview.gpio1_fake] 1199type=AmbaFake 1200amba_id=0 1201ignore_access=false 1202pio_addr=268517376 1203pio_latency=1000 1204system=system 1205pio=system.iobus.master[17] 1206 1207[system.realview.gpio2_fake] 1208type=AmbaFake 1209amba_id=0 1210ignore_access=false 1211pio_addr=268521472 1212pio_latency=1000 1213system=system 1214pio=system.iobus.master[18] 1215 1216[system.realview.kmi0] 1217type=Pl050 1218amba_id=1314896 1219gic=system.realview.gic 1220int_delay=1000000 1221int_num=52 1222is_mouse=false 1223pio_addr=268460032 1224pio_latency=1000 1225system=system 1226vnc=system.vncserver 1227pio=system.iobus.master[5] 1228 1229[system.realview.kmi1] 1230type=Pl050 1231amba_id=1314896 1232gic=system.realview.gic 1233int_delay=1000000 1234int_num=53 1235is_mouse=true 1236pio_addr=268464128 1237pio_latency=1000 1238system=system 1239vnc=system.vncserver 1240pio=system.iobus.master[6] 1241 1242[system.realview.l2x0_fake] 1243type=IsaFake 1244fake_mem=false 1245pio_addr=520101888 1246pio_latency=1000 1247pio_size=4095 1248ret_bad_addr=false 1249ret_data16=65535 1250ret_data32=4294967295 1251ret_data64=18446744073709551615 1252ret_data8=255 1253system=system 1254update_data=false 1255warn_access= 1256pio=system.membus.master[4] 1257 1258[system.realview.local_cpu_timer] 1259type=CpuLocalTimer 1260clock=1000 1261gic=system.realview.gic 1262int_num_timer=29 1263int_num_watchdog=30 1264pio_addr=520095232 1265pio_latency=1000 1266system=system 1267pio=system.membus.master[6] 1268 1269[system.realview.mmc_fake] 1270type=AmbaFake 1271amba_id=0 1272ignore_access=false 1273pio_addr=268455936 1274pio_latency=1000 1275system=system 1276pio=system.iobus.master[22] 1277 1278[system.realview.nvmem] 1279type=SimpleMemory 1280conf_table_reported=false 1281file= 1282in_addr_map=true 1283latency=30000 1284latency_var=0 1285null=false 1286range=2147483648:2214592511 1287zero=true 1288port=system.membus.master[1] 1289 1290[system.realview.realview_io] 1291type=RealViewCtrl 1292idreg=0 1293pio_addr=268435456 1294pio_latency=1000 1295proc_id0=201326592 1296proc_id1=201327138 1297system=system 1298pio=system.iobus.master[1] 1299 1300[system.realview.rtc] 1301type=PL031 1302amba_id=3412017 1303gic=system.realview.gic 1304int_delay=100000 1305int_num=42 1306pio_addr=268529664 1307pio_latency=1000 1308system=system 1309time=Thu Jan 1 00:00:00 2009 1310pio=system.iobus.master[23] 1311 1312[system.realview.sci_fake] 1313type=AmbaFake 1314amba_id=0 1315ignore_access=false 1316pio_addr=268492800 1317pio_latency=1000 1318system=system 1319pio=system.iobus.master[20] 1320 1321[system.realview.smc_fake] 1322type=AmbaFake 1323amba_id=0 1324ignore_access=false 1325pio_addr=269357056 1326pio_latency=1000 1327system=system 1328pio=system.iobus.master[13] 1329 1330[system.realview.sp810_fake] 1331type=AmbaFake 1332amba_id=0 1333ignore_access=true 1334pio_addr=268439552 1335pio_latency=1000 1336system=system 1337pio=system.iobus.master[14] 1338 1339[system.realview.ssp_fake] 1340type=AmbaFake 1341amba_id=0 1342ignore_access=false 1343pio_addr=268488704 1344pio_latency=1000 1345system=system 1346pio=system.iobus.master[19] 1347 1348[system.realview.timer0] 1349type=Sp804 1350amba_id=1316868 1351clock0=1000000 1352clock1=1000000 1353gic=system.realview.gic 1354int_num0=36 1355int_num1=36 1356pio_addr=268505088 1357pio_latency=1000 1358system=system 1359pio=system.iobus.master[2] 1360 1361[system.realview.timer1] 1362type=Sp804 1363amba_id=1316868 1364clock0=1000000 1365clock1=1000000 1366gic=system.realview.gic 1367int_num0=37 1368int_num1=37 1369pio_addr=268509184 1370pio_latency=1000 1371system=system 1372pio=system.iobus.master[3] 1373 1374[system.realview.uart] 1375type=Pl011 1376end_on_eot=false 1377gic=system.realview.gic 1378int_delay=100000 1379int_num=44 1380pio_addr=268472320 1381pio_latency=1000 1382platform=system.realview 1383system=system 1384terminal=system.terminal 1385pio=system.iobus.master[0] 1386 1387[system.realview.uart1_fake] 1388type=AmbaFake 1389amba_id=0 1390ignore_access=false 1391pio_addr=268476416 1392pio_latency=1000 1393system=system 1394pio=system.iobus.master[10] 1395 1396[system.realview.uart2_fake] 1397type=AmbaFake 1398amba_id=0 1399ignore_access=false 1400pio_addr=268480512 1401pio_latency=1000 1402system=system 1403pio=system.iobus.master[11] 1404 1405[system.realview.uart3_fake] 1406type=AmbaFake 1407amba_id=0 1408ignore_access=false 1409pio_addr=268484608 1410pio_latency=1000 1411system=system 1412pio=system.iobus.master[12] 1413 1414[system.realview.watchdog_fake] 1415type=AmbaFake 1416amba_id=0 1417ignore_access=false 1418pio_addr=268500992 1419pio_latency=1000 1420system=system 1421pio=system.iobus.master[15] 1422 1423[system.terminal] 1424type=Terminal 1425intr_control=system.intrctrl 1426number=0 1427output=true 1428port=3456 1429 1430[system.toL2Bus] 1431type=CoherentBus 1432block_size=64 1433clock=1000 1434header_cycles=1 1435use_default_range=false 1436width=64 1437master=system.l2c.cpu_side 1438slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1439 1440[system.vncserver] 1441type=VncServer 1442frame_capture=false 1443number=0 1444port=5900 1445 1446