config.ini revision 10038:7eccd14e2610
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 14atags_addr=256 15boot_loader=/dist/binaries/boot.arm 16boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 17boot_release_addr=65528 18cache_line_size=64 19clk_domain=system.clk_domain 20dtb_filename= 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24flags_addr=268435504 25gic_cpu_addr=520093952 26have_generic_timer=false 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0 33kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 34load_addr_mask=268435455 35load_offset=0 36machine_type=RealView_PBX 37mem_mode=timing 38mem_ranges=0:134217727 39memories=system.physmem system.realview.nvmem 40multi_proc=true 41num_work_ids=16 42panic_on_oops=true 43panic_on_panic=true 44phys_addr_range_64=40 45readfile=tests/halt.sh 46reset_addr_64=0 47symbolfile= 48work_begin_ckpt_count=0 49work_begin_cpu_id_exit=-1 50work_begin_exit_count=0 51work_cpus_ckpt_count=0 52work_end_ckpt_count=0 53work_end_exit_count=0 54work_item_id=-1 55system_port=system.membus.slave[0] 56 57[system.bridge] 58type=Bridge 59clk_domain=system.clk_domain 60delay=50000 61eventq_index=0 62ranges=268435456:520093695 1073741824:1610612735 63req_size=16 64resp_size=16 65master=system.iobus.slave[0] 66slave=system.membus.master[0] 67 68[system.cf0] 69type=IdeDisk 70children=image 71delay=1000000 72driveID=master 73eventq_index=0 74image=system.cf0.image 75 76[system.cf0.image] 77type=CowDiskImage 78children=child 79child=system.cf0.image.child 80eventq_index=0 81image_file= 82read_only=false 83table_size=65536 84 85[system.cf0.image.child] 86type=RawDiskImage 87eventq_index=0 88image_file=/dist/disks/linux-arm-ael.img 89read_only=true 90 91[system.clk_domain] 92type=SrcClockDomain 93clock=1000 94eventq_index=0 95voltage_domain=system.voltage_domain 96 97[system.cpu0] 98type=DerivO3CPU 99children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer 100LFSTSize=1024 101LQEntries=32 102LSQCheckLoads=true 103LSQDepCheckShift=4 104SQEntries=32 105SSITSize=1024 106activity=0 107backComSize=5 108branchPred=system.cpu0.branchPred 109cachePorts=200 110checker=Null 111clk_domain=system.cpu_clk_domain 112commitToDecodeDelay=1 113commitToFetchDelay=1 114commitToIEWDelay=1 115commitToRenameDelay=1 116commitWidth=8 117cpu_id=0 118decodeToFetchDelay=1 119decodeToRenameDelay=1 120decodeWidth=8 121dispatchWidth=8 122do_checkpoint_insts=true 123do_quiesce=true 124do_statistics_insts=true 125dstage2_mmu=system.cpu0.dstage2_mmu 126dtb=system.cpu0.dtb 127eventq_index=0 128fetchBufferSize=64 129fetchToDecodeDelay=1 130fetchTrapLatency=1 131fetchWidth=8 132forwardComSize=5 133fuPool=system.cpu0.fuPool 134function_trace=false 135function_trace_start=0 136iewToCommitDelay=1 137iewToDecodeDelay=1 138iewToFetchDelay=1 139iewToRenameDelay=1 140interrupts=system.cpu0.interrupts 141isa=system.cpu0.isa 142issueToExecuteDelay=1 143issueWidth=8 144istage2_mmu=system.cpu0.istage2_mmu 145itb=system.cpu0.itb 146max_insts_all_threads=0 147max_insts_any_thread=0 148max_loads_all_threads=0 149max_loads_any_thread=0 150needsTSO=false 151numIQEntries=64 152numPhysCCRegs=0 153numPhysFloatRegs=256 154numPhysIntRegs=256 155numROBEntries=192 156numRobs=1 157numThreads=1 158profile=0 159progress_interval=0 160renameToDecodeDelay=1 161renameToFetchDelay=1 162renameToIEWDelay=2 163renameToROBDelay=1 164renameWidth=8 165simpoint_start_insts= 166smtCommitPolicy=RoundRobin 167smtFetchPolicy=SingleThread 168smtIQPolicy=Partitioned 169smtIQThreshold=100 170smtLSQPolicy=Partitioned 171smtLSQThreshold=100 172smtNumFetchingThreads=1 173smtROBPolicy=Partitioned 174smtROBThreshold=100 175squashWidth=8 176store_set_clear_period=250000 177switched_out=false 178system=system 179tracer=system.cpu0.tracer 180trapLatency=13 181wbDepth=1 182wbWidth=8 183workload= 184dcache_port=system.cpu0.dcache.cpu_side 185icache_port=system.cpu0.icache.cpu_side 186 187[system.cpu0.branchPred] 188type=BranchPredictor 189BTBEntries=4096 190BTBTagSize=16 191RASSize=16 192choiceCtrBits=2 193choicePredictorSize=8192 194eventq_index=0 195globalCtrBits=2 196globalPredictorSize=8192 197instShiftAmt=2 198localCtrBits=2 199localHistoryTableSize=2048 200localPredictorSize=2048 201numThreads=1 202predType=tournament 203 204[system.cpu0.dcache] 205type=BaseCache 206children=tags 207addr_ranges=0:18446744073709551615 208assoc=4 209clk_domain=system.cpu_clk_domain 210eventq_index=0 211forward_snoops=true 212hit_latency=2 213is_top_level=true 214max_miss_count=0 215mshrs=4 216prefetch_on_access=false 217prefetcher=Null 218response_latency=2 219sequential_access=false 220size=32768 221system=system 222tags=system.cpu0.dcache.tags 223tgts_per_mshr=20 224two_queue=false 225write_buffers=8 226cpu_side=system.cpu0.dcache_port 227mem_side=system.toL2Bus.slave[1] 228 229[system.cpu0.dcache.tags] 230type=LRU 231assoc=4 232block_size=64 233clk_domain=system.cpu_clk_domain 234eventq_index=0 235hit_latency=2 236sequential_access=false 237size=32768 238 239[system.cpu0.dstage2_mmu] 240type=ArmStage2MMU 241children=stage2_tlb 242eventq_index=0 243stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb 244tlb=system.cpu0.dtb 245 246[system.cpu0.dstage2_mmu.stage2_tlb] 247type=ArmTLB 248children=walker 249eventq_index=0 250is_stage2=true 251size=32 252walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 253 254[system.cpu0.dstage2_mmu.stage2_tlb.walker] 255type=ArmTableWalker 256clk_domain=system.cpu_clk_domain 257eventq_index=0 258is_stage2=true 259num_squash_per_cycle=2 260sys=system 261port=system.toL2Bus.slave[5] 262 263[system.cpu0.dtb] 264type=ArmTLB 265children=walker 266eventq_index=0 267is_stage2=false 268size=64 269walker=system.cpu0.dtb.walker 270 271[system.cpu0.dtb.walker] 272type=ArmTableWalker 273clk_domain=system.cpu_clk_domain 274eventq_index=0 275is_stage2=false 276num_squash_per_cycle=2 277sys=system 278port=system.toL2Bus.slave[3] 279 280[system.cpu0.fuPool] 281type=FUPool 282children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 283FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 284eventq_index=0 285 286[system.cpu0.fuPool.FUList0] 287type=FUDesc 288children=opList 289count=6 290eventq_index=0 291opList=system.cpu0.fuPool.FUList0.opList 292 293[system.cpu0.fuPool.FUList0.opList] 294type=OpDesc 295eventq_index=0 296issueLat=1 297opClass=IntAlu 298opLat=1 299 300[system.cpu0.fuPool.FUList1] 301type=FUDesc 302children=opList0 opList1 303count=2 304eventq_index=0 305opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 306 307[system.cpu0.fuPool.FUList1.opList0] 308type=OpDesc 309eventq_index=0 310issueLat=1 311opClass=IntMult 312opLat=3 313 314[system.cpu0.fuPool.FUList1.opList1] 315type=OpDesc 316eventq_index=0 317issueLat=19 318opClass=IntDiv 319opLat=20 320 321[system.cpu0.fuPool.FUList2] 322type=FUDesc 323children=opList0 opList1 opList2 324count=4 325eventq_index=0 326opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 327 328[system.cpu0.fuPool.FUList2.opList0] 329type=OpDesc 330eventq_index=0 331issueLat=1 332opClass=FloatAdd 333opLat=2 334 335[system.cpu0.fuPool.FUList2.opList1] 336type=OpDesc 337eventq_index=0 338issueLat=1 339opClass=FloatCmp 340opLat=2 341 342[system.cpu0.fuPool.FUList2.opList2] 343type=OpDesc 344eventq_index=0 345issueLat=1 346opClass=FloatCvt 347opLat=2 348 349[system.cpu0.fuPool.FUList3] 350type=FUDesc 351children=opList0 opList1 opList2 352count=2 353eventq_index=0 354opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 355 356[system.cpu0.fuPool.FUList3.opList0] 357type=OpDesc 358eventq_index=0 359issueLat=1 360opClass=FloatMult 361opLat=4 362 363[system.cpu0.fuPool.FUList3.opList1] 364type=OpDesc 365eventq_index=0 366issueLat=12 367opClass=FloatDiv 368opLat=12 369 370[system.cpu0.fuPool.FUList3.opList2] 371type=OpDesc 372eventq_index=0 373issueLat=24 374opClass=FloatSqrt 375opLat=24 376 377[system.cpu0.fuPool.FUList4] 378type=FUDesc 379children=opList 380count=0 381eventq_index=0 382opList=system.cpu0.fuPool.FUList4.opList 383 384[system.cpu0.fuPool.FUList4.opList] 385type=OpDesc 386eventq_index=0 387issueLat=1 388opClass=MemRead 389opLat=1 390 391[system.cpu0.fuPool.FUList5] 392type=FUDesc 393children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 394count=4 395eventq_index=0 396opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 397 398[system.cpu0.fuPool.FUList5.opList00] 399type=OpDesc 400eventq_index=0 401issueLat=1 402opClass=SimdAdd 403opLat=1 404 405[system.cpu0.fuPool.FUList5.opList01] 406type=OpDesc 407eventq_index=0 408issueLat=1 409opClass=SimdAddAcc 410opLat=1 411 412[system.cpu0.fuPool.FUList5.opList02] 413type=OpDesc 414eventq_index=0 415issueLat=1 416opClass=SimdAlu 417opLat=1 418 419[system.cpu0.fuPool.FUList5.opList03] 420type=OpDesc 421eventq_index=0 422issueLat=1 423opClass=SimdCmp 424opLat=1 425 426[system.cpu0.fuPool.FUList5.opList04] 427type=OpDesc 428eventq_index=0 429issueLat=1 430opClass=SimdCvt 431opLat=1 432 433[system.cpu0.fuPool.FUList5.opList05] 434type=OpDesc 435eventq_index=0 436issueLat=1 437opClass=SimdMisc 438opLat=1 439 440[system.cpu0.fuPool.FUList5.opList06] 441type=OpDesc 442eventq_index=0 443issueLat=1 444opClass=SimdMult 445opLat=1 446 447[system.cpu0.fuPool.FUList5.opList07] 448type=OpDesc 449eventq_index=0 450issueLat=1 451opClass=SimdMultAcc 452opLat=1 453 454[system.cpu0.fuPool.FUList5.opList08] 455type=OpDesc 456eventq_index=0 457issueLat=1 458opClass=SimdShift 459opLat=1 460 461[system.cpu0.fuPool.FUList5.opList09] 462type=OpDesc 463eventq_index=0 464issueLat=1 465opClass=SimdShiftAcc 466opLat=1 467 468[system.cpu0.fuPool.FUList5.opList10] 469type=OpDesc 470eventq_index=0 471issueLat=1 472opClass=SimdSqrt 473opLat=1 474 475[system.cpu0.fuPool.FUList5.opList11] 476type=OpDesc 477eventq_index=0 478issueLat=1 479opClass=SimdFloatAdd 480opLat=1 481 482[system.cpu0.fuPool.FUList5.opList12] 483type=OpDesc 484eventq_index=0 485issueLat=1 486opClass=SimdFloatAlu 487opLat=1 488 489[system.cpu0.fuPool.FUList5.opList13] 490type=OpDesc 491eventq_index=0 492issueLat=1 493opClass=SimdFloatCmp 494opLat=1 495 496[system.cpu0.fuPool.FUList5.opList14] 497type=OpDesc 498eventq_index=0 499issueLat=1 500opClass=SimdFloatCvt 501opLat=1 502 503[system.cpu0.fuPool.FUList5.opList15] 504type=OpDesc 505eventq_index=0 506issueLat=1 507opClass=SimdFloatDiv 508opLat=1 509 510[system.cpu0.fuPool.FUList5.opList16] 511type=OpDesc 512eventq_index=0 513issueLat=1 514opClass=SimdFloatMisc 515opLat=1 516 517[system.cpu0.fuPool.FUList5.opList17] 518type=OpDesc 519eventq_index=0 520issueLat=1 521opClass=SimdFloatMult 522opLat=1 523 524[system.cpu0.fuPool.FUList5.opList18] 525type=OpDesc 526eventq_index=0 527issueLat=1 528opClass=SimdFloatMultAcc 529opLat=1 530 531[system.cpu0.fuPool.FUList5.opList19] 532type=OpDesc 533eventq_index=0 534issueLat=1 535opClass=SimdFloatSqrt 536opLat=1 537 538[system.cpu0.fuPool.FUList6] 539type=FUDesc 540children=opList 541count=0 542eventq_index=0 543opList=system.cpu0.fuPool.FUList6.opList 544 545[system.cpu0.fuPool.FUList6.opList] 546type=OpDesc 547eventq_index=0 548issueLat=1 549opClass=MemWrite 550opLat=1 551 552[system.cpu0.fuPool.FUList7] 553type=FUDesc 554children=opList0 opList1 555count=4 556eventq_index=0 557opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 558 559[system.cpu0.fuPool.FUList7.opList0] 560type=OpDesc 561eventq_index=0 562issueLat=1 563opClass=MemRead 564opLat=1 565 566[system.cpu0.fuPool.FUList7.opList1] 567type=OpDesc 568eventq_index=0 569issueLat=1 570opClass=MemWrite 571opLat=1 572 573[system.cpu0.fuPool.FUList8] 574type=FUDesc 575children=opList 576count=1 577eventq_index=0 578opList=system.cpu0.fuPool.FUList8.opList 579 580[system.cpu0.fuPool.FUList8.opList] 581type=OpDesc 582eventq_index=0 583issueLat=3 584opClass=IprAccess 585opLat=3 586 587[system.cpu0.icache] 588type=BaseCache 589children=tags 590addr_ranges=0:18446744073709551615 591assoc=1 592clk_domain=system.cpu_clk_domain 593eventq_index=0 594forward_snoops=true 595hit_latency=2 596is_top_level=true 597max_miss_count=0 598mshrs=4 599prefetch_on_access=false 600prefetcher=Null 601response_latency=2 602sequential_access=false 603size=32768 604system=system 605tags=system.cpu0.icache.tags 606tgts_per_mshr=20 607two_queue=false 608write_buffers=8 609cpu_side=system.cpu0.icache_port 610mem_side=system.toL2Bus.slave[0] 611 612[system.cpu0.icache.tags] 613type=LRU 614assoc=1 615block_size=64 616clk_domain=system.cpu_clk_domain 617eventq_index=0 618hit_latency=2 619sequential_access=false 620size=32768 621 622[system.cpu0.interrupts] 623type=ArmInterrupts 624eventq_index=0 625 626[system.cpu0.isa] 627type=ArmISA 628eventq_index=0 629fpsid=1090793632 630id_aa64afr0_el1=0 631id_aa64afr1_el1=0 632id_aa64dfr0_el1=1052678 633id_aa64dfr1_el1=0 634id_aa64isar0_el1=0 635id_aa64isar1_el1=0 636id_aa64mmfr0_el1=15728642 637id_aa64mmfr1_el1=0 638id_aa64pfr0_el1=17 639id_aa64pfr1_el1=0 640id_isar0=34607377 641id_isar1=34677009 642id_isar2=555950401 643id_isar3=17899825 644id_isar4=268501314 645id_isar5=0 646id_mmfr0=270536963 647id_mmfr1=0 648id_mmfr2=19070976 649id_mmfr3=34611729 650id_pfr0=49 651id_pfr1=4113 652midr=1091551472 653system=system 654 655[system.cpu0.istage2_mmu] 656type=ArmStage2MMU 657children=stage2_tlb 658eventq_index=0 659stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb 660tlb=system.cpu0.itb 661 662[system.cpu0.istage2_mmu.stage2_tlb] 663type=ArmTLB 664children=walker 665eventq_index=0 666is_stage2=true 667size=32 668walker=system.cpu0.istage2_mmu.stage2_tlb.walker 669 670[system.cpu0.istage2_mmu.stage2_tlb.walker] 671type=ArmTableWalker 672clk_domain=system.cpu_clk_domain 673eventq_index=0 674is_stage2=true 675num_squash_per_cycle=2 676sys=system 677port=system.toL2Bus.slave[4] 678 679[system.cpu0.itb] 680type=ArmTLB 681children=walker 682eventq_index=0 683is_stage2=false 684size=64 685walker=system.cpu0.itb.walker 686 687[system.cpu0.itb.walker] 688type=ArmTableWalker 689clk_domain=system.cpu_clk_domain 690eventq_index=0 691is_stage2=false 692num_squash_per_cycle=2 693sys=system 694port=system.toL2Bus.slave[2] 695 696[system.cpu0.tracer] 697type=ExeTracer 698eventq_index=0 699 700[system.cpu1] 701type=DerivO3CPU 702children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer 703LFSTSize=1024 704LQEntries=32 705LSQCheckLoads=true 706LSQDepCheckShift=4 707SQEntries=32 708SSITSize=1024 709activity=0 710backComSize=5 711branchPred=system.cpu1.branchPred 712cachePorts=200 713checker=Null 714clk_domain=system.cpu_clk_domain 715commitToDecodeDelay=1 716commitToFetchDelay=1 717commitToIEWDelay=1 718commitToRenameDelay=1 719commitWidth=8 720cpu_id=1 721decodeToFetchDelay=1 722decodeToRenameDelay=1 723decodeWidth=8 724dispatchWidth=8 725do_checkpoint_insts=true 726do_quiesce=true 727do_statistics_insts=true 728dstage2_mmu=system.cpu1.dstage2_mmu 729dtb=system.cpu1.dtb 730eventq_index=0 731fetchBufferSize=64 732fetchToDecodeDelay=1 733fetchTrapLatency=1 734fetchWidth=8 735forwardComSize=5 736fuPool=system.cpu1.fuPool 737function_trace=false 738function_trace_start=0 739iewToCommitDelay=1 740iewToDecodeDelay=1 741iewToFetchDelay=1 742iewToRenameDelay=1 743interrupts=system.cpu1.interrupts 744isa=system.cpu1.isa 745issueToExecuteDelay=1 746issueWidth=8 747istage2_mmu=system.cpu1.istage2_mmu 748itb=system.cpu1.itb 749max_insts_all_threads=0 750max_insts_any_thread=0 751max_loads_all_threads=0 752max_loads_any_thread=0 753needsTSO=false 754numIQEntries=64 755numPhysCCRegs=0 756numPhysFloatRegs=256 757numPhysIntRegs=256 758numROBEntries=192 759numRobs=1 760numThreads=1 761profile=0 762progress_interval=0 763renameToDecodeDelay=1 764renameToFetchDelay=1 765renameToIEWDelay=2 766renameToROBDelay=1 767renameWidth=8 768simpoint_start_insts= 769smtCommitPolicy=RoundRobin 770smtFetchPolicy=SingleThread 771smtIQPolicy=Partitioned 772smtIQThreshold=100 773smtLSQPolicy=Partitioned 774smtLSQThreshold=100 775smtNumFetchingThreads=1 776smtROBPolicy=Partitioned 777smtROBThreshold=100 778squashWidth=8 779store_set_clear_period=250000 780switched_out=false 781system=system 782tracer=system.cpu1.tracer 783trapLatency=13 784wbDepth=1 785wbWidth=8 786workload= 787dcache_port=system.cpu1.dcache.cpu_side 788icache_port=system.cpu1.icache.cpu_side 789 790[system.cpu1.branchPred] 791type=BranchPredictor 792BTBEntries=4096 793BTBTagSize=16 794RASSize=16 795choiceCtrBits=2 796choicePredictorSize=8192 797eventq_index=0 798globalCtrBits=2 799globalPredictorSize=8192 800instShiftAmt=2 801localCtrBits=2 802localHistoryTableSize=2048 803localPredictorSize=2048 804numThreads=1 805predType=tournament 806 807[system.cpu1.dcache] 808type=BaseCache 809children=tags 810addr_ranges=0:18446744073709551615 811assoc=4 812clk_domain=system.cpu_clk_domain 813eventq_index=0 814forward_snoops=true 815hit_latency=2 816is_top_level=true 817max_miss_count=0 818mshrs=4 819prefetch_on_access=false 820prefetcher=Null 821response_latency=2 822sequential_access=false 823size=32768 824system=system 825tags=system.cpu1.dcache.tags 826tgts_per_mshr=20 827two_queue=false 828write_buffers=8 829cpu_side=system.cpu1.dcache_port 830mem_side=system.toL2Bus.slave[7] 831 832[system.cpu1.dcache.tags] 833type=LRU 834assoc=4 835block_size=64 836clk_domain=system.cpu_clk_domain 837eventq_index=0 838hit_latency=2 839sequential_access=false 840size=32768 841 842[system.cpu1.dstage2_mmu] 843type=ArmStage2MMU 844children=stage2_tlb 845eventq_index=0 846stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb 847tlb=system.cpu1.dtb 848 849[system.cpu1.dstage2_mmu.stage2_tlb] 850type=ArmTLB 851children=walker 852eventq_index=0 853is_stage2=true 854size=32 855walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 856 857[system.cpu1.dstage2_mmu.stage2_tlb.walker] 858type=ArmTableWalker 859clk_domain=system.cpu_clk_domain 860eventq_index=0 861is_stage2=true 862num_squash_per_cycle=2 863sys=system 864port=system.toL2Bus.slave[11] 865 866[system.cpu1.dtb] 867type=ArmTLB 868children=walker 869eventq_index=0 870is_stage2=false 871size=64 872walker=system.cpu1.dtb.walker 873 874[system.cpu1.dtb.walker] 875type=ArmTableWalker 876clk_domain=system.cpu_clk_domain 877eventq_index=0 878is_stage2=false 879num_squash_per_cycle=2 880sys=system 881port=system.toL2Bus.slave[9] 882 883[system.cpu1.fuPool] 884type=FUPool 885children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 886FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 887eventq_index=0 888 889[system.cpu1.fuPool.FUList0] 890type=FUDesc 891children=opList 892count=6 893eventq_index=0 894opList=system.cpu1.fuPool.FUList0.opList 895 896[system.cpu1.fuPool.FUList0.opList] 897type=OpDesc 898eventq_index=0 899issueLat=1 900opClass=IntAlu 901opLat=1 902 903[system.cpu1.fuPool.FUList1] 904type=FUDesc 905children=opList0 opList1 906count=2 907eventq_index=0 908opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 909 910[system.cpu1.fuPool.FUList1.opList0] 911type=OpDesc 912eventq_index=0 913issueLat=1 914opClass=IntMult 915opLat=3 916 917[system.cpu1.fuPool.FUList1.opList1] 918type=OpDesc 919eventq_index=0 920issueLat=19 921opClass=IntDiv 922opLat=20 923 924[system.cpu1.fuPool.FUList2] 925type=FUDesc 926children=opList0 opList1 opList2 927count=4 928eventq_index=0 929opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 930 931[system.cpu1.fuPool.FUList2.opList0] 932type=OpDesc 933eventq_index=0 934issueLat=1 935opClass=FloatAdd 936opLat=2 937 938[system.cpu1.fuPool.FUList2.opList1] 939type=OpDesc 940eventq_index=0 941issueLat=1 942opClass=FloatCmp 943opLat=2 944 945[system.cpu1.fuPool.FUList2.opList2] 946type=OpDesc 947eventq_index=0 948issueLat=1 949opClass=FloatCvt 950opLat=2 951 952[system.cpu1.fuPool.FUList3] 953type=FUDesc 954children=opList0 opList1 opList2 955count=2 956eventq_index=0 957opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 958 959[system.cpu1.fuPool.FUList3.opList0] 960type=OpDesc 961eventq_index=0 962issueLat=1 963opClass=FloatMult 964opLat=4 965 966[system.cpu1.fuPool.FUList3.opList1] 967type=OpDesc 968eventq_index=0 969issueLat=12 970opClass=FloatDiv 971opLat=12 972 973[system.cpu1.fuPool.FUList3.opList2] 974type=OpDesc 975eventq_index=0 976issueLat=24 977opClass=FloatSqrt 978opLat=24 979 980[system.cpu1.fuPool.FUList4] 981type=FUDesc 982children=opList 983count=0 984eventq_index=0 985opList=system.cpu1.fuPool.FUList4.opList 986 987[system.cpu1.fuPool.FUList4.opList] 988type=OpDesc 989eventq_index=0 990issueLat=1 991opClass=MemRead 992opLat=1 993 994[system.cpu1.fuPool.FUList5] 995type=FUDesc 996children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 997count=4 998eventq_index=0 999opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 1000 1001[system.cpu1.fuPool.FUList5.opList00] 1002type=OpDesc 1003eventq_index=0 1004issueLat=1 1005opClass=SimdAdd 1006opLat=1 1007 1008[system.cpu1.fuPool.FUList5.opList01] 1009type=OpDesc 1010eventq_index=0 1011issueLat=1 1012opClass=SimdAddAcc 1013opLat=1 1014 1015[system.cpu1.fuPool.FUList5.opList02] 1016type=OpDesc 1017eventq_index=0 1018issueLat=1 1019opClass=SimdAlu 1020opLat=1 1021 1022[system.cpu1.fuPool.FUList5.opList03] 1023type=OpDesc 1024eventq_index=0 1025issueLat=1 1026opClass=SimdCmp 1027opLat=1 1028 1029[system.cpu1.fuPool.FUList5.opList04] 1030type=OpDesc 1031eventq_index=0 1032issueLat=1 1033opClass=SimdCvt 1034opLat=1 1035 1036[system.cpu1.fuPool.FUList5.opList05] 1037type=OpDesc 1038eventq_index=0 1039issueLat=1 1040opClass=SimdMisc 1041opLat=1 1042 1043[system.cpu1.fuPool.FUList5.opList06] 1044type=OpDesc 1045eventq_index=0 1046issueLat=1 1047opClass=SimdMult 1048opLat=1 1049 1050[system.cpu1.fuPool.FUList5.opList07] 1051type=OpDesc 1052eventq_index=0 1053issueLat=1 1054opClass=SimdMultAcc 1055opLat=1 1056 1057[system.cpu1.fuPool.FUList5.opList08] 1058type=OpDesc 1059eventq_index=0 1060issueLat=1 1061opClass=SimdShift 1062opLat=1 1063 1064[system.cpu1.fuPool.FUList5.opList09] 1065type=OpDesc 1066eventq_index=0 1067issueLat=1 1068opClass=SimdShiftAcc 1069opLat=1 1070 1071[system.cpu1.fuPool.FUList5.opList10] 1072type=OpDesc 1073eventq_index=0 1074issueLat=1 1075opClass=SimdSqrt 1076opLat=1 1077 1078[system.cpu1.fuPool.FUList5.opList11] 1079type=OpDesc 1080eventq_index=0 1081issueLat=1 1082opClass=SimdFloatAdd 1083opLat=1 1084 1085[system.cpu1.fuPool.FUList5.opList12] 1086type=OpDesc 1087eventq_index=0 1088issueLat=1 1089opClass=SimdFloatAlu 1090opLat=1 1091 1092[system.cpu1.fuPool.FUList5.opList13] 1093type=OpDesc 1094eventq_index=0 1095issueLat=1 1096opClass=SimdFloatCmp 1097opLat=1 1098 1099[system.cpu1.fuPool.FUList5.opList14] 1100type=OpDesc 1101eventq_index=0 1102issueLat=1 1103opClass=SimdFloatCvt 1104opLat=1 1105 1106[system.cpu1.fuPool.FUList5.opList15] 1107type=OpDesc 1108eventq_index=0 1109issueLat=1 1110opClass=SimdFloatDiv 1111opLat=1 1112 1113[system.cpu1.fuPool.FUList5.opList16] 1114type=OpDesc 1115eventq_index=0 1116issueLat=1 1117opClass=SimdFloatMisc 1118opLat=1 1119 1120[system.cpu1.fuPool.FUList5.opList17] 1121type=OpDesc 1122eventq_index=0 1123issueLat=1 1124opClass=SimdFloatMult 1125opLat=1 1126 1127[system.cpu1.fuPool.FUList5.opList18] 1128type=OpDesc 1129eventq_index=0 1130issueLat=1 1131opClass=SimdFloatMultAcc 1132opLat=1 1133 1134[system.cpu1.fuPool.FUList5.opList19] 1135type=OpDesc 1136eventq_index=0 1137issueLat=1 1138opClass=SimdFloatSqrt 1139opLat=1 1140 1141[system.cpu1.fuPool.FUList6] 1142type=FUDesc 1143children=opList 1144count=0 1145eventq_index=0 1146opList=system.cpu1.fuPool.FUList6.opList 1147 1148[system.cpu1.fuPool.FUList6.opList] 1149type=OpDesc 1150eventq_index=0 1151issueLat=1 1152opClass=MemWrite 1153opLat=1 1154 1155[system.cpu1.fuPool.FUList7] 1156type=FUDesc 1157children=opList0 opList1 1158count=4 1159eventq_index=0 1160opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1161 1162[system.cpu1.fuPool.FUList7.opList0] 1163type=OpDesc 1164eventq_index=0 1165issueLat=1 1166opClass=MemRead 1167opLat=1 1168 1169[system.cpu1.fuPool.FUList7.opList1] 1170type=OpDesc 1171eventq_index=0 1172issueLat=1 1173opClass=MemWrite 1174opLat=1 1175 1176[system.cpu1.fuPool.FUList8] 1177type=FUDesc 1178children=opList 1179count=1 1180eventq_index=0 1181opList=system.cpu1.fuPool.FUList8.opList 1182 1183[system.cpu1.fuPool.FUList8.opList] 1184type=OpDesc 1185eventq_index=0 1186issueLat=3 1187opClass=IprAccess 1188opLat=3 1189 1190[system.cpu1.icache] 1191type=BaseCache 1192children=tags 1193addr_ranges=0:18446744073709551615 1194assoc=1 1195clk_domain=system.cpu_clk_domain 1196eventq_index=0 1197forward_snoops=true 1198hit_latency=2 1199is_top_level=true 1200max_miss_count=0 1201mshrs=4 1202prefetch_on_access=false 1203prefetcher=Null 1204response_latency=2 1205sequential_access=false 1206size=32768 1207system=system 1208tags=system.cpu1.icache.tags 1209tgts_per_mshr=20 1210two_queue=false 1211write_buffers=8 1212cpu_side=system.cpu1.icache_port 1213mem_side=system.toL2Bus.slave[6] 1214 1215[system.cpu1.icache.tags] 1216type=LRU 1217assoc=1 1218block_size=64 1219clk_domain=system.cpu_clk_domain 1220eventq_index=0 1221hit_latency=2 1222sequential_access=false 1223size=32768 1224 1225[system.cpu1.interrupts] 1226type=ArmInterrupts 1227eventq_index=0 1228 1229[system.cpu1.isa] 1230type=ArmISA 1231eventq_index=0 1232fpsid=1090793632 1233id_aa64afr0_el1=0 1234id_aa64afr1_el1=0 1235id_aa64dfr0_el1=1052678 1236id_aa64dfr1_el1=0 1237id_aa64isar0_el1=0 1238id_aa64isar1_el1=0 1239id_aa64mmfr0_el1=15728642 1240id_aa64mmfr1_el1=0 1241id_aa64pfr0_el1=17 1242id_aa64pfr1_el1=0 1243id_isar0=34607377 1244id_isar1=34677009 1245id_isar2=555950401 1246id_isar3=17899825 1247id_isar4=268501314 1248id_isar5=0 1249id_mmfr0=270536963 1250id_mmfr1=0 1251id_mmfr2=19070976 1252id_mmfr3=34611729 1253id_pfr0=49 1254id_pfr1=4113 1255midr=1091551472 1256system=system 1257 1258[system.cpu1.istage2_mmu] 1259type=ArmStage2MMU 1260children=stage2_tlb 1261eventq_index=0 1262stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb 1263tlb=system.cpu1.itb 1264 1265[system.cpu1.istage2_mmu.stage2_tlb] 1266type=ArmTLB 1267children=walker 1268eventq_index=0 1269is_stage2=true 1270size=32 1271walker=system.cpu1.istage2_mmu.stage2_tlb.walker 1272 1273[system.cpu1.istage2_mmu.stage2_tlb.walker] 1274type=ArmTableWalker 1275clk_domain=system.cpu_clk_domain 1276eventq_index=0 1277is_stage2=true 1278num_squash_per_cycle=2 1279sys=system 1280port=system.toL2Bus.slave[10] 1281 1282[system.cpu1.itb] 1283type=ArmTLB 1284children=walker 1285eventq_index=0 1286is_stage2=false 1287size=64 1288walker=system.cpu1.itb.walker 1289 1290[system.cpu1.itb.walker] 1291type=ArmTableWalker 1292clk_domain=system.cpu_clk_domain 1293eventq_index=0 1294is_stage2=false 1295num_squash_per_cycle=2 1296sys=system 1297port=system.toL2Bus.slave[8] 1298 1299[system.cpu1.tracer] 1300type=ExeTracer 1301eventq_index=0 1302 1303[system.cpu_clk_domain] 1304type=SrcClockDomain 1305clock=500 1306eventq_index=0 1307voltage_domain=system.voltage_domain 1308 1309[system.intrctrl] 1310type=IntrControl 1311eventq_index=0 1312sys=system 1313 1314[system.iobus] 1315type=NoncoherentBus 1316clk_domain=system.clk_domain 1317eventq_index=0 1318header_cycles=1 1319use_default_range=false 1320width=8 1321master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 1322slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1323 1324[system.iocache] 1325type=BaseCache 1326children=tags 1327addr_ranges=0:134217727 1328assoc=8 1329clk_domain=system.clk_domain 1330eventq_index=0 1331forward_snoops=false 1332hit_latency=50 1333is_top_level=true 1334max_miss_count=0 1335mshrs=20 1336prefetch_on_access=false 1337prefetcher=Null 1338response_latency=50 1339sequential_access=false 1340size=1024 1341system=system 1342tags=system.iocache.tags 1343tgts_per_mshr=12 1344two_queue=false 1345write_buffers=8 1346cpu_side=system.iobus.master[25] 1347mem_side=system.membus.slave[2] 1348 1349[system.iocache.tags] 1350type=LRU 1351assoc=8 1352block_size=64 1353clk_domain=system.clk_domain 1354eventq_index=0 1355hit_latency=50 1356sequential_access=false 1357size=1024 1358 1359[system.l2c] 1360type=BaseCache 1361children=tags 1362addr_ranges=0:18446744073709551615 1363assoc=8 1364clk_domain=system.cpu_clk_domain 1365eventq_index=0 1366forward_snoops=true 1367hit_latency=20 1368is_top_level=false 1369max_miss_count=0 1370mshrs=20 1371prefetch_on_access=false 1372prefetcher=Null 1373response_latency=20 1374sequential_access=false 1375size=4194304 1376system=system 1377tags=system.l2c.tags 1378tgts_per_mshr=12 1379two_queue=false 1380write_buffers=8 1381cpu_side=system.toL2Bus.master[0] 1382mem_side=system.membus.slave[1] 1383 1384[system.l2c.tags] 1385type=LRU 1386assoc=8 1387block_size=64 1388clk_domain=system.cpu_clk_domain 1389eventq_index=0 1390hit_latency=20 1391sequential_access=false 1392size=4194304 1393 1394[system.membus] 1395type=CoherentBus 1396children=badaddr_responder 1397clk_domain=system.clk_domain 1398eventq_index=0 1399header_cycles=1 1400system=system 1401use_default_range=false 1402width=8 1403default=system.membus.badaddr_responder.pio 1404master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port 1405slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1406 1407[system.membus.badaddr_responder] 1408type=IsaFake 1409clk_domain=system.clk_domain 1410eventq_index=0 1411fake_mem=false 1412pio_addr=0 1413pio_latency=100000 1414pio_size=8 1415ret_bad_addr=true 1416ret_data16=65535 1417ret_data32=4294967295 1418ret_data64=18446744073709551615 1419ret_data8=255 1420system=system 1421update_data=false 1422warn_access=warn 1423pio=system.membus.default 1424 1425[system.physmem] 1426type=SimpleDRAM 1427activation_limit=4 1428addr_mapping=RaBaChCo 1429banks_per_rank=8 1430burst_length=8 1431channels=1 1432clk_domain=system.clk_domain 1433conf_table_reported=true 1434device_bus_width=8 1435device_rowbuffer_size=1024 1436devices_per_rank=8 1437eventq_index=0 1438in_addr_map=true 1439mem_sched_policy=frfcfs 1440null=false 1441page_policy=open 1442range=0:134217727 1443ranks_per_channel=2 1444read_buffer_size=32 1445static_backend_latency=10000 1446static_frontend_latency=10000 1447tBURST=5000 1448tCL=13750 1449tRAS=35000 1450tRCD=13750 1451tREFI=7800000 1452tRFC=300000 1453tRP=13750 1454tRRD=6250 1455tWTR=7500 1456tXAW=40000 1457write_buffer_size=32 1458write_high_thresh_perc=70 1459write_low_thresh_perc=0 1460port=system.membus.master[6] 1461 1462[system.realview] 1463type=RealView 1464children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1465eventq_index=0 1466intrctrl=system.intrctrl 1467max_mem_size=268435456 1468mem_start_addr=0 1469pci_cfg_base=0 1470system=system 1471 1472[system.realview.a9scu] 1473type=A9SCU 1474clk_domain=system.clk_domain 1475eventq_index=0 1476pio_addr=520093696 1477pio_latency=100000 1478system=system 1479pio=system.membus.master[4] 1480 1481[system.realview.aaci_fake] 1482type=AmbaFake 1483amba_id=0 1484clk_domain=system.clk_domain 1485eventq_index=0 1486ignore_access=false 1487pio_addr=268451840 1488pio_latency=100000 1489system=system 1490pio=system.iobus.master[21] 1491 1492[system.realview.cf_ctrl] 1493type=IdeController 1494BAR0=402653184 1495BAR0LegacyIO=true 1496BAR0Size=16 1497BAR1=402653440 1498BAR1LegacyIO=true 1499BAR1Size=1 1500BAR2=1 1501BAR2LegacyIO=false 1502BAR2Size=8 1503BAR3=1 1504BAR3LegacyIO=false 1505BAR3Size=4 1506BAR4=1 1507BAR4LegacyIO=false 1508BAR4Size=16 1509BAR5=1 1510BAR5LegacyIO=false 1511BAR5Size=0 1512BIST=0 1513CacheLineSize=0 1514CapabilityPtr=0 1515CardbusCIS=0 1516ClassCode=1 1517Command=1 1518DeviceID=28945 1519ExpansionROM=0 1520HeaderType=0 1521InterruptLine=31 1522InterruptPin=1 1523LatencyTimer=0 1524MSICAPBaseOffset=0 1525MSICAPCapId=0 1526MSICAPMaskBits=0 1527MSICAPMsgAddr=0 1528MSICAPMsgCtrl=0 1529MSICAPMsgData=0 1530MSICAPMsgUpperAddr=0 1531MSICAPNextCapability=0 1532MSICAPPendingBits=0 1533MSIXCAPBaseOffset=0 1534MSIXCAPCapId=0 1535MSIXCAPNextCapability=0 1536MSIXMsgCtrl=0 1537MSIXPbaOffset=0 1538MSIXTableOffset=0 1539MaximumLatency=0 1540MinimumGrant=0 1541PMCAPBaseOffset=0 1542PMCAPCapId=0 1543PMCAPCapabilities=0 1544PMCAPCtrlStatus=0 1545PMCAPNextCapability=0 1546PXCAPBaseOffset=0 1547PXCAPCapId=0 1548PXCAPCapabilities=0 1549PXCAPDevCap2=0 1550PXCAPDevCapabilities=0 1551PXCAPDevCtrl=0 1552PXCAPDevCtrl2=0 1553PXCAPDevStatus=0 1554PXCAPLinkCap=0 1555PXCAPLinkCtrl=0 1556PXCAPLinkStatus=0 1557PXCAPNextCapability=0 1558ProgIF=133 1559Revision=0 1560Status=640 1561SubClassCode=1 1562SubsystemID=0 1563SubsystemVendorID=0 1564VendorID=32902 1565clk_domain=system.clk_domain 1566config_latency=20000 1567ctrl_offset=2 1568disks=system.cf0 1569eventq_index=0 1570io_shift=1 1571pci_bus=2 1572pci_dev=7 1573pci_func=0 1574pio_latency=30000 1575platform=system.realview 1576system=system 1577config=system.iobus.master[8] 1578dma=system.iobus.slave[2] 1579pio=system.iobus.master[7] 1580 1581[system.realview.clcd] 1582type=Pl111 1583amba_id=1315089 1584clk_domain=system.clk_domain 1585enable_capture=true 1586eventq_index=0 1587gic=system.realview.gic 1588int_num=55 1589pio_addr=268566528 1590pio_latency=10000 1591pixel_clock=41667 1592system=system 1593vnc=system.vncserver 1594dma=system.iobus.slave[1] 1595pio=system.iobus.master[4] 1596 1597[system.realview.dmac_fake] 1598type=AmbaFake 1599amba_id=0 1600clk_domain=system.clk_domain 1601eventq_index=0 1602ignore_access=false 1603pio_addr=268632064 1604pio_latency=100000 1605system=system 1606pio=system.iobus.master[9] 1607 1608[system.realview.flash_fake] 1609type=IsaFake 1610clk_domain=system.clk_domain 1611eventq_index=0 1612fake_mem=true 1613pio_addr=1073741824 1614pio_latency=100000 1615pio_size=536870912 1616ret_bad_addr=false 1617ret_data16=65535 1618ret_data32=4294967295 1619ret_data64=18446744073709551615 1620ret_data8=255 1621system=system 1622update_data=false 1623warn_access= 1624pio=system.iobus.master[24] 1625 1626[system.realview.gic] 1627type=Pl390 1628clk_domain=system.clk_domain 1629cpu_addr=520093952 1630cpu_pio_delay=10000 1631dist_addr=520097792 1632dist_pio_delay=10000 1633eventq_index=0 1634int_latency=10000 1635it_lines=128 1636msix_addr=0 1637platform=system.realview 1638system=system 1639pio=system.membus.master[2] 1640 1641[system.realview.gpio0_fake] 1642type=AmbaFake 1643amba_id=0 1644clk_domain=system.clk_domain 1645eventq_index=0 1646ignore_access=false 1647pio_addr=268513280 1648pio_latency=100000 1649system=system 1650pio=system.iobus.master[16] 1651 1652[system.realview.gpio1_fake] 1653type=AmbaFake 1654amba_id=0 1655clk_domain=system.clk_domain 1656eventq_index=0 1657ignore_access=false 1658pio_addr=268517376 1659pio_latency=100000 1660system=system 1661pio=system.iobus.master[17] 1662 1663[system.realview.gpio2_fake] 1664type=AmbaFake 1665amba_id=0 1666clk_domain=system.clk_domain 1667eventq_index=0 1668ignore_access=false 1669pio_addr=268521472 1670pio_latency=100000 1671system=system 1672pio=system.iobus.master[18] 1673 1674[system.realview.kmi0] 1675type=Pl050 1676amba_id=1314896 1677clk_domain=system.clk_domain 1678eventq_index=0 1679gic=system.realview.gic 1680int_delay=1000000 1681int_num=52 1682is_mouse=false 1683pio_addr=268460032 1684pio_latency=100000 1685system=system 1686vnc=system.vncserver 1687pio=system.iobus.master[5] 1688 1689[system.realview.kmi1] 1690type=Pl050 1691amba_id=1314896 1692clk_domain=system.clk_domain 1693eventq_index=0 1694gic=system.realview.gic 1695int_delay=1000000 1696int_num=53 1697is_mouse=true 1698pio_addr=268464128 1699pio_latency=100000 1700system=system 1701vnc=system.vncserver 1702pio=system.iobus.master[6] 1703 1704[system.realview.l2x0_fake] 1705type=IsaFake 1706clk_domain=system.clk_domain 1707eventq_index=0 1708fake_mem=false 1709pio_addr=520101888 1710pio_latency=100000 1711pio_size=4095 1712ret_bad_addr=false 1713ret_data16=65535 1714ret_data32=4294967295 1715ret_data64=18446744073709551615 1716ret_data8=255 1717system=system 1718update_data=false 1719warn_access= 1720pio=system.membus.master[3] 1721 1722[system.realview.local_cpu_timer] 1723type=CpuLocalTimer 1724clk_domain=system.clk_domain 1725eventq_index=0 1726gic=system.realview.gic 1727int_num_timer=29 1728int_num_watchdog=30 1729pio_addr=520095232 1730pio_latency=100000 1731system=system 1732pio=system.membus.master[5] 1733 1734[system.realview.mmc_fake] 1735type=AmbaFake 1736amba_id=0 1737clk_domain=system.clk_domain 1738eventq_index=0 1739ignore_access=false 1740pio_addr=268455936 1741pio_latency=100000 1742system=system 1743pio=system.iobus.master[22] 1744 1745[system.realview.nvmem] 1746type=SimpleMemory 1747bandwidth=73.000000 1748clk_domain=system.clk_domain 1749conf_table_reported=false 1750eventq_index=0 1751in_addr_map=true 1752latency=30000 1753latency_var=0 1754null=false 1755range=2147483648:2214592511 1756port=system.membus.master[1] 1757 1758[system.realview.realview_io] 1759type=RealViewCtrl 1760clk_domain=system.clk_domain 1761eventq_index=0 1762idreg=0 1763pio_addr=268435456 1764pio_latency=100000 1765proc_id0=201326592 1766proc_id1=201327138 1767system=system 1768pio=system.iobus.master[1] 1769 1770[system.realview.rtc] 1771type=PL031 1772amba_id=3412017 1773clk_domain=system.clk_domain 1774eventq_index=0 1775gic=system.realview.gic 1776int_delay=100000 1777int_num=42 1778pio_addr=268529664 1779pio_latency=100000 1780system=system 1781time=Thu Jan 1 00:00:00 2009 1782pio=system.iobus.master[23] 1783 1784[system.realview.sci_fake] 1785type=AmbaFake 1786amba_id=0 1787clk_domain=system.clk_domain 1788eventq_index=0 1789ignore_access=false 1790pio_addr=268492800 1791pio_latency=100000 1792system=system 1793pio=system.iobus.master[20] 1794 1795[system.realview.smc_fake] 1796type=AmbaFake 1797amba_id=0 1798clk_domain=system.clk_domain 1799eventq_index=0 1800ignore_access=false 1801pio_addr=269357056 1802pio_latency=100000 1803system=system 1804pio=system.iobus.master[13] 1805 1806[system.realview.sp810_fake] 1807type=AmbaFake 1808amba_id=0 1809clk_domain=system.clk_domain 1810eventq_index=0 1811ignore_access=true 1812pio_addr=268439552 1813pio_latency=100000 1814system=system 1815pio=system.iobus.master[14] 1816 1817[system.realview.ssp_fake] 1818type=AmbaFake 1819amba_id=0 1820clk_domain=system.clk_domain 1821eventq_index=0 1822ignore_access=false 1823pio_addr=268488704 1824pio_latency=100000 1825system=system 1826pio=system.iobus.master[19] 1827 1828[system.realview.timer0] 1829type=Sp804 1830amba_id=1316868 1831clk_domain=system.clk_domain 1832clock0=1000000 1833clock1=1000000 1834eventq_index=0 1835gic=system.realview.gic 1836int_num0=36 1837int_num1=36 1838pio_addr=268505088 1839pio_latency=100000 1840system=system 1841pio=system.iobus.master[2] 1842 1843[system.realview.timer1] 1844type=Sp804 1845amba_id=1316868 1846clk_domain=system.clk_domain 1847clock0=1000000 1848clock1=1000000 1849eventq_index=0 1850gic=system.realview.gic 1851int_num0=37 1852int_num1=37 1853pio_addr=268509184 1854pio_latency=100000 1855system=system 1856pio=system.iobus.master[3] 1857 1858[system.realview.uart] 1859type=Pl011 1860clk_domain=system.clk_domain 1861end_on_eot=false 1862eventq_index=0 1863gic=system.realview.gic 1864int_delay=100000 1865int_num=44 1866pio_addr=268472320 1867pio_latency=100000 1868platform=system.realview 1869system=system 1870terminal=system.terminal 1871pio=system.iobus.master[0] 1872 1873[system.realview.uart1_fake] 1874type=AmbaFake 1875amba_id=0 1876clk_domain=system.clk_domain 1877eventq_index=0 1878ignore_access=false 1879pio_addr=268476416 1880pio_latency=100000 1881system=system 1882pio=system.iobus.master[10] 1883 1884[system.realview.uart2_fake] 1885type=AmbaFake 1886amba_id=0 1887clk_domain=system.clk_domain 1888eventq_index=0 1889ignore_access=false 1890pio_addr=268480512 1891pio_latency=100000 1892system=system 1893pio=system.iobus.master[11] 1894 1895[system.realview.uart3_fake] 1896type=AmbaFake 1897amba_id=0 1898clk_domain=system.clk_domain 1899eventq_index=0 1900ignore_access=false 1901pio_addr=268484608 1902pio_latency=100000 1903system=system 1904pio=system.iobus.master[12] 1905 1906[system.realview.watchdog_fake] 1907type=AmbaFake 1908amba_id=0 1909clk_domain=system.clk_domain 1910eventq_index=0 1911ignore_access=false 1912pio_addr=268500992 1913pio_latency=100000 1914system=system 1915pio=system.iobus.master[15] 1916 1917[system.terminal] 1918type=Terminal 1919eventq_index=0 1920intr_control=system.intrctrl 1921number=0 1922output=true 1923port=3456 1924 1925[system.toL2Bus] 1926type=CoherentBus 1927clk_domain=system.cpu_clk_domain 1928eventq_index=0 1929header_cycles=1 1930system=system 1931use_default_range=false 1932width=8 1933master=system.l2c.cpu_side 1934slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port 1935 1936[system.vncserver] 1937type=VncServer 1938eventq_index=0 1939frame_capture=false 1940number=0 1941port=5900 1942 1943[system.voltage_domain] 1944type=VoltageDomain 1945eventq_index=0 1946voltage=1.000000 1947 1948