config.ini revision 9536
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/projects/pd/randd/dist/binaries/boot.arm 14boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 15clock=1000 16dtb_filename= 17early_kernel_symbols=false 18enable_context_switch_stats_dump=false 19flags_addr=268435504 20gic_cpu_addr=520093952 21init_param=0 22kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 23load_addr_mask=268435455 24machine_type=RealView_PBX 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.realview.nvmem system.physmem 28multi_proc=true 29num_work_ids=16 30readfile=tests/halt.sh 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clock=1000 44delay=50000 45ranges=268435456:520093695 1073741824:1610612735 46req_size=16 47resp_size=16 48master=system.iobus.slave[0] 49slave=system.membus.master[0] 50 51[system.cf0] 52type=IdeDisk 53children=image 54delay=1000000 55driveID=master 56image=system.cf0.image 57 58[system.cf0.image] 59type=CowDiskImage 60children=child 61child=system.cf0.image.child 62image_file= 63read_only=false 64table_size=65536 65 66[system.cf0.image.child] 67type=RawDiskImage 68image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img 69read_only=true 70 71[system.cpu0] 72type=DerivO3CPU 73children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 74LFSTSize=1024 75LQEntries=32 76LSQCheckLoads=true 77LSQDepCheckShift=4 78SQEntries=32 79SSITSize=1024 80activity=0 81backComSize=5 82branchPred=system.cpu0.branchPred 83cachePorts=200 84checker=Null 85clock=500 86commitToDecodeDelay=1 87commitToFetchDelay=1 88commitToIEWDelay=1 89commitToRenameDelay=1 90commitWidth=8 91cpu_id=0 92decodeToFetchDelay=1 93decodeToRenameDelay=1 94decodeWidth=8 95dispatchWidth=8 96do_checkpoint_insts=true 97do_quiesce=true 98do_statistics_insts=true 99dtb=system.cpu0.dtb 100fetchToDecodeDelay=1 101fetchTrapLatency=1 102fetchWidth=8 103forwardComSize=5 104fuPool=system.cpu0.fuPool 105function_trace=false 106function_trace_start=0 107iewToCommitDelay=1 108iewToDecodeDelay=1 109iewToFetchDelay=1 110iewToRenameDelay=1 111interrupts=system.cpu0.interrupts 112isa=system.cpu0.isa 113issueToExecuteDelay=1 114issueWidth=8 115itb=system.cpu0.itb 116max_insts_all_threads=0 117max_insts_any_thread=0 118max_loads_all_threads=0 119max_loads_any_thread=0 120needsTSO=false 121numIQEntries=64 122numPhysFloatRegs=256 123numPhysIntRegs=256 124numROBEntries=192 125numRobs=1 126numThreads=1 127profile=0 128progress_interval=0 129renameToDecodeDelay=1 130renameToFetchDelay=1 131renameToIEWDelay=2 132renameToROBDelay=1 133renameWidth=8 134smtCommitPolicy=RoundRobin 135smtFetchPolicy=SingleThread 136smtIQPolicy=Partitioned 137smtIQThreshold=100 138smtLSQPolicy=Partitioned 139smtLSQThreshold=100 140smtNumFetchingThreads=1 141smtROBPolicy=Partitioned 142smtROBThreshold=100 143squashWidth=8 144store_set_clear_period=250000 145switched_out=false 146system=system 147tracer=system.cpu0.tracer 148trapLatency=13 149wbDepth=1 150wbWidth=8 151workload= 152dcache_port=system.cpu0.dcache.cpu_side 153icache_port=system.cpu0.icache.cpu_side 154 155[system.cpu0.branchPred] 156type=BranchPredictor 157BTBEntries=4096 158BTBTagSize=16 159RASSize=16 160choiceCtrBits=2 161choicePredictorSize=8192 162globalCtrBits=2 163globalHistoryBits=13 164globalPredictorSize=8192 165instShiftAmt=2 166localCtrBits=2 167localHistoryBits=11 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171predType=tournament 172 173[system.cpu0.dcache] 174type=BaseCache 175addr_ranges=0:18446744073709551615 176assoc=4 177block_size=64 178clock=500 179forward_snoops=true 180hit_latency=2 181is_top_level=true 182max_miss_count=0 183mshrs=4 184prefetch_on_access=false 185prefetcher=Null 186response_latency=2 187size=32768 188system=system 189tgts_per_mshr=20 190two_queue=false 191write_buffers=8 192cpu_side=system.cpu0.dcache_port 193mem_side=system.toL2Bus.slave[1] 194 195[system.cpu0.dtb] 196type=ArmTLB 197children=walker 198size=64 199walker=system.cpu0.dtb.walker 200 201[system.cpu0.dtb.walker] 202type=ArmTableWalker 203clock=500 204num_squash_per_cycle=2 205sys=system 206port=system.toL2Bus.slave[3] 207 208[system.cpu0.fuPool] 209type=FUPool 210children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 211FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 212 213[system.cpu0.fuPool.FUList0] 214type=FUDesc 215children=opList 216count=6 217opList=system.cpu0.fuPool.FUList0.opList 218 219[system.cpu0.fuPool.FUList0.opList] 220type=OpDesc 221issueLat=1 222opClass=IntAlu 223opLat=1 224 225[system.cpu0.fuPool.FUList1] 226type=FUDesc 227children=opList0 opList1 228count=2 229opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 230 231[system.cpu0.fuPool.FUList1.opList0] 232type=OpDesc 233issueLat=1 234opClass=IntMult 235opLat=3 236 237[system.cpu0.fuPool.FUList1.opList1] 238type=OpDesc 239issueLat=19 240opClass=IntDiv 241opLat=20 242 243[system.cpu0.fuPool.FUList2] 244type=FUDesc 245children=opList0 opList1 opList2 246count=4 247opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 248 249[system.cpu0.fuPool.FUList2.opList0] 250type=OpDesc 251issueLat=1 252opClass=FloatAdd 253opLat=2 254 255[system.cpu0.fuPool.FUList2.opList1] 256type=OpDesc 257issueLat=1 258opClass=FloatCmp 259opLat=2 260 261[system.cpu0.fuPool.FUList2.opList2] 262type=OpDesc 263issueLat=1 264opClass=FloatCvt 265opLat=2 266 267[system.cpu0.fuPool.FUList3] 268type=FUDesc 269children=opList0 opList1 opList2 270count=2 271opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 272 273[system.cpu0.fuPool.FUList3.opList0] 274type=OpDesc 275issueLat=1 276opClass=FloatMult 277opLat=4 278 279[system.cpu0.fuPool.FUList3.opList1] 280type=OpDesc 281issueLat=12 282opClass=FloatDiv 283opLat=12 284 285[system.cpu0.fuPool.FUList3.opList2] 286type=OpDesc 287issueLat=24 288opClass=FloatSqrt 289opLat=24 290 291[system.cpu0.fuPool.FUList4] 292type=FUDesc 293children=opList 294count=0 295opList=system.cpu0.fuPool.FUList4.opList 296 297[system.cpu0.fuPool.FUList4.opList] 298type=OpDesc 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu0.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 308 309[system.cpu0.fuPool.FUList5.opList00] 310type=OpDesc 311issueLat=1 312opClass=SimdAdd 313opLat=1 314 315[system.cpu0.fuPool.FUList5.opList01] 316type=OpDesc 317issueLat=1 318opClass=SimdAddAcc 319opLat=1 320 321[system.cpu0.fuPool.FUList5.opList02] 322type=OpDesc 323issueLat=1 324opClass=SimdAlu 325opLat=1 326 327[system.cpu0.fuPool.FUList5.opList03] 328type=OpDesc 329issueLat=1 330opClass=SimdCmp 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList04] 334type=OpDesc 335issueLat=1 336opClass=SimdCvt 337opLat=1 338 339[system.cpu0.fuPool.FUList5.opList05] 340type=OpDesc 341issueLat=1 342opClass=SimdMisc 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList06] 346type=OpDesc 347issueLat=1 348opClass=SimdMult 349opLat=1 350 351[system.cpu0.fuPool.FUList5.opList07] 352type=OpDesc 353issueLat=1 354opClass=SimdMultAcc 355opLat=1 356 357[system.cpu0.fuPool.FUList5.opList08] 358type=OpDesc 359issueLat=1 360opClass=SimdShift 361opLat=1 362 363[system.cpu0.fuPool.FUList5.opList09] 364type=OpDesc 365issueLat=1 366opClass=SimdShiftAcc 367opLat=1 368 369[system.cpu0.fuPool.FUList5.opList10] 370type=OpDesc 371issueLat=1 372opClass=SimdSqrt 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList11] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatAdd 379opLat=1 380 381[system.cpu0.fuPool.FUList5.opList12] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatAlu 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList13] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatCmp 391opLat=1 392 393[system.cpu0.fuPool.FUList5.opList14] 394type=OpDesc 395issueLat=1 396opClass=SimdFloatCvt 397opLat=1 398 399[system.cpu0.fuPool.FUList5.opList15] 400type=OpDesc 401issueLat=1 402opClass=SimdFloatDiv 403opLat=1 404 405[system.cpu0.fuPool.FUList5.opList16] 406type=OpDesc 407issueLat=1 408opClass=SimdFloatMisc 409opLat=1 410 411[system.cpu0.fuPool.FUList5.opList17] 412type=OpDesc 413issueLat=1 414opClass=SimdFloatMult 415opLat=1 416 417[system.cpu0.fuPool.FUList5.opList18] 418type=OpDesc 419issueLat=1 420opClass=SimdFloatMultAcc 421opLat=1 422 423[system.cpu0.fuPool.FUList5.opList19] 424type=OpDesc 425issueLat=1 426opClass=SimdFloatSqrt 427opLat=1 428 429[system.cpu0.fuPool.FUList6] 430type=FUDesc 431children=opList 432count=0 433opList=system.cpu0.fuPool.FUList6.opList 434 435[system.cpu0.fuPool.FUList6.opList] 436type=OpDesc 437issueLat=1 438opClass=MemWrite 439opLat=1 440 441[system.cpu0.fuPool.FUList7] 442type=FUDesc 443children=opList0 opList1 444count=4 445opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 446 447[system.cpu0.fuPool.FUList7.opList0] 448type=OpDesc 449issueLat=1 450opClass=MemRead 451opLat=1 452 453[system.cpu0.fuPool.FUList7.opList1] 454type=OpDesc 455issueLat=1 456opClass=MemWrite 457opLat=1 458 459[system.cpu0.fuPool.FUList8] 460type=FUDesc 461children=opList 462count=1 463opList=system.cpu0.fuPool.FUList8.opList 464 465[system.cpu0.fuPool.FUList8.opList] 466type=OpDesc 467issueLat=3 468opClass=IprAccess 469opLat=3 470 471[system.cpu0.icache] 472type=BaseCache 473addr_ranges=0:18446744073709551615 474assoc=1 475block_size=64 476clock=500 477forward_snoops=true 478hit_latency=2 479is_top_level=true 480max_miss_count=0 481mshrs=4 482prefetch_on_access=false 483prefetcher=Null 484response_latency=2 485size=32768 486system=system 487tgts_per_mshr=20 488two_queue=false 489write_buffers=8 490cpu_side=system.cpu0.icache_port 491mem_side=system.toL2Bus.slave[0] 492 493[system.cpu0.interrupts] 494type=ArmInterrupts 495 496[system.cpu0.isa] 497type=ArmISA 498fpsid=1090793632 499id_isar0=34607377 500id_isar1=34677009 501id_isar2=555950401 502id_isar3=17899825 503id_isar4=268501314 504id_isar5=0 505id_mmfr0=3 506id_mmfr1=0 507id_mmfr2=19070976 508id_mmfr3=4027589137 509id_pfr0=49 510id_pfr1=1 511midr=890224640 512 513[system.cpu0.itb] 514type=ArmTLB 515children=walker 516size=64 517walker=system.cpu0.itb.walker 518 519[system.cpu0.itb.walker] 520type=ArmTableWalker 521clock=500 522num_squash_per_cycle=2 523sys=system 524port=system.toL2Bus.slave[2] 525 526[system.cpu0.tracer] 527type=ExeTracer 528 529[system.cpu1] 530type=DerivO3CPU 531children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 532LFSTSize=1024 533LQEntries=32 534LSQCheckLoads=true 535LSQDepCheckShift=4 536SQEntries=32 537SSITSize=1024 538activity=0 539backComSize=5 540branchPred=system.cpu1.branchPred 541cachePorts=200 542checker=Null 543clock=500 544commitToDecodeDelay=1 545commitToFetchDelay=1 546commitToIEWDelay=1 547commitToRenameDelay=1 548commitWidth=8 549cpu_id=1 550decodeToFetchDelay=1 551decodeToRenameDelay=1 552decodeWidth=8 553dispatchWidth=8 554do_checkpoint_insts=true 555do_quiesce=true 556do_statistics_insts=true 557dtb=system.cpu1.dtb 558fetchToDecodeDelay=1 559fetchTrapLatency=1 560fetchWidth=8 561forwardComSize=5 562fuPool=system.cpu1.fuPool 563function_trace=false 564function_trace_start=0 565iewToCommitDelay=1 566iewToDecodeDelay=1 567iewToFetchDelay=1 568iewToRenameDelay=1 569interrupts=system.cpu1.interrupts 570isa=system.cpu1.isa 571issueToExecuteDelay=1 572issueWidth=8 573itb=system.cpu1.itb 574max_insts_all_threads=0 575max_insts_any_thread=0 576max_loads_all_threads=0 577max_loads_any_thread=0 578needsTSO=false 579numIQEntries=64 580numPhysFloatRegs=256 581numPhysIntRegs=256 582numROBEntries=192 583numRobs=1 584numThreads=1 585profile=0 586progress_interval=0 587renameToDecodeDelay=1 588renameToFetchDelay=1 589renameToIEWDelay=2 590renameToROBDelay=1 591renameWidth=8 592smtCommitPolicy=RoundRobin 593smtFetchPolicy=SingleThread 594smtIQPolicy=Partitioned 595smtIQThreshold=100 596smtLSQPolicy=Partitioned 597smtLSQThreshold=100 598smtNumFetchingThreads=1 599smtROBPolicy=Partitioned 600smtROBThreshold=100 601squashWidth=8 602store_set_clear_period=250000 603switched_out=false 604system=system 605tracer=system.cpu1.tracer 606trapLatency=13 607wbDepth=1 608wbWidth=8 609workload= 610dcache_port=system.cpu1.dcache.cpu_side 611icache_port=system.cpu1.icache.cpu_side 612 613[system.cpu1.branchPred] 614type=BranchPredictor 615BTBEntries=4096 616BTBTagSize=16 617RASSize=16 618choiceCtrBits=2 619choicePredictorSize=8192 620globalCtrBits=2 621globalHistoryBits=13 622globalPredictorSize=8192 623instShiftAmt=2 624localCtrBits=2 625localHistoryBits=11 626localHistoryTableSize=2048 627localPredictorSize=2048 628numThreads=1 629predType=tournament 630 631[system.cpu1.dcache] 632type=BaseCache 633addr_ranges=0:18446744073709551615 634assoc=4 635block_size=64 636clock=500 637forward_snoops=true 638hit_latency=2 639is_top_level=true 640max_miss_count=0 641mshrs=4 642prefetch_on_access=false 643prefetcher=Null 644response_latency=2 645size=32768 646system=system 647tgts_per_mshr=20 648two_queue=false 649write_buffers=8 650cpu_side=system.cpu1.dcache_port 651mem_side=system.toL2Bus.slave[5] 652 653[system.cpu1.dtb] 654type=ArmTLB 655children=walker 656size=64 657walker=system.cpu1.dtb.walker 658 659[system.cpu1.dtb.walker] 660type=ArmTableWalker 661clock=500 662num_squash_per_cycle=2 663sys=system 664port=system.toL2Bus.slave[7] 665 666[system.cpu1.fuPool] 667type=FUPool 668children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 669FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 670 671[system.cpu1.fuPool.FUList0] 672type=FUDesc 673children=opList 674count=6 675opList=system.cpu1.fuPool.FUList0.opList 676 677[system.cpu1.fuPool.FUList0.opList] 678type=OpDesc 679issueLat=1 680opClass=IntAlu 681opLat=1 682 683[system.cpu1.fuPool.FUList1] 684type=FUDesc 685children=opList0 opList1 686count=2 687opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 688 689[system.cpu1.fuPool.FUList1.opList0] 690type=OpDesc 691issueLat=1 692opClass=IntMult 693opLat=3 694 695[system.cpu1.fuPool.FUList1.opList1] 696type=OpDesc 697issueLat=19 698opClass=IntDiv 699opLat=20 700 701[system.cpu1.fuPool.FUList2] 702type=FUDesc 703children=opList0 opList1 opList2 704count=4 705opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 706 707[system.cpu1.fuPool.FUList2.opList0] 708type=OpDesc 709issueLat=1 710opClass=FloatAdd 711opLat=2 712 713[system.cpu1.fuPool.FUList2.opList1] 714type=OpDesc 715issueLat=1 716opClass=FloatCmp 717opLat=2 718 719[system.cpu1.fuPool.FUList2.opList2] 720type=OpDesc 721issueLat=1 722opClass=FloatCvt 723opLat=2 724 725[system.cpu1.fuPool.FUList3] 726type=FUDesc 727children=opList0 opList1 opList2 728count=2 729opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 730 731[system.cpu1.fuPool.FUList3.opList0] 732type=OpDesc 733issueLat=1 734opClass=FloatMult 735opLat=4 736 737[system.cpu1.fuPool.FUList3.opList1] 738type=OpDesc 739issueLat=12 740opClass=FloatDiv 741opLat=12 742 743[system.cpu1.fuPool.FUList3.opList2] 744type=OpDesc 745issueLat=24 746opClass=FloatSqrt 747opLat=24 748 749[system.cpu1.fuPool.FUList4] 750type=FUDesc 751children=opList 752count=0 753opList=system.cpu1.fuPool.FUList4.opList 754 755[system.cpu1.fuPool.FUList4.opList] 756type=OpDesc 757issueLat=1 758opClass=MemRead 759opLat=1 760 761[system.cpu1.fuPool.FUList5] 762type=FUDesc 763children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 764count=4 765opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 766 767[system.cpu1.fuPool.FUList5.opList00] 768type=OpDesc 769issueLat=1 770opClass=SimdAdd 771opLat=1 772 773[system.cpu1.fuPool.FUList5.opList01] 774type=OpDesc 775issueLat=1 776opClass=SimdAddAcc 777opLat=1 778 779[system.cpu1.fuPool.FUList5.opList02] 780type=OpDesc 781issueLat=1 782opClass=SimdAlu 783opLat=1 784 785[system.cpu1.fuPool.FUList5.opList03] 786type=OpDesc 787issueLat=1 788opClass=SimdCmp 789opLat=1 790 791[system.cpu1.fuPool.FUList5.opList04] 792type=OpDesc 793issueLat=1 794opClass=SimdCvt 795opLat=1 796 797[system.cpu1.fuPool.FUList5.opList05] 798type=OpDesc 799issueLat=1 800opClass=SimdMisc 801opLat=1 802 803[system.cpu1.fuPool.FUList5.opList06] 804type=OpDesc 805issueLat=1 806opClass=SimdMult 807opLat=1 808 809[system.cpu1.fuPool.FUList5.opList07] 810type=OpDesc 811issueLat=1 812opClass=SimdMultAcc 813opLat=1 814 815[system.cpu1.fuPool.FUList5.opList08] 816type=OpDesc 817issueLat=1 818opClass=SimdShift 819opLat=1 820 821[system.cpu1.fuPool.FUList5.opList09] 822type=OpDesc 823issueLat=1 824opClass=SimdShiftAcc 825opLat=1 826 827[system.cpu1.fuPool.FUList5.opList10] 828type=OpDesc 829issueLat=1 830opClass=SimdSqrt 831opLat=1 832 833[system.cpu1.fuPool.FUList5.opList11] 834type=OpDesc 835issueLat=1 836opClass=SimdFloatAdd 837opLat=1 838 839[system.cpu1.fuPool.FUList5.opList12] 840type=OpDesc 841issueLat=1 842opClass=SimdFloatAlu 843opLat=1 844 845[system.cpu1.fuPool.FUList5.opList13] 846type=OpDesc 847issueLat=1 848opClass=SimdFloatCmp 849opLat=1 850 851[system.cpu1.fuPool.FUList5.opList14] 852type=OpDesc 853issueLat=1 854opClass=SimdFloatCvt 855opLat=1 856 857[system.cpu1.fuPool.FUList5.opList15] 858type=OpDesc 859issueLat=1 860opClass=SimdFloatDiv 861opLat=1 862 863[system.cpu1.fuPool.FUList5.opList16] 864type=OpDesc 865issueLat=1 866opClass=SimdFloatMisc 867opLat=1 868 869[system.cpu1.fuPool.FUList5.opList17] 870type=OpDesc 871issueLat=1 872opClass=SimdFloatMult 873opLat=1 874 875[system.cpu1.fuPool.FUList5.opList18] 876type=OpDesc 877issueLat=1 878opClass=SimdFloatMultAcc 879opLat=1 880 881[system.cpu1.fuPool.FUList5.opList19] 882type=OpDesc 883issueLat=1 884opClass=SimdFloatSqrt 885opLat=1 886 887[system.cpu1.fuPool.FUList6] 888type=FUDesc 889children=opList 890count=0 891opList=system.cpu1.fuPool.FUList6.opList 892 893[system.cpu1.fuPool.FUList6.opList] 894type=OpDesc 895issueLat=1 896opClass=MemWrite 897opLat=1 898 899[system.cpu1.fuPool.FUList7] 900type=FUDesc 901children=opList0 opList1 902count=4 903opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 904 905[system.cpu1.fuPool.FUList7.opList0] 906type=OpDesc 907issueLat=1 908opClass=MemRead 909opLat=1 910 911[system.cpu1.fuPool.FUList7.opList1] 912type=OpDesc 913issueLat=1 914opClass=MemWrite 915opLat=1 916 917[system.cpu1.fuPool.FUList8] 918type=FUDesc 919children=opList 920count=1 921opList=system.cpu1.fuPool.FUList8.opList 922 923[system.cpu1.fuPool.FUList8.opList] 924type=OpDesc 925issueLat=3 926opClass=IprAccess 927opLat=3 928 929[system.cpu1.icache] 930type=BaseCache 931addr_ranges=0:18446744073709551615 932assoc=1 933block_size=64 934clock=500 935forward_snoops=true 936hit_latency=2 937is_top_level=true 938max_miss_count=0 939mshrs=4 940prefetch_on_access=false 941prefetcher=Null 942response_latency=2 943size=32768 944system=system 945tgts_per_mshr=20 946two_queue=false 947write_buffers=8 948cpu_side=system.cpu1.icache_port 949mem_side=system.toL2Bus.slave[4] 950 951[system.cpu1.interrupts] 952type=ArmInterrupts 953 954[system.cpu1.isa] 955type=ArmISA 956fpsid=1090793632 957id_isar0=34607377 958id_isar1=34677009 959id_isar2=555950401 960id_isar3=17899825 961id_isar4=268501314 962id_isar5=0 963id_mmfr0=3 964id_mmfr1=0 965id_mmfr2=19070976 966id_mmfr3=4027589137 967id_pfr0=49 968id_pfr1=1 969midr=890224640 970 971[system.cpu1.itb] 972type=ArmTLB 973children=walker 974size=64 975walker=system.cpu1.itb.walker 976 977[system.cpu1.itb.walker] 978type=ArmTableWalker 979clock=500 980num_squash_per_cycle=2 981sys=system 982port=system.toL2Bus.slave[6] 983 984[system.cpu1.tracer] 985type=ExeTracer 986 987[system.intrctrl] 988type=IntrControl 989sys=system 990 991[system.iobus] 992type=NoncoherentBus 993block_size=64 994clock=1000 995header_cycles=1 996use_default_range=false 997width=8 998master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side 999slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 1000 1001[system.iocache] 1002type=BaseCache 1003addr_ranges=0:134217727 1004assoc=8 1005block_size=64 1006clock=1000 1007forward_snoops=false 1008hit_latency=50 1009is_top_level=true 1010max_miss_count=0 1011mshrs=20 1012prefetch_on_access=false 1013prefetcher=Null 1014response_latency=50 1015size=1024 1016system=system 1017tgts_per_mshr=12 1018two_queue=false 1019write_buffers=8 1020cpu_side=system.iobus.master[25] 1021mem_side=system.membus.slave[2] 1022 1023[system.l2c] 1024type=BaseCache 1025addr_ranges=0:18446744073709551615 1026assoc=8 1027block_size=64 1028clock=500 1029forward_snoops=true 1030hit_latency=20 1031is_top_level=false 1032max_miss_count=0 1033mshrs=20 1034prefetch_on_access=false 1035prefetcher=Null 1036response_latency=20 1037size=4194304 1038system=system 1039tgts_per_mshr=12 1040two_queue=false 1041write_buffers=8 1042cpu_side=system.toL2Bus.master[0] 1043mem_side=system.membus.slave[1] 1044 1045[system.membus] 1046type=CoherentBus 1047children=badaddr_responder 1048block_size=64 1049clock=1000 1050header_cycles=1 1051system=system 1052use_default_range=false 1053width=8 1054default=system.membus.badaddr_responder.pio 1055master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 1056slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1057 1058[system.membus.badaddr_responder] 1059type=IsaFake 1060clock=1000 1061fake_mem=false 1062pio_addr=0 1063pio_latency=100000 1064pio_size=8 1065ret_bad_addr=true 1066ret_data16=65535 1067ret_data32=4294967295 1068ret_data64=18446744073709551615 1069ret_data8=255 1070system=system 1071update_data=false 1072warn_access=warn 1073pio=system.membus.default 1074 1075[system.physmem] 1076type=SimpleDRAM 1077activation_limit=4 1078addr_mapping=openmap 1079banks_per_rank=8 1080clock=1000 1081conf_table_reported=true 1082in_addr_map=true 1083lines_per_rowbuffer=32 1084mem_sched_policy=frfcfs 1085null=false 1086page_policy=open 1087range=0:134217727 1088ranks_per_channel=2 1089read_buffer_size=32 1090tBURST=5000 1091tCL=13750 1092tRCD=13750 1093tREFI=7800000 1094tRFC=300000 1095tRP=13750 1096tWTR=7500 1097tXAW=40000 1098write_buffer_size=32 1099write_thresh_perc=70 1100zero=false 1101port=system.membus.master[2] 1102 1103[system.realview] 1104type=RealView 1105children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 1106intrctrl=system.intrctrl 1107max_mem_size=268435456 1108mem_start_addr=0 1109pci_cfg_base=0 1110system=system 1111 1112[system.realview.a9scu] 1113type=A9SCU 1114clock=1000 1115pio_addr=520093696 1116pio_latency=100000 1117system=system 1118pio=system.membus.master[5] 1119 1120[system.realview.aaci_fake] 1121type=AmbaFake 1122amba_id=0 1123clock=1000 1124ignore_access=false 1125pio_addr=268451840 1126pio_latency=100000 1127system=system 1128pio=system.iobus.master[21] 1129 1130[system.realview.cf_ctrl] 1131type=IdeController 1132BAR0=402653184 1133BAR0LegacyIO=true 1134BAR0Size=16 1135BAR1=402653440 1136BAR1LegacyIO=true 1137BAR1Size=1 1138BAR2=1 1139BAR2LegacyIO=false 1140BAR2Size=8 1141BAR3=1 1142BAR3LegacyIO=false 1143BAR3Size=4 1144BAR4=1 1145BAR4LegacyIO=false 1146BAR4Size=16 1147BAR5=1 1148BAR5LegacyIO=false 1149BAR5Size=0 1150BIST=0 1151CacheLineSize=0 1152CardbusCIS=0 1153ClassCode=1 1154Command=1 1155DeviceID=28945 1156ExpansionROM=0 1157HeaderType=0 1158InterruptLine=31 1159InterruptPin=1 1160LatencyTimer=0 1161MaximumLatency=0 1162MinimumGrant=0 1163ProgIF=133 1164Revision=0 1165Status=640 1166SubClassCode=1 1167SubsystemID=0 1168SubsystemVendorID=0 1169VendorID=32902 1170clock=1000 1171config_latency=20000 1172ctrl_offset=2 1173disks=system.cf0 1174io_shift=1 1175pci_bus=2 1176pci_dev=7 1177pci_func=0 1178pio_latency=30000 1179platform=system.realview 1180system=system 1181config=system.iobus.master[8] 1182dma=system.iobus.slave[2] 1183pio=system.iobus.master[7] 1184 1185[system.realview.clcd] 1186type=Pl111 1187amba_id=1315089 1188clock=1000 1189gic=system.realview.gic 1190int_num=55 1191pio_addr=268566528 1192pio_latency=10000 1193pixel_clock=41667 1194system=system 1195vnc=system.vncserver 1196dma=system.iobus.slave[1] 1197pio=system.iobus.master[4] 1198 1199[system.realview.dmac_fake] 1200type=AmbaFake 1201amba_id=0 1202clock=1000 1203ignore_access=false 1204pio_addr=268632064 1205pio_latency=100000 1206system=system 1207pio=system.iobus.master[9] 1208 1209[system.realview.flash_fake] 1210type=IsaFake 1211clock=1000 1212fake_mem=true 1213pio_addr=1073741824 1214pio_latency=100000 1215pio_size=536870912 1216ret_bad_addr=false 1217ret_data16=65535 1218ret_data32=4294967295 1219ret_data64=18446744073709551615 1220ret_data8=255 1221system=system 1222update_data=false 1223warn_access= 1224pio=system.iobus.master[24] 1225 1226[system.realview.gic] 1227type=Pl390 1228clock=1000 1229cpu_addr=520093952 1230cpu_pio_delay=10000 1231dist_addr=520097792 1232dist_pio_delay=10000 1233int_latency=10000 1234it_lines=128 1235platform=system.realview 1236system=system 1237pio=system.membus.master[3] 1238 1239[system.realview.gpio0_fake] 1240type=AmbaFake 1241amba_id=0 1242clock=1000 1243ignore_access=false 1244pio_addr=268513280 1245pio_latency=100000 1246system=system 1247pio=system.iobus.master[16] 1248 1249[system.realview.gpio1_fake] 1250type=AmbaFake 1251amba_id=0 1252clock=1000 1253ignore_access=false 1254pio_addr=268517376 1255pio_latency=100000 1256system=system 1257pio=system.iobus.master[17] 1258 1259[system.realview.gpio2_fake] 1260type=AmbaFake 1261amba_id=0 1262clock=1000 1263ignore_access=false 1264pio_addr=268521472 1265pio_latency=100000 1266system=system 1267pio=system.iobus.master[18] 1268 1269[system.realview.kmi0] 1270type=Pl050 1271amba_id=1314896 1272clock=1000 1273gic=system.realview.gic 1274int_delay=1000000 1275int_num=52 1276is_mouse=false 1277pio_addr=268460032 1278pio_latency=100000 1279system=system 1280vnc=system.vncserver 1281pio=system.iobus.master[5] 1282 1283[system.realview.kmi1] 1284type=Pl050 1285amba_id=1314896 1286clock=1000 1287gic=system.realview.gic 1288int_delay=1000000 1289int_num=53 1290is_mouse=true 1291pio_addr=268464128 1292pio_latency=100000 1293system=system 1294vnc=system.vncserver 1295pio=system.iobus.master[6] 1296 1297[system.realview.l2x0_fake] 1298type=IsaFake 1299clock=1000 1300fake_mem=false 1301pio_addr=520101888 1302pio_latency=100000 1303pio_size=4095 1304ret_bad_addr=false 1305ret_data16=65535 1306ret_data32=4294967295 1307ret_data64=18446744073709551615 1308ret_data8=255 1309system=system 1310update_data=false 1311warn_access= 1312pio=system.membus.master[4] 1313 1314[system.realview.local_cpu_timer] 1315type=CpuLocalTimer 1316clock=1000 1317gic=system.realview.gic 1318int_num_timer=29 1319int_num_watchdog=30 1320pio_addr=520095232 1321pio_latency=100000 1322system=system 1323pio=system.membus.master[6] 1324 1325[system.realview.mmc_fake] 1326type=AmbaFake 1327amba_id=0 1328clock=1000 1329ignore_access=false 1330pio_addr=268455936 1331pio_latency=100000 1332system=system 1333pio=system.iobus.master[22] 1334 1335[system.realview.nvmem] 1336type=SimpleMemory 1337bandwidth=73.000000 1338clock=1000 1339conf_table_reported=false 1340in_addr_map=true 1341latency=30000 1342latency_var=0 1343null=false 1344range=2147483648:2214592511 1345zero=true 1346port=system.membus.master[1] 1347 1348[system.realview.realview_io] 1349type=RealViewCtrl 1350clock=1000 1351idreg=0 1352pio_addr=268435456 1353pio_latency=100000 1354proc_id0=201326592 1355proc_id1=201327138 1356system=system 1357pio=system.iobus.master[1] 1358 1359[system.realview.rtc] 1360type=PL031 1361amba_id=3412017 1362clock=1000 1363gic=system.realview.gic 1364int_delay=100000 1365int_num=42 1366pio_addr=268529664 1367pio_latency=100000 1368system=system 1369time=Thu Jan 1 00:00:00 2009 1370pio=system.iobus.master[23] 1371 1372[system.realview.sci_fake] 1373type=AmbaFake 1374amba_id=0 1375clock=1000 1376ignore_access=false 1377pio_addr=268492800 1378pio_latency=100000 1379system=system 1380pio=system.iobus.master[20] 1381 1382[system.realview.smc_fake] 1383type=AmbaFake 1384amba_id=0 1385clock=1000 1386ignore_access=false 1387pio_addr=269357056 1388pio_latency=100000 1389system=system 1390pio=system.iobus.master[13] 1391 1392[system.realview.sp810_fake] 1393type=AmbaFake 1394amba_id=0 1395clock=1000 1396ignore_access=true 1397pio_addr=268439552 1398pio_latency=100000 1399system=system 1400pio=system.iobus.master[14] 1401 1402[system.realview.ssp_fake] 1403type=AmbaFake 1404amba_id=0 1405clock=1000 1406ignore_access=false 1407pio_addr=268488704 1408pio_latency=100000 1409system=system 1410pio=system.iobus.master[19] 1411 1412[system.realview.timer0] 1413type=Sp804 1414amba_id=1316868 1415clock=1000 1416clock0=1000000 1417clock1=1000000 1418gic=system.realview.gic 1419int_num0=36 1420int_num1=36 1421pio_addr=268505088 1422pio_latency=100000 1423system=system 1424pio=system.iobus.master[2] 1425 1426[system.realview.timer1] 1427type=Sp804 1428amba_id=1316868 1429clock=1000 1430clock0=1000000 1431clock1=1000000 1432gic=system.realview.gic 1433int_num0=37 1434int_num1=37 1435pio_addr=268509184 1436pio_latency=100000 1437system=system 1438pio=system.iobus.master[3] 1439 1440[system.realview.uart] 1441type=Pl011 1442clock=1000 1443end_on_eot=false 1444gic=system.realview.gic 1445int_delay=100000 1446int_num=44 1447pio_addr=268472320 1448pio_latency=100000 1449platform=system.realview 1450system=system 1451terminal=system.terminal 1452pio=system.iobus.master[0] 1453 1454[system.realview.uart1_fake] 1455type=AmbaFake 1456amba_id=0 1457clock=1000 1458ignore_access=false 1459pio_addr=268476416 1460pio_latency=100000 1461system=system 1462pio=system.iobus.master[10] 1463 1464[system.realview.uart2_fake] 1465type=AmbaFake 1466amba_id=0 1467clock=1000 1468ignore_access=false 1469pio_addr=268480512 1470pio_latency=100000 1471system=system 1472pio=system.iobus.master[11] 1473 1474[system.realview.uart3_fake] 1475type=AmbaFake 1476amba_id=0 1477clock=1000 1478ignore_access=false 1479pio_addr=268484608 1480pio_latency=100000 1481system=system 1482pio=system.iobus.master[12] 1483 1484[system.realview.watchdog_fake] 1485type=AmbaFake 1486amba_id=0 1487clock=1000 1488ignore_access=false 1489pio_addr=268500992 1490pio_latency=100000 1491system=system 1492pio=system.iobus.master[15] 1493 1494[system.terminal] 1495type=Terminal 1496intr_control=system.intrctrl 1497number=0 1498output=true 1499port=3456 1500 1501[system.toL2Bus] 1502type=CoherentBus 1503block_size=64 1504clock=500 1505header_cycles=1 1506system=system 1507use_default_range=false 1508width=8 1509master=system.l2c.cpu_side 1510slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port 1511 1512[system.vncserver] 1513type=VncServer 1514frame_capture=false 1515number=0 1516port=5900 1517 1518