stats.txt revision 11547:dd6dfd38b6c2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858505 # Number of seconds simulated 4sim_ticks 2858505242500 # Number of ticks simulated 5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 152549 # Simulator instruction rate (inst/s) 8host_op_rate 184443 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3896990443 # Simulator tick rate (ticks/s) 10host_mem_usage 585436 # Number of bytes of host memory used 11host_seconds 733.52 # Real time elapsed on the host 12sim_insts 111897168 # Number of instructions simulated 13sim_ops 135292215 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 10871852 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1705984 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1705984 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7955328 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7972852 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 26656 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 143599 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 170394 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 124302 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 128683 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 2754 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 596810 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3203413 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3803335 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 596810 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 596810 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2783038 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2789168 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2783038 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2754 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 596810 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3209543 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6592503 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170394 # Number of read requests accepted 56system.physmem.writeReqs 128683 # Number of write requests accepted 57system.physmem.readBursts 170394 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 128683 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10896320 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7985280 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10871852 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7972852 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 10648 # Per bank write bursts 68system.physmem.perBankRdBursts::1 11113 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10810 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10613 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13551 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10292 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10857 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10932 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10292 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10622 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10100 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9078 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10356 # Per bank write bursts 80system.physmem.perBankRdBursts::13 10810 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10110 # Per bank write bursts 82system.physmem.perBankRdBursts::15 10071 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7962 # Per bank write bursts 84system.physmem.perBankWrBursts::1 8429 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8465 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8172 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7181 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7509 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7876 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8019 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7862 # Per bank write bursts 92system.physmem.perBankWrBursts::9 8101 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7665 # Per bank write bursts 94system.physmem.perBankWrBursts::11 6948 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7780 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8006 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7432 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7363 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 101system.physmem.totGap 2858504798000 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 543 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 169837 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 124302 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 162916 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 7039 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 1900 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 7027 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6391 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 7111 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6484 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6369 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6552 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7255 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 6931 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 7511 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8551 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7289 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7564 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8849 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7445 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 7178 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1232 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 130 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 122 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 109 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 80 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 96 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 71 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 37 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 61459 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 307.217495 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 182.591879 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 324.526171 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 22578 36.74% 36.74% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14767 24.03% 60.76% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6693 10.89% 71.65% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3646 5.93% 77.59% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2555 4.16% 81.74% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 2031 3.30% 85.05% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1005 1.64% 86.68% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1119 1.82% 88.50% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7065 11.50% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 61459 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6091 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.951896 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 574.936120 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6090 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6091 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6090 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.486535 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.508732 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 14.308920 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5400 88.67% 88.67% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 109 1.79% 90.46% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 32 0.53% 90.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 43 0.71% 91.69% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 35 0.57% 92.27% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 14 0.23% 92.50% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 47 0.77% 93.27% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 15 0.25% 93.51% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 145 2.38% 95.89% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 5 0.08% 95.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 5 0.08% 96.06% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 14 0.23% 96.29% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 63 1.03% 97.32% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 9 0.15% 97.47% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 5 0.08% 97.55% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 27 0.44% 98.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 95 1.56% 99.56% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.57% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 1 0.02% 99.59% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::128-131 8 0.13% 99.77% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::140-143 1 0.02% 99.79% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::160-163 1 0.02% 99.93% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::176-179 3 0.05% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 6090 # Writes before turning the bus around for reads 266system.physmem.totQLat 1821948750 # Total ticks spent queuing 267system.physmem.totMemAccLat 5014230000 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 851275000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 10701.29 # Average queueing delay per DRAM burst 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 271system.physmem.avgMemAccLat 29451.29 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 25.82 # Average write queue length when enqueuing 282system.physmem.readRowHits 139699 # Number of row buffer hits during reads 283system.physmem.writeRowHits 93863 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes 286system.physmem.avgGap 9557755.35 # Average gap between requests 287system.physmem.pageHitRate 79.16 # Row buffer hit rate, read and write combined 288system.physmem_0.actEnergy 240408000 # Energy for activate commands per rank (pJ) 289system.physmem_0.preEnergy 131175000 # Energy for precharge commands per rank (pJ) 290system.physmem_0.readEnergy 692764800 # Energy for read commands per rank (pJ) 291system.physmem_0.writeEnergy 412173360 # Energy for write commands per rank (pJ) 292system.physmem_0.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) 293system.physmem_0.actBackEnergy 86549850225 # Energy for active background per rank (pJ) 294system.physmem_0.preBackEnergy 1639181430000 # Energy for precharge background per rank (pJ) 295system.physmem_0.totalEnergy 1913911365705 # Total energy per rank (pJ) 296system.physmem_0.averagePower 669.550023 # Core power per rank (mW) 297system.physmem_0.memoryStateTime::IDLE 2726766742000 # Time in different power states 298system.physmem_0.memoryStateTime::REF 95451720000 # Time in different power states 299system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 300system.physmem_0.memoryStateTime::ACT 36286757000 # Time in different power states 301system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 302system.physmem_1.actEnergy 224214480 # Energy for activate commands per rank (pJ) 303system.physmem_1.preEnergy 122339250 # Energy for precharge commands per rank (pJ) 304system.physmem_1.readEnergy 635216400 # Energy for read commands per rank (pJ) 305system.physmem_1.writeEnergy 396290880 # Energy for write commands per rank (pJ) 306system.physmem_1.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) 307system.physmem_1.actBackEnergy 85109194890 # Energy for active background per rank (pJ) 308system.physmem_1.preBackEnergy 1640445162750 # Energy for precharge background per rank (pJ) 309system.physmem_1.totalEnergy 1913635982970 # Total energy per rank (pJ) 310system.physmem_1.averagePower 669.453685 # Core power per rank (mW) 311system.physmem_1.memoryStateTime::IDLE 2728879759500 # Time in different power states 312system.physmem_1.memoryStateTime::REF 95451720000 # Time in different power states 313system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 314system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states 315system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 316system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 317system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 318system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 319system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 320system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 321system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 322system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 323system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 328system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) 329system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 330system.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 331system.bridge.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 332system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 333system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 334system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 335system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 336system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 337system.cf0.dma_write_txs 631 # Number of DMA write transactions. 338system.cpu.branchPred.lookups 30988279 # Number of BP lookups 339system.cpu.branchPred.condPredicted 16810499 # Number of conditional branches predicted 340system.cpu.branchPred.condIncorrect 2467893 # Number of conditional branches incorrect 341system.cpu.branchPred.BTBLookups 18543680 # Number of BTB lookups 342system.cpu.branchPred.BTBHits 10372624 # Number of BTB hits 343system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 344system.cpu.branchPred.BTBHitPct 55.936168 # BTB Hit Percentage 345system.cpu.branchPred.usedRAS 7863209 # Number of times the RAS was used to get a target. 346system.cpu.branchPred.RASInCorrect 1506080 # Number of incorrect RAS predictions. 347system.cpu.branchPred.indirectLookups 3044381 # Number of indirect predictor lookups. 348system.cpu.branchPred.indirectHits 2857246 # Number of indirect target hits. 349system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses. 350system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches. 351system.cpu_clk_domain.clock 500 # Clock period in ticks 352system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 353system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 362system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 363system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 364system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 365system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 366system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 370system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 371system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 372system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 374system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 377system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 378system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 379system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 380system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 381system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 382system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 383system.cpu.dtb.walker.walks 66151 # Table walker walks requested 384system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors 385system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate 386system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22641 # Level at which table walker walks with short descriptors terminate 387system.cpu.dtb.walker.walkWaitTime::samples 66151 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::0 66151 100.00% 100.00% # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::total 66151 # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkCompletionTime::samples 7866 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::mean 12681.604373 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::gmean 10478.068683 # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::stdev 8425.510925 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::0-32767 7859 99.91% 99.91% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::total 7866 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution 399system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution 400system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution 401system.cpu.dtb.walker.walkPageSizes::4K 6508 82.74% 82.74% # Table walker page sizes translated 402system.cpu.dtb.walker.walkPageSizes::1M 1358 17.26% 100.00% # Table walker page sizes translated 403system.cpu.dtb.walker.walkPageSizes::total 7866 # Table walker page sizes translated 404system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66151 # Table walker requests started/completed, data/inst 405system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 406system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66151 # Table walker requests started/completed, data/inst 407system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7866 # Table walker requests started/completed, data/inst 408system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 # Table walker requests started/completed, data/inst 410system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst 411system.cpu.dtb.inst_hits 0 # ITB inst hits 412system.cpu.dtb.inst_misses 0 # ITB inst misses 413system.cpu.dtb.read_hits 24710833 # DTB read hits 414system.cpu.dtb.read_misses 59358 # DTB read misses 415system.cpu.dtb.write_hits 19424404 # DTB write hits 416system.cpu.dtb.write_misses 6793 # DTB write misses 417system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 418system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 419system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 420system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 421system.cpu.dtb.flush_entries 4286 # Number of entries that have been flushed from TLB 422system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions 423system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch 424system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 425system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions 426system.cpu.dtb.read_accesses 24770191 # DTB read accesses 427system.cpu.dtb.write_accesses 19431197 # DTB write accesses 428system.cpu.dtb.inst_accesses 0 # ITB inst accesses 429system.cpu.dtb.hits 44135237 # DTB hits 430system.cpu.dtb.misses 66151 # DTB misses 431system.cpu.dtb.accesses 44201388 # DTB accesses 432system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 433system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 434system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 435system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 436system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 437system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 438system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 442system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 443system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 444system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 445system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 446system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 447system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 448system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 449system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 450system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 451system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 452system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 453system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 454system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 455system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 456system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 457system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 458system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 459system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 460system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 461system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 462system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 463system.cpu.itb.walker.walks 5761 # Table walker walks requested 464system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors 465system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate 466system.cpu.itb.walker.walksShortTerminationLevel::Level2 5434 # Level at which table walker walks with short descriptors terminate 467system.cpu.itb.walker.walkWaitTime::samples 5761 # Table walker wait (enqueue to first request) latency 468system.cpu.itb.walker.walkWaitTime::0 5761 100.00% 100.00% # Table walker wait (enqueue to first request) latency 469system.cpu.itb.walker.walkWaitTime::total 5761 # Table walker wait (enqueue to first request) latency 470system.cpu.itb.walker.walkCompletionTime::samples 3206 # Table walker service (enqueue to completion) latency 471system.cpu.itb.walker.walkCompletionTime::mean 12829.694323 # Table walker service (enqueue to completion) latency 472system.cpu.itb.walker.walkCompletionTime::gmean 10737.941546 # Table walker service (enqueue to completion) latency 473system.cpu.itb.walker.walkCompletionTime::stdev 7417.860411 # Table walker service (enqueue to completion) latency 474system.cpu.itb.walker.walkCompletionTime::0-16383 2464 76.86% 76.86% # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::16384-32767 741 23.11% 99.97% # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::total 3206 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution 479system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution 480system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution 481system.cpu.itb.walker.walkPageSizes::4K 2896 90.33% 90.33% # Table walker page sizes translated 482system.cpu.itb.walker.walkPageSizes::1M 310 9.67% 100.00% # Table walker page sizes translated 483system.cpu.itb.walker.walkPageSizes::total 3206 # Table walker page sizes translated 484system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 485system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5761 # Table walker requests started/completed, data/inst 486system.cpu.itb.walker.walkRequestOrigin_Requested::total 5761 # Table walker requests started/completed, data/inst 487system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 488system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3206 # Table walker requests started/completed, data/inst 489system.cpu.itb.walker.walkRequestOrigin_Completed::total 3206 # Table walker requests started/completed, data/inst 490system.cpu.itb.walker.walkRequestOrigin::total 8967 # Table walker requests started/completed, data/inst 491system.cpu.itb.inst_hits 57333922 # ITB inst hits 492system.cpu.itb.inst_misses 5761 # ITB inst misses 493system.cpu.itb.read_hits 0 # DTB read hits 494system.cpu.itb.read_misses 0 # DTB read misses 495system.cpu.itb.write_hits 0 # DTB write hits 496system.cpu.itb.write_misses 0 # DTB write misses 497system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 498system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 499system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 501system.cpu.itb.flush_entries 2928 # Number of entries that have been flushed from TLB 502system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions 506system.cpu.itb.read_accesses 0 # DTB read accesses 507system.cpu.itb.write_accesses 0 # DTB write accesses 508system.cpu.itb.inst_accesses 57339683 # ITB inst accesses 509system.cpu.itb.hits 57333922 # DTB hits 510system.cpu.itb.misses 5761 # DTB misses 511system.cpu.itb.accesses 57339683 # DTB accesses 512system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 513system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state 514system.cpu.pwrStateClkGateDist::mean 887601126.287174 # Distribution of time spent in the clock gated state 515system.cpu.pwrStateClkGateDist::stdev 17445279478.153702 # Distribution of time spent in the clock gated state 516system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state 517system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state 518system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 519system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 520system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 521system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 522system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 523system.cpu.pwrStateClkGateDist::max_value 499966497156 # Distribution of time spent in the clock gated state 524system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state 525system.cpu.pwrStateResidencyTicks::ON 166411026471 # Cumulative time (in ticks) in various power states 526system.cpu.pwrStateResidencyTicks::CLK_GATED 2692094216029 # Cumulative time (in ticks) in various power states 527system.cpu.numCycles 332822103 # number of cpu cycles simulated 528system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 529system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 530system.cpu.committedInsts 111897168 # Number of instructions committed 531system.cpu.committedOps 135292215 # Number of ops (including micro ops) committed 532system.cpu.discardedOps 7734017 # Number of ops (including micro ops) which were discarded before commit 533system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching 534system.cpu.quiesceCycles 5384249089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 535system.cpu.cpi 2.974357 # CPI: cycles per instruction 536system.cpu.ipc 0.336207 # IPC: instructions per cycle 537system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction 538system.cpu.op_class_0::IntAlu 90691008 67.03% 67.04% # Class of committed instruction 539system.cpu.op_class_0::IntMult 113025 0.08% 67.12% # Class of committed instruction 540system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction 541system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction 542system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction 543system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction 544system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction 545system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction 546system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction 547system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction 548system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction 549system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction 550system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction 551system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction 552system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction 553system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction 554system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction 555system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction 556system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction 557system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction 558system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction 559system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction 560system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction 561system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction 562system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction 563system.cpu.op_class_0::SimdFloatMisc 8533 0.01% 67.13% # Class of committed instruction 564system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction 565system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction 566system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction 567system.cpu.op_class_0::MemRead 24225299 17.91% 85.03% # Class of committed instruction 568system.cpu.op_class_0::MemWrite 20252013 14.97% 100.00% # Class of committed instruction 569system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 571system.cpu.op_class_0::total 135292215 # Class of committed instruction 572system.cpu.kern.inst.arm 0 # number of arm instructions executed 573system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 574system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked 575system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped 576system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 577system.cpu.dcache.tags.replacements 842468 # number of replacements 578system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use 579system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks. 580system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks. 581system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks. 582system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. 583system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor 584system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy 585system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 594system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 18262413 # number of WriteReq hits 598system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits 599system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits 600system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits 601system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits 602system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits 603system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits 604system.cpu.dcache.demand_hits::cpu.data 41278668 # number of demand (read+write) hits 605system.cpu.dcache.demand_hits::total 41278668 # number of demand (read+write) hits 606system.cpu.dcache.overall_hits::cpu.data 41634970 # number of overall hits 607system.cpu.dcache.overall_hits::total 41634970 # number of overall hits 608system.cpu.dcache.ReadReq_misses::cpu.data 493842 # number of ReadReq misses 609system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses 610system.cpu.dcache.WriteReq_misses::cpu.data 547981 # number of WriteReq misses 611system.cpu.dcache.WriteReq_misses::total 547981 # number of WriteReq misses 612system.cpu.dcache.SoftPFReq_misses::cpu.data 169870 # number of SoftPFReq misses 613system.cpu.dcache.SoftPFReq_misses::total 169870 # number of SoftPFReq misses 614system.cpu.dcache.LoadLockedReq_misses::cpu.data 22311 # number of LoadLockedReq misses 615system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses 616system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 617system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 618system.cpu.dcache.demand_misses::cpu.data 1041823 # number of demand (read+write) misses 619system.cpu.dcache.demand_misses::total 1041823 # number of demand (read+write) misses 620system.cpu.dcache.overall_misses::cpu.data 1211693 # number of overall misses 621system.cpu.dcache.overall_misses::total 1211693 # number of overall misses 622system.cpu.dcache.ReadReq_miss_latency::cpu.data 8047572500 # number of ReadReq miss cycles 623system.cpu.dcache.ReadReq_miss_latency::total 8047572500 # number of ReadReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::cpu.data 35605363979 # number of WriteReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::total 35605363979 # number of WriteReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292635500 # number of LoadLockedReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::total 292635500 # number of LoadLockedReq miss cycles 628system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 629system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles 630system.cpu.dcache.demand_miss_latency::cpu.data 43652936479 # number of demand (read+write) miss cycles 631system.cpu.dcache.demand_miss_latency::total 43652936479 # number of demand (read+write) miss cycles 632system.cpu.dcache.overall_miss_latency::cpu.data 43652936479 # number of overall miss cycles 633system.cpu.dcache.overall_miss_latency::total 43652936479 # number of overall miss cycles 634system.cpu.dcache.ReadReq_accesses::cpu.data 23510097 # number of ReadReq accesses(hits+misses) 635system.cpu.dcache.ReadReq_accesses::total 23510097 # number of ReadReq accesses(hits+misses) 636system.cpu.dcache.WriteReq_accesses::cpu.data 18810394 # number of WriteReq accesses(hits+misses) 637system.cpu.dcache.WriteReq_accesses::total 18810394 # number of WriteReq accesses(hits+misses) 638system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172 # number of SoftPFReq accesses(hits+misses) 639system.cpu.dcache.SoftPFReq_accesses::total 526172 # number of SoftPFReq accesses(hits+misses) 640system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016 # number of LoadLockedReq accesses(hits+misses) 641system.cpu.dcache.LoadLockedReq_accesses::total 466016 # number of LoadLockedReq accesses(hits+misses) 642system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207 # number of StoreCondReq accesses(hits+misses) 643system.cpu.dcache.StoreCondReq_accesses::total 460207 # number of StoreCondReq accesses(hits+misses) 644system.cpu.dcache.demand_accesses::cpu.data 42320491 # number of demand (read+write) accesses 645system.cpu.dcache.demand_accesses::total 42320491 # number of demand (read+write) accesses 646system.cpu.dcache.overall_accesses::cpu.data 42846663 # number of overall (read+write) accesses 647system.cpu.dcache.overall_accesses::total 42846663 # number of overall (read+write) accesses 648system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses 650system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132 # miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_miss_rate::total 0.029132 # miss rate for WriteReq accesses 652system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322841 # miss rate for SoftPFReq accesses 653system.cpu.dcache.SoftPFReq_miss_rate::total 0.322841 # miss rate for SoftPFReq accesses 654system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047876 # miss rate for LoadLockedReq accesses 655system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses 656system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 657system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 658system.cpu.dcache.demand_miss_rate::cpu.data 0.024617 # miss rate for demand accesses 659system.cpu.dcache.demand_miss_rate::total 0.024617 # miss rate for demand accesses 660system.cpu.dcache.overall_miss_rate::cpu.data 0.028280 # miss rate for overall accesses 661system.cpu.dcache.overall_miss_rate::total 0.028280 # miss rate for overall accesses 662system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16295.844622 # average ReadReq miss latency 663system.cpu.dcache.ReadReq_avg_miss_latency::total 16295.844622 # average ReadReq miss latency 664system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64975.544734 # average WriteReq miss latency 665system.cpu.dcache.WriteReq_avg_miss_latency::total 64975.544734 # average WriteReq miss latency 666system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13116.198288 # average LoadLockedReq miss latency 667system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13116.198288 # average LoadLockedReq miss latency 668system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency 669system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency 670system.cpu.dcache.demand_avg_miss_latency::cpu.data 41900.530588 # average overall miss latency 671system.cpu.dcache.demand_avg_miss_latency::total 41900.530588 # average overall miss latency 672system.cpu.dcache.overall_avg_miss_latency::cpu.data 36026.399822 # average overall miss latency 673system.cpu.dcache.overall_avg_miss_latency::total 36026.399822 # average overall miss latency 674system.cpu.dcache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked 675system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 677system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.304348 # average number of cycles each access was blocked 679system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.dcache.writebacks::writebacks 699681 # number of writebacks 681system.cpu.dcache.writebacks::total 699681 # number of writebacks 682system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76216 # number of ReadReq MSHR hits 683system.cpu.dcache.ReadReq_mshr_hits::total 76216 # number of ReadReq MSHR hits 684system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249477 # number of WriteReq MSHR hits 685system.cpu.dcache.WriteReq_mshr_hits::total 249477 # number of WriteReq MSHR hits 686system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14071 # number of LoadLockedReq MSHR hits 687system.cpu.dcache.LoadLockedReq_mshr_hits::total 14071 # number of LoadLockedReq MSHR hits 688system.cpu.dcache.demand_mshr_hits::cpu.data 325693 # number of demand (read+write) MSHR hits 689system.cpu.dcache.demand_mshr_hits::total 325693 # number of demand (read+write) MSHR hits 690system.cpu.dcache.overall_mshr_hits::cpu.data 325693 # number of overall MSHR hits 691system.cpu.dcache.overall_mshr_hits::total 325693 # number of overall MSHR hits 692system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417626 # number of ReadReq MSHR misses 693system.cpu.dcache.ReadReq_mshr_misses::total 417626 # number of ReadReq MSHR misses 694system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298504 # number of WriteReq MSHR misses 695system.cpu.dcache.WriteReq_mshr_misses::total 298504 # number of WriteReq MSHR misses 696system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121419 # number of SoftPFReq MSHR misses 697system.cpu.dcache.SoftPFReq_mshr_misses::total 121419 # number of SoftPFReq MSHR misses 698system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8240 # number of LoadLockedReq MSHR misses 699system.cpu.dcache.LoadLockedReq_mshr_misses::total 8240 # number of LoadLockedReq MSHR misses 700system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 701system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 702system.cpu.dcache.demand_mshr_misses::cpu.data 716130 # number of demand (read+write) MSHR misses 703system.cpu.dcache.demand_mshr_misses::total 716130 # number of demand (read+write) MSHR misses 704system.cpu.dcache.overall_mshr_misses::cpu.data 837549 # number of overall MSHR misses 705system.cpu.dcache.overall_mshr_misses::total 837549 # number of overall MSHR misses 706system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable 707system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable 708system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 709system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable 710system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 711system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses 712system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6547764500 # number of ReadReq MSHR miss cycles 713system.cpu.dcache.ReadReq_mshr_miss_latency::total 6547764500 # number of ReadReq MSHR miss cycles 714system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19179621500 # number of WriteReq MSHR miss cycles 715system.cpu.dcache.WriteReq_mshr_miss_latency::total 19179621500 # number of WriteReq MSHR miss cycles 716system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1710969500 # number of SoftPFReq MSHR miss cycles 717system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1710969500 # number of SoftPFReq MSHR miss cycles 718system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 114416000 # number of LoadLockedReq MSHR miss cycles 719system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 114416000 # number of LoadLockedReq MSHR miss cycles 720system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 721system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles 722system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25727386000 # number of demand (read+write) MSHR miss cycles 723system.cpu.dcache.demand_mshr_miss_latency::total 25727386000 # number of demand (read+write) MSHR miss cycles 724system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27438355500 # number of overall MSHR miss cycles 725system.cpu.dcache.overall_mshr_miss_latency::total 27438355500 # number of overall MSHR miss cycles 726system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277881000 # number of ReadReq MSHR uncacheable cycles 727system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277881000 # number of ReadReq MSHR uncacheable cycles 728system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6277881000 # number of overall MSHR uncacheable cycles 729system.cpu.dcache.overall_mshr_uncacheable_latency::total 6277881000 # number of overall MSHR uncacheable cycles 730system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017764 # mshr miss rate for ReadReq accesses 731system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017764 # mshr miss rate for ReadReq accesses 732system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015869 # mshr miss rate for WriteReq accesses 733system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015869 # mshr miss rate for WriteReq accesses 734system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230759 # mshr miss rate for SoftPFReq accesses 735system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230759 # mshr miss rate for SoftPFReq accesses 736system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017682 # mshr miss rate for LoadLockedReq accesses 737system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017682 # mshr miss rate for LoadLockedReq accesses 738system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 739system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 740system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016922 # mshr miss rate for demand accesses 741system.cpu.dcache.demand_mshr_miss_rate::total 0.016922 # mshr miss rate for demand accesses 742system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019548 # mshr miss rate for overall accesses 743system.cpu.dcache.overall_mshr_miss_rate::total 0.019548 # mshr miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.536537 # average ReadReq mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.536537 # average ReadReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64252.477354 # average WriteReq mshr miss latency 747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64252.477354 # average WriteReq mshr miss latency 748system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.447796 # average SoftPFReq mshr miss latency 749system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.447796 # average SoftPFReq mshr miss latency 750system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13885.436893 # average LoadLockedReq mshr miss latency 751system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13885.436893 # average LoadLockedReq mshr miss latency 752system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 753system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency 754system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551 # average overall mshr miss latency 755system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551 # average overall mshr miss latency 756system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800 # average overall mshr miss latency 757system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency 758system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency 759system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency 760system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency 761system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency 762system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 763system.cpu.icache.tags.replacements 2894371 # number of replacements 764system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use 765system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks. 766system.cpu.icache.tags.sampled_refs 2894883 # Sample count of references to valid blocks. 767system.cpu.icache.tags.avg_refs 18.802260 # Average number of references to valid blocks. 768system.cpu.icache.tags.warmup_cycle 18407091500 # Cycle when the warmup percentage was hit. 769system.cpu.icache.tags.occ_blocks::cpu.inst 511.208818 # Average occupied blocks per requestor 770system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy 771system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy 772system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 773system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 774system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id 775system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 776system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 777system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses 778system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses 779system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 780system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits 781system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits 782system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits 783system.cpu.icache.demand_hits::total 54430342 # number of demand (read+write) hits 784system.cpu.icache.overall_hits::cpu.inst 54430342 # number of overall hits 785system.cpu.icache.overall_hits::total 54430342 # number of overall hits 786system.cpu.icache.ReadReq_misses::cpu.inst 2894895 # number of ReadReq misses 787system.cpu.icache.ReadReq_misses::total 2894895 # number of ReadReq misses 788system.cpu.icache.demand_misses::cpu.inst 2894895 # number of demand (read+write) misses 789system.cpu.icache.demand_misses::total 2894895 # number of demand (read+write) misses 790system.cpu.icache.overall_misses::cpu.inst 2894895 # number of overall misses 791system.cpu.icache.overall_misses::total 2894895 # number of overall misses 792system.cpu.icache.ReadReq_miss_latency::cpu.inst 40452971500 # number of ReadReq miss cycles 793system.cpu.icache.ReadReq_miss_latency::total 40452971500 # number of ReadReq miss cycles 794system.cpu.icache.demand_miss_latency::cpu.inst 40452971500 # number of demand (read+write) miss cycles 795system.cpu.icache.demand_miss_latency::total 40452971500 # number of demand (read+write) miss cycles 796system.cpu.icache.overall_miss_latency::cpu.inst 40452971500 # number of overall miss cycles 797system.cpu.icache.overall_miss_latency::total 40452971500 # number of overall miss cycles 798system.cpu.icache.ReadReq_accesses::cpu.inst 57325237 # number of ReadReq accesses(hits+misses) 799system.cpu.icache.ReadReq_accesses::total 57325237 # number of ReadReq accesses(hits+misses) 800system.cpu.icache.demand_accesses::cpu.inst 57325237 # number of demand (read+write) accesses 801system.cpu.icache.demand_accesses::total 57325237 # number of demand (read+write) accesses 802system.cpu.icache.overall_accesses::cpu.inst 57325237 # number of overall (read+write) accesses 803system.cpu.icache.overall_accesses::total 57325237 # number of overall (read+write) accesses 804system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050499 # miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_miss_rate::total 0.050499 # miss rate for ReadReq accesses 806system.cpu.icache.demand_miss_rate::cpu.inst 0.050499 # miss rate for demand accesses 807system.cpu.icache.demand_miss_rate::total 0.050499 # miss rate for demand accesses 808system.cpu.icache.overall_miss_rate::cpu.inst 0.050499 # miss rate for overall accesses 809system.cpu.icache.overall_miss_rate::total 0.050499 # miss rate for overall accesses 810system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.899399 # average ReadReq miss latency 811system.cpu.icache.ReadReq_avg_miss_latency::total 13973.899399 # average ReadReq miss latency 812system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.899399 # average overall miss latency 813system.cpu.icache.demand_avg_miss_latency::total 13973.899399 # average overall miss latency 814system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.899399 # average overall miss latency 815system.cpu.icache.overall_avg_miss_latency::total 13973.899399 # average overall miss latency 816system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 817system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 818system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 819system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 820system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 821system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 822system.cpu.icache.writebacks::writebacks 2894371 # number of writebacks 823system.cpu.icache.writebacks::total 2894371 # number of writebacks 824system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894895 # number of ReadReq MSHR misses 825system.cpu.icache.ReadReq_mshr_misses::total 2894895 # number of ReadReq MSHR misses 826system.cpu.icache.demand_mshr_misses::cpu.inst 2894895 # number of demand (read+write) MSHR misses 827system.cpu.icache.demand_mshr_misses::total 2894895 # number of demand (read+write) MSHR misses 828system.cpu.icache.overall_mshr_misses::cpu.inst 2894895 # number of overall MSHR misses 829system.cpu.icache.overall_mshr_misses::total 2894895 # number of overall MSHR misses 830system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable 831system.cpu.icache.ReadReq_mshr_uncacheable::total 3763 # number of ReadReq MSHR uncacheable 832system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses 833system.cpu.icache.overall_mshr_uncacheable_misses::total 3763 # number of overall MSHR uncacheable misses 834system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37558077500 # number of ReadReq MSHR miss cycles 835system.cpu.icache.ReadReq_mshr_miss_latency::total 37558077500 # number of ReadReq MSHR miss cycles 836system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37558077500 # number of demand (read+write) MSHR miss cycles 837system.cpu.icache.demand_mshr_miss_latency::total 37558077500 # number of demand (read+write) MSHR miss cycles 838system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37558077500 # number of overall MSHR miss cycles 839system.cpu.icache.overall_mshr_miss_latency::total 37558077500 # number of overall MSHR miss cycles 840system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485921500 # number of ReadReq MSHR uncacheable cycles 841system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485921500 # number of ReadReq MSHR uncacheable cycles 842system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485921500 # number of overall MSHR uncacheable cycles 843system.cpu.icache.overall_mshr_uncacheable_latency::total 485921500 # number of overall MSHR uncacheable cycles 844system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050499 # mshr miss rate for ReadReq accesses 845system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050499 # mshr miss rate for ReadReq accesses 846system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050499 # mshr miss rate for demand accesses 847system.cpu.icache.demand_mshr_miss_rate::total 0.050499 # mshr miss rate for demand accesses 848system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050499 # mshr miss rate for overall accesses 849system.cpu.icache.overall_mshr_miss_rate::total 0.050499 # mshr miss rate for overall accesses 850system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12973.899744 # average ReadReq mshr miss latency 851system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12973.899744 # average ReadReq mshr miss latency 852system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency 853system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency 854system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency 855system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency 856system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency 857system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency 858system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency 859system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency 860system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 861system.cpu.l2cache.tags.replacements 96490 # number of replacements 862system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use 863system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks. 864system.cpu.l2cache.tags.sampled_refs 161737 # Sample count of references to valid blocks. 865system.cpu.l2cache.tags.avg_refs 43.434700 # Average number of references to valid blocks. 866system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 867system.cpu.l2cache.tags.occ_blocks::writebacks 47281.634154 # Average occupied blocks per requestor 868system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 66.002490 # Average occupied blocks per requestor 869system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000511 # Average occupied blocks per requestor 870system.cpu.l2cache.tags.occ_blocks::cpu.inst 12184.043868 # Average occupied blocks per requestor 871system.cpu.l2cache.tags.occ_blocks::cpu.data 5484.988939 # Average occupied blocks per requestor 872system.cpu.l2cache.tags.occ_percent::writebacks 0.721460 # Average percentage of cache occupancy 873system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001007 # Average percentage of cache occupancy 874system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 875system.cpu.l2cache.tags.occ_percent::cpu.inst 0.185914 # Average percentage of cache occupancy 876system.cpu.l2cache.tags.occ_percent::cpu.data 0.083694 # Average percentage of cache occupancy 877system.cpu.l2cache.tags.occ_percent::total 0.992076 # Average percentage of cache occupancy 878system.cpu.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id 879system.cpu.l2cache.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id 880system.cpu.l2cache.tags.age_task_id_blocks_1023::4 54 # Occupied blocks per task id 881system.cpu.l2cache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 882system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 883system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2277 # Occupied blocks per task id 884system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6859 # Occupied blocks per task id 885system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55942 # Occupied blocks per task id 886system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000824 # Percentage of cache occupancy per task id 887system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id 888system.cpu.l2cache.tags.tag_accesses 60430282 # Number of tag accesses 889system.cpu.l2cache.tags.data_accesses 60430282 # Number of data accesses 890system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 891system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71969 # number of ReadReq hits 892system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4812 # number of ReadReq hits 893system.cpu.l2cache.ReadReq_hits::total 76781 # number of ReadReq hits 894system.cpu.l2cache.WritebackDirty_hits::writebacks 699681 # number of WritebackDirty hits 895system.cpu.l2cache.WritebackDirty_hits::total 699681 # number of WritebackDirty hits 896system.cpu.l2cache.WritebackClean_hits::writebacks 2843248 # number of WritebackClean hits 897system.cpu.l2cache.WritebackClean_hits::total 2843248 # number of WritebackClean hits 898system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits 899system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits 900system.cpu.l2cache.ReadExReq_hits::cpu.data 164802 # number of ReadExReq hits 901system.cpu.l2cache.ReadExReq_hits::total 164802 # number of ReadExReq hits 902system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2871936 # number of ReadCleanReq hits 903system.cpu.l2cache.ReadCleanReq_hits::total 2871936 # number of ReadCleanReq hits 904system.cpu.l2cache.ReadSharedReq_hits::cpu.data 532893 # number of ReadSharedReq hits 905system.cpu.l2cache.ReadSharedReq_hits::total 532893 # number of ReadSharedReq hits 906system.cpu.l2cache.demand_hits::cpu.dtb.walker 71969 # number of demand (read+write) hits 907system.cpu.l2cache.demand_hits::cpu.itb.walker 4812 # number of demand (read+write) hits 908system.cpu.l2cache.demand_hits::cpu.inst 2871936 # number of demand (read+write) hits 909system.cpu.l2cache.demand_hits::cpu.data 697695 # number of demand (read+write) hits 910system.cpu.l2cache.demand_hits::total 3646412 # number of demand (read+write) hits 911system.cpu.l2cache.overall_hits::cpu.dtb.walker 71969 # number of overall hits 912system.cpu.l2cache.overall_hits::cpu.itb.walker 4812 # number of overall hits 913system.cpu.l2cache.overall_hits::cpu.inst 2871936 # number of overall hits 914system.cpu.l2cache.overall_hits::cpu.data 697695 # number of overall hits 915system.cpu.l2cache.overall_hits::total 3646412 # number of overall hits 916system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 123 # number of ReadReq misses 917system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 918system.cpu.l2cache.ReadReq_misses::total 124 # number of ReadReq misses 919system.cpu.l2cache.UpgradeReq_misses::cpu.data 2729 # number of UpgradeReq misses 920system.cpu.l2cache.UpgradeReq_misses::total 2729 # number of UpgradeReq misses 921system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 922system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 923system.cpu.l2cache.ReadExReq_misses::cpu.data 130929 # number of ReadExReq misses 924system.cpu.l2cache.ReadExReq_misses::total 130929 # number of ReadExReq misses 925system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22929 # number of ReadCleanReq misses 926system.cpu.l2cache.ReadCleanReq_misses::total 22929 # number of ReadCleanReq misses 927system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14387 # number of ReadSharedReq misses 928system.cpu.l2cache.ReadSharedReq_misses::total 14387 # number of ReadSharedReq misses 929system.cpu.l2cache.demand_misses::cpu.dtb.walker 123 # number of demand (read+write) misses 930system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 931system.cpu.l2cache.demand_misses::cpu.inst 22929 # number of demand (read+write) misses 932system.cpu.l2cache.demand_misses::cpu.data 145316 # number of demand (read+write) misses 933system.cpu.l2cache.demand_misses::total 168369 # number of demand (read+write) misses 934system.cpu.l2cache.overall_misses::cpu.dtb.walker 123 # number of overall misses 935system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 936system.cpu.l2cache.overall_misses::cpu.inst 22929 # number of overall misses 937system.cpu.l2cache.overall_misses::cpu.data 145316 # number of overall misses 938system.cpu.l2cache.overall_misses::total 168369 # number of overall misses 939system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 17201000 # number of ReadReq miss cycles 940system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 132500 # number of ReadReq miss cycles 941system.cpu.l2cache.ReadReq_miss_latency::total 17333500 # number of ReadReq miss cycles 942system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2805500 # number of UpgradeReq miss cycles 943system.cpu.l2cache.UpgradeReq_miss_latency::total 2805500 # number of UpgradeReq miss cycles 944system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 945system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 946system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16777223500 # number of ReadExReq miss cycles 947system.cpu.l2cache.ReadExReq_miss_latency::total 16777223500 # number of ReadExReq miss cycles 948system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2992993000 # number of ReadCleanReq miss cycles 949system.cpu.l2cache.ReadCleanReq_miss_latency::total 2992993000 # number of ReadCleanReq miss cycles 950system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1908318000 # number of ReadSharedReq miss cycles 951system.cpu.l2cache.ReadSharedReq_miss_latency::total 1908318000 # number of ReadSharedReq miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17201000 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 132500 # number of demand (read+write) miss cycles 954system.cpu.l2cache.demand_miss_latency::cpu.inst 2992993000 # number of demand (read+write) miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.data 18685541500 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::total 21695868000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17201000 # number of overall miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 132500 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::cpu.inst 2992993000 # number of overall miss cycles 960system.cpu.l2cache.overall_miss_latency::cpu.data 18685541500 # number of overall miss cycles 961system.cpu.l2cache.overall_miss_latency::total 21695868000 # number of overall miss cycles 962system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 72092 # number of ReadReq accesses(hits+misses) 963system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4813 # number of ReadReq accesses(hits+misses) 964system.cpu.l2cache.ReadReq_accesses::total 76905 # number of ReadReq accesses(hits+misses) 965system.cpu.l2cache.WritebackDirty_accesses::writebacks 699681 # number of WritebackDirty accesses(hits+misses) 966system.cpu.l2cache.WritebackDirty_accesses::total 699681 # number of WritebackDirty accesses(hits+misses) 967system.cpu.l2cache.WritebackClean_accesses::writebacks 2843248 # number of WritebackClean accesses(hits+misses) 968system.cpu.l2cache.WritebackClean_accesses::total 2843248 # number of WritebackClean accesses(hits+misses) 969system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2778 # number of UpgradeReq accesses(hits+misses) 970system.cpu.l2cache.UpgradeReq_accesses::total 2778 # number of UpgradeReq accesses(hits+misses) 971system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 973system.cpu.l2cache.ReadExReq_accesses::cpu.data 295731 # number of ReadExReq accesses(hits+misses) 974system.cpu.l2cache.ReadExReq_accesses::total 295731 # number of ReadExReq accesses(hits+misses) 975system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2894865 # number of ReadCleanReq accesses(hits+misses) 976system.cpu.l2cache.ReadCleanReq_accesses::total 2894865 # number of ReadCleanReq accesses(hits+misses) 977system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 547280 # number of ReadSharedReq accesses(hits+misses) 978system.cpu.l2cache.ReadSharedReq_accesses::total 547280 # number of ReadSharedReq accesses(hits+misses) 979system.cpu.l2cache.demand_accesses::cpu.dtb.walker 72092 # number of demand (read+write) accesses 980system.cpu.l2cache.demand_accesses::cpu.itb.walker 4813 # number of demand (read+write) accesses 981system.cpu.l2cache.demand_accesses::cpu.inst 2894865 # number of demand (read+write) accesses 982system.cpu.l2cache.demand_accesses::cpu.data 843011 # number of demand (read+write) accesses 983system.cpu.l2cache.demand_accesses::total 3814781 # number of demand (read+write) accesses 984system.cpu.l2cache.overall_accesses::cpu.dtb.walker 72092 # number of overall (read+write) accesses 985system.cpu.l2cache.overall_accesses::cpu.itb.walker 4813 # number of overall (read+write) accesses 986system.cpu.l2cache.overall_accesses::cpu.inst 2894865 # number of overall (read+write) accesses 987system.cpu.l2cache.overall_accesses::cpu.data 843011 # number of overall (read+write) accesses 988system.cpu.l2cache.overall_accesses::total 3814781 # number of overall (read+write) accesses 989system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001706 # miss rate for ReadReq accesses 990system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000208 # miss rate for ReadReq accesses 991system.cpu.l2cache.ReadReq_miss_rate::total 0.001612 # miss rate for ReadReq accesses 992system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982361 # miss rate for UpgradeReq accesses 993system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982361 # miss rate for UpgradeReq accesses 994system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 995system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 996system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442730 # miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadExReq_miss_rate::total 0.442730 # miss rate for ReadExReq accesses 998system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007921 # miss rate for ReadCleanReq accesses 999system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007921 # miss rate for ReadCleanReq accesses 1000system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026288 # miss rate for ReadSharedReq accesses 1001system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026288 # miss rate for ReadSharedReq accesses 1002system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001706 # miss rate for demand accesses 1003system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000208 # miss rate for demand accesses 1004system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007921 # miss rate for demand accesses 1005system.cpu.l2cache.demand_miss_rate::cpu.data 0.172377 # miss rate for demand accesses 1006system.cpu.l2cache.demand_miss_rate::total 0.044136 # miss rate for demand accesses 1007system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001706 # miss rate for overall accesses 1008system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000208 # miss rate for overall accesses 1009system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007921 # miss rate for overall accesses 1010system.cpu.l2cache.overall_miss_rate::cpu.data 0.172377 # miss rate for overall accesses 1011system.cpu.l2cache.overall_miss_rate::total 0.044136 # miss rate for overall accesses 1012system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139845.528455 # average ReadReq miss latency 1013system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132500 # average ReadReq miss latency 1014system.cpu.l2cache.ReadReq_avg_miss_latency::total 139786.290323 # average ReadReq miss latency 1015system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1028.032246 # average UpgradeReq miss latency 1016system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1028.032246 # average UpgradeReq miss latency 1017system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency 1018system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency 1019system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128139.858244 # average ReadExReq miss latency 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128139.858244 # average ReadExReq miss latency 1021system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130533.080379 # average ReadCleanReq miss latency 1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130533.080379 # average ReadCleanReq miss latency 1023system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132641.829429 # average ReadSharedReq miss latency 1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132641.829429 # average ReadSharedReq miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139845.528455 # average overall miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130533.080379 # average overall miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128585.575573 # average overall miss latency 1029system.cpu.l2cache.demand_avg_miss_latency::total 128859.041748 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139845.528455 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency 1032system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130533.080379 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128585.575573 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::total 128859.041748 # average overall miss latency 1035system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1036system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1037system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1040system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1041system.cpu.l2cache.writebacks::writebacks 88112 # number of writebacks 1042system.cpu.l2cache.writebacks::total 88112 # number of writebacks 1043system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits 1044system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits 1045system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 140 # number of ReadSharedReq MSHR hits 1046system.cpu.l2cache.ReadSharedReq_mshr_hits::total 140 # number of ReadSharedReq MSHR hits 1047system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits 1048system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits 1049system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 1050system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits 1051system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits 1052system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits 1053system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 123 # number of ReadReq MSHR misses 1054system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 1055system.cpu.l2cache.ReadReq_mshr_misses::total 124 # number of ReadReq MSHR misses 1056system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2729 # number of UpgradeReq MSHR misses 1057system.cpu.l2cache.UpgradeReq_mshr_misses::total 2729 # number of UpgradeReq MSHR misses 1058system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1059system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1060system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130929 # number of ReadExReq MSHR misses 1061system.cpu.l2cache.ReadExReq_mshr_misses::total 130929 # number of ReadExReq MSHR misses 1062system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22904 # number of ReadCleanReq MSHR misses 1063system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22904 # number of ReadCleanReq MSHR misses 1064system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14247 # number of ReadSharedReq MSHR misses 1065system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14247 # number of ReadSharedReq MSHR misses 1066system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses 1067system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 1068system.cpu.l2cache.demand_mshr_misses::cpu.inst 22904 # number of demand (read+write) MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::cpu.data 145176 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.demand_mshr_misses::total 168204 # number of demand (read+write) MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 1073system.cpu.l2cache.overall_mshr_misses::cpu.inst 22904 # number of overall MSHR misses 1074system.cpu.l2cache.overall_mshr_misses::cpu.data 145176 # number of overall MSHR misses 1075system.cpu.l2cache.overall_mshr_misses::total 168204 # number of overall MSHR misses 1076system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable 1077system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable 1078system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34891 # number of ReadReq MSHR uncacheable 1079system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 1080system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable 1081system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses 1082system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1083system.cpu.l2cache.overall_mshr_uncacheable_misses::total 62474 # number of overall MSHR uncacheable misses 1084system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 15971000 # number of ReadReq MSHR miss cycles 1085system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 122500 # number of ReadReq MSHR miss cycles 1086system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16093500 # number of ReadReq MSHR miss cycles 1087system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185652500 # number of UpgradeReq MSHR miss cycles 1088system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185652500 # number of UpgradeReq MSHR miss cycles 1089system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142000 # number of SCUpgradeReq MSHR miss cycles 1090system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142000 # number of SCUpgradeReq MSHR miss cycles 1091system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15467933500 # number of ReadExReq MSHR miss cycles 1092system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15467933500 # number of ReadExReq MSHR miss cycles 1093system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2761977000 # number of ReadCleanReq MSHR miss cycles 1094system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2761977000 # number of ReadCleanReq MSHR miss cycles 1095system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1748121000 # number of ReadSharedReq MSHR miss cycles 1096system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1748121000 # number of ReadSharedReq MSHR miss cycles 1097system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15971000 # number of demand (read+write) MSHR miss cycles 1098system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) MSHR miss cycles 1099system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2761977000 # number of demand (read+write) MSHR miss cycles 1100system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17216054500 # number of demand (read+write) MSHR miss cycles 1101system.cpu.l2cache.demand_mshr_miss_latency::total 19994125000 # number of demand (read+write) MSHR miss cycles 1102system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15971000 # number of overall MSHR miss cycles 1103system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 122500 # number of overall MSHR miss cycles 1104system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2761977000 # number of overall MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17216054500 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::total 19994125000 # number of overall MSHR miss cycles 1107system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 427218000 # number of ReadReq MSHR uncacheable cycles 1108system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888707000 # number of ReadReq MSHR uncacheable cycles 1109system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315925000 # number of ReadReq MSHR uncacheable cycles 1110system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 427218000 # number of overall MSHR uncacheable cycles 1111system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888707000 # number of overall MSHR uncacheable cycles 1112system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6315925000 # number of overall MSHR uncacheable cycles 1113system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for ReadReq accesses 1114system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for ReadReq accesses 1115system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001612 # mshr miss rate for ReadReq accesses 1116system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982361 # mshr miss rate for UpgradeReq accesses 1117system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982361 # mshr miss rate for UpgradeReq accesses 1118system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1119system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1120system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442730 # mshr miss rate for ReadExReq accesses 1121system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442730 # mshr miss rate for ReadExReq accesses 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadCleanReq accesses 1123system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007912 # mshr miss rate for ReadCleanReq accesses 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026032 # mshr miss rate for ReadSharedReq accesses 1125system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026032 # mshr miss rate for ReadSharedReq accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for demand accesses 1127system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for demand accesses 1128system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for demand accesses 1129system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172211 # mshr miss rate for demand accesses 1130system.cpu.l2cache.demand_mshr_miss_rate::total 0.044093 # mshr miss rate for demand accesses 1131system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for overall accesses 1132system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for overall accesses 1133system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for overall accesses 1134system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172211 # mshr miss rate for overall accesses 1135system.cpu.l2cache.overall_mshr_miss_rate::total 0.044093 # mshr miss rate for overall accesses 1136system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average ReadReq mshr miss latency 1137system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency 1138system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129786.290323 # average ReadReq mshr miss latency 1139system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68029.497985 # average UpgradeReq mshr miss latency 1140system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68029.497985 # average UpgradeReq mshr miss latency 1141system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency 1142system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency 1143system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118139.858244 # average ReadExReq mshr miss latency 1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118139.858244 # average ReadExReq mshr miss latency 1145system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120589.285714 # average ReadCleanReq mshr miss latency 1146system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120589.285714 # average ReadCleanReq mshr miss latency 1147system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122700.989682 # average ReadSharedReq mshr miss latency 1148system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122700.989682 # average ReadSharedReq mshr miss latency 1149system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency 1150system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1151system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency 1152system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency 1153system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency 1154system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency 1155system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1156system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency 1157system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency 1158system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency 1159system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency 1160system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency 1161system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency 1162system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency 1163system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency 1164system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency 1165system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter. 1166system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1167system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1168system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. 1169system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1170system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1171system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1172system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::WritebackDirty 823992 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::WritebackClean 2894371 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::CleanEvict 151399 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::UpgradeReq 2778 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::ReadExReq 295731 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::ReadExResp 295731 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894895 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::ReadSharedReq 547514 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1187system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691656 # Packet count per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2651684 # Packet count per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16008 # Packet count per connected master and slave (bytes) 1190system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160884 # Packet count per connected master and slave (bytes) 1191system.cpu.toL2Bus.pkt_count::total 11520232 # Packet count per connected master and slave (bytes) 1192system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370751872 # Cumulative packet size per connected master and slave (bytes) 1193system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98928925 # Cumulative packet size per connected master and slave (bytes) 1194system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19252 # Cumulative packet size per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288368 # Cumulative packet size per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_size::total 469988417 # Cumulative packet size per connected master and slave (bytes) 1197system.cpu.toL2Bus.snoops 192705 # Total snoops (count) 1198system.cpu.toL2Bus.snoop_fanout::samples 4072528 # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::mean 0.021538 # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::stdev 0.145168 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1202system.cpu.toL2Bus.snoop_fanout::0 3984815 97.85% 97.85% # Request fanout histogram 1203system.cpu.toL2Bus.snoop_fanout::1 87713 2.15% 100.00% # Request fanout histogram 1204system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1206system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::total 4072528 # Request fanout histogram 1209system.cpu.toL2Bus.reqLayer0.occupancy 7427836500 # Layer occupancy (ticks) 1210system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1211system.cpu.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks) 1212system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1213system.cpu.toL2Bus.respLayer0.occupancy 4348460548 # Layer occupancy (ticks) 1214system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1215system.cpu.toL2Bus.respLayer1.occupancy 1310984681 # Layer occupancy (ticks) 1216system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1217system.cpu.toL2Bus.respLayer2.occupancy 11196996 # Layer occupancy (ticks) 1218system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1219system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks) 1220system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1221system.iobus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1222system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1223system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1224system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1225system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1226system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1227system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1228system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1229system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1230system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1231system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1232system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1240system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1241system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1243system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1244system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1245system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1246system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1247system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1250system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1251system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1252system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1253system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1254system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1255system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1267system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1268system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.reqLayer0.occupancy 46452000 # Layer occupancy (ticks) 1273system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1274system.iobus.reqLayer1.occupancy 104000 # Layer occupancy (ticks) 1275system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1276system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) 1277system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1278system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) 1279system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1280system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) 1281system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1282system.iobus.reqLayer7.occupancy 85500 # Layer occupancy (ticks) 1283system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1284system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) 1285system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1286system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) 1287system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1288system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1289system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1290system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 1291system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1292system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 1293system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1294system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) 1295system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1296system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 1297system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1298system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) 1299system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1300system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 1301system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1302system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 1303system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1304system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) 1305system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1306system.iobus.reqLayer23.occupancy 6139500 # Layer occupancy (ticks) 1307system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1308system.iobus.reqLayer24.occupancy 34107000 # Layer occupancy (ticks) 1309system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1310system.iobus.reqLayer25.occupancy 187147502 # Layer occupancy (ticks) 1311system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1312system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1313system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1314system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1315system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1316system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1317system.iocache.tags.replacements 36424 # number of replacements 1318system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use 1319system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1320system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1321system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1322system.iocache.tags.warmup_cycle 274806935000 # Cycle when the warmup percentage was hit. 1323system.iocache.tags.occ_blocks::realview.ide 1.037066 # Average occupied blocks per requestor 1324system.iocache.tags.occ_percent::realview.ide 0.064817 # Average percentage of cache occupancy 1325system.iocache.tags.occ_percent::total 0.064817 # Average percentage of cache occupancy 1326system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1327system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1328system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1329system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1330system.iocache.tags.data_accesses 328122 # Number of data accesses 1331system.iocache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1332system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1333system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1334system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1335system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1336system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1337system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1338system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1339system.iocache.overall_misses::total 36458 # number of overall misses 1340system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles 1341system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles 1342system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles 1343system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles 1344system.iocache.demand_miss_latency::realview.ide 4578036502 # number of demand (read+write) miss cycles 1345system.iocache.demand_miss_latency::total 4578036502 # number of demand (read+write) miss cycles 1346system.iocache.overall_miss_latency::realview.ide 4578036502 # number of overall miss cycles 1347system.iocache.overall_miss_latency::total 4578036502 # number of overall miss cycles 1348system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1349system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1350system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1351system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1352system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1353system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1354system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1355system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses 1356system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1357system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1358system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1359system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1360system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1361system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1362system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1363system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1364system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795 # average ReadReq miss latency 1365system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency 1366system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency 1367system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency 1368system.iocache.demand_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency 1369system.iocache.demand_avg_miss_latency::total 125570.149268 # average overall miss latency 1370system.iocache.overall_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency 1371system.iocache.overall_avg_miss_latency::total 125570.149268 # average overall miss latency 1372system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1373system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1374system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1375system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1376system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1377system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1378system.iocache.writebacks::writebacks 36190 # number of writebacks 1379system.iocache.writebacks::total 36190 # number of writebacks 1380system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1381system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1382system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1383system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1384system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1385system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1386system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1387system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses 1388system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles 1389system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles 1390system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles 1391system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles 1392system.iocache.demand_mshr_miss_latency::realview.ide 2753710997 # number of demand (read+write) MSHR miss cycles 1393system.iocache.demand_mshr_miss_latency::total 2753710997 # number of demand (read+write) MSHR miss cycles 1394system.iocache.overall_mshr_miss_latency::realview.ide 2753710997 # number of overall MSHR miss cycles 1395system.iocache.overall_mshr_miss_latency::total 2753710997 # number of overall MSHR miss cycles 1396system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1397system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1398system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1399system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1400system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1401system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1402system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1403system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1404system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency 1405system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency 1406system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency 1407system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency 1408system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency 1409system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency 1410system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency 1411system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency 1412system.membus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1413system.membus.trans_dist::ReadReq 34891 # Transaction distribution 1414system.membus.trans_dist::ReadResp 72400 # Transaction distribution 1415system.membus.trans_dist::WriteReq 27583 # Transaction distribution 1416system.membus.trans_dist::WriteResp 27583 # Transaction distribution 1417system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution 1418system.membus.trans_dist::CleanEvict 8612 # Transaction distribution 1419system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution 1420system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1421system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1422system.membus.trans_dist::ReadExReq 129077 # Transaction distribution 1423system.membus.trans_dist::ReadExResp 129077 # Transaction distribution 1424system.membus.trans_dist::ReadSharedReq 37509 # Transaction distribution 1425system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1426system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1427system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1428system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) 1429system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450878 # Packet count per connected master and slave (bytes) 1430system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558440 # Packet count per connected master and slave (bytes) 1431system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1432system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) 1433system.membus.pkt_count::total 631337 # Packet count per connected master and slave (bytes) 1434system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1435system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) 1436system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) 1437system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16527584 # Cumulative packet size per connected master and slave (bytes) 1438system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16691357 # Cumulative packet size per connected master and slave (bytes) 1439system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1440system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1441system.membus.pkt_size::total 19008477 # Cumulative packet size per connected master and slave (bytes) 1442system.membus.snoops 506 # Total snoops (count) 1443system.membus.snoop_fanout::samples 402790 # Request fanout histogram 1444system.membus.snoop_fanout::mean 1 # Request fanout histogram 1445system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1446system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1447system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1448system.membus.snoop_fanout::1 402790 100.00% 100.00% # Request fanout histogram 1449system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1450system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1451system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1452system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1453system.membus.snoop_fanout::total 402790 # Request fanout histogram 1454system.membus.reqLayer0.occupancy 87987000 # Layer occupancy (ticks) 1455system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1456system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) 1457system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1458system.membus.reqLayer2.occupancy 1702000 # Layer occupancy (ticks) 1459system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1460system.membus.reqLayer5.occupancy 879699870 # Layer occupancy (ticks) 1461system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1462system.membus.respLayer2.occupancy 990225250 # Layer occupancy (ticks) 1463system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1464system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks) 1465system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1466system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1467system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1468system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1469system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1470system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1471system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1472system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1473system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1474system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1475system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1476system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1477system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1478system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1479system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1480system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1481system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1482system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1483system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1484system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1485system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1486system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1487system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1488system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1489system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1490system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1491system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1492system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1493system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1494system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1495system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1496system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1497system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1498system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1499system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1500system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1501system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1502system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1503system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1504system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1505system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1506system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1507system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1508system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1509system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1510system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1511system.realview.ethernet.droppedPackets 0 # number of packets dropped 1512system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1513system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1514system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1515system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1516system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1517system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1518system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1519system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1520system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1521system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1522system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1523system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1524system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1525system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1526system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1527system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1528system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1529system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1530system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1531system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1532system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1533system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1534system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 1535 1536---------- End Simulation Statistics ---------- 1537