stats.txt revision 11336:b318499f676c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858536 # Number of seconds simulated 4sim_ticks 2858536032500 # Number of ticks simulated 5final_tick 2858536032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 177299 # Simulator instruction rate (inst/s) 8host_op_rate 214372 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4522420422 # Simulator tick rate (ticks/s) 10host_mem_usage 585260 # Number of bytes of host memory used 11host_seconds 632.08 # Real time elapsed on the host 12sim_insts 112067614 # Number of instructions simulated 13sim_ops 135500271 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9152172 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10869356 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7939328 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7956852 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 143524 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 170355 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 124052 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 128433 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2799 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 597542 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3201699 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3802420 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 597542 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 597542 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2777411 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2783541 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2777411 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2799 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 597542 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3207829 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6585961 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 170355 # Number of read requests accepted 55system.physmem.writeReqs 128433 # Number of write requests accepted 56system.physmem.readBursts 170355 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 128433 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10894592 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7969344 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10869356 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7956852 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10771 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10790 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10898 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10736 # Per bank write bursts 70system.physmem.perBankRdBursts::4 14068 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10207 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11005 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10952 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9928 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10232 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9939 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9163 # Per bank write bursts 78system.physmem.perBankRdBursts::12 10281 # Per bank write bursts 79system.physmem.perBankRdBursts::13 11195 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10251 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9812 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8074 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8145 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8532 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8274 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7651 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7419 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7942 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8023 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7561 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7722 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7504 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7050 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7678 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8296 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7536 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7114 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 100system.physmem.totGap 2858535588000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 543 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 169798 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 124052 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 163475 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 6450 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2999 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6966 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6332 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 7132 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6386 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6374 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6606 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6977 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 7506 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8488 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7336 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7586 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 8729 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7393 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7050 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7132 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1109 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 326 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 234 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 132 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 61427 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 307.093102 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 182.837118 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 324.066728 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22431 36.52% 36.52% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14913 24.28% 60.79% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6673 10.86% 71.66% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3644 5.93% 77.59% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2598 4.23% 81.82% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 2007 3.27% 85.09% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1018 1.66% 86.74% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1090 1.77% 88.52% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7053 11.48% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 61427 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6076 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 28.016458 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 575.560734 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6075 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 6076 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.495967 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.543257 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 14.157568 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5370 88.40% 88.40% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 94 1.55% 89.94% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 44 0.72% 90.67% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 49 0.81% 91.47% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 46 0.76% 92.23% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 25 0.41% 92.64% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 47 0.77% 93.42% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 10 0.16% 93.58% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 146 2.40% 95.98% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 3 0.05% 96.03% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 8 0.13% 96.16% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 10 0.16% 96.33% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 76 1.25% 97.58% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 4 0.07% 97.65% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 5 0.08% 97.73% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 24 0.40% 98.12% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 88 1.45% 99.57% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 2 0.03% 99.60% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::128-131 8 0.13% 99.75% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::140-143 1 0.02% 99.77% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::144-147 8 0.13% 99.90% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads 262system.physmem.totQLat 1806632250 # Total ticks spent queuing 263system.physmem.totMemAccLat 4998407250 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 851140000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 10613.01 # Average queueing delay per DRAM burst 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 267system.physmem.avgMemAccLat 29363.01 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.05 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 277system.physmem.avgWrQLen 21.23 # Average write queue length when enqueuing 278system.physmem.readRowHits 139599 # Number of row buffer hits during reads 279system.physmem.writeRowHits 93721 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes 282system.physmem.avgGap 9567103.06 # Average gap between requests 283system.physmem.pageHitRate 79.15 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 242282880 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 132198000 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 697530600 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 415063440 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) 289system.physmem_0.actBackEnergy 87013655235 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 1638793270500 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 1913999599215 # Total energy per rank (pJ) 292system.physmem_0.averagePower 669.573595 # Core power per rank (mW) 293system.physmem_0.memoryStateTime::IDLE 2726118833250 # Time in different power states 294system.physmem_0.memoryStateTime::REF 95452760000 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 296system.physmem_0.memoryStateTime::ACT 36964415750 # Time in different power states 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 630240000 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 391780800 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 85155956550 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 1640422830750 # Energy for precharge background per rank (pJ) 305system.physmem_1.totalEnergy 1913649653535 # Total energy per rank (pJ) 306system.physmem_1.averagePower 669.451174 # Core power per rank (mW) 307system.physmem_1.memoryStateTime::IDLE 2728842952750 # Time in different power states 308system.physmem_1.memoryStateTime::REF 95452760000 # Time in different power states 309system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 310system.physmem_1.memoryStateTime::ACT 34240173750 # Time in different power states 311system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 312system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 313system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 314system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 315system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 316system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 317system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 318system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 323system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) 324system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 325system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 326system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 327system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 328system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 329system.cf0.dma_write_txs 631 # Number of DMA write transactions. 330system.cpu.branchPred.lookups 31018850 # Number of BP lookups 331system.cpu.branchPred.condPredicted 16837096 # Number of conditional branches predicted 332system.cpu.branchPred.condIncorrect 2510697 # Number of conditional branches incorrect 333system.cpu.branchPred.BTBLookups 18467994 # Number of BTB lookups 334system.cpu.branchPred.BTBHits 13332341 # Number of BTB hits 335system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 336system.cpu.branchPred.BTBHitPct 72.191603 # BTB Hit Percentage 337system.cpu.branchPred.usedRAS 7836957 # Number of times the RAS was used to get a target. 338system.cpu.branchPred.RASInCorrect 1518082 # Number of incorrect RAS predictions. 339system.cpu_clk_domain.clock 500 # Clock period in ticks 340system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 349system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 350system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 351system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 352system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 353system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 354system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 355system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 356system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 357system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 358system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 359system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 360system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 361system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 369system.cpu.dtb.walker.walks 66340 # Table walker walks requested 370system.cpu.dtb.walker.walksShort 66340 # Table walker walks initiated with short descriptors 371system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43350 # Level at which table walker walks with short descriptors terminate 372system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22990 # Level at which table walker walks with short descriptors terminate 373system.cpu.dtb.walker.walkWaitTime::samples 66340 # Table walker wait (enqueue to first request) latency 374system.cpu.dtb.walker.walkWaitTime::0 66340 100.00% 100.00% # Table walker wait (enqueue to first request) latency 375system.cpu.dtb.walker.walkWaitTime::total 66340 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkCompletionTime::samples 7812 # Table walker service (enqueue to completion) latency 377system.cpu.dtb.walker.walkCompletionTime::mean 12842.037890 # Table walker service (enqueue to completion) latency 378system.cpu.dtb.walker.walkCompletionTime::gmean 10664.293591 # Table walker service (enqueue to completion) latency 379system.cpu.dtb.walker.walkCompletionTime::stdev 8573.106392 # Table walker service (enqueue to completion) latency 380system.cpu.dtb.walker.walkCompletionTime::0-32767 7804 99.90% 99.90% # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::total 7812 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution 385system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution 386system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution 387system.cpu.dtb.walker.walkPageSizes::4K 6422 82.21% 82.21% # Table walker page sizes translated 388system.cpu.dtb.walker.walkPageSizes::1M 1390 17.79% 100.00% # Table walker page sizes translated 389system.cpu.dtb.walker.walkPageSizes::total 7812 # Table walker page sizes translated 390system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66340 # Table walker requests started/completed, data/inst 391system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 392system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66340 # Table walker requests started/completed, data/inst 393system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7812 # Table walker requests started/completed, data/inst 394system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7812 # Table walker requests started/completed, data/inst 396system.cpu.dtb.walker.walkRequestOrigin::total 74152 # Table walker requests started/completed, data/inst 397system.cpu.dtb.inst_hits 0 # ITB inst hits 398system.cpu.dtb.inst_misses 0 # ITB inst misses 399system.cpu.dtb.read_hits 24767530 # DTB read hits 400system.cpu.dtb.read_misses 59359 # DTB read misses 401system.cpu.dtb.write_hits 19448397 # DTB write hits 402system.cpu.dtb.write_misses 6981 # DTB write misses 403system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 404system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 405system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 406system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 407system.cpu.dtb.flush_entries 4358 # Number of entries that have been flushed from TLB 408system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions 409system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch 410system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu.dtb.perms_faults 756 # Number of TLB faults due to permissions restrictions 412system.cpu.dtb.read_accesses 24826889 # DTB read accesses 413system.cpu.dtb.write_accesses 19455378 # DTB write accesses 414system.cpu.dtb.inst_accesses 0 # ITB inst accesses 415system.cpu.dtb.hits 44215927 # DTB hits 416system.cpu.dtb.misses 66340 # DTB misses 417system.cpu.dtb.accesses 44282267 # DTB accesses 418system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 419system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 420system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 421system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 422system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 423system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 424system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 427system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 428system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 429system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 430system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 431system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 432system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 433system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 434system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 435system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 436system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 437system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 438system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 439system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 440system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 441system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 442system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 443system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 444system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 445system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 446system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 447system.cpu.itb.walker.walks 5454 # Table walker walks requested 448system.cpu.itb.walker.walksShort 5454 # Table walker walks initiated with short descriptors 449system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate 450system.cpu.itb.walker.walksShortTerminationLevel::Level2 5133 # Level at which table walker walks with short descriptors terminate 451system.cpu.itb.walker.walkWaitTime::samples 5454 # Table walker wait (enqueue to first request) latency 452system.cpu.itb.walker.walkWaitTime::0 5454 100.00% 100.00% # Table walker wait (enqueue to first request) latency 453system.cpu.itb.walker.walkWaitTime::total 5454 # Table walker wait (enqueue to first request) latency 454system.cpu.itb.walker.walkCompletionTime::samples 3187 # Table walker service (enqueue to completion) latency 455system.cpu.itb.walker.walkCompletionTime::mean 13010.982115 # Table walker service (enqueue to completion) latency 456system.cpu.itb.walker.walkCompletionTime::gmean 10938.412651 # Table walker service (enqueue to completion) latency 457system.cpu.itb.walker.walkCompletionTime::stdev 7360.815983 # Table walker service (enqueue to completion) latency 458system.cpu.itb.walker.walkCompletionTime::0-16383 2457 77.09% 77.09% # Table walker service (enqueue to completion) latency 459system.cpu.itb.walker.walkCompletionTime::16384-32767 729 22.87% 99.97% # Table walker service (enqueue to completion) latency 460system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 461system.cpu.itb.walker.walkCompletionTime::total 3187 # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution 463system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution 464system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution 465system.cpu.itb.walker.walkPageSizes::4K 2877 90.27% 90.27% # Table walker page sizes translated 466system.cpu.itb.walker.walkPageSizes::1M 310 9.73% 100.00% # Table walker page sizes translated 467system.cpu.itb.walker.walkPageSizes::total 3187 # Table walker page sizes translated 468system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 469system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5454 # Table walker requests started/completed, data/inst 470system.cpu.itb.walker.walkRequestOrigin_Requested::total 5454 # Table walker requests started/completed, data/inst 471system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 472system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3187 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Completed::total 3187 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin::total 8641 # Table walker requests started/completed, data/inst 475system.cpu.itb.inst_hits 57568551 # ITB inst hits 476system.cpu.itb.inst_misses 5454 # ITB inst misses 477system.cpu.itb.read_hits 0 # DTB read hits 478system.cpu.itb.read_misses 0 # DTB read misses 479system.cpu.itb.write_hits 0 # DTB write hits 480system.cpu.itb.write_misses 0 # DTB write misses 481system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 482system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 483system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 484system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 485system.cpu.itb.flush_entries 2975 # Number of entries that have been flushed from TLB 486system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 487system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 488system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 489system.cpu.itb.perms_faults 8464 # Number of TLB faults due to permissions restrictions 490system.cpu.itb.read_accesses 0 # DTB read accesses 491system.cpu.itb.write_accesses 0 # DTB write accesses 492system.cpu.itb.inst_accesses 57574005 # ITB inst accesses 493system.cpu.itb.hits 57568551 # DTB hits 494system.cpu.itb.misses 5454 # DTB misses 495system.cpu.itb.accesses 57574005 # DTB accesses 496system.cpu.numCycles 333181944 # number of cpu cycles simulated 497system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 498system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 499system.cpu.committedInsts 112067614 # Number of instructions committed 500system.cpu.committedOps 135500271 # Number of ops (including micro ops) committed 501system.cpu.discardedOps 7782146 # Number of ops (including micro ops) which were discarded before commit 502system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching 503system.cpu.quiesceCycles 5383950822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 504system.cpu.cpi 2.973044 # CPI: cycles per instruction 505system.cpu.ipc 0.336356 # IPC: instructions per cycle 506system.cpu.kern.inst.arm 0 # number of arm instructions executed 507system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed 508system.cpu.tickCycles 228532556 # Number of cycles that the object actually ticked 509system.cpu.idleCycles 104649388 # Total number of cycles that the object has spent stopped 510system.cpu.dcache.tags.replacements 842951 # number of replacements 511system.cpu.dcache.tags.tagsinuse 511.899807 # Cycle average of tags in use 512system.cpu.dcache.tags.total_refs 42615127 # Total number of references to valid blocks. 513system.cpu.dcache.tags.sampled_refs 843463 # Sample count of references to valid blocks. 514system.cpu.dcache.tags.avg_refs 50.524003 # Average number of references to valid blocks. 515system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. 516system.cpu.dcache.tags.occ_blocks::cpu.data 511.899807 # Average occupied blocks per requestor 517system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy 518system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy 519system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 520system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 521system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id 522system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id 523system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 524system.cpu.dcache.tags.tag_accesses 176233418 # Number of tag accesses 525system.cpu.dcache.tags.data_accesses 176233418 # Number of data accesses 526system.cpu.dcache.ReadReq_hits::cpu.data 23069734 # number of ReadReq hits 527system.cpu.dcache.ReadReq_hits::total 23069734 # number of ReadReq hits 528system.cpu.dcache.WriteReq_hits::cpu.data 18281775 # number of WriteReq hits 529system.cpu.dcache.WriteReq_hits::total 18281775 # number of WriteReq hits 530system.cpu.dcache.SoftPFReq_hits::cpu.data 356571 # number of SoftPFReq hits 531system.cpu.dcache.SoftPFReq_hits::total 356571 # number of SoftPFReq hits 532system.cpu.dcache.LoadLockedReq_hits::cpu.data 443857 # number of LoadLockedReq hits 533system.cpu.dcache.LoadLockedReq_hits::total 443857 # number of LoadLockedReq hits 534system.cpu.dcache.StoreCondReq_hits::cpu.data 460299 # number of StoreCondReq hits 535system.cpu.dcache.StoreCondReq_hits::total 460299 # number of StoreCondReq hits 536system.cpu.dcache.demand_hits::cpu.data 41351509 # number of demand (read+write) hits 537system.cpu.dcache.demand_hits::total 41351509 # number of demand (read+write) hits 538system.cpu.dcache.overall_hits::cpu.data 41708080 # number of overall hits 539system.cpu.dcache.overall_hits::total 41708080 # number of overall hits 540system.cpu.dcache.ReadReq_misses::cpu.data 494516 # number of ReadReq misses 541system.cpu.dcache.ReadReq_misses::total 494516 # number of ReadReq misses 542system.cpu.dcache.WriteReq_misses::cpu.data 548690 # number of WriteReq misses 543system.cpu.dcache.WriteReq_misses::total 548690 # number of WriteReq misses 544system.cpu.dcache.SoftPFReq_misses::cpu.data 169778 # number of SoftPFReq misses 545system.cpu.dcache.SoftPFReq_misses::total 169778 # number of SoftPFReq misses 546system.cpu.dcache.LoadLockedReq_misses::cpu.data 22259 # number of LoadLockedReq misses 547system.cpu.dcache.LoadLockedReq_misses::total 22259 # number of LoadLockedReq misses 548system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 549system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 550system.cpu.dcache.demand_misses::cpu.data 1043206 # number of demand (read+write) misses 551system.cpu.dcache.demand_misses::total 1043206 # number of demand (read+write) misses 552system.cpu.dcache.overall_misses::cpu.data 1212984 # number of overall misses 553system.cpu.dcache.overall_misses::total 1212984 # number of overall misses 554system.cpu.dcache.ReadReq_miss_latency::cpu.data 8031253000 # number of ReadReq miss cycles 555system.cpu.dcache.ReadReq_miss_latency::total 8031253000 # number of ReadReq miss cycles 556system.cpu.dcache.WriteReq_miss_latency::cpu.data 35635370481 # number of WriteReq miss cycles 557system.cpu.dcache.WriteReq_miss_latency::total 35635370481 # number of WriteReq miss cycles 558system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293366000 # number of LoadLockedReq miss cycles 559system.cpu.dcache.LoadLockedReq_miss_latency::total 293366000 # number of LoadLockedReq miss cycles 560system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 561system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles 562system.cpu.dcache.demand_miss_latency::cpu.data 43666623481 # number of demand (read+write) miss cycles 563system.cpu.dcache.demand_miss_latency::total 43666623481 # number of demand (read+write) miss cycles 564system.cpu.dcache.overall_miss_latency::cpu.data 43666623481 # number of overall miss cycles 565system.cpu.dcache.overall_miss_latency::total 43666623481 # number of overall miss cycles 566system.cpu.dcache.ReadReq_accesses::cpu.data 23564250 # number of ReadReq accesses(hits+misses) 567system.cpu.dcache.ReadReq_accesses::total 23564250 # number of ReadReq accesses(hits+misses) 568system.cpu.dcache.WriteReq_accesses::cpu.data 18830465 # number of WriteReq accesses(hits+misses) 569system.cpu.dcache.WriteReq_accesses::total 18830465 # number of WriteReq accesses(hits+misses) 570system.cpu.dcache.SoftPFReq_accesses::cpu.data 526349 # number of SoftPFReq accesses(hits+misses) 571system.cpu.dcache.SoftPFReq_accesses::total 526349 # number of SoftPFReq accesses(hits+misses) 572system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466116 # number of LoadLockedReq accesses(hits+misses) 573system.cpu.dcache.LoadLockedReq_accesses::total 466116 # number of LoadLockedReq accesses(hits+misses) 574system.cpu.dcache.StoreCondReq_accesses::cpu.data 460301 # number of StoreCondReq accesses(hits+misses) 575system.cpu.dcache.StoreCondReq_accesses::total 460301 # number of StoreCondReq accesses(hits+misses) 576system.cpu.dcache.demand_accesses::cpu.data 42394715 # number of demand (read+write) accesses 577system.cpu.dcache.demand_accesses::total 42394715 # number of demand (read+write) accesses 578system.cpu.dcache.overall_accesses::cpu.data 42921064 # number of overall (read+write) accesses 579system.cpu.dcache.overall_accesses::total 42921064 # number of overall (read+write) accesses 580system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020986 # miss rate for ReadReq accesses 581system.cpu.dcache.ReadReq_miss_rate::total 0.020986 # miss rate for ReadReq accesses 582system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029138 # miss rate for WriteReq accesses 583system.cpu.dcache.WriteReq_miss_rate::total 0.029138 # miss rate for WriteReq accesses 584system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322558 # miss rate for SoftPFReq accesses 585system.cpu.dcache.SoftPFReq_miss_rate::total 0.322558 # miss rate for SoftPFReq accesses 586system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047754 # miss rate for LoadLockedReq accesses 587system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047754 # miss rate for LoadLockedReq accesses 588system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 589system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 590system.cpu.dcache.demand_miss_rate::cpu.data 0.024607 # miss rate for demand accesses 591system.cpu.dcache.demand_miss_rate::total 0.024607 # miss rate for demand accesses 592system.cpu.dcache.overall_miss_rate::cpu.data 0.028261 # miss rate for overall accesses 593system.cpu.dcache.overall_miss_rate::total 0.028261 # miss rate for overall accesses 594system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16240.633266 # average ReadReq miss latency 595system.cpu.dcache.ReadReq_avg_miss_latency::total 16240.633266 # average ReadReq miss latency 596system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64946.272906 # average WriteReq miss latency 597system.cpu.dcache.WriteReq_avg_miss_latency::total 64946.272906 # average WriteReq miss latency 598system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13179.657667 # average LoadLockedReq miss latency 599system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13179.657667 # average LoadLockedReq miss latency 600system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency 601system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency 602system.cpu.dcache.demand_avg_miss_latency::cpu.data 41858.102312 # average overall miss latency 603system.cpu.dcache.demand_avg_miss_latency::total 41858.102312 # average overall miss latency 604system.cpu.dcache.overall_avg_miss_latency::cpu.data 35999.340042 # average overall miss latency 605system.cpu.dcache.overall_avg_miss_latency::total 35999.340042 # average overall miss latency 606system.cpu.dcache.blocked_cycles::no_mshrs 280 # number of cycles access was blocked 607system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 608system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked 609system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 610system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.333333 # average number of cycles each access was blocked 611system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 612system.cpu.dcache.fast_writes 0 # number of fast writes performed 613system.cpu.dcache.cache_copies 0 # number of cache copies performed 614system.cpu.dcache.writebacks::writebacks 700113 # number of writebacks 615system.cpu.dcache.writebacks::total 700113 # number of writebacks 616system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76813 # number of ReadReq MSHR hits 617system.cpu.dcache.ReadReq_mshr_hits::total 76813 # number of ReadReq MSHR hits 618system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249717 # number of WriteReq MSHR hits 619system.cpu.dcache.WriteReq_mshr_hits::total 249717 # number of WriteReq MSHR hits 620system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13991 # number of LoadLockedReq MSHR hits 621system.cpu.dcache.LoadLockedReq_mshr_hits::total 13991 # number of LoadLockedReq MSHR hits 622system.cpu.dcache.demand_mshr_hits::cpu.data 326530 # number of demand (read+write) MSHR hits 623system.cpu.dcache.demand_mshr_hits::total 326530 # number of demand (read+write) MSHR hits 624system.cpu.dcache.overall_mshr_hits::cpu.data 326530 # number of overall MSHR hits 625system.cpu.dcache.overall_mshr_hits::total 326530 # number of overall MSHR hits 626system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417703 # number of ReadReq MSHR misses 627system.cpu.dcache.ReadReq_mshr_misses::total 417703 # number of ReadReq MSHR misses 628system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298973 # number of WriteReq MSHR misses 629system.cpu.dcache.WriteReq_mshr_misses::total 298973 # number of WriteReq MSHR misses 630system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121335 # number of SoftPFReq MSHR misses 631system.cpu.dcache.SoftPFReq_mshr_misses::total 121335 # number of SoftPFReq MSHR misses 632system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8268 # number of LoadLockedReq MSHR misses 633system.cpu.dcache.LoadLockedReq_mshr_misses::total 8268 # number of LoadLockedReq MSHR misses 634system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 635system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 636system.cpu.dcache.demand_mshr_misses::cpu.data 716676 # number of demand (read+write) MSHR misses 637system.cpu.dcache.demand_mshr_misses::total 716676 # number of demand (read+write) MSHR misses 638system.cpu.dcache.overall_mshr_misses::cpu.data 838011 # number of overall MSHR misses 639system.cpu.dcache.overall_mshr_misses::total 838011 # number of overall MSHR misses 640system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 641system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable 642system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 643system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 644system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 645system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 646system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6520814500 # number of ReadReq MSHR miss cycles 647system.cpu.dcache.ReadReq_mshr_miss_latency::total 6520814500 # number of ReadReq MSHR miss cycles 648system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19192223000 # number of WriteReq MSHR miss cycles 649system.cpu.dcache.WriteReq_mshr_miss_latency::total 19192223000 # number of WriteReq MSHR miss cycles 650system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1711136500 # number of SoftPFReq MSHR miss cycles 651system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1711136500 # number of SoftPFReq MSHR miss cycles 652system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115838000 # number of LoadLockedReq MSHR miss cycles 653system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115838000 # number of LoadLockedReq MSHR miss cycles 654system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 655system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles 656system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25713037500 # number of demand (read+write) MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::total 25713037500 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27424174000 # number of overall MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::total 27424174000 # number of overall MSHR miss cycles 660system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277780500 # number of ReadReq MSHR uncacheable cycles 661system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277780500 # number of ReadReq MSHR uncacheable cycles 662system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5083615500 # number of WriteReq MSHR uncacheable cycles 663system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5083615500 # number of WriteReq MSHR uncacheable cycles 664system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11361396000 # number of overall MSHR uncacheable cycles 665system.cpu.dcache.overall_mshr_uncacheable_latency::total 11361396000 # number of overall MSHR uncacheable cycles 666system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017726 # mshr miss rate for ReadReq accesses 667system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017726 # mshr miss rate for ReadReq accesses 668system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015877 # mshr miss rate for WriteReq accesses 669system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015877 # mshr miss rate for WriteReq accesses 670system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230522 # mshr miss rate for SoftPFReq accesses 671system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230522 # mshr miss rate for SoftPFReq accesses 672system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017738 # mshr miss rate for LoadLockedReq accesses 673system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017738 # mshr miss rate for LoadLockedReq accesses 674system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 675system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 676system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016905 # mshr miss rate for demand accesses 677system.cpu.dcache.demand_mshr_miss_rate::total 0.016905 # mshr miss rate for demand accesses 678system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019524 # mshr miss rate for overall accesses 679system.cpu.dcache.overall_mshr_miss_rate::total 0.019524 # mshr miss rate for overall accesses 680system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15611.126805 # average ReadReq mshr miss latency 681system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15611.126805 # average ReadReq mshr miss latency 682system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64193.833557 # average WriteReq mshr miss latency 683system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64193.833557 # average WriteReq mshr miss latency 684system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14102.579635 # average SoftPFReq mshr miss latency 685system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14102.579635 # average SoftPFReq mshr miss latency 686system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14010.401548 # average LoadLockedReq mshr miss latency 687system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14010.401548 # average LoadLockedReq mshr miss latency 688system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 689system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency 690system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35878.189726 # average overall mshr miss latency 691system.cpu.dcache.demand_avg_mshr_miss_latency::total 35878.189726 # average overall mshr miss latency 692system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32725.315061 # average overall mshr miss latency 693system.cpu.dcache.overall_avg_mshr_miss_latency::total 32725.315061 # average overall mshr miss latency 694system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201663.363315 # average ReadReq mshr uncacheable latency 695system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201663.363315 # average ReadReq mshr uncacheable latency 696system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.805539 # average WriteReq mshr uncacheable latency 697system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.805539 # average WriteReq mshr uncacheable latency 698system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193504.036516 # average overall mshr uncacheable latency 699system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193504.036516 # average overall mshr uncacheable latency 700system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 701system.cpu.icache.tags.replacements 2897049 # number of replacements 702system.cpu.icache.tags.tagsinuse 511.208859 # Cycle average of tags in use 703system.cpu.icache.tags.total_refs 54662046 # Total number of references to valid blocks. 704system.cpu.icache.tags.sampled_refs 2897561 # Sample count of references to valid blocks. 705system.cpu.icache.tags.avg_refs 18.864847 # Average number of references to valid blocks. 706system.cpu.icache.tags.warmup_cycle 18409362500 # Cycle when the warmup percentage was hit. 707system.cpu.icache.tags.occ_blocks::cpu.inst 511.208859 # Average occupied blocks per requestor 708system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy 709system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy 710system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 711system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 712system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 714system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 715system.cpu.icache.tags.tag_accesses 60457191 # Number of tag accesses 716system.cpu.icache.tags.data_accesses 60457191 # Number of data accesses 717system.cpu.icache.ReadReq_hits::cpu.inst 54662046 # number of ReadReq hits 718system.cpu.icache.ReadReq_hits::total 54662046 # number of ReadReq hits 719system.cpu.icache.demand_hits::cpu.inst 54662046 # number of demand (read+write) hits 720system.cpu.icache.demand_hits::total 54662046 # number of demand (read+write) hits 721system.cpu.icache.overall_hits::cpu.inst 54662046 # number of overall hits 722system.cpu.icache.overall_hits::total 54662046 # number of overall hits 723system.cpu.icache.ReadReq_misses::cpu.inst 2897573 # number of ReadReq misses 724system.cpu.icache.ReadReq_misses::total 2897573 # number of ReadReq misses 725system.cpu.icache.demand_misses::cpu.inst 2897573 # number of demand (read+write) misses 726system.cpu.icache.demand_misses::total 2897573 # number of demand (read+write) misses 727system.cpu.icache.overall_misses::cpu.inst 2897573 # number of overall misses 728system.cpu.icache.overall_misses::total 2897573 # number of overall misses 729system.cpu.icache.ReadReq_miss_latency::cpu.inst 40485768000 # number of ReadReq miss cycles 730system.cpu.icache.ReadReq_miss_latency::total 40485768000 # number of ReadReq miss cycles 731system.cpu.icache.demand_miss_latency::cpu.inst 40485768000 # number of demand (read+write) miss cycles 732system.cpu.icache.demand_miss_latency::total 40485768000 # number of demand (read+write) miss cycles 733system.cpu.icache.overall_miss_latency::cpu.inst 40485768000 # number of overall miss cycles 734system.cpu.icache.overall_miss_latency::total 40485768000 # number of overall miss cycles 735system.cpu.icache.ReadReq_accesses::cpu.inst 57559619 # number of ReadReq accesses(hits+misses) 736system.cpu.icache.ReadReq_accesses::total 57559619 # number of ReadReq accesses(hits+misses) 737system.cpu.icache.demand_accesses::cpu.inst 57559619 # number of demand (read+write) accesses 738system.cpu.icache.demand_accesses::total 57559619 # number of demand (read+write) accesses 739system.cpu.icache.overall_accesses::cpu.inst 57559619 # number of overall (read+write) accesses 740system.cpu.icache.overall_accesses::total 57559619 # number of overall (read+write) accesses 741system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050340 # miss rate for ReadReq accesses 742system.cpu.icache.ReadReq_miss_rate::total 0.050340 # miss rate for ReadReq accesses 743system.cpu.icache.demand_miss_rate::cpu.inst 0.050340 # miss rate for demand accesses 744system.cpu.icache.demand_miss_rate::total 0.050340 # miss rate for demand accesses 745system.cpu.icache.overall_miss_rate::cpu.inst 0.050340 # miss rate for overall accesses 746system.cpu.icache.overall_miss_rate::total 0.050340 # miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13972.303027 # average ReadReq miss latency 748system.cpu.icache.ReadReq_avg_miss_latency::total 13972.303027 # average ReadReq miss latency 749system.cpu.icache.demand_avg_miss_latency::cpu.inst 13972.303027 # average overall miss latency 750system.cpu.icache.demand_avg_miss_latency::total 13972.303027 # average overall miss latency 751system.cpu.icache.overall_avg_miss_latency::cpu.inst 13972.303027 # average overall miss latency 752system.cpu.icache.overall_avg_miss_latency::total 13972.303027 # average overall miss latency 753system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu.icache.fast_writes 0 # number of fast writes performed 760system.cpu.icache.cache_copies 0 # number of cache copies performed 761system.cpu.icache.writebacks::writebacks 2897049 # number of writebacks 762system.cpu.icache.writebacks::total 2897049 # number of writebacks 763system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897573 # number of ReadReq MSHR misses 764system.cpu.icache.ReadReq_mshr_misses::total 2897573 # number of ReadReq MSHR misses 765system.cpu.icache.demand_mshr_misses::cpu.inst 2897573 # number of demand (read+write) MSHR misses 766system.cpu.icache.demand_mshr_misses::total 2897573 # number of demand (read+write) MSHR misses 767system.cpu.icache.overall_mshr_misses::cpu.inst 2897573 # number of overall MSHR misses 768system.cpu.icache.overall_mshr_misses::total 2897573 # number of overall MSHR misses 769system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable 770system.cpu.icache.ReadReq_mshr_uncacheable::total 3763 # number of ReadReq MSHR uncacheable 771system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses 772system.cpu.icache.overall_mshr_uncacheable_misses::total 3763 # number of overall MSHR uncacheable misses 773system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37588196000 # number of ReadReq MSHR miss cycles 774system.cpu.icache.ReadReq_mshr_miss_latency::total 37588196000 # number of ReadReq MSHR miss cycles 775system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37588196000 # number of demand (read+write) MSHR miss cycles 776system.cpu.icache.demand_mshr_miss_latency::total 37588196000 # number of demand (read+write) MSHR miss cycles 777system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37588196000 # number of overall MSHR miss cycles 778system.cpu.icache.overall_mshr_miss_latency::total 37588196000 # number of overall MSHR miss cycles 779system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485921500 # number of ReadReq MSHR uncacheable cycles 780system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485921500 # number of ReadReq MSHR uncacheable cycles 781system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485921500 # number of overall MSHR uncacheable cycles 782system.cpu.icache.overall_mshr_uncacheable_latency::total 485921500 # number of overall MSHR uncacheable cycles 783system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for ReadReq accesses 784system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050340 # mshr miss rate for ReadReq accesses 785system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for demand accesses 786system.cpu.icache.demand_mshr_miss_rate::total 0.050340 # mshr miss rate for demand accesses 787system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for overall accesses 788system.cpu.icache.overall_mshr_miss_rate::total 0.050340 # mshr miss rate for overall accesses 789system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12972.303373 # average ReadReq mshr miss latency 790system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12972.303373 # average ReadReq mshr miss latency 791system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12972.303373 # average overall mshr miss latency 792system.cpu.icache.demand_avg_mshr_miss_latency::total 12972.303373 # average overall mshr miss latency 793system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12972.303373 # average overall mshr miss latency 794system.cpu.icache.overall_avg_mshr_miss_latency::total 12972.303373 # average overall mshr miss latency 795system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency 796system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency 797system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency 798system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency 799system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 800system.cpu.l2cache.tags.replacements 96446 # number of replacements 801system.cpu.l2cache.tags.tagsinuse 65019.357335 # Cycle average of tags in use 802system.cpu.l2cache.tags.total_refs 7030182 # Total number of references to valid blocks. 803system.cpu.l2cache.tags.sampled_refs 161691 # Sample count of references to valid blocks. 804system.cpu.l2cache.tags.avg_refs 43.479118 # Average number of references to valid blocks. 805system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 806system.cpu.l2cache.tags.occ_blocks::writebacks 47362.045211 # Average occupied blocks per requestor 807system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 65.242479 # Average occupied blocks per requestor 808system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009917 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.inst 12253.651278 # Average occupied blocks per requestor 810system.cpu.l2cache.tags.occ_blocks::cpu.data 5338.408451 # Average occupied blocks per requestor 811system.cpu.l2cache.tags.occ_percent::writebacks 0.722687 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000996 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 814system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186976 # Average percentage of cache occupancy 815system.cpu.l2cache.tags.occ_percent::cpu.data 0.081458 # Average percentage of cache occupancy 816system.cpu.l2cache.tags.occ_percent::total 0.992117 # Average percentage of cache occupancy 817system.cpu.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id 818system.cpu.l2cache.tags.occ_task_id_blocks::1024 65194 # Occupied blocks per task id 819system.cpu.l2cache.tags.age_task_id_blocks_1023::4 51 # Occupied blocks per task id 820system.cpu.l2cache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 821system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2289 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6892 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55898 # Occupied blocks per task id 825system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000778 # Percentage of cache occupancy per task id 826system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994781 # Percentage of cache occupancy per task id 827system.cpu.l2cache.tags.tag_accesses 60478007 # Number of tag accesses 828system.cpu.l2cache.tags.data_accesses 60478007 # Number of data accesses 829system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 72095 # number of ReadReq hits 830system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4693 # number of ReadReq hits 831system.cpu.l2cache.ReadReq_hits::total 76788 # number of ReadReq hits 832system.cpu.l2cache.WritebackDirty_hits::writebacks 700113 # number of WritebackDirty hits 833system.cpu.l2cache.WritebackDirty_hits::total 700113 # number of WritebackDirty hits 834system.cpu.l2cache.WritebackClean_hits::writebacks 2845529 # number of WritebackClean hits 835system.cpu.l2cache.WritebackClean_hits::total 2845529 # number of WritebackClean hits 836system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits 837system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits 838system.cpu.l2cache.ReadExReq_hits::cpu.data 165186 # number of ReadExReq hits 839system.cpu.l2cache.ReadExReq_hits::total 165186 # number of ReadExReq hits 840system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2874588 # number of ReadCleanReq hits 841system.cpu.l2cache.ReadCleanReq_hits::total 2874588 # number of ReadCleanReq hits 842system.cpu.l2cache.ReadSharedReq_hits::cpu.data 533051 # number of ReadSharedReq hits 843system.cpu.l2cache.ReadSharedReq_hits::total 533051 # number of ReadSharedReq hits 844system.cpu.l2cache.demand_hits::cpu.dtb.walker 72095 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::cpu.itb.walker 4693 # number of demand (read+write) hits 846system.cpu.l2cache.demand_hits::cpu.inst 2874588 # number of demand (read+write) hits 847system.cpu.l2cache.demand_hits::cpu.data 698237 # number of demand (read+write) hits 848system.cpu.l2cache.demand_hits::total 3649613 # number of demand (read+write) hits 849system.cpu.l2cache.overall_hits::cpu.dtb.walker 72095 # number of overall hits 850system.cpu.l2cache.overall_hits::cpu.itb.walker 4693 # number of overall hits 851system.cpu.l2cache.overall_hits::cpu.inst 2874588 # number of overall hits 852system.cpu.l2cache.overall_hits::cpu.data 698237 # number of overall hits 853system.cpu.l2cache.overall_hits::total 3649613 # number of overall hits 854system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 125 # number of ReadReq misses 855system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 856system.cpu.l2cache.ReadReq_misses::total 127 # number of ReadReq misses 857system.cpu.l2cache.UpgradeReq_misses::cpu.data 2737 # number of UpgradeReq misses 858system.cpu.l2cache.UpgradeReq_misses::total 2737 # number of UpgradeReq misses 859system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 860system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 861system.cpu.l2cache.ReadExReq_misses::cpu.data 131007 # number of ReadExReq misses 862system.cpu.l2cache.ReadExReq_misses::total 131007 # number of ReadExReq misses 863system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22960 # number of ReadCleanReq misses 864system.cpu.l2cache.ReadCleanReq_misses::total 22960 # number of ReadCleanReq misses 865system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14250 # number of ReadSharedReq misses 866system.cpu.l2cache.ReadSharedReq_misses::total 14250 # number of ReadSharedReq misses 867system.cpu.l2cache.demand_misses::cpu.dtb.walker 125 # number of demand (read+write) misses 868system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 869system.cpu.l2cache.demand_misses::cpu.inst 22960 # number of demand (read+write) misses 870system.cpu.l2cache.demand_misses::cpu.data 145257 # number of demand (read+write) misses 871system.cpu.l2cache.demand_misses::total 168344 # number of demand (read+write) misses 872system.cpu.l2cache.overall_misses::cpu.dtb.walker 125 # number of overall misses 873system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 874system.cpu.l2cache.overall_misses::cpu.inst 22960 # number of overall misses 875system.cpu.l2cache.overall_misses::cpu.data 145257 # number of overall misses 876system.cpu.l2cache.overall_misses::total 168344 # number of overall misses 877system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 17736500 # number of ReadReq miss cycles 878system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 279000 # number of ReadReq miss cycles 879system.cpu.l2cache.ReadReq_miss_latency::total 18015500 # number of ReadReq miss cycles 880system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2961500 # number of UpgradeReq miss cycles 881system.cpu.l2cache.UpgradeReq_miss_latency::total 2961500 # number of UpgradeReq miss cycles 882system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 883system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 884system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16784670000 # number of ReadExReq miss cycles 885system.cpu.l2cache.ReadExReq_miss_latency::total 16784670000 # number of ReadExReq miss cycles 886system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2992161000 # number of ReadCleanReq miss cycles 887system.cpu.l2cache.ReadCleanReq_miss_latency::total 2992161000 # number of ReadCleanReq miss cycles 888system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1880931500 # number of ReadSharedReq miss cycles 889system.cpu.l2cache.ReadSharedReq_miss_latency::total 1880931500 # number of ReadSharedReq miss cycles 890system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17736500 # number of demand (read+write) miss cycles 891system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 279000 # number of demand (read+write) miss cycles 892system.cpu.l2cache.demand_miss_latency::cpu.inst 2992161000 # number of demand (read+write) miss cycles 893system.cpu.l2cache.demand_miss_latency::cpu.data 18665601500 # number of demand (read+write) miss cycles 894system.cpu.l2cache.demand_miss_latency::total 21675778000 # number of demand (read+write) miss cycles 895system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17736500 # number of overall miss cycles 896system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 279000 # number of overall miss cycles 897system.cpu.l2cache.overall_miss_latency::cpu.inst 2992161000 # number of overall miss cycles 898system.cpu.l2cache.overall_miss_latency::cpu.data 18665601500 # number of overall miss cycles 899system.cpu.l2cache.overall_miss_latency::total 21675778000 # number of overall miss cycles 900system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 72220 # number of ReadReq accesses(hits+misses) 901system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4695 # number of ReadReq accesses(hits+misses) 902system.cpu.l2cache.ReadReq_accesses::total 76915 # number of ReadReq accesses(hits+misses) 903system.cpu.l2cache.WritebackDirty_accesses::writebacks 700113 # number of WritebackDirty accesses(hits+misses) 904system.cpu.l2cache.WritebackDirty_accesses::total 700113 # number of WritebackDirty accesses(hits+misses) 905system.cpu.l2cache.WritebackClean_accesses::writebacks 2845529 # number of WritebackClean accesses(hits+misses) 906system.cpu.l2cache.WritebackClean_accesses::total 2845529 # number of WritebackClean accesses(hits+misses) 907system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2785 # number of UpgradeReq accesses(hits+misses) 908system.cpu.l2cache.UpgradeReq_accesses::total 2785 # number of UpgradeReq accesses(hits+misses) 909system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 910system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 911system.cpu.l2cache.ReadExReq_accesses::cpu.data 296193 # number of ReadExReq accesses(hits+misses) 912system.cpu.l2cache.ReadExReq_accesses::total 296193 # number of ReadExReq accesses(hits+misses) 913system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2897548 # number of ReadCleanReq accesses(hits+misses) 914system.cpu.l2cache.ReadCleanReq_accesses::total 2897548 # number of ReadCleanReq accesses(hits+misses) 915system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 547301 # number of ReadSharedReq accesses(hits+misses) 916system.cpu.l2cache.ReadSharedReq_accesses::total 547301 # number of ReadSharedReq accesses(hits+misses) 917system.cpu.l2cache.demand_accesses::cpu.dtb.walker 72220 # number of demand (read+write) accesses 918system.cpu.l2cache.demand_accesses::cpu.itb.walker 4695 # number of demand (read+write) accesses 919system.cpu.l2cache.demand_accesses::cpu.inst 2897548 # number of demand (read+write) accesses 920system.cpu.l2cache.demand_accesses::cpu.data 843494 # number of demand (read+write) accesses 921system.cpu.l2cache.demand_accesses::total 3817957 # number of demand (read+write) accesses 922system.cpu.l2cache.overall_accesses::cpu.dtb.walker 72220 # number of overall (read+write) accesses 923system.cpu.l2cache.overall_accesses::cpu.itb.walker 4695 # number of overall (read+write) accesses 924system.cpu.l2cache.overall_accesses::cpu.inst 2897548 # number of overall (read+write) accesses 925system.cpu.l2cache.overall_accesses::cpu.data 843494 # number of overall (read+write) accesses 926system.cpu.l2cache.overall_accesses::total 3817957 # number of overall (read+write) accesses 927system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001731 # miss rate for ReadReq accesses 928system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000426 # miss rate for ReadReq accesses 929system.cpu.l2cache.ReadReq_miss_rate::total 0.001651 # miss rate for ReadReq accesses 930system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982765 # miss rate for UpgradeReq accesses 931system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982765 # miss rate for UpgradeReq accesses 932system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 933system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 934system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442303 # miss rate for ReadExReq accesses 935system.cpu.l2cache.ReadExReq_miss_rate::total 0.442303 # miss rate for ReadExReq accesses 936system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007924 # miss rate for ReadCleanReq accesses 937system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007924 # miss rate for ReadCleanReq accesses 938system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026037 # miss rate for ReadSharedReq accesses 939system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026037 # miss rate for ReadSharedReq accesses 940system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001731 # miss rate for demand accesses 941system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000426 # miss rate for demand accesses 942system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007924 # miss rate for demand accesses 943system.cpu.l2cache.demand_miss_rate::cpu.data 0.172209 # miss rate for demand accesses 944system.cpu.l2cache.demand_miss_rate::total 0.044093 # miss rate for demand accesses 945system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001731 # miss rate for overall accesses 946system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000426 # miss rate for overall accesses 947system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007924 # miss rate for overall accesses 948system.cpu.l2cache.overall_miss_rate::cpu.data 0.172209 # miss rate for overall accesses 949system.cpu.l2cache.overall_miss_rate::total 0.044093 # miss rate for overall accesses 950system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141892 # average ReadReq miss latency 951system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139500 # average ReadReq miss latency 952system.cpu.l2cache.ReadReq_avg_miss_latency::total 141854.330709 # average ReadReq miss latency 953system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1082.024114 # average UpgradeReq miss latency 954system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1082.024114 # average UpgradeReq miss latency 955system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency 956system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency 957system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128120.405780 # average ReadExReq miss latency 958system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128120.405780 # average ReadExReq miss latency 959system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130320.601045 # average ReadCleanReq miss latency 960system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130320.601045 # average ReadCleanReq miss latency 961system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131995.192982 # average ReadSharedReq miss latency 962system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131995.192982 # average ReadSharedReq miss latency 963system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141892 # average overall miss latency 964system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139500 # average overall miss latency 965system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130320.601045 # average overall miss latency 966system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128500.530095 # average overall miss latency 967system.cpu.l2cache.demand_avg_miss_latency::total 128758.839044 # average overall miss latency 968system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141892 # average overall miss latency 969system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139500 # average overall miss latency 970system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130320.601045 # average overall miss latency 971system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128500.530095 # average overall miss latency 972system.cpu.l2cache.overall_avg_miss_latency::total 128758.839044 # average overall miss latency 973system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 974system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 975system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 976system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 977system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 978system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 979system.cpu.l2cache.fast_writes 0 # number of fast writes performed 980system.cpu.l2cache.cache_copies 0 # number of cache copies performed 981system.cpu.l2cache.writebacks::writebacks 87862 # number of writebacks 982system.cpu.l2cache.writebacks::total 87862 # number of writebacks 983system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits 984system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits 985system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 142 # number of ReadSharedReq MSHR hits 986system.cpu.l2cache.ReadSharedReq_mshr_hits::total 142 # number of ReadSharedReq MSHR hits 987system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits 988system.cpu.l2cache.demand_mshr_hits::cpu.data 142 # number of demand (read+write) MSHR hits 989system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 990system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits 991system.cpu.l2cache.overall_mshr_hits::cpu.data 142 # number of overall MSHR hits 992system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits 993system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 125 # number of ReadReq MSHR misses 994system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 995system.cpu.l2cache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses 996system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2737 # number of UpgradeReq MSHR misses 997system.cpu.l2cache.UpgradeReq_mshr_misses::total 2737 # number of UpgradeReq MSHR misses 998system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 999system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1000system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131007 # number of ReadExReq MSHR misses 1001system.cpu.l2cache.ReadExReq_mshr_misses::total 131007 # number of ReadExReq MSHR misses 1002system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22937 # number of ReadCleanReq MSHR misses 1003system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22937 # number of ReadCleanReq MSHR misses 1004system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14108 # number of ReadSharedReq MSHR misses 1005system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14108 # number of ReadSharedReq MSHR misses 1006system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 125 # number of demand (read+write) MSHR misses 1007system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1008system.cpu.l2cache.demand_mshr_misses::cpu.inst 22937 # number of demand (read+write) MSHR misses 1009system.cpu.l2cache.demand_mshr_misses::cpu.data 145115 # number of demand (read+write) MSHR misses 1010system.cpu.l2cache.demand_mshr_misses::total 168179 # number of demand (read+write) MSHR misses 1011system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 125 # number of overall MSHR misses 1012system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1013system.cpu.l2cache.overall_mshr_misses::cpu.inst 22937 # number of overall MSHR misses 1014system.cpu.l2cache.overall_mshr_misses::cpu.data 145115 # number of overall MSHR misses 1015system.cpu.l2cache.overall_mshr_misses::total 168179 # number of overall MSHR misses 1016system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable 1017system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 1018system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34893 # number of ReadReq MSHR uncacheable 1019system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1020system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1021system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses 1022system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1023system.cpu.l2cache.overall_mshr_uncacheable_misses::total 62477 # number of overall MSHR uncacheable misses 1024system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 16486500 # number of ReadReq MSHR miss cycles 1025system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 259000 # number of ReadReq MSHR miss cycles 1026system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16745500 # number of ReadReq MSHR miss cycles 1027system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186130000 # number of UpgradeReq MSHR miss cycles 1028system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186130000 # number of UpgradeReq MSHR miss cycles 1029system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142000 # number of SCUpgradeReq MSHR miss cycles 1030system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142000 # number of SCUpgradeReq MSHR miss cycles 1031system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15474600000 # number of ReadExReq MSHR miss cycles 1032system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15474600000 # number of ReadExReq MSHR miss cycles 1033system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2761139500 # number of ReadCleanReq MSHR miss cycles 1034system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2761139500 # number of ReadCleanReq MSHR miss cycles 1035system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1723039000 # number of ReadSharedReq MSHR miss cycles 1036system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1723039000 # number of ReadSharedReq MSHR miss cycles 1037system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 16486500 # number of demand (read+write) MSHR miss cycles 1038system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 259000 # number of demand (read+write) MSHR miss cycles 1039system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2761139500 # number of demand (read+write) MSHR miss cycles 1040system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17197639000 # number of demand (read+write) MSHR miss cycles 1041system.cpu.l2cache.demand_mshr_miss_latency::total 19975524000 # number of demand (read+write) MSHR miss cycles 1042system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 16486500 # number of overall MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 259000 # number of overall MSHR miss cycles 1044system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2761139500 # number of overall MSHR miss cycles 1045system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17197639000 # number of overall MSHR miss cycles 1046system.cpu.l2cache.overall_mshr_miss_latency::total 19975524000 # number of overall MSHR miss cycles 1047system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 427218000 # number of ReadReq MSHR uncacheable cycles 1048system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888601000 # number of ReadReq MSHR uncacheable cycles 1049system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315819000 # number of ReadReq MSHR uncacheable cycles 1050system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4766368000 # number of WriteReq MSHR uncacheable cycles 1051system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4766368000 # number of WriteReq MSHR uncacheable cycles 1052system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 427218000 # number of overall MSHR uncacheable cycles 1053system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10654969000 # number of overall MSHR uncacheable cycles 1054system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11082187000 # number of overall MSHR uncacheable cycles 1055system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for ReadReq accesses 1056system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for ReadReq accesses 1057system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001651 # mshr miss rate for ReadReq accesses 1058system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982765 # mshr miss rate for UpgradeReq accesses 1059system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982765 # mshr miss rate for UpgradeReq accesses 1060system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1061system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1062system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442303 # mshr miss rate for ReadExReq accesses 1063system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442303 # mshr miss rate for ReadExReq accesses 1064system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for ReadCleanReq accesses 1065system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007916 # mshr miss rate for ReadCleanReq accesses 1066system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025777 # mshr miss rate for ReadSharedReq accesses 1067system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025777 # mshr miss rate for ReadSharedReq accesses 1068system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for demand accesses 1069system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for demand accesses 1070system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for demand accesses 1071system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for demand accesses 1072system.cpu.l2cache.demand_mshr_miss_rate::total 0.044049 # mshr miss rate for demand accesses 1073system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for overall accesses 1074system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for overall accesses 1075system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for overall accesses 1076system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for overall accesses 1077system.cpu.l2cache.overall_mshr_miss_rate::total 0.044049 # mshr miss rate for overall accesses 1078system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average ReadReq mshr miss latency 1079system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129500 # average ReadReq mshr miss latency 1080system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131854.330709 # average ReadReq mshr miss latency 1081system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68005.115090 # average UpgradeReq mshr miss latency 1082system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68005.115090 # average UpgradeReq mshr miss latency 1083system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency 1084system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency 1085system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118120.405780 # average ReadExReq mshr miss latency 1086system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118120.405780 # average ReadExReq mshr miss latency 1087system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120379.278022 # average ReadCleanReq mshr miss latency 1088system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120379.278022 # average ReadCleanReq mshr miss latency 1089system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122132.052736 # average ReadSharedReq mshr miss latency 1090system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122132.052736 # average ReadSharedReq mshr miss latency 1091system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency 1092system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency 1093system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency 1094system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency 1095system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency 1096system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency 1097system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency 1098system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency 1099system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency 1100system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency 1101system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency 1102system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189161.612592 # average ReadReq mshr uncacheable latency 1103system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181005.330582 # average ReadReq mshr uncacheable latency 1104system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172794.663573 # average WriteReq mshr uncacheable latency 1105system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172794.663573 # average WriteReq mshr uncacheable latency 1106system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency 1107system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181472.374561 # average overall mshr uncacheable latency 1108system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177380.267939 # average overall mshr uncacheable latency 1109system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1110system.cpu.toL2Bus.snoop_filter.tot_requests 7513127 # Total number of requests made to the snoop filter. 1111system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772095 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1112system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58799 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1113system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter. 1114system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1115system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1116system.cpu.toL2Bus.trans_dist::ReadReq 134810 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::ReadResp 3579896 # Transaction distribution 1118system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::WritebackDirty 824175 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::WritebackClean 2897049 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::CleanEvict 151656 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::ReadExReq 296193 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::ReadExResp 296193 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897573 # Transaction distribution 1129system.cpu.toL2Bus.trans_dist::ReadSharedReq 547535 # Transaction distribution 1130system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1131system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8699695 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2653154 # Packet count per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15282 # Packet count per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161550 # Packet count per connected master and slave (bytes) 1135system.cpu.toL2Bus.pkt_count::total 11529681 # Packet count per connected master and slave (bytes) 1136system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 371094976 # Cumulative packet size per connected master and slave (bytes) 1137system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98987561 # Cumulative packet size per connected master and slave (bytes) 1138system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18780 # Cumulative packet size per connected master and slave (bytes) 1139system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288880 # Cumulative packet size per connected master and slave (bytes) 1140system.cpu.toL2Bus.pkt_size::total 470390197 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu.toL2Bus.snoops 192578 # Total snoops (count) 1142system.cpu.toL2Bus.snoop_fanout::samples 4075586 # Request fanout histogram 1143system.cpu.toL2Bus.snoop_fanout::mean 0.021763 # Request fanout histogram 1144system.cpu.toL2Bus.snoop_fanout::stdev 0.145909 # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::0 3986889 97.82% 97.82% # Request fanout histogram 1147system.cpu.toL2Bus.snoop_fanout::1 88697 2.18% 100.00% # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1150system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1152system.cpu.toL2Bus.snoop_fanout::total 4075586 # Request fanout histogram 1153system.cpu.toL2Bus.reqLayer0.occupancy 7434078000 # Layer occupancy (ticks) 1154system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1155system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) 1156system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1157system.cpu.toL2Bus.respLayer0.occupancy 4352565871 # Layer occupancy (ticks) 1158system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1159system.cpu.toL2Bus.respLayer1.occupancy 1311717177 # Layer occupancy (ticks) 1160system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1161system.cpu.toL2Bus.respLayer2.occupancy 10589994 # Layer occupancy (ticks) 1162system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1163system.cpu.toL2Bus.respLayer3.occupancy 89368907 # Layer occupancy (ticks) 1164system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1165system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1166system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1167system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1168system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1169system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1211system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.reqLayer0.occupancy 46502500 # Layer occupancy (ticks) 1216system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1217system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 1218system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1219system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) 1220system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1221system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) 1222system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1223system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) 1224system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1225system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) 1226system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1227system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks) 1228system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1229system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) 1230system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1231system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 1232system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1233system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 1234system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1235system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 1236system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1237system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) 1238system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1239system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1240system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1241system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1242system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 1244system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 1246system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1247system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) 1248system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1249system.iobus.reqLayer23.occupancy 6064500 # Layer occupancy (ticks) 1250system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1251system.iobus.reqLayer24.occupancy 33518500 # Layer occupancy (ticks) 1252system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1253system.iobus.reqLayer25.occupancy 187144507 # Layer occupancy (ticks) 1254system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1255system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1256system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1257system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1258system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1259system.iocache.tags.replacements 36424 # number of replacements 1260system.iocache.tags.tagsinuse 1.036750 # Cycle average of tags in use 1261system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1262system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1263system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1264system.iocache.tags.warmup_cycle 274891170000 # Cycle when the warmup percentage was hit. 1265system.iocache.tags.occ_blocks::realview.ide 1.036750 # Average occupied blocks per requestor 1266system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy 1267system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy 1268system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1269system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1270system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1271system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1272system.iocache.tags.data_accesses 328122 # Number of data accesses 1273system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1274system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1275system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1276system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1277system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1278system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1279system.iocache.overall_misses::realview.ide 234 # number of overall misses 1280system.iocache.overall_misses::total 234 # number of overall misses 1281system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles 1282system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles 1283system.iocache.WriteLineReq_miss_latency::realview.ide 4549676630 # number of WriteLineReq miss cycles 1284system.iocache.WriteLineReq_miss_latency::total 4549676630 # number of WriteLineReq miss cycles 1285system.iocache.demand_miss_latency::realview.ide 29054877 # number of demand (read+write) miss cycles 1286system.iocache.demand_miss_latency::total 29054877 # number of demand (read+write) miss cycles 1287system.iocache.overall_miss_latency::realview.ide 29054877 # number of overall miss cycles 1288system.iocache.overall_miss_latency::total 29054877 # number of overall miss cycles 1289system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1290system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1291system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1292system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1293system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1294system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1295system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1296system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1297system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1298system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1299system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1300system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1301system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1302system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1303system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1304system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1305system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency 1306system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency 1307system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125598.405201 # average WriteLineReq miss latency 1308system.iocache.WriteLineReq_avg_miss_latency::total 125598.405201 # average WriteLineReq miss latency 1309system.iocache.demand_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency 1310system.iocache.demand_avg_miss_latency::total 124166.141026 # average overall miss latency 1311system.iocache.overall_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency 1312system.iocache.overall_avg_miss_latency::total 124166.141026 # average overall miss latency 1313system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1314system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1315system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1316system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1317system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1318system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1319system.iocache.fast_writes 0 # number of fast writes performed 1320system.iocache.cache_copies 0 # number of cache copies performed 1321system.iocache.writebacks::writebacks 36190 # number of writebacks 1322system.iocache.writebacks::total 36190 # number of writebacks 1323system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1324system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1325system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1326system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1327system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1328system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1329system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1330system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1331system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles 1332system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles 1333system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737053618 # number of WriteLineReq MSHR miss cycles 1334system.iocache.WriteLineReq_mshr_miss_latency::total 2737053618 # number of WriteLineReq MSHR miss cycles 1335system.iocache.demand_mshr_miss_latency::realview.ide 17354877 # number of demand (read+write) MSHR miss cycles 1336system.iocache.demand_mshr_miss_latency::total 17354877 # number of demand (read+write) MSHR miss cycles 1337system.iocache.overall_mshr_miss_latency::realview.ide 17354877 # number of overall MSHR miss cycles 1338system.iocache.overall_mshr_miss_latency::total 17354877 # number of overall MSHR miss cycles 1339system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1340system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1341system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1342system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1343system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1344system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1345system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1346system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1347system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency 1348system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency 1349system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75559.121522 # average WriteLineReq mshr miss latency 1350system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75559.121522 # average WriteLineReq mshr miss latency 1351system.iocache.demand_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency 1352system.iocache.demand_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency 1353system.iocache.overall_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency 1354system.iocache.overall_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency 1355system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1356system.membus.trans_dist::ReadReq 34893 # Transaction distribution 1357system.membus.trans_dist::ReadResp 72299 # Transaction distribution 1358system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1359system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1360system.membus.trans_dist::WritebackDirty 124052 # Transaction distribution 1361system.membus.trans_dist::CleanEvict 8818 # Transaction distribution 1362system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution 1363system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1364system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1365system.membus.trans_dist::ReadExReq 129140 # Transaction distribution 1366system.membus.trans_dist::ReadExResp 129140 # Transaction distribution 1367system.membus.trans_dist::ReadSharedReq 37406 # Transaction distribution 1368system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1369system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1370system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1371system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) 1372system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450778 # Packet count per connected master and slave (bytes) 1373system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558346 # Packet count per connected master and slave (bytes) 1374system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1375system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) 1376system.membus.pkt_count::total 631243 # Packet count per connected master and slave (bytes) 1377system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1378system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) 1379system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) 1380system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16509088 # Cumulative packet size per connected master and slave (bytes) 1381system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16672873 # Cumulative packet size per connected master and slave (bytes) 1382system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1383system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1384system.membus.pkt_size::total 18989993 # Cumulative packet size per connected master and slave (bytes) 1385system.membus.snoops 505 # Total snoops (count) 1386system.membus.snoop_fanout::samples 402733 # Request fanout histogram 1387system.membus.snoop_fanout::mean 1 # Request fanout histogram 1388system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1389system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1390system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1391system.membus.snoop_fanout::1 402733 100.00% 100.00% # Request fanout histogram 1392system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1393system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1394system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1395system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1396system.membus.snoop_fanout::total 402733 # Request fanout histogram 1397system.membus.reqLayer0.occupancy 87415500 # Layer occupancy (ticks) 1398system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1399system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) 1400system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1401system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) 1402system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1403system.membus.reqLayer5.occupancy 878266116 # Layer occupancy (ticks) 1404system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1405system.membus.respLayer2.occupancy 990100000 # Layer occupancy (ticks) 1406system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1407system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) 1408system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1409system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1410system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1411system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1412system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1413system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1414system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1415system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1416system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1417system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1418system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1419system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1420system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1421system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1422system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1423system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1424system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1425system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1426system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1427system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1428system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1429system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1430system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1431system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1432system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1433system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1434system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1435system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1436system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1437system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1438system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1439system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1440system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1441system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1442system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1443system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1444system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1445system.realview.ethernet.droppedPackets 0 # number of packets dropped 1446system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1447system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1448system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1449system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1450 1451---------- End Simulation Statistics ---------- 1452