stats.txt revision 11239:3be64e1f80ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858555 # Number of seconds simulated 4sim_ticks 2858554679500 # Number of ticks simulated 5final_tick 2858554679500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 152763 # Simulator instruction rate (inst/s) 8host_op_rate 184703 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3901193118 # Simulator tick rate (ticks/s) 10host_mem_usage 583172 # Number of bytes of host memory used 11host_seconds 732.74 # Real time elapsed on the host 12sim_insts 111935485 # Number of instructions simulated 13sim_ops 135338943 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7616 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9149804 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10866540 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7937280 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7954804 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 119 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 143487 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 170311 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 124020 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 128401 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2664 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 597538 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3200850 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3801411 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 597538 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 597538 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2776676 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2782806 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2776676 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2664 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 597538 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3206980 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6584217 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 170311 # Number of read requests accepted 55system.physmem.writeReqs 128401 # Number of write requests accepted 56system.physmem.readBursts 170311 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 128401 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10891264 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7967296 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10866540 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7954804 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 49408 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10771 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10784 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10887 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10717 # Per bank write bursts 70system.physmem.perBankRdBursts::4 14062 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10208 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10996 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10949 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9936 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10239 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9937 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9167 # Per bank write bursts 78system.physmem.perBankRdBursts::12 10278 # Per bank write bursts 79system.physmem.perBankRdBursts::13 11186 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10249 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9810 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8068 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8140 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8529 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8260 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7653 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7417 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7934 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8022 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7566 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7724 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7504 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7051 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7682 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8291 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7536 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7112 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 100system.physmem.totGap 2858554234000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 543 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 169754 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 124020 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 163165 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 6708 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2047 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2399 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6060 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6728 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6786 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7644 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 7385 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8118 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8306 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8126 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9757 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7720 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7133 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7200 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6847 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6581 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6447 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 319 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 225 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 104 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 113 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 91 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 100 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 44 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 61347 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 307.404893 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 183.124702 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 323.856556 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22378 36.48% 36.48% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14856 24.22% 60.69% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6657 10.85% 71.55% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3691 6.02% 77.56% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2584 4.21% 81.77% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1979 3.23% 85.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1099 1.79% 86.79% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1109 1.81% 88.60% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 6994 11.40% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 61347 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.377091 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 569.055211 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6215 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6215 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.029123 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.467033 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.100027 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5396 86.82% 86.82% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 102 1.64% 88.46% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 39 0.63% 89.09% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 172 2.77% 91.86% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 31 0.50% 92.36% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 152 2.45% 94.80% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 39 0.63% 95.43% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 12 0.19% 95.62% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 17 0.27% 95.90% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 24 0.39% 96.28% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 4 0.06% 96.35% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 7 0.11% 96.46% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 159 2.56% 99.02% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 6 0.10% 99.12% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 7 0.11% 99.23% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 26 0.42% 99.65% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 2 0.03% 99.68% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.69% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::92-95 1 0.02% 99.71% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 1 0.02% 99.73% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::100-103 2 0.03% 99.76% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 1 0.02% 99.77% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::124-127 1 0.02% 99.79% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::128-131 5 0.08% 99.87% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::140-143 1 0.02% 99.89% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::152-155 3 0.05% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::156-159 3 0.05% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 6215 # Writes before turning the bus around for reads 264system.physmem.totQLat 1812035750 # Total ticks spent queuing 265system.physmem.totMemAccLat 5002835750 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 850880000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 10648.01 # Average queueing delay per DRAM burst 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 269system.physmem.avgMemAccLat 29398.01 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.05 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 278system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 279system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing 280system.physmem.readRowHits 139556 # Number of row buffer hits during reads 281system.physmem.writeRowHits 93759 # Number of row buffer hits during writes 282system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads 283system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes 284system.physmem.avgGap 9569599.59 # Average gap between requests 285system.physmem.pageHitRate 79.17 # Row buffer hit rate, read and write combined 286system.physmem_0.actEnergy 241731000 # Energy for activate commands per rank (pJ) 287system.physmem_0.preEnergy 131896875 # Energy for precharge commands per rank (pJ) 288system.physmem_0.readEnergy 697117200 # Energy for read commands per rank (pJ) 289system.physmem_0.writeEnergy 414817200 # Energy for write commands per rank (pJ) 290system.physmem_0.refreshEnergy 186706615680 # Energy for refresh commands per rank (pJ) 291system.physmem_0.actBackEnergy 86828058675 # Energy for active background per rank (pJ) 292system.physmem_0.preBackEnergy 1638965418000 # Energy for precharge background per rank (pJ) 293system.physmem_0.totalEnergy 1913985654630 # Total energy per rank (pJ) 294system.physmem_0.averagePower 669.565069 # Core power per rank (mW) 295system.physmem_0.memoryStateTime::IDLE 2726406946000 # Time in different power states 296system.physmem_0.memoryStateTime::REF 95453280000 # Time in different power states 297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 298system.physmem_0.memoryStateTime::ACT 36694429000 # Time in different power states 299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 300system.physmem_1.actEnergy 222037200 # Energy for activate commands per rank (pJ) 301system.physmem_1.preEnergy 121151250 # Energy for precharge commands per rank (pJ) 302system.physmem_1.readEnergy 630247800 # Energy for read commands per rank (pJ) 303system.physmem_1.writeEnergy 391819680 # Energy for write commands per rank (pJ) 304system.physmem_1.refreshEnergy 186706615680 # Energy for refresh commands per rank (pJ) 305system.physmem_1.actBackEnergy 85116075930 # Energy for active background per rank (pJ) 306system.physmem_1.preBackEnergy 1640467157250 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 1913655104790 # Total energy per rank (pJ) 308system.physmem_1.averagePower 669.449434 # Core power per rank (mW) 309system.physmem_1.memoryStateTime::IDLE 2728919167500 # Time in different power states 310system.physmem_1.memoryStateTime::REF 95453280000 # Time in different power states 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 312system.physmem_1.memoryStateTime::ACT 34182085000 # Time in different power states 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 314system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 315system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 316system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 317system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 318system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 319system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 320system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 325system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) 326system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 327system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 328system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 329system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 330system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 331system.cf0.dma_write_txs 631 # Number of DMA write transactions. 332system.cpu.branchPred.lookups 31017399 # Number of BP lookups 333system.cpu.branchPred.condPredicted 16820647 # Number of conditional branches predicted 334system.cpu.branchPred.condIncorrect 2503170 # Number of conditional branches incorrect 335system.cpu.branchPred.BTBLookups 18419836 # Number of BTB lookups 336system.cpu.branchPred.BTBHits 13303162 # Number of BTB hits 337system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 338system.cpu.branchPred.BTBHitPct 72.221935 # BTB Hit Percentage 339system.cpu.branchPred.usedRAS 7872052 # Number of times the RAS was used to get a target. 340system.cpu.branchPred.RASInCorrect 1510670 # Number of incorrect RAS predictions. 341system.cpu_clk_domain.clock 500 # Clock period in ticks 342system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 351system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 352system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 353system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 354system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 355system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 356system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 357system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 358system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 359system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 360system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 361system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 362system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 363system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 364system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 365system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 366system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 367system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 368system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 369system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 370system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 371system.cpu.dtb.walker.walks 65808 # Table walker walks requested 372system.cpu.dtb.walker.walksShort 65808 # Table walker walks initiated with short descriptors 373system.cpu.dtb.walker.walksShortTerminationLevel::Level1 42987 # Level at which table walker walks with short descriptors terminate 374system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22821 # Level at which table walker walks with short descriptors terminate 375system.cpu.dtb.walker.walkWaitTime::samples 65808 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkWaitTime::0 65808 100.00% 100.00% # Table walker wait (enqueue to first request) latency 377system.cpu.dtb.walker.walkWaitTime::total 65808 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkCompletionTime::samples 7823 # Table walker service (enqueue to completion) latency 379system.cpu.dtb.walker.walkCompletionTime::mean 12723.315863 # Table walker service (enqueue to completion) latency 380system.cpu.dtb.walker.walkCompletionTime::gmean 10567.827696 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::stdev 8328.598591 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::0-32767 7817 99.92% 99.92% # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.06% 99.99% # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::total 7823 # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution 387system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution 388system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution 389system.cpu.dtb.walker.walkPageSizes::4K 6431 82.21% 82.21% # Table walker page sizes translated 390system.cpu.dtb.walker.walkPageSizes::1M 1392 17.79% 100.00% # Table walker page sizes translated 391system.cpu.dtb.walker.walkPageSizes::total 7823 # Table walker page sizes translated 392system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65808 # Table walker requests started/completed, data/inst 393system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65808 # Table walker requests started/completed, data/inst 395system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7823 # Table walker requests started/completed, data/inst 396system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7823 # Table walker requests started/completed, data/inst 398system.cpu.dtb.walker.walkRequestOrigin::total 73631 # Table walker requests started/completed, data/inst 399system.cpu.dtb.inst_hits 0 # ITB inst hits 400system.cpu.dtb.inst_misses 0 # ITB inst misses 401system.cpu.dtb.read_hits 24739501 # DTB read hits 402system.cpu.dtb.read_misses 58797 # DTB read misses 403system.cpu.dtb.write_hits 19434146 # DTB write hits 404system.cpu.dtb.write_misses 7011 # DTB write misses 405system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 406system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 407system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB 410system.cpu.dtb.align_faults 1307 # Number of TLB faults due to alignment restrictions 411system.cpu.dtb.prefetch_faults 1800 # Number of TLB faults due to prefetch 412system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu.dtb.perms_faults 763 # Number of TLB faults due to permissions restrictions 414system.cpu.dtb.read_accesses 24798298 # DTB read accesses 415system.cpu.dtb.write_accesses 19441157 # DTB write accesses 416system.cpu.dtb.inst_accesses 0 # ITB inst accesses 417system.cpu.dtb.hits 44173647 # DTB hits 418system.cpu.dtb.misses 65808 # DTB misses 419system.cpu.dtb.accesses 44239455 # DTB accesses 420system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 421system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 422system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 423system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 424system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 429system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 430system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 431system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 432system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 433system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 434system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 435system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 436system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 437system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 438system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 439system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 440system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 441system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 442system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 443system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 444system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 445system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 446system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 447system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 448system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 449system.cpu.itb.walker.walks 5439 # Table walker walks requested 450system.cpu.itb.walker.walksShort 5439 # Table walker walks initiated with short descriptors 451system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate 452system.cpu.itb.walker.walksShortTerminationLevel::Level2 5120 # Level at which table walker walks with short descriptors terminate 453system.cpu.itb.walker.walkWaitTime::samples 5439 # Table walker wait (enqueue to first request) latency 454system.cpu.itb.walker.walkWaitTime::0 5439 100.00% 100.00% # Table walker wait (enqueue to first request) latency 455system.cpu.itb.walker.walkWaitTime::total 5439 # Table walker wait (enqueue to first request) latency 456system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency 457system.cpu.itb.walker.walkCompletionTime::mean 12910.175879 # Table walker service (enqueue to completion) latency 458system.cpu.itb.walker.walkCompletionTime::gmean 10824.296487 # Table walker service (enqueue to completion) latency 459system.cpu.itb.walker.walkCompletionTime::stdev 7389.330309 # Table walker service (enqueue to completion) latency 460system.cpu.itb.walker.walkCompletionTime::0-16383 2456 77.14% 77.14% # Table walker service (enqueue to completion) latency 461system.cpu.itb.walker.walkCompletionTime::16384-32767 727 22.83% 99.97% # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution 465system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution 466system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution 467system.cpu.itb.walker.walkPageSizes::4K 2874 90.26% 90.26% # Table walker page sizes translated 468system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated 469system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated 470system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 471system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5439 # Table walker requests started/completed, data/inst 472system.cpu.itb.walker.walkRequestOrigin_Requested::total 5439 # Table walker requests started/completed, data/inst 473system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst 475system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst 476system.cpu.itb.walker.walkRequestOrigin::total 8623 # Table walker requests started/completed, data/inst 477system.cpu.itb.inst_hits 57560838 # ITB inst hits 478system.cpu.itb.inst_misses 5439 # ITB inst misses 479system.cpu.itb.read_hits 0 # DTB read hits 480system.cpu.itb.read_misses 0 # DTB read misses 481system.cpu.itb.write_hits 0 # DTB write hits 482system.cpu.itb.write_misses 0 # DTB write misses 483system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 484system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 485system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 486system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 487system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB 488system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 489system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 490system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 491system.cpu.itb.perms_faults 8472 # Number of TLB faults due to permissions restrictions 492system.cpu.itb.read_accesses 0 # DTB read accesses 493system.cpu.itb.write_accesses 0 # DTB write accesses 494system.cpu.itb.inst_accesses 57566277 # ITB inst accesses 495system.cpu.itb.hits 57560838 # DTB hits 496system.cpu.itb.misses 5439 # DTB misses 497system.cpu.itb.accesses 57566277 # DTB accesses 498system.cpu.numCycles 333233745 # number of cpu cycles simulated 499system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 500system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 501system.cpu.committedInsts 111935485 # Number of instructions committed 502system.cpu.committedOps 135338943 # Number of ops (including micro ops) committed 503system.cpu.discardedOps 7768370 # Number of ops (including micro ops) which were discarded before commit 504system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching 505system.cpu.quiesceCycles 5383936377 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 506system.cpu.cpi 2.977016 # CPI: cycles per instruction 507system.cpu.ipc 0.335907 # IPC: instructions per cycle 508system.cpu.kern.inst.arm 0 # number of arm instructions executed 509system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed 510system.cpu.tickCycles 228546607 # Number of cycles that the object actually ticked 511system.cpu.idleCycles 104687138 # Total number of cycles that the object has spent stopped 512system.cpu.dcache.tags.replacements 843126 # number of replacements 513system.cpu.dcache.tags.tagsinuse 511.899809 # Cycle average of tags in use 514system.cpu.dcache.tags.total_refs 42573204 # Total number of references to valid blocks. 515system.cpu.dcache.tags.sampled_refs 843638 # Sample count of references to valid blocks. 516system.cpu.dcache.tags.avg_refs 50.463829 # Average number of references to valid blocks. 517system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. 518system.cpu.dcache.tags.occ_blocks::cpu.data 511.899809 # Average occupied blocks per requestor 519system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy 520system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy 521system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 522system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 523system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id 524system.cpu.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 525system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 526system.cpu.dcache.tags.tag_accesses 176066237 # Number of tag accesses 527system.cpu.dcache.tags.data_accesses 176066237 # Number of data accesses 528system.cpu.dcache.ReadReq_hits::cpu.data 23041742 # number of ReadReq hits 529system.cpu.dcache.ReadReq_hits::total 23041742 # number of ReadReq hits 530system.cpu.dcache.WriteReq_hits::cpu.data 18267850 # number of WriteReq hits 531system.cpu.dcache.WriteReq_hits::total 18267850 # number of WriteReq hits 532system.cpu.dcache.SoftPFReq_hits::cpu.data 356487 # number of SoftPFReq hits 533system.cpu.dcache.SoftPFReq_hits::total 356487 # number of SoftPFReq hits 534system.cpu.dcache.LoadLockedReq_hits::cpu.data 443903 # number of LoadLockedReq hits 535system.cpu.dcache.LoadLockedReq_hits::total 443903 # number of LoadLockedReq hits 536system.cpu.dcache.StoreCondReq_hits::cpu.data 460330 # number of StoreCondReq hits 537system.cpu.dcache.StoreCondReq_hits::total 460330 # number of StoreCondReq hits 538system.cpu.dcache.demand_hits::cpu.data 41309592 # number of demand (read+write) hits 539system.cpu.dcache.demand_hits::total 41309592 # number of demand (read+write) hits 540system.cpu.dcache.overall_hits::cpu.data 41666079 # number of overall hits 541system.cpu.dcache.overall_hits::total 41666079 # number of overall hits 542system.cpu.dcache.ReadReq_misses::cpu.data 494543 # number of ReadReq misses 543system.cpu.dcache.ReadReq_misses::total 494543 # number of ReadReq misses 544system.cpu.dcache.WriteReq_misses::cpu.data 548727 # number of WriteReq misses 545system.cpu.dcache.WriteReq_misses::total 548727 # number of WriteReq misses 546system.cpu.dcache.SoftPFReq_misses::cpu.data 169803 # number of SoftPFReq misses 547system.cpu.dcache.SoftPFReq_misses::total 169803 # number of SoftPFReq misses 548system.cpu.dcache.LoadLockedReq_misses::cpu.data 22255 # number of LoadLockedReq misses 549system.cpu.dcache.LoadLockedReq_misses::total 22255 # number of LoadLockedReq misses 550system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 551system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 552system.cpu.dcache.demand_misses::cpu.data 1043270 # number of demand (read+write) misses 553system.cpu.dcache.demand_misses::total 1043270 # number of demand (read+write) misses 554system.cpu.dcache.overall_misses::cpu.data 1213073 # number of overall misses 555system.cpu.dcache.overall_misses::total 1213073 # number of overall misses 556system.cpu.dcache.ReadReq_miss_latency::cpu.data 8036420500 # number of ReadReq miss cycles 557system.cpu.dcache.ReadReq_miss_latency::total 8036420500 # number of ReadReq miss cycles 558system.cpu.dcache.WriteReq_miss_latency::cpu.data 35621632480 # number of WriteReq miss cycles 559system.cpu.dcache.WriteReq_miss_latency::total 35621632480 # number of WriteReq miss cycles 560system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292921000 # number of LoadLockedReq miss cycles 561system.cpu.dcache.LoadLockedReq_miss_latency::total 292921000 # number of LoadLockedReq miss cycles 562system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 563system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles 564system.cpu.dcache.demand_miss_latency::cpu.data 43658052980 # number of demand (read+write) miss cycles 565system.cpu.dcache.demand_miss_latency::total 43658052980 # number of demand (read+write) miss cycles 566system.cpu.dcache.overall_miss_latency::cpu.data 43658052980 # number of overall miss cycles 567system.cpu.dcache.overall_miss_latency::total 43658052980 # number of overall miss cycles 568system.cpu.dcache.ReadReq_accesses::cpu.data 23536285 # number of ReadReq accesses(hits+misses) 569system.cpu.dcache.ReadReq_accesses::total 23536285 # number of ReadReq accesses(hits+misses) 570system.cpu.dcache.WriteReq_accesses::cpu.data 18816577 # number of WriteReq accesses(hits+misses) 571system.cpu.dcache.WriteReq_accesses::total 18816577 # number of WriteReq accesses(hits+misses) 572system.cpu.dcache.SoftPFReq_accesses::cpu.data 526290 # number of SoftPFReq accesses(hits+misses) 573system.cpu.dcache.SoftPFReq_accesses::total 526290 # number of SoftPFReq accesses(hits+misses) 574system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466158 # number of LoadLockedReq accesses(hits+misses) 575system.cpu.dcache.LoadLockedReq_accesses::total 466158 # number of LoadLockedReq accesses(hits+misses) 576system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses) 577system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses) 578system.cpu.dcache.demand_accesses::cpu.data 42352862 # number of demand (read+write) accesses 579system.cpu.dcache.demand_accesses::total 42352862 # number of demand (read+write) accesses 580system.cpu.dcache.overall_accesses::cpu.data 42879152 # number of overall (read+write) accesses 581system.cpu.dcache.overall_accesses::total 42879152 # number of overall (read+write) accesses 582system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021012 # miss rate for ReadReq accesses 583system.cpu.dcache.ReadReq_miss_rate::total 0.021012 # miss rate for ReadReq accesses 584system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029162 # miss rate for WriteReq accesses 585system.cpu.dcache.WriteReq_miss_rate::total 0.029162 # miss rate for WriteReq accesses 586system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322642 # miss rate for SoftPFReq accesses 587system.cpu.dcache.SoftPFReq_miss_rate::total 0.322642 # miss rate for SoftPFReq accesses 588system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047741 # miss rate for LoadLockedReq accesses 589system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047741 # miss rate for LoadLockedReq accesses 590system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 591system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 592system.cpu.dcache.demand_miss_rate::cpu.data 0.024633 # miss rate for demand accesses 593system.cpu.dcache.demand_miss_rate::total 0.024633 # miss rate for demand accesses 594system.cpu.dcache.overall_miss_rate::cpu.data 0.028291 # miss rate for overall accesses 595system.cpu.dcache.overall_miss_rate::total 0.028291 # miss rate for overall accesses 596system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16250.195635 # average ReadReq miss latency 597system.cpu.dcache.ReadReq_avg_miss_latency::total 16250.195635 # average ReadReq miss latency 598system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64916.857527 # average WriteReq miss latency 599system.cpu.dcache.WriteReq_avg_miss_latency::total 64916.857527 # average WriteReq miss latency 600system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13162.031004 # average LoadLockedReq miss latency 601system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13162.031004 # average LoadLockedReq miss latency 602system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency 603system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency 604system.cpu.dcache.demand_avg_miss_latency::cpu.data 41847.319467 # average overall miss latency 605system.cpu.dcache.demand_avg_miss_latency::total 41847.319467 # average overall miss latency 606system.cpu.dcache.overall_avg_miss_latency::cpu.data 35989.633748 # average overall miss latency 607system.cpu.dcache.overall_avg_miss_latency::total 35989.633748 # average overall miss latency 608system.cpu.dcache.blocked_cycles::no_mshrs 277 # number of cycles access was blocked 609system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 610system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 611system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 612system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.043478 # average number of cycles each access was blocked 613system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 614system.cpu.dcache.fast_writes 0 # number of fast writes performed 615system.cpu.dcache.cache_copies 0 # number of cache copies performed 616system.cpu.dcache.writebacks::writebacks 700279 # number of writebacks 617system.cpu.dcache.writebacks::total 700279 # number of writebacks 618system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76721 # number of ReadReq MSHR hits 619system.cpu.dcache.ReadReq_mshr_hits::total 76721 # number of ReadReq MSHR hits 620system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249708 # number of WriteReq MSHR hits 621system.cpu.dcache.WriteReq_mshr_hits::total 249708 # number of WriteReq MSHR hits 622system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14008 # number of LoadLockedReq MSHR hits 623system.cpu.dcache.LoadLockedReq_mshr_hits::total 14008 # number of LoadLockedReq MSHR hits 624system.cpu.dcache.demand_mshr_hits::cpu.data 326429 # number of demand (read+write) MSHR hits 625system.cpu.dcache.demand_mshr_hits::total 326429 # number of demand (read+write) MSHR hits 626system.cpu.dcache.overall_mshr_hits::cpu.data 326429 # number of overall MSHR hits 627system.cpu.dcache.overall_mshr_hits::total 326429 # number of overall MSHR hits 628system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417822 # number of ReadReq MSHR misses 629system.cpu.dcache.ReadReq_mshr_misses::total 417822 # number of ReadReq MSHR misses 630system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299019 # number of WriteReq MSHR misses 631system.cpu.dcache.WriteReq_mshr_misses::total 299019 # number of WriteReq MSHR misses 632system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121366 # number of SoftPFReq MSHR misses 633system.cpu.dcache.SoftPFReq_mshr_misses::total 121366 # number of SoftPFReq MSHR misses 634system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8247 # number of LoadLockedReq MSHR misses 635system.cpu.dcache.LoadLockedReq_mshr_misses::total 8247 # number of LoadLockedReq MSHR misses 636system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 637system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 638system.cpu.dcache.demand_mshr_misses::cpu.data 716841 # number of demand (read+write) MSHR misses 639system.cpu.dcache.demand_mshr_misses::total 716841 # number of demand (read+write) MSHR misses 640system.cpu.dcache.overall_mshr_misses::cpu.data 838207 # number of overall MSHR misses 641system.cpu.dcache.overall_mshr_misses::total 838207 # number of overall MSHR misses 642system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 643system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable 644system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 645system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 646system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 647system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 648system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6533285000 # number of ReadReq MSHR miss cycles 649system.cpu.dcache.ReadReq_mshr_miss_latency::total 6533285000 # number of ReadReq MSHR miss cycles 650system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19191527000 # number of WriteReq MSHR miss cycles 651system.cpu.dcache.WriteReq_mshr_miss_latency::total 19191527000 # number of WriteReq MSHR miss cycles 652system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1710229000 # number of SoftPFReq MSHR miss cycles 653system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1710229000 # number of SoftPFReq MSHR miss cycles 654system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 114982000 # number of LoadLockedReq MSHR miss cycles 655system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 114982000 # number of LoadLockedReq MSHR miss cycles 656system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 657system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles 658system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25724812000 # number of demand (read+write) MSHR miss cycles 659system.cpu.dcache.demand_mshr_miss_latency::total 25724812000 # number of demand (read+write) MSHR miss cycles 660system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27435041000 # number of overall MSHR miss cycles 661system.cpu.dcache.overall_mshr_miss_latency::total 27435041000 # number of overall MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277494000 # number of ReadReq MSHR uncacheable cycles 663system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277494000 # number of ReadReq MSHR uncacheable cycles 664system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5085199500 # number of WriteReq MSHR uncacheable cycles 665system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5085199500 # number of WriteReq MSHR uncacheable cycles 666system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11362693500 # number of overall MSHR uncacheable cycles 667system.cpu.dcache.overall_mshr_uncacheable_latency::total 11362693500 # number of overall MSHR uncacheable cycles 668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017752 # mshr miss rate for ReadReq accesses 669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017752 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015891 # mshr miss rate for WriteReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015891 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230607 # mshr miss rate for SoftPFReq accesses 673system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230607 # mshr miss rate for SoftPFReq accesses 674system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017691 # mshr miss rate for LoadLockedReq accesses 675system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017691 # mshr miss rate for LoadLockedReq accesses 676system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 677system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016925 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.016925 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019548 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.019548 # mshr miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15636.527038 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15636.527038 # average ReadReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64181.630599 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64181.630599 # average WriteReq mshr miss latency 686system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.500091 # average SoftPFReq mshr miss latency 687system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.500091 # average SoftPFReq mshr miss latency 688system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13942.282042 # average LoadLockedReq mshr miss latency 689system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13942.282042 # average LoadLockedReq mshr miss latency 690system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 691system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency 692system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35886.356947 # average overall mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::total 35886.356947 # average overall mshr miss latency 694system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32730.627399 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::total 32730.627399 # average overall mshr miss latency 696system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201654.159974 # average ReadReq mshr uncacheable latency 697system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201654.159974 # average ReadReq mshr uncacheable latency 698system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184353.230133 # average WriteReq mshr uncacheable latency 699system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184353.230133 # average WriteReq mshr uncacheable latency 700system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193526.135164 # average overall mshr uncacheable latency 701system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193526.135164 # average overall mshr uncacheable latency 702system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 703system.cpu.icache.tags.replacements 2897280 # number of replacements 704system.cpu.icache.tags.tagsinuse 511.208865 # Cycle average of tags in use 705system.cpu.icache.tags.total_refs 54654096 # Total number of references to valid blocks. 706system.cpu.icache.tags.sampled_refs 2897792 # Sample count of references to valid blocks. 707system.cpu.icache.tags.avg_refs 18.860600 # Average number of references to valid blocks. 708system.cpu.icache.tags.warmup_cycle 18409362500 # Cycle when the warmup percentage was hit. 709system.cpu.icache.tags.occ_blocks::cpu.inst 511.208865 # Average occupied blocks per requestor 710system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy 711system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy 712system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 714system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 715system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id 716system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 717system.cpu.icache.tags.tag_accesses 60449703 # Number of tag accesses 718system.cpu.icache.tags.data_accesses 60449703 # Number of data accesses 719system.cpu.icache.ReadReq_hits::cpu.inst 54654096 # number of ReadReq hits 720system.cpu.icache.ReadReq_hits::total 54654096 # number of ReadReq hits 721system.cpu.icache.demand_hits::cpu.inst 54654096 # number of demand (read+write) hits 722system.cpu.icache.demand_hits::total 54654096 # number of demand (read+write) hits 723system.cpu.icache.overall_hits::cpu.inst 54654096 # number of overall hits 724system.cpu.icache.overall_hits::total 54654096 # number of overall hits 725system.cpu.icache.ReadReq_misses::cpu.inst 2897804 # number of ReadReq misses 726system.cpu.icache.ReadReq_misses::total 2897804 # number of ReadReq misses 727system.cpu.icache.demand_misses::cpu.inst 2897804 # number of demand (read+write) misses 728system.cpu.icache.demand_misses::total 2897804 # number of demand (read+write) misses 729system.cpu.icache.overall_misses::cpu.inst 2897804 # number of overall misses 730system.cpu.icache.overall_misses::total 2897804 # number of overall misses 731system.cpu.icache.ReadReq_miss_latency::cpu.inst 40494431000 # number of ReadReq miss cycles 732system.cpu.icache.ReadReq_miss_latency::total 40494431000 # number of ReadReq miss cycles 733system.cpu.icache.demand_miss_latency::cpu.inst 40494431000 # number of demand (read+write) miss cycles 734system.cpu.icache.demand_miss_latency::total 40494431000 # number of demand (read+write) miss cycles 735system.cpu.icache.overall_miss_latency::cpu.inst 40494431000 # number of overall miss cycles 736system.cpu.icache.overall_miss_latency::total 40494431000 # number of overall miss cycles 737system.cpu.icache.ReadReq_accesses::cpu.inst 57551900 # number of ReadReq accesses(hits+misses) 738system.cpu.icache.ReadReq_accesses::total 57551900 # number of ReadReq accesses(hits+misses) 739system.cpu.icache.demand_accesses::cpu.inst 57551900 # number of demand (read+write) accesses 740system.cpu.icache.demand_accesses::total 57551900 # number of demand (read+write) accesses 741system.cpu.icache.overall_accesses::cpu.inst 57551900 # number of overall (read+write) accesses 742system.cpu.icache.overall_accesses::total 57551900 # number of overall (read+write) accesses 743system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050351 # miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_miss_rate::total 0.050351 # miss rate for ReadReq accesses 745system.cpu.icache.demand_miss_rate::cpu.inst 0.050351 # miss rate for demand accesses 746system.cpu.icache.demand_miss_rate::total 0.050351 # miss rate for demand accesses 747system.cpu.icache.overall_miss_rate::cpu.inst 0.050351 # miss rate for overall accesses 748system.cpu.icache.overall_miss_rate::total 0.050351 # miss rate for overall accesses 749system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13974.178723 # average ReadReq miss latency 750system.cpu.icache.ReadReq_avg_miss_latency::total 13974.178723 # average ReadReq miss latency 751system.cpu.icache.demand_avg_miss_latency::cpu.inst 13974.178723 # average overall miss latency 752system.cpu.icache.demand_avg_miss_latency::total 13974.178723 # average overall miss latency 753system.cpu.icache.overall_avg_miss_latency::cpu.inst 13974.178723 # average overall miss latency 754system.cpu.icache.overall_avg_miss_latency::total 13974.178723 # average overall miss latency 755system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 756system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 760system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.icache.fast_writes 0 # number of fast writes performed 762system.cpu.icache.cache_copies 0 # number of cache copies performed 763system.cpu.icache.writebacks::writebacks 2897280 # number of writebacks 764system.cpu.icache.writebacks::total 2897280 # number of writebacks 765system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897804 # number of ReadReq MSHR misses 766system.cpu.icache.ReadReq_mshr_misses::total 2897804 # number of ReadReq MSHR misses 767system.cpu.icache.demand_mshr_misses::cpu.inst 2897804 # number of demand (read+write) MSHR misses 768system.cpu.icache.demand_mshr_misses::total 2897804 # number of demand (read+write) MSHR misses 769system.cpu.icache.overall_mshr_misses::cpu.inst 2897804 # number of overall MSHR misses 770system.cpu.icache.overall_mshr_misses::total 2897804 # number of overall MSHR misses 771system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable 772system.cpu.icache.ReadReq_mshr_uncacheable::total 3763 # number of ReadReq MSHR uncacheable 773system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses 774system.cpu.icache.overall_mshr_uncacheable_misses::total 3763 # number of overall MSHR uncacheable misses 775system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37596628000 # number of ReadReq MSHR miss cycles 776system.cpu.icache.ReadReq_mshr_miss_latency::total 37596628000 # number of ReadReq MSHR miss cycles 777system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37596628000 # number of demand (read+write) MSHR miss cycles 778system.cpu.icache.demand_mshr_miss_latency::total 37596628000 # number of demand (read+write) MSHR miss cycles 779system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37596628000 # number of overall MSHR miss cycles 780system.cpu.icache.overall_mshr_miss_latency::total 37596628000 # number of overall MSHR miss cycles 781system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485921500 # number of ReadReq MSHR uncacheable cycles 782system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485921500 # number of ReadReq MSHR uncacheable cycles 783system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485921500 # number of overall MSHR uncacheable cycles 784system.cpu.icache.overall_mshr_uncacheable_latency::total 485921500 # number of overall MSHR uncacheable cycles 785system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for ReadReq accesses 786system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050351 # mshr miss rate for ReadReq accesses 787system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for demand accesses 788system.cpu.icache.demand_mshr_miss_rate::total 0.050351 # mshr miss rate for demand accesses 789system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for overall accesses 790system.cpu.icache.overall_mshr_miss_rate::total 0.050351 # mshr miss rate for overall accesses 791system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12974.179068 # average ReadReq mshr miss latency 792system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12974.179068 # average ReadReq mshr miss latency 793system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12974.179068 # average overall mshr miss latency 794system.cpu.icache.demand_avg_mshr_miss_latency::total 12974.179068 # average overall mshr miss latency 795system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12974.179068 # average overall mshr miss latency 796system.cpu.icache.overall_avg_mshr_miss_latency::total 12974.179068 # average overall mshr miss latency 797system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency 798system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency 799system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency 800system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency 801system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 802system.cpu.l2cache.tags.replacements 96402 # number of replacements 803system.cpu.l2cache.tags.tagsinuse 65018.831836 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 7030117 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 161646 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 43.490819 # Average number of references to valid blocks. 807system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 808system.cpu.l2cache.tags.occ_blocks::writebacks 47317.372704 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 63.574942 # Average occupied blocks per requestor 810system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000511 # Average occupied blocks per requestor 811system.cpu.l2cache.tags.occ_blocks::cpu.inst 12247.402145 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.data 5390.481534 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_percent::writebacks 0.722006 # Average percentage of cache occupancy 814system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000970 # Average percentage of cache occupancy 815system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 816system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186881 # Average percentage of cache occupancy 817system.cpu.l2cache.tags.occ_percent::cpu.data 0.082252 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::total 0.992109 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id 820system.cpu.l2cache.tags.occ_task_id_blocks::1024 65199 # Occupied blocks per task id 821system.cpu.l2cache.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2290 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6877 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55918 # Occupied blocks per task id 827system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000687 # Percentage of cache occupancy per task id 828system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994858 # Percentage of cache occupancy per task id 829system.cpu.l2cache.tags.tag_accesses 60477611 # Number of tag accesses 830system.cpu.l2cache.tags.data_accesses 60477611 # Number of data accesses 831system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71430 # number of ReadReq hits 832system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4620 # number of ReadReq hits 833system.cpu.l2cache.ReadReq_hits::total 76050 # number of ReadReq hits 834system.cpu.l2cache.WritebackDirty_hits::writebacks 700279 # number of WritebackDirty hits 835system.cpu.l2cache.WritebackDirty_hits::total 700279 # number of WritebackDirty hits 836system.cpu.l2cache.WritebackClean_hits::writebacks 2845639 # number of WritebackClean hits 837system.cpu.l2cache.WritebackClean_hits::total 2845639 # number of WritebackClean hits 838system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits 839system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits 840system.cpu.l2cache.ReadExReq_hits::cpu.data 165313 # number of ReadExReq hits 841system.cpu.l2cache.ReadExReq_hits::total 165313 # number of ReadExReq hits 842system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2874818 # number of ReadCleanReq hits 843system.cpu.l2cache.ReadCleanReq_hits::total 2874818 # number of ReadCleanReq hits 844system.cpu.l2cache.ReadSharedReq_hits::cpu.data 533139 # number of ReadSharedReq hits 845system.cpu.l2cache.ReadSharedReq_hits::total 533139 # number of ReadSharedReq hits 846system.cpu.l2cache.demand_hits::cpu.dtb.walker 71430 # number of demand (read+write) hits 847system.cpu.l2cache.demand_hits::cpu.itb.walker 4620 # number of demand (read+write) hits 848system.cpu.l2cache.demand_hits::cpu.inst 2874818 # number of demand (read+write) hits 849system.cpu.l2cache.demand_hits::cpu.data 698452 # number of demand (read+write) hits 850system.cpu.l2cache.demand_hits::total 3649320 # number of demand (read+write) hits 851system.cpu.l2cache.overall_hits::cpu.dtb.walker 71430 # number of overall hits 852system.cpu.l2cache.overall_hits::cpu.itb.walker 4620 # number of overall hits 853system.cpu.l2cache.overall_hits::cpu.inst 2874818 # number of overall hits 854system.cpu.l2cache.overall_hits::cpu.data 698452 # number of overall hits 855system.cpu.l2cache.overall_hits::total 3649320 # number of overall hits 856system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 119 # number of ReadReq misses 857system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 858system.cpu.l2cache.ReadReq_misses::total 120 # number of ReadReq misses 859system.cpu.l2cache.UpgradeReq_misses::cpu.data 2736 # number of UpgradeReq misses 860system.cpu.l2cache.UpgradeReq_misses::total 2736 # number of UpgradeReq misses 861system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 862system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 863system.cpu.l2cache.ReadExReq_misses::cpu.data 130926 # number of ReadExReq misses 864system.cpu.l2cache.ReadExReq_misses::total 130926 # number of ReadExReq misses 865system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22960 # number of ReadCleanReq misses 866system.cpu.l2cache.ReadCleanReq_misses::total 22960 # number of ReadCleanReq misses 867system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14291 # number of ReadSharedReq misses 868system.cpu.l2cache.ReadSharedReq_misses::total 14291 # number of ReadSharedReq misses 869system.cpu.l2cache.demand_misses::cpu.dtb.walker 119 # number of demand (read+write) misses 870system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 871system.cpu.l2cache.demand_misses::cpu.inst 22960 # number of demand (read+write) misses 872system.cpu.l2cache.demand_misses::cpu.data 145217 # number of demand (read+write) misses 873system.cpu.l2cache.demand_misses::total 168297 # number of demand (read+write) misses 874system.cpu.l2cache.overall_misses::cpu.dtb.walker 119 # number of overall misses 875system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 876system.cpu.l2cache.overall_misses::cpu.inst 22960 # number of overall misses 877system.cpu.l2cache.overall_misses::cpu.data 145217 # number of overall misses 878system.cpu.l2cache.overall_misses::total 168297 # number of overall misses 879system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 16819500 # number of ReadReq miss cycles 880system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 132500 # number of ReadReq miss cycles 881system.cpu.l2cache.ReadReq_miss_latency::total 16952000 # number of ReadReq miss cycles 882system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 3065500 # number of UpgradeReq miss cycles 883system.cpu.l2cache.UpgradeReq_miss_latency::total 3065500 # number of UpgradeReq miss cycles 884system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 885system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 886system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16775103500 # number of ReadExReq miss cycles 887system.cpu.l2cache.ReadExReq_miss_latency::total 16775103500 # number of ReadExReq miss cycles 888system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2997728000 # number of ReadCleanReq miss cycles 889system.cpu.l2cache.ReadCleanReq_miss_latency::total 2997728000 # number of ReadCleanReq miss cycles 890system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1890435000 # number of ReadSharedReq miss cycles 891system.cpu.l2cache.ReadSharedReq_miss_latency::total 1890435000 # number of ReadSharedReq miss cycles 892system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 16819500 # number of demand (read+write) miss cycles 893system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 132500 # number of demand (read+write) miss cycles 894system.cpu.l2cache.demand_miss_latency::cpu.inst 2997728000 # number of demand (read+write) miss cycles 895system.cpu.l2cache.demand_miss_latency::cpu.data 18665538500 # number of demand (read+write) miss cycles 896system.cpu.l2cache.demand_miss_latency::total 21680218500 # number of demand (read+write) miss cycles 897system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 16819500 # number of overall miss cycles 898system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 132500 # number of overall miss cycles 899system.cpu.l2cache.overall_miss_latency::cpu.inst 2997728000 # number of overall miss cycles 900system.cpu.l2cache.overall_miss_latency::cpu.data 18665538500 # number of overall miss cycles 901system.cpu.l2cache.overall_miss_latency::total 21680218500 # number of overall miss cycles 902system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71549 # number of ReadReq accesses(hits+misses) 903system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4621 # number of ReadReq accesses(hits+misses) 904system.cpu.l2cache.ReadReq_accesses::total 76170 # number of ReadReq accesses(hits+misses) 905system.cpu.l2cache.WritebackDirty_accesses::writebacks 700279 # number of WritebackDirty accesses(hits+misses) 906system.cpu.l2cache.WritebackDirty_accesses::total 700279 # number of WritebackDirty accesses(hits+misses) 907system.cpu.l2cache.WritebackClean_accesses::writebacks 2845639 # number of WritebackClean accesses(hits+misses) 908system.cpu.l2cache.WritebackClean_accesses::total 2845639 # number of WritebackClean accesses(hits+misses) 909system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2785 # number of UpgradeReq accesses(hits+misses) 910system.cpu.l2cache.UpgradeReq_accesses::total 2785 # number of UpgradeReq accesses(hits+misses) 911system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 912system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 913system.cpu.l2cache.ReadExReq_accesses::cpu.data 296239 # number of ReadExReq accesses(hits+misses) 914system.cpu.l2cache.ReadExReq_accesses::total 296239 # number of ReadExReq accesses(hits+misses) 915system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2897778 # number of ReadCleanReq accesses(hits+misses) 916system.cpu.l2cache.ReadCleanReq_accesses::total 2897778 # number of ReadCleanReq accesses(hits+misses) 917system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 547430 # number of ReadSharedReq accesses(hits+misses) 918system.cpu.l2cache.ReadSharedReq_accesses::total 547430 # number of ReadSharedReq accesses(hits+misses) 919system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71549 # number of demand (read+write) accesses 920system.cpu.l2cache.demand_accesses::cpu.itb.walker 4621 # number of demand (read+write) accesses 921system.cpu.l2cache.demand_accesses::cpu.inst 2897778 # number of demand (read+write) accesses 922system.cpu.l2cache.demand_accesses::cpu.data 843669 # number of demand (read+write) accesses 923system.cpu.l2cache.demand_accesses::total 3817617 # number of demand (read+write) accesses 924system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71549 # number of overall (read+write) accesses 925system.cpu.l2cache.overall_accesses::cpu.itb.walker 4621 # number of overall (read+write) accesses 926system.cpu.l2cache.overall_accesses::cpu.inst 2897778 # number of overall (read+write) accesses 927system.cpu.l2cache.overall_accesses::cpu.data 843669 # number of overall (read+write) accesses 928system.cpu.l2cache.overall_accesses::total 3817617 # number of overall (read+write) accesses 929system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001663 # miss rate for ReadReq accesses 930system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000216 # miss rate for ReadReq accesses 931system.cpu.l2cache.ReadReq_miss_rate::total 0.001575 # miss rate for ReadReq accesses 932system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982406 # miss rate for UpgradeReq accesses 933system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982406 # miss rate for UpgradeReq accesses 934system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 935system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 936system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.441961 # miss rate for ReadExReq accesses 937system.cpu.l2cache.ReadExReq_miss_rate::total 0.441961 # miss rate for ReadExReq accesses 938system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007923 # miss rate for ReadCleanReq accesses 939system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007923 # miss rate for ReadCleanReq accesses 940system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026106 # miss rate for ReadSharedReq accesses 941system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026106 # miss rate for ReadSharedReq accesses 942system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001663 # miss rate for demand accesses 943system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000216 # miss rate for demand accesses 944system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007923 # miss rate for demand accesses 945system.cpu.l2cache.demand_miss_rate::cpu.data 0.172126 # miss rate for demand accesses 946system.cpu.l2cache.demand_miss_rate::total 0.044084 # miss rate for demand accesses 947system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001663 # miss rate for overall accesses 948system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000216 # miss rate for overall accesses 949system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007923 # miss rate for overall accesses 950system.cpu.l2cache.overall_miss_rate::cpu.data 0.172126 # miss rate for overall accesses 951system.cpu.l2cache.overall_miss_rate::total 0.044084 # miss rate for overall accesses 952system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141340.336134 # average ReadReq miss latency 953system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132500 # average ReadReq miss latency 954system.cpu.l2cache.ReadReq_avg_miss_latency::total 141266.666667 # average ReadReq miss latency 955system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1120.431287 # average UpgradeReq miss latency 956system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1120.431287 # average UpgradeReq miss latency 957system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency 958system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency 959system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128126.602050 # average ReadExReq miss latency 960system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128126.602050 # average ReadExReq miss latency 961system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130563.066202 # average ReadCleanReq miss latency 962system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130563.066202 # average ReadCleanReq miss latency 963system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132281.505843 # average ReadSharedReq miss latency 964system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132281.505843 # average ReadSharedReq miss latency 965system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141340.336134 # average overall miss latency 966system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency 967system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130563.066202 # average overall miss latency 968system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128535.491712 # average overall miss latency 969system.cpu.l2cache.demand_avg_miss_latency::total 128821.182196 # average overall miss latency 970system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141340.336134 # average overall miss latency 971system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency 972system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130563.066202 # average overall miss latency 973system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128535.491712 # average overall miss latency 974system.cpu.l2cache.overall_avg_miss_latency::total 128821.182196 # average overall miss latency 975system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 976system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 977system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 978system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 979system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 980system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 981system.cpu.l2cache.fast_writes 0 # number of fast writes performed 982system.cpu.l2cache.cache_copies 0 # number of cache copies performed 983system.cpu.l2cache.writebacks::writebacks 87830 # number of writebacks 984system.cpu.l2cache.writebacks::total 87830 # number of writebacks 985system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits 986system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits 987system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 142 # number of ReadSharedReq MSHR hits 988system.cpu.l2cache.ReadSharedReq_mshr_hits::total 142 # number of ReadSharedReq MSHR hits 989system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits 990system.cpu.l2cache.demand_mshr_hits::cpu.data 142 # number of demand (read+write) MSHR hits 991system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 992system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits 993system.cpu.l2cache.overall_mshr_hits::cpu.data 142 # number of overall MSHR hits 994system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits 995system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 119 # number of ReadReq MSHR misses 996system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 997system.cpu.l2cache.ReadReq_mshr_misses::total 120 # number of ReadReq MSHR misses 998system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2736 # number of UpgradeReq MSHR misses 999system.cpu.l2cache.UpgradeReq_mshr_misses::total 2736 # number of UpgradeReq MSHR misses 1000system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1001system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1002system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130926 # number of ReadExReq MSHR misses 1003system.cpu.l2cache.ReadExReq_mshr_misses::total 130926 # number of ReadExReq MSHR misses 1004system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22937 # number of ReadCleanReq MSHR misses 1005system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22937 # number of ReadCleanReq MSHR misses 1006system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14149 # number of ReadSharedReq MSHR misses 1007system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14149 # number of ReadSharedReq MSHR misses 1008system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 119 # number of demand (read+write) MSHR misses 1009system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 1010system.cpu.l2cache.demand_mshr_misses::cpu.inst 22937 # number of demand (read+write) MSHR misses 1011system.cpu.l2cache.demand_mshr_misses::cpu.data 145075 # number of demand (read+write) MSHR misses 1012system.cpu.l2cache.demand_mshr_misses::total 168132 # number of demand (read+write) MSHR misses 1013system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 119 # number of overall MSHR misses 1014system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 1015system.cpu.l2cache.overall_mshr_misses::cpu.inst 22937 # number of overall MSHR misses 1016system.cpu.l2cache.overall_mshr_misses::cpu.data 145075 # number of overall MSHR misses 1017system.cpu.l2cache.overall_mshr_misses::total 168132 # number of overall MSHR misses 1018system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable 1019system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 1020system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34893 # number of ReadReq MSHR uncacheable 1021system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1022system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1023system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses 1024system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1025system.cpu.l2cache.overall_mshr_uncacheable_misses::total 62477 # number of overall MSHR uncacheable misses 1026system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 15629500 # number of ReadReq MSHR miss cycles 1027system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 122500 # number of ReadReq MSHR miss cycles 1028system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15752000 # number of ReadReq MSHR miss cycles 1029system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 193587000 # number of UpgradeReq MSHR miss cycles 1030system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 193587000 # number of UpgradeReq MSHR miss cycles 1031system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142000 # number of SCUpgradeReq MSHR miss cycles 1032system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142000 # number of SCUpgradeReq MSHR miss cycles 1033system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15465843500 # number of ReadExReq MSHR miss cycles 1034system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15465843500 # number of ReadExReq MSHR miss cycles 1035system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2766934500 # number of ReadCleanReq MSHR miss cycles 1036system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2766934500 # number of ReadCleanReq MSHR miss cycles 1037system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1732237500 # number of ReadSharedReq MSHR miss cycles 1038system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1732237500 # number of ReadSharedReq MSHR miss cycles 1039system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15629500 # number of demand (read+write) MSHR miss cycles 1040system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) MSHR miss cycles 1041system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2766934500 # number of demand (read+write) MSHR miss cycles 1042system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17198081000 # number of demand (read+write) MSHR miss cycles 1043system.cpu.l2cache.demand_mshr_miss_latency::total 19980767500 # number of demand (read+write) MSHR miss cycles 1044system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15629500 # number of overall MSHR miss cycles 1045system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 122500 # number of overall MSHR miss cycles 1046system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2766934500 # number of overall MSHR miss cycles 1047system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17198081000 # number of overall MSHR miss cycles 1048system.cpu.l2cache.overall_mshr_miss_latency::total 19980767500 # number of overall MSHR miss cycles 1049system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 427218000 # number of ReadReq MSHR uncacheable cycles 1050system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888307500 # number of ReadReq MSHR uncacheable cycles 1051system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315525500 # number of ReadReq MSHR uncacheable cycles 1052system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4767951000 # number of WriteReq MSHR uncacheable cycles 1053system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4767951000 # number of WriteReq MSHR uncacheable cycles 1054system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 427218000 # number of overall MSHR uncacheable cycles 1055system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10656258500 # number of overall MSHR uncacheable cycles 1056system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11083476500 # number of overall MSHR uncacheable cycles 1057system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for ReadReq accesses 1058system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for ReadReq accesses 1059system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001575 # mshr miss rate for ReadReq accesses 1060system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982406 # mshr miss rate for UpgradeReq accesses 1061system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982406 # mshr miss rate for UpgradeReq accesses 1062system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1063system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1064system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.441961 # mshr miss rate for ReadExReq accesses 1065system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.441961 # mshr miss rate for ReadExReq accesses 1066system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for ReadCleanReq accesses 1067system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007915 # mshr miss rate for ReadCleanReq accesses 1068system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025846 # mshr miss rate for ReadSharedReq accesses 1069system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025846 # mshr miss rate for ReadSharedReq accesses 1070system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for demand accesses 1071system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for demand accesses 1072system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for demand accesses 1073system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171957 # mshr miss rate for demand accesses 1074system.cpu.l2cache.demand_mshr_miss_rate::total 0.044041 # mshr miss rate for demand accesses 1075system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for overall accesses 1076system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for overall accesses 1077system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for overall accesses 1078system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171957 # mshr miss rate for overall accesses 1079system.cpu.l2cache.overall_mshr_miss_rate::total 0.044041 # mshr miss rate for overall accesses 1080system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average ReadReq mshr miss latency 1081system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency 1082system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131266.666667 # average ReadReq mshr miss latency 1083system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70755.482456 # average UpgradeReq mshr miss latency 1084system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70755.482456 # average UpgradeReq mshr miss latency 1085system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency 1086system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency 1087system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118126.602050 # average ReadExReq mshr miss latency 1088system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118126.602050 # average ReadExReq mshr miss latency 1089system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120631.926582 # average ReadCleanReq mshr miss latency 1090system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120631.926582 # average ReadCleanReq mshr miss latency 1091system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122428.263482 # average ReadSharedReq mshr miss latency 1092system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122428.263482 # average ReadSharedReq mshr miss latency 1093system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average overall mshr miss latency 1094system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1095system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120631.926582 # average overall mshr miss latency 1096system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118546.138204 # average overall mshr miss latency 1097system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118839.765779 # average overall mshr miss latency 1098system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average overall mshr miss latency 1099system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1100system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120631.926582 # average overall mshr miss latency 1101system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118546.138204 # average overall mshr miss latency 1102system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118839.765779 # average overall mshr miss latency 1103system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency 1104system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189152.184388 # average ReadReq mshr uncacheable latency 1105system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180996.919153 # average ReadReq mshr uncacheable latency 1106system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172852.051914 # average WriteReq mshr uncacheable latency 1107system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172852.051914 # average WriteReq mshr uncacheable latency 1108system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency 1109system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181494.336955 # average overall mshr uncacheable latency 1110system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177400.907534 # average overall mshr uncacheable latency 1111system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1112system.cpu.toL2Bus.snoop_filter.tot_requests 7513660 # Total number of requests made to the snoop filter. 1113system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772219 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1114system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58915 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1115system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter. 1116system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1117system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1118system.cpu.toL2Bus.trans_dist::ReadReq 134081 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::ReadResp 3579527 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::WritebackDirty 824300 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::WritebackClean 2845639 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::CleanEvict 144382 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadExReq 296239 # Transaction distribution 1129system.cpu.toL2Bus.trans_dist::ReadExResp 296239 # Transaction distribution 1130system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897804 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::ReadSharedReq 547664 # Transaction distribution 1132system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1133system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8648746 # Packet count per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2646408 # Packet count per connected master and slave (bytes) 1135system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15180 # Packet count per connected master and slave (bytes) 1136system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160178 # Packet count per connected master and slave (bytes) 1137system.cpu.toL2Bus.pkt_count::total 11470512 # Packet count per connected master and slave (bytes) 1138system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 367819456 # Cumulative packet size per connected master and slave (bytes) 1139system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99009385 # Cumulative packet size per connected master and slave (bytes) 1140system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18484 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 286196 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu.toL2Bus.pkt_size::total 467133521 # Cumulative packet size per connected master and slave (bytes) 1143system.cpu.toL2Bus.snoops 192542 # Total snoops (count) 1144system.cpu.toL2Bus.snoop_fanout::samples 4075210 # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::mean 0.021724 # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::stdev 0.145782 # Request fanout histogram 1147system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::0 3986679 97.83% 97.83% # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::1 88531 2.17% 100.00% # Request fanout histogram 1150system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1152system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1154system.cpu.toL2Bus.snoop_fanout::total 4075210 # Request fanout histogram 1155system.cpu.toL2Bus.reqLayer0.occupancy 7434516500 # Layer occupancy (ticks) 1156system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1157system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) 1158system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1159system.cpu.toL2Bus.respLayer0.occupancy 4352877441 # Layer occupancy (ticks) 1160system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1161system.cpu.toL2Bus.respLayer1.occupancy 1312009118 # Layer occupancy (ticks) 1162system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1163system.cpu.toL2Bus.respLayer2.occupancy 10561994 # Layer occupancy (ticks) 1164system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1165system.cpu.toL2Bus.respLayer3.occupancy 88663416 # Layer occupancy (ticks) 1166system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1167system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1168system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1169system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1170system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1171system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1195system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1211system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) 1221system.iobus.reqLayer0.occupancy 46504000 # Layer occupancy (ticks) 1222system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1223system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 1224system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1225system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) 1226system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1227system.iobus.reqLayer3.occupancy 14500 # Layer occupancy (ticks) 1228system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1229system.iobus.reqLayer6.occupancy 89000 # Layer occupancy (ticks) 1230system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1231system.iobus.reqLayer7.occupancy 569500 # Layer occupancy (ticks) 1232system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1233system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1234system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1235system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 1236system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1237system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 1238system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1239system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 1240system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1241system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) 1242system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1244system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1246system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1247system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 1248system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1249system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 1250system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1251system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) 1252system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1253system.iobus.reqLayer23.occupancy 6052000 # Layer occupancy (ticks) 1254system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1255system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) 1256system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1257system.iobus.reqLayer25.occupancy 33698500 # Layer occupancy (ticks) 1258system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1259system.iobus.reqLayer26.occupancy 124500 # Layer occupancy (ticks) 1260system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1261system.iobus.reqLayer27.occupancy 186339520 # Layer occupancy (ticks) 1262system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1263system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) 1264system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1265system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1266system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1267system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1268system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1269system.iocache.tags.replacements 36424 # number of replacements 1270system.iocache.tags.tagsinuse 1.036928 # Cycle average of tags in use 1271system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1272system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1273system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1274system.iocache.tags.warmup_cycle 274875272000 # Cycle when the warmup percentage was hit. 1275system.iocache.tags.occ_blocks::realview.ide 1.036928 # Average occupied blocks per requestor 1276system.iocache.tags.occ_percent::realview.ide 0.064808 # Average percentage of cache occupancy 1277system.iocache.tags.occ_percent::total 0.064808 # Average percentage of cache occupancy 1278system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1279system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1280system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1281system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1282system.iocache.tags.data_accesses 328122 # Number of data accesses 1283system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1284system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1285system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1286system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1287system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1288system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1289system.iocache.overall_misses::realview.ide 234 # number of overall misses 1290system.iocache.overall_misses::total 234 # number of overall misses 1291system.iocache.ReadReq_miss_latency::realview.ide 29051377 # number of ReadReq miss cycles 1292system.iocache.ReadReq_miss_latency::total 29051377 # number of ReadReq miss cycles 1293system.iocache.WriteLineReq_miss_latency::realview.ide 4719366143 # number of WriteLineReq miss cycles 1294system.iocache.WriteLineReq_miss_latency::total 4719366143 # number of WriteLineReq miss cycles 1295system.iocache.demand_miss_latency::realview.ide 29051377 # number of demand (read+write) miss cycles 1296system.iocache.demand_miss_latency::total 29051377 # number of demand (read+write) miss cycles 1297system.iocache.overall_miss_latency::realview.ide 29051377 # number of overall miss cycles 1298system.iocache.overall_miss_latency::total 29051377 # number of overall miss cycles 1299system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1300system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1301system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1302system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1303system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1304system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1305system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1306system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1307system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1308system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1309system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1310system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1311system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1312system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1313system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1314system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1315system.iocache.ReadReq_avg_miss_latency::realview.ide 124151.183761 # average ReadReq miss latency 1316system.iocache.ReadReq_avg_miss_latency::total 124151.183761 # average ReadReq miss latency 1317system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130282.855096 # average WriteLineReq miss latency 1318system.iocache.WriteLineReq_avg_miss_latency::total 130282.855096 # average WriteLineReq miss latency 1319system.iocache.demand_avg_miss_latency::realview.ide 124151.183761 # average overall miss latency 1320system.iocache.demand_avg_miss_latency::total 124151.183761 # average overall miss latency 1321system.iocache.overall_avg_miss_latency::realview.ide 124151.183761 # average overall miss latency 1322system.iocache.overall_avg_miss_latency::total 124151.183761 # average overall miss latency 1323system.iocache.blocked_cycles::no_mshrs 731 # number of cycles access was blocked 1324system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1325system.iocache.blocked::no_mshrs 70 # number of cycles access was blocked 1326system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1327system.iocache.avg_blocked_cycles::no_mshrs 10.442857 # average number of cycles each access was blocked 1328system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1329system.iocache.fast_writes 0 # number of fast writes performed 1330system.iocache.cache_copies 0 # number of cache copies performed 1331system.iocache.writebacks::writebacks 36190 # number of writebacks 1332system.iocache.writebacks::total 36190 # number of writebacks 1333system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1334system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1335system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1336system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1337system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1338system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1339system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1340system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1341system.iocache.ReadReq_mshr_miss_latency::realview.ide 17351377 # number of ReadReq MSHR miss cycles 1342system.iocache.ReadReq_mshr_miss_latency::total 17351377 # number of ReadReq MSHR miss cycles 1343system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2908166143 # number of WriteLineReq MSHR miss cycles 1344system.iocache.WriteLineReq_mshr_miss_latency::total 2908166143 # number of WriteLineReq MSHR miss cycles 1345system.iocache.demand_mshr_miss_latency::realview.ide 17351377 # number of demand (read+write) MSHR miss cycles 1346system.iocache.demand_mshr_miss_latency::total 17351377 # number of demand (read+write) MSHR miss cycles 1347system.iocache.overall_mshr_miss_latency::realview.ide 17351377 # number of overall MSHR miss cycles 1348system.iocache.overall_mshr_miss_latency::total 17351377 # number of overall MSHR miss cycles 1349system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1350system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1351system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1352system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1353system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1354system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1355system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1356system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1357system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74151.183761 # average ReadReq mshr miss latency 1358system.iocache.ReadReq_avg_mshr_miss_latency::total 74151.183761 # average ReadReq mshr miss latency 1359system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80282.855096 # average WriteLineReq mshr miss latency 1360system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80282.855096 # average WriteLineReq mshr miss latency 1361system.iocache.demand_avg_mshr_miss_latency::realview.ide 74151.183761 # average overall mshr miss latency 1362system.iocache.demand_avg_mshr_miss_latency::total 74151.183761 # average overall mshr miss latency 1363system.iocache.overall_avg_mshr_miss_latency::realview.ide 74151.183761 # average overall mshr miss latency 1364system.iocache.overall_avg_mshr_miss_latency::total 74151.183761 # average overall mshr miss latency 1365system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1366system.membus.trans_dist::ReadReq 34893 # Transaction distribution 1367system.membus.trans_dist::ReadResp 72333 # Transaction distribution 1368system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1369system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1370system.membus.trans_dist::WritebackDirty 124020 # Transaction distribution 1371system.membus.trans_dist::CleanEvict 8585 # Transaction distribution 1372system.membus.trans_dist::UpgradeReq 4599 # Transaction distribution 1373system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1374system.membus.trans_dist::UpgradeResp 4601 # Transaction distribution 1375system.membus.trans_dist::ReadExReq 129063 # Transaction distribution 1376system.membus.trans_dist::ReadExResp 129063 # Transaction distribution 1377system.membus.trans_dist::ReadSharedReq 37440 # Transaction distribution 1378system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1379system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1380system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1381system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1382system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) 1383system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455241 # Packet count per connected master and slave (bytes) 1384system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562809 # Packet count per connected master and slave (bytes) 1385system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) 1386system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) 1387system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) 1388system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1389system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) 1390system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) 1391system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16504224 # Cumulative packet size per connected master and slave (bytes) 1392system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16668009 # Cumulative packet size per connected master and slave (bytes) 1393system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1394system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1395system.membus.pkt_size::total 18985129 # Cumulative packet size per connected master and slave (bytes) 1396system.membus.snoops 506 # Total snoops (count) 1397system.membus.snoop_fanout::samples 402632 # Request fanout histogram 1398system.membus.snoop_fanout::mean 1 # Request fanout histogram 1399system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1400system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1401system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1402system.membus.snoop_fanout::1 402632 100.00% 100.00% # Request fanout histogram 1403system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1404system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1405system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1406system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1407system.membus.snoop_fanout::total 402632 # Request fanout histogram 1408system.membus.reqLayer0.occupancy 87539000 # Layer occupancy (ticks) 1409system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1410system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) 1411system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1412system.membus.reqLayer2.occupancy 1722000 # Layer occupancy (ticks) 1413system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1414system.membus.reqLayer5.occupancy 878086902 # Layer occupancy (ticks) 1415system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1416system.membus.respLayer2.occupancy 999035643 # Layer occupancy (ticks) 1417system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1418system.membus.respLayer3.occupancy 64196432 # Layer occupancy (ticks) 1419system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1420system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1421system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1422system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1423system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1424system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1425system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1426system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1427system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1428system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1429system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1430system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1431system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1432system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1433system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1434system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1435system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1436system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1437system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1438system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1439system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1440system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1441system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1442system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1443system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1444system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1445system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1446system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1447system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1448system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1449system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1450system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1451system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1452system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1453system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1454system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1455system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1456system.realview.ethernet.droppedPackets 0 # number of packets dropped 1457system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1458system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1459system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1460system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1461 1462---------- End Simulation Statistics ---------- 1463