stats.txt revision 10753:48a72150f82c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.852832 # Number of seconds simulated 4sim_ticks 2852831758500 # Number of ticks simulated 5final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 111123 # Simulator instruction rate (inst/s) 8host_op_rate 134357 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2834419538 # Simulator tick rate (ticks/s) 10host_mem_usage 554504 # Number of bytes of host memory used 11host_seconds 1006.50 # Real time elapsed on the host 12sim_insts 111845135 # Number of instructions simulated 13sim_ops 135229426 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 585344 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3220679 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6603165 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 170038 # Number of read requests accepted 55system.physmem.writeReqs 165152 # Number of write requests accepted 56system.physmem.readBursts 170038 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 165152 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10876672 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9051328 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10849188 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 10306868 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 23701 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4591 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10711 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10418 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10743 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10617 # Per bank write bursts 70system.physmem.perBankRdBursts::4 13557 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10851 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10986 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10951 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10335 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10516 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10068 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9192 # Per bank write bursts 78system.physmem.perBankRdBursts::12 10325 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10893 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9864 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9921 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8907 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8809 # Per bank write bursts 84system.physmem.perBankWrBursts::2 9307 # Per bank write bursts 85system.physmem.perBankWrBursts::3 9147 # Per bank write bursts 86system.physmem.perBankWrBursts::4 8787 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9076 # Per bank write bursts 88system.physmem.perBankWrBursts::6 9209 # Per bank write bursts 89system.physmem.perBankWrBursts::7 9123 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9054 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9064 # Per bank write bursts 92system.physmem.perBankWrBursts::10 8553 # Per bank write bursts 93system.physmem.perBankWrBursts::11 8266 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8846 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9045 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8063 # Per bank write bursts 97system.physmem.perBankWrBursts::15 8171 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 51 # Number of times write queue was full causing retry 100system.physmem.totGap 2852831352500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 541 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 169483 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 160771 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 163196 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 6460 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1486 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 1656 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5410 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 5965 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6172 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7573 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6474 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6716 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6751 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6513 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 8515 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7300 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6993 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1421 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 1060 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 1325 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 2414 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 2262 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 1874 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 1812 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 2371 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 1817 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 1970 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 1688 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 1644 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 1359 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 1311 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 1040 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 618 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 389 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 373 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 140 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 113 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 157 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 61712 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 322.918330 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 189.336942 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 338.461853 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22238 36.04% 36.04% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14509 23.51% 59.55% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6552 10.62% 70.16% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3615 5.86% 76.02% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2651 4.30% 80.32% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1538 2.49% 82.81% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1136 1.84% 84.65% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1152 1.87% 86.52% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 8321 13.48% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 61712 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 28.886962 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 584.019916 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 5882 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 24.039946 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.374321 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 43.145306 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-31 5549 94.32% 94.32% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-47 83 1.41% 95.73% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-63 21 0.36% 96.09% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-79 19 0.32% 96.41% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::80-95 30 0.51% 96.92% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::96-111 24 0.41% 97.33% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::112-127 22 0.37% 97.71% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::128-143 15 0.25% 97.96% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-159 11 0.19% 98.15% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-175 3 0.05% 98.20% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::176-191 21 0.36% 98.56% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::192-207 13 0.22% 98.78% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::208-223 9 0.15% 98.93% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads 266system.physmem.totQLat 1723441444 # Total ticks spent queuing 267system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 271system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing 282system.physmem.readRowHits 140236 # Number of row buffer hits during reads 283system.physmem.writeRowHits 109426 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes 286system.physmem.avgGap 8511087.30 # Average gap between requests 287system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined 288system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ) 289system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ) 290system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ) 291system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ) 292system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) 293system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ) 294system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ) 295system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ) 296system.physmem_0.averagePower 669.450935 # Core power per rank (mW) 297system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states 298system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states 299system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 300system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states 301system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 302system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ) 303system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ) 304system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ) 305system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ) 306system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) 307system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ) 308system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ) 309system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ) 310system.physmem_1.averagePower 669.358845 # Core power per rank (mW) 311system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states 312system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states 313system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 314system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states 315system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 316system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) 328system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 329system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 330system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 331system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 332system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 333system.cf0.dma_write_txs 631 # Number of DMA write transactions. 334system.cpu.branchPred.lookups 31016169 # Number of BP lookups 335system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted 336system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect 337system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups 338system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits 339system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 340system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage 341system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target. 342system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions. 343system.cpu_clk_domain.clock 500 # Clock period in ticks 344system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 352system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 353system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 354system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 355system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 356system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 357system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 358system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 359system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 360system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 361system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 362system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 363system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 364system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 365system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 368system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 369system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 370system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 371system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 372system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 373system.cpu.dtb.walker.walks 66365 # Table walker walks requested 374system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors 375system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate 376system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate 377system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution 392system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution 393system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution 394system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated 395system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated 396system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated 397system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst 398system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst 400system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst 401system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst 403system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst 404system.cpu.dtb.inst_hits 0 # ITB inst hits 405system.cpu.dtb.inst_misses 0 # ITB inst misses 406system.cpu.dtb.read_hits 24709745 # DTB read hits 407system.cpu.dtb.read_misses 59626 # DTB read misses 408system.cpu.dtb.write_hits 19412201 # DTB write hits 409system.cpu.dtb.write_misses 6739 # DTB write misses 410system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 411system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 412system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 413system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 414system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB 415system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions 416system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch 417system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 418system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions 419system.cpu.dtb.read_accesses 24769371 # DTB read accesses 420system.cpu.dtb.write_accesses 19418940 # DTB write accesses 421system.cpu.dtb.inst_accesses 0 # ITB inst accesses 422system.cpu.dtb.hits 44121946 # DTB hits 423system.cpu.dtb.misses 66365 # DTB misses 424system.cpu.dtb.accesses 44188311 # DTB accesses 425system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 433system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 434system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 435system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 436system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 437system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 438system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 439system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 440system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 441system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 442system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 443system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 444system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 445system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 446system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 448system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 449system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 450system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 451system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 452system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 453system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 454system.cpu.itb.walker.walks 5448 # Table walker walks requested 455system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors 456system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate 457system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate 458system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency 459system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency 460system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency 461system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency 465system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency 466system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency 467system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency 468system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 469system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency 470system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution 471system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution 472system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution 473system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated 474system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated 475system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated 476system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst 478system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst 479system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 480system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst 481system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst 482system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst 483system.cpu.itb.inst_hits 57588649 # ITB inst hits 484system.cpu.itb.inst_misses 5448 # ITB inst misses 485system.cpu.itb.read_hits 0 # DTB read hits 486system.cpu.itb.read_misses 0 # DTB read misses 487system.cpu.itb.write_hits 0 # DTB write hits 488system.cpu.itb.write_misses 0 # DTB write misses 489system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 490system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 491system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 492system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 493system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB 494system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 495system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 496system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 497system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions 498system.cpu.itb.read_accesses 0 # DTB read accesses 499system.cpu.itb.write_accesses 0 # DTB write accesses 500system.cpu.itb.inst_accesses 57594097 # ITB inst accesses 501system.cpu.itb.hits 57588649 # DTB hits 502system.cpu.itb.misses 5448 # DTB misses 503system.cpu.itb.accesses 57594097 # DTB accesses 504system.cpu.numCycles 315565701 # number of cpu cycles simulated 505system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 506system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 507system.cpu.committedInsts 111845135 # Number of instructions committed 508system.cpu.committedOps 135229426 # Number of ops (including micro ops) committed 509system.cpu.discardedOps 7692999 # Number of ops (including micro ops) which were discarded before commit 510system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching 511system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 512system.cpu.cpi 2.821452 # CPI: cycles per instruction 513system.cpu.ipc 0.354427 # IPC: instructions per cycle 514system.cpu.kern.inst.arm 0 # number of arm instructions executed 515system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed 516system.cpu.tickCycles 227544928 # Number of cycles that the object actually ticked 517system.cpu.idleCycles 88020773 # Total number of cycles that the object has spent stopped 518system.cpu.dcache.tags.replacements 842581 # number of replacements 519system.cpu.dcache.tags.tagsinuse 511.947861 # Cycle average of tags in use 520system.cpu.dcache.tags.total_refs 42538360 # Total number of references to valid blocks. 521system.cpu.dcache.tags.sampled_refs 843093 # Sample count of references to valid blocks. 522system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks. 523system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. 524system.cpu.dcache.tags.occ_blocks::cpu.data 511.947861 # Average occupied blocks per requestor 525system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy 526system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy 527system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 528system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 529system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id 530system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 531system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 532system.cpu.dcache.tags.tag_accesses 175914832 # Number of tag accesses 533system.cpu.dcache.tags.data_accesses 175914832 # Number of data accesses 534system.cpu.dcache.ReadReq_hits::cpu.data 23018220 # number of ReadReq hits 535system.cpu.dcache.ReadReq_hits::total 23018220 # number of ReadReq hits 536system.cpu.dcache.WriteReq_hits::cpu.data 18257083 # number of WriteReq hits 537system.cpu.dcache.WriteReq_hits::total 18257083 # number of WriteReq hits 538system.cpu.dcache.SoftPFReq_hits::cpu.data 356514 # number of SoftPFReq hits 539system.cpu.dcache.SoftPFReq_hits::total 356514 # number of SoftPFReq hits 540system.cpu.dcache.LoadLockedReq_hits::cpu.data 443429 # number of LoadLockedReq hits 541system.cpu.dcache.LoadLockedReq_hits::total 443429 # number of LoadLockedReq hits 542system.cpu.dcache.StoreCondReq_hits::cpu.data 460179 # number of StoreCondReq hits 543system.cpu.dcache.StoreCondReq_hits::total 460179 # number of StoreCondReq hits 544system.cpu.dcache.demand_hits::cpu.data 41275303 # number of demand (read+write) hits 545system.cpu.dcache.demand_hits::total 41275303 # number of demand (read+write) hits 546system.cpu.dcache.overall_hits::cpu.data 41631817 # number of overall hits 547system.cpu.dcache.overall_hits::total 41631817 # number of overall hits 548system.cpu.dcache.ReadReq_misses::cpu.data 492255 # number of ReadReq misses 549system.cpu.dcache.ReadReq_misses::total 492255 # number of ReadReq misses 550system.cpu.dcache.WriteReq_misses::cpu.data 547766 # number of WriteReq misses 551system.cpu.dcache.WriteReq_misses::total 547766 # number of WriteReq misses 552system.cpu.dcache.SoftPFReq_misses::cpu.data 169911 # number of SoftPFReq misses 553system.cpu.dcache.SoftPFReq_misses::total 169911 # number of SoftPFReq misses 554system.cpu.dcache.LoadLockedReq_misses::cpu.data 22569 # number of LoadLockedReq misses 555system.cpu.dcache.LoadLockedReq_misses::total 22569 # number of LoadLockedReq misses 556system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 557system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 558system.cpu.dcache.demand_misses::cpu.data 1040021 # number of demand (read+write) misses 559system.cpu.dcache.demand_misses::total 1040021 # number of demand (read+write) misses 560system.cpu.dcache.overall_misses::cpu.data 1209932 # number of overall misses 561system.cpu.dcache.overall_misses::total 1209932 # number of overall misses 562system.cpu.dcache.ReadReq_miss_latency::cpu.data 7281770758 # number of ReadReq miss cycles 563system.cpu.dcache.ReadReq_miss_latency::total 7281770758 # number of ReadReq miss cycles 564system.cpu.dcache.WriteReq_miss_latency::cpu.data 23432647284 # number of WriteReq miss cycles 565system.cpu.dcache.WriteReq_miss_latency::total 23432647284 # number of WriteReq miss cycles 566system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285921000 # number of LoadLockedReq miss cycles 567system.cpu.dcache.LoadLockedReq_miss_latency::total 285921000 # number of LoadLockedReq miss cycles 568system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles 569system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles 570system.cpu.dcache.demand_miss_latency::cpu.data 30714418042 # number of demand (read+write) miss cycles 571system.cpu.dcache.demand_miss_latency::total 30714418042 # number of demand (read+write) miss cycles 572system.cpu.dcache.overall_miss_latency::cpu.data 30714418042 # number of overall miss cycles 573system.cpu.dcache.overall_miss_latency::total 30714418042 # number of overall miss cycles 574system.cpu.dcache.ReadReq_accesses::cpu.data 23510475 # number of ReadReq accesses(hits+misses) 575system.cpu.dcache.ReadReq_accesses::total 23510475 # number of ReadReq accesses(hits+misses) 576system.cpu.dcache.WriteReq_accesses::cpu.data 18804849 # number of WriteReq accesses(hits+misses) 577system.cpu.dcache.WriteReq_accesses::total 18804849 # number of WriteReq accesses(hits+misses) 578system.cpu.dcache.SoftPFReq_accesses::cpu.data 526425 # number of SoftPFReq accesses(hits+misses) 579system.cpu.dcache.SoftPFReq_accesses::total 526425 # number of SoftPFReq accesses(hits+misses) 580system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465998 # number of LoadLockedReq accesses(hits+misses) 581system.cpu.dcache.LoadLockedReq_accesses::total 465998 # number of LoadLockedReq accesses(hits+misses) 582system.cpu.dcache.StoreCondReq_accesses::cpu.data 460181 # number of StoreCondReq accesses(hits+misses) 583system.cpu.dcache.StoreCondReq_accesses::total 460181 # number of StoreCondReq accesses(hits+misses) 584system.cpu.dcache.demand_accesses::cpu.data 42315324 # number of demand (read+write) accesses 585system.cpu.dcache.demand_accesses::total 42315324 # number of demand (read+write) accesses 586system.cpu.dcache.overall_accesses::cpu.data 42841749 # number of overall (read+write) accesses 587system.cpu.dcache.overall_accesses::total 42841749 # number of overall (read+write) accesses 588system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020938 # miss rate for ReadReq accesses 589system.cpu.dcache.ReadReq_miss_rate::total 0.020938 # miss rate for ReadReq accesses 590system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029129 # miss rate for WriteReq accesses 591system.cpu.dcache.WriteReq_miss_rate::total 0.029129 # miss rate for WriteReq accesses 592system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322764 # miss rate for SoftPFReq accesses 593system.cpu.dcache.SoftPFReq_miss_rate::total 0.322764 # miss rate for SoftPFReq accesses 594system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048432 # miss rate for LoadLockedReq accesses 595system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048432 # miss rate for LoadLockedReq accesses 596system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 597system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 598system.cpu.dcache.demand_miss_rate::cpu.data 0.024578 # miss rate for demand accesses 599system.cpu.dcache.demand_miss_rate::total 0.024578 # miss rate for demand accesses 600system.cpu.dcache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses 601system.cpu.dcache.overall_miss_rate::total 0.028242 # miss rate for overall accesses 602system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14792.680131 # average ReadReq miss latency 603system.cpu.dcache.ReadReq_avg_miss_latency::total 14792.680131 # average ReadReq miss latency 604system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42778.572025 # average WriteReq miss latency 605system.cpu.dcache.WriteReq_avg_miss_latency::total 42778.572025 # average WriteReq miss latency 606system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12668.749169 # average LoadLockedReq miss latency 607system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12668.749169 # average LoadLockedReq miss latency 608system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency 609system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency 610system.cpu.dcache.demand_avg_miss_latency::cpu.data 29532.497942 # average overall miss latency 611system.cpu.dcache.demand_avg_miss_latency::total 29532.497942 # average overall miss latency 612system.cpu.dcache.overall_avg_miss_latency::cpu.data 25385.243172 # average overall miss latency 613system.cpu.dcache.overall_avg_miss_latency::total 25385.243172 # average overall miss latency 614system.cpu.dcache.blocked_cycles::no_mshrs 240 # number of cycles access was blocked 615system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 616system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked 617system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 618system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked 619system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 620system.cpu.dcache.fast_writes 0 # number of fast writes performed 621system.cpu.dcache.cache_copies 0 # number of cache copies performed 622system.cpu.dcache.writebacks::writebacks 698329 # number of writebacks 623system.cpu.dcache.writebacks::total 698329 # number of writebacks 624system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75041 # number of ReadReq MSHR hits 625system.cpu.dcache.ReadReq_mshr_hits::total 75041 # number of ReadReq MSHR hits 626system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits 627system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits 628system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14319 # number of LoadLockedReq MSHR hits 629system.cpu.dcache.LoadLockedReq_mshr_hits::total 14319 # number of LoadLockedReq MSHR hits 630system.cpu.dcache.demand_mshr_hits::cpu.data 324082 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 324082 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 324082 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 324082 # number of overall MSHR hits 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417214 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 417214 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298725 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 298725 # number of WriteReq MSHR misses 638system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121762 # number of SoftPFReq MSHR misses 639system.cpu.dcache.SoftPFReq_mshr_misses::total 121762 # number of SoftPFReq MSHR misses 640system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8250 # number of LoadLockedReq MSHR misses 641system.cpu.dcache.LoadLockedReq_mshr_misses::total 8250 # number of LoadLockedReq MSHR misses 642system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 643system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 644system.cpu.dcache.demand_mshr_misses::cpu.data 715939 # number of demand (read+write) MSHR misses 645system.cpu.dcache.demand_mshr_misses::total 715939 # number of demand (read+write) MSHR misses 646system.cpu.dcache.overall_mshr_misses::cpu.data 837701 # number of overall MSHR misses 647system.cpu.dcache.overall_mshr_misses::total 837701 # number of overall MSHR misses 648system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703446143 # number of ReadReq MSHR miss cycles 649system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703446143 # number of ReadReq MSHR miss cycles 650system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12331014162 # number of WriteReq MSHR miss cycles 651system.cpu.dcache.WriteReq_mshr_miss_latency::total 12331014162 # number of WriteReq MSHR miss cycles 652system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562604290 # number of SoftPFReq MSHR miss cycles 653system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562604290 # number of SoftPFReq MSHR miss cycles 654system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106206750 # number of LoadLockedReq MSHR miss cycles 655system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106206750 # number of LoadLockedReq MSHR miss cycles 656system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles 657system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles 658system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18034460305 # number of demand (read+write) MSHR miss cycles 659system.cpu.dcache.demand_mshr_miss_latency::total 18034460305 # number of demand (read+write) MSHR miss cycles 660system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19597064595 # number of overall MSHR miss cycles 661system.cpu.dcache.overall_mshr_miss_latency::total 19597064595 # number of overall MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836567000 # number of ReadReq MSHR uncacheable cycles 663system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836567000 # number of ReadReq MSHR uncacheable cycles 664system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510270500 # number of WriteReq MSHR uncacheable cycles 665system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510270500 # number of WriteReq MSHR uncacheable cycles 666system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346837500 # number of overall MSHR uncacheable cycles 667system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346837500 # number of overall MSHR uncacheable cycles 668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017746 # mshr miss rate for ReadReq accesses 669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017746 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015886 # mshr miss rate for WriteReq accesses 671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015886 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231300 # mshr miss rate for SoftPFReq accesses 673system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231300 # mshr miss rate for SoftPFReq accesses 674system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses 675system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses 676system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 677system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016919 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.016919 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019553 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.019553 # mshr miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.313419 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.313419 # average ReadReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41278.815506 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41278.815506 # average WriteReq mshr miss latency 686system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12833.267276 # average SoftPFReq mshr miss latency 687system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12833.267276 # average SoftPFReq mshr miss latency 688system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12873.545455 # average LoadLockedReq mshr miss latency 689system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12873.545455 # average LoadLockedReq mshr miss latency 690system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency 691system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency 692system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25189.939792 # average overall mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::total 25189.939792 # average overall mshr miss latency 694system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23393.865586 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::total 23393.865586 # average overall mshr miss latency 696system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 697system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 698system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 699system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 700system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 701system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 702system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 703system.cpu.icache.tags.replacements 2897467 # number of replacements 704system.cpu.icache.tags.tagsinuse 511.399907 # Cycle average of tags in use 705system.cpu.icache.tags.total_refs 54681814 # Total number of references to valid blocks. 706system.cpu.icache.tags.sampled_refs 2897979 # Sample count of references to valid blocks. 707system.cpu.icache.tags.avg_refs 18.868948 # Average number of references to valid blocks. 708system.cpu.icache.tags.warmup_cycle 15532087250 # Cycle when the warmup percentage was hit. 709system.cpu.icache.tags.occ_blocks::cpu.inst 511.399907 # Average occupied blocks per requestor 710system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy 711system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy 712system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 714system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 715system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id 716system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 717system.cpu.icache.tags.tag_accesses 60477795 # Number of tag accesses 718system.cpu.icache.tags.data_accesses 60477795 # Number of data accesses 719system.cpu.icache.ReadReq_hits::cpu.inst 54681814 # number of ReadReq hits 720system.cpu.icache.ReadReq_hits::total 54681814 # number of ReadReq hits 721system.cpu.icache.demand_hits::cpu.inst 54681814 # number of demand (read+write) hits 722system.cpu.icache.demand_hits::total 54681814 # number of demand (read+write) hits 723system.cpu.icache.overall_hits::cpu.inst 54681814 # number of overall hits 724system.cpu.icache.overall_hits::total 54681814 # number of overall hits 725system.cpu.icache.ReadReq_misses::cpu.inst 2897991 # number of ReadReq misses 726system.cpu.icache.ReadReq_misses::total 2897991 # number of ReadReq misses 727system.cpu.icache.demand_misses::cpu.inst 2897991 # number of demand (read+write) misses 728system.cpu.icache.demand_misses::total 2897991 # number of demand (read+write) misses 729system.cpu.icache.overall_misses::cpu.inst 2897991 # number of overall misses 730system.cpu.icache.overall_misses::total 2897991 # number of overall misses 731system.cpu.icache.ReadReq_miss_latency::cpu.inst 39294300362 # number of ReadReq miss cycles 732system.cpu.icache.ReadReq_miss_latency::total 39294300362 # number of ReadReq miss cycles 733system.cpu.icache.demand_miss_latency::cpu.inst 39294300362 # number of demand (read+write) miss cycles 734system.cpu.icache.demand_miss_latency::total 39294300362 # number of demand (read+write) miss cycles 735system.cpu.icache.overall_miss_latency::cpu.inst 39294300362 # number of overall miss cycles 736system.cpu.icache.overall_miss_latency::total 39294300362 # number of overall miss cycles 737system.cpu.icache.ReadReq_accesses::cpu.inst 57579805 # number of ReadReq accesses(hits+misses) 738system.cpu.icache.ReadReq_accesses::total 57579805 # number of ReadReq accesses(hits+misses) 739system.cpu.icache.demand_accesses::cpu.inst 57579805 # number of demand (read+write) accesses 740system.cpu.icache.demand_accesses::total 57579805 # number of demand (read+write) accesses 741system.cpu.icache.overall_accesses::cpu.inst 57579805 # number of overall (read+write) accesses 742system.cpu.icache.overall_accesses::total 57579805 # number of overall (read+write) accesses 743system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050330 # miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_miss_rate::total 0.050330 # miss rate for ReadReq accesses 745system.cpu.icache.demand_miss_rate::cpu.inst 0.050330 # miss rate for demand accesses 746system.cpu.icache.demand_miss_rate::total 0.050330 # miss rate for demand accesses 747system.cpu.icache.overall_miss_rate::cpu.inst 0.050330 # miss rate for overall accesses 748system.cpu.icache.overall_miss_rate::total 0.050330 # miss rate for overall accesses 749system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.151965 # average ReadReq miss latency 750system.cpu.icache.ReadReq_avg_miss_latency::total 13559.151965 # average ReadReq miss latency 751system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency 752system.cpu.icache.demand_avg_miss_latency::total 13559.151965 # average overall miss latency 753system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency 754system.cpu.icache.overall_avg_miss_latency::total 13559.151965 # average overall miss latency 755system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 756system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 760system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.icache.fast_writes 0 # number of fast writes performed 762system.cpu.icache.cache_copies 0 # number of cache copies performed 763system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897991 # number of ReadReq MSHR misses 764system.cpu.icache.ReadReq_mshr_misses::total 2897991 # number of ReadReq MSHR misses 765system.cpu.icache.demand_mshr_misses::cpu.inst 2897991 # number of demand (read+write) MSHR misses 766system.cpu.icache.demand_mshr_misses::total 2897991 # number of demand (read+write) MSHR misses 767system.cpu.icache.overall_mshr_misses::cpu.inst 2897991 # number of overall MSHR misses 768system.cpu.icache.overall_mshr_misses::total 2897991 # number of overall MSHR misses 769system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34937740638 # number of ReadReq MSHR miss cycles 770system.cpu.icache.ReadReq_mshr_miss_latency::total 34937740638 # number of ReadReq MSHR miss cycles 771system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34937740638 # number of demand (read+write) MSHR miss cycles 772system.cpu.icache.demand_mshr_miss_latency::total 34937740638 # number of demand (read+write) MSHR miss cycles 773system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34937740638 # number of overall MSHR miss cycles 774system.cpu.icache.overall_mshr_miss_latency::total 34937740638 # number of overall MSHR miss cycles 775system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles 776system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles 777system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles 778system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles 779system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for ReadReq accesses 780system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050330 # mshr miss rate for ReadReq accesses 781system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for demand accesses 782system.cpu.icache.demand_mshr_miss_rate::total 0.050330 # mshr miss rate for demand accesses 783system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for overall accesses 784system.cpu.icache.overall_mshr_miss_rate::total 0.050330 # mshr miss rate for overall accesses 785system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.848565 # average ReadReq mshr miss latency 786system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.848565 # average ReadReq mshr miss latency 787system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency 788system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency 789system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency 790system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency 791system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 792system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 793system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 794system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 795system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 796system.cpu.l2cache.tags.replacements 96766 # number of replacements 797system.cpu.l2cache.tags.tagsinuse 65065.875064 # Cycle average of tags in use 798system.cpu.l2cache.tags.total_refs 4045925 # Total number of references to valid blocks. 799system.cpu.l2cache.tags.sampled_refs 162028 # Sample count of references to valid blocks. 800system.cpu.l2cache.tags.avg_refs 24.970530 # Average number of references to valid blocks. 801system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 802system.cpu.l2cache.tags.occ_blocks::writebacks 47500.722639 # Average occupied blocks per requestor 803system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.826977 # Average occupied blocks per requestor 804system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor 805system.cpu.l2cache.tags.occ_blocks::cpu.inst 12189.076144 # Average occupied blocks per requestor 806system.cpu.l2cache.tags.occ_blocks::cpu.data 5308.248921 # Average occupied blocks per requestor 807system.cpu.l2cache.tags.occ_percent::writebacks 0.724804 # Average percentage of cache occupancy 808system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001035 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::cpu.inst 0.185991 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::cpu.data 0.080997 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::total 0.992826 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id 814system.cpu.l2cache.tags.occ_task_id_blocks::1024 65218 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2302 # Occupied blocks per task id 819system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6937 # Occupied blocks per task id 820system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55861 # Occupied blocks per task id 821system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 822system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995148 # Percentage of cache occupancy per task id 823system.cpu.l2cache.tags.tag_accesses 36601578 # Number of tag accesses 824system.cpu.l2cache.tags.data_accesses 36601578 # Number of data accesses 825system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70583 # number of ReadReq hits 826system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4448 # number of ReadReq hits 827system.cpu.l2cache.ReadReq_hits::cpu.inst 2875013 # number of ReadReq hits 828system.cpu.l2cache.ReadReq_hits::cpu.data 532926 # number of ReadReq hits 829system.cpu.l2cache.ReadReq_hits::total 3482970 # number of ReadReq hits 830system.cpu.l2cache.Writeback_hits::writebacks 698329 # number of Writeback hits 831system.cpu.l2cache.Writeback_hits::total 698329 # number of Writeback hits 832system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits 833system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits 834system.cpu.l2cache.ReadExReq_hits::cpu.data 164703 # number of ReadExReq hits 835system.cpu.l2cache.ReadExReq_hits::total 164703 # number of ReadExReq hits 836system.cpu.l2cache.demand_hits::cpu.dtb.walker 70583 # number of demand (read+write) hits 837system.cpu.l2cache.demand_hits::cpu.itb.walker 4448 # number of demand (read+write) hits 838system.cpu.l2cache.demand_hits::cpu.inst 2875013 # number of demand (read+write) hits 839system.cpu.l2cache.demand_hits::cpu.data 697629 # number of demand (read+write) hits 840system.cpu.l2cache.demand_hits::total 3647673 # number of demand (read+write) hits 841system.cpu.l2cache.overall_hits::cpu.dtb.walker 70583 # number of overall hits 842system.cpu.l2cache.overall_hits::cpu.itb.walker 4448 # number of overall hits 843system.cpu.l2cache.overall_hits::cpu.inst 2875013 # number of overall hits 844system.cpu.l2cache.overall_hits::cpu.data 697629 # number of overall hits 845system.cpu.l2cache.overall_hits::total 3647673 # number of overall hits 846system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 121 # number of ReadReq misses 847system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 848system.cpu.l2cache.ReadReq_misses::cpu.inst 22948 # number of ReadReq misses 849system.cpu.l2cache.ReadReq_misses::cpu.data 14295 # number of ReadReq misses 850system.cpu.l2cache.ReadReq_misses::total 37365 # number of ReadReq misses 851system.cpu.l2cache.UpgradeReq_misses::cpu.data 2778 # number of UpgradeReq misses 852system.cpu.l2cache.UpgradeReq_misses::total 2778 # number of UpgradeReq misses 853system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 854system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 855system.cpu.l2cache.ReadExReq_misses::cpu.data 131196 # number of ReadExReq misses 856system.cpu.l2cache.ReadExReq_misses::total 131196 # number of ReadExReq misses 857system.cpu.l2cache.demand_misses::cpu.dtb.walker 121 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 859system.cpu.l2cache.demand_misses::cpu.inst 22948 # number of demand (read+write) misses 860system.cpu.l2cache.demand_misses::cpu.data 145491 # number of demand (read+write) misses 861system.cpu.l2cache.demand_misses::total 168561 # number of demand (read+write) misses 862system.cpu.l2cache.overall_misses::cpu.dtb.walker 121 # number of overall misses 863system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 864system.cpu.l2cache.overall_misses::cpu.inst 22948 # number of overall misses 865system.cpu.l2cache.overall_misses::cpu.data 145491 # number of overall misses 866system.cpu.l2cache.overall_misses::total 168561 # number of overall misses 867system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10389500 # number of ReadReq miss cycles 868system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles 869system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1838002000 # number of ReadReq miss cycles 870system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1203040290 # number of ReadReq miss cycles 871system.cpu.l2cache.ReadReq_miss_latency::total 3051514290 # number of ReadReq miss cycles 872system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1092965 # number of UpgradeReq miss cycles 873system.cpu.l2cache.UpgradeReq_miss_latency::total 1092965 # number of UpgradeReq miss cycles 874system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 875system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 876system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10205321187 # number of ReadExReq miss cycles 877system.cpu.l2cache.ReadExReq_miss_latency::total 10205321187 # number of ReadExReq miss cycles 878system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10389500 # number of demand (read+write) miss cycles 879system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles 880system.cpu.l2cache.demand_miss_latency::cpu.inst 1838002000 # number of demand (read+write) miss cycles 881system.cpu.l2cache.demand_miss_latency::cpu.data 11408361477 # number of demand (read+write) miss cycles 882system.cpu.l2cache.demand_miss_latency::total 13256835477 # number of demand (read+write) miss cycles 883system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10389500 # number of overall miss cycles 884system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles 885system.cpu.l2cache.overall_miss_latency::cpu.inst 1838002000 # number of overall miss cycles 886system.cpu.l2cache.overall_miss_latency::cpu.data 11408361477 # number of overall miss cycles 887system.cpu.l2cache.overall_miss_latency::total 13256835477 # number of overall miss cycles 888system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70704 # number of ReadReq accesses(hits+misses) 889system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4449 # number of ReadReq accesses(hits+misses) 890system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897961 # number of ReadReq accesses(hits+misses) 891system.cpu.l2cache.ReadReq_accesses::cpu.data 547221 # number of ReadReq accesses(hits+misses) 892system.cpu.l2cache.ReadReq_accesses::total 3520335 # number of ReadReq accesses(hits+misses) 893system.cpu.l2cache.Writeback_accesses::writebacks 698329 # number of Writeback accesses(hits+misses) 894system.cpu.l2cache.Writeback_accesses::total 698329 # number of Writeback accesses(hits+misses) 895system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2831 # number of UpgradeReq accesses(hits+misses) 896system.cpu.l2cache.UpgradeReq_accesses::total 2831 # number of UpgradeReq accesses(hits+misses) 897system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 898system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 899system.cpu.l2cache.ReadExReq_accesses::cpu.data 295899 # number of ReadExReq accesses(hits+misses) 900system.cpu.l2cache.ReadExReq_accesses::total 295899 # number of ReadExReq accesses(hits+misses) 901system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70704 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::cpu.itb.walker 4449 # number of demand (read+write) accesses 903system.cpu.l2cache.demand_accesses::cpu.inst 2897961 # number of demand (read+write) accesses 904system.cpu.l2cache.demand_accesses::cpu.data 843120 # number of demand (read+write) accesses 905system.cpu.l2cache.demand_accesses::total 3816234 # number of demand (read+write) accesses 906system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70704 # number of overall (read+write) accesses 907system.cpu.l2cache.overall_accesses::cpu.itb.walker 4449 # number of overall (read+write) accesses 908system.cpu.l2cache.overall_accesses::cpu.inst 2897961 # number of overall (read+write) accesses 909system.cpu.l2cache.overall_accesses::cpu.data 843120 # number of overall (read+write) accesses 910system.cpu.l2cache.overall_accesses::total 3816234 # number of overall (read+write) accesses 911system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001711 # miss rate for ReadReq accesses 912system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000225 # miss rate for ReadReq accesses 913system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007919 # miss rate for ReadReq accesses 914system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026123 # miss rate for ReadReq accesses 915system.cpu.l2cache.ReadReq_miss_rate::total 0.010614 # miss rate for ReadReq accesses 916system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981279 # miss rate for UpgradeReq accesses 917system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981279 # miss rate for UpgradeReq accesses 918system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 919system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 920system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443381 # miss rate for ReadExReq accesses 921system.cpu.l2cache.ReadExReq_miss_rate::total 0.443381 # miss rate for ReadExReq accesses 922system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001711 # miss rate for demand accesses 923system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000225 # miss rate for demand accesses 924system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007919 # miss rate for demand accesses 925system.cpu.l2cache.demand_miss_rate::cpu.data 0.172563 # miss rate for demand accesses 926system.cpu.l2cache.demand_miss_rate::total 0.044169 # miss rate for demand accesses 927system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001711 # miss rate for overall accesses 928system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000225 # miss rate for overall accesses 929system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007919 # miss rate for overall accesses 930system.cpu.l2cache.overall_miss_rate::cpu.data 0.172563 # miss rate for overall accesses 931system.cpu.l2cache.overall_miss_rate::total 0.044169 # miss rate for overall accesses 932system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85863.636364 # average ReadReq miss latency 933system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency 934system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80094.213003 # average ReadReq miss latency 935system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84158.117524 # average ReadReq miss latency 936system.cpu.l2cache.ReadReq_avg_miss_latency::total 81667.718185 # average ReadReq miss latency 937system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 393.435925 # average UpgradeReq miss latency 938system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 393.435925 # average UpgradeReq miss latency 939system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency 940system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency 941system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77786.831817 # average ReadExReq miss latency 942system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77786.831817 # average ReadExReq miss latency 943system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency 944system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency 945system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency 946system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency 947system.cpu.l2cache.demand_avg_miss_latency::total 78647.109812 # average overall miss latency 948system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency 949system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency 950system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency 951system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency 952system.cpu.l2cache.overall_avg_miss_latency::total 78647.109812 # average overall miss latency 953system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 954system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 955system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 956system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 957system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 958system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 959system.cpu.l2cache.fast_writes 0 # number of fast writes performed 960system.cpu.l2cache.cache_copies 0 # number of cache copies performed 961system.cpu.l2cache.writebacks::writebacks 88357 # number of writebacks 962system.cpu.l2cache.writebacks::total 88357 # number of writebacks 963system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits 964system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 143 # number of ReadReq MSHR hits 965system.cpu.l2cache.ReadReq_mshr_hits::total 161 # number of ReadReq MSHR hits 966system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits 967system.cpu.l2cache.demand_mshr_hits::cpu.data 143 # number of demand (read+write) MSHR hits 968system.cpu.l2cache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits 969system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits 970system.cpu.l2cache.overall_mshr_hits::cpu.data 143 # number of overall MSHR hits 971system.cpu.l2cache.overall_mshr_hits::total 161 # number of overall MSHR hits 972system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 121 # number of ReadReq MSHR misses 973system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 974system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22930 # number of ReadReq MSHR misses 975system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14152 # number of ReadReq MSHR misses 976system.cpu.l2cache.ReadReq_mshr_misses::total 37204 # number of ReadReq MSHR misses 977system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2778 # number of UpgradeReq MSHR misses 978system.cpu.l2cache.UpgradeReq_mshr_misses::total 2778 # number of UpgradeReq MSHR misses 979system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # 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number of overall MSHR misses 991system.cpu.l2cache.overall_mshr_misses::cpu.data 145348 # number of overall MSHR misses 992system.cpu.l2cache.overall_mshr_misses::total 168400 # number of overall MSHR misses 993system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8873000 # number of ReadReq MSHR miss cycles 994system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles 995system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1549821750 # number of ReadReq MSHR miss cycles 996system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1015754460 # number of ReadReq MSHR miss cycles 997system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574519210 # number of ReadReq MSHR miss cycles 998system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49350278 # number of UpgradeReq MSHR miss cycles 999system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49350278 # number of UpgradeReq MSHR miss cycles 1000system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # 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number of overall MSHR miss cycles 1010system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles 1011system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1549821750 # number of overall MSHR miss cycles 1012system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9579292273 # number of overall MSHR miss cycles 1013system.cpu.l2cache.overall_mshr_miss_latency::total 11138057023 # number of overall MSHR miss cycles 1014system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400289500 # number of ReadReq MSHR uncacheable cycles 1016system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592019250 # number of ReadReq MSHR uncacheable cycles 1017system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151564500 # number of WriteReq MSHR uncacheable cycles 1018system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151564500 # number of WriteReq MSHR uncacheable cycles 1019system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles 1020system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551854000 # number of overall MSHR uncacheable cycles 1021system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743583750 # number of overall MSHR uncacheable cycles 1022system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for ReadReq accesses 1023system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for ReadReq accesses 1024system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadReq accesses 1025system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025862 # mshr miss rate for ReadReq accesses 1026system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010568 # mshr miss rate for ReadReq accesses 1027system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for UpgradeReq accesses 1028system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981279 # mshr miss rate for UpgradeReq accesses 1029system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1030system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1031system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443381 # mshr miss rate for ReadExReq accesses 1032system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443381 # mshr miss rate for ReadExReq accesses 1033system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for demand accesses 1034system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for demand accesses 1035system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for demand accesses 1036system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for demand accesses 1037system.cpu.l2cache.demand_mshr_miss_rate::total 0.044127 # mshr miss rate for demand accesses 1038system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for overall accesses 1039system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for overall accesses 1040system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for overall accesses 1041system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for overall accesses 1042system.cpu.l2cache.overall_mshr_miss_rate::total 0.044127 # mshr miss rate for overall accesses 1043system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average ReadReq mshr miss latency 1044system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency 1045system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67589.260794 # average ReadReq mshr miss latency 1046system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71774.622668 # average ReadReq mshr miss latency 1047system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69200.064778 # average ReadReq mshr miss latency 1048system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17764.678906 # average UpgradeReq mshr miss latency 1049system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17764.678906 # average UpgradeReq mshr miss latency 1050system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency 1051system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency 1052system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65272.857503 # average ReadExReq mshr miss latency 1053system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65272.857503 # average ReadExReq mshr miss latency 1054system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency 1055system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency 1056system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency 1057system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency 1058system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency 1059system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency 1060system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency 1061system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency 1062system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency 1063system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency 1064system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1065system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1066system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1067system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1068system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1069system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1070system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1071system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1072system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1073system.cpu.toL2Bus.trans_dist::ReadReq 3579472 # Transaction distribution 1074system.cpu.toL2Bus.trans_dist::ReadResp 3579378 # Transaction distribution 1075system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution 1076system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution 1077system.cpu.toL2Bus.trans_dist::Writeback 698329 # Transaction distribution 1078system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::UpgradeReq 2831 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::UpgradeResp 2833 # Transaction distribution 1082system.cpu.toL2Bus.trans_dist::ReadExReq 295899 # Transaction distribution 1083system.cpu.toL2Bus.trans_dist::ReadExResp 295899 # Transaction distribution 1084system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802295 # Packet count per connected master and slave (bytes) 1085system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2507794 # Packet count per connected master and slave (bytes) 1086system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15026 # Packet count per connected master and slave (bytes) 1087system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159855 # Packet count per connected master and slave (bytes) 1088system.cpu.toL2Bus.pkt_count::total 8484970 # Packet count per connected master and slave (bytes) 1089system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185672448 # Cumulative packet size per connected master and slave (bytes) 1090system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98844821 # Cumulative packet size per connected master and slave (bytes) 1091system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17796 # Cumulative packet size per connected master and slave (bytes) 1092system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 282816 # Cumulative packet size per connected master and slave (bytes) 1093system.cpu.toL2Bus.pkt_size::total 284817881 # Cumulative packet size per connected master and slave (bytes) 1094system.cpu.toL2Bus.snoops 61238 # Total snoops (count) 1095system.cpu.toL2Bus.snoop_fanout::samples 4578493 # Request fanout histogram 1096system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram 1097system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram 1098system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1099system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1100system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::3 4542001 99.20% 99.20% # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::4 36492 0.80% 100.00% # Request fanout histogram 1104system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1106system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::total 4578493 # Request fanout histogram 1108system.cpu.toL2Bus.reqLayer0.occupancy 3014061750 # Layer occupancy (ticks) 1109system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1110system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) 1111system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1112system.cpu.toL2Bus.respLayer0.occupancy 4357263112 # Layer occupancy (ticks) 1113system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1114system.cpu.toL2Bus.respLayer1.occupancy 1342100655 # Layer occupancy (ticks) 1115system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1116system.cpu.toL2Bus.respLayer2.occupancy 10577000 # Layer occupancy (ticks) 1117system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1118system.cpu.toL2Bus.respLayer3.occupancy 89155750 # Layer occupancy (ticks) 1119system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1120system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1121system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1122system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1123system.iobus.trans_dist::WriteResp 22790 # Transaction distribution 1124system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1125system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1133system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1134system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1135system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1136system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1137system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1138system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1139system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1140system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1141system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1142system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1143system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1144system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1145system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1146system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1147system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1148system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1149system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) 1150system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1158system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1159system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1160system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1161system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1163system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1164system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1165system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1166system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1167system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1168system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1169system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1170system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1171system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1172system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1173system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1174system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) 1175system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) 1176system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1177system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1178system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1179system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1180system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1181system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1182system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1183system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1184system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1185system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1186system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1187system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1188system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1189system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1190system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1191system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1192system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1193system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1194system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1195system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1196system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1197system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1198system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1199system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1200system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1201system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1202system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1203system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1204system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1205system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1206system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1207system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1208system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1209system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1210system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1211system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1212system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1213system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1214system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1215system.iobus.reqLayer27.occupancy 198870981 # Layer occupancy (ticks) 1216system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1217system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1218system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1219system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1220system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1221system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks) 1222system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1223system.iocache.tags.replacements 36424 # number of replacements 1224system.iocache.tags.tagsinuse 1.031296 # Cycle average of tags in use 1225system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1226system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1227system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1228system.iocache.tags.warmup_cycle 270543128000 # Cycle when the warmup percentage was hit. 1229system.iocache.tags.occ_blocks::realview.ide 1.031296 # Average occupied blocks per requestor 1230system.iocache.tags.occ_percent::realview.ide 0.064456 # Average percentage of cache occupancy 1231system.iocache.tags.occ_percent::total 0.064456 # Average percentage of cache occupancy 1232system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1233system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1234system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1235system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1236system.iocache.tags.data_accesses 328122 # Number of data accesses 1237system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1238system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1239system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1240system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 1241system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1242system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1243system.iocache.overall_misses::realview.ide 234 # number of overall misses 1244system.iocache.overall_misses::total 234 # number of overall misses 1245system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles 1246system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles 1247system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6646548599 # number of WriteInvalidateReq miss cycles 1248system.iocache.WriteInvalidateReq_miss_latency::total 6646548599 # number of WriteInvalidateReq miss cycles 1249system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles 1250system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles 1251system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles 1252system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles 1253system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1254system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1255system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1256system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1257system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1258system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1259system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1260system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1261system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1262system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1263system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1264system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1265system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1266system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1267system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1268system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1269system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency 1270system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency 1271system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183484.667596 # average WriteInvalidateReq miss latency 1272system.iocache.WriteInvalidateReq_avg_miss_latency::total 183484.667596 # average WriteInvalidateReq miss latency 1273system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency 1274system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency 1275system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency 1276system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency 1277system.iocache.blocked_cycles::no_mshrs 22676 # number of cycles access was blocked 1278system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1279system.iocache.blocked::no_mshrs 3466 # number of cycles access was blocked 1280system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1281system.iocache.avg_blocked_cycles::no_mshrs 6.542412 # average number of cycles each access was blocked 1282system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1283system.iocache.fast_writes 0 # number of fast writes performed 1284system.iocache.cache_copies 0 # number of cache copies performed 1285system.iocache.writebacks::writebacks 36190 # number of writebacks 1286system.iocache.writebacks::total 36190 # number of writebacks 1287system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1288system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1289system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1290system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 1291system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1292system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1293system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1294system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1295system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles 1296system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles 1297system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4762888611 # number of WriteInvalidateReq MSHR miss cycles 1298system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4762888611 # number of WriteInvalidateReq MSHR miss cycles 1299system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles 1300system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles 1301system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles 1302system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles 1303system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1304system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1305system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1306system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1307system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1308system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1309system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1310system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1311system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency 1312system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency 1313system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131484.336655 # average WriteInvalidateReq mshr miss latency 1314system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131484.336655 # average WriteInvalidateReq mshr miss latency 1315system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency 1316system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency 1317system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency 1318system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency 1319system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1320system.membus.trans_dist::ReadReq 71736 # Transaction distribution 1321system.membus.trans_dist::ReadResp 71736 # Transaction distribution 1322system.membus.trans_dist::WriteReq 27583 # Transaction distribution 1323system.membus.trans_dist::WriteResp 27583 # Transaction distribution 1324system.membus.trans_dist::Writeback 124547 # Transaction distribution 1325system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1326system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1327system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution 1328system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1329system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution 1330system.membus.trans_dist::ReadExReq 129383 # Transaction distribution 1331system.membus.trans_dist::ReadExResp 129383 # Transaction distribution 1332system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1333system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1334system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) 1335system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes) 1336system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes) 1337system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) 1338system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) 1339system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes) 1340system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1341system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 1342system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) 1343system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes) 1344system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes) 1345system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1346system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 1347system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes) 1348system.membus.snoops 505 # Total snoops (count) 1349system.membus.snoop_fanout::samples 332236 # Request fanout histogram 1350system.membus.snoop_fanout::mean 1 # Request fanout histogram 1351system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1352system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1353system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1354system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram 1355system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1356system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1357system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1358system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1359system.membus.snoop_fanout::total 332236 # Request fanout histogram 1360system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks) 1361system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1362system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) 1363system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1364system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks) 1365system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1366system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks) 1367system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1368system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks) 1369system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1370system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks) 1371system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1372system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1373system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1374system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1375system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1376system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1377system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1378system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1379system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1380system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1381system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1382system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1383system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1384system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1385system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1386system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1387system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1388system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1389system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1390system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1391system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1392system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1393system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1394system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1395system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1396system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1397system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1398system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1399system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1400system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1401system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1402system.realview.ethernet.droppedPackets 0 # number of packets dropped 1403 1404---------- End Simulation Statistics ---------- 1405