stats.txt revision 10636:9ac724889705
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.852858 # Number of seconds simulated 4sim_ticks 2852857543000 # Number of ticks simulated 5final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 109881 # Simulator instruction rate (inst/s) 8host_op_rate 132861 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2793727953 # Simulator tick rate (ticks/s) 10host_mem_usage 608784 # Number of bytes of host memory used 11host_seconds 1021.17 # Real time elapsed on the host 12sim_insts 112207125 # Number of instructions simulated 13sim_ops 135672670 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1662912 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9175012 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 25983 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 143879 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 582893 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3216078 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 582893 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3222220 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 170006 # Number of read requests accepted 55system.physmem.writeReqs 165023 # Number of write requests accepted 56system.physmem.readBursts 170006 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 165023 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10873728 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue 60system.physmem.bytesWritten 10175104 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10847140 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 10298612 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 6006 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10656 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10651 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10704 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10614 # Per bank write bursts 70system.physmem.perBankRdBursts::4 13356 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10666 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11042 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10972 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10208 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10672 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10509 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9657 # Per bank write bursts 78system.physmem.perBankRdBursts::12 10109 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10747 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9757 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9582 # Per bank write bursts 82system.physmem.perBankWrBursts::0 10072 # Per bank write bursts 83system.physmem.perBankWrBursts::1 10092 # Per bank write bursts 84system.physmem.perBankWrBursts::2 10491 # Per bank write bursts 85system.physmem.perBankWrBursts::3 10304 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9538 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9899 # Per bank write bursts 88system.physmem.perBankWrBursts::6 10133 # Per bank write bursts 89system.physmem.perBankWrBursts::7 10134 # Per bank write bursts 90system.physmem.perBankWrBursts::8 10091 # Per bank write bursts 91system.physmem.perBankWrBursts::9 10380 # Per bank write bursts 92system.physmem.perBankWrBursts::10 10169 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9697 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9799 # Per bank write bursts 95system.physmem.perBankWrBursts::13 10201 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9040 # Per bank write bursts 97system.physmem.perBankWrBursts::15 8946 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2852857119000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 541 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 169451 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 160642 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 163533 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 6320 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3913 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7826 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 8953 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 9279 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 10066 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 10452 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 11206 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 11037 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11618 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10744 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 10251 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9284 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7662 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7362 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7187 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7081 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 369 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 240 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 56 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 62962 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 334.308059 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 193.690406 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 348.894179 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22562 35.83% 35.83% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14454 22.96% 58.79% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6551 10.40% 69.20% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3518 5.59% 74.78% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2542 4.04% 78.82% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1533 2.43% 81.26% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1128 1.79% 83.05% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1127 1.79% 84.84% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 9547 15.16% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 62962 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.554603 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 562.154464 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 23.914862 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.938842 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 22.611148 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5537 83.29% 83.29% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 45 0.68% 83.97% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 19 0.29% 84.25% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 242 3.64% 87.89% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 123 1.85% 89.74% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 53 0.80% 90.54% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 26 0.39% 90.93% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 33 0.50% 91.43% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 114 1.71% 93.14% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 19 0.29% 93.43% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 14 0.21% 93.64% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 11 0.17% 93.80% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 33 0.50% 94.30% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 20 0.30% 94.60% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 10 0.15% 94.75% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 22 0.33% 95.08% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 16 0.24% 96.22% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 7 0.11% 96.33% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 13 0.20% 96.53% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 84 1.26% 97.79% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 5 0.08% 97.86% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 9 0.14% 98.00% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 9 0.14% 98.13% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 15 0.23% 98.36% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::116-119 3 0.05% 98.41% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 10 0.15% 98.56% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::124-127 3 0.05% 98.60% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 37 0.56% 99.16% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::132-135 8 0.12% 99.28% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::140-143 4 0.06% 99.34% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::144-147 9 0.14% 99.47% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::156-159 4 0.06% 99.61% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::160-163 2 0.03% 99.64% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::164-167 4 0.06% 99.70% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::168-171 5 0.08% 99.77% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::172-175 2 0.03% 99.80% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::176-179 1 0.02% 99.82% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::180-183 1 0.02% 99.83% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::184-187 2 0.03% 99.86% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::192-195 1 0.02% 99.89% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::196-199 1 0.02% 99.91% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::200-203 4 0.06% 99.97% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::224-227 1 0.02% 99.98% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::232-235 1 0.02% 100.00% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads 284system.physmem.totQLat 1659710000 # Total ticks spent queuing 285system.physmem.totMemAccLat 4845372500 # Total ticks spent from burst creation until serviced by the DRAM 286system.physmem.totBusLat 849510000 # Total ticks spent in databus transfers 287system.physmem.avgQLat 9768.63 # Average queueing delay per DRAM burst 288system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 289system.physmem.avgMemAccLat 28518.63 # Average memory access latency per DRAM burst 290system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 291system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s 292system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 293system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s 294system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 295system.physmem.busUtil 0.06 # Data bus utilization in percentage 296system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 297system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 298system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 299system.physmem.avgWrQLen 27.33 # Average write queue length when enqueuing 300system.physmem.readRowHits 140084 # Number of row buffer hits during reads 301system.physmem.writeRowHits 125841 # Number of row buffer hits during writes 302system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads 303system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes 304system.physmem.avgGap 8515254.26 # Average gap between requests 305system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined 306system.physmem_0.actEnergy 246909600 # Energy for activate commands per rank (pJ) 307system.physmem_0.preEnergy 134722500 # Energy for precharge commands per rank (pJ) 308system.physmem_0.readEnergy 691555800 # Energy for read commands per rank (pJ) 309system.physmem_0.writeEnergy 522696240 # Energy for write commands per rank (pJ) 310system.physmem_0.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) 311system.physmem_0.actBackEnergy 83503223595 # Energy for active background per rank (pJ) 312system.physmem_0.preBackEnergy 1638462219000 # Energy for precharge background per rank (pJ) 313system.physmem_0.totalEnergy 1909895676495 # Total energy per rank (pJ) 314system.physmem_0.averagePower 669.469106 # Core power per rank (mW) 315system.physmem_0.memoryStateTime::IDLE 2725585905000 # Time in different power states 316system.physmem_0.memoryStateTime::REF 95262960000 # Time in different power states 317system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 318system.physmem_0.memoryStateTime::ACT 32002250000 # Time in different power states 319system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 320system.physmem_1.actEnergy 229083120 # Energy for activate commands per rank (pJ) 321system.physmem_1.preEnergy 124995750 # Energy for precharge commands per rank (pJ) 322system.physmem_1.readEnergy 633664200 # Energy for read commands per rank (pJ) 323system.physmem_1.writeEnergy 507533040 # Energy for write commands per rank (pJ) 324system.physmem_1.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) 325system.physmem_1.actBackEnergy 82044200295 # Energy for active background per rank (pJ) 326system.physmem_1.preBackEnergy 1639742072250 # Energy for precharge background per rank (pJ) 327system.physmem_1.totalEnergy 1909615898415 # Total energy per rank (pJ) 328system.physmem_1.averagePower 669.371033 # Core power per rank (mW) 329system.physmem_1.memoryStateTime::IDLE 2727729306000 # Time in different power states 330system.physmem_1.memoryStateTime::REF 95262960000 # Time in different power states 331system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 332system.physmem_1.memoryStateTime::ACT 29860939000 # Time in different power states 333system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 334system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory 335system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 336system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory 337system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 338system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 339system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 340system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) 346system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 347system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 348system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 349system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 350system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 351system.cf0.dma_write_txs 631 # Number of DMA write transactions. 352system.cpu.branchPred.lookups 31058702 # Number of BP lookups 353system.cpu.branchPred.condPredicted 16880390 # Number of conditional branches predicted 354system.cpu.branchPred.condIncorrect 2530392 # Number of conditional branches incorrect 355system.cpu.branchPred.BTBLookups 18557624 # Number of BTB lookups 356system.cpu.branchPred.BTBHits 13376459 # Number of BTB hits 357system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 358system.cpu.branchPred.BTBHitPct 72.080666 # BTB Hit Percentage 359system.cpu.branchPred.usedRAS 7810096 # Number of times the RAS was used to get a target. 360system.cpu.branchPred.RASInCorrect 1523796 # Number of incorrect RAS predictions. 361system.cpu_clk_domain.clock 500 # Clock period in ticks 362system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 370system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu.dtb.walker.walks 66845 # Table walker walks requested 392system.cpu.dtb.walker.walksShort 66845 # Table walker walks initiated with short descriptors 393system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43967 # Level at which table walker walks with short descriptors terminate 394system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22878 # Level at which table walker walks with short descriptors terminate 395system.cpu.dtb.walker.walkWaitTime::samples 66845 # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::0 66845 100.00% 100.00% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::total 66845 # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkCompletionTime::samples 7791 # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299 # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::gmean 7513.505454 # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::stdev 7923.201613 # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::0-32767 7786 99.94% 99.94% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.96% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.97% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::total 7791 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walksPending::samples 234495500 # Table walker pending requests distribution 409system.cpu.dtb.walker.walksPending::0 234495500 100.00% 100.00% # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::total 234495500 # Table walker pending requests distribution 411system.cpu.dtb.walker.walkPageSizes::4K 6429 82.52% 82.52% # Table walker page sizes translated 412system.cpu.dtb.walker.walkPageSizes::1M 1362 17.48% 100.00% # Table walker page sizes translated 413system.cpu.dtb.walker.walkPageSizes::total 7791 # Table walker page sizes translated 414system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66845 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66845 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7791 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7791 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin::total 74636 # Table walker requests started/completed, data/inst 421system.cpu.dtb.inst_hits 0 # ITB inst hits 422system.cpu.dtb.inst_misses 0 # ITB inst misses 423system.cpu.dtb.read_hits 24793006 # DTB read hits 424system.cpu.dtb.read_misses 59858 # DTB read misses 425system.cpu.dtb.write_hits 19468400 # DTB write hits 426system.cpu.dtb.write_misses 6987 # DTB write misses 427system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 428system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 429system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 430system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 431system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB 432system.cpu.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions 433system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch 434system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 435system.cpu.dtb.perms_faults 757 # Number of TLB faults due to permissions restrictions 436system.cpu.dtb.read_accesses 24852864 # DTB read accesses 437system.cpu.dtb.write_accesses 19475387 # DTB write accesses 438system.cpu.dtb.inst_accesses 0 # ITB inst accesses 439system.cpu.dtb.hits 44261406 # DTB hits 440system.cpu.dtb.misses 66845 # DTB misses 441system.cpu.dtb.accesses 44328251 # DTB accesses 442system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 451system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 452system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 453system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 454system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 455system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 456system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 459system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 460system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 461system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 462system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 463system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 464system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 465system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 466system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 467system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 468system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 469system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 470system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 471system.cpu.itb.walker.walks 5440 # Table walker walks requested 472system.cpu.itb.walker.walksShort 5440 # Table walker walks initiated with short descriptors 473system.cpu.itb.walker.walksShortTerminationLevel::Level1 316 # Level at which table walker walks with short descriptors terminate 474system.cpu.itb.walker.walksShortTerminationLevel::Level2 5124 # Level at which table walker walks with short descriptors terminate 475system.cpu.itb.walker.walkWaitTime::samples 5440 # Table walker wait (enqueue to first request) latency 476system.cpu.itb.walker.walkWaitTime::0 5440 100.00% 100.00% # Table walker wait (enqueue to first request) latency 477system.cpu.itb.walker.walkWaitTime::total 5440 # Table walker wait (enqueue to first request) latency 478system.cpu.itb.walker.walkCompletionTime::samples 3188 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::mean 10236.198243 # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::gmean 7641.069075 # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::stdev 7067.497935 # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::0-8191 1310 41.09% 41.09% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::8192-16383 1157 36.29% 77.38% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::16384-24575 720 22.58% 99.97% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::total 3188 # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walksPending::samples 234126500 # Table walker pending requests distribution 488system.cpu.itb.walker.walksPending::0 234126500 100.00% 100.00% # Table walker pending requests distribution 489system.cpu.itb.walker.walksPending::total 234126500 # Table walker pending requests distribution 490system.cpu.itb.walker.walkPageSizes::4K 2879 90.31% 90.31% # Table walker page sizes translated 491system.cpu.itb.walker.walkPageSizes::1M 309 9.69% 100.00% # Table walker page sizes translated 492system.cpu.itb.walker.walkPageSizes::total 3188 # Table walker page sizes translated 493system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 494system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5440 # Table walker requests started/completed, data/inst 495system.cpu.itb.walker.walkRequestOrigin_Requested::total 5440 # Table walker requests started/completed, data/inst 496system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3188 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin_Completed::total 3188 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin::total 8628 # Table walker requests started/completed, data/inst 500system.cpu.itb.inst_hits 57692911 # ITB inst hits 501system.cpu.itb.inst_misses 5440 # ITB inst misses 502system.cpu.itb.read_hits 0 # DTB read hits 503system.cpu.itb.read_misses 0 # DTB read misses 504system.cpu.itb.write_hits 0 # DTB write hits 505system.cpu.itb.write_misses 0 # DTB write misses 506system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 507system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 508system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 509system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 510system.cpu.itb.flush_entries 2976 # Number of entries that have been flushed from TLB 511system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 512system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 513system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 514system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions 515system.cpu.itb.read_accesses 0 # DTB read accesses 516system.cpu.itb.write_accesses 0 # DTB write accesses 517system.cpu.itb.inst_accesses 57698351 # ITB inst accesses 518system.cpu.itb.hits 57692911 # DTB hits 519system.cpu.itb.misses 5440 # DTB misses 520system.cpu.itb.accesses 57698351 # DTB accesses 521system.cpu.numCycles 314937774 # number of cpu cycles simulated 522system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 523system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 524system.cpu.committedInsts 112207125 # Number of instructions committed 525system.cpu.committedOps 135672670 # Number of ops (including micro ops) committed 526system.cpu.discardedOps 7783589 # Number of ops (including micro ops) which were discarded before commit 527system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching 528system.cpu.quiesceCycles 5390825701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 529system.cpu.cpi 2.806754 # CPI: cycles per instruction 530system.cpu.ipc 0.356283 # IPC: instructions per cycle 531system.cpu.kern.inst.arm 0 # number of arm instructions executed 532system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed 533system.cpu.tickCycles 228221487 # Number of cycles that the object actually ticked 534system.cpu.idleCycles 86716287 # Total number of cycles that the object has spent stopped 535system.cpu.dcache.tags.replacements 841983 # number of replacements 536system.cpu.dcache.tags.tagsinuse 511.953279 # Cycle average of tags in use 537system.cpu.dcache.tags.total_refs 42762284 # Total number of references to valid blocks. 538system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks. 539system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks. 540system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. 541system.cpu.dcache.tags.occ_blocks::cpu.data 511.953279 # Average occupied blocks per requestor 542system.cpu.dcache.tags.occ_percent::cpu.data 0.999909 # Average percentage of cache occupancy 543system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 544system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 545system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 546system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id 547system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 548system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 549system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses 550system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses 551system.cpu.dcache.ReadReq_hits::cpu.data 23536274 # number of ReadReq hits 552system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits 553system.cpu.dcache.WriteReq_hits::cpu.data 18304900 # number of WriteReq hits 554system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits 555system.cpu.dcache.LoadLockedReq_hits::cpu.data 457909 # number of LoadLockedReq hits 556system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits 557system.cpu.dcache.StoreCondReq_hits::cpu.data 460268 # number of StoreCondReq hits 558system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits 559system.cpu.dcache.demand_hits::cpu.data 41841174 # number of demand (read+write) hits 560system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits 561system.cpu.dcache.overall_hits::cpu.data 41841174 # number of overall hits 562system.cpu.dcache.overall_hits::total 41841174 # number of overall hits 563system.cpu.dcache.ReadReq_misses::cpu.data 583393 # number of ReadReq misses 564system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses 565system.cpu.dcache.WriteReq_misses::cpu.data 541748 # number of WriteReq misses 566system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses 567system.cpu.dcache.LoadLockedReq_misses::cpu.data 8195 # number of LoadLockedReq misses 568system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses 569system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 570system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 571system.cpu.dcache.demand_misses::cpu.data 1125141 # number of demand (read+write) misses 572system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses 573system.cpu.dcache.overall_misses::cpu.data 1125141 # number of overall misses 574system.cpu.dcache.overall_misses::total 1125141 # number of overall misses 575system.cpu.dcache.ReadReq_miss_latency::cpu.data 8651014339 # number of ReadReq miss cycles 576system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles 577system.cpu.dcache.WriteReq_miss_latency::cpu.data 21393186307 # number of WriteReq miss cycles 578system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles 579system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116036500 # number of LoadLockedReq miss cycles 580system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles 581system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles 582system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles 583system.cpu.dcache.demand_miss_latency::cpu.data 30044200646 # number of demand (read+write) miss cycles 584system.cpu.dcache.demand_miss_latency::total 30044200646 # number of demand (read+write) miss cycles 585system.cpu.dcache.overall_miss_latency::cpu.data 30044200646 # number of overall miss cycles 586system.cpu.dcache.overall_miss_latency::total 30044200646 # number of overall miss cycles 587system.cpu.dcache.ReadReq_accesses::cpu.data 24119667 # number of ReadReq accesses(hits+misses) 588system.cpu.dcache.ReadReq_accesses::total 24119667 # number of ReadReq accesses(hits+misses) 589system.cpu.dcache.WriteReq_accesses::cpu.data 18846648 # number of WriteReq accesses(hits+misses) 590system.cpu.dcache.WriteReq_accesses::total 18846648 # number of WriteReq accesses(hits+misses) 591system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466104 # number of LoadLockedReq accesses(hits+misses) 592system.cpu.dcache.LoadLockedReq_accesses::total 466104 # number of LoadLockedReq accesses(hits+misses) 593system.cpu.dcache.StoreCondReq_accesses::cpu.data 460270 # number of StoreCondReq accesses(hits+misses) 594system.cpu.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) 595system.cpu.dcache.demand_accesses::cpu.data 42966315 # number of demand (read+write) accesses 596system.cpu.dcache.demand_accesses::total 42966315 # number of demand (read+write) accesses 597system.cpu.dcache.overall_accesses::cpu.data 42966315 # number of overall (read+write) accesses 598system.cpu.dcache.overall_accesses::total 42966315 # number of overall (read+write) accesses 599system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024187 # miss rate for ReadReq accesses 600system.cpu.dcache.ReadReq_miss_rate::total 0.024187 # miss rate for ReadReq accesses 601system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028745 # miss rate for WriteReq accesses 602system.cpu.dcache.WriteReq_miss_rate::total 0.028745 # miss rate for WriteReq accesses 603system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017582 # miss rate for LoadLockedReq accesses 604system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017582 # miss rate for LoadLockedReq accesses 605system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 606system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 607system.cpu.dcache.demand_miss_rate::cpu.data 0.026187 # miss rate for demand accesses 608system.cpu.dcache.demand_miss_rate::total 0.026187 # miss rate for demand accesses 609system.cpu.dcache.overall_miss_rate::cpu.data 0.026187 # miss rate for overall accesses 610system.cpu.dcache.overall_miss_rate::total 0.026187 # miss rate for overall accesses 611system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14828.793522 # average ReadReq miss latency 612system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522 # average ReadReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39489.183729 # average WriteReq miss latency 614system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729 # average WriteReq miss latency 615system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14159.426480 # average LoadLockedReq miss latency 616system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480 # average LoadLockedReq miss latency 617system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency 618system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency 619system.cpu.dcache.demand_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency 620system.cpu.dcache.demand_avg_miss_latency::total 26702.609403 # average overall miss latency 621system.cpu.dcache.overall_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency 622system.cpu.dcache.overall_avg_miss_latency::total 26702.609403 # average overall miss latency 623system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 624system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 625system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 626system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 627system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 628system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 629system.cpu.dcache.fast_writes 0 # number of fast writes performed 630system.cpu.dcache.cache_copies 0 # number of cache copies performed 631system.cpu.dcache.writebacks::writebacks 698310 # number of writebacks 632system.cpu.dcache.writebacks::total 698310 # number of writebacks 633system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45149 # number of ReadReq MSHR hits 634system.cpu.dcache.ReadReq_mshr_hits::total 45149 # number of ReadReq MSHR hits 635system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242834 # number of WriteReq MSHR hits 636system.cpu.dcache.WriteReq_mshr_hits::total 242834 # number of WriteReq MSHR hits 637system.cpu.dcache.demand_mshr_hits::cpu.data 287983 # number of demand (read+write) MSHR hits 638system.cpu.dcache.demand_mshr_hits::total 287983 # number of demand (read+write) MSHR hits 639system.cpu.dcache.overall_mshr_hits::cpu.data 287983 # number of overall MSHR hits 640system.cpu.dcache.overall_mshr_hits::total 287983 # number of overall MSHR hits 641system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538244 # number of ReadReq MSHR misses 642system.cpu.dcache.ReadReq_mshr_misses::total 538244 # number of ReadReq MSHR misses 643system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298914 # number of WriteReq MSHR misses 644system.cpu.dcache.WriteReq_mshr_misses::total 298914 # number of WriteReq MSHR misses 645system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8195 # number of LoadLockedReq MSHR misses 646system.cpu.dcache.LoadLockedReq_mshr_misses::total 8195 # number of LoadLockedReq MSHR misses 647system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 648system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 649system.cpu.dcache.demand_mshr_misses::cpu.data 837158 # number of demand (read+write) MSHR misses 650system.cpu.dcache.demand_mshr_misses::total 837158 # number of demand (read+write) MSHR misses 651system.cpu.dcache.overall_mshr_misses::cpu.data 837158 # number of overall MSHR misses 652system.cpu.dcache.overall_mshr_misses::total 837158 # number of overall MSHR misses 653system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6893184142 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.ReadReq_mshr_miss_latency::total 6893184142 # number of ReadReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11166823654 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.WriteReq_mshr_miss_latency::total 11166823654 # number of WriteReq MSHR miss cycles 657system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99620500 # number of LoadLockedReq MSHR miss cycles 658system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99620500 # number of LoadLockedReq MSHR miss cycles 659system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146500 # number of StoreCondReq MSHR miss cycles 660system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles 661system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18060007796 # number of demand (read+write) MSHR miss cycles 662system.cpu.dcache.demand_mshr_miss_latency::total 18060007796 # number of demand (read+write) MSHR miss cycles 663system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18060007796 # number of overall MSHR miss cycles 664system.cpu.dcache.overall_mshr_miss_latency::total 18060007796 # number of overall MSHR miss cycles 665system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790998000 # number of ReadReq MSHR uncacheable cycles 666system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790998000 # number of ReadReq MSHR uncacheable cycles 667system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4439562500 # number of WriteReq MSHR uncacheable cycles 668system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439562500 # number of WriteReq MSHR uncacheable cycles 669system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10230560500 # number of overall MSHR uncacheable cycles 670system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230560500 # number of overall MSHR uncacheable cycles 671system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022316 # mshr miss rate for ReadReq accesses 672system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022316 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015860 # mshr miss rate for WriteReq accesses 674system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015860 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017582 # mshr miss rate for LoadLockedReq accesses 676system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017582 # mshr miss rate for LoadLockedReq accesses 677system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 678system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 679system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for demand accesses 680system.cpu.dcache.demand_mshr_miss_rate::total 0.019484 # mshr miss rate for demand accesses 681system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for overall accesses 682system.cpu.dcache.overall_mshr_miss_rate::total 0.019484 # mshr miss rate for overall accesses 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12806.801640 # average ReadReq mshr miss latency 684system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640 # average ReadReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37357.981406 # average WriteReq mshr miss latency 686system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406 # average WriteReq mshr miss latency 687system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12156.253813 # average LoadLockedReq mshr miss latency 688system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813 # average LoadLockedReq mshr miss latency 689system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency 690system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency 691system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency 692system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency 693system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency 694system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency 695system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 696system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 697system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 698system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 699system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 700system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 701system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 702system.cpu.icache.tags.replacements 2900110 # number of replacements 703system.cpu.icache.tags.tagsinuse 511.424371 # Cycle average of tags in use 704system.cpu.icache.tags.total_refs 54783568 # Total number of references to valid blocks. 705system.cpu.icache.tags.sampled_refs 2900622 # Sample count of references to valid blocks. 706system.cpu.icache.tags.avg_refs 18.886835 # Average number of references to valid blocks. 707system.cpu.icache.tags.warmup_cycle 15309705250 # Cycle when the warmup percentage was hit. 708system.cpu.icache.tags.occ_blocks::cpu.inst 511.424371 # Average occupied blocks per requestor 709system.cpu.icache.tags.occ_percent::cpu.inst 0.998876 # Average percentage of cache occupancy 710system.cpu.icache.tags.occ_percent::total 0.998876 # Average percentage of cache occupancy 711system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 712system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 714system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id 715system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 716system.cpu.icache.tags.tag_accesses 60584835 # Number of tag accesses 717system.cpu.icache.tags.data_accesses 60584835 # Number of data accesses 718system.cpu.icache.ReadReq_hits::cpu.inst 54783568 # number of ReadReq hits 719system.cpu.icache.ReadReq_hits::total 54783568 # number of ReadReq hits 720system.cpu.icache.demand_hits::cpu.inst 54783568 # number of demand (read+write) hits 721system.cpu.icache.demand_hits::total 54783568 # number of demand (read+write) hits 722system.cpu.icache.overall_hits::cpu.inst 54783568 # number of overall hits 723system.cpu.icache.overall_hits::total 54783568 # number of overall hits 724system.cpu.icache.ReadReq_misses::cpu.inst 2900634 # number of ReadReq misses 725system.cpu.icache.ReadReq_misses::total 2900634 # number of ReadReq misses 726system.cpu.icache.demand_misses::cpu.inst 2900634 # number of demand (read+write) misses 727system.cpu.icache.demand_misses::total 2900634 # number of demand (read+write) misses 728system.cpu.icache.overall_misses::cpu.inst 2900634 # number of overall misses 729system.cpu.icache.overall_misses::total 2900634 # number of overall misses 730system.cpu.icache.ReadReq_miss_latency::cpu.inst 39169046291 # number of ReadReq miss cycles 731system.cpu.icache.ReadReq_miss_latency::total 39169046291 # number of ReadReq miss cycles 732system.cpu.icache.demand_miss_latency::cpu.inst 39169046291 # number of demand (read+write) miss cycles 733system.cpu.icache.demand_miss_latency::total 39169046291 # number of demand (read+write) miss cycles 734system.cpu.icache.overall_miss_latency::cpu.inst 39169046291 # number of overall miss cycles 735system.cpu.icache.overall_miss_latency::total 39169046291 # number of overall miss cycles 736system.cpu.icache.ReadReq_accesses::cpu.inst 57684202 # number of ReadReq accesses(hits+misses) 737system.cpu.icache.ReadReq_accesses::total 57684202 # number of ReadReq accesses(hits+misses) 738system.cpu.icache.demand_accesses::cpu.inst 57684202 # number of demand (read+write) accesses 739system.cpu.icache.demand_accesses::total 57684202 # number of demand (read+write) accesses 740system.cpu.icache.overall_accesses::cpu.inst 57684202 # number of overall (read+write) accesses 741system.cpu.icache.overall_accesses::total 57684202 # number of overall (read+write) accesses 742system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050285 # miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_miss_rate::total 0.050285 # miss rate for ReadReq accesses 744system.cpu.icache.demand_miss_rate::cpu.inst 0.050285 # miss rate for demand accesses 745system.cpu.icache.demand_miss_rate::total 0.050285 # miss rate for demand accesses 746system.cpu.icache.overall_miss_rate::cpu.inst 0.050285 # miss rate for overall accesses 747system.cpu.icache.overall_miss_rate::total 0.050285 # miss rate for overall accesses 748system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.615517 # average ReadReq miss latency 749system.cpu.icache.ReadReq_avg_miss_latency::total 13503.615517 # average ReadReq miss latency 750system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency 751system.cpu.icache.demand_avg_miss_latency::total 13503.615517 # average overall miss latency 752system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency 753system.cpu.icache.overall_avg_miss_latency::total 13503.615517 # average overall miss latency 754system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 755system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 756system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 757system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 758system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 759system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 760system.cpu.icache.fast_writes 0 # number of fast writes performed 761system.cpu.icache.cache_copies 0 # number of cache copies performed 762system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2900634 # number of ReadReq MSHR misses 763system.cpu.icache.ReadReq_mshr_misses::total 2900634 # number of ReadReq MSHR misses 764system.cpu.icache.demand_mshr_misses::cpu.inst 2900634 # number of demand (read+write) MSHR misses 765system.cpu.icache.demand_mshr_misses::total 2900634 # number of demand (read+write) MSHR misses 766system.cpu.icache.overall_mshr_misses::cpu.inst 2900634 # number of overall MSHR misses 767system.cpu.icache.overall_mshr_misses::total 2900634 # number of overall MSHR misses 768system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33358375709 # number of ReadReq MSHR miss cycles 769system.cpu.icache.ReadReq_mshr_miss_latency::total 33358375709 # number of ReadReq MSHR miss cycles 770system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33358375709 # number of demand (read+write) MSHR miss cycles 771system.cpu.icache.demand_mshr_miss_latency::total 33358375709 # number of demand (read+write) MSHR miss cycles 772system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33358375709 # number of overall MSHR miss cycles 773system.cpu.icache.overall_mshr_miss_latency::total 33358375709 # number of overall MSHR miss cycles 774system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222066250 # number of ReadReq MSHR uncacheable cycles 775system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222066250 # number of ReadReq MSHR uncacheable cycles 776system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222066250 # number of overall MSHR uncacheable cycles 777system.cpu.icache.overall_mshr_uncacheable_latency::total 222066250 # number of overall MSHR uncacheable cycles 778system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for ReadReq accesses 779system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050285 # mshr miss rate for ReadReq accesses 780system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for demand accesses 781system.cpu.icache.demand_mshr_miss_rate::total 0.050285 # mshr miss rate for demand accesses 782system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for overall accesses 783system.cpu.icache.overall_mshr_miss_rate::total 0.050285 # mshr miss rate for overall accesses 784system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11500.373956 # average ReadReq mshr miss latency 785system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11500.373956 # average ReadReq mshr miss latency 786system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency 787system.cpu.icache.demand_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency 788system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency 789system.cpu.icache.overall_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency 790system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 791system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 792system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 793system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 794system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 795system.cpu.l2cache.tags.replacements 96921 # number of replacements 796system.cpu.l2cache.tags.tagsinuse 65071.012008 # Cycle average of tags in use 797system.cpu.l2cache.tags.total_refs 4047776 # Total number of references to valid blocks. 798system.cpu.l2cache.tags.sampled_refs 162169 # Sample count of references to valid blocks. 799system.cpu.l2cache.tags.avg_refs 24.960233 # Average number of references to valid blocks. 800system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 801system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.489031 # Average occupied blocks per requestor 803system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000365 # Average occupied blocks per requestor 804system.cpu.l2cache.tags.occ_blocks::cpu.inst 12194.784847 # Average occupied blocks per requestor 805system.cpu.l2cache.tags.occ_blocks::cpu.data 5306.229599 # Average occupied blocks per requestor 806system.cpu.l2cache.tags.occ_percent::writebacks 0.724770 # Average percentage of cache occupancy 807system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001091 # Average percentage of cache occupancy 808system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186078 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::cpu.data 0.080967 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::total 0.992905 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id 813system.cpu.l2cache.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1023::4 37 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2285 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6934 # Occupied blocks per task id 819system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55872 # Occupied blocks per task id 820system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000565 # Percentage of cache occupancy per task id 821system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id 822system.cpu.l2cache.tags.tag_accesses 36621683 # Number of tag accesses 823system.cpu.l2cache.tags.data_accesses 36621683 # Number of data accesses 824system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71038 # number of ReadReq hits 825system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4429 # number of ReadReq hits 826system.cpu.l2cache.ReadReq_hits::cpu.inst 2877594 # number of ReadReq hits 827system.cpu.l2cache.ReadReq_hits::cpu.data 532037 # number of ReadReq hits 828system.cpu.l2cache.ReadReq_hits::total 3485098 # number of ReadReq hits 829system.cpu.l2cache.Writeback_hits::writebacks 698310 # number of Writeback hits 830system.cpu.l2cache.Writeback_hits::total 698310 # number of Writeback hits 831system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits 832system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits 833system.cpu.l2cache.ReadExReq_hits::cpu.data 164919 # number of ReadExReq hits 834system.cpu.l2cache.ReadExReq_hits::total 164919 # number of ReadExReq hits 835system.cpu.l2cache.demand_hits::cpu.dtb.walker 71038 # number of demand (read+write) hits 836system.cpu.l2cache.demand_hits::cpu.itb.walker 4429 # number of demand (read+write) hits 837system.cpu.l2cache.demand_hits::cpu.inst 2877594 # number of demand (read+write) hits 838system.cpu.l2cache.demand_hits::cpu.data 696956 # number of demand (read+write) hits 839system.cpu.l2cache.demand_hits::total 3650017 # number of demand (read+write) hits 840system.cpu.l2cache.overall_hits::cpu.dtb.walker 71038 # number of overall hits 841system.cpu.l2cache.overall_hits::cpu.itb.walker 4429 # number of overall hits 842system.cpu.l2cache.overall_hits::cpu.inst 2877594 # number of overall hits 843system.cpu.l2cache.overall_hits::cpu.data 696956 # number of overall hits 844system.cpu.l2cache.overall_hits::total 3650017 # number of overall hits 845system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 128 # number of ReadReq misses 846system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 847system.cpu.l2cache.ReadReq_misses::cpu.inst 23013 # number of ReadReq misses 848system.cpu.l2cache.ReadReq_misses::cpu.data 14397 # number of ReadReq misses 849system.cpu.l2cache.ReadReq_misses::total 37539 # number of ReadReq misses 850system.cpu.l2cache.UpgradeReq_misses::cpu.data 2779 # number of UpgradeReq misses 851system.cpu.l2cache.UpgradeReq_misses::total 2779 # number of UpgradeReq misses 852system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 853system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 854system.cpu.l2cache.ReadExReq_misses::cpu.data 131168 # number of ReadExReq misses 855system.cpu.l2cache.ReadExReq_misses::total 131168 # number of ReadExReq misses 856system.cpu.l2cache.demand_misses::cpu.dtb.walker 128 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::cpu.inst 23013 # number of demand (read+write) misses 859system.cpu.l2cache.demand_misses::cpu.data 145565 # number of demand (read+write) misses 860system.cpu.l2cache.demand_misses::total 168707 # number of demand (read+write) misses 861system.cpu.l2cache.overall_misses::cpu.dtb.walker 128 # number of overall misses 862system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 863system.cpu.l2cache.overall_misses::cpu.inst 23013 # number of overall misses 864system.cpu.l2cache.overall_misses::cpu.data 145565 # number of overall misses 865system.cpu.l2cache.overall_misses::total 168707 # number of overall misses 866system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10214250 # number of ReadReq miss cycles 867system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 74500 # number of ReadReq miss cycles 868system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1672158250 # number of ReadReq miss cycles 869system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1100939750 # number of ReadReq miss cycles 870system.cpu.l2cache.ReadReq_miss_latency::total 2783386750 # number of ReadReq miss cycles 871system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 790966 # number of UpgradeReq miss cycles 872system.cpu.l2cache.UpgradeReq_miss_latency::total 790966 # number of UpgradeReq miss cycles 873system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles 874system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles 875system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9154216683 # number of ReadExReq miss cycles 876system.cpu.l2cache.ReadExReq_miss_latency::total 9154216683 # number of ReadExReq miss cycles 877system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10214250 # number of demand (read+write) miss cycles 878system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 74500 # number of demand (read+write) miss cycles 879system.cpu.l2cache.demand_miss_latency::cpu.inst 1672158250 # number of demand (read+write) miss cycles 880system.cpu.l2cache.demand_miss_latency::cpu.data 10255156433 # number of demand (read+write) miss cycles 881system.cpu.l2cache.demand_miss_latency::total 11937603433 # number of demand (read+write) miss cycles 882system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10214250 # number of overall miss cycles 883system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 74500 # number of overall miss cycles 884system.cpu.l2cache.overall_miss_latency::cpu.inst 1672158250 # number of overall miss cycles 885system.cpu.l2cache.overall_miss_latency::cpu.data 10255156433 # number of overall miss cycles 886system.cpu.l2cache.overall_miss_latency::total 11937603433 # number of overall miss cycles 887system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71166 # number of ReadReq accesses(hits+misses) 888system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4430 # number of ReadReq accesses(hits+misses) 889system.cpu.l2cache.ReadReq_accesses::cpu.inst 2900607 # number of ReadReq accesses(hits+misses) 890system.cpu.l2cache.ReadReq_accesses::cpu.data 546434 # number of ReadReq accesses(hits+misses) 891system.cpu.l2cache.ReadReq_accesses::total 3522637 # number of ReadReq accesses(hits+misses) 892system.cpu.l2cache.Writeback_accesses::writebacks 698310 # number of Writeback accesses(hits+misses) 893system.cpu.l2cache.Writeback_accesses::total 698310 # number of Writeback accesses(hits+misses) 894system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2832 # number of UpgradeReq accesses(hits+misses) 895system.cpu.l2cache.UpgradeReq_accesses::total 2832 # number of UpgradeReq accesses(hits+misses) 896system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 897system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 898system.cpu.l2cache.ReadExReq_accesses::cpu.data 296087 # number of ReadExReq accesses(hits+misses) 899system.cpu.l2cache.ReadExReq_accesses::total 296087 # number of ReadExReq accesses(hits+misses) 900system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71166 # number of demand (read+write) accesses 901system.cpu.l2cache.demand_accesses::cpu.itb.walker 4430 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::cpu.inst 2900607 # number of demand (read+write) accesses 903system.cpu.l2cache.demand_accesses::cpu.data 842521 # number of demand (read+write) accesses 904system.cpu.l2cache.demand_accesses::total 3818724 # number of demand (read+write) accesses 905system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71166 # number of overall (read+write) accesses 906system.cpu.l2cache.overall_accesses::cpu.itb.walker 4430 # number of overall (read+write) accesses 907system.cpu.l2cache.overall_accesses::cpu.inst 2900607 # number of overall (read+write) accesses 908system.cpu.l2cache.overall_accesses::cpu.data 842521 # number of overall (read+write) accesses 909system.cpu.l2cache.overall_accesses::total 3818724 # number of overall (read+write) accesses 910system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001799 # miss rate for ReadReq accesses 911system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000226 # miss rate for ReadReq accesses 912system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007934 # miss rate for ReadReq accesses 913system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026347 # miss rate for ReadReq accesses 914system.cpu.l2cache.ReadReq_miss_rate::total 0.010657 # miss rate for ReadReq accesses 915system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981285 # miss rate for UpgradeReq accesses 916system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981285 # miss rate for UpgradeReq accesses 917system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 918system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 919system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443005 # miss rate for ReadExReq accesses 920system.cpu.l2cache.ReadExReq_miss_rate::total 0.443005 # miss rate for ReadExReq accesses 921system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001799 # miss rate for demand accesses 922system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000226 # miss rate for demand accesses 923system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007934 # miss rate for demand accesses 924system.cpu.l2cache.demand_miss_rate::cpu.data 0.172773 # miss rate for demand accesses 925system.cpu.l2cache.demand_miss_rate::total 0.044179 # miss rate for demand accesses 926system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001799 # miss rate for overall accesses 927system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000226 # miss rate for overall accesses 928system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007934 # miss rate for overall accesses 929system.cpu.l2cache.overall_miss_rate::cpu.data 0.172773 # miss rate for overall accesses 930system.cpu.l2cache.overall_miss_rate::total 0.044179 # miss rate for overall accesses 931system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79798.828125 # average ReadReq miss latency 932system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency 933system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72661.463086 # average ReadReq miss latency 934system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76470.080572 # average ReadReq miss latency 935system.cpu.l2cache.ReadReq_avg_miss_latency::total 74146.534271 # average ReadReq miss latency 936system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 284.622526 # average UpgradeReq miss latency 937system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 284.622526 # average UpgradeReq miss latency 938system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency 939system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency 940system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69790.014966 # average ReadExReq miss latency 941system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69790.014966 # average ReadExReq miss latency 942system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency 943system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency 944system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency 945system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency 946system.cpu.l2cache.demand_avg_miss_latency::total 70759.384216 # average overall miss latency 947system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency 948system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency 949system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency 950system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency 951system.cpu.l2cache.overall_avg_miss_latency::total 70759.384216 # average overall miss latency 952system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 953system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 954system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 955system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 956system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 957system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 958system.cpu.l2cache.fast_writes 0 # number of fast writes performed 959system.cpu.l2cache.cache_copies 0 # number of cache copies performed 960system.cpu.l2cache.writebacks::writebacks 88228 # number of writebacks 961system.cpu.l2cache.writebacks::total 88228 # number of writebacks 962system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits 963system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 142 # number of ReadReq MSHR hits 964system.cpu.l2cache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits 965system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits 966system.cpu.l2cache.demand_mshr_hits::cpu.data 142 # number of demand (read+write) MSHR hits 967system.cpu.l2cache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits 968system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits 969system.cpu.l2cache.overall_mshr_hits::cpu.data 142 # number of overall MSHR hits 970system.cpu.l2cache.overall_mshr_hits::total 162 # number of overall MSHR hits 971system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 128 # number of ReadReq MSHR misses 972system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 973system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22993 # number of ReadReq MSHR misses 974system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14255 # number of ReadReq MSHR misses 975system.cpu.l2cache.ReadReq_mshr_misses::total 37377 # number of ReadReq MSHR misses 976system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2779 # number of UpgradeReq MSHR misses 977system.cpu.l2cache.UpgradeReq_mshr_misses::total 2779 # number of UpgradeReq MSHR misses 978system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 979system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 980system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131168 # number of ReadExReq MSHR misses 981system.cpu.l2cache.ReadExReq_mshr_misses::total 131168 # number of ReadExReq MSHR misses 982system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 128 # number of demand (read+write) MSHR misses 983system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 984system.cpu.l2cache.demand_mshr_misses::cpu.inst 22993 # number of demand (read+write) MSHR misses 985system.cpu.l2cache.demand_mshr_misses::cpu.data 145423 # number of demand (read+write) MSHR misses 986system.cpu.l2cache.demand_mshr_misses::total 168545 # number of demand (read+write) MSHR misses 987system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 128 # number of overall MSHR misses 988system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 989system.cpu.l2cache.overall_mshr_misses::cpu.inst 22993 # number of overall MSHR misses 990system.cpu.l2cache.overall_mshr_misses::cpu.data 145423 # number of overall MSHR misses 991system.cpu.l2cache.overall_mshr_misses::total 168545 # number of overall MSHR misses 992system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8641250 # number of ReadReq MSHR miss cycles 993system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 62500 # number of ReadReq MSHR miss cycles 994system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1382505500 # number of ReadReq MSHR miss cycles 995system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 913321500 # number of ReadReq MSHR miss cycles 996system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2304530750 # number of ReadReq MSHR miss cycles 997system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27979779 # number of UpgradeReq MSHR miss cycles 998system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27979779 # number of UpgradeReq MSHR miss cycles 999system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles 1000system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles 1001system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500556317 # number of ReadExReq MSHR miss cycles 1002system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500556317 # number of ReadExReq MSHR miss cycles 1003system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8641250 # number of demand (read+write) MSHR miss cycles 1004system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 1005system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1382505500 # number of demand (read+write) MSHR miss cycles 1006system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413877817 # number of demand (read+write) MSHR miss cycles 1007system.cpu.l2cache.demand_mshr_miss_latency::total 9805087067 # number of demand (read+write) MSHR miss cycles 1008system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8641250 # number of overall MSHR miss cycles 1009system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 62500 # number of overall MSHR miss cycles 1010system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1382505500 # number of overall MSHR miss cycles 1011system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413877817 # number of overall MSHR miss cycles 1012system.cpu.l2cache.overall_mshr_miss_latency::total 9805087067 # number of overall MSHR miss cycles 1013system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 159586250 # number of ReadReq MSHR uncacheable cycles 1014system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385715000 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545301250 # number of ReadReq MSHR uncacheable cycles 1016system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107025000 # number of WriteReq MSHR uncacheable cycles 1017system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107025000 # number of WriteReq MSHR uncacheable cycles 1018system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 159586250 # number of overall MSHR uncacheable cycles 1019system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9492740000 # number of overall MSHR uncacheable cycles 1020system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652326250 # number of overall MSHR uncacheable cycles 1021system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for ReadReq accesses 1022system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for ReadReq accesses 1023system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for ReadReq accesses 1024system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026087 # mshr miss rate for ReadReq accesses 1025system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010611 # mshr miss rate for ReadReq accesses 1026system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981285 # mshr miss rate for UpgradeReq accesses 1027system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981285 # mshr miss rate for UpgradeReq accesses 1028system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1029system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1030system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443005 # mshr miss rate for ReadExReq accesses 1031system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443005 # mshr miss rate for ReadExReq accesses 1032system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for demand accesses 1033system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for demand accesses 1034system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for demand accesses 1035system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for demand accesses 1036system.cpu.l2cache.demand_mshr_miss_rate::total 0.044136 # mshr miss rate for demand accesses 1037system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for overall accesses 1038system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for overall accesses 1039system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for overall accesses 1040system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for overall accesses 1041system.cpu.l2cache.overall_mshr_miss_rate::total 0.044136 # mshr miss rate for overall accesses 1042system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average ReadReq mshr miss latency 1043system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 1044system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60127.234376 # average ReadReq mshr miss latency 1045system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64070.256051 # average ReadReq mshr miss latency 1046system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280 # average ReadReq mshr miss latency 1047system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10068.290392 # average UpgradeReq mshr miss latency 1048system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392 # average UpgradeReq mshr miss latency 1049system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency 1050system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency 1051system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57182.821397 # average ReadExReq mshr miss latency 1052system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency 1053system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency 1054system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1055system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency 1056system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency 1057system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency 1058system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency 1059system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1060system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency 1061system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency 1062system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency 1063system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1064system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1065system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1066system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1067system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1068system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1069system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1070system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1071system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1072system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution 1073system.cpu.toL2Bus.trans_dist::ReadResp 3581627 # Transaction distribution 1074system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution 1075system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution 1076system.cpu.toL2Bus.trans_dist::Writeback 698310 # Transaction distribution 1077system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1078system.cpu.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::UpgradeResp 2834 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::ReadExReq 296087 # Transaction distribution 1082system.cpu.toL2Bus.trans_dist::ReadExResp 296087 # Transaction distribution 1083system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5807240 # Packet count per connected master and slave (bytes) 1084system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506645 # Packet count per connected master and slave (bytes) 1085system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14994 # Packet count per connected master and slave (bytes) 1086system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160889 # Packet count per connected master and slave (bytes) 1087system.cpu.toL2Bus.pkt_count::total 8489768 # Packet count per connected master and slave (bytes) 1088system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185830784 # Cumulative packet size per connected master and slave (bytes) 1089system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98804957 # Cumulative packet size per connected master and slave (bytes) 1090system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17720 # Cumulative packet size per connected master and slave (bytes) 1091system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284664 # Cumulative packet size per connected master and slave (bytes) 1092system.cpu.toL2Bus.pkt_size::total 284938125 # Cumulative packet size per connected master and slave (bytes) 1093system.cpu.toL2Bus.snoops 61311 # Total snoops (count) 1094system.cpu.toL2Bus.snoop_fanout::samples 4581044 # Request fanout histogram 1095system.cpu.toL2Bus.snoop_fanout::mean 5.007958 # Request fanout histogram 1096system.cpu.toL2Bus.snoop_fanout::stdev 0.088854 # Request fanout histogram 1097system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1098system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1099system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1100system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::5 4544586 99.20% 99.20% # Request fanout histogram 1104system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1106system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1108system.cpu.toL2Bus.snoop_fanout::total 4581044 # Request fanout histogram 1109system.cpu.toL2Bus.reqLayer0.occupancy 3015323412 # Layer occupancy (ticks) 1110system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1111system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) 1112system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1113system.cpu.toL2Bus.respLayer0.occupancy 4360848041 # Layer occupancy (ticks) 1114system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1115system.cpu.toL2Bus.respLayer1.occupancy 1341145704 # Layer occupancy (ticks) 1116system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1117system.cpu.toL2Bus.respLayer2.occupancy 10564000 # Layer occupancy (ticks) 1118system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1119system.cpu.toL2Bus.respLayer3.occupancy 89727250 # Layer occupancy (ticks) 1120system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1121system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 1122system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 1123system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 1124system.iobus.trans_dist::WriteResp 22814 # Transaction distribution 1125system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1126system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1133system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1134system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1135system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1136system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1137system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1138system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1139system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1140system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1141system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1142system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1143system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1144system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1145system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1146system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1147system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 1148system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1149system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1150system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1158system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1159system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1160system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1161system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1163system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1164system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1165system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1166system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1167system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1168system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1169system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1170system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1171system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1172system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 1173system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1174system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1175system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 1176system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 1177system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1178system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1179system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1180system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1181system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1182system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1183system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1184system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1185system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1186system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1187system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1188system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1189system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1190system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1191system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1192system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1193system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1194system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1195system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1196system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1197system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1198system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1199system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1201system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1203system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1205system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1207system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1209system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1211system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1213system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1214system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1215system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1216system.iobus.reqLayer27.occupancy 347055145 # Layer occupancy (ticks) 1217system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1219system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1220system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1221system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1222system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) 1223system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1224system.iocache.tags.replacements 36424 # number of replacements 1225system.iocache.tags.tagsinuse 1.033413 # Cycle average of tags in use 1226system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1227system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1228system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1229system.iocache.tags.warmup_cycle 270192614000 # Cycle when the warmup percentage was hit. 1230system.iocache.tags.occ_blocks::realview.ide 1.033413 # Average occupied blocks per requestor 1231system.iocache.tags.occ_percent::realview.ide 0.064588 # Average percentage of cache occupancy 1232system.iocache.tags.occ_percent::total 0.064588 # Average percentage of cache occupancy 1233system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1234system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1235system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1236system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1237system.iocache.tags.data_accesses 328122 # Number of data accesses 1238system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1239system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1240system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1241system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 1242system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1243system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1244system.iocache.overall_misses::realview.ide 234 # number of overall misses 1245system.iocache.overall_misses::total 234 # number of overall misses 1246system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles 1247system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles 1248system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9592588263 # number of WriteInvalidateReq miss cycles 1249system.iocache.WriteInvalidateReq_miss_latency::total 9592588263 # number of WriteInvalidateReq miss cycles 1250system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles 1251system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles 1252system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles 1253system.iocache.overall_miss_latency::total 27950377 # number of overall miss cycles 1254system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1255system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1256system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1257system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1258system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1259system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1260system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1261system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1262system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1263system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1264system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1265system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1266system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1267system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1268system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1269system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1270system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency 1271system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency 1272system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381 # average WriteInvalidateReq miss latency 1273system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381 # average WriteInvalidateReq miss latency 1274system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency 1275system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency 1276system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency 1277system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency 1278system.iocache.blocked_cycles::no_mshrs 55542 # number of cycles access was blocked 1279system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1280system.iocache.blocked::no_mshrs 7161 # number of cycles access was blocked 1281system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1282system.iocache.avg_blocked_cycles::no_mshrs 7.756179 # average number of cycles each access was blocked 1283system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1284system.iocache.fast_writes 0 # number of fast writes performed 1285system.iocache.cache_copies 0 # number of cache copies performed 1286system.iocache.writebacks::writebacks 36190 # number of writebacks 1287system.iocache.writebacks::total 36190 # number of writebacks 1288system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1289system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1290system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1291system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 1292system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1293system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1294system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1295system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1296system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles 1297system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles 1298system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7708930273 # number of WriteInvalidateReq MSHR miss cycles 1299system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7708930273 # number of WriteInvalidateReq MSHR miss cycles 1300system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles 1301system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles 1302system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles 1303system.iocache.overall_mshr_miss_latency::total 15781377 # number of overall MSHR miss cycles 1304system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1305system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1306system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1307system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1308system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1309system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1310system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1311system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1312system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency 1313system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency 1314system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597 # average WriteInvalidateReq mshr miss latency 1315system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597 # average WriteInvalidateReq mshr miss latency 1316system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency 1317system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency 1318system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency 1319system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency 1320system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1321system.membus.trans_dist::ReadReq 71749 # Transaction distribution 1322system.membus.trans_dist::ReadResp 71749 # Transaction distribution 1323system.membus.trans_dist::WriteReq 27607 # Transaction distribution 1324system.membus.trans_dist::WriteResp 27607 # Transaction distribution 1325system.membus.trans_dist::Writeback 124418 # Transaction distribution 1326system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1327system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1328system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution 1329system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1330system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution 1331system.membus.trans_dist::ReadExReq 129351 # Transaction distribution 1332system.membus.trans_dist::ReadExResp 129351 # Transaction distribution 1333system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1334system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1335system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) 1336system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446451 # Packet count per connected master and slave (bytes) 1337system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554083 # Packet count per connected master and slave (bytes) 1338system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) 1339system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) 1340system.membus.pkt_count::total 662970 # Packet count per connected master and slave (bytes) 1341system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1342system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 1343system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) 1344system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16510296 # Cumulative packet size per connected master and slave (bytes) 1345system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16674077 # Cumulative packet size per connected master and slave (bytes) 1346system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1347system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 1348system.membus.pkt_size::total 21309533 # Cumulative packet size per connected master and slave (bytes) 1349system.membus.snoops 506 # Total snoops (count) 1350system.membus.snoop_fanout::samples 332202 # Request fanout histogram 1351system.membus.snoop_fanout::mean 1 # Request fanout histogram 1352system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1353system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1354system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1355system.membus.snoop_fanout::1 332202 100.00% 100.00% # Request fanout histogram 1356system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1357system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1358system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1359system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1360system.membus.snoop_fanout::total 332202 # Request fanout histogram 1361system.membus.reqLayer0.occupancy 87413000 # Layer occupancy (ticks) 1362system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1363system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1364system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1365system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) 1366system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1367system.membus.reqLayer5.occupancy 1674431500 # Layer occupancy (ticks) 1368system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 1369system.membus.respLayer2.occupancy 1690391904 # Layer occupancy (ticks) 1370system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1371system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) 1372system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1373system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1374system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1375system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1376system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1377system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1378system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1379system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1380system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1381system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1382system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1383system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1384system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1385system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1386system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1387system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1388system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1389system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1390system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1391system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1392system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1393system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1394system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1395system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1396system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1397system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1398system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1399system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1400system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1401system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1402system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1403system.realview.ethernet.droppedPackets 0 # number of packets dropped 1404 1405---------- End Simulation Statistics ---------- 1406