stats.txt revision 10585:1c9d5d9417b3
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.852850 # Number of seconds simulated 4sim_ticks 2852849954000 # Number of ticks simulated 5final_tick 2852849954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 160685 # Simulator instruction rate (inst/s) 8host_op_rate 194286 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4092855045 # Simulator tick rate (ticks/s) 10host_mem_usage 562916 # Number of bytes of host memory used 11host_seconds 697.03 # Real time elapsed on the host 12sim_insts 112002684 # Number of instructions simulated 13sim_ops 135423332 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10823844 # Number of bytes read from this memory 19system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 10832740 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1658560 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1658560 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7967296 # Number of bytes written to this memory 24system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory 25system.physmem.bytes_written::total 7984820 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 169642 # Number of read requests responded to by this memory 29system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 169781 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 124489 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 128870 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 2759 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 3794046 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 3797164 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu.inst 581370 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::total 581370 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_write::writebacks 2792750 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_write::cpu.inst 6143 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 2798892 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 2792750 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 2759 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 3800189 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::total 6596057 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.readReqs 169781 # Number of read requests accepted 51system.physmem.writeReqs 165094 # Number of write requests accepted 52system.physmem.readBursts 169781 # Number of DRAM read bursts, including those serviced by the write queue 53system.physmem.writeBursts 165094 # Number of DRAM write bursts, including those merged in the write queue 54system.physmem.bytesReadDRAM 10858880 # Total number of bytes read from DRAM 55system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue 56system.physmem.bytesWritten 10194112 # Total number of bytes written to DRAM 57system.physmem.bytesReadSys 10832740 # Total read bytes from the system interface side 58system.physmem.bytesWrittenSys 10303156 # Total written bytes from the system interface side 59system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue 60system.physmem.mergedWrBursts 5787 # Number of DRAM write bursts merged with an existing one 61system.physmem.neitherReadNorWriteReqs 4592 # Number of requests that are neither read nor write 62system.physmem.perBankRdBursts::0 10675 # Per bank write bursts 63system.physmem.perBankRdBursts::1 10570 # Per bank write bursts 64system.physmem.perBankRdBursts::2 10940 # Per bank write bursts 65system.physmem.perBankRdBursts::3 10884 # Per bank write bursts 66system.physmem.perBankRdBursts::4 12996 # Per bank write bursts 67system.physmem.perBankRdBursts::5 10666 # Per bank write bursts 68system.physmem.perBankRdBursts::6 11098 # Per bank write bursts 69system.physmem.perBankRdBursts::7 10877 # Per bank write bursts 70system.physmem.perBankRdBursts::8 10287 # Per bank write bursts 71system.physmem.perBankRdBursts::9 10457 # Per bank write bursts 72system.physmem.perBankRdBursts::10 10268 # Per bank write bursts 73system.physmem.perBankRdBursts::11 9318 # Per bank write bursts 74system.physmem.perBankRdBursts::12 10425 # Per bank write bursts 75system.physmem.perBankRdBursts::13 10908 # Per bank write bursts 76system.physmem.perBankRdBursts::14 9678 # Per bank write bursts 77system.physmem.perBankRdBursts::15 9623 # Per bank write bursts 78system.physmem.perBankWrBursts::0 10097 # Per bank write bursts 79system.physmem.perBankWrBursts::1 10006 # Per bank write bursts 80system.physmem.perBankWrBursts::2 10747 # Per bank write bursts 81system.physmem.perBankWrBursts::3 10511 # Per bank write bursts 82system.physmem.perBankWrBursts::4 9282 # Per bank write bursts 83system.physmem.perBankWrBursts::5 9914 # Per bank write bursts 84system.physmem.perBankWrBursts::6 10247 # Per bank write bursts 85system.physmem.perBankWrBursts::7 10166 # Per bank write bursts 86system.physmem.perBankWrBursts::8 10178 # Per bank write bursts 87system.physmem.perBankWrBursts::9 10302 # Per bank write bursts 88system.physmem.perBankWrBursts::10 10037 # Per bank write bursts 89system.physmem.perBankWrBursts::11 9553 # Per bank write bursts 90system.physmem.perBankWrBursts::12 10068 # Per bank write bursts 91system.physmem.perBankWrBursts::13 10279 # Per bank write bursts 92system.physmem.perBankWrBursts::14 8984 # Per bank write bursts 93system.physmem.perBankWrBursts::15 8912 # Per bank write bursts 94system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 95system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 96system.physmem.totGap 2852849531000 # Total gap between requests 97system.physmem.readPktSize::0 0 # Read request sizes (log2) 98system.physmem.readPktSize::1 0 # Read request sizes (log2) 99system.physmem.readPktSize::2 541 # Read request sizes (log2) 100system.physmem.readPktSize::3 14 # Read request sizes (log2) 101system.physmem.readPktSize::4 0 # Read request sizes (log2) 102system.physmem.readPktSize::5 0 # Read request sizes (log2) 103system.physmem.readPktSize::6 169226 # Read request sizes (log2) 104system.physmem.writePktSize::0 0 # Write request sizes (log2) 105system.physmem.writePktSize::1 0 # Write request sizes (log2) 106system.physmem.writePktSize::2 4381 # Write request sizes (log2) 107system.physmem.writePktSize::3 0 # Write request sizes (log2) 108system.physmem.writePktSize::4 0 # Write request sizes (log2) 109system.physmem.writePktSize::5 0 # Write request sizes (log2) 110system.physmem.writePktSize::6 160713 # Write request sizes (log2) 111system.physmem.rdQLenPdf::0 162999 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 6619 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 143system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::15 2176 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 3867 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 7745 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::18 8889 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::19 9235 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::20 9997 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 10332 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::22 11185 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 11099 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 11636 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 10861 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::26 10486 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::27 9441 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::28 8955 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::29 7752 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 7407 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::31 7274 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::32 7126 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::35 317 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::36 275 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::38 223 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::39 205 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::41 187 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::42 174 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 207system.physmem.bytesPerActivate::samples 62892 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::mean 334.747313 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::gmean 194.220308 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::stdev 348.895470 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::0-127 22415 35.64% 35.64% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::128-255 14531 23.10% 58.75% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::256-383 6612 10.51% 69.26% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::384-511 3482 5.54% 74.79% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::512-639 2506 3.98% 78.78% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::640-767 1581 2.51% 81.29% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::768-895 1054 1.68% 82.97% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::896-1023 1133 1.80% 84.77% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1024-1151 9578 15.23% 100.00% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::total 62892 # Bytes accessed per row activation 221system.physmem.rdPerTurnAround::samples 6668 # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::mean 25.444061 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::stdev 561.318574 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::0-2047 6666 99.97% 99.97% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::total 6668 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 6668 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 23.887672 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 19.937507 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 22.272912 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 5557 83.34% 83.34% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 39 0.58% 83.92% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 24 0.36% 84.28% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 223 3.34% 87.63% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 119 1.78% 89.41% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 51 0.76% 90.18% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 29 0.43% 90.61% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 45 0.67% 91.29% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 120 1.80% 93.09% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 12 0.18% 93.27% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 15 0.22% 93.49% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 14 0.21% 93.70% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 30 0.45% 94.15% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 19 0.28% 94.44% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 8 0.12% 94.56% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 35 0.52% 95.08% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 9 0.13% 96.12% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 6 0.09% 96.21% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::92-95 14 0.21% 96.42% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 100 1.50% 97.92% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 13 0.19% 98.17% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 8 0.12% 98.29% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 22 0.33% 98.62% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 3 0.04% 98.67% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 10 0.15% 98.82% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 3 0.04% 98.86% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 27 0.40% 99.27% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 9 0.13% 99.40% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 2 0.03% 99.43% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 4 0.06% 99.49% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 8 0.12% 99.61% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 5 0.07% 99.69% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::152-155 1 0.01% 99.70% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 2 0.03% 99.73% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 3 0.04% 99.78% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::168-171 1 0.01% 99.79% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::172-175 2 0.03% 99.82% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::176-179 3 0.04% 99.87% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::180-183 1 0.01% 99.88% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::184-187 2 0.03% 99.91% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::188-191 1 0.01% 99.93% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::200-203 1 0.01% 99.94% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::252-255 2 0.03% 100.00% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::total 6668 # Writes before turning the bus around for reads 280system.physmem.totQLat 1702635750 # Total ticks spent queuing 281system.physmem.totMemAccLat 4883948250 # Total ticks spent from burst creation until serviced by the DRAM 282system.physmem.totBusLat 848350000 # Total ticks spent in databus transfers 283system.physmem.avgQLat 10034.98 # Average queueing delay per DRAM burst 284system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 285system.physmem.avgMemAccLat 28784.98 # Average memory access latency per DRAM burst 286system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 287system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s 288system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 289system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s 290system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 291system.physmem.busUtil 0.06 # Data bus utilization in percentage 292system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 293system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 294system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 295system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing 296system.physmem.readRowHits 139924 # Number of row buffer hits during reads 297system.physmem.writeRowHits 126136 # Number of row buffer hits during writes 298system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads 299system.physmem.writeRowHitRate 79.18 # Row buffer hit rate for writes 300system.physmem.avgGap 8519147.54 # Average gap between requests 301system.physmem.pageHitRate 80.87 # Row buffer hit rate, read and write combined 302system.physmem.memoryStateTime::IDLE 2713515031250 # Time in different power states 303system.physmem.memoryStateTime::REF 95262700000 # Time in different power states 304system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 305system.physmem.memoryStateTime::ACT 44072132750 # Time in different power states 306system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 307system.physmem.actEnergy::0 246765960 # Energy for activate commands per rank (pJ) 308system.physmem.actEnergy::1 228697560 # Energy for activate commands per rank (pJ) 309system.physmem.preEnergy::0 134644125 # Energy for precharge commands per rank (pJ) 310system.physmem.preEnergy::1 124785375 # Energy for precharge commands per rank (pJ) 311system.physmem.readEnergy::0 691906800 # Energy for read commands per rank (pJ) 312system.physmem.readEnergy::1 631511400 # Energy for read commands per rank (pJ) 313system.physmem.writeEnergy::0 524685600 # Energy for write commands per rank (pJ) 314system.physmem.writeEnergy::1 507468240 # Energy for write commands per rank (pJ) 315system.physmem.refreshEnergy::0 186333841200 # Energy for refresh commands per rank (pJ) 316system.physmem.refreshEnergy::1 186333841200 # Energy for refresh commands per rank (pJ) 317system.physmem.actBackEnergy::0 83199782385 # Energy for active background per rank (pJ) 318system.physmem.actBackEnergy::1 82045768365 # Energy for active background per rank (pJ) 319system.physmem.preBackEnergy::0 1638723732000 # Energy for precharge background per rank (pJ) 320system.physmem.preBackEnergy::1 1639736025000 # Energy for precharge background per rank (pJ) 321system.physmem.totalEnergy::0 1909855358070 # Total energy per rank (pJ) 322system.physmem.totalEnergy::1 1909608097140 # Total energy per rank (pJ) 323system.physmem.averagePower::0 669.456797 # Core power per rank (mW) 324system.physmem.averagePower::1 669.370126 # Core power per rank (mW) 325system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 329system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 331system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) 336system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) 337system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 338system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 339system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 340system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 341system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 342system.cf0.dma_write_txs 631 # Number of DMA write transactions. 343system.cpu.branchPred.lookups 31051775 # Number of BP lookups 344system.cpu.branchPred.condPredicted 16857996 # Number of conditional branches predicted 345system.cpu.branchPred.condIncorrect 2519060 # Number of conditional branches incorrect 346system.cpu.branchPred.BTBLookups 18534749 # Number of BTB lookups 347system.cpu.branchPred.BTBHits 13337392 # Number of BTB hits 348system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 349system.cpu.branchPred.BTBHitPct 71.958849 # BTB Hit Percentage 350system.cpu.branchPred.usedRAS 7856975 # Number of times the RAS was used to get a target. 351system.cpu.branchPred.RASInCorrect 1512712 # Number of incorrect RAS predictions. 352system.cpu_clk_domain.clock 500 # Clock period in ticks 353system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 354system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 355system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 356system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 357system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 358system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 359system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 360system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 361system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 362system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 363system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 364system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 365system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 366system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 367system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 369system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 370system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 371system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 372system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 373system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 374system.cpu.dtb.inst_hits 0 # ITB inst hits 375system.cpu.dtb.inst_misses 0 # ITB inst misses 376system.cpu.dtb.read_hits 24746159 # DTB read hits 377system.cpu.dtb.read_misses 60199 # DTB read misses 378system.cpu.dtb.write_hits 19443156 # DTB write hits 379system.cpu.dtb.write_misses 6950 # DTB write misses 380system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 381system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 382system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 383system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 384system.cpu.dtb.flush_entries 4352 # Number of entries that have been flushed from TLB 385system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions 386system.cpu.dtb.prefetch_faults 1783 # Number of TLB faults due to prefetch 387system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 388system.cpu.dtb.perms_faults 751 # Number of TLB faults due to permissions restrictions 389system.cpu.dtb.read_accesses 24806358 # DTB read accesses 390system.cpu.dtb.write_accesses 19450106 # DTB write accesses 391system.cpu.dtb.inst_accesses 0 # ITB inst accesses 392system.cpu.dtb.hits 44189315 # DTB hits 393system.cpu.dtb.misses 67149 # DTB misses 394system.cpu.dtb.accesses 44256464 # DTB accesses 395system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 396system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 397system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 398system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 399system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 400system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 401system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 402system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 403system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 404system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 405system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 406system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 407system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 408system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 409system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 411system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 412system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 413system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 414system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 415system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 416system.cpu.itb.inst_hits 57672689 # ITB inst hits 417system.cpu.itb.inst_misses 5411 # ITB inst misses 418system.cpu.itb.read_hits 0 # DTB read hits 419system.cpu.itb.read_misses 0 # DTB read misses 420system.cpu.itb.write_hits 0 # DTB write hits 421system.cpu.itb.write_misses 0 # DTB write misses 422system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 423system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 424system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 425system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 426system.cpu.itb.flush_entries 2970 # Number of entries that have been flushed from TLB 427system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 428system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 429system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 430system.cpu.itb.perms_faults 8383 # Number of TLB faults due to permissions restrictions 431system.cpu.itb.read_accesses 0 # DTB read accesses 432system.cpu.itb.write_accesses 0 # DTB write accesses 433system.cpu.itb.inst_accesses 57678100 # ITB inst accesses 434system.cpu.itb.hits 57672689 # DTB hits 435system.cpu.itb.misses 5411 # DTB misses 436system.cpu.itb.accesses 57678100 # DTB accesses 437system.cpu.numCycles 314966932 # number of cpu cycles simulated 438system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 439system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 440system.cpu.committedInsts 112002684 # Number of instructions committed 441system.cpu.committedOps 135423332 # Number of ops (including micro ops) committed 442system.cpu.discardedOps 7762811 # Number of ops (including micro ops) which were discarded before commit 443system.cpu.numFetchSuspends 3036 # Number of times Execute suspended instruction fetching 444system.cpu.quiesceCycles 5390780993 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 445system.cpu.cpi 2.812137 # CPI: cycles per instruction 446system.cpu.ipc 0.355601 # IPC: instructions per cycle 447system.cpu.kern.inst.arm 0 # number of arm instructions executed 448system.cpu.kern.inst.quiesce 3036 # number of quiesce instructions executed 449system.cpu.tickCycles 228185661 # Number of cycles that the object actually ticked 450system.cpu.idleCycles 86781271 # Total number of cycles that the object has spent stopped 451system.cpu.dcache.tags.replacements 843230 # number of replacements 452system.cpu.dcache.tags.tagsinuse 511.953176 # Cycle average of tags in use 453system.cpu.dcache.tags.total_refs 42691062 # Total number of references to valid blocks. 454system.cpu.dcache.tags.sampled_refs 843742 # Sample count of references to valid blocks. 455system.cpu.dcache.tags.avg_refs 50.597294 # Average number of references to valid blocks. 456system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. 457system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953176 # Average occupied blocks per requestor 458system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy 459system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 461system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id 464system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 465system.cpu.dcache.tags.tag_accesses 176134397 # Number of tag accesses 466system.cpu.dcache.tags.data_accesses 176134397 # Number of data accesses 467system.cpu.dcache.ReadReq_hits::cpu.inst 23488260 # number of ReadReq hits 468system.cpu.dcache.ReadReq_hits::total 23488260 # number of ReadReq hits 469system.cpu.dcache.WriteReq_hits::cpu.inst 18281937 # number of WriteReq hits 470system.cpu.dcache.WriteReq_hits::total 18281937 # number of WriteReq hits 471system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457712 # number of LoadLockedReq hits 472system.cpu.dcache.LoadLockedReq_hits::total 457712 # number of LoadLockedReq hits 473system.cpu.dcache.StoreCondReq_hits::cpu.inst 460238 # number of StoreCondReq hits 474system.cpu.dcache.StoreCondReq_hits::total 460238 # number of StoreCondReq hits 475system.cpu.dcache.demand_hits::cpu.inst 41770197 # number of demand (read+write) hits 476system.cpu.dcache.demand_hits::total 41770197 # number of demand (read+write) hits 477system.cpu.dcache.overall_hits::cpu.inst 41770197 # number of overall hits 478system.cpu.dcache.overall_hits::total 41770197 # number of overall hits 479system.cpu.dcache.ReadReq_misses::cpu.inst 584617 # number of ReadReq misses 480system.cpu.dcache.ReadReq_misses::total 584617 # number of ReadReq misses 481system.cpu.dcache.WriteReq_misses::cpu.inst 541532 # number of WriteReq misses 482system.cpu.dcache.WriteReq_misses::total 541532 # number of WriteReq misses 483system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8359 # number of LoadLockedReq misses 484system.cpu.dcache.LoadLockedReq_misses::total 8359 # number of LoadLockedReq misses 485system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 486system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 487system.cpu.dcache.demand_misses::cpu.inst 1126149 # number of demand (read+write) misses 488system.cpu.dcache.demand_misses::total 1126149 # number of demand (read+write) misses 489system.cpu.dcache.overall_misses::cpu.inst 1126149 # number of overall misses 490system.cpu.dcache.overall_misses::total 1126149 # number of overall misses 491system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8658802092 # number of ReadReq miss cycles 492system.cpu.dcache.ReadReq_miss_latency::total 8658802092 # number of ReadReq miss cycles 493system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21460434801 # number of WriteReq miss cycles 494system.cpu.dcache.WriteReq_miss_latency::total 21460434801 # number of WriteReq miss cycles 495system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117977250 # number of LoadLockedReq miss cycles 496system.cpu.dcache.LoadLockedReq_miss_latency::total 117977250 # number of LoadLockedReq miss cycles 497system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 152000 # number of StoreCondReq miss cycles 498system.cpu.dcache.StoreCondReq_miss_latency::total 152000 # number of StoreCondReq miss cycles 499system.cpu.dcache.demand_miss_latency::cpu.inst 30119236893 # number of demand (read+write) miss cycles 500system.cpu.dcache.demand_miss_latency::total 30119236893 # number of demand (read+write) miss cycles 501system.cpu.dcache.overall_miss_latency::cpu.inst 30119236893 # number of overall miss cycles 502system.cpu.dcache.overall_miss_latency::total 30119236893 # number of overall miss cycles 503system.cpu.dcache.ReadReq_accesses::cpu.inst 24072877 # number of ReadReq accesses(hits+misses) 504system.cpu.dcache.ReadReq_accesses::total 24072877 # number of ReadReq accesses(hits+misses) 505system.cpu.dcache.WriteReq_accesses::cpu.inst 18823469 # number of WriteReq accesses(hits+misses) 506system.cpu.dcache.WriteReq_accesses::total 18823469 # number of WriteReq accesses(hits+misses) 507system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466071 # number of LoadLockedReq accesses(hits+misses) 508system.cpu.dcache.LoadLockedReq_accesses::total 466071 # number of LoadLockedReq accesses(hits+misses) 509system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460240 # number of StoreCondReq accesses(hits+misses) 510system.cpu.dcache.StoreCondReq_accesses::total 460240 # number of StoreCondReq accesses(hits+misses) 511system.cpu.dcache.demand_accesses::cpu.inst 42896346 # number of demand (read+write) accesses 512system.cpu.dcache.demand_accesses::total 42896346 # number of demand (read+write) accesses 513system.cpu.dcache.overall_accesses::cpu.inst 42896346 # number of overall (read+write) accesses 514system.cpu.dcache.overall_accesses::total 42896346 # number of overall (read+write) accesses 515system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024285 # miss rate for ReadReq accesses 516system.cpu.dcache.ReadReq_miss_rate::total 0.024285 # miss rate for ReadReq accesses 517system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028769 # miss rate for WriteReq accesses 518system.cpu.dcache.WriteReq_miss_rate::total 0.028769 # miss rate for WriteReq accesses 519system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017935 # miss rate for LoadLockedReq accesses 520system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017935 # miss rate for LoadLockedReq accesses 521system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses 522system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 523system.cpu.dcache.demand_miss_rate::cpu.inst 0.026253 # miss rate for demand accesses 524system.cpu.dcache.demand_miss_rate::total 0.026253 # miss rate for demand accesses 525system.cpu.dcache.overall_miss_rate::cpu.inst 0.026253 # miss rate for overall accesses 526system.cpu.dcache.overall_miss_rate::total 0.026253 # miss rate for overall accesses 527system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14811.067916 # average ReadReq miss latency 528system.cpu.dcache.ReadReq_avg_miss_latency::total 14811.067916 # average ReadReq miss latency 529system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39629.116656 # average WriteReq miss latency 530system.cpu.dcache.WriteReq_avg_miss_latency::total 39629.116656 # average WriteReq miss latency 531system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14113.799498 # average LoadLockedReq miss latency 532system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14113.799498 # average LoadLockedReq miss latency 533system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 76000 # average StoreCondReq miss latency 534system.cpu.dcache.StoreCondReq_avg_miss_latency::total 76000 # average StoreCondReq miss latency 535system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26745.339110 # average overall miss latency 536system.cpu.dcache.demand_avg_miss_latency::total 26745.339110 # average overall miss latency 537system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26745.339110 # average overall miss latency 538system.cpu.dcache.overall_avg_miss_latency::total 26745.339110 # average overall miss latency 539system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 540system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 542system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 543system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 544system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.cpu.dcache.fast_writes 0 # number of fast writes performed 546system.cpu.dcache.cache_copies 0 # number of cache copies performed 547system.cpu.dcache.writebacks::writebacks 699279 # number of writebacks 548system.cpu.dcache.writebacks::total 699279 # number of writebacks 549system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45143 # number of ReadReq MSHR hits 550system.cpu.dcache.ReadReq_mshr_hits::total 45143 # number of ReadReq MSHR hits 551system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242778 # number of WriteReq MSHR hits 552system.cpu.dcache.WriteReq_mshr_hits::total 242778 # number of WriteReq MSHR hits 553system.cpu.dcache.demand_mshr_hits::cpu.inst 287921 # number of demand (read+write) MSHR hits 554system.cpu.dcache.demand_mshr_hits::total 287921 # number of demand (read+write) MSHR hits 555system.cpu.dcache.overall_mshr_hits::cpu.inst 287921 # number of overall MSHR hits 556system.cpu.dcache.overall_mshr_hits::total 287921 # number of overall MSHR hits 557system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 539474 # number of ReadReq MSHR misses 558system.cpu.dcache.ReadReq_mshr_misses::total 539474 # number of ReadReq MSHR misses 559system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298754 # number of WriteReq MSHR misses 560system.cpu.dcache.WriteReq_mshr_misses::total 298754 # number of WriteReq MSHR misses 561system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8359 # number of LoadLockedReq MSHR misses 562system.cpu.dcache.LoadLockedReq_mshr_misses::total 8359 # number of LoadLockedReq MSHR misses 563system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 564system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 565system.cpu.dcache.demand_mshr_misses::cpu.inst 838228 # number of demand (read+write) MSHR misses 566system.cpu.dcache.demand_mshr_misses::total 838228 # number of demand (read+write) MSHR misses 567system.cpu.dcache.overall_mshr_misses::cpu.inst 838228 # number of overall MSHR misses 568system.cpu.dcache.overall_mshr_misses::total 838228 # number of overall MSHR misses 569system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6896325139 # number of ReadReq MSHR miss cycles 570system.cpu.dcache.ReadReq_mshr_miss_latency::total 6896325139 # number of ReadReq MSHR miss cycles 571system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11211804160 # number of WriteReq MSHR miss cycles 572system.cpu.dcache.WriteReq_mshr_miss_latency::total 11211804160 # number of WriteReq MSHR miss cycles 573system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101230750 # number of LoadLockedReq MSHR miss cycles 574system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101230750 # number of LoadLockedReq MSHR miss cycles 575system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 148000 # number of StoreCondReq MSHR miss cycles 576system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 148000 # number of StoreCondReq MSHR miss cycles 577system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18108129299 # number of demand (read+write) MSHR miss cycles 578system.cpu.dcache.demand_mshr_miss_latency::total 18108129299 # number of demand (read+write) MSHR miss cycles 579system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18108129299 # number of overall MSHR miss cycles 580system.cpu.dcache.overall_mshr_miss_latency::total 18108129299 # number of overall MSHR miss cycles 581system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790997000 # number of ReadReq MSHR uncacheable cycles 582system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790997000 # number of ReadReq MSHR uncacheable cycles 583system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439577500 # number of WriteReq MSHR uncacheable cycles 584system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439577500 # number of WriteReq MSHR uncacheable cycles 585system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230574500 # number of overall MSHR uncacheable cycles 586system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230574500 # number of overall MSHR uncacheable cycles 587system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022410 # mshr miss rate for ReadReq accesses 588system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022410 # mshr miss rate for ReadReq accesses 589system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015871 # mshr miss rate for WriteReq accesses 590system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015871 # mshr miss rate for WriteReq accesses 591system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017935 # mshr miss rate for LoadLockedReq accesses 592system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017935 # mshr miss rate for LoadLockedReq accesses 593system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses 594system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 595system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019541 # mshr miss rate for demand accesses 596system.cpu.dcache.demand_mshr_miss_rate::total 0.019541 # mshr miss rate for demand accesses 597system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019541 # mshr miss rate for overall accesses 598system.cpu.dcache.overall_mshr_miss_rate::total 0.019541 # mshr miss rate for overall accesses 599system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.424482 # average ReadReq mshr miss latency 600system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.424482 # average ReadReq mshr miss latency 601system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37528.549107 # average WriteReq mshr miss latency 602system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37528.549107 # average WriteReq mshr miss latency 603system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12110.389999 # average LoadLockedReq mshr miss latency 604system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12110.389999 # average LoadLockedReq mshr miss latency 605system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 74000 # average StoreCondReq mshr miss latency 606system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 74000 # average StoreCondReq mshr miss latency 607system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21602.868550 # average overall mshr miss latency 608system.cpu.dcache.demand_avg_mshr_miss_latency::total 21602.868550 # average overall mshr miss latency 609system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21602.868550 # average overall mshr miss latency 610system.cpu.dcache.overall_avg_mshr_miss_latency::total 21602.868550 # average overall mshr miss latency 611system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 612system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 613system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 614system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 615system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 616system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 617system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 618system.cpu.icache.tags.replacements 2898546 # number of replacements 619system.cpu.icache.tags.tagsinuse 511.424366 # Cycle average of tags in use 620system.cpu.icache.tags.total_refs 54764882 # Total number of references to valid blocks. 621system.cpu.icache.tags.sampled_refs 2899058 # Sample count of references to valid blocks. 622system.cpu.icache.tags.avg_refs 18.890578 # Average number of references to valid blocks. 623system.cpu.icache.tags.warmup_cycle 15302672250 # Cycle when the warmup percentage was hit. 624system.cpu.icache.tags.occ_blocks::cpu.inst 511.424366 # Average occupied blocks per requestor 625system.cpu.icache.tags.occ_percent::cpu.inst 0.998876 # Average percentage of cache occupancy 626system.cpu.icache.tags.occ_percent::total 0.998876 # Average percentage of cache occupancy 627system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 628system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 629system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id 631system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 632system.cpu.icache.tags.tag_accesses 60563021 # Number of tag accesses 633system.cpu.icache.tags.data_accesses 60563021 # Number of data accesses 634system.cpu.icache.ReadReq_hits::cpu.inst 54764882 # number of ReadReq hits 635system.cpu.icache.ReadReq_hits::total 54764882 # number of ReadReq hits 636system.cpu.icache.demand_hits::cpu.inst 54764882 # number of demand (read+write) hits 637system.cpu.icache.demand_hits::total 54764882 # number of demand (read+write) hits 638system.cpu.icache.overall_hits::cpu.inst 54764882 # number of overall hits 639system.cpu.icache.overall_hits::total 54764882 # number of overall hits 640system.cpu.icache.ReadReq_misses::cpu.inst 2899070 # number of ReadReq misses 641system.cpu.icache.ReadReq_misses::total 2899070 # number of ReadReq misses 642system.cpu.icache.demand_misses::cpu.inst 2899070 # number of demand (read+write) misses 643system.cpu.icache.demand_misses::total 2899070 # number of demand (read+write) misses 644system.cpu.icache.overall_misses::cpu.inst 2899070 # number of overall misses 645system.cpu.icache.overall_misses::total 2899070 # number of overall misses 646system.cpu.icache.ReadReq_miss_latency::cpu.inst 39144211468 # number of ReadReq miss cycles 647system.cpu.icache.ReadReq_miss_latency::total 39144211468 # number of ReadReq miss cycles 648system.cpu.icache.demand_miss_latency::cpu.inst 39144211468 # number of demand (read+write) miss cycles 649system.cpu.icache.demand_miss_latency::total 39144211468 # number of demand (read+write) miss cycles 650system.cpu.icache.overall_miss_latency::cpu.inst 39144211468 # number of overall miss cycles 651system.cpu.icache.overall_miss_latency::total 39144211468 # number of overall miss cycles 652system.cpu.icache.ReadReq_accesses::cpu.inst 57663952 # number of ReadReq accesses(hits+misses) 653system.cpu.icache.ReadReq_accesses::total 57663952 # number of ReadReq accesses(hits+misses) 654system.cpu.icache.demand_accesses::cpu.inst 57663952 # number of demand (read+write) accesses 655system.cpu.icache.demand_accesses::total 57663952 # number of demand (read+write) accesses 656system.cpu.icache.overall_accesses::cpu.inst 57663952 # number of overall (read+write) accesses 657system.cpu.icache.overall_accesses::total 57663952 # number of overall (read+write) accesses 658system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050275 # miss rate for ReadReq accesses 659system.cpu.icache.ReadReq_miss_rate::total 0.050275 # miss rate for ReadReq accesses 660system.cpu.icache.demand_miss_rate::cpu.inst 0.050275 # miss rate for demand accesses 661system.cpu.icache.demand_miss_rate::total 0.050275 # miss rate for demand accesses 662system.cpu.icache.overall_miss_rate::cpu.inst 0.050275 # miss rate for overall accesses 663system.cpu.icache.overall_miss_rate::total 0.050275 # miss rate for overall accesses 664system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13502.334013 # average ReadReq miss latency 665system.cpu.icache.ReadReq_avg_miss_latency::total 13502.334013 # average ReadReq miss latency 666system.cpu.icache.demand_avg_miss_latency::cpu.inst 13502.334013 # average overall miss latency 667system.cpu.icache.demand_avg_miss_latency::total 13502.334013 # average overall miss latency 668system.cpu.icache.overall_avg_miss_latency::cpu.inst 13502.334013 # average overall miss latency 669system.cpu.icache.overall_avg_miss_latency::total 13502.334013 # average overall miss latency 670system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 671system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 673system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 674system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 675system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu.icache.fast_writes 0 # number of fast writes performed 677system.cpu.icache.cache_copies 0 # number of cache copies performed 678system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2899070 # number of ReadReq MSHR misses 679system.cpu.icache.ReadReq_mshr_misses::total 2899070 # number of ReadReq MSHR misses 680system.cpu.icache.demand_mshr_misses::cpu.inst 2899070 # number of demand (read+write) MSHR misses 681system.cpu.icache.demand_mshr_misses::total 2899070 # number of demand (read+write) MSHR misses 682system.cpu.icache.overall_mshr_misses::cpu.inst 2899070 # number of overall MSHR misses 683system.cpu.icache.overall_mshr_misses::total 2899070 # number of overall MSHR misses 684system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33336586532 # number of ReadReq MSHR miss cycles 685system.cpu.icache.ReadReq_mshr_miss_latency::total 33336586532 # number of ReadReq MSHR miss cycles 686system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33336586532 # number of demand (read+write) MSHR miss cycles 687system.cpu.icache.demand_mshr_miss_latency::total 33336586532 # number of demand (read+write) MSHR miss cycles 688system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33336586532 # number of overall MSHR miss cycles 689system.cpu.icache.overall_mshr_miss_latency::total 33336586532 # number of overall MSHR miss cycles 690system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222066250 # number of ReadReq MSHR uncacheable cycles 691system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222066250 # number of ReadReq MSHR uncacheable cycles 692system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222066250 # number of overall MSHR uncacheable cycles 693system.cpu.icache.overall_mshr_uncacheable_latency::total 222066250 # number of overall MSHR uncacheable cycles 694system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050275 # mshr miss rate for ReadReq accesses 695system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050275 # mshr miss rate for ReadReq accesses 696system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050275 # mshr miss rate for demand accesses 697system.cpu.icache.demand_mshr_miss_rate::total 0.050275 # mshr miss rate for demand accesses 698system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050275 # mshr miss rate for overall accesses 699system.cpu.icache.overall_mshr_miss_rate::total 0.050275 # mshr miss rate for overall accesses 700system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11499.062297 # average ReadReq mshr miss latency 701system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11499.062297 # average ReadReq mshr miss latency 702system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11499.062297 # average overall mshr miss latency 703system.cpu.icache.demand_avg_mshr_miss_latency::total 11499.062297 # average overall mshr miss latency 704system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11499.062297 # average overall mshr miss latency 705system.cpu.icache.overall_avg_mshr_miss_latency::total 11499.062297 # average overall mshr miss latency 706system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 707system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 708system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 709system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 710system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 711system.cpu.l2cache.tags.replacements 96693 # number of replacements 712system.cpu.l2cache.tags.tagsinuse 65074.721793 # Cycle average of tags in use 713system.cpu.l2cache.tags.total_refs 4049393 # Total number of references to valid blocks. 714system.cpu.l2cache.tags.sampled_refs 161936 # Sample count of references to valid blocks. 715system.cpu.l2cache.tags.avg_refs 25.006132 # Average number of references to valid blocks. 716system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 717system.cpu.l2cache.tags.occ_blocks::writebacks 47626.273785 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.769943 # Average occupied blocks per requestor 719system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000365 # Average occupied blocks per requestor 720system.cpu.l2cache.tags.occ_blocks::cpu.inst 17377.677699 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_percent::writebacks 0.726719 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001080 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 724system.cpu.l2cache.tags.occ_percent::cpu.inst 0.265162 # Average percentage of cache occupancy 725system.cpu.l2cache.tags.occ_percent::total 0.992961 # Average percentage of cache occupancy 726system.cpu.l2cache.tags.occ_task_id_blocks::1023 43 # Occupied blocks per task id 727system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id 729system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 730system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 731system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2281 # Occupied blocks per task id 732system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6890 # Occupied blocks per task id 733system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55911 # Occupied blocks per task id 734system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000656 # Percentage of cache occupancy per task id 735system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id 736system.cpu.l2cache.tags.tag_accesses 36630547 # Number of tag accesses 737system.cpu.l2cache.tags.data_accesses 36630547 # Number of data accesses 738system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71506 # number of ReadReq hits 739system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4492 # number of ReadReq hits 740system.cpu.l2cache.ReadReq_hits::cpu.inst 3409625 # number of ReadReq hits 741system.cpu.l2cache.ReadReq_hits::total 3485623 # number of ReadReq hits 742system.cpu.l2cache.Writeback_hits::writebacks 699279 # number of Writeback hits 743system.cpu.l2cache.Writeback_hits::total 699279 # number of Writeback hits 744system.cpu.l2cache.UpgradeReq_hits::cpu.inst 49 # number of UpgradeReq hits 745system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits 746system.cpu.l2cache.ReadExReq_hits::cpu.inst 164818 # number of ReadExReq hits 747system.cpu.l2cache.ReadExReq_hits::total 164818 # number of ReadExReq hits 748system.cpu.l2cache.demand_hits::cpu.dtb.walker 71506 # number of demand (read+write) hits 749system.cpu.l2cache.demand_hits::cpu.itb.walker 4492 # number of demand (read+write) hits 750system.cpu.l2cache.demand_hits::cpu.inst 3574443 # number of demand (read+write) hits 751system.cpu.l2cache.demand_hits::total 3650441 # number of demand (read+write) hits 752system.cpu.l2cache.overall_hits::cpu.dtb.walker 71506 # number of overall hits 753system.cpu.l2cache.overall_hits::cpu.itb.walker 4492 # number of overall hits 754system.cpu.l2cache.overall_hits::cpu.inst 3574443 # number of overall hits 755system.cpu.l2cache.overall_hits::total 3650441 # number of overall hits 756system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 123 # number of ReadReq misses 757system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 758system.cpu.l2cache.ReadReq_misses::cpu.inst 37236 # number of ReadReq misses 759system.cpu.l2cache.ReadReq_misses::total 37360 # number of ReadReq misses 760system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2769 # number of UpgradeReq misses 761system.cpu.l2cache.UpgradeReq_misses::total 2769 # number of UpgradeReq misses 762system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses 763system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 764system.cpu.l2cache.ReadExReq_misses::cpu.inst 131123 # number of ReadExReq misses 765system.cpu.l2cache.ReadExReq_misses::total 131123 # number of ReadExReq misses 766system.cpu.l2cache.demand_misses::cpu.dtb.walker 123 # number of demand (read+write) misses 767system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 768system.cpu.l2cache.demand_misses::cpu.inst 168359 # number of demand (read+write) misses 769system.cpu.l2cache.demand_misses::total 168483 # number of demand (read+write) misses 770system.cpu.l2cache.overall_misses::cpu.dtb.walker 123 # number of overall misses 771system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 772system.cpu.l2cache.overall_misses::cpu.inst 168359 # number of overall misses 773system.cpu.l2cache.overall_misses::total 168483 # number of overall misses 774system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 9516500 # number of ReadReq miss cycles 775system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 74500 # number of ReadReq miss cycles 776system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2756078250 # number of ReadReq miss cycles 777system.cpu.l2cache.ReadReq_miss_latency::total 2765669250 # number of ReadReq miss cycles 778system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 839964 # number of UpgradeReq miss cycles 779system.cpu.l2cache.UpgradeReq_miss_latency::total 839964 # number of UpgradeReq miss cycles 780system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 146000 # number of SCUpgradeReq miss cycles 781system.cpu.l2cache.SCUpgradeReq_miss_latency::total 146000 # number of SCUpgradeReq miss cycles 782system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9200663428 # number of ReadExReq miss cycles 783system.cpu.l2cache.ReadExReq_miss_latency::total 9200663428 # number of ReadExReq miss cycles 784system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9516500 # number of demand (read+write) miss cycles 785system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 74500 # number of demand (read+write) miss cycles 786system.cpu.l2cache.demand_miss_latency::cpu.inst 11956741678 # number of demand (read+write) miss cycles 787system.cpu.l2cache.demand_miss_latency::total 11966332678 # number of demand (read+write) miss cycles 788system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9516500 # number of overall miss cycles 789system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 74500 # number of overall miss cycles 790system.cpu.l2cache.overall_miss_latency::cpu.inst 11956741678 # number of overall miss cycles 791system.cpu.l2cache.overall_miss_latency::total 11966332678 # number of overall miss cycles 792system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71629 # number of ReadReq accesses(hits+misses) 793system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4493 # number of ReadReq accesses(hits+misses) 794system.cpu.l2cache.ReadReq_accesses::cpu.inst 3446861 # number of ReadReq accesses(hits+misses) 795system.cpu.l2cache.ReadReq_accesses::total 3522983 # number of ReadReq accesses(hits+misses) 796system.cpu.l2cache.Writeback_accesses::writebacks 699279 # number of Writeback accesses(hits+misses) 797system.cpu.l2cache.Writeback_accesses::total 699279 # number of Writeback accesses(hits+misses) 798system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2818 # number of UpgradeReq accesses(hits+misses) 799system.cpu.l2cache.UpgradeReq_accesses::total 2818 # number of UpgradeReq accesses(hits+misses) 800system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 801system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 802system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295941 # number of ReadExReq accesses(hits+misses) 803system.cpu.l2cache.ReadExReq_accesses::total 295941 # number of ReadExReq accesses(hits+misses) 804system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71629 # number of demand (read+write) accesses 805system.cpu.l2cache.demand_accesses::cpu.itb.walker 4493 # number of demand (read+write) accesses 806system.cpu.l2cache.demand_accesses::cpu.inst 3742802 # number of demand (read+write) accesses 807system.cpu.l2cache.demand_accesses::total 3818924 # number of demand (read+write) accesses 808system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71629 # number of overall (read+write) accesses 809system.cpu.l2cache.overall_accesses::cpu.itb.walker 4493 # number of overall (read+write) accesses 810system.cpu.l2cache.overall_accesses::cpu.inst 3742802 # number of overall (read+write) accesses 811system.cpu.l2cache.overall_accesses::total 3818924 # number of overall (read+write) accesses 812system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001717 # miss rate for ReadReq accesses 813system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000223 # miss rate for ReadReq accesses 814system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010803 # miss rate for ReadReq accesses 815system.cpu.l2cache.ReadReq_miss_rate::total 0.010605 # miss rate for ReadReq accesses 816system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.982612 # miss rate for UpgradeReq accesses 817system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982612 # miss rate for UpgradeReq accesses 818system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 819system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 820system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.443071 # miss rate for ReadExReq accesses 821system.cpu.l2cache.ReadExReq_miss_rate::total 0.443071 # miss rate for ReadExReq accesses 822system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001717 # miss rate for demand accesses 823system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000223 # miss rate for demand accesses 824system.cpu.l2cache.demand_miss_rate::cpu.inst 0.044982 # miss rate for demand accesses 825system.cpu.l2cache.demand_miss_rate::total 0.044118 # miss rate for demand accesses 826system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001717 # miss rate for overall accesses 827system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000223 # miss rate for overall accesses 828system.cpu.l2cache.overall_miss_rate::cpu.inst 0.044982 # miss rate for overall accesses 829system.cpu.l2cache.overall_miss_rate::total 0.044118 # miss rate for overall accesses 830system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77369.918699 # average ReadReq miss latency 831system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency 832system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74016.496133 # average ReadReq miss latency 833system.cpu.l2cache.ReadReq_avg_miss_latency::total 74027.549518 # average ReadReq miss latency 834system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 303.345612 # average UpgradeReq miss latency 835system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 303.345612 # average UpgradeReq miss latency 836system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 73000 # average SCUpgradeReq miss latency 837system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 73000 # average SCUpgradeReq miss latency 838system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.188861 # average ReadExReq miss latency 839system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.188861 # average ReadExReq miss latency 840system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77369.918699 # average overall miss latency 841system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency 842system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71019.319894 # average overall miss latency 843system.cpu.l2cache.demand_avg_miss_latency::total 71023.976769 # average overall miss latency 844system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77369.918699 # average overall miss latency 845system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency 846system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71019.319894 # average overall miss latency 847system.cpu.l2cache.overall_avg_miss_latency::total 71023.976769 # average overall miss latency 848system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 849system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 850system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 851system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 852system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 853system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 854system.cpu.l2cache.fast_writes 0 # number of fast writes performed 855system.cpu.l2cache.cache_copies 0 # number of cache copies performed 856system.cpu.l2cache.writebacks::writebacks 88299 # number of writebacks 857system.cpu.l2cache.writebacks::total 88299 # number of writebacks 858system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 156 # number of ReadReq MSHR hits 859system.cpu.l2cache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits 860system.cpu.l2cache.demand_mshr_hits::cpu.inst 156 # number of demand (read+write) MSHR hits 861system.cpu.l2cache.demand_mshr_hits::total 156 # number of demand (read+write) MSHR hits 862system.cpu.l2cache.overall_mshr_hits::cpu.inst 156 # number of overall MSHR hits 863system.cpu.l2cache.overall_mshr_hits::total 156 # number of overall MSHR hits 864system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 123 # number of ReadReq MSHR misses 865system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 866system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37080 # number of ReadReq MSHR misses 867system.cpu.l2cache.ReadReq_mshr_misses::total 37204 # number of ReadReq MSHR misses 868system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2769 # number of UpgradeReq MSHR misses 869system.cpu.l2cache.UpgradeReq_mshr_misses::total 2769 # number of UpgradeReq MSHR misses 870system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 871system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 872system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131123 # number of ReadExReq MSHR misses 873system.cpu.l2cache.ReadExReq_mshr_misses::total 131123 # number of ReadExReq MSHR misses 874system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses 875system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 876system.cpu.l2cache.demand_mshr_misses::cpu.inst 168203 # number of demand (read+write) MSHR misses 877system.cpu.l2cache.demand_mshr_misses::total 168327 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses 879system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 880system.cpu.l2cache.overall_mshr_misses::cpu.inst 168203 # number of overall MSHR misses 881system.cpu.l2cache.overall_mshr_misses::total 168327 # number of overall MSHR misses 882system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8002500 # number of ReadReq MSHR miss cycles 883system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 62500 # number of ReadReq MSHR miss cycles 884system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2281616000 # number of ReadReq MSHR miss cycles 885system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2289681000 # number of ReadReq MSHR miss cycles 886system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27874769 # number of UpgradeReq MSHR miss cycles 887system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27874769 # number of UpgradeReq MSHR miss cycles 888system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 122000 # number of SCUpgradeReq MSHR miss cycles 889system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 122000 # number of SCUpgradeReq MSHR miss cycles 890system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7547217572 # number of ReadExReq MSHR miss cycles 891system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7547217572 # number of ReadExReq MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8002500 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9828833572 # number of demand (read+write) MSHR miss cycles 895system.cpu.l2cache.demand_mshr_miss_latency::total 9836898572 # number of demand (read+write) MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8002500 # number of overall MSHR miss cycles 897system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 62500 # number of overall MSHR miss cycles 898system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9828833572 # number of overall MSHR miss cycles 899system.cpu.l2cache.overall_mshr_miss_latency::total 9836898572 # number of overall MSHR miss cycles 900system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545306500 # number of ReadReq MSHR uncacheable cycles 901system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545306500 # number of ReadReq MSHR uncacheable cycles 902system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4107046000 # number of WriteReq MSHR uncacheable cycles 903system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107046000 # number of WriteReq MSHR uncacheable cycles 904system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652352500 # number of overall MSHR uncacheable cycles 905system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652352500 # number of overall MSHR uncacheable cycles 906system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses 907system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010758 # mshr miss rate for ReadReq accesses 909system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010560 # mshr miss rate for ReadReq accesses 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.982612 # mshr miss rate for UpgradeReq accesses 911system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982612 # mshr miss rate for UpgradeReq accesses 912system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 913system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 914system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443071 # mshr miss rate for ReadExReq accesses 915system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443071 # mshr miss rate for ReadExReq accesses 916system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses 917system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses 918system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for demand accesses 919system.cpu.l2cache.demand_mshr_miss_rate::total 0.044077 # mshr miss rate for demand accesses 920system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses 921system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for overall accesses 922system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for overall accesses 923system.cpu.l2cache.overall_mshr_miss_rate::total 0.044077 # mshr miss rate for overall accesses 924system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average ReadReq mshr miss latency 925system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 926system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61532.254585 # average ReadReq mshr miss latency 927system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61543.946887 # average ReadReq mshr miss latency 928system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10066.727700 # average UpgradeReq mshr miss latency 929system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10066.727700 # average UpgradeReq mshr miss latency 930system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 61000 # average SCUpgradeReq mshr miss latency 931system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 61000 # average SCUpgradeReq mshr miss latency 932system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57558.304584 # average ReadExReq mshr miss latency 933system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57558.304584 # average ReadExReq mshr miss latency 934system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency 935system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 936system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency 938system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency 939system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency 941system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency 942system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 943system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 944system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 945system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 946system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 947system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 948system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 949system.cpu.toL2Bus.trans_dist::ReadReq 3581708 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::ReadResp 3581608 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::Writeback 699279 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution 959system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution 960system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804102 # Packet count per connected master and slave (bytes) 961system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2510082 # Packet count per connected master and slave (bytes) 962system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14997 # Packet count per connected master and slave (bytes) 963system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161563 # Packet count per connected master and slave (bytes) 964system.cpu.toL2Bus.pkt_count::total 8490744 # Packet count per connected master and slave (bytes) 965system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185730048 # Cumulative packet size per connected master and slave (bytes) 966system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98946845 # Cumulative packet size per connected master and slave (bytes) 967system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17972 # Cumulative packet size per connected master and slave (bytes) 968system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 286516 # Cumulative packet size per connected master and slave (bytes) 969system.cpu.toL2Bus.pkt_size::total 284981381 # Cumulative packet size per connected master and slave (bytes) 970system.cpu.toL2Bus.snoops 60946 # Total snoops (count) 971system.cpu.toL2Bus.snoop_fanout::samples 4581834 # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::mean 5.007957 # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::stdev 0.088847 # Request fanout histogram 974system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 977system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 978system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 979system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 980system.cpu.toL2Bus.snoop_fanout::5 4545376 99.20% 99.20% # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 983system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 984system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 985system.cpu.toL2Bus.snoop_fanout::total 4581834 # Request fanout histogram 986system.cpu.toL2Bus.reqLayer0.occupancy 3016682672 # Layer occupancy (ticks) 987system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 988system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) 989system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 990system.cpu.toL2Bus.respLayer0.occupancy 4358543218 # Layer occupancy (ticks) 991system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 992system.cpu.toL2Bus.respLayer1.occupancy 1342977701 # Layer occupancy (ticks) 993system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 994system.cpu.toL2Bus.respLayer2.occupancy 10504000 # Layer occupancy (ticks) 995system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 996system.cpu.toL2Bus.respLayer3.occupancy 89938750 # Layer occupancy (ticks) 997system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 998system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 999system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 1000system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 1001system.iobus.trans_dist::WriteResp 22814 # Transaction distribution 1002system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1003system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1005system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1006system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1007system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1008system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1009system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1010system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1011system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1012system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1013system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1014system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1015system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1016system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1017system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1018system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1019system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1020system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1021system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1022system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1024system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 1025system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1026system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1027system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 1028system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 1029system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1030system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1031system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1032system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1033system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1034system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1035system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1036system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1037system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1038system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1039system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1040system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1041system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1042system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1043system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1044system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1045system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1052system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 1053system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 1054system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1055system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1056system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1057system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1058system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1059system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1060system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1061system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1062system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1063system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1064system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1065system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1066system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1067system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1068system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1069system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1070system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1071system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1072system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1073system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1074system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1075system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1076system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1077system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1078system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1079system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1080system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1081system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1082system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1083system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1084system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1085system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1086system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1087system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1088system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1090system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1092system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1093system.iobus.reqLayer27.occupancy 347024164 # Layer occupancy (ticks) 1094system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1096system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1097system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1098system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1099system.iobus.respLayer3.occupancy 36804504 # Layer occupancy (ticks) 1100system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1101system.iocache.tags.replacements 36424 # number of replacements 1102system.iocache.tags.tagsinuse 1.033420 # Cycle average of tags in use 1103system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1104system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1105system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1106system.iocache.tags.warmup_cycle 270180945000 # Cycle when the warmup percentage was hit. 1107system.iocache.tags.occ_blocks::realview.ide 1.033420 # Average occupied blocks per requestor 1108system.iocache.tags.occ_percent::realview.ide 0.064589 # Average percentage of cache occupancy 1109system.iocache.tags.occ_percent::total 0.064589 # Average percentage of cache occupancy 1110system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1111system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1112system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1113system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1114system.iocache.tags.data_accesses 328122 # Number of data accesses 1115system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1116system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1117system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1118system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 1119system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1120system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1121system.iocache.overall_misses::realview.ide 234 # number of overall misses 1122system.iocache.overall_misses::total 234 # number of overall misses 1123system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles 1124system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles 1125system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9603131283 # number of WriteInvalidateReq miss cycles 1126system.iocache.WriteInvalidateReq_miss_latency::total 9603131283 # number of WriteInvalidateReq miss cycles 1127system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles 1128system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles 1129system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles 1130system.iocache.overall_miss_latency::total 27950377 # number of overall miss cycles 1131system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1132system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1133system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1134system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1135system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1136system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1137system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1138system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1139system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1140system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1141system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1142system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1143system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1144system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1145system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1146system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1147system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency 1148system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency 1149system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265104.110065 # average WriteInvalidateReq miss latency 1150system.iocache.WriteInvalidateReq_avg_miss_latency::total 265104.110065 # average WriteInvalidateReq miss latency 1151system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency 1152system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency 1153system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency 1154system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency 1155system.iocache.blocked_cycles::no_mshrs 56022 # number of cycles access was blocked 1156system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1157system.iocache.blocked::no_mshrs 7210 # number of cycles access was blocked 1158system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1159system.iocache.avg_blocked_cycles::no_mshrs 7.770042 # average number of cycles each access was blocked 1160system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1161system.iocache.fast_writes 0 # number of fast writes performed 1162system.iocache.cache_copies 0 # number of cache copies performed 1163system.iocache.writebacks::writebacks 36190 # number of writebacks 1164system.iocache.writebacks::total 36190 # number of writebacks 1165system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1166system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1167system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1168system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 1169system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1170system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1171system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1172system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1173system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles 1174system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles 1175system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7719475291 # number of WriteInvalidateReq MSHR miss cycles 1176system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7719475291 # number of WriteInvalidateReq MSHR miss cycles 1177system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles 1178system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles 1179system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles 1180system.iocache.overall_mshr_miss_latency::total 15781377 # number of overall MSHR miss cycles 1181system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1182system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1183system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1184system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1185system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1186system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1187system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1188system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1189system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency 1190system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency 1191system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213103.889438 # average WriteInvalidateReq mshr miss latency 1192system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213103.889438 # average WriteInvalidateReq mshr miss latency 1193system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency 1194system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency 1195system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency 1196system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency 1197system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1198system.membus.trans_dist::ReadReq 71576 # Transaction distribution 1199system.membus.trans_dist::ReadResp 71576 # Transaction distribution 1200system.membus.trans_dist::WriteReq 27607 # Transaction distribution 1201system.membus.trans_dist::WriteResp 27607 # Transaction distribution 1202system.membus.trans_dist::Writeback 124489 # Transaction distribution 1203system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1204system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1205system.membus.trans_dist::UpgradeReq 4592 # Transaction distribution 1206system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1207system.membus.trans_dist::UpgradeResp 4594 # Transaction distribution 1208system.membus.trans_dist::ReadExReq 129300 # Transaction distribution 1209system.membus.trans_dist::ReadExResp 129300 # Transaction distribution 1210system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1211system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1212system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) 1213system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446065 # Packet count per connected master and slave (bytes) 1214system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553697 # Packet count per connected master and slave (bytes) 1215system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) 1216system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) 1217system.membus.pkt_count::total 662584 # Packet count per connected master and slave (bytes) 1218system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1219system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 1220system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) 1221system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16500440 # Cumulative packet size per connected master and slave (bytes) 1222system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16664221 # Cumulative packet size per connected master and slave (bytes) 1223system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1224system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 1225system.membus.pkt_size::total 21299677 # Cumulative packet size per connected master and slave (bytes) 1226system.membus.snoops 507 # Total snoops (count) 1227system.membus.snoop_fanout::samples 332045 # Request fanout histogram 1228system.membus.snoop_fanout::mean 1 # Request fanout histogram 1229system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1230system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1231system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1232system.membus.snoop_fanout::1 332045 100.00% 100.00% # Request fanout histogram 1233system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1234system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1235system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1236system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1237system.membus.snoop_fanout::total 332045 # Request fanout histogram 1238system.membus.reqLayer0.occupancy 87455500 # Layer occupancy (ticks) 1239system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1240system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1241system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1242system.membus.reqLayer2.occupancy 1699000 # Layer occupancy (ticks) 1243system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1244system.membus.reqLayer5.occupancy 1675329000 # Layer occupancy (ticks) 1245system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 1246system.membus.respLayer2.occupancy 1688631909 # Layer occupancy (ticks) 1247system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1248system.membus.respLayer3.occupancy 38334496 # Layer occupancy (ticks) 1249system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1250system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1251system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1252system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1253system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1254system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1255system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1256system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1257system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1258system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1259system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1260system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1261system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1262system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1263system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1264system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1265system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1266system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1267system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1268system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1269system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1270system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1271system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1272system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1273system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1274system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1275system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1276system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1277system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1278system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1279system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1280system.realview.ethernet.droppedPackets 0 # number of packets dropped 1281 1282---------- End Simulation Statistics ---------- 1283