stats.txt revision 10260
110260SAndrew.Bardsley@arm.com 210260SAndrew.Bardsley@arm.com---------- Begin Simulation Statistics ---------- 310260SAndrew.Bardsley@arm.comfinal_tick 2567690995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 410260SAndrew.Bardsley@arm.comhost_inst_rate 83247 # Simulator instruction rate (inst/s) 510260SAndrew.Bardsley@arm.comhost_mem_usage 453632 # Number of bytes of host memory used 610260SAndrew.Bardsley@arm.comhost_op_rate 107007 # Simulator op (including micro ops) rate (op/s) 710260SAndrew.Bardsley@arm.comhost_seconds 727.87 # Real time elapsed on the host 810260SAndrew.Bardsley@arm.comhost_tick_rate 3527658330 # Simulator tick rate (ticks/s) 910260SAndrew.Bardsley@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 1010260SAndrew.Bardsley@arm.comsim_insts 60593069 # Number of instructions simulated 1110260SAndrew.Bardsley@arm.comsim_ops 77887632 # Number of ops (including micro ops) simulated 1210260SAndrew.Bardsley@arm.comsim_seconds 2.567691 # Number of seconds simulated 1310260SAndrew.Bardsley@arm.comsim_ticks 2567690995500 # Number of ticks simulated 1410260SAndrew.Bardsley@arm.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1510260SAndrew.Bardsley@arm.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1610260SAndrew.Bardsley@arm.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1710260SAndrew.Bardsley@arm.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1810260SAndrew.Bardsley@arm.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1910260SAndrew.Bardsley@arm.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 2010260SAndrew.Bardsley@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 2110260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2210260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBHitPct 71.037327 # BTB Hit Percentage 2310260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBHits 6285951 # Number of BTB hits 2410260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.BTBLookups 8848800 # Number of BTB lookups 2510260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.RASInCorrect 141766 # Number of incorrect RAS predictions. 2610260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.condIncorrect 1083327 # Number of conditional branches incorrect 2710260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.condPredicted 9899581 # Number of conditional branches predicted 2810260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.lookups 12901223 # Number of BP lookups 2910260SAndrew.Bardsley@arm.comsystem.cpu.branchPred.usedRAS 1514142 # Number of times the RAS was used to get a target. 3010260SAndrew.Bardsley@arm.comsystem.cpu.committedInsts 60593069 # Number of instructions committed 3110260SAndrew.Bardsley@arm.comsystem.cpu.committedOps 77887632 # Number of ops (including micro ops) committed 3210260SAndrew.Bardsley@arm.comsystem.cpu.cpi 9.521608 # CPI: cycles per instruction 3310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247603 # number of LoadLockedReq accesses(hits+misses) 3410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 247603 # number of LoadLockedReq accesses(hits+misses) 3510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13892.781561 # average LoadLockedReq miss latency 3610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13892.781561 # average LoadLockedReq miss latency 3710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11890.018527 # average LoadLockedReq mshr miss latency 3810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.018527 # average LoadLockedReq mshr miss latency 3910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.inst 236735 # number of LoadLockedReq hits 4010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 236735 # number of LoadLockedReq hits 4110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 150986750 # number of LoadLockedReq miss cycles 4210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 150986750 # number of LoadLockedReq miss cycles 4310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043893 # miss rate for LoadLockedReq accesses 4410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.043893 # miss rate for LoadLockedReq accesses 4510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.inst 10868 # number of LoadLockedReq misses 4610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 10868 # number of LoadLockedReq misses 4710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 73 # number of LoadLockedReq MSHR hits 4810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 73 # number of LoadLockedReq MSHR hits 4910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 128352750 # number of LoadLockedReq MSHR miss cycles 5010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128352750 # number of LoadLockedReq MSHR miss cycles 5110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043598 # mshr miss rate for LoadLockedReq accesses 5210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043598 # mshr miss rate for LoadLockedReq accesses 5310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10795 # number of LoadLockedReq MSHR misses 5410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 10795 # number of LoadLockedReq MSHR misses 5510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.inst 13864450 # number of ReadReq accesses(hits+misses) 5610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_accesses::total 13864450 # number of ReadReq accesses(hits+misses) 5710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15150.498583 # average ReadReq miss latency 5810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 15150.498583 # average ReadReq miss latency 5910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12786.142134 # average ReadReq mshr miss latency 6010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12786.142134 # average ReadReq mshr miss latency 6110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 6210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 6310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.inst 13401466 # number of ReadReq hits 6410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_hits::total 13401466 # number of ReadReq hits 6510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.inst 7014438436 # number of ReadReq miss cycles 6610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 7014438436 # number of ReadReq miss cycles 6710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.033394 # miss rate for ReadReq accesses 6810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.033394 # miss rate for ReadReq accesses 6910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.inst 462984 # number of ReadReq misses 7010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_misses::total 462984 # number of ReadReq misses 7110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.inst 82872 # number of ReadReq MSHR hits 7210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 82872 # number of ReadReq MSHR hits 7310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4860166059 # number of ReadReq MSHR miss cycles 7410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4860166059 # number of ReadReq MSHR miss cycles 7510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.027416 # mshr miss rate for ReadReq accesses 7610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027416 # mshr miss rate for ReadReq accesses 7710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.inst 380112 # number of ReadReq MSHR misses 7810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 380112 # number of ReadReq MSHR misses 7910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182581857500 # number of ReadReq MSHR uncacheable cycles 8010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182581857500 # number of ReadReq MSHR uncacheable cycles 8110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.inst 247602 # number of StoreCondReq accesses(hits+misses) 8210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 247602 # number of StoreCondReq accesses(hits+misses) 8310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.inst 247602 # number of StoreCondReq hits 8410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits 8510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.inst 10222557 # number of WriteReq accesses(hits+misses) 8610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_accesses::total 10222557 # number of WriteReq accesses(hits+misses) 8710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46293.122518 # average WriteReq miss latency 8810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 46293.122518 # average WriteReq miss latency 8910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.604187 # average WriteReq mshr miss latency 9010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.604187 # average WriteReq mshr miss latency 9110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 9210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 9310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.inst 9749254 # number of WriteReq hits 9410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_hits::total 9749254 # number of WriteReq hits 9510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.inst 21910673767 # number of WriteReq miss cycles 9610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 21910673767 # number of WriteReq miss cycles 9710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046300 # miss rate for WriteReq accesses 9810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.046300 # miss rate for WriteReq accesses 9910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.inst 473303 # number of WriteReq misses 10010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_misses::total 473303 # number of WriteReq misses 10110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.inst 222786 # number of WriteReq MSHR hits 10210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 222786 # number of WriteReq MSHR hits 10310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10668668321 # number of WriteReq MSHR miss cycles 10410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 10668668321 # number of WriteReq MSHR miss cycles 10510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024506 # mshr miss rate for WriteReq accesses 10610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses 10710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250517 # number of WriteReq MSHR misses 10810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 250517 # number of WriteReq MSHR misses 10910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058222680 # number of WriteReq MSHR uncacheable cycles 11010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058222680 # number of WriteReq MSHR uncacheable cycles 11110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 11310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 11410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 11510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 11810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_accesses::cpu.inst 24087007 # number of demand (read+write) accesses 11910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_accesses::total 24087007 # number of demand (read+write) accesses 12010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.inst 30893.424989 # average overall miss latency 12110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 30893.424989 # average overall miss latency 12210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24624.358188 # average overall mshr miss latency 12310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 24624.358188 # average overall mshr miss latency 12410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_hits::cpu.inst 23150720 # number of demand (read+write) hits 12510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_hits::total 23150720 # number of demand (read+write) hits 12610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.inst 28925112203 # number of demand (read+write) miss cycles 12710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_latency::total 28925112203 # number of demand (read+write) miss cycles 12810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.inst 0.038871 # miss rate for demand accesses 12910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.038871 # miss rate for demand accesses 13010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_misses::cpu.inst 936287 # number of demand (read+write) misses 13110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_misses::total 936287 # number of demand (read+write) misses 13210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.inst 305658 # number of demand (read+write) MSHR hits 13310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_hits::total 305658 # number of demand (read+write) MSHR hits 13410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15528834380 # number of demand (read+write) MSHR miss cycles 13510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 15528834380 # number of demand (read+write) MSHR miss cycles 13610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.026181 # mshr miss rate for demand accesses 13710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.026181 # mshr miss rate for demand accesses 13810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.inst 630629 # number of demand (read+write) MSHR misses 13910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_misses::total 630629 # number of demand (read+write) MSHR misses 14010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 14110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 14210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_accesses::cpu.inst 24087007 # number of overall (read+write) accesses 14310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_accesses::total 24087007 # number of overall (read+write) accesses 14410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.inst 30893.424989 # average overall miss latency 14510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 30893.424989 # average overall miss latency 14610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24624.358188 # average overall mshr miss latency 14710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 24624.358188 # average overall mshr miss latency 14810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 14910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 15010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_hits::cpu.inst 23150720 # number of overall hits 15110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_hits::total 23150720 # number of overall hits 15210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.inst 28925112203 # number of overall miss cycles 15310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_latency::total 28925112203 # number of overall miss cycles 15410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.inst 0.038871 # miss rate for overall accesses 15510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.038871 # miss rate for overall accesses 15610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_misses::cpu.inst 936287 # number of overall misses 15710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_misses::total 936287 # number of overall misses 15810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.inst 305658 # number of overall MSHR hits 15910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_hits::total 305658 # number of overall MSHR hits 16010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15528834380 # number of overall MSHR miss cycles 16110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 15528834380 # number of overall MSHR miss cycles 16210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.026181 # mshr miss rate for overall accesses 16310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.026181 # mshr miss rate for overall accesses 16410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.inst 630629 # number of overall MSHR misses 16510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_misses::total 630629 # number of overall MSHR misses 16610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640080180 # number of overall MSHR uncacheable cycles 16710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 208640080180 # number of overall MSHR uncacheable cycles 16810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 16910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id 17010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 17110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.avg_refs 37.024295 # Average number of references to valid blocks. 17210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.data_accesses 98967296 # Number of data accesses 17310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.inst 511.959208 # Average occupied blocks per requestor 17410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy 17510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy 17610260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 17710260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 17810260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.replacements 637936 # number of replacements 17910260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.sampled_refs 638448 # Sample count of references to valid blocks. 18010260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.tag_accesses 98967296 # Number of tag accesses 18110260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.tagsinuse 511.959208 # Cycle average of tags in use 18210260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.total_refs 23638087 # Total number of references to valid blocks. 18310260SAndrew.Bardsley@arm.comsystem.cpu.dcache.tags.warmup_cycle 227414250 # Cycle when the warmup percentage was hit. 18410260SAndrew.Bardsley@arm.comsystem.cpu.dcache.writebacks::writebacks 603000 # number of writebacks 18510260SAndrew.Bardsley@arm.comsystem.cpu.dcache.writebacks::total 603000 # number of writebacks 18610260SAndrew.Bardsley@arm.comsystem.cpu.discardedOps 3607979 # Number of ops (including micro ops) which were discarded before commit 18710260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 18810260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18910260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19010260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19110260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19210260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19310260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19410260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19510260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 19610260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 19710260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 19810260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 19910260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 20010260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 20110260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 20210260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20310260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 20410260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 20510260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20610260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 20710260SAndrew.Bardsley@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 20810260SAndrew.Bardsley@arm.comsystem.cpu.dtb.accesses 26805017 # DTB accesses 20910260SAndrew.Bardsley@arm.comsystem.cpu.dtb.align_faults 1584 # Number of TLB faults due to alignment restrictions 21010260SAndrew.Bardsley@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 21110260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_entries 3457 # Number of entries that have been flushed from TLB 21210260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 21310260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 21410260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 21510260SAndrew.Bardsley@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 21610260SAndrew.Bardsley@arm.comsystem.cpu.dtb.hits 26758984 # DTB hits 21710260SAndrew.Bardsley@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 21810260SAndrew.Bardsley@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 21910260SAndrew.Bardsley@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 22010260SAndrew.Bardsley@arm.comsystem.cpu.dtb.misses 46033 # DTB misses 22110260SAndrew.Bardsley@arm.comsystem.cpu.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions 22210260SAndrew.Bardsley@arm.comsystem.cpu.dtb.prefetch_faults 266 # Number of TLB faults due to prefetch 22310260SAndrew.Bardsley@arm.comsystem.cpu.dtb.read_accesses 15458164 # DTB read accesses 22410260SAndrew.Bardsley@arm.comsystem.cpu.dtb.read_hits 15416095 # DTB read hits 22510260SAndrew.Bardsley@arm.comsystem.cpu.dtb.read_misses 42069 # DTB read misses 22610260SAndrew.Bardsley@arm.comsystem.cpu.dtb.write_accesses 11346853 # DTB write accesses 22710260SAndrew.Bardsley@arm.comsystem.cpu.dtb.write_hits 11342889 # DTB write hits 22810260SAndrew.Bardsley@arm.comsystem.cpu.dtb.write_misses 3964 # DTB write misses 22910260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 23332180 # number of ReadReq accesses(hits+misses) 23010260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_accesses::total 23332180 # number of ReadReq accesses(hits+misses) 23110260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.944355 # average ReadReq miss latency 23210260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13520.944355 # average ReadReq miss latency 23310260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11517.182541 # average ReadReq mshr miss latency 23410260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11517.182541 # average ReadReq mshr miss latency 23510260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 23610260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 23710260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 21786211 # number of ReadReq hits 23810260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_hits::total 21786211 # number of ReadReq hits 23910260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 20902960824 # number of ReadReq miss cycles 24010260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 20902960824 # number of ReadReq miss cycles 24110260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066259 # miss rate for ReadReq accesses 24210260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.066259 # miss rate for ReadReq accesses 24310260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1545969 # number of ReadReq misses 24410260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_misses::total 1545969 # number of ReadReq misses 24510260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17805207176 # number of ReadReq MSHR miss cycles 24610260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 17805207176 # number of ReadReq MSHR miss cycles 24710260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for ReadReq accesses 24810260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.066259 # mshr miss rate for ReadReq accesses 24910260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1545969 # number of ReadReq MSHR misses 25010260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1545969 # number of ReadReq MSHR misses 25110260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172412750 # number of ReadReq MSHR uncacheable cycles 25210260SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172412750 # number of ReadReq MSHR uncacheable cycles 25310260SAndrew.Bardsley@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 25410260SAndrew.Bardsley@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 25510260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 25610260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 25710260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 25810260SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 25910260SAndrew.Bardsley@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 26010260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 23332180 # number of demand (read+write) accesses 26110260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_accesses::total 23332180 # number of demand (read+write) accesses 26210260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.944355 # average overall miss latency 26310260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13520.944355 # average overall miss latency 26410260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11517.182541 # average overall mshr miss latency 26510260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11517.182541 # average overall mshr miss latency 26610260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_hits::cpu.inst 21786211 # number of demand (read+write) hits 26710260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_hits::total 21786211 # number of demand (read+write) hits 26810260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 20902960824 # number of demand (read+write) miss cycles 26910260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_latency::total 20902960824 # number of demand (read+write) miss cycles 27010260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.066259 # miss rate for demand accesses 27110260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_rate::total 0.066259 # miss rate for demand accesses 27210260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1545969 # number of demand (read+write) misses 27310260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_misses::total 1545969 # number of demand (read+write) misses 27410260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 17805207176 # number of demand (read+write) MSHR miss cycles 27510260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 17805207176 # number of demand (read+write) MSHR miss cycles 27610260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for demand accesses 27710260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.066259 # mshr miss rate for demand accesses 27810260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1545969 # number of demand (read+write) MSHR misses 27910260SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_misses::total 1545969 # number of demand (read+write) MSHR misses 28010260SAndrew.Bardsley@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 28110260SAndrew.Bardsley@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 28210260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 23332180 # number of overall (read+write) accesses 28310260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_accesses::total 23332180 # number of overall (read+write) accesses 28410260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.944355 # average overall miss latency 28510260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13520.944355 # average overall miss latency 28610260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11517.182541 # average overall mshr miss latency 28710260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11517.182541 # average overall mshr miss latency 28810260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 28910260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 29010260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_hits::cpu.inst 21786211 # number of overall hits 29110260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_hits::total 21786211 # number of overall hits 29210260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 20902960824 # number of overall miss cycles 29310260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_latency::total 20902960824 # number of overall miss cycles 29410260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.066259 # miss rate for overall accesses 29510260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_rate::total 0.066259 # miss rate for overall accesses 29610260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1545969 # number of overall misses 29710260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_misses::total 1545969 # number of overall misses 29810260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 17805207176 # number of overall MSHR miss cycles 29910260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 17805207176 # number of overall MSHR miss cycles 30010260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for overall accesses 30110260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.066259 # mshr miss rate for overall accesses 30210260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1545969 # number of overall MSHR misses 30310260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_misses::total 1545969 # number of overall MSHR misses 30410260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172412750 # number of overall MSHR uncacheable cycles 30510260SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 172412750 # number of overall MSHR uncacheable cycles 30610260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 30710260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id 30810260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 181 # Occupied blocks per task id 30910260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 31010260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.avg_refs 14.092278 # Average number of references to valid blocks. 31110260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.data_accesses 24878148 # Number of data accesses 31210260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.467492 # Average occupied blocks per requestor 31310260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy 31410260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy 31510260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31610260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 31710260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.replacements 1545456 # number of replacements 31810260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.sampled_refs 1545968 # Sample count of references to valid blocks. 31910260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.tag_accesses 24878148 # Number of tag accesses 32010260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.tagsinuse 511.467492 # Cycle average of tags in use 32110260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.total_refs 21786211 # Total number of references to valid blocks. 32210260SAndrew.Bardsley@arm.comsystem.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. 32310260SAndrew.Bardsley@arm.comsystem.cpu.idleCycles 106196788 # Total number of cycles that the CPU has spent unscheduled due to idling 32410260SAndrew.Bardsley@arm.comsystem.cpu.ipc 0.105024 # IPC: instructions per cycle 32510260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 32610260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 32710260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 32810260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 32910260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 33010260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33110260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33210260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33310260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 33410260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 33510260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33610260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33710260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 33810260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33910260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34010260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34110260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34210260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34310260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 34410260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34510260SAndrew.Bardsley@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34610260SAndrew.Bardsley@arm.comsystem.cpu.itb.accesses 23345804 # DTB accesses 34710260SAndrew.Bardsley@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 34810260SAndrew.Bardsley@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 34910260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_entries 2396 # Number of entries that have been flushed from TLB 35010260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 35110260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 35210260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35310260SAndrew.Bardsley@arm.comsystem.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 35410260SAndrew.Bardsley@arm.comsystem.cpu.itb.hits 23336489 # DTB hits 35510260SAndrew.Bardsley@arm.comsystem.cpu.itb.inst_accesses 23345804 # ITB inst accesses 35610260SAndrew.Bardsley@arm.comsystem.cpu.itb.inst_hits 23336489 # ITB inst hits 35710260SAndrew.Bardsley@arm.comsystem.cpu.itb.inst_misses 9315 # ITB inst misses 35810260SAndrew.Bardsley@arm.comsystem.cpu.itb.misses 9315 # DTB misses 35910260SAndrew.Bardsley@arm.comsystem.cpu.itb.perms_faults 4052 # Number of TLB faults due to permissions restrictions 36010260SAndrew.Bardsley@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 36110260SAndrew.Bardsley@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 36210260SAndrew.Bardsley@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 36310260SAndrew.Bardsley@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 36410260SAndrew.Bardsley@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 36510260SAndrew.Bardsley@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 36610260SAndrew.Bardsley@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 36710260SAndrew.Bardsley@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 36810260SAndrew.Bardsley@arm.comsystem.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed 36910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.inst 247542 # number of ReadExReq accesses(hits+misses) 37010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 247542 # number of ReadExReq accesses(hits+misses) 37110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69059.848663 # average ReadExReq miss latency 37210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 69059.848663 # average ReadExReq miss latency 37310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56515.321009 # average ReadExReq mshr miss latency 37410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56515.321009 # average ReadExReq mshr miss latency 37510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.inst 114197 # number of ReadExReq hits 37610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 114197 # number of ReadExReq hits 37710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9208785520 # number of ReadExReq miss cycles 37810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 9208785520 # number of ReadExReq miss cycles 37910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538676 # miss rate for ReadExReq accesses 38010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.538676 # miss rate for ReadExReq accesses 38110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.inst 133345 # number of ReadExReq misses 38210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 133345 # number of ReadExReq misses 38310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7536035480 # number of ReadExReq MSHR miss cycles 38410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7536035480 # number of ReadExReq MSHR miss cycles 38510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538676 # mshr miss rate for ReadExReq accesses 38610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538676 # mshr miss rate for ReadExReq accesses 38710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133345 # number of ReadExReq MSHR misses 38810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 133345 # number of ReadExReq MSHR misses 38910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52818 # number of ReadReq accesses(hits+misses) 39010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11330 # number of ReadReq accesses(hits+misses) 39110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1934916 # number of ReadReq accesses(hits+misses) 39210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1999064 # number of ReadReq accesses(hits+misses) 39310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85107.142857 # average ReadReq miss latency 39410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 39510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71955.193483 # average ReadReq miss latency 39610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 71966.894361 # average ReadReq miss latency 39710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average ReadReq mshr miss latency 39810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 39910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59447.036018 # average ReadReq mshr miss latency 40010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59458.945900 # average ReadReq mshr miss latency 40110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 40210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 40310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52797 # number of ReadReq hits 40410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11328 # number of ReadReq hits 40510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1910857 # number of ReadReq hits 40610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1974982 # number of ReadReq hits 40710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1787250 # number of ReadReq miss cycles 40810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 40910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1731170000 # number of ReadReq miss cycles 41010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 1733106750 # number of ReadReq miss cycles 41110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000398 # miss rate for ReadReq accesses 41210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000177 # miss rate for ReadReq accesses 41310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012434 # miss rate for ReadReq accesses 41410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.012047 # miss rate for ReadReq accesses 41510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses 41610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 41710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 24059 # number of ReadReq misses 41810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::total 24082 # number of ReadReq misses 41910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits 42010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 42110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1528250 # number of ReadReq MSHR miss cycles 42210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 42310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1426015500 # number of ReadReq MSHR miss cycles 42410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 1427668750 # number of ReadReq MSHR miss cycles 42510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for ReadReq accesses 42610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for ReadReq accesses 42710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses 42810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012011 # mshr miss rate for ReadReq accesses 42910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses 43010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 43110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23988 # number of ReadReq MSHR misses 43210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 24011 # number of ReadReq MSHR misses 43310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167311975000 # number of ReadReq MSHR uncacheable cycles 43410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167311975000 # number of ReadReq MSHR uncacheable cycles 43510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2976 # number of UpgradeReq accesses(hits+misses) 43610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2976 # number of UpgradeReq accesses(hits+misses) 43710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 126.265763 # average UpgradeReq miss latency 43810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 126.265763 # average UpgradeReq miss latency 43910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10004.558983 # average UpgradeReq mshr miss latency 44010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10004.558983 # average UpgradeReq mshr miss latency 44110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.inst 26 # number of UpgradeReq hits 44210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 44310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 372484 # number of UpgradeReq miss cycles 44410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 372484 # number of UpgradeReq miss cycles 44510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991263 # miss rate for UpgradeReq accesses 44610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.991263 # miss rate for UpgradeReq accesses 44710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.inst 2950 # number of UpgradeReq misses 44810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 2950 # number of UpgradeReq misses 44910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29513449 # number of UpgradeReq MSHR miss cycles 45010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29513449 # number of UpgradeReq MSHR miss cycles 45110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991263 # mshr miss rate for UpgradeReq accesses 45210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991263 # mshr miss rate for UpgradeReq accesses 45310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2950 # number of UpgradeReq MSHR misses 45410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 2950 # number of UpgradeReq MSHR misses 45510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 45610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 45710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707831820 # number of WriteReq MSHR uncacheable cycles 45810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707831820 # number of WriteReq MSHR uncacheable cycles 45910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 603000 # number of Writeback accesses(hits+misses) 46010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_accesses::total 603000 # number of Writeback accesses(hits+misses) 46110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 603000 # number of Writeback hits 46210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_hits::total 603000 # number of Writeback hits 46310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 46410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 46510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 46610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 46710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 46810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 46910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 47010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 52818 # number of demand (read+write) accesses 47110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 11330 # number of demand (read+write) accesses 47210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 2182458 # number of demand (read+write) accesses 47310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::total 2246606 # number of demand (read+write) accesses 47410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85107.142857 # average overall miss latency 47510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 47610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69502.398414 # average overall miss latency 47710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 69504.546679 # average overall miss latency 47810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average overall mshr miss latency 47910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 48010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.309115 # average overall mshr miss latency 48110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 56964.489629 # average overall mshr miss latency 48210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 52797 # number of demand (read+write) hits 48310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 11328 # number of demand (read+write) hits 48410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 2025054 # number of demand (read+write) hits 48510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::total 2089179 # number of demand (read+write) hits 48610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1787250 # number of demand (read+write) miss cycles 48710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 48810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 10939955520 # number of demand (read+write) miss cycles 48910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::total 10941892270 # number of demand (read+write) miss cycles 49010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000398 # miss rate for demand accesses 49110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000177 # miss rate for demand accesses 49210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.072122 # miss rate for demand accesses 49310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.070073 # miss rate for demand accesses 49410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses 49510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 49610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 157404 # number of demand (read+write) misses 49710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::total 157427 # number of demand (read+write) misses 49810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits 49910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 50010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1528250 # number of demand (read+write) MSHR miss cycles 50110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 50210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8962050980 # number of demand (read+write) MSHR miss cycles 50310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 8963704230 # number of demand (read+write) MSHR miss cycles 50410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for demand accesses 50510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for demand accesses 50610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072090 # mshr miss rate for demand accesses 50710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.070042 # mshr miss rate for demand accesses 50810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses 50910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 51010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 157333 # number of demand (read+write) MSHR misses 51110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 157356 # number of demand (read+write) MSHR misses 51210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 51310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 51410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 52818 # number of overall (read+write) accesses 51510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 11330 # number of overall (read+write) accesses 51610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 2182458 # number of overall (read+write) accesses 51710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::total 2246606 # number of overall (read+write) accesses 51810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85107.142857 # average overall miss latency 51910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 52010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69502.398414 # average overall miss latency 52110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 69504.546679 # average overall miss latency 52210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average overall mshr miss latency 52310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 52410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.309115 # average overall mshr miss latency 52510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 56964.489629 # average overall mshr miss latency 52610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 52710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 52810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 52797 # number of overall hits 52910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 11328 # number of overall hits 53010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 2025054 # number of overall hits 53110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::total 2089179 # number of overall hits 53210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1787250 # number of overall miss cycles 53310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 53410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 10939955520 # number of overall miss cycles 53510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::total 10941892270 # number of overall miss cycles 53610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000398 # miss rate for overall accesses 53710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000177 # miss rate for overall accesses 53810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.072122 # miss rate for overall accesses 53910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.070073 # miss rate for overall accesses 54010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses 54110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 54210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 157404 # number of overall misses 54310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::total 157427 # number of overall misses 54410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits 54510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits 54610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1528250 # number of overall MSHR miss cycles 54710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 54810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8962050980 # number of overall MSHR miss cycles 54910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 8963704230 # number of overall MSHR miss cycles 55010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for overall accesses 55110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for overall accesses 55210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072090 # mshr miss rate for overall accesses 55310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.070042 # mshr miss rate for overall accesses 55410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses 55510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 55610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 157333 # number of overall MSHR misses 55710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 157356 # number of overall MSHR misses 55810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184019806820 # number of overall MSHR uncacheable cycles 55910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 184019806820 # number of overall MSHR uncacheable cycles 56010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 56110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 56210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 56310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2431 # Occupied blocks per task id 56410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 6707 # Occupied blocks per task id 56510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 56131 # Occupied blocks per task id 56610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.avg_refs 18.629243 # Average number of references to valid blocks. 56710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.data_accesses 23223720 # Number of data accesses 56810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 36351.350875 # Average occupied blocks per requestor 56910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.813342 # Average occupied blocks per requestor 57010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor 57110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 15263.969553 # Average occupied blocks per requestor 57210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.554678 # Average percentage of cache occupancy 57310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000196 # Average percentage of cache occupancy 57410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 57510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.232910 # Average percentage of cache occupancy 57610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.787783 # Average percentage of cache occupancy 57710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 57810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65377 # Occupied blocks per task id 57910260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 58010260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.997574 # Percentage of cache occupancy per task id 58110260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.replacements 65515 # number of replacements 58210260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.sampled_refs 130905 # Sample count of references to valid blocks. 58310260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.tag_accesses 23223720 # Number of tag accesses 58410260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.tagsinuse 51628.134347 # Cycle average of tags in use 58510260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.total_refs 2438661 # Total number of references to valid blocks. 58610260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tags.warmup_cycle 2525287108000 # Cycle when the warmup percentage was hit. 58710260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.writebacks::writebacks 59837 # number of writebacks 58810260SAndrew.Bardsley@arm.comsystem.cpu.l2cache.writebacks::total 59837 # number of writebacks 58910260SAndrew.Bardsley@arm.comsystem.cpu.numCycles 576943440 # number of cpu cycles simulated 59010260SAndrew.Bardsley@arm.comsystem.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching 59110260SAndrew.Bardsley@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 59210260SAndrew.Bardsley@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 59310260SAndrew.Bardsley@arm.comsystem.cpu.quiesceCycles 4560354752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 59410260SAndrew.Bardsley@arm.comsystem.cpu.tickCycles 470746652 # Number of cycles that the CPU actually ticked 59510260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.data_through_bus 184089158 # Total data (bytes) 59610260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094634 # Packet count per connected master and slave (bytes) 59710260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780828 # Packet count per connected master and slave (bytes) 59810260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29817 # Packet count per connected master and slave (bytes) 59910260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 125263 # Packet count per connected master and slave (bytes) 60010260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.pkt_count::total 9030542 # Packet count per connected master and slave (bytes) 60110260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 3400418424 # Layer occupancy (ticks) 60210260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 60310260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 2325892574 # Layer occupancy (ticks) 60410260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 60510260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2551470440 # Layer occupancy (ticks) 60610260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 60710260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 18491990 # Layer occupancy (ticks) 60810260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 60910260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 72446749 # Layer occupancy (ticks) 61010260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 61110260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 232512 # Total snoop data (bytes) 61210260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.throughput 71784989 # Throughput (bytes/s) 61310260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98965568 # Cumulative packet size per connected master and slave (bytes) 61410260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84866998 # Cumulative packet size per connected master and slave (bytes) 61510260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45320 # Cumulative packet size per connected master and slave (bytes) 61610260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 211272 # Cumulative packet size per connected master and slave (bytes) 61710260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 184089158 # Cumulative packet size per connected master and slave (bytes) 61810260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 3214260 # Transaction distribution 61910260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 3214259 # Transaction distribution 62010260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution 62110260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution 62210260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 603000 # Transaction distribution 62310260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2976 # Transaction distribution 62410260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2976 # Transaction distribution 62510260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution 62610260SAndrew.Bardsley@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution 62710260SAndrew.Bardsley@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 62810260SAndrew.Bardsley@arm.comsystem.iobus.data_through_bus 123501026 # Total data (bytes) 62910260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 63010260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) 63110260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) 63210260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) 63310260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 63410260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 63510260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 63610260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 63710260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 63810260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 63910260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 64010260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 64110260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 64210260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 64310260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 64410260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 64510260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 64610260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 64710260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 64810260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 64910260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 65010260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 65110260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 65210260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes) 65310260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 65410260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 65510260SAndrew.Bardsley@arm.comsystem.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes) 65610260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 65710260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 65810260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) 65910260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 66010260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 66110260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 66210260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 66310260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 66410260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 66510260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 66610260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 66710260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 66810260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 66910260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 67010260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 67110260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 67210260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 67310260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 67410260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 67510260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 67610260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 67710260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 67810260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 67910260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 68010260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks) 68110260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 68210260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 68310260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 68410260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 68510260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 68610260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 68710260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 68810260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 68910260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 69010260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 69110260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 69210260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) 69310260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 69410260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 69510260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 69610260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 69710260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 69810260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 69910260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 70010260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 70110260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 70210260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 70310260SAndrew.Bardsley@arm.comsystem.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 70410260SAndrew.Bardsley@arm.comsystem.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks) 70510260SAndrew.Bardsley@arm.comsystem.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 70610260SAndrew.Bardsley@arm.comsystem.iobus.respLayer1.occupancy 38216821000 # Layer occupancy (ticks) 70710260SAndrew.Bardsley@arm.comsystem.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 70810260SAndrew.Bardsley@arm.comsystem.iobus.throughput 48098087 # Throughput (bytes/s) 70910260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 71010260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) 71110260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) 71210260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 71310260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 71410260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 71510260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 71610260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 71710260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 71810260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 71910260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72010260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72110260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72210260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 72310260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72410260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72510260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72610260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72710260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72810260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 72910260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 73010260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 73110260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 73210260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes) 73310260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 73410260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 73510260SAndrew.Bardsley@arm.comsystem.iobus.tot_pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes) 73610260SAndrew.Bardsley@arm.comsystem.iobus.trans_dist::ReadReq 16322171 # Transaction distribution 73710260SAndrew.Bardsley@arm.comsystem.iobus.trans_dist::ReadResp 16322171 # Transaction distribution 73810260SAndrew.Bardsley@arm.comsystem.iobus.trans_dist::WriteReq 8178 # Transaction distribution 73910260SAndrew.Bardsley@arm.comsystem.iobus.trans_dist::WriteResp 8178 # Transaction distribution 74010260SAndrew.Bardsley@arm.comsystem.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 74110260SAndrew.Bardsley@arm.comsystem.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 74210260SAndrew.Bardsley@arm.comsystem.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738144017000 # number of ReadReq MSHR uncacheable cycles 74310260SAndrew.Bardsley@arm.comsystem.iocache.ReadReq_mshr_uncacheable_latency::total 1738144017000 # number of ReadReq MSHR uncacheable cycles 74410260SAndrew.Bardsley@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 74510260SAndrew.Bardsley@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74610260SAndrew.Bardsley@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 74710260SAndrew.Bardsley@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 74810260SAndrew.Bardsley@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 74910260SAndrew.Bardsley@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 75010260SAndrew.Bardsley@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 75110260SAndrew.Bardsley@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 75210260SAndrew.Bardsley@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 75310260SAndrew.Bardsley@arm.comsystem.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 75410260SAndrew.Bardsley@arm.comsystem.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 75510260SAndrew.Bardsley@arm.comsystem.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738144017000 # number of overall MSHR uncacheable cycles 75610260SAndrew.Bardsley@arm.comsystem.iocache.overall_mshr_uncacheable_latency::total 1738144017000 # number of overall MSHR uncacheable cycles 75710260SAndrew.Bardsley@arm.comsystem.iocache.tags.avg_refs nan # Average number of references to valid blocks. 75810260SAndrew.Bardsley@arm.comsystem.iocache.tags.data_accesses 0 # Number of data accesses 75910260SAndrew.Bardsley@arm.comsystem.iocache.tags.replacements 0 # number of replacements 76010260SAndrew.Bardsley@arm.comsystem.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 76110260SAndrew.Bardsley@arm.comsystem.iocache.tags.tag_accesses 0 # Number of tag accesses 76210260SAndrew.Bardsley@arm.comsystem.iocache.tags.tagsinuse 0 # Cycle average of tags in use 76310260SAndrew.Bardsley@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 76410260SAndrew.Bardsley@arm.comsystem.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 76510260SAndrew.Bardsley@arm.comsystem.membus.data_through_bus 140463478 # Total data (bytes) 76610260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes) 76710260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) 76810260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) 76910260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 77010260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893209 # Packet count per connected master and slave (bytes) 77110260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280085 # Packet count per connected master and slave (bytes) 77210260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 77310260SAndrew.Bardsley@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 77410260SAndrew.Bardsley@arm.comsystem.membus.pkt_count::total 34557717 # Packet count per connected master and slave (bytes) 77510260SAndrew.Bardsley@arm.comsystem.membus.reqLayer0.occupancy 1731044000 # Layer occupancy (ticks) 77610260SAndrew.Bardsley@arm.comsystem.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 77710260SAndrew.Bardsley@arm.comsystem.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) 77810260SAndrew.Bardsley@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 77910260SAndrew.Bardsley@arm.comsystem.membus.reqLayer2.occupancy 3530500 # Layer occupancy (ticks) 78010260SAndrew.Bardsley@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 78110260SAndrew.Bardsley@arm.comsystem.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 78210260SAndrew.Bardsley@arm.comsystem.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 78310260SAndrew.Bardsley@arm.comsystem.membus.reqLayer6.occupancy 17560934000 # Layer occupancy (ticks) 78410260SAndrew.Bardsley@arm.comsystem.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 78510260SAndrew.Bardsley@arm.comsystem.membus.respLayer1.occupancy 4805612001 # Layer occupancy (ticks) 78610260SAndrew.Bardsley@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 78710260SAndrew.Bardsley@arm.comsystem.membus.respLayer2.occupancy 37417137000 # Layer occupancy (ticks) 78810260SAndrew.Bardsley@arm.comsystem.membus.respLayer2.utilization 1.5 # Layer utilization (%) 78910260SAndrew.Bardsley@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 79010260SAndrew.Bardsley@arm.comsystem.membus.throughput 54704199 # Throughput (bytes/s) 79110260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes) 79210260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) 79310260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) 79410260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 79510260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16954592 # Cumulative packet size per connected master and slave (bytes) 79610260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19352950 # Cumulative packet size per connected master and slave (bytes) 79710260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 79810260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 79910260SAndrew.Bardsley@arm.comsystem.membus.tot_pkt_size::total 140463478 # Cumulative packet size per connected master and slave (bytes) 80010260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadReq 16349280 # Transaction distribution 80110260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadResp 16349280 # Transaction distribution 80210260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::WriteReq 763365 # Transaction distribution 80310260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::WriteResp 763365 # Transaction distribution 80410260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::Writeback 59837 # Transaction distribution 80510260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::UpgradeReq 4680 # Transaction distribution 80610260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::UpgradeResp 4680 # Transaction distribution 80710260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadExReq 131615 # Transaction distribution 80810260SAndrew.Bardsley@arm.comsystem.membus.trans_dist::ReadExResp 131615 # Transaction distribution 80910260SAndrew.Bardsley@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 81010260SAndrew.Bardsley@arm.comsystem.physmem.avgGap 159378.28 # Average gap between requests 81110260SAndrew.Bardsley@arm.comsystem.physmem.avgMemAccLat 44638.69 # Average memory access latency per DRAM burst 81210260SAndrew.Bardsley@arm.comsystem.physmem.avgQLat 25888.69 # Average queueing delay per DRAM burst 81310260SAndrew.Bardsley@arm.comsystem.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s 81410260SAndrew.Bardsley@arm.comsystem.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s 81510260SAndrew.Bardsley@arm.comsystem.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing 81610260SAndrew.Bardsley@arm.comsystem.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s 81710260SAndrew.Bardsley@arm.comsystem.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s 81810260SAndrew.Bardsley@arm.comsystem.physmem.avgWrQLen 25.93 # Average write queue length when enqueuing 81910260SAndrew.Bardsley@arm.comsystem.physmem.busUtil 3.00 # Data bus utilization in percentage 82010260SAndrew.Bardsley@arm.comsystem.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 82110260SAndrew.Bardsley@arm.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 82210260SAndrew.Bardsley@arm.comsystem.physmem.bw_inst_read::cpu.inst 396534 # Instruction read bandwidth from this memory (bytes/s) 82310260SAndrew.Bardsley@arm.comsystem.physmem.bw_inst_read::total 396534 # Instruction read bandwidth from this memory (bytes/s) 82410260SAndrew.Bardsley@arm.comsystem.physmem.bw_read::realview.clcd 47167096 # Total read bandwidth from this memory (bytes/s) 82510260SAndrew.Bardsley@arm.comsystem.physmem.bw_read::cpu.dtb.walker 523 # Total read bandwidth from this memory (bytes/s) 82610260SAndrew.Bardsley@arm.comsystem.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) 82710260SAndrew.Bardsley@arm.comsystem.physmem.bw_read::cpu.inst 3936408 # Total read bandwidth from this memory (bytes/s) 82810260SAndrew.Bardsley@arm.comsystem.physmem.bw_read::total 51104078 # Total read bandwidth from this memory (bytes/s) 82910260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::writebacks 1491444 # Total bandwidth to/from this memory (bytes/s) 83010260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::realview.clcd 47167096 # Total bandwidth to/from this memory (bytes/s) 83110260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::cpu.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s) 83210260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) 83310260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::cpu.inst 5111032 # Total bandwidth to/from this memory (bytes/s) 83410260SAndrew.Bardsley@arm.comsystem.physmem.bw_total::total 53770146 # Total bandwidth to/from this memory (bytes/s) 83510260SAndrew.Bardsley@arm.comsystem.physmem.bw_write::writebacks 1491444 # Write bandwidth from this memory (bytes/s) 83610260SAndrew.Bardsley@arm.comsystem.physmem.bw_write::cpu.inst 1174624 # Write bandwidth from this memory (bytes/s) 83710260SAndrew.Bardsley@arm.comsystem.physmem.bw_write::total 2666068 # Write bandwidth from this memory (bytes/s) 83810260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::samples 1015061 # Bytes accessed per row activation 83910260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::mean 971.117866 # Bytes accessed per row activation 84010260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::gmean 904.579267 # Bytes accessed per row activation 84110260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::stdev 205.091565 # Bytes accessed per row activation 84210260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::0-127 22463 2.21% 2.21% # Bytes accessed per row activation 84310260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::128-255 22781 2.24% 4.46% # Bytes accessed per row activation 84410260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::256-383 8586 0.85% 5.30% # Bytes accessed per row activation 84510260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::384-511 2483 0.24% 5.55% # Bytes accessed per row activation 84610260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::512-639 2672 0.26% 5.81% # Bytes accessed per row activation 84710260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::640-767 1833 0.18% 5.99% # Bytes accessed per row activation 84810260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::768-895 8618 0.85% 6.84% # Bytes accessed per row activation 84910260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::896-1023 926 0.09% 6.93% # Bytes accessed per row activation 85010260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::1024-1151 944699 93.07% 100.00% # Bytes accessed per row activation 85110260SAndrew.Bardsley@arm.comsystem.physmem.bytesPerActivate::total 1015061 # Bytes accessed per row activation 85210260SAndrew.Bardsley@arm.comsystem.physmem.bytesReadDRAM 978888704 # Total number of bytes read from DRAM 85310260SAndrew.Bardsley@arm.comsystem.physmem.bytesReadSys 131219480 # Total read bytes from the system interface side 85410260SAndrew.Bardsley@arm.comsystem.physmem.bytesReadWrQ 106752 # Total number of bytes read from write queue 85510260SAndrew.Bardsley@arm.comsystem.physmem.bytesWritten 6855168 # Total number of bytes written to DRAM 85610260SAndrew.Bardsley@arm.comsystem.physmem.bytesWrittenSys 6845640 # Total written bytes from the system interface side 85710260SAndrew.Bardsley@arm.comsystem.physmem.bytes_inst_read::cpu.inst 1018176 # Number of instructions bytes read from this memory 85810260SAndrew.Bardsley@arm.comsystem.physmem.bytes_inst_read::total 1018176 # Number of instructions bytes read from this memory 85910260SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 86010260SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory 86110260SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 86210260SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::cpu.inst 10107480 # Number of bytes read from this memory 86310260SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::total 131219480 # Number of bytes read from this memory 86410260SAndrew.Bardsley@arm.comsystem.physmem.bytes_written::writebacks 3829568 # Number of bytes written to this memory 86510260SAndrew.Bardsley@arm.comsystem.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory 86610260SAndrew.Bardsley@arm.comsystem.physmem.bytes_written::total 6845640 # Number of bytes written to this memory 86710260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::IDLE 2210491886500 # Time in different power states 86810260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::REF 85740720000 # Time in different power states 86910260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 87010260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::ACT 271454888500 # Time in different power states 87110260SAndrew.Bardsley@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 87210260SAndrew.Bardsley@arm.comsystem.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one 87310260SAndrew.Bardsley@arm.comsystem.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write 87410260SAndrew.Bardsley@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 87510260SAndrew.Bardsley@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 87610260SAndrew.Bardsley@arm.comsystem.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 87710260SAndrew.Bardsley@arm.comsystem.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory 87810260SAndrew.Bardsley@arm.comsystem.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 87910260SAndrew.Bardsley@arm.comsystem.physmem.num_reads::cpu.inst 157965 # Number of read requests responded to by this memory 88010260SAndrew.Bardsley@arm.comsystem.physmem.num_reads::total 15296804 # Number of read requests responded to by this memory 88110260SAndrew.Bardsley@arm.comsystem.physmem.num_writes::writebacks 59837 # Number of write requests responded to by this memory 88210260SAndrew.Bardsley@arm.comsystem.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory 88310260SAndrew.Bardsley@arm.comsystem.physmem.num_writes::total 813855 # Number of write requests responded to by this memory 88410260SAndrew.Bardsley@arm.comsystem.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined 88510260SAndrew.Bardsley@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 88610260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::0 955934 # Per bank write bursts 88710260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::1 955610 # Per bank write bursts 88810260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::2 955719 # Per bank write bursts 88910260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::3 955960 # Per bank write bursts 89010260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::4 957705 # Per bank write bursts 89110260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::5 955718 # Per bank write bursts 89210260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::6 955569 # Per bank write bursts 89310260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::7 955478 # Per bank write bursts 89410260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::8 956345 # Per bank write bursts 89510260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::9 955973 # Per bank write bursts 89610260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::10 955562 # Per bank write bursts 89710260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::11 955146 # Per bank write bursts 89810260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::12 956303 # Per bank write bursts 89910260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::13 956034 # Per bank write bursts 90010260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::14 956157 # Per bank write bursts 90110260SAndrew.Bardsley@arm.comsystem.physmem.perBankRdBursts::15 955923 # Per bank write bursts 90210260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::0 6634 # Per bank write bursts 90310260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::1 6445 # Per bank write bursts 90410260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::2 6533 # Per bank write bursts 90510260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::3 6602 # Per bank write bursts 90610260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::4 6504 # Per bank write bursts 90710260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::5 6748 # Per bank write bursts 90810260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::6 6784 # Per bank write bursts 90910260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::7 6699 # Per bank write bursts 91010260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::8 7075 # Per bank write bursts 91110260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::9 6807 # Per bank write bursts 91210260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::10 6488 # Per bank write bursts 91310260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::11 6148 # Per bank write bursts 91410260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::12 7101 # Per bank write bursts 91510260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::13 6684 # Per bank write bursts 91610260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::14 7006 # Per bank write bursts 91710260SAndrew.Bardsley@arm.comsystem.physmem.perBankWrBursts::15 6854 # Per bank write bursts 91810260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes 91910260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::mean 2460.607465 # Reads before turning the bus around for writes 92010260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::stdev 89585.482628 # Reads before turning the bus around for writes 92110260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::0-262143 6210 99.90% 99.90% # Reads before turning the bus around for writes 92210260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes 92310260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes 92410260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes 92510260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 92610260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 92710260SAndrew.Bardsley@arm.comsystem.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes 92810260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::0 1112302 # What read queue length does an incoming req see 92910260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::1 958564 # What read queue length does an incoming req see 93010260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::2 963836 # What read queue length does an incoming req see 93110260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::3 1083179 # What read queue length does an incoming req see 93210260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::4 974176 # What read queue length does an incoming req see 93310260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::5 1042396 # What read queue length does an incoming req see 93410260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::6 2682768 # What read queue length does an incoming req see 93510260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::7 2583039 # What read queue length does an incoming req see 93610260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::8 3365419 # What read queue length does an incoming req see 93710260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::9 138919 # What read queue length does an incoming req see 93810260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::10 118710 # What read queue length does an incoming req see 93910260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::11 109585 # What read queue length does an incoming req see 94010260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::12 106194 # What read queue length does an incoming req see 94110260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::13 19284 # What read queue length does an incoming req see 94210260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::14 18426 # What read queue length does an incoming req see 94310260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::15 18172 # What read queue length does an incoming req see 94410260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see 94510260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see 94610260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 94710260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 94810260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 94910260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 95010260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 95110260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 95210260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 95310260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 95410260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 95510260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 95610260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 95710260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 95810260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 95910260SAndrew.Bardsley@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 96010260SAndrew.Bardsley@arm.comsystem.physmem.readBursts 15296804 # Number of DRAM read bursts, including those serviced by the write queue 96110260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 96210260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 96310260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::2 38 # Read request sizes (log2) 96410260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::3 15138816 # Read request sizes (log2) 96510260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 96610260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 96710260SAndrew.Bardsley@arm.comsystem.physmem.readPktSize::6 157950 # Read request sizes (log2) 96810260SAndrew.Bardsley@arm.comsystem.physmem.readReqs 15296804 # Number of read requests accepted 96910260SAndrew.Bardsley@arm.comsystem.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads 97010260SAndrew.Bardsley@arm.comsystem.physmem.readRowHits 14297551 # Number of row buffer hits during reads 97110260SAndrew.Bardsley@arm.comsystem.physmem.servicedByWrQ 1668 # Number of DRAM read bursts serviced by the write queue 97210260SAndrew.Bardsley@arm.comsystem.physmem.totBusLat 76475680000 # Total ticks spent in databus transfers 97310260SAndrew.Bardsley@arm.comsystem.physmem.totGap 2567689117500 # Total gap between requests 97410260SAndrew.Bardsley@arm.comsystem.physmem.totMemAccLat 682754832250 # Total ticks spent from burst creation until serviced by the DRAM 97510260SAndrew.Bardsley@arm.comsystem.physmem.totQLat 395971032250 # Total ticks spent queuing 97610260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads 97710260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::mean 17.231660 # Writes before turning the bus around for reads 97810260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::gmean 17.203648 # Writes before turning the bus around for reads 97910260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::stdev 0.973536 # Writes before turning the bus around for reads 98010260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::16 2382 38.32% 38.32% # Writes before turning the bus around for reads 98110260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::17 22 0.35% 38.67% # Writes before turning the bus around for reads 98210260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::18 3802 61.16% 99.84% # Writes before turning the bus around for reads 98310260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::19 10 0.16% 100.00% # Writes before turning the bus around for reads 98410260SAndrew.Bardsley@arm.comsystem.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads 98510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 98610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 98710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 98810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 98910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 99010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 99110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 99210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 99310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 99410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 99510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 99610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 99710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 99810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 99910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 100010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::15 3810 # What write queue length does an incoming req see 100110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::16 3834 # What write queue length does an incoming req see 100210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::17 6190 # What write queue length does an incoming req see 100310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see 100410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see 100510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see 100610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see 100710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::22 6217 # What write queue length does an incoming req see 100810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::23 6220 # What write queue length does an incoming req see 100910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::24 6217 # What write queue length does an incoming req see 101010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::25 6219 # What write queue length does an incoming req see 101110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::26 6222 # What write queue length does an incoming req see 101210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see 101310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::28 6221 # What write queue length does an incoming req see 101410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see 101510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see 101610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see 101710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see 101810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see 101910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 102010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 102110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 102210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 102310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 102410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 102510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 102610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 102710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 102810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 102910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 103010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 103110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 103210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 103310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 103410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 103510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 103610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 103710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 103810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 103910260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 104010260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 104110260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 104210260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 104310260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 104410260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 104510260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 104610260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 104710260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 104810260SAndrew.Bardsley@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 104910260SAndrew.Bardsley@arm.comsystem.physmem.writeBursts 813855 # Number of DRAM write bursts, including those merged in the write queue 105010260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 105110260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 105210260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::2 754018 # Write request sizes (log2) 105310260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 105410260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 105510260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 105610260SAndrew.Bardsley@arm.comsystem.physmem.writePktSize::6 59837 # Write request sizes (log2) 105710260SAndrew.Bardsley@arm.comsystem.physmem.writeReqs 813855 # Number of write requests accepted 105810260SAndrew.Bardsley@arm.comsystem.physmem.writeRowHitRate 83.67 # Row buffer hit rate for writes 105910260SAndrew.Bardsley@arm.comsystem.physmem.writeRowHits 89636 # Number of row buffer hits during writes 106010260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) 106110260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) 106210260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) 106310260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) 106410260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) 106510260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) 106610260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory 106710260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory 106810260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory 106910260SAndrew.Bardsley@arm.comsystem.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory 107010260SAndrew.Bardsley@arm.comsystem.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory 107110260SAndrew.Bardsley@arm.comsystem.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory 107210260SAndrew.Bardsley@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 107310260SAndrew.Bardsley@arm.com 107410260SAndrew.Bardsley@arm.com---------- End Simulation Statistics ---------- 1075