simout revision 10513:ca4438b6e39a
113481Sgiacomo.travaglini@arm.comgem5 Simulator System. http://gem5.org 213481Sgiacomo.travaglini@arm.comgem5 is copyrighted software; use the --copyright option for details. 313481Sgiacomo.travaglini@arm.com 413481Sgiacomo.travaglini@arm.comgem5 compiled Oct 29 2014 09:18:22 513481Sgiacomo.travaglini@arm.comgem5 started Oct 29 2014 10:01:02 613481Sgiacomo.travaglini@arm.comgem5 executing on u200540-lin 713481Sgiacomo.travaglini@arm.comcommand line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor 813481Sgiacomo.travaglini@arm.comGlobal frequency set at 1000000000000 ticks per second 913481Sgiacomo.travaglini@arm.cominfo: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 1013481Sgiacomo.travaglini@arm.com 0: system.cpu.isa: ISA system set to: 0x4defb00 0x4defb00 1113481Sgiacomo.travaglini@arm.cominfo: Using bootloader at address 0x10 1213481Sgiacomo.travaglini@arm.cominfo: Using kernel entry physical address at 0x80008000 1313481Sgiacomo.travaglini@arm.cominfo: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 1413481Sgiacomo.travaglini@arm.cominfo: Entering event queue @ 0. Starting simulation... 1513481Sgiacomo.travaglini@arm.cominfo: Read CNTFREQ_EL0 frequency 1613481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 1713481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 1813481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 1913481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2013481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2113481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2213481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2313481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2413481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2513481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2613481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2713481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2813481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 2913481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 3013481Sgiacomo.travaglini@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 3113481Sgiacomo.travaglini@arm.comExiting @ tick 2852200332000 because m5_exit instruction encountered 3213481Sgiacomo.travaglini@arm.com